arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include <linux/frame.h>
  37 #include "kvm_cache_regs.h"
  38 #include "x86.h"
  39
  40 #include <asm/cpu.h>
  41 #include <asm/io.h>
  42 #include <asm/desc.h>
  43 #include <asm/vmx.h>
  44 #include <asm/virtext.h>
  45 #include <asm/mce.h>
  46 #include <asm/fpu/internal.h>
  47 #include <asm/perf_event.h>
  48 #include <asm/debugreg.h>
  49 #include <asm/kexec.h>
  50 #include <asm/apic.h>
  51 #include <asm/irq_remapping.h>
  52 #include <asm/mmu_context.h>
  53
  54 #include "trace.h"
  55 #include "pmu.h"
  56
  57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  58 #define __ex_clear(x, reg) \
  59         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  60
  61 MODULE_AUTHOR("Qumranet");
  62 MODULE_LICENSE("GPL");
  63
  64 static const struct x86_cpu_id vmx_cpu_id[] = {
  65         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  66         {}
  67 };
  68 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  69
  70 static bool __read_mostly enable_vpid = 1;
  71 module_param_named(vpid, enable_vpid, bool, 0444);
  72
  73 static bool __read_mostly flexpriority_enabled = 1;
  74 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_ept = 1;
  77 module_param_named(ept, enable_ept, bool, S_IRUGO);
  78
  79 static bool __read_mostly enable_unrestricted_guest = 1;
  80 module_param_named(unrestricted_guest,
  81                         enable_unrestricted_guest, bool, S_IRUGO);
  82
  83 static bool __read_mostly enable_ept_ad_bits = 1;
  84 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  85
  86 static bool __read_mostly emulate_invalid_guest_state = true;
  87 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 111
 112 /* Guest_tsc -> host_tsc conversion requires 64-bit division.  */
 113 static int __read_mostly cpu_preemption_timer_multi;
 114 static bool __read_mostly enable_preemption_timer = 1;
 115 #ifdef CONFIG_X86_64
 116 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
 117 #endif
 118
 119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 121 #define KVM_VM_CR0_ALWAYS_ON                                            \
 122         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 123 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 124         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 125          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 126
 127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 129
 130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 131
 132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 133
 134 /*
 135  * Hyper-V requires all of these, so mark them as supported even though
 136  * they are just treated the same as all-context.
 137  */
 138 #define VMX_VPID_EXTENT_SUPPORTED_MASK          \
 139         (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT |  \
 140         VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |    \
 141         VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT |    \
 142         VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
 143
 144 /*
 145  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 146  * ple_gap:    upper bound on the amount of time between two successive
 147  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 148  *             According to test, this time is usually smaller than 128 cycles.
 149  * ple_window: upper bound on the amount of time a guest is allowed to execute
 150  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 151  *             less than 2^12 cycles
 152  * Time is measured based on a counter that runs at the same rate as the TSC,
 153  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 154  */
 155 #define KVM_VMX_DEFAULT_PLE_GAP           128
 156 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 160                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 161
 162 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 163 module_param(ple_gap, int, S_IRUGO);
 164
 165 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 166 module_param(ple_window, int, S_IRUGO);
 167
 168 /* Default doubles per-vcpu window every exit. */
 169 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 170 module_param(ple_window_grow, int, S_IRUGO);
 171
 172 /* Default resets per-vcpu window every exit to ple_window. */
 173 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 174 module_param(ple_window_shrink, int, S_IRUGO);
 175
 176 /* Default is to compute the maximum so we can never overflow. */
 177 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 178 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 179 module_param(ple_window_max, int, S_IRUGO);
 180
 181 extern const ulong vmx_return;
 182
 183 #define NR_AUTOLOAD_MSRS 8
 184 #define VMCS02_POOL_SIZE 1
 185
 186 struct vmcs {
 187         u32 revision_id;
 188         u32 abort;
 189         char data[0];
 190 };
 191
 192 /*
 193  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 194  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 195  * loaded on this CPU (so we can clear them if the CPU goes down).
 196  */
 197 struct loaded_vmcs {
 198         struct vmcs *vmcs;
 199         struct vmcs *shadow_vmcs;
 200         int cpu;
 201         int launched;
 202         struct list_head loaded_vmcss_on_cpu_link;
 203 };
 204
 205 struct shared_msr_entry {
 206         unsigned index;
 207         u64 data;
 208         u64 mask;
 209 };
 210
 211 /*
 212  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 213  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 214  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 215  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 216  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 217  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 218  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 219  * underlying hardware which will be used to run L2.
 220  * This structure is packed to ensure that its layout is identical across
 221  * machines (necessary for live migration).
 222  * If there are changes in this struct, VMCS12_REVISION must be changed.
 223  */
 224 typedef u64 natural_width;
 225 struct __packed vmcs12 {
 226         /* According to the Intel spec, a VMCS region must start with the
 227          * following two fields. Then follow implementation-specific data.
 228          */
 229         u32 revision_id;
 230         u32 abort;
 231
 232         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 233         u32 padding[7]; /* room for future expansion */
 234
 235         u64 io_bitmap_a;
 236         u64 io_bitmap_b;
 237         u64 msr_bitmap;
 238         u64 vm_exit_msr_store_addr;
 239         u64 vm_exit_msr_load_addr;
 240         u64 vm_entry_msr_load_addr;
 241         u64 tsc_offset;
 242         u64 virtual_apic_page_addr;
 243         u64 apic_access_addr;
 244         u64 posted_intr_desc_addr;
 245         u64 ept_pointer;
 246         u64 eoi_exit_bitmap0;
 247         u64 eoi_exit_bitmap1;
 248         u64 eoi_exit_bitmap2;
 249         u64 eoi_exit_bitmap3;
 250         u64 xss_exit_bitmap;
 251         u64 guest_physical_address;
 252         u64 vmcs_link_pointer;
 253         u64 pml_address;
 254         u64 guest_ia32_debugctl;
 255         u64 guest_ia32_pat;
 256         u64 guest_ia32_efer;
 257         u64 guest_ia32_perf_global_ctrl;
 258         u64 guest_pdptr0;
 259         u64 guest_pdptr1;
 260         u64 guest_pdptr2;
 261         u64 guest_pdptr3;
 262         u64 guest_bndcfgs;
 263         u64 host_ia32_pat;
 264         u64 host_ia32_efer;
 265         u64 host_ia32_perf_global_ctrl;
 266         u64 padding64[8]; /* room for future expansion */
 267         /*
 268          * To allow migration of L1 (complete with its L2 guests) between
 269          * machines of different natural widths (32 or 64 bit), we cannot have
 270          * unsigned long fields with no explict size. We use u64 (aliased
 271          * natural_width) instead. Luckily, x86 is little-endian.
 272          */
 273         natural_width cr0_guest_host_mask;
 274         natural_width cr4_guest_host_mask;
 275         natural_width cr0_read_shadow;
 276         natural_width cr4_read_shadow;
 277         natural_width cr3_target_value0;
 278         natural_width cr3_target_value1;
 279         natural_width cr3_target_value2;
 280         natural_width cr3_target_value3;
 281         natural_width exit_qualification;
 282         natural_width guest_linear_address;
 283         natural_width guest_cr0;
 284         natural_width guest_cr3;
 285         natural_width guest_cr4;
 286         natural_width guest_es_base;
 287         natural_width guest_cs_base;
 288         natural_width guest_ss_base;
 289         natural_width guest_ds_base;
 290         natural_width guest_fs_base;
 291         natural_width guest_gs_base;
 292         natural_width guest_ldtr_base;
 293         natural_width guest_tr_base;
 294         natural_width guest_gdtr_base;
 295         natural_width guest_idtr_base;
 296         natural_width guest_dr7;
 297         natural_width guest_rsp;
 298         natural_width guest_rip;
 299         natural_width guest_rflags;
 300         natural_width guest_pending_dbg_exceptions;
 301         natural_width guest_sysenter_esp;
 302         natural_width guest_sysenter_eip;
 303         natural_width host_cr0;
 304         natural_width host_cr3;
 305         natural_width host_cr4;
 306         natural_width host_fs_base;
 307         natural_width host_gs_base;
 308         natural_width host_tr_base;
 309         natural_width host_gdtr_base;
 310         natural_width host_idtr_base;
 311         natural_width host_ia32_sysenter_esp;
 312         natural_width host_ia32_sysenter_eip;
 313         natural_width host_rsp;
 314         natural_width host_rip;
 315         natural_width paddingl[8]; /* room for future expansion */
 316         u32 pin_based_vm_exec_control;
 317         u32 cpu_based_vm_exec_control;
 318         u32 exception_bitmap;
 319         u32 page_fault_error_code_mask;
 320         u32 page_fault_error_code_match;
 321         u32 cr3_target_count;
 322         u32 vm_exit_controls;
 323         u32 vm_exit_msr_store_count;
 324         u32 vm_exit_msr_load_count;
 325         u32 vm_entry_controls;
 326         u32 vm_entry_msr_load_count;
 327         u32 vm_entry_intr_info_field;
 328         u32 vm_entry_exception_error_code;
 329         u32 vm_entry_instruction_len;
 330         u32 tpr_threshold;
 331         u32 secondary_vm_exec_control;
 332         u32 vm_instruction_error;
 333         u32 vm_exit_reason;
 334         u32 vm_exit_intr_info;
 335         u32 vm_exit_intr_error_code;
 336         u32 idt_vectoring_info_field;
 337         u32 idt_vectoring_error_code;
 338         u32 vm_exit_instruction_len;
 339         u32 vmx_instruction_info;
 340         u32 guest_es_limit;
 341         u32 guest_cs_limit;
 342         u32 guest_ss_limit;
 343         u32 guest_ds_limit;
 344         u32 guest_fs_limit;
 345         u32 guest_gs_limit;
 346         u32 guest_ldtr_limit;
 347         u32 guest_tr_limit;
 348         u32 guest_gdtr_limit;
 349         u32 guest_idtr_limit;
 350         u32 guest_es_ar_bytes;
 351         u32 guest_cs_ar_bytes;
 352         u32 guest_ss_ar_bytes;
 353         u32 guest_ds_ar_bytes;
 354         u32 guest_fs_ar_bytes;
 355         u32 guest_gs_ar_bytes;
 356         u32 guest_ldtr_ar_bytes;
 357         u32 guest_tr_ar_bytes;
 358         u32 guest_interruptibility_info;
 359         u32 guest_activity_state;
 360         u32 guest_sysenter_cs;
 361         u32 host_ia32_sysenter_cs;
 362         u32 vmx_preemption_timer_value;
 363         u32 padding32[7]; /* room for future expansion */
 364         u16 virtual_processor_id;
 365         u16 posted_intr_nv;
 366         u16 guest_es_selector;
 367         u16 guest_cs_selector;
 368         u16 guest_ss_selector;
 369         u16 guest_ds_selector;
 370         u16 guest_fs_selector;
 371         u16 guest_gs_selector;
 372         u16 guest_ldtr_selector;
 373         u16 guest_tr_selector;
 374         u16 guest_intr_status;
 375         u16 guest_pml_index;
 376         u16 host_es_selector;
 377         u16 host_cs_selector;
 378         u16 host_ss_selector;
 379         u16 host_ds_selector;
 380         u16 host_fs_selector;
 381         u16 host_gs_selector;
 382         u16 host_tr_selector;
 383 };
 384
 385 /*
 386  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 387  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 388  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 389  */
 390 #define VMCS12_REVISION 0x11e57ed0
 391
 392 /*
 393  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 394  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 395  * current implementation, 4K are reserved to avoid future complications.
 396  */
 397 #define VMCS12_SIZE 0x1000
 398
 399 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 400 struct vmcs02_list {
 401         struct list_head list;
 402         gpa_t vmptr;
 403         struct loaded_vmcs vmcs02;
 404 };
 405
 406 /*
 407  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 408  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 409  */
 410 struct nested_vmx {
 411         /* Has the level1 guest done vmxon? */
 412         bool vmxon;
 413         gpa_t vmxon_ptr;
 414         bool pml_full;
 415
 416         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 417         gpa_t current_vmptr;
 418         /* The host-usable pointer to the above */
 419         struct page *current_vmcs12_page;
 420         struct vmcs12 *current_vmcs12;
 421         /*
 422          * Cache of the guest's VMCS, existing outside of guest memory.
 423          * Loaded from guest memory during VMPTRLD. Flushed to guest
 424          * memory during VMXOFF, VMCLEAR, VMPTRLD.
 425          */
 426         struct vmcs12 *cached_vmcs12;
 427         /*
 428          * Indicates if the shadow vmcs must be updated with the
 429          * data hold by vmcs12
 430          */
 431         bool sync_shadow_vmcs;
 432
 433         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 434         struct list_head vmcs02_pool;
 435         int vmcs02_num;
 436         bool change_vmcs01_virtual_x2apic_mode;
 437         /* L2 must run next, and mustn't decide to exit to L1. */
 438         bool nested_run_pending;
 439         /*
 440          * Guest pages referred to in vmcs02 with host-physical pointers, so
 441          * we must keep them pinned while L2 runs.
 442          */
 443         struct page *apic_access_page;
 444         struct page *virtual_apic_page;
 445         struct page *pi_desc_page;
 446         struct pi_desc *pi_desc;
 447         bool pi_pending;
 448         u16 posted_intr_nv;
 449
 450         unsigned long *msr_bitmap;
 451
 452         struct hrtimer preemption_timer;
 453         bool preemption_timer_expired;
 454
 455         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 456         u64 vmcs01_debugctl;
 457
 458         u16 vpid02;
 459         u16 last_vpid;
 460
 461         /*
 462          * We only store the "true" versions of the VMX capability MSRs. We
 463          * generate the "non-true" versions by setting the must-be-1 bits
 464          * according to the SDM.
 465          */
 466         u32 nested_vmx_procbased_ctls_low;
 467         u32 nested_vmx_procbased_ctls_high;
 468         u32 nested_vmx_secondary_ctls_low;
 469         u32 nested_vmx_secondary_ctls_high;
 470         u32 nested_vmx_pinbased_ctls_low;
 471         u32 nested_vmx_pinbased_ctls_high;
 472         u32 nested_vmx_exit_ctls_low;
 473         u32 nested_vmx_exit_ctls_high;
 474         u32 nested_vmx_entry_ctls_low;
 475         u32 nested_vmx_entry_ctls_high;
 476         u32 nested_vmx_misc_low;
 477         u32 nested_vmx_misc_high;
 478         u32 nested_vmx_ept_caps;
 479         u32 nested_vmx_vpid_caps;
 480         u64 nested_vmx_basic;
 481         u64 nested_vmx_cr0_fixed0;
 482         u64 nested_vmx_cr0_fixed1;
 483         u64 nested_vmx_cr4_fixed0;
 484         u64 nested_vmx_cr4_fixed1;
 485         u64 nested_vmx_vmcs_enum;
 486 };
 487
 488 #define POSTED_INTR_ON  0
 489 #define POSTED_INTR_SN  1
 490
 491 /* Posted-Interrupt Descriptor */
 492 struct pi_desc {
 493         u32 pir[8];     /* Posted interrupt requested */
 494         union {
 495                 struct {
 496                                 /* bit 256 - Outstanding Notification */
 497                         u16     on      : 1,
 498                                 /* bit 257 - Suppress Notification */
 499                                 sn      : 1,
 500                                 /* bit 271:258 - Reserved */
 501                                 rsvd_1  : 14;
 502                                 /* bit 279:272 - Notification Vector */
 503                         u8      nv;
 504                                 /* bit 287:280 - Reserved */
 505                         u8      rsvd_2;
 506                                 /* bit 319:288 - Notification Destination */
 507                         u32     ndst;
 508                 };
 509                 u64 control;
 510         };
 511         u32 rsvd[6];
 512 } __aligned(64);
 513
 514 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 515 {
 516         return test_and_set_bit(POSTED_INTR_ON,
 517                         (unsigned long *)&pi_desc->control);
 518 }
 519
 520 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 521 {
 522         return test_and_clear_bit(POSTED_INTR_ON,
 523                         (unsigned long *)&pi_desc->control);
 524 }
 525
 526 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 527 {
 528         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 529 }
 530
 531 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 532 {
 533         return clear_bit(POSTED_INTR_SN,
 534                         (unsigned long *)&pi_desc->control);
 535 }
 536
 537 static inline void pi_set_sn(struct pi_desc *pi_desc)
 538 {
 539         return set_bit(POSTED_INTR_SN,
 540                         (unsigned long *)&pi_desc->control);
 541 }
 542
 543 static inline void pi_clear_on(struct pi_desc *pi_desc)
 544 {
 545         clear_bit(POSTED_INTR_ON,
 546                   (unsigned long *)&pi_desc->control);
 547 }
 548
 549 static inline int pi_test_on(struct pi_desc *pi_desc)
 550 {
 551         return test_bit(POSTED_INTR_ON,
 552                         (unsigned long *)&pi_desc->control);
 553 }
 554
 555 static inline int pi_test_sn(struct pi_desc *pi_desc)
 556 {
 557         return test_bit(POSTED_INTR_SN,
 558                         (unsigned long *)&pi_desc->control);
 559 }
 560
 561 struct vcpu_vmx {
 562         struct kvm_vcpu       vcpu;
 563         unsigned long         host_rsp;
 564         u8                    fail;
 565         bool                  nmi_known_unmasked;
 566         u32                   exit_intr_info;
 567         u32                   idt_vectoring_info;
 568         ulong                 rflags;
 569         struct shared_msr_entry *guest_msrs;
 570         int                   nmsrs;
 571         int                   save_nmsrs;
 572         unsigned long         host_idt_base;
 573 #ifdef CONFIG_X86_64
 574         u64                   msr_host_kernel_gs_base;
 575         u64                   msr_guest_kernel_gs_base;
 576 #endif
 577         u32 vm_entry_controls_shadow;
 578         u32 vm_exit_controls_shadow;
 579         /*
 580          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 581          * non-nested (L1) guest, it always points to vmcs01. For a nested
 582          * guest (L2), it points to a different VMCS.
 583          */
 584         struct loaded_vmcs    vmcs01;
 585         struct loaded_vmcs   *loaded_vmcs;
 586         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 587         struct msr_autoload {
 588                 unsigned nr;
 589                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 590                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 591         } msr_autoload;
 592         struct {
 593                 int           loaded;
 594                 u16           fs_sel, gs_sel, ldt_sel;
 595 #ifdef CONFIG_X86_64
 596                 u16           ds_sel, es_sel;
 597 #endif
 598                 int           gs_ldt_reload_needed;
 599                 int           fs_reload_needed;
 600                 u64           msr_host_bndcfgs;
 601                 unsigned long vmcs_host_cr3;    /* May not match real cr3 */
 602                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 603         } host_state;
 604         struct {
 605                 int vm86_active;
 606                 ulong save_rflags;
 607                 struct kvm_segment segs[8];
 608         } rmode;
 609         struct {
 610                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 611                 struct kvm_save_segment {
 612                         u16 selector;
 613                         unsigned long base;
 614                         u32 limit;
 615                         u32 ar;
 616                 } seg[8];
 617         } segment_cache;
 618         int vpid;
 619         bool emulation_required;
 620
 621         u32 exit_reason;
 622
 623         /* Posted interrupt descriptor */
 624         struct pi_desc pi_desc;
 625
 626         /* Support for a guest hypervisor (nested VMX) */
 627         struct nested_vmx nested;
 628
 629         /* Dynamic PLE window. */
 630         int ple_window;
 631         bool ple_window_dirty;
 632
 633         /* Support for PML */
 634 #define PML_ENTITY_NUM          512
 635         struct page *pml_pg;
 636
 637         /* apic deadline value in host tsc */
 638         u64 hv_deadline_tsc;
 639
 640         u64 current_tsc_ratio;
 641
 642         bool guest_pkru_valid;
 643         u32 guest_pkru;
 644         u32 host_pkru;
 645
 646         /*
 647          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 648          * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
 649          * in msr_ia32_feature_control_valid_bits.
 650          */
 651         u64 msr_ia32_feature_control;
 652         u64 msr_ia32_feature_control_valid_bits;
 653 };
 654
 655 enum segment_cache_field {
 656         SEG_FIELD_SEL = 0,
 657         SEG_FIELD_BASE = 1,
 658         SEG_FIELD_LIMIT = 2,
 659         SEG_FIELD_AR = 3,
 660
 661         SEG_FIELD_NR = 4
 662 };
 663
 664 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 665 {
 666         return container_of(vcpu, struct vcpu_vmx, vcpu);
 667 }
 668
 669 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 670 {
 671         return &(to_vmx(vcpu)->pi_desc);
 672 }
 673
 674 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 675 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 676 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 677                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 678
 679
 680 static unsigned long shadow_read_only_fields[] = {
 681         /*
 682          * We do NOT shadow fields that are modified when L0
 683          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 684          * VMXON...) executed by L1.
 685          * For example, VM_INSTRUCTION_ERROR is read
 686          * by L1 if a vmx instruction fails (part of the error path).
 687          * Note the code assumes this logic. If for some reason
 688          * we start shadowing these fields then we need to
 689          * force a shadow sync when L0 emulates vmx instructions
 690          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 691          * by nested_vmx_failValid)
 692          */
 693         VM_EXIT_REASON,
 694         VM_EXIT_INTR_INFO,
 695         VM_EXIT_INSTRUCTION_LEN,
 696         IDT_VECTORING_INFO_FIELD,
 697         IDT_VECTORING_ERROR_CODE,
 698         VM_EXIT_INTR_ERROR_CODE,
 699         EXIT_QUALIFICATION,
 700         GUEST_LINEAR_ADDRESS,
 701         GUEST_PHYSICAL_ADDRESS
 702 };
 703 static int max_shadow_read_only_fields =
 704         ARRAY_SIZE(shadow_read_only_fields);
 705
 706 static unsigned long shadow_read_write_fields[] = {
 707         TPR_THRESHOLD,
 708         GUEST_RIP,
 709         GUEST_RSP,
 710         GUEST_CR0,
 711         GUEST_CR3,
 712         GUEST_CR4,
 713         GUEST_INTERRUPTIBILITY_INFO,
 714         GUEST_RFLAGS,
 715         GUEST_CS_SELECTOR,
 716         GUEST_CS_AR_BYTES,
 717         GUEST_CS_LIMIT,
 718         GUEST_CS_BASE,
 719         GUEST_ES_BASE,
 720         GUEST_BNDCFGS,
 721         CR0_GUEST_HOST_MASK,
 722         CR0_READ_SHADOW,
 723         CR4_READ_SHADOW,
 724         TSC_OFFSET,
 725         EXCEPTION_BITMAP,
 726         CPU_BASED_VM_EXEC_CONTROL,
 727         VM_ENTRY_EXCEPTION_ERROR_CODE,
 728         VM_ENTRY_INTR_INFO_FIELD,
 729         VM_ENTRY_INSTRUCTION_LEN,
 730         VM_ENTRY_EXCEPTION_ERROR_CODE,
 731         HOST_FS_BASE,
 732         HOST_GS_BASE,
 733         HOST_FS_SELECTOR,
 734         HOST_GS_SELECTOR
 735 };
 736 static int max_shadow_read_write_fields =
 737         ARRAY_SIZE(shadow_read_write_fields);
 738
 739 static const unsigned short vmcs_field_to_offset_table[] = {
 740         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 741         FIELD(POSTED_INTR_NV, posted_intr_nv),
 742         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 743         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 744         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 745         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 746         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 747         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 748         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 749         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 750         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 751         FIELD(GUEST_PML_INDEX, guest_pml_index),
 752         FIELD(HOST_ES_SELECTOR, host_es_selector),
 753         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 754         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 755         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 756         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 757         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 758         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 759         FIELD64(IO_BITMAP_A, io_bitmap_a),
 760         FIELD64(IO_BITMAP_B, io_bitmap_b),
 761         FIELD64(MSR_BITMAP, msr_bitmap),
 762         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 763         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 764         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 765         FIELD64(TSC_OFFSET, tsc_offset),
 766         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 767         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 768         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 769         FIELD64(EPT_POINTER, ept_pointer),
 770         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 771         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 772         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 773         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 774         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 775         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 776         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 777         FIELD64(PML_ADDRESS, pml_address),
 778         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 779         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 780         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 781         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 782         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 783         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 784         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 785         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 786         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 787         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 788         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 789         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 790         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 791         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 792         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 793         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 794         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 795         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 796         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 797         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 798         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 799         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 800         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 801         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 802         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 803         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 804         FIELD(TPR_THRESHOLD, tpr_threshold),
 805         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 806         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 807         FIELD(VM_EXIT_REASON, vm_exit_reason),
 808         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 809         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 810         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 811         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 812         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 813         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 814         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 815         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 816         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 817         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 818         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 819         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 820         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 821         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 822         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 823         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 824         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 825         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 826         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 827         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 828         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 829         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 830         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 831         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 832         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 833         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 834         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 835         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 836         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 837         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 838         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 839         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 840         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 841         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 842         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 843         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 844         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 845         FIELD(EXIT_QUALIFICATION, exit_qualification),
 846         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 847         FIELD(GUEST_CR0, guest_cr0),
 848         FIELD(GUEST_CR3, guest_cr3),
 849         FIELD(GUEST_CR4, guest_cr4),
 850         FIELD(GUEST_ES_BASE, guest_es_base),
 851         FIELD(GUEST_CS_BASE, guest_cs_base),
 852         FIELD(GUEST_SS_BASE, guest_ss_base),
 853         FIELD(GUEST_DS_BASE, guest_ds_base),
 854         FIELD(GUEST_FS_BASE, guest_fs_base),
 855         FIELD(GUEST_GS_BASE, guest_gs_base),
 856         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 857         FIELD(GUEST_TR_BASE, guest_tr_base),
 858         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 859         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 860         FIELD(GUEST_DR7, guest_dr7),
 861         FIELD(GUEST_RSP, guest_rsp),
 862         FIELD(GUEST_RIP, guest_rip),
 863         FIELD(GUEST_RFLAGS, guest_rflags),
 864         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 865         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 866         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 867         FIELD(HOST_CR0, host_cr0),
 868         FIELD(HOST_CR3, host_cr3),
 869         FIELD(HOST_CR4, host_cr4),
 870         FIELD(HOST_FS_BASE, host_fs_base),
 871         FIELD(HOST_GS_BASE, host_gs_base),
 872         FIELD(HOST_TR_BASE, host_tr_base),
 873         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 874         FIELD(HOST_IDTR_BASE, host_idtr_base),
 875         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 876         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 877         FIELD(HOST_RSP, host_rsp),
 878         FIELD(HOST_RIP, host_rip),
 879 };
 880
 881 static inline short vmcs_field_to_offset(unsigned long field)
 882 {
 883         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 884
 885         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 886             vmcs_field_to_offset_table[field] == 0)
 887                 return -ENOENT;
 888
 889         return vmcs_field_to_offset_table[field];
 890 }
 891
 892 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 893 {
 894         return to_vmx(vcpu)->nested.cached_vmcs12;
 895 }
 896
 897 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 898 {
 899         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 900         if (is_error_page(page))
 901                 return NULL;
 902
 903         return page;
 904 }
 905
 906 static void nested_release_page(struct page *page)
 907 {
 908         kvm_release_page_dirty(page);
 909 }
 910
 911 static void nested_release_page_clean(struct page *page)
 912 {
 913         kvm_release_page_clean(page);
 914 }
 915
 916 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu);
 917 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 918 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa);
 919 static bool vmx_xsaves_supported(void);
 920 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 921 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 922                             struct kvm_segment *var, int seg);
 923 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 924                             struct kvm_segment *var, int seg);
 925 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 926 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 927 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 928 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 929 static int alloc_identity_pagetable(struct kvm *kvm);
 930
 931 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 932 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 933 /*
 934  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 935  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 936  */
 937 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 938
 939 /*
 940  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 941  * can find which vCPU should be waken up.
 942  */
 943 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 944 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 945
 946 enum {
 947         VMX_IO_BITMAP_A,
 948         VMX_IO_BITMAP_B,
 949         VMX_MSR_BITMAP_LEGACY,
 950         VMX_MSR_BITMAP_LONGMODE,
 951         VMX_MSR_BITMAP_LEGACY_X2APIC_APICV,
 952         VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV,
 953         VMX_MSR_BITMAP_LEGACY_X2APIC,
 954         VMX_MSR_BITMAP_LONGMODE_X2APIC,
 955         VMX_VMREAD_BITMAP,
 956         VMX_VMWRITE_BITMAP,
 957         VMX_BITMAP_NR
 958 };
 959
 960 static unsigned long *vmx_bitmap[VMX_BITMAP_NR];
 961
 962 #define vmx_io_bitmap_a                      (vmx_bitmap[VMX_IO_BITMAP_A])
 963 #define vmx_io_bitmap_b                      (vmx_bitmap[VMX_IO_BITMAP_B])
 964 #define vmx_msr_bitmap_legacy                (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
 965 #define vmx_msr_bitmap_longmode              (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
 966 #define vmx_msr_bitmap_legacy_x2apic_apicv   (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
 967 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
 968 #define vmx_msr_bitmap_legacy_x2apic         (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
 969 #define vmx_msr_bitmap_longmode_x2apic       (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
 970 #define vmx_vmread_bitmap                    (vmx_bitmap[VMX_VMREAD_BITMAP])
 971 #define vmx_vmwrite_bitmap                   (vmx_bitmap[VMX_VMWRITE_BITMAP])
 972
 973 static bool cpu_has_load_ia32_efer;
 974 static bool cpu_has_load_perf_global_ctrl;
 975
 976 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 977 static DEFINE_SPINLOCK(vmx_vpid_lock);
 978
 979 static struct vmcs_config {
 980         int size;
 981         int order;
 982         u32 basic_cap;
 983         u32 revision_id;
 984         u32 pin_based_exec_ctrl;
 985         u32 cpu_based_exec_ctrl;
 986         u32 cpu_based_2nd_exec_ctrl;
 987         u32 vmexit_ctrl;
 988         u32 vmentry_ctrl;
 989 } vmcs_config;
 990
 991 static struct vmx_capability {
 992         u32 ept;
 993         u32 vpid;
 994 } vmx_capability;
 995
 996 #define VMX_SEGMENT_FIELD(seg)                                  \
 997         [VCPU_SREG_##seg] = {                                   \
 998                 .selector = GUEST_##seg##_SELECTOR,             \
 999                 .base = GUEST_##seg##_BASE,                     \
1000                 .limit = GUEST_##seg##_LIMIT,                   \
1001                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
1002         }
1003
1004 static const struct kvm_vmx_segment_field {
1005         unsigned selector;
1006         unsigned base;
1007         unsigned limit;
1008         unsigned ar_bytes;
1009 } kvm_vmx_segment_fields[] = {
1010         VMX_SEGMENT_FIELD(CS),
1011         VMX_SEGMENT_FIELD(DS),
1012         VMX_SEGMENT_FIELD(ES),
1013         VMX_SEGMENT_FIELD(FS),
1014         VMX_SEGMENT_FIELD(GS),
1015         VMX_SEGMENT_FIELD(SS),
1016         VMX_SEGMENT_FIELD(TR),
1017         VMX_SEGMENT_FIELD(LDTR),
1018 };
1019
1020 static u64 host_efer;
1021
1022 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
1023
1024 /*
1025  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1026  * away by decrementing the array size.
1027  */
1028 static const u32 vmx_msr_index[] = {
1029 #ifdef CONFIG_X86_64
1030         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
1031 #endif
1032         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
1033 };
1034
1035 static inline bool is_exception_n(u32 intr_info, u8 vector)
1036 {
1037         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1038                              INTR_INFO_VALID_MASK)) ==
1039                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
1040 }
1041
1042 static inline bool is_debug(u32 intr_info)
1043 {
1044         return is_exception_n(intr_info, DB_VECTOR);
1045 }
1046
1047 static inline bool is_breakpoint(u32 intr_info)
1048 {
1049         return is_exception_n(intr_info, BP_VECTOR);
1050 }
1051
1052 static inline bool is_page_fault(u32 intr_info)
1053 {
1054         return is_exception_n(intr_info, PF_VECTOR);
1055 }
1056
1057 static inline bool is_no_device(u32 intr_info)
1058 {
1059         return is_exception_n(intr_info, NM_VECTOR);
1060 }
1061
1062 static inline bool is_invalid_opcode(u32 intr_info)
1063 {
1064         return is_exception_n(intr_info, UD_VECTOR);
1065 }
1066
1067 static inline bool is_external_interrupt(u32 intr_info)
1068 {
1069         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1070                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1071 }
1072
1073 static inline bool is_machine_check(u32 intr_info)
1074 {
1075         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1076                              INTR_INFO_VALID_MASK)) ==
1077                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1078 }
1079
1080 static inline bool cpu_has_vmx_msr_bitmap(void)
1081 {
1082         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1083 }
1084
1085 static inline bool cpu_has_vmx_tpr_shadow(void)
1086 {
1087         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1088 }
1089
1090 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1091 {
1092         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1093 }
1094
1095 static inline bool cpu_has_secondary_exec_ctrls(void)
1096 {
1097         return vmcs_config.cpu_based_exec_ctrl &
1098                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1099 }
1100
1101 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1102 {
1103         return vmcs_config.cpu_based_2nd_exec_ctrl &
1104                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1105 }
1106
1107 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1108 {
1109         return vmcs_config.cpu_based_2nd_exec_ctrl &
1110                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1111 }
1112
1113 static inline bool cpu_has_vmx_apic_register_virt(void)
1114 {
1115         return vmcs_config.cpu_based_2nd_exec_ctrl &
1116                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1117 }
1118
1119 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1120 {
1121         return vmcs_config.cpu_based_2nd_exec_ctrl &
1122                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1123 }
1124
1125 /*
1126  * Comment's format: document - errata name - stepping - processor name.
1127  * Refer from
1128  * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1129  */
1130 static u32 vmx_preemption_cpu_tfms[] = {
1131 /* 323344.pdf - BA86   - D0 - Xeon 7500 Series */
1132 0x000206E6,
1133 /* 323056.pdf - AAX65  - C2 - Xeon L3406 */
1134 /* 322814.pdf - AAT59  - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1135 /* 322911.pdf - AAU65  - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1136 0x00020652,
1137 /* 322911.pdf - AAU65  - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1138 0x00020655,
1139 /* 322373.pdf - AAO95  - B1 - Xeon 3400 Series */
1140 /* 322166.pdf - AAN92  - B1 - i7-800 and i5-700 Desktop */
1141 /*
1142  * 320767.pdf - AAP86  - B1 -
1143  * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1144  */
1145 0x000106E5,
1146 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1147 0x000106A0,
1148 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1149 0x000106A1,
1150 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1151 0x000106A4,
1152  /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1153  /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1154  /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1155 0x000106A5,
1156 };
1157
1158 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1159 {
1160         u32 eax = cpuid_eax(0x00000001), i;
1161
1162         /* Clear the reserved bits */
1163         eax &= ~(0x3U << 14 | 0xfU << 28);
1164         for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
1165                 if (eax == vmx_preemption_cpu_tfms[i])
1166                         return true;
1167
1168         return false;
1169 }
1170
1171 static inline bool cpu_has_vmx_preemption_timer(void)
1172 {
1173         return vmcs_config.pin_based_exec_ctrl &
1174                 PIN_BASED_VMX_PREEMPTION_TIMER;
1175 }
1176
1177 static inline bool cpu_has_vmx_posted_intr(void)
1178 {
1179         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1180                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1181 }
1182
1183 static inline bool cpu_has_vmx_apicv(void)
1184 {
1185         return cpu_has_vmx_apic_register_virt() &&
1186                 cpu_has_vmx_virtual_intr_delivery() &&
1187                 cpu_has_vmx_posted_intr();
1188 }
1189
1190 static inline bool cpu_has_vmx_flexpriority(void)
1191 {
1192         return cpu_has_vmx_tpr_shadow() &&
1193                 cpu_has_vmx_virtualize_apic_accesses();
1194 }
1195
1196 static inline bool cpu_has_vmx_ept_execute_only(void)
1197 {
1198         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1199 }
1200
1201 static inline bool cpu_has_vmx_ept_2m_page(void)
1202 {
1203         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1204 }
1205
1206 static inline bool cpu_has_vmx_ept_1g_page(void)
1207 {
1208         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1209 }
1210
1211 static inline bool cpu_has_vmx_ept_4levels(void)
1212 {
1213         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1214 }
1215
1216 static inline bool cpu_has_vmx_ept_ad_bits(void)
1217 {
1218         return vmx_capability.ept & VMX_EPT_AD_BIT;
1219 }
1220
1221 static inline bool cpu_has_vmx_invept_context(void)
1222 {
1223         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1224 }
1225
1226 static inline bool cpu_has_vmx_invept_global(void)
1227 {
1228         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1229 }
1230
1231 static inline bool cpu_has_vmx_invvpid_single(void)
1232 {
1233         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1234 }
1235
1236 static inline bool cpu_has_vmx_invvpid_global(void)
1237 {
1238         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1239 }
1240
1241 static inline bool cpu_has_vmx_invvpid(void)
1242 {
1243         return vmx_capability.vpid & VMX_VPID_INVVPID_BIT;
1244 }
1245
1246 static inline bool cpu_has_vmx_ept(void)
1247 {
1248         return vmcs_config.cpu_based_2nd_exec_ctrl &
1249                 SECONDARY_EXEC_ENABLE_EPT;
1250 }
1251
1252 static inline bool cpu_has_vmx_unrestricted_guest(void)
1253 {
1254         return vmcs_config.cpu_based_2nd_exec_ctrl &
1255                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1256 }
1257
1258 static inline bool cpu_has_vmx_ple(void)
1259 {
1260         return vmcs_config.cpu_based_2nd_exec_ctrl &
1261                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1262 }
1263
1264 static inline bool cpu_has_vmx_basic_inout(void)
1265 {
1266         return  (((u64)vmcs_config.basic_cap << 32) & VMX_BASIC_INOUT);
1267 }
1268
1269 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1270 {
1271         return flexpriority_enabled && lapic_in_kernel(vcpu);
1272 }
1273
1274 static inline bool cpu_has_vmx_vpid(void)
1275 {
1276         return vmcs_config.cpu_based_2nd_exec_ctrl &
1277                 SECONDARY_EXEC_ENABLE_VPID;
1278 }
1279
1280 static inline bool cpu_has_vmx_rdtscp(void)
1281 {
1282         return vmcs_config.cpu_based_2nd_exec_ctrl &
1283                 SECONDARY_EXEC_RDTSCP;
1284 }
1285
1286 static inline bool cpu_has_vmx_invpcid(void)
1287 {
1288         return vmcs_config.cpu_based_2nd_exec_ctrl &
1289                 SECONDARY_EXEC_ENABLE_INVPCID;
1290 }
1291
1292 static inline bool cpu_has_vmx_wbinvd_exit(void)
1293 {
1294         return vmcs_config.cpu_based_2nd_exec_ctrl &
1295                 SECONDARY_EXEC_WBINVD_EXITING;
1296 }
1297
1298 static inline bool cpu_has_vmx_shadow_vmcs(void)
1299 {
1300         u64 vmx_msr;
1301         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1302         /* check if the cpu supports writing r/o exit information fields */
1303         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1304                 return false;
1305
1306         return vmcs_config.cpu_based_2nd_exec_ctrl &
1307                 SECONDARY_EXEC_SHADOW_VMCS;
1308 }
1309
1310 static inline bool cpu_has_vmx_pml(void)
1311 {
1312         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1313 }
1314
1315 static inline bool cpu_has_vmx_tsc_scaling(void)
1316 {
1317         return vmcs_config.cpu_based_2nd_exec_ctrl &
1318                 SECONDARY_EXEC_TSC_SCALING;
1319 }
1320
1321 static inline bool report_flexpriority(void)
1322 {
1323         return flexpriority_enabled;
1324 }
1325
1326 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu *vcpu)
1327 {
1328         return vmx_misc_cr3_count(to_vmx(vcpu)->nested.nested_vmx_misc_low);
1329 }
1330
1331 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1332 {
1333         return vmcs12->cpu_based_vm_exec_control & bit;
1334 }
1335
1336 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1337 {
1338         return (vmcs12->cpu_based_vm_exec_control &
1339                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1340                 (vmcs12->secondary_vm_exec_control & bit);
1341 }
1342
1343 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1344 {
1345         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1346 }
1347
1348 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1349 {
1350         return vmcs12->pin_based_vm_exec_control &
1351                 PIN_BASED_VMX_PREEMPTION_TIMER;
1352 }
1353
1354 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1355 {
1356         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1357 }
1358
1359 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1360 {
1361         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1362                 vmx_xsaves_supported();
1363 }
1364
1365 static inline bool nested_cpu_has_pml(struct vmcs12 *vmcs12)
1366 {
1367         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML);
1368 }
1369
1370 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1371 {
1372         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1373 }
1374
1375 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1376 {
1377         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1378 }
1379
1380 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1381 {
1382         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1383 }
1384
1385 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1386 {
1387         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1388 }
1389
1390 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1391 {
1392         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1393 }
1394
1395 static inline bool is_nmi(u32 intr_info)
1396 {
1397         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1398                 == (INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK);
1399 }
1400
1401 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1402                               u32 exit_intr_info,
1403                               unsigned long exit_qualification);
1404 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1405                         struct vmcs12 *vmcs12,
1406                         u32 reason, unsigned long qualification);
1407
1408 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1409 {
1410         int i;
1411
1412         for (i = 0; i < vmx->nmsrs; ++i)
1413                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1414                         return i;
1415         return -1;
1416 }
1417
1418 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1419 {
1420     struct {
1421         u64 vpid : 16;
1422         u64 rsvd : 48;
1423         u64 gva;
1424     } operand = { vpid, 0, gva };
1425
1426     asm volatile (__ex(ASM_VMX_INVVPID)
1427                   /* CF==1 or ZF==1 --> rc = -1 */
1428                   "; ja 1f ; ud2 ; 1:"
1429                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1430 }
1431
1432 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1433 {
1434         struct {
1435                 u64 eptp, gpa;
1436         } operand = {eptp, gpa};
1437
1438         asm volatile (__ex(ASM_VMX_INVEPT)
1439                         /* CF==1 or ZF==1 --> rc = -1 */
1440                         "; ja 1f ; ud2 ; 1:\n"
1441                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1442 }
1443
1444 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1445 {
1446         int i;
1447
1448         i = __find_msr_index(vmx, msr);
1449         if (i >= 0)
1450                 return &vmx->guest_msrs[i];
1451         return NULL;
1452 }
1453
1454 static void vmcs_clear(struct vmcs *vmcs)
1455 {
1456         u64 phys_addr = __pa(vmcs);
1457         u8 error;
1458
1459         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1460                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1461                       : "cc", "memory");
1462         if (error)
1463                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1464                        vmcs, phys_addr);
1465 }
1466
1467 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1468 {
1469         vmcs_clear(loaded_vmcs->vmcs);
1470         if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
1471                 vmcs_clear(loaded_vmcs->shadow_vmcs);
1472         loaded_vmcs->cpu = -1;
1473         loaded_vmcs->launched = 0;
1474 }
1475
1476 static void vmcs_load(struct vmcs *vmcs)
1477 {
1478         u64 phys_addr = __pa(vmcs);
1479         u8 error;
1480
1481         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1482                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1483                         : "cc", "memory");
1484         if (error)
1485                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1486                        vmcs, phys_addr);
1487 }
1488
1489 #ifdef CONFIG_KEXEC_CORE
1490 /*
1491  * This bitmap is used to indicate whether the vmclear
1492  * operation is enabled on all cpus. All disabled by
1493  * default.
1494  */
1495 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1496
1497 static inline void crash_enable_local_vmclear(int cpu)
1498 {
1499         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1500 }
1501
1502 static inline void crash_disable_local_vmclear(int cpu)
1503 {
1504         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1505 }
1506
1507 static inline int crash_local_vmclear_enabled(int cpu)
1508 {
1509         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1510 }
1511
1512 static void crash_vmclear_local_loaded_vmcss(void)
1513 {
1514         int cpu = raw_smp_processor_id();
1515         struct loaded_vmcs *v;
1516
1517         if (!crash_local_vmclear_enabled(cpu))
1518                 return;
1519
1520         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1521                             loaded_vmcss_on_cpu_link)
1522                 vmcs_clear(v->vmcs);
1523 }
1524 #else
1525 static inline void crash_enable_local_vmclear(int cpu) { }
1526 static inline void crash_disable_local_vmclear(int cpu) { }
1527 #endif /* CONFIG_KEXEC_CORE */
1528
1529 static void __loaded_vmcs_clear(void *arg)
1530 {
1531         struct loaded_vmcs *loaded_vmcs = arg;
1532         int cpu = raw_smp_processor_id();
1533
1534         if (loaded_vmcs->cpu != cpu)
1535                 return; /* vcpu migration can race with cpu offline */
1536         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1537                 per_cpu(current_vmcs, cpu) = NULL;
1538         crash_disable_local_vmclear(cpu);
1539         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1540
1541         /*
1542          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1543          * is before setting loaded_vmcs->vcpu to -1 which is done in
1544          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1545          * then adds the vmcs into percpu list before it is deleted.
1546          */
1547         smp_wmb();
1548
1549         loaded_vmcs_init(loaded_vmcs);
1550         crash_enable_local_vmclear(cpu);
1551 }
1552
1553 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1554 {
1555         int cpu = loaded_vmcs->cpu;
1556
1557         if (cpu != -1)
1558                 smp_call_function_single(cpu,
1559                          __loaded_vmcs_clear, loaded_vmcs, 1);
1560 }
1561
1562 static inline void vpid_sync_vcpu_single(int vpid)
1563 {
1564         if (vpid == 0)
1565                 return;
1566
1567         if (cpu_has_vmx_invvpid_single())
1568                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1569 }
1570
1571 static inline void vpid_sync_vcpu_global(void)
1572 {
1573         if (cpu_has_vmx_invvpid_global())
1574                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1575 }
1576
1577 static inline void vpid_sync_context(int vpid)
1578 {
1579         if (cpu_has_vmx_invvpid_single())
1580                 vpid_sync_vcpu_single(vpid);
1581         else
1582                 vpid_sync_vcpu_global();
1583 }
1584
1585 static inline void ept_sync_global(void)
1586 {
1587         if (cpu_has_vmx_invept_global())
1588                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1589 }
1590
1591 static inline void ept_sync_context(u64 eptp)
1592 {
1593         if (enable_ept) {
1594                 if (cpu_has_vmx_invept_context())
1595                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1596                 else
1597                         ept_sync_global();
1598         }
1599 }
1600
1601 static __always_inline void vmcs_check16(unsigned long field)
1602 {
1603         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1604                          "16-bit accessor invalid for 64-bit field");
1605         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1606                          "16-bit accessor invalid for 64-bit high field");
1607         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1608                          "16-bit accessor invalid for 32-bit high field");
1609         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1610                          "16-bit accessor invalid for natural width field");
1611 }
1612
1613 static __always_inline void vmcs_check32(unsigned long field)
1614 {
1615         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1616                          "32-bit accessor invalid for 16-bit field");
1617         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1618                          "32-bit accessor invalid for natural width field");
1619 }
1620
1621 static __always_inline void vmcs_check64(unsigned long field)
1622 {
1623         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1624                          "64-bit accessor invalid for 16-bit field");
1625         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1626                          "64-bit accessor invalid for 64-bit high field");
1627         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1628                          "64-bit accessor invalid for 32-bit field");
1629         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1630                          "64-bit accessor invalid for natural width field");
1631 }
1632
1633 static __always_inline void vmcs_checkl(unsigned long field)
1634 {
1635         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1636                          "Natural width accessor invalid for 16-bit field");
1637         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1638                          "Natural width accessor invalid for 64-bit field");
1639         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1640                          "Natural width accessor invalid for 64-bit high field");
1641         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1642                          "Natural width accessor invalid for 32-bit field");
1643 }
1644
1645 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1646 {
1647         unsigned long value;
1648
1649         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1650                       : "=a"(value) : "d"(field) : "cc");
1651         return value;
1652 }
1653
1654 static __always_inline u16 vmcs_read16(unsigned long field)
1655 {
1656         vmcs_check16(field);
1657         return __vmcs_readl(field);
1658 }
1659
1660 static __always_inline u32 vmcs_read32(unsigned long field)
1661 {
1662         vmcs_check32(field);
1663         return __vmcs_readl(field);
1664 }
1665
1666 static __always_inline u64 vmcs_read64(unsigned long field)
1667 {
1668         vmcs_check64(field);
1669 #ifdef CONFIG_X86_64
1670         return __vmcs_readl(field);
1671 #else
1672         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1673 #endif
1674 }
1675
1676 static __always_inline unsigned long vmcs_readl(unsigned long field)
1677 {
1678         vmcs_checkl(field);
1679         return __vmcs_readl(field);
1680 }
1681
1682 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1683 {
1684         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1685                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1686         dump_stack();
1687 }
1688
1689 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1690 {
1691         u8 error;
1692
1693         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1694                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1695         if (unlikely(error))
1696                 vmwrite_error(field, value);
1697 }
1698
1699 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1700 {
1701         vmcs_check16(field);
1702         __vmcs_writel(field, value);
1703 }
1704
1705 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1706 {
1707         vmcs_check32(field);
1708         __vmcs_writel(field, value);
1709 }
1710
1711 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1712 {
1713         vmcs_check64(field);
1714         __vmcs_writel(field, value);
1715 #ifndef CONFIG_X86_64
1716         asm volatile ("");
1717         __vmcs_writel(field+1, value >> 32);
1718 #endif
1719 }
1720
1721 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1722 {
1723         vmcs_checkl(field);
1724         __vmcs_writel(field, value);
1725 }
1726
1727 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1728 {
1729         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1730                          "vmcs_clear_bits does not support 64-bit fields");
1731         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1732 }
1733
1734 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1735 {
1736         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1737                          "vmcs_set_bits does not support 64-bit fields");
1738         __vmcs_writel(field, __vmcs_readl(field) | mask);
1739 }
1740
1741 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx *vmx)
1742 {
1743         vmx->vm_entry_controls_shadow = vmcs_read32(VM_ENTRY_CONTROLS);
1744 }
1745
1746 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1747 {
1748         vmcs_write32(VM_ENTRY_CONTROLS, val);
1749         vmx->vm_entry_controls_shadow = val;
1750 }
1751
1752 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1753 {
1754         if (vmx->vm_entry_controls_shadow != val)
1755                 vm_entry_controls_init(vmx, val);
1756 }
1757
1758 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1759 {
1760         return vmx->vm_entry_controls_shadow;
1761 }
1762
1763
1764 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1765 {
1766         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1767 }
1768
1769 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1770 {
1771         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1772 }
1773
1774 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx *vmx)
1775 {
1776         vmx->vm_exit_controls_shadow = vmcs_read32(VM_EXIT_CONTROLS);
1777 }
1778
1779 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1780 {
1781         vmcs_write32(VM_EXIT_CONTROLS, val);
1782         vmx->vm_exit_controls_shadow = val;
1783 }
1784
1785 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1786 {
1787         if (vmx->vm_exit_controls_shadow != val)
1788                 vm_exit_controls_init(vmx, val);
1789 }
1790
1791 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1792 {
1793         return vmx->vm_exit_controls_shadow;
1794 }
1795
1796
1797 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1798 {
1799         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1800 }
1801
1802 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1803 {
1804         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1805 }
1806
1807 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1808 {
1809         vmx->segment_cache.bitmask = 0;
1810 }
1811
1812 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1813                                        unsigned field)
1814 {
1815         bool ret;
1816         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1817
1818         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1819                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1820                 vmx->segment_cache.bitmask = 0;
1821         }
1822         ret = vmx->segment_cache.bitmask & mask;
1823         vmx->segment_cache.bitmask |= mask;
1824         return ret;
1825 }
1826
1827 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1828 {
1829         u16 *p = &vmx->segment_cache.seg[seg].selector;
1830
1831         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1832                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1833         return *p;
1834 }
1835
1836 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1837 {
1838         ulong *p = &vmx->segment_cache.seg[seg].base;
1839
1840         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1841                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1842         return *p;
1843 }
1844
1845 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1846 {
1847         u32 *p = &vmx->segment_cache.seg[seg].limit;
1848
1849         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1850                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1851         return *p;
1852 }
1853
1854 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1855 {
1856         u32 *p = &vmx->segment_cache.seg[seg].ar;
1857
1858         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1859                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1860         return *p;
1861 }
1862
1863 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1864 {
1865         u32 eb;
1866
1867         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1868              (1u << DB_VECTOR) | (1u << AC_VECTOR);
1869         if ((vcpu->guest_debug &
1870              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1871             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1872                 eb |= 1u << BP_VECTOR;
1873         if (to_vmx(vcpu)->rmode.vm86_active)
1874                 eb = ~0;
1875         if (enable_ept)
1876                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1877
1878         /* When we are running a nested L2 guest and L1 specified for it a
1879          * certain exception bitmap, we must trap the same exceptions and pass
1880          * them to L1. When running L2, we will only handle the exceptions
1881          * specified above if L1 did not want them.
1882          */
1883         if (is_guest_mode(vcpu))
1884                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1885
1886         vmcs_write32(EXCEPTION_BITMAP, eb);
1887 }
1888
1889 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1890                 unsigned long entry, unsigned long exit)
1891 {
1892         vm_entry_controls_clearbit(vmx, entry);
1893         vm_exit_controls_clearbit(vmx, exit);
1894 }
1895
1896 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1897 {
1898         unsigned i;
1899         struct msr_autoload *m = &vmx->msr_autoload;
1900
1901         switch (msr) {
1902         case MSR_EFER:
1903                 if (cpu_has_load_ia32_efer) {
1904                         clear_atomic_switch_msr_special(vmx,
1905                                         VM_ENTRY_LOAD_IA32_EFER,
1906                                         VM_EXIT_LOAD_IA32_EFER);
1907                         return;
1908                 }
1909                 break;
1910         case MSR_CORE_PERF_GLOBAL_CTRL:
1911                 if (cpu_has_load_perf_global_ctrl) {
1912                         clear_atomic_switch_msr_special(vmx,
1913                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1914                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1915                         return;
1916                 }
1917                 break;
1918         }
1919
1920         for (i = 0; i < m->nr; ++i)
1921                 if (m->guest[i].index == msr)
1922                         break;
1923
1924         if (i == m->nr)
1925                 return;
1926         --m->nr;
1927         m->guest[i] = m->guest[m->nr];
1928         m->host[i] = m->host[m->nr];
1929         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1930         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1931 }
1932
1933 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1934                 unsigned long entry, unsigned long exit,
1935                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1936                 u64 guest_val, u64 host_val)
1937 {
1938         vmcs_write64(guest_val_vmcs, guest_val);
1939         vmcs_write64(host_val_vmcs, host_val);
1940         vm_entry_controls_setbit(vmx, entry);
1941         vm_exit_controls_setbit(vmx, exit);
1942 }
1943
1944 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1945                                   u64 guest_val, u64 host_val)
1946 {
1947         unsigned i;
1948         struct msr_autoload *m = &vmx->msr_autoload;
1949
1950         switch (msr) {
1951         case MSR_EFER:
1952                 if (cpu_has_load_ia32_efer) {
1953                         add_atomic_switch_msr_special(vmx,
1954                                         VM_ENTRY_LOAD_IA32_EFER,
1955                                         VM_EXIT_LOAD_IA32_EFER,
1956                                         GUEST_IA32_EFER,
1957                                         HOST_IA32_EFER,
1958                                         guest_val, host_val);
1959                         return;
1960                 }
1961                 break;
1962         case MSR_CORE_PERF_GLOBAL_CTRL:
1963                 if (cpu_has_load_perf_global_ctrl) {
1964                         add_atomic_switch_msr_special(vmx,
1965                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1966                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1967                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1968                                         HOST_IA32_PERF_GLOBAL_CTRL,
1969                                         guest_val, host_val);
1970                         return;
1971                 }
1972                 break;
1973         case MSR_IA32_PEBS_ENABLE:
1974                 /* PEBS needs a quiescent period after being disabled (to write
1975                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1976                  * provide that period, so a CPU could write host's record into
1977                  * guest's memory.
1978                  */
1979                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1980         }
1981
1982         for (i = 0; i < m->nr; ++i)
1983                 if (m->guest[i].index == msr)
1984                         break;
1985
1986         if (i == NR_AUTOLOAD_MSRS) {
1987                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1988                                 "Can't add msr %x\n", msr);
1989                 return;
1990         } else if (i == m->nr) {
1991                 ++m->nr;
1992                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1993                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1994         }
1995
1996         m->guest[i].index = msr;
1997         m->guest[i].value = guest_val;
1998         m->host[i].index = msr;
1999         m->host[i].value = host_val;
2000 }
2001
2002 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2003 {
2004         u64 guest_efer = vmx->vcpu.arch.efer;
2005         u64 ignore_bits = 0;
2006
2007         if (!enable_ept) {
2008                 /*
2009                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
2010                  * host CPUID is more efficient than testing guest CPUID
2011                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
2012                  */
2013                 if (boot_cpu_has(X86_FEATURE_SMEP))
2014                         guest_efer |= EFER_NX;
2015                 else if (!(guest_efer & EFER_NX))
2016                         ignore_bits |= EFER_NX;
2017         }
2018
2019         /*
2020          * LMA and LME handled by hardware; SCE meaningless outside long mode.
2021          */
2022         ignore_bits |= EFER_SCE;
2023 #ifdef CONFIG_X86_64
2024         ignore_bits |= EFER_LMA | EFER_LME;
2025         /* SCE is meaningful only in long mode on Intel */
2026         if (guest_efer & EFER_LMA)
2027                 ignore_bits &= ~(u64)EFER_SCE;
2028 #endif
2029
2030         clear_atomic_switch_msr(vmx, MSR_EFER);
2031
2032         /*
2033          * On EPT, we can't emulate NX, so we must switch EFER atomically.
2034          * On CPUs that support "load IA32_EFER", always switch EFER
2035          * atomically, since it's faster than switching it manually.
2036          */
2037         if (cpu_has_load_ia32_efer ||
2038             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
2039                 if (!(guest_efer & EFER_LMA))
2040                         guest_efer &= ~EFER_LME;
2041                 if (guest_efer != host_efer)
2042                         add_atomic_switch_msr(vmx, MSR_EFER,
2043                                               guest_efer, host_efer);
2044                 return false;
2045         } else {
2046                 guest_efer &= ~ignore_bits;
2047                 guest_efer |= host_efer & ignore_bits;
2048
2049                 vmx->guest_msrs[efer_offset].data = guest_efer;
2050                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
2051
2052                 return true;
2053         }
2054 }
2055
2056 #ifdef CONFIG_X86_32
2057 /*
2058  * On 32-bit kernels, VM exits still load the FS and GS bases from the
2059  * VMCS rather than the segment table.  KVM uses this helper to figure
2060  * out the current bases to poke them into the VMCS before entry.
2061  */
2062 static unsigned long segment_base(u16 selector)
2063 {
2064         struct desc_struct *table;
2065         unsigned long v;
2066
2067         if (!(selector & ~SEGMENT_RPL_MASK))
2068                 return 0;
2069
2070         table = get_current_gdt_ro();
2071
2072         if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2073                 u16 ldt_selector = kvm_read_ldt();
2074
2075                 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2076                         return 0;
2077
2078                 table = (struct desc_struct *)segment_base(ldt_selector);
2079         }
2080         v = get_desc_base(&table[selector >> 3]);
2081         return v;
2082 }
2083 #endif
2084
2085 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
2086 {
2087         struct vcpu_vmx *vmx = to_vmx(vcpu);
2088         int i;
2089
2090         if (vmx->host_state.loaded)
2091                 return;
2092
2093         vmx->host_state.loaded = 1;
2094         /*
2095          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
2096          * allow segment selectors with cpl > 0 or ti == 1.
2097          */
2098         vmx->host_state.ldt_sel = kvm_read_ldt();
2099         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
2100         savesegment(fs, vmx->host_state.fs_sel);
2101         if (!(vmx->host_state.fs_sel & 7)) {
2102                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
2103                 vmx->host_state.fs_reload_needed = 0;
2104         } else {
2105                 vmcs_write16(HOST_FS_SELECTOR, 0);
2106                 vmx->host_state.fs_reload_needed = 1;
2107         }
2108         savesegment(gs, vmx->host_state.gs_sel);
2109         if (!(vmx->host_state.gs_sel & 7))
2110                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
2111         else {
2112                 vmcs_write16(HOST_GS_SELECTOR, 0);
2113                 vmx->host_state.gs_ldt_reload_needed = 1;
2114         }
2115
2116 #ifdef CONFIG_X86_64
2117         savesegment(ds, vmx->host_state.ds_sel);
2118         savesegment(es, vmx->host_state.es_sel);
2119 #endif
2120
2121 #ifdef CONFIG_X86_64
2122         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2123         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2124 #else
2125         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2126         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2127 #endif
2128
2129 #ifdef CONFIG_X86_64
2130         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2131         if (is_long_mode(&vmx->vcpu))
2132                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2133 #endif
2134         if (boot_cpu_has(X86_FEATURE_MPX))
2135                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2136         for (i = 0; i < vmx->save_nmsrs; ++i)
2137                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2138                                    vmx->guest_msrs[i].data,
2139                                    vmx->guest_msrs[i].mask);
2140 }
2141
2142 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2143 {
2144         if (!vmx->host_state.loaded)
2145                 return;
2146
2147         ++vmx->vcpu.stat.host_state_reload;
2148         vmx->host_state.loaded = 0;
2149 #ifdef CONFIG_X86_64
2150         if (is_long_mode(&vmx->vcpu))
2151                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2152 #endif
2153         if (vmx->host_state.gs_ldt_reload_needed) {
2154                 kvm_load_ldt(vmx->host_state.ldt_sel);
2155 #ifdef CONFIG_X86_64
2156                 load_gs_index(vmx->host_state.gs_sel);
2157 #else
2158                 loadsegment(gs, vmx->host_state.gs_sel);
2159 #endif
2160         }
2161         if (vmx->host_state.fs_reload_needed)
2162                 loadsegment(fs, vmx->host_state.fs_sel);
2163 #ifdef CONFIG_X86_64
2164         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2165                 loadsegment(ds, vmx->host_state.ds_sel);
2166                 loadsegment(es, vmx->host_state.es_sel);
2167         }
2168 #endif
2169         invalidate_tss_limit();
2170 #ifdef CONFIG_X86_64
2171         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2172 #endif
2173         if (vmx->host_state.msr_host_bndcfgs)
2174                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2175         load_fixmap_gdt(raw_smp_processor_id());
2176 }
2177
2178 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2179 {
2180         preempt_disable();
2181         __vmx_load_host_state(vmx);
2182         preempt_enable();
2183 }
2184
2185 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2186 {
2187         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2188         struct pi_desc old, new;
2189         unsigned int dest;
2190
2191         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2192                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2193                 !kvm_vcpu_apicv_active(vcpu))
2194                 return;
2195
2196         do {
2197                 old.control = new.control = pi_desc->control;
2198
2199                 /*
2200                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2201                  * are two possible cases:
2202                  * 1. After running 'pre_block', context switch
2203                  *    happened. For this case, 'sn' was set in
2204                  *    vmx_vcpu_put(), so we need to clear it here.
2205                  * 2. After running 'pre_block', we were blocked,
2206                  *    and woken up by some other guy. For this case,
2207                  *    we don't need to do anything, 'pi_post_block'
2208                  *    will do everything for us. However, we cannot
2209                  *    check whether it is case #1 or case #2 here
2210                  *    (maybe, not needed), so we also clear sn here,
2211                  *    I think it is not a big deal.
2212                  */
2213                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2214                         if (vcpu->cpu != cpu) {
2215                                 dest = cpu_physical_id(cpu);
2216
2217                                 if (x2apic_enabled())
2218                                         new.ndst = dest;
2219                                 else
2220                                         new.ndst = (dest << 8) & 0xFF00;
2221                         }
2222
2223                         /* set 'NV' to 'notification vector' */
2224                         new.nv = POSTED_INTR_VECTOR;
2225                 }
2226
2227                 /* Allow posting non-urgent interrupts */
2228                 new.sn = 0;
2229         } while (cmpxchg(&pi_desc->control, old.control,
2230                         new.control) != old.control);
2231 }
2232
2233 static void decache_tsc_multiplier(struct vcpu_vmx *vmx)
2234 {
2235         vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
2236         vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2237 }
2238
2239 /*
2240  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2241  * vcpu mutex is already taken.
2242  */
2243 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2244 {
2245         struct vcpu_vmx *vmx = to_vmx(vcpu);
2246         bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
2247
2248         if (!already_loaded) {
2249                 loaded_vmcs_clear(vmx->loaded_vmcs);
2250                 local_irq_disable();
2251                 crash_disable_local_vmclear(cpu);
2252
2253                 /*
2254                  * Read loaded_vmcs->cpu should be before fetching
2255                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2256                  * See the comments in __loaded_vmcs_clear().
2257                  */
2258                 smp_rmb();
2259
2260                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2261                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2262                 crash_enable_local_vmclear(cpu);
2263                 local_irq_enable();
2264         }
2265
2266         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2267                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2268                 vmcs_load(vmx->loaded_vmcs->vmcs);
2269         }
2270
2271         if (!already_loaded) {
2272                 void *gdt = get_current_gdt_ro();
2273                 unsigned long sysenter_esp;
2274
2275                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2276
2277                 /*
2278                  * Linux uses per-cpu TSS and GDT, so set these when switching
2279                  * processors.  See 22.2.4.
2280                  */
2281                 vmcs_writel(HOST_TR_BASE,
2282                             (unsigned long)this_cpu_ptr(&cpu_tss));
2283                 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt);   /* 22.2.4 */
2284
2285                 /*
2286                  * VM exits change the host TR limit to 0x67 after a VM
2287                  * exit.  This is okay, since 0x67 covers everything except
2288                  * the IO bitmap and have have code to handle the IO bitmap
2289                  * being lost after a VM exit.
2290                  */
2291                 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
2292
2293                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2294                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2295
2296                 vmx->loaded_vmcs->cpu = cpu;
2297         }
2298
2299         /* Setup TSC multiplier */
2300         if (kvm_has_tsc_control &&
2301             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
2302                 decache_tsc_multiplier(vmx);
2303
2304         vmx_vcpu_pi_load(vcpu, cpu);
2305         vmx->host_pkru = read_pkru();
2306 }
2307
2308 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2309 {
2310         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2311
2312         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2313                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
2314                 !kvm_vcpu_apicv_active(vcpu))
2315                 return;
2316
2317         /* Set SN when the vCPU is preempted */
2318         if (vcpu->preempted)
2319                 pi_set_sn(pi_desc);
2320 }
2321
2322 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2323 {
2324         vmx_vcpu_pi_put(vcpu);
2325
2326         __vmx_load_host_state(to_vmx(vcpu));
2327 }
2328
2329 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2330
2331 /*
2332  * Return the cr0 value that a nested guest would read. This is a combination
2333  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2334  * its hypervisor (cr0_read_shadow).
2335  */
2336 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2337 {
2338         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2339                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2340 }
2341 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2342 {
2343         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2344                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2345 }
2346
2347 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2348 {
2349         unsigned long rflags, save_rflags;
2350
2351         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2352                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2353                 rflags = vmcs_readl(GUEST_RFLAGS);
2354                 if (to_vmx(vcpu)->rmode.vm86_active) {
2355                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2356                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2357                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2358                 }
2359                 to_vmx(vcpu)->rflags = rflags;
2360         }
2361         return to_vmx(vcpu)->rflags;
2362 }
2363
2364 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2365 {
2366         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2367         to_vmx(vcpu)->rflags = rflags;
2368         if (to_vmx(vcpu)->rmode.vm86_active) {
2369                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2370                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2371         }
2372         vmcs_writel(GUEST_RFLAGS, rflags);
2373 }
2374
2375 static u32 vmx_get_pkru(struct kvm_vcpu *vcpu)
2376 {
2377         return to_vmx(vcpu)->guest_pkru;
2378 }
2379
2380 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2381 {
2382         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2383         int ret = 0;
2384
2385         if (interruptibility & GUEST_INTR_STATE_STI)
2386                 ret |= KVM_X86_SHADOW_INT_STI;
2387         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2388                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2389
2390         return ret;
2391 }
2392
2393 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2394 {
2395         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2396         u32 interruptibility = interruptibility_old;
2397
2398         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2399
2400         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2401                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2402         else if (mask & KVM_X86_SHADOW_INT_STI)
2403                 interruptibility |= GUEST_INTR_STATE_STI;
2404
2405         if ((interruptibility != interruptibility_old))
2406                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2407 }
2408
2409 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2410 {
2411         unsigned long rip;
2412
2413         rip = kvm_rip_read(vcpu);
2414         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2415         kvm_rip_write(vcpu, rip);
2416
2417         /* skipping an emulated instruction also counts */
2418         vmx_set_interrupt_shadow(vcpu, 0);
2419 }
2420
2421 /*
2422  * KVM wants to inject page-faults which it got to the guest. This function
2423  * checks whether in a nested guest, we need to inject them to L1 or L2.
2424  */
2425 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2426 {
2427         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2428
2429         if (!(vmcs12->exception_bitmap & (1u << nr)))
2430                 return 0;
2431
2432         nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
2433                           vmcs_read32(VM_EXIT_INTR_INFO),
2434                           vmcs_readl(EXIT_QUALIFICATION));
2435         return 1;
2436 }
2437
2438 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2439                                 bool has_error_code, u32 error_code,
2440                                 bool reinject)
2441 {
2442         struct vcpu_vmx *vmx = to_vmx(vcpu);
2443         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2444
2445         if (!reinject && is_guest_mode(vcpu) &&
2446             nested_vmx_check_exception(vcpu, nr))
2447                 return;
2448
2449         if (has_error_code) {
2450                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2451                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2452         }
2453
2454         if (vmx->rmode.vm86_active) {
2455                 int inc_eip = 0;
2456                 if (kvm_exception_is_soft(nr))
2457                         inc_eip = vcpu->arch.event_exit_inst_len;
2458                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2459                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2460                 return;
2461         }
2462
2463         if (kvm_exception_is_soft(nr)) {
2464                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2465                              vmx->vcpu.arch.event_exit_inst_len);
2466                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2467         } else
2468                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2469
2470         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2471 }
2472
2473 static bool vmx_rdtscp_supported(void)
2474 {
2475         return cpu_has_vmx_rdtscp();
2476 }
2477
2478 static bool vmx_invpcid_supported(void)
2479 {
2480         return cpu_has_vmx_invpcid() && enable_ept;
2481 }
2482
2483 /*
2484  * Swap MSR entry in host/guest MSR entry array.
2485  */
2486 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2487 {
2488         struct shared_msr_entry tmp;
2489
2490         tmp = vmx->guest_msrs[to];
2491         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2492         vmx->guest_msrs[from] = tmp;
2493 }
2494
2495 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2496 {
2497         unsigned long *msr_bitmap;
2498
2499         if (is_guest_mode(vcpu))
2500                 msr_bitmap = to_vmx(vcpu)->nested.msr_bitmap;
2501         else if (cpu_has_secondary_exec_ctrls() &&
2502                  (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
2503                   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
2504                 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) {
2505                         if (is_long_mode(vcpu))
2506                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic_apicv;
2507                         else
2508                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic_apicv;
2509                 } else {
2510                         if (is_long_mode(vcpu))
2511                                 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2512                         else
2513                                 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2514                 }
2515         } else {
2516                 if (is_long_mode(vcpu))
2517                         msr_bitmap = vmx_msr_bitmap_longmode;
2518                 else
2519                         msr_bitmap = vmx_msr_bitmap_legacy;
2520         }
2521
2522         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2523 }
2524
2525 /*
2526  * Set up the vmcs to automatically save and restore system
2527  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2528  * mode, as fiddling with msrs is very expensive.
2529  */
2530 static void setup_msrs(struct vcpu_vmx *vmx)
2531 {
2532         int save_nmsrs, index;
2533
2534         save_nmsrs = 0;
2535 #ifdef CONFIG_X86_64
2536         if (is_long_mode(&vmx->vcpu)) {
2537                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2538                 if (index >= 0)
2539                         move_msr_up(vmx, index, save_nmsrs++);
2540                 index = __find_msr_index(vmx, MSR_LSTAR);
2541                 if (index >= 0)
2542                         move_msr_up(vmx, index, save_nmsrs++);
2543                 index = __find_msr_index(vmx, MSR_CSTAR);
2544                 if (index >= 0)
2545                         move_msr_up(vmx, index, save_nmsrs++);
2546                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2547                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2548                         move_msr_up(vmx, index, save_nmsrs++);
2549                 /*
2550                  * MSR_STAR is only needed on long mode guests, and only
2551                  * if efer.sce is enabled.
2552                  */
2553                 index = __find_msr_index(vmx, MSR_STAR);
2554                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2555                         move_msr_up(vmx, index, save_nmsrs++);
2556         }
2557 #endif
2558         index = __find_msr_index(vmx, MSR_EFER);
2559         if (index >= 0 && update_transition_efer(vmx, index))
2560                 move_msr_up(vmx, index, save_nmsrs++);
2561
2562         vmx->save_nmsrs = save_nmsrs;
2563
2564         if (cpu_has_vmx_msr_bitmap())
2565                 vmx_set_msr_bitmap(&vmx->vcpu);
2566 }
2567
2568 /*
2569  * reads and returns guest's timestamp counter "register"
2570  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2571  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2572  */
2573 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2574 {
2575         u64 host_tsc, tsc_offset;
2576
2577         host_tsc = rdtsc();
2578         tsc_offset = vmcs_read64(TSC_OFFSET);
2579         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2580 }
2581
2582 /*
2583  * writes 'offset' into guest's timestamp counter offset register
2584  */
2585 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2586 {
2587         if (is_guest_mode(vcpu)) {
2588                 /*
2589                  * We're here if L1 chose not to trap WRMSR to TSC. According
2590                  * to the spec, this should set L1's TSC; The offset that L1
2591                  * set for L2 remains unchanged, and still needs to be added
2592                  * to the newly set TSC to get L2's TSC.
2593                  */
2594                 struct vmcs12 *vmcs12;
2595                 /* recalculate vmcs02.TSC_OFFSET: */
2596                 vmcs12 = get_vmcs12(vcpu);
2597                 vmcs_write64(TSC_OFFSET, offset +
2598                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2599                          vmcs12->tsc_offset : 0));
2600         } else {
2601                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2602                                            vmcs_read64(TSC_OFFSET), offset);
2603                 vmcs_write64(TSC_OFFSET, offset);
2604         }
2605 }
2606
2607 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2608 {
2609         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2610         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2611 }
2612
2613 /*
2614  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2615  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2616  * all guests if the "nested" module option is off, and can also be disabled
2617  * for a single guest by disabling its VMX cpuid bit.
2618  */
2619 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2620 {
2621         return nested && guest_cpuid_has_vmx(vcpu);
2622 }
2623
2624 /*
2625  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2626  * returned for the various VMX controls MSRs when nested VMX is enabled.
2627  * The same values should also be used to verify that vmcs12 control fields are
2628  * valid during nested entry from L1 to L2.
2629  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2630  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2631  * bit in the high half is on if the corresponding bit in the control field
2632  * may be on. See also vmx_control_verify().
2633  */
2634 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2635 {
2636         /*
2637          * Note that as a general rule, the high half of the MSRs (bits in
2638          * the control fields which may be 1) should be initialized by the
2639          * intersection of the underlying hardware's MSR (i.e., features which
2640          * can be supported) and the list of features we want to expose -
2641          * because they are known to be properly supported in our code.
2642          * Also, usually, the low half of the MSRs (bits which must be 1) can
2643          * be set to 0, meaning that L1 may turn off any of these bits. The
2644          * reason is that if one of these bits is necessary, it will appear
2645          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2646          * fields of vmcs01 and vmcs02, will turn these bits off - and
2647          * nested_vmx_exit_handled() will not pass related exits to L1.
2648          * These rules have exceptions below.
2649          */
2650
2651         /* pin-based controls */
2652         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2653                 vmx->nested.nested_vmx_pinbased_ctls_low,
2654                 vmx->nested.nested_vmx_pinbased_ctls_high);
2655         vmx->nested.nested_vmx_pinbased_ctls_low |=
2656                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2657         vmx->nested.nested_vmx_pinbased_ctls_high &=
2658                 PIN_BASED_EXT_INTR_MASK |
2659                 PIN_BASED_NMI_EXITING |
2660                 PIN_BASED_VIRTUAL_NMIS;
2661         vmx->nested.nested_vmx_pinbased_ctls_high |=
2662                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2663                 PIN_BASED_VMX_PREEMPTION_TIMER;
2664         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2665                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2666                         PIN_BASED_POSTED_INTR;
2667
2668         /* exit controls */
2669         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2670                 vmx->nested.nested_vmx_exit_ctls_low,
2671                 vmx->nested.nested_vmx_exit_ctls_high);
2672         vmx->nested.nested_vmx_exit_ctls_low =
2673                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2674
2675         vmx->nested.nested_vmx_exit_ctls_high &=
2676 #ifdef CONFIG_X86_64
2677                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2678 #endif
2679                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2680         vmx->nested.nested_vmx_exit_ctls_high |=
2681                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2682                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2683                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2684
2685         if (kvm_mpx_supported())
2686                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2687
2688         /* We support free control of debug control saving. */
2689         vmx->nested.nested_vmx_exit_ctls_low &= ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2690
2691         /* entry controls */
2692         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2693                 vmx->nested.nested_vmx_entry_ctls_low,
2694                 vmx->nested.nested_vmx_entry_ctls_high);
2695         vmx->nested.nested_vmx_entry_ctls_low =
2696                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2697         vmx->nested.nested_vmx_entry_ctls_high &=
2698 #ifdef CONFIG_X86_64
2699                 VM_ENTRY_IA32E_MODE |
2700 #endif
2701                 VM_ENTRY_LOAD_IA32_PAT;
2702         vmx->nested.nested_vmx_entry_ctls_high |=
2703                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2704         if (kvm_mpx_supported())
2705                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2706
2707         /* We support free control of debug control loading. */
2708         vmx->nested.nested_vmx_entry_ctls_low &= ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2709
2710         /* cpu-based controls */
2711         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2712                 vmx->nested.nested_vmx_procbased_ctls_low,
2713                 vmx->nested.nested_vmx_procbased_ctls_high);
2714         vmx->nested.nested_vmx_procbased_ctls_low =
2715                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2716         vmx->nested.nested_vmx_procbased_ctls_high &=
2717                 CPU_BASED_VIRTUAL_INTR_PENDING |
2718                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2719                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2720                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2721                 CPU_BASED_CR3_STORE_EXITING |
2722 #ifdef CONFIG_X86_64
2723                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2724 #endif
2725                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2726                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2727                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2728                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2729                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2730         /*
2731          * We can allow some features even when not supported by the
2732          * hardware. For example, L1 can specify an MSR bitmap - and we
2733          * can use it to avoid exits to L1 - even when L0 runs L2
2734          * without MSR bitmaps.
2735          */
2736         vmx->nested.nested_vmx_procbased_ctls_high |=
2737                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2738                 CPU_BASED_USE_MSR_BITMAPS;
2739
2740         /* We support free control of CR3 access interception. */
2741         vmx->nested.nested_vmx_procbased_ctls_low &=
2742                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2743
2744         /* secondary cpu-based controls */
2745         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2746                 vmx->nested.nested_vmx_secondary_ctls_low,
2747                 vmx->nested.nested_vmx_secondary_ctls_high);
2748         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2749         vmx->nested.nested_vmx_secondary_ctls_high &=
2750                 SECONDARY_EXEC_RDRAND | SECONDARY_EXEC_RDSEED |
2751                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2752                 SECONDARY_EXEC_RDTSCP |
2753                 SECONDARY_EXEC_DESC |
2754                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2755                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2756                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2757                 SECONDARY_EXEC_WBINVD_EXITING |
2758                 SECONDARY_EXEC_XSAVES;
2759
2760         if (enable_ept) {
2761                 /* nested EPT: emulate EPT also to L1 */
2762                 vmx->nested.nested_vmx_secondary_ctls_high |=
2763                         SECONDARY_EXEC_ENABLE_EPT;
2764                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2765                          VMX_EPTP_WB_BIT | VMX_EPT_INVEPT_BIT;
2766                 if (cpu_has_vmx_ept_execute_only())
2767                         vmx->nested.nested_vmx_ept_caps |=
2768                                 VMX_EPT_EXECUTE_ONLY_BIT;
2769                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2770                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2771                         VMX_EPT_EXTENT_CONTEXT_BIT | VMX_EPT_2MB_PAGE_BIT |
2772                         VMX_EPT_1GB_PAGE_BIT;
2773                 if (enable_ept_ad_bits) {
2774                         vmx->nested.nested_vmx_secondary_ctls_high |=
2775                                 SECONDARY_EXEC_ENABLE_PML;
2776                         vmx->nested.nested_vmx_ept_caps |= VMX_EPT_AD_BIT;
2777                 }
2778         } else
2779                 vmx->nested.nested_vmx_ept_caps = 0;
2780
2781         /*
2782          * Old versions of KVM use the single-context version without
2783          * checking for support, so declare that it is supported even
2784          * though it is treated as global context.  The alternative is
2785          * not failing the single-context invvpid, and it is worse.
2786          */
2787         if (enable_vpid) {
2788                 vmx->nested.nested_vmx_secondary_ctls_high |=
2789                         SECONDARY_EXEC_ENABLE_VPID;
2790                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2791                         VMX_VPID_EXTENT_SUPPORTED_MASK;
2792         } else
2793                 vmx->nested.nested_vmx_vpid_caps = 0;
2794
2795         if (enable_unrestricted_guest)
2796                 vmx->nested.nested_vmx_secondary_ctls_high |=
2797                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2798
2799         /* miscellaneous data */
2800         rdmsr(MSR_IA32_VMX_MISC,
2801                 vmx->nested.nested_vmx_misc_low,
2802                 vmx->nested.nested_vmx_misc_high);
2803         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2804         vmx->nested.nested_vmx_misc_low |=
2805                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2806                 VMX_MISC_ACTIVITY_HLT;
2807         vmx->nested.nested_vmx_misc_high = 0;
2808
2809         /*
2810          * This MSR reports some information about VMX support. We
2811          * should return information about the VMX we emulate for the
2812          * guest, and the VMCS structure we give it - not about the
2813          * VMX support of the underlying hardware.
2814          */
2815         vmx->nested.nested_vmx_basic =
2816                 VMCS12_REVISION |
2817                 VMX_BASIC_TRUE_CTLS |
2818                 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2819                 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2820
2821         if (cpu_has_vmx_basic_inout())
2822                 vmx->nested.nested_vmx_basic |= VMX_BASIC_INOUT;
2823
2824         /*
2825          * These MSRs specify bits which the guest must keep fixed on
2826          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2827          * We picked the standard core2 setting.
2828          */
2829 #define VMXON_CR0_ALWAYSON     (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2830 #define VMXON_CR4_ALWAYSON     X86_CR4_VMXE
2831         vmx->nested.nested_vmx_cr0_fixed0 = VMXON_CR0_ALWAYSON;
2832         vmx->nested.nested_vmx_cr4_fixed0 = VMXON_CR4_ALWAYSON;
2833
2834         /* These MSRs specify bits which the guest must keep fixed off. */
2835         rdmsrl(MSR_IA32_VMX_CR0_FIXED1, vmx->nested.nested_vmx_cr0_fixed1);
2836         rdmsrl(MSR_IA32_VMX_CR4_FIXED1, vmx->nested.nested_vmx_cr4_fixed1);
2837
2838         /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2839         vmx->nested.nested_vmx_vmcs_enum = 0x2e;
2840 }
2841
2842 /*
2843  * if fixed0[i] == 1: val[i] must be 1
2844  * if fixed1[i] == 0: val[i] must be 0
2845  */
2846 static inline bool fixed_bits_valid(u64 val, u64 fixed0, u64 fixed1)
2847 {
2848         return ((val & fixed1) | fixed0) == val;
2849 }
2850
2851 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2852 {
2853         return fixed_bits_valid(control, low, high);
2854 }
2855
2856 static inline u64 vmx_control_msr(u32 low, u32 high)
2857 {
2858         return low | ((u64)high << 32);
2859 }
2860
2861 static bool is_bitwise_subset(u64 superset, u64 subset, u64 mask)
2862 {
2863         superset &= mask;
2864         subset &= mask;
2865
2866         return (superset | subset) == superset;
2867 }
2868
2869 static int vmx_restore_vmx_basic(struct vcpu_vmx *vmx, u64 data)
2870 {
2871         const u64 feature_and_reserved =
2872                 /* feature (except bit 48; see below) */
2873                 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2874                 /* reserved */
2875                 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2876         u64 vmx_basic = vmx->nested.nested_vmx_basic;
2877
2878         if (!is_bitwise_subset(vmx_basic, data, feature_and_reserved))
2879                 return -EINVAL;
2880
2881         /*
2882          * KVM does not emulate a version of VMX that constrains physical
2883          * addresses of VMX structures (e.g. VMCS) to 32-bits.
2884          */
2885         if (data & BIT_ULL(48))
2886                 return -EINVAL;
2887
2888         if (vmx_basic_vmcs_revision_id(vmx_basic) !=
2889             vmx_basic_vmcs_revision_id(data))
2890                 return -EINVAL;
2891
2892         if (vmx_basic_vmcs_size(vmx_basic) > vmx_basic_vmcs_size(data))
2893                 return -EINVAL;
2894
2895         vmx->nested.nested_vmx_basic = data;
2896         return 0;
2897 }
2898
2899 static int
2900 vmx_restore_control_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2901 {
2902         u64 supported;
2903         u32 *lowp, *highp;
2904
2905         switch (msr_index) {
2906         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2907                 lowp = &vmx->nested.nested_vmx_pinbased_ctls_low;
2908                 highp = &vmx->nested.nested_vmx_pinbased_ctls_high;
2909                 break;
2910         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2911                 lowp = &vmx->nested.nested_vmx_procbased_ctls_low;
2912                 highp = &vmx->nested.nested_vmx_procbased_ctls_high;
2913                 break;
2914         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2915                 lowp = &vmx->nested.nested_vmx_exit_ctls_low;
2916                 highp = &vmx->nested.nested_vmx_exit_ctls_high;
2917                 break;
2918         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2919                 lowp = &vmx->nested.nested_vmx_entry_ctls_low;
2920                 highp = &vmx->nested.nested_vmx_entry_ctls_high;
2921                 break;
2922         case MSR_IA32_VMX_PROCBASED_CTLS2:
2923                 lowp = &vmx->nested.nested_vmx_secondary_ctls_low;
2924                 highp = &vmx->nested.nested_vmx_secondary_ctls_high;
2925                 break;
2926         default:
2927                 BUG();
2928         }
2929
2930         supported = vmx_control_msr(*lowp, *highp);
2931
2932         /* Check must-be-1 bits are still 1. */
2933         if (!is_bitwise_subset(data, supported, GENMASK_ULL(31, 0)))
2934                 return -EINVAL;
2935
2936         /* Check must-be-0 bits are still 0. */
2937         if (!is_bitwise_subset(supported, data, GENMASK_ULL(63, 32)))
2938                 return -EINVAL;
2939
2940         *lowp = data;
2941         *highp = data >> 32;
2942         return 0;
2943 }
2944
2945 static int vmx_restore_vmx_misc(struct vcpu_vmx *vmx, u64 data)
2946 {
2947         const u64 feature_and_reserved_bits =
2948                 /* feature */
2949                 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2950                 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2951                 /* reserved */
2952                 GENMASK_ULL(13, 9) | BIT_ULL(31);
2953         u64 vmx_misc;
2954
2955         vmx_misc = vmx_control_msr(vmx->nested.nested_vmx_misc_low,
2956                                    vmx->nested.nested_vmx_misc_high);
2957
2958         if (!is_bitwise_subset(vmx_misc, data, feature_and_reserved_bits))
2959                 return -EINVAL;
2960
2961         if ((vmx->nested.nested_vmx_pinbased_ctls_high &
2962              PIN_BASED_VMX_PREEMPTION_TIMER) &&
2963             vmx_misc_preemption_timer_rate(data) !=
2964             vmx_misc_preemption_timer_rate(vmx_misc))
2965                 return -EINVAL;
2966
2967         if (vmx_misc_cr3_count(data) > vmx_misc_cr3_count(vmx_misc))
2968                 return -EINVAL;
2969
2970         if (vmx_misc_max_msr(data) > vmx_misc_max_msr(vmx_misc))
2971                 return -EINVAL;
2972
2973         if (vmx_misc_mseg_revid(data) != vmx_misc_mseg_revid(vmx_misc))
2974                 return -EINVAL;
2975
2976         vmx->nested.nested_vmx_misc_low = data;
2977         vmx->nested.nested_vmx_misc_high = data >> 32;
2978         return 0;
2979 }
2980
2981 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx *vmx, u64 data)
2982 {
2983         u64 vmx_ept_vpid_cap;
2984
2985         vmx_ept_vpid_cap = vmx_control_msr(vmx->nested.nested_vmx_ept_caps,
2986                                            vmx->nested.nested_vmx_vpid_caps);
2987
2988         /* Every bit is either reserved or a feature bit. */
2989         if (!is_bitwise_subset(vmx_ept_vpid_cap, data, -1ULL))
2990                 return -EINVAL;
2991
2992         vmx->nested.nested_vmx_ept_caps = data;
2993         vmx->nested.nested_vmx_vpid_caps = data >> 32;
2994         return 0;
2995 }
2996
2997 static int vmx_restore_fixed0_msr(struct vcpu_vmx *vmx, u32 msr_index, u64 data)
2998 {
2999         u64 *msr;
3000
3001         switch (msr_index) {
3002         case MSR_IA32_VMX_CR0_FIXED0:
3003                 msr = &vmx->nested.nested_vmx_cr0_fixed0;
3004                 break;
3005         case MSR_IA32_VMX_CR4_FIXED0:
3006                 msr = &vmx->nested.nested_vmx_cr4_fixed0;
3007                 break;
3008         default:
3009                 BUG();
3010         }
3011
3012         /*
3013          * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3014          * must be 1 in the restored value.
3015          */
3016         if (!is_bitwise_subset(data, *msr, -1ULL))
3017                 return -EINVAL;
3018
3019         *msr = data;
3020         return 0;
3021 }
3022
3023 /*
3024  * Called when userspace is restoring VMX MSRs.
3025  *
3026  * Returns 0 on success, non-0 otherwise.
3027  */
3028 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
3029 {
3030         struct vcpu_vmx *vmx = to_vmx(vcpu);
3031
3032         switch (msr_index) {
3033         case MSR_IA32_VMX_BASIC:
3034                 return vmx_restore_vmx_basic(vmx, data);
3035         case MSR_IA32_VMX_PINBASED_CTLS:
3036         case MSR_IA32_VMX_PROCBASED_CTLS:
3037         case MSR_IA32_VMX_EXIT_CTLS:
3038         case MSR_IA32_VMX_ENTRY_CTLS:
3039                 /*
3040                  * The "non-true" VMX capability MSRs are generated from the
3041                  * "true" MSRs, so we do not support restoring them directly.
3042                  *
3043                  * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3044                  * should restore the "true" MSRs with the must-be-1 bits
3045                  * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3046                  * DEFAULT SETTINGS".
3047                  */
3048                 return -EINVAL;
3049         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3050         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3051         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3052         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3053         case MSR_IA32_VMX_PROCBASED_CTLS2:
3054                 return vmx_restore_control_msr(vmx, msr_index, data);
3055         case MSR_IA32_VMX_MISC:
3056                 return vmx_restore_vmx_misc(vmx, data);
3057         case MSR_IA32_VMX_CR0_FIXED0:
3058         case MSR_IA32_VMX_CR4_FIXED0:
3059                 return vmx_restore_fixed0_msr(vmx, msr_index, data);
3060         case MSR_IA32_VMX_CR0_FIXED1:
3061         case MSR_IA32_VMX_CR4_FIXED1:
3062                 /*
3063                  * These MSRs are generated based on the vCPU's CPUID, so we
3064                  * do not support restoring them directly.
3065                  */
3066                 return -EINVAL;
3067         case MSR_IA32_VMX_EPT_VPID_CAP:
3068                 return vmx_restore_vmx_ept_vpid_cap(vmx, data);
3069         case MSR_IA32_VMX_VMCS_ENUM:
3070                 vmx->nested.nested_vmx_vmcs_enum = data;
3071                 return 0;
3072         default:
3073                 /*
3074                  * The rest of the VMX capability MSRs do not support restore.
3075                  */
3076                 return -EINVAL;
3077         }
3078 }
3079
3080 /* Returns 0 on success, non-0 otherwise. */
3081 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
3082 {
3083         struct vcpu_vmx *vmx = to_vmx(vcpu);
3084
3085         switch (msr_index) {
3086         case MSR_IA32_VMX_BASIC:
3087                 *pdata = vmx->nested.nested_vmx_basic;
3088                 break;
3089         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
3090         case MSR_IA32_VMX_PINBASED_CTLS:
3091                 *pdata = vmx_control_msr(
3092                         vmx->nested.nested_vmx_pinbased_ctls_low,
3093                         vmx->nested.nested_vmx_pinbased_ctls_high);
3094                 if (msr_index == MSR_IA32_VMX_PINBASED_CTLS)
3095                         *pdata |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3096                 break;
3097         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3098         case MSR_IA32_VMX_PROCBASED_CTLS:
3099                 *pdata = vmx_control_msr(
3100                         vmx->nested.nested_vmx_procbased_ctls_low,
3101                         vmx->nested.nested_vmx_procbased_ctls_high);
3102                 if (msr_index == MSR_IA32_VMX_PROCBASED_CTLS)
3103                         *pdata |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
3104                 break;
3105         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
3106         case MSR_IA32_VMX_EXIT_CTLS:
3107                 *pdata = vmx_control_msr(
3108                         vmx->nested.nested_vmx_exit_ctls_low,
3109                         vmx->nested.nested_vmx_exit_ctls_high);
3110                 if (msr_index == MSR_IA32_VMX_EXIT_CTLS)
3111                         *pdata |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
3112                 break;
3113         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
3114         case MSR_IA32_VMX_ENTRY_CTLS:
3115                 *pdata = vmx_control_msr(
3116                         vmx->nested.nested_vmx_entry_ctls_low,
3117                         vmx->nested.nested_vmx_entry_ctls_high);
3118                 if (msr_index == MSR_IA32_VMX_ENTRY_CTLS)
3119                         *pdata |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
3120                 break;
3121         case MSR_IA32_VMX_MISC:
3122                 *pdata = vmx_control_msr(
3123                         vmx->nested.nested_vmx_misc_low,
3124                         vmx->nested.nested_vmx_misc_high);
3125                 break;
3126         case MSR_IA32_VMX_CR0_FIXED0:
3127                 *pdata = vmx->nested.nested_vmx_cr0_fixed0;
3128                 break;
3129         case MSR_IA32_VMX_CR0_FIXED1:
3130                 *pdata = vmx->nested.nested_vmx_cr0_fixed1;
3131                 break;
3132         case MSR_IA32_VMX_CR4_FIXED0:
3133                 *pdata = vmx->nested.nested_vmx_cr4_fixed0;
3134                 break;
3135         case MSR_IA32_VMX_CR4_FIXED1:
3136                 *pdata = vmx->nested.nested_vmx_cr4_fixed1;
3137                 break;
3138         case MSR_IA32_VMX_VMCS_ENUM:
3139                 *pdata = vmx->nested.nested_vmx_vmcs_enum;
3140                 break;
3141         case MSR_IA32_VMX_PROCBASED_CTLS2:
3142                 *pdata = vmx_control_msr(
3143                         vmx->nested.nested_vmx_secondary_ctls_low,
3144                         vmx->nested.nested_vmx_secondary_ctls_high);
3145                 break;
3146         case MSR_IA32_VMX_EPT_VPID_CAP:
3147                 *pdata = vmx->nested.nested_vmx_ept_caps |
3148                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
3149                 break;
3150         default:
3151                 return 1;
3152         }
3153
3154         return 0;
3155 }
3156
3157 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
3158                                                  uint64_t val)
3159 {
3160         uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
3161
3162         return !(val & ~valid_bits);
3163 }
3164
3165 /*
3166  * Reads an msr value (of 'msr_index') into 'pdata'.
3167  * Returns 0 on success, non-0 otherwise.
3168  * Assumes vcpu_load() was already called.
3169  */
3170 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3171 {
3172         struct shared_msr_entry *msr;
3173
3174         switch (msr_info->index) {
3175 #ifdef CONFIG_X86_64
3176         case MSR_FS_BASE:
3177                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
3178                 break;
3179         case MSR_GS_BASE:
3180                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
3181                 break;
3182         case MSR_KERNEL_GS_BASE:
3183                 vmx_load_host_state(to_vmx(vcpu));
3184                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
3185                 break;
3186 #endif
3187         case MSR_EFER:
3188                 return kvm_get_msr_common(vcpu, msr_info);
3189         case MSR_IA32_TSC:
3190                 msr_info->data = guest_read_tsc(vcpu);
3191                 break;
3192         case MSR_IA32_SYSENTER_CS:
3193                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
3194                 break;
3195         case MSR_IA32_SYSENTER_EIP:
3196                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
3197                 break;
3198         case MSR_IA32_SYSENTER_ESP:
3199                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
3200                 break;
3201         case MSR_IA32_BNDCFGS:
3202                 if (!kvm_mpx_supported() ||
3203                     (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
3204                         return 1;
3205                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
3206                 break;
3207         case MSR_IA32_MCG_EXT_CTL:
3208                 if (!msr_info->host_initiated &&
3209                     !(to_vmx(vcpu)->msr_ia32_feature_control &
3210                       FEATURE_CONTROL_LMCE))
3211                         return 1;
3212                 msr_info->data = vcpu->arch.mcg_ext_ctl;
3213                 break;
3214         case MSR_IA32_FEATURE_CONTROL:
3215                 msr_info->data = to_vmx(vcpu)->msr_ia32_feature_control;
3216                 break;
3217         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3218                 if (!nested_vmx_allowed(vcpu))
3219                         return 1;
3220                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
3221         case MSR_IA32_XSS:
3222                 if (!vmx_xsaves_supported())
3223                         return 1;
3224                 msr_info->data = vcpu->arch.ia32_xss;
3225                 break;
3226         case MSR_TSC_AUX:
3227                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3228                         return 1;
3229                 /* Otherwise falls through */
3230         default:
3231                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
3232                 if (msr) {
3233                         msr_info->data = msr->data;
3234                         break;
3235                 }
3236                 return kvm_get_msr_common(vcpu, msr_info);
3237         }
3238
3239         return 0;
3240 }
3241
3242 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
3243
3244 /*
3245  * Writes msr value into into the appropriate "register".
3246  * Returns 0 on success, non-0 otherwise.
3247  * Assumes vcpu_load() was already called.
3248  */
3249 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3250 {
3251         struct vcpu_vmx *vmx = to_vmx(vcpu);
3252         struct shared_msr_entry *msr;
3253         int ret = 0;
3254         u32 msr_index = msr_info->index;
3255         u64 data = msr_info->data;
3256
3257         switch (msr_index) {
3258         case MSR_EFER:
3259                 ret = kvm_set_msr_common(vcpu, msr_info);
3260                 break;
3261 #ifdef CONFIG_X86_64
3262         case MSR_FS_BASE:
3263                 vmx_segment_cache_clear(vmx);
3264                 vmcs_writel(GUEST_FS_BASE, data);
3265                 break;
3266         case MSR_GS_BASE:
3267                 vmx_segment_cache_clear(vmx);
3268                 vmcs_writel(GUEST_GS_BASE, data);
3269                 break;
3270         case MSR_KERNEL_GS_BASE:
3271                 vmx_load_host_state(vmx);
3272                 vmx->msr_guest_kernel_gs_base = data;
3273                 break;
3274 #endif
3275         case MSR_IA32_SYSENTER_CS:
3276                 vmcs_write32(GUEST_SYSENTER_CS, data);
3277                 break;
3278         case MSR_IA32_SYSENTER_EIP:
3279                 vmcs_writel(GUEST_SYSENTER_EIP, data);
3280                 break;
3281         case MSR_IA32_SYSENTER_ESP:
3282                 vmcs_writel(GUEST_SYSENTER_ESP, data);
3283                 break;
3284         case MSR_IA32_BNDCFGS:
3285                 if (!kvm_mpx_supported() ||
3286                     (!msr_info->host_initiated && !guest_cpuid_has_mpx(vcpu)))
3287                         return 1;
3288                 if (is_noncanonical_address(data & PAGE_MASK) ||
3289                     (data & MSR_IA32_BNDCFGS_RSVD))
3290                         return 1;
3291                 vmcs_write64(GUEST_BNDCFGS, data);
3292                 break;
3293         case MSR_IA32_TSC:
3294                 kvm_write_tsc(vcpu, msr_info);
3295                 break;
3296         case MSR_IA32_CR_PAT:
3297                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3298                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
3299                                 return 1;
3300                         vmcs_write64(GUEST_IA32_PAT, data);
3301                         vcpu->arch.pat = data;
3302                         break;
3303                 }
3304                 ret = kvm_set_msr_common(vcpu, msr_info);
3305                 break;
3306         case MSR_IA32_TSC_ADJUST:
3307                 ret = kvm_set_msr_common(vcpu, msr_info);
3308                 break;
3309         case MSR_IA32_MCG_EXT_CTL:
3310                 if ((!msr_info->host_initiated &&
3311                      !(to_vmx(vcpu)->msr_ia32_feature_control &
3312                        FEATURE_CONTROL_LMCE)) ||
3313                     (data & ~MCG_EXT_CTL_LMCE_EN))
3314                         return 1;
3315                 vcpu->arch.mcg_ext_ctl = data;
3316                 break;
3317         case MSR_IA32_FEATURE_CONTROL:
3318                 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3319                     (to_vmx(vcpu)->msr_ia32_feature_control &
3320                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
3321                         return 1;
3322                 vmx->msr_ia32_feature_control = data;
3323                 if (msr_info->host_initiated && data == 0)
3324                         vmx_leave_nested(vcpu);
3325                 break;
3326         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3327                 if (!msr_info->host_initiated)
3328                         return 1; /* they are read-only */
3329                 if (!nested_vmx_allowed(vcpu))
3330                         return 1;
3331                 return vmx_set_vmx_msr(vcpu, msr_index, data);
3332         case MSR_IA32_XSS:
3333                 if (!vmx_xsaves_supported())
3334                         return 1;
3335                 /*
3336                  * The only supported bit as of Skylake is bit 8, but
3337                  * it is not supported on KVM.
3338                  */
3339                 if (data != 0)
3340                         return 1;
3341                 vcpu->arch.ia32_xss = data;
3342                 if (vcpu->arch.ia32_xss != host_xss)
3343                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3344                                 vcpu->arch.ia32_xss, host_xss);
3345                 else
3346                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3347                 break;
3348         case MSR_TSC_AUX:
3349                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3350                         return 1;
3351                 /* Check reserved bit, higher 32 bits should be zero */
3352                 if ((data >> 32) != 0)
3353                         return 1;
3354                 /* Otherwise falls through */
3355         default:
3356                 msr = find_msr_entry(vmx, msr_index);
3357                 if (msr) {
3358                         u64 old_msr_data = msr->data;
3359                         msr->data = data;
3360                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3361                                 preempt_disable();
3362                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3363                                                          msr->mask);
3364                                 preempt_enable();
3365                                 if (ret)
3366                                         msr->data = old_msr_data;
3367                         }
3368                         break;
3369                 }
3370                 ret = kvm_set_msr_common(vcpu, msr_info);
3371         }
3372
3373         return ret;
3374 }
3375
3376 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3377 {
3378         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3379         switch (reg) {
3380         case VCPU_REGS_RSP:
3381                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3382                 break;
3383         case VCPU_REGS_RIP:
3384                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3385                 break;
3386         case VCPU_EXREG_PDPTR:
3387                 if (enable_ept)
3388                         ept_save_pdptrs(vcpu);
3389                 break;
3390         default:
3391                 break;
3392         }
3393 }
3394
3395 static __init int cpu_has_kvm_support(void)
3396 {
3397         return cpu_has_vmx();
3398 }
3399
3400 static __init int vmx_disabled_by_bios(void)
3401 {
3402         u64 msr;
3403
3404         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3405         if (msr & FEATURE_CONTROL_LOCKED) {
3406                 /* launched w/ TXT and VMX disabled */
3407                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3408                         && tboot_enabled())
3409                         return 1;
3410                 /* launched w/o TXT and VMX only enabled w/ TXT */
3411                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3412                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3413                         && !tboot_enabled()) {
3414                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3415                                 "activate TXT before enabling KVM\n");
3416                         return 1;
3417                 }
3418                 /* launched w/o TXT and VMX disabled */
3419                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3420                         && !tboot_enabled())
3421                         return 1;
3422         }
3423
3424         return 0;
3425 }
3426
3427 static void kvm_cpu_vmxon(u64 addr)
3428 {
3429         cr4_set_bits(X86_CR4_VMXE);
3430         intel_pt_handle_vmx(1);
3431
3432         asm volatile (ASM_VMX_VMXON_RAX
3433                         : : "a"(&addr), "m"(addr)
3434                         : "memory", "cc");
3435 }
3436
3437 static int hardware_enable(void)
3438 {
3439         int cpu = raw_smp_processor_id();
3440         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3441         u64 old, test_bits;
3442
3443         if (cr4_read_shadow() & X86_CR4_VMXE)
3444                 return -EBUSY;
3445
3446         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3447         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3448         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3449
3450         /*
3451          * Now we can enable the vmclear operation in kdump
3452          * since the loaded_vmcss_on_cpu list on this cpu
3453          * has been initialized.
3454          *
3455          * Though the cpu is not in VMX operation now, there
3456          * is no problem to enable the vmclear operation
3457          * for the loaded_vmcss_on_cpu list is empty!
3458          */
3459         crash_enable_local_vmclear(cpu);
3460
3461         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3462
3463         test_bits = FEATURE_CONTROL_LOCKED;
3464         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3465         if (tboot_enabled())
3466                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3467
3468         if ((old & test_bits) != test_bits) {
3469                 /* enable and lock */
3470                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3471         }
3472         kvm_cpu_vmxon(phys_addr);
3473         ept_sync_global();
3474
3475         return 0;
3476 }
3477
3478 static void vmclear_local_loaded_vmcss(void)
3479 {
3480         int cpu = raw_smp_processor_id();
3481         struct loaded_vmcs *v, *n;
3482
3483         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3484                                  loaded_vmcss_on_cpu_link)
3485                 __loaded_vmcs_clear(v);
3486 }
3487
3488
3489 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3490  * tricks.
3491  */
3492 static void kvm_cpu_vmxoff(void)
3493 {
3494         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3495
3496         intel_pt_handle_vmx(0);
3497         cr4_clear_bits(X86_CR4_VMXE);
3498 }
3499
3500 static void hardware_disable(void)
3501 {
3502         vmclear_local_loaded_vmcss();
3503         kvm_cpu_vmxoff();
3504 }
3505
3506 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3507                                       u32 msr, u32 *result)
3508 {
3509         u32 vmx_msr_low, vmx_msr_high;
3510         u32 ctl = ctl_min | ctl_opt;
3511
3512         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3513
3514         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3515         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3516
3517         /* Ensure minimum (required) set of control bits are supported. */
3518         if (ctl_min & ~ctl)
3519                 return -EIO;
3520
3521         *result = ctl;
3522         return 0;
3523 }
3524
3525 static __init bool allow_1_setting(u32 msr, u32 ctl)
3526 {
3527         u32 vmx_msr_low, vmx_msr_high;
3528
3529         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3530         return vmx_msr_high & ctl;
3531 }
3532
3533 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3534 {
3535         u32 vmx_msr_low, vmx_msr_high;
3536         u32 min, opt, min2, opt2;
3537         u32 _pin_based_exec_control = 0;
3538         u32 _cpu_based_exec_control = 0;
3539         u32 _cpu_based_2nd_exec_control = 0;
3540         u32 _vmexit_control = 0;
3541         u32 _vmentry_control = 0;
3542
3543         min = CPU_BASED_HLT_EXITING |
3544 #ifdef CONFIG_X86_64
3545               CPU_BASED_CR8_LOAD_EXITING |
3546               CPU_BASED_CR8_STORE_EXITING |
3547 #endif
3548               CPU_BASED_CR3_LOAD_EXITING |
3549               CPU_BASED_CR3_STORE_EXITING |
3550               CPU_BASED_USE_IO_BITMAPS |
3551               CPU_BASED_MOV_DR_EXITING |
3552               CPU_BASED_USE_TSC_OFFSETING |
3553               CPU_BASED_INVLPG_EXITING |
3554               CPU_BASED_RDPMC_EXITING;
3555
3556         if (!kvm_mwait_in_guest())
3557                 min |= CPU_BASED_MWAIT_EXITING |
3558                         CPU_BASED_MONITOR_EXITING;
3559
3560         opt = CPU_BASED_TPR_SHADOW |
3561               CPU_BASED_USE_MSR_BITMAPS |
3562               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3563         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3564                                 &_cpu_based_exec_control) < 0)
3565                 return -EIO;
3566 #ifdef CONFIG_X86_64
3567         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3568                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3569                                            ~CPU_BASED_CR8_STORE_EXITING;
3570 #endif
3571         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3572                 min2 = 0;
3573                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3574                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3575                         SECONDARY_EXEC_WBINVD_EXITING |
3576                         SECONDARY_EXEC_ENABLE_VPID |
3577                         SECONDARY_EXEC_ENABLE_EPT |
3578                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3579                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3580                         SECONDARY_EXEC_RDTSCP |
3581                         SECONDARY_EXEC_ENABLE_INVPCID |
3582                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3583                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3584                         SECONDARY_EXEC_SHADOW_VMCS |
3585                         SECONDARY_EXEC_XSAVES |
3586                         SECONDARY_EXEC_ENABLE_PML |
3587                         SECONDARY_EXEC_TSC_SCALING;
3588                 if (adjust_vmx_controls(min2, opt2,
3589                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3590                                         &_cpu_based_2nd_exec_control) < 0)
3591                         return -EIO;
3592         }
3593 #ifndef CONFIG_X86_64
3594         if (!(_cpu_based_2nd_exec_control &
3595                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3596                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3597 #endif
3598
3599         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3600                 _cpu_based_2nd_exec_control &= ~(
3601                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3602                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3603                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3604
3605         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3606                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3607                    enabled */
3608                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3609                                              CPU_BASED_CR3_STORE_EXITING |
3610                                              CPU_BASED_INVLPG_EXITING);
3611                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3612                       vmx_capability.ept, vmx_capability.vpid);
3613         }
3614
3615         min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
3616 #ifdef CONFIG_X86_64
3617         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3618 #endif
3619         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3620                 VM_EXIT_CLEAR_BNDCFGS;
3621         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3622                                 &_vmexit_control) < 0)
3623                 return -EIO;
3624
3625         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
3626                 PIN_BASED_VIRTUAL_NMIS;
3627         opt = PIN_BASED_POSTED_INTR | PIN_BASED_VMX_PREEMPTION_TIMER;
3628         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3629                                 &_pin_based_exec_control) < 0)
3630                 return -EIO;
3631
3632         if (cpu_has_broken_vmx_preemption_timer())
3633                 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
3634         if (!(_cpu_based_2nd_exec_control &
3635                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
3636                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3637
3638         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3639         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3640         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3641                                 &_vmentry_control) < 0)
3642                 return -EIO;
3643
3644         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3645
3646         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3647         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3648                 return -EIO;
3649
3650 #ifdef CONFIG_X86_64
3651         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3652         if (vmx_msr_high & (1u<<16))
3653                 return -EIO;
3654 #endif
3655
3656         /* Require Write-Back (WB) memory type for VMCS accesses. */
3657         if (((vmx_msr_high >> 18) & 15) != 6)
3658                 return -EIO;
3659
3660         vmcs_conf->size = vmx_msr_high & 0x1fff;
3661         vmcs_conf->order = get_order(vmcs_conf->size);
3662         vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
3663         vmcs_conf->revision_id = vmx_msr_low;
3664
3665         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3666         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3667         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3668         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3669         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3670
3671         cpu_has_load_ia32_efer =
3672                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3673                                 VM_ENTRY_LOAD_IA32_EFER)
3674                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3675                                    VM_EXIT_LOAD_IA32_EFER);
3676
3677         cpu_has_load_perf_global_ctrl =
3678                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3679                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3680                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3681                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3682
3683         /*
3684          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3685          * but due to errata below it can't be used. Workaround is to use
3686          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3687          *
3688          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3689          *
3690          * AAK155             (model 26)
3691          * AAP115             (model 30)
3692          * AAT100             (model 37)
3693          * BC86,AAY89,BD102   (model 44)
3694          * BA97               (model 46)
3695          *
3696          */
3697         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3698                 switch (boot_cpu_data.x86_model) {
3699                 case 26:
3700                 case 30:
3701                 case 37:
3702                 case 44:
3703                 case 46:
3704                         cpu_has_load_perf_global_ctrl = false;
3705                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3706                                         "does not work properly. Using workaround\n");
3707                         break;
3708                 default:
3709                         break;
3710                 }
3711         }
3712
3713         if (boot_cpu_has(X86_FEATURE_XSAVES))
3714                 rdmsrl(MSR_IA32_XSS, host_xss);
3715
3716         return 0;
3717 }
3718
3719 static struct vmcs *alloc_vmcs_cpu(int cpu)
3720 {
3721         int node = cpu_to_node(cpu);
3722         struct page *pages;
3723         struct vmcs *vmcs;
3724
3725         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3726         if (!pages)
3727                 return NULL;
3728         vmcs = page_address(pages);
3729         memset(vmcs, 0, vmcs_config.size);
3730         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3731         return vmcs;
3732 }
3733
3734 static struct vmcs *alloc_vmcs(void)
3735 {
3736         return alloc_vmcs_cpu(raw_smp_processor_id());
3737 }
3738
3739 static void free_vmcs(struct vmcs *vmcs)
3740 {
3741         free_pages((unsigned long)vmcs, vmcs_config.order);
3742 }
3743
3744 /*
3745  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3746  */
3747 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3748 {
3749         if (!loaded_vmcs->vmcs)
3750                 return;
3751         loaded_vmcs_clear(loaded_vmcs);
3752         free_vmcs(loaded_vmcs->vmcs);
3753         loaded_vmcs->vmcs = NULL;
3754         WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
3755 }
3756
3757 static void free_kvm_area(void)
3758 {
3759         int cpu;
3760
3761         for_each_possible_cpu(cpu) {
3762                 free_vmcs(per_cpu(vmxarea, cpu));
3763                 per_cpu(vmxarea, cpu) = NULL;
3764         }
3765 }
3766
3767 static void init_vmcs_shadow_fields(void)
3768 {
3769         int i, j;
3770
3771         /* No checks for read only fields yet */
3772
3773         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3774                 switch (shadow_read_write_fields[i]) {
3775                 case GUEST_BNDCFGS:
3776                         if (!kvm_mpx_supported())
3777                                 continue;
3778                         break;
3779                 default:
3780                         break;
3781                 }
3782
3783                 if (j < i)
3784                         shadow_read_write_fields[j] =
3785                                 shadow_read_write_fields[i];
3786                 j++;
3787         }
3788         max_shadow_read_write_fields = j;
3789
3790         /* shadowed fields guest access without vmexit */
3791         for (i = 0; i < max_shadow_read_write_fields; i++) {
3792                 clear_bit(shadow_read_write_fields[i],
3793                           vmx_vmwrite_bitmap);
3794                 clear_bit(shadow_read_write_fields[i],
3795                           vmx_vmread_bitmap);
3796         }
3797         for (i = 0; i < max_shadow_read_only_fields; i++)
3798                 clear_bit(shadow_read_only_fields[i],
3799                           vmx_vmread_bitmap);
3800 }
3801
3802 static __init int alloc_kvm_area(void)
3803 {
3804         int cpu;
3805
3806         for_each_possible_cpu(cpu) {
3807                 struct vmcs *vmcs;
3808
3809                 vmcs = alloc_vmcs_cpu(cpu);
3810                 if (!vmcs) {
3811                         free_kvm_area();
3812                         return -ENOMEM;
3813                 }
3814
3815                 per_cpu(vmxarea, cpu) = vmcs;
3816         }
3817         return 0;
3818 }
3819
3820 static bool emulation_required(struct kvm_vcpu *vcpu)
3821 {
3822         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3823 }
3824
3825 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3826                 struct kvm_segment *save)
3827 {
3828         if (!emulate_invalid_guest_state) {
3829                 /*
3830                  * CS and SS RPL should be equal during guest entry according
3831                  * to VMX spec, but in reality it is not always so. Since vcpu
3832                  * is in the middle of the transition from real mode to
3833                  * protected mode it is safe to assume that RPL 0 is a good
3834                  * default value.
3835                  */
3836                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3837                         save->selector &= ~SEGMENT_RPL_MASK;
3838                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3839                 save->s = 1;
3840         }
3841         vmx_set_segment(vcpu, save, seg);
3842 }
3843
3844 static void enter_pmode(struct kvm_vcpu *vcpu)
3845 {
3846         unsigned long flags;
3847         struct vcpu_vmx *vmx = to_vmx(vcpu);
3848
3849         /*
3850          * Update real mode segment cache. It may be not up-to-date if sement
3851          * register was written while vcpu was in a guest mode.
3852          */
3853         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3854         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3855         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3856         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3857         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3858         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3859
3860         vmx->rmode.vm86_active = 0;
3861
3862         vmx_segment_cache_clear(vmx);
3863
3864         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3865
3866         flags = vmcs_readl(GUEST_RFLAGS);
3867         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3868         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3869         vmcs_writel(GUEST_RFLAGS, flags);
3870
3871         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3872                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3873
3874         update_exception_bitmap(vcpu);
3875
3876         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3877         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3878         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3879         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3880         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3881         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3882 }
3883
3884 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3885 {
3886         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3887         struct kvm_segment var = *save;
3888
3889         var.dpl = 0x3;
3890         if (seg == VCPU_SREG_CS)
3891                 var.type = 0x3;
3892
3893         if (!emulate_invalid_guest_state) {
3894                 var.selector = var.base >> 4;
3895                 var.base = var.base & 0xffff0;
3896                 var.limit = 0xffff;
3897                 var.g = 0;
3898                 var.db = 0;
3899                 var.present = 1;
3900                 var.s = 1;
3901                 var.l = 0;
3902                 var.unusable = 0;
3903                 var.type = 0x3;
3904                 var.avl = 0;
3905                 if (save->base & 0xf)
3906                         printk_once(KERN_WARNING "kvm: segment base is not "
3907                                         "paragraph aligned when entering "
3908                                         "protected mode (seg=%d)", seg);
3909         }
3910
3911         vmcs_write16(sf->selector, var.selector);
3912         vmcs_writel(sf->base, var.base);
3913         vmcs_write32(sf->limit, var.limit);
3914         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3915 }
3916
3917 static void enter_rmode(struct kvm_vcpu *vcpu)
3918 {
3919         unsigned long flags;
3920         struct vcpu_vmx *vmx = to_vmx(vcpu);
3921
3922         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3923         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3924         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3925         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3926         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3927         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3928         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3929
3930         vmx->rmode.vm86_active = 1;
3931
3932         /*
3933          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3934          * vcpu. Warn the user that an update is overdue.
3935          */
3936         if (!vcpu->kvm->arch.tss_addr)
3937                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3938                              "called before entering vcpu\n");
3939
3940         vmx_segment_cache_clear(vmx);
3941
3942         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3943         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3944         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3945
3946         flags = vmcs_readl(GUEST_RFLAGS);
3947         vmx->rmode.save_rflags = flags;
3948
3949         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3950
3951         vmcs_writel(GUEST_RFLAGS, flags);
3952         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3953         update_exception_bitmap(vcpu);
3954
3955         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3956         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3957         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3958         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3959         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3960         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3961
3962         kvm_mmu_reset_context(vcpu);
3963 }
3964
3965 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3966 {
3967         struct vcpu_vmx *vmx = to_vmx(vcpu);
3968         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3969
3970         if (!msr)
3971                 return;
3972
3973         /*
3974          * Force kernel_gs_base reloading before EFER changes, as control
3975          * of this msr depends on is_long_mode().
3976          */
3977         vmx_load_host_state(to_vmx(vcpu));
3978         vcpu->arch.efer = efer;
3979         if (efer & EFER_LMA) {
3980                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3981                 msr->data = efer;
3982         } else {
3983                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3984
3985                 msr->data = efer & ~EFER_LME;
3986         }
3987         setup_msrs(vmx);
3988 }
3989
3990 #ifdef CONFIG_X86_64
3991
3992 static void enter_lmode(struct kvm_vcpu *vcpu)
3993 {
3994         u32 guest_tr_ar;
3995
3996         vmx_segment_cache_clear(to_vmx(vcpu));
3997
3998         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3999         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
4000                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4001                                      __func__);
4002                 vmcs_write32(GUEST_TR_AR_BYTES,
4003                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
4004                              | VMX_AR_TYPE_BUSY_64_TSS);
4005         }
4006         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
4007 }
4008
4009 static void exit_lmode(struct kvm_vcpu *vcpu)
4010 {
4011         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
4012         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
4013 }
4014
4015 #endif
4016
4017 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
4018 {
4019         if (enable_ept) {
4020                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
4021                         return;
4022                 ept_sync_context(construct_eptp(vcpu, vcpu->arch.mmu.root_hpa));
4023         } else {
4024                 vpid_sync_context(vpid);
4025         }
4026 }
4027
4028 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
4029 {
4030         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
4031 }
4032
4033 static void vmx_flush_tlb_ept_only(struct kvm_vcpu *vcpu)
4034 {
4035         if (enable_ept)
4036                 vmx_flush_tlb(vcpu);
4037 }
4038
4039 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
4040 {
4041         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
4042
4043         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
4044         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
4045 }
4046
4047 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
4048 {
4049         if (enable_ept && is_paging(vcpu))
4050                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
4051         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
4052 }
4053
4054 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
4055 {
4056         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
4057
4058         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
4059         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
4060 }
4061
4062 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
4063 {
4064         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4065
4066         if (!test_bit(VCPU_EXREG_PDPTR,
4067                       (unsigned long *)&vcpu->arch.regs_dirty))
4068                 return;
4069
4070         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4071                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
4072                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
4073                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
4074                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
4075         }
4076 }
4077
4078 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
4079 {
4080         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
4081
4082         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
4083                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
4084                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
4085                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
4086                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
4087         }
4088
4089         __set_bit(VCPU_EXREG_PDPTR,
4090                   (unsigned long *)&vcpu->arch.regs_avail);
4091         __set_bit(VCPU_EXREG_PDPTR,
4092                   (unsigned long *)&vcpu->arch.regs_dirty);
4093 }
4094
4095 static bool nested_guest_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4096 {
4097         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4098         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4099         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4100
4101         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
4102                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4103             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4104                 fixed0 &= ~(X86_CR0_PE | X86_CR0_PG);
4105
4106         return fixed_bits_valid(val, fixed0, fixed1);
4107 }
4108
4109 static bool nested_host_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
4110 {
4111         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed0;
4112         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr0_fixed1;
4113
4114         return fixed_bits_valid(val, fixed0, fixed1);
4115 }
4116
4117 static bool nested_cr4_valid(struct kvm_vcpu *vcpu, unsigned long val)
4118 {
4119         u64 fixed0 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed0;
4120         u64 fixed1 = to_vmx(vcpu)->nested.nested_vmx_cr4_fixed1;
4121
4122         return fixed_bits_valid(val, fixed0, fixed1);
4123 }
4124
4125 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4126 #define nested_guest_cr4_valid  nested_cr4_valid
4127 #define nested_host_cr4_valid   nested_cr4_valid
4128
4129 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
4130
4131 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
4132                                         unsigned long cr0,
4133                                         struct kvm_vcpu *vcpu)
4134 {
4135         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
4136                 vmx_decache_cr3(vcpu);
4137         if (!(cr0 & X86_CR0_PG)) {
4138                 /* From paging/starting to nonpaging */
4139                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4140                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
4141                              (CPU_BASED_CR3_LOAD_EXITING |
4142                               CPU_BASED_CR3_STORE_EXITING));
4143                 vcpu->arch.cr0 = cr0;
4144                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4145         } else if (!is_paging(vcpu)) {
4146                 /* From nonpaging to paging */
4147                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
4148                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
4149                              ~(CPU_BASED_CR3_LOAD_EXITING |
4150                                CPU_BASED_CR3_STORE_EXITING));
4151                 vcpu->arch.cr0 = cr0;
4152                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
4153         }
4154
4155         if (!(cr0 & X86_CR0_WP))
4156                 *hw_cr0 &= ~X86_CR0_WP;
4157 }
4158
4159 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
4160 {
4161         struct vcpu_vmx *vmx = to_vmx(vcpu);
4162         unsigned long hw_cr0;
4163
4164         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
4165         if (enable_unrestricted_guest)
4166                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
4167         else {
4168                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
4169
4170                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
4171                         enter_pmode(vcpu);
4172
4173                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
4174                         enter_rmode(vcpu);
4175         }
4176
4177 #ifdef CONFIG_X86_64
4178         if (vcpu->arch.efer & EFER_LME) {
4179                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
4180                         enter_lmode(vcpu);
4181                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
4182                         exit_lmode(vcpu);
4183         }
4184 #endif
4185
4186         if (enable_ept)
4187                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
4188
4189         vmcs_writel(CR0_READ_SHADOW, cr0);
4190         vmcs_writel(GUEST_CR0, hw_cr0);
4191         vcpu->arch.cr0 = cr0;
4192
4193         /* depends on vcpu->arch.cr0 to be set to a new value */
4194         vmx->emulation_required = emulation_required(vcpu);
4195 }
4196
4197 static u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
4198 {
4199         u64 eptp;
4200
4201         /* TODO write the value reading from MSR */
4202         eptp = VMX_EPT_DEFAULT_MT |
4203                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
4204         if (enable_ept_ad_bits &&
4205             (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
4206                 eptp |= VMX_EPT_AD_ENABLE_BIT;
4207         eptp |= (root_hpa & PAGE_MASK);
4208
4209         return eptp;
4210 }
4211
4212 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
4213 {
4214         unsigned long guest_cr3;
4215         u64 eptp;
4216
4217         guest_cr3 = cr3;
4218         if (enable_ept) {
4219                 eptp = construct_eptp(vcpu, cr3);
4220                 vmcs_write64(EPT_POINTER, eptp);
4221                 if (is_paging(vcpu) || is_guest_mode(vcpu))
4222                         guest_cr3 = kvm_read_cr3(vcpu);
4223                 else
4224                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
4225                 ept_load_pdptrs(vcpu);
4226         }
4227
4228         vmx_flush_tlb(vcpu);
4229         vmcs_writel(GUEST_CR3, guest_cr3);
4230 }
4231
4232 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
4233 {
4234         /*
4235          * Pass through host's Machine Check Enable value to hw_cr4, which
4236          * is in force while we are in guest mode.  Do not let guests control
4237          * this bit, even if host CR4.MCE == 0.
4238          */
4239         unsigned long hw_cr4 =
4240                 (cr4_read_shadow() & X86_CR4_MCE) |
4241                 (cr4 & ~X86_CR4_MCE) |
4242                 (to_vmx(vcpu)->rmode.vm86_active ?
4243                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
4244
4245         if (cr4 & X86_CR4_VMXE) {
4246                 /*
4247                  * To use VMXON (and later other VMX instructions), a guest
4248                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
4249                  * So basically the check on whether to allow nested VMX
4250                  * is here.
4251                  */
4252                 if (!nested_vmx_allowed(vcpu))
4253                         return 1;
4254         }
4255
4256         if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
4257                 return 1;
4258
4259         vcpu->arch.cr4 = cr4;
4260         if (enable_ept) {
4261                 if (!is_paging(vcpu)) {
4262                         hw_cr4 &= ~X86_CR4_PAE;
4263                         hw_cr4 |= X86_CR4_PSE;
4264                 } else if (!(cr4 & X86_CR4_PAE)) {
4265                         hw_cr4 &= ~X86_CR4_PAE;
4266                 }
4267         }
4268
4269         if (!enable_unrestricted_guest && !is_paging(vcpu))
4270                 /*
4271                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4272                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
4273                  * to be manually disabled when guest switches to non-paging
4274                  * mode.
4275                  *
4276                  * If !enable_unrestricted_guest, the CPU is always running
4277                  * with CR0.PG=1 and CR4 needs to be modified.
4278                  * If enable_unrestricted_guest, the CPU automatically
4279                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4280                  */
4281                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
4282
4283         vmcs_writel(CR4_READ_SHADOW, cr4);
4284         vmcs_writel(GUEST_CR4, hw_cr4);
4285         return 0;
4286 }
4287
4288 static void vmx_get_segment(struct kvm_vcpu *vcpu,
4289                             struct kvm_segment *var, int seg)
4290 {
4291         struct vcpu_vmx *vmx = to_vmx(vcpu);
4292         u32 ar;
4293
4294         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4295                 *var = vmx->rmode.segs[seg];
4296                 if (seg == VCPU_SREG_TR
4297                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
4298                         return;
4299                 var->base = vmx_read_guest_seg_base(vmx, seg);
4300                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
4301                 return;
4302         }
4303         var->base = vmx_read_guest_seg_base(vmx, seg);
4304         var->limit = vmx_read_guest_seg_limit(vmx, seg);
4305         var->selector = vmx_read_guest_seg_selector(vmx, seg);
4306         ar = vmx_read_guest_seg_ar(vmx, seg);
4307         var->unusable = (ar >> 16) & 1;
4308         var->type = ar & 15;
4309         var->s = (ar >> 4) & 1;
4310         var->dpl = (ar >> 5) & 3;
4311         /*
4312          * Some userspaces do not preserve unusable property. Since usable
4313          * segment has to be present according to VMX spec we can use present
4314          * property to amend userspace bug by making unusable segment always
4315          * nonpresent. vmx_segment_access_rights() already marks nonpresent
4316          * segment as unusable.
4317          */
4318         var->present = !var->unusable;
4319         var->avl = (ar >> 12) & 1;
4320         var->l = (ar >> 13) & 1;
4321         var->db = (ar >> 14) & 1;
4322         var->g = (ar >> 15) & 1;
4323 }
4324
4325 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
4326 {
4327         struct kvm_segment s;
4328
4329         if (to_vmx(vcpu)->rmode.vm86_active) {
4330                 vmx_get_segment(vcpu, &s, seg);
4331                 return s.base;
4332         }
4333         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
4334 }
4335
4336 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
4337 {
4338         struct vcpu_vmx *vmx = to_vmx(vcpu);
4339
4340         if (unlikely(vmx->rmode.vm86_active))
4341                 return 0;
4342         else {
4343                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4344                 return VMX_AR_DPL(ar);
4345         }
4346 }
4347
4348 static u32 vmx_segment_access_rights(struct kvm_segment *var)
4349 {
4350         u32 ar;
4351
4352         if (var->unusable || !var->present)
4353                 ar = 1 << 16;
4354         else {
4355                 ar = var->type & 15;
4356                 ar |= (var->s & 1) << 4;
4357                 ar |= (var->dpl & 3) << 5;
4358                 ar |= (var->present & 1) << 7;
4359                 ar |= (var->avl & 1) << 12;
4360                 ar |= (var->l & 1) << 13;
4361                 ar |= (var->db & 1) << 14;
4362                 ar |= (var->g & 1) << 15;
4363         }
4364
4365         return ar;
4366 }
4367
4368 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4369                             struct kvm_segment *var, int seg)
4370 {
4371         struct vcpu_vmx *vmx = to_vmx(vcpu);
4372         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4373
4374         vmx_segment_cache_clear(vmx);
4375
4376         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4377                 vmx->rmode.segs[seg] = *var;
4378                 if (seg == VCPU_SREG_TR)
4379                         vmcs_write16(sf->selector, var->selector);
4380                 else if (var->s)
4381                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4382                 goto out;
4383         }
4384
4385         vmcs_writel(sf->base, var->base);
4386         vmcs_write32(sf->limit, var->limit);
4387         vmcs_write16(sf->selector, var->selector);
4388
4389         /*
4390          *   Fix the "Accessed" bit in AR field of segment registers for older
4391          * qemu binaries.
4392          *   IA32 arch specifies that at the time of processor reset the
4393          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4394          * is setting it to 0 in the userland code. This causes invalid guest
4395          * state vmexit when "unrestricted guest" mode is turned on.
4396          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4397          * tree. Newer qemu binaries with that qemu fix would not need this
4398          * kvm hack.
4399          */
4400         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4401                 var->type |= 0x1; /* Accessed */
4402
4403         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4404
4405 out:
4406         vmx->emulation_required = emulation_required(vcpu);
4407 }
4408
4409 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4410 {
4411         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4412
4413         *db = (ar >> 14) & 1;
4414         *l = (ar >> 13) & 1;
4415 }
4416
4417 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4418 {
4419         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4420         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4421 }
4422
4423 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4424 {
4425         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4426         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4427 }
4428
4429 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4430 {
4431         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4432         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4433 }
4434
4435 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4436 {
4437         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4438         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4439 }
4440
4441 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4442 {
4443         struct kvm_segment var;
4444         u32 ar;
4445
4446         vmx_get_segment(vcpu, &var, seg);
4447         var.dpl = 0x3;
4448         if (seg == VCPU_SREG_CS)
4449                 var.type = 0x3;
4450         ar = vmx_segment_access_rights(&var);
4451
4452         if (var.base != (var.selector << 4))
4453                 return false;
4454         if (var.limit != 0xffff)
4455                 return false;
4456         if (ar != 0xf3)
4457                 return false;
4458
4459         return true;
4460 }
4461
4462 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4463 {
4464         struct kvm_segment cs;
4465         unsigned int cs_rpl;
4466
4467         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4468         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4469
4470         if (cs.unusable)
4471                 return false;
4472         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4473                 return false;
4474         if (!cs.s)
4475                 return false;
4476         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4477                 if (cs.dpl > cs_rpl)
4478                         return false;
4479         } else {
4480                 if (cs.dpl != cs_rpl)
4481                         return false;
4482         }
4483         if (!cs.present)
4484                 return false;
4485
4486         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4487         return true;
4488 }
4489
4490 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4491 {
4492         struct kvm_segment ss;
4493         unsigned int ss_rpl;
4494
4495         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4496         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4497
4498         if (ss.unusable)
4499                 return true;
4500         if (ss.type != 3 && ss.type != 7)
4501                 return false;
4502         if (!ss.s)
4503                 return false;
4504         if (ss.dpl != ss_rpl) /* DPL != RPL */
4505                 return false;
4506         if (!ss.present)
4507                 return false;
4508
4509         return true;
4510 }
4511
4512 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4513 {
4514         struct kvm_segment var;
4515         unsigned int rpl;
4516
4517         vmx_get_segment(vcpu, &var, seg);
4518         rpl = var.selector & SEGMENT_RPL_MASK;
4519
4520         if (var.unusable)
4521                 return true;
4522         if (!var.s)
4523                 return false;
4524         if (!var.present)
4525                 return false;
4526         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4527                 if (var.dpl < rpl) /* DPL < RPL */
4528                         return false;
4529         }
4530
4531         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4532          * rights flags
4533          */
4534         return true;
4535 }
4536
4537 static bool tr_valid(struct kvm_vcpu *vcpu)
4538 {
4539         struct kvm_segment tr;
4540
4541         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4542
4543         if (tr.unusable)
4544                 return false;
4545         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4546                 return false;
4547         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4548                 return false;
4549         if (!tr.present)
4550                 return false;
4551
4552         return true;
4553 }
4554
4555 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4556 {
4557         struct kvm_segment ldtr;
4558
4559         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4560
4561         if (ldtr.unusable)
4562                 return true;
4563         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4564                 return false;
4565         if (ldtr.type != 2)
4566                 return false;
4567         if (!ldtr.present)
4568                 return false;
4569
4570         return true;
4571 }
4572
4573 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4574 {
4575         struct kvm_segment cs, ss;
4576
4577         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4578         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4579
4580         return ((cs.selector & SEGMENT_RPL_MASK) ==
4581                  (ss.selector & SEGMENT_RPL_MASK));
4582 }
4583
4584 /*
4585  * Check if guest state is valid. Returns true if valid, false if
4586  * not.
4587  * We assume that registers are always usable
4588  */
4589 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4590 {
4591         if (enable_unrestricted_guest)
4592                 return true;
4593
4594         /* real mode guest state checks */
4595         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4596                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4597                         return false;
4598                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4599                         return false;
4600                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4601                         return false;
4602                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4603                         return false;
4604                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4605                         return false;
4606                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4607                         return false;
4608         } else {
4609         /* protected mode guest state checks */
4610                 if (!cs_ss_rpl_check(vcpu))
4611                         return false;
4612                 if (!code_segment_valid(vcpu))
4613                         return false;
4614                 if (!stack_segment_valid(vcpu))
4615                         return false;
4616                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4617                         return false;
4618                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4619                         return false;
4620                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4621                         return false;
4622                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4623                         return false;
4624                 if (!tr_valid(vcpu))
4625                         return false;
4626                 if (!ldtr_valid(vcpu))
4627                         return false;
4628         }
4629         /* TODO:
4630          * - Add checks on RIP
4631          * - Add checks on RFLAGS
4632          */
4633
4634         return true;
4635 }
4636
4637 static int init_rmode_tss(struct kvm *kvm)
4638 {
4639         gfn_t fn;
4640         u16 data = 0;
4641         int idx, r;
4642
4643         idx = srcu_read_lock(&kvm->srcu);
4644         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4645         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4646         if (r < 0)
4647                 goto out;
4648         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4649         r = kvm_write_guest_page(kvm, fn++, &data,
4650                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4651         if (r < 0)
4652                 goto out;
4653         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4654         if (r < 0)
4655                 goto out;
4656         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4657         if (r < 0)
4658                 goto out;
4659         data = ~0;
4660         r = kvm_write_guest_page(kvm, fn, &data,
4661                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4662                                  sizeof(u8));
4663 out:
4664         srcu_read_unlock(&kvm->srcu, idx);
4665         return r;
4666 }
4667
4668 static int init_rmode_identity_map(struct kvm *kvm)
4669 {
4670         int i, idx, r = 0;
4671         kvm_pfn_t identity_map_pfn;
4672         u32 tmp;
4673
4674         if (!enable_ept)
4675                 return 0;
4676
4677         /* Protect kvm->arch.ept_identity_pagetable_done. */
4678         mutex_lock(&kvm->slots_lock);
4679
4680         if (likely(kvm->arch.ept_identity_pagetable_done))
4681                 goto out2;
4682
4683         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4684
4685         r = alloc_identity_pagetable(kvm);
4686         if (r < 0)
4687                 goto out2;
4688
4689         idx = srcu_read_lock(&kvm->srcu);
4690         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4691         if (r < 0)
4692                 goto out;
4693         /* Set up identity-mapping pagetable for EPT in real mode */
4694         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4695                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4696                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4697                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4698                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4699                 if (r < 0)
4700                         goto out;
4701         }
4702         kvm->arch.ept_identity_pagetable_done = true;
4703
4704 out:
4705         srcu_read_unlock(&kvm->srcu, idx);
4706
4707 out2:
4708         mutex_unlock(&kvm->slots_lock);
4709         return r;
4710 }
4711
4712 static void seg_setup(int seg)
4713 {
4714         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4715         unsigned int ar;
4716
4717         vmcs_write16(sf->selector, 0);
4718         vmcs_writel(sf->base, 0);
4719         vmcs_write32(sf->limit, 0xffff);
4720         ar = 0x93;
4721         if (seg == VCPU_SREG_CS)
4722                 ar |= 0x08; /* code segment */
4723
4724         vmcs_write32(sf->ar_bytes, ar);
4725 }
4726
4727 static int alloc_apic_access_page(struct kvm *kvm)
4728 {
4729         struct page *page;
4730         int r = 0;
4731
4732         mutex_lock(&kvm->slots_lock);
4733         if (kvm->arch.apic_access_page_done)
4734                 goto out;
4735         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4736                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4737         if (r)
4738                 goto out;
4739
4740         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4741         if (is_error_page(page)) {
4742                 r = -EFAULT;
4743                 goto out;
4744         }
4745
4746         /*
4747          * Do not pin the page in memory, so that memory hot-unplug
4748          * is able to migrate it.
4749          */
4750         put_page(page);
4751         kvm->arch.apic_access_page_done = true;
4752 out:
4753         mutex_unlock(&kvm->slots_lock);
4754         return r;
4755 }
4756
4757 static int alloc_identity_pagetable(struct kvm *kvm)
4758 {
4759         /* Called with kvm->slots_lock held. */
4760
4761         int r = 0;
4762
4763         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4764
4765         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4766                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4767
4768         return r;
4769 }
4770
4771 static int allocate_vpid(void)
4772 {
4773         int vpid;
4774
4775         if (!enable_vpid)
4776                 return 0;
4777         spin_lock(&vmx_vpid_lock);
4778         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4779         if (vpid < VMX_NR_VPIDS)
4780                 __set_bit(vpid, vmx_vpid_bitmap);
4781         else
4782                 vpid = 0;
4783         spin_unlock(&vmx_vpid_lock);
4784         return vpid;
4785 }
4786
4787 static void free_vpid(int vpid)
4788 {
4789         if (!enable_vpid || vpid == 0)
4790                 return;
4791         spin_lock(&vmx_vpid_lock);
4792         __clear_bit(vpid, vmx_vpid_bitmap);
4793         spin_unlock(&vmx_vpid_lock);
4794 }
4795
4796 #define MSR_TYPE_R      1
4797 #define MSR_TYPE_W      2
4798 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4799                                                 u32 msr, int type)
4800 {
4801         int f = sizeof(unsigned long);
4802
4803         if (!cpu_has_vmx_msr_bitmap())
4804                 return;
4805
4806         /*
4807          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4808          * have the write-low and read-high bitmap offsets the wrong way round.
4809          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4810          */
4811         if (msr <= 0x1fff) {
4812                 if (type & MSR_TYPE_R)
4813                         /* read-low */
4814                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4815
4816                 if (type & MSR_TYPE_W)
4817                         /* write-low */
4818                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4819
4820         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4821                 msr &= 0x1fff;
4822                 if (type & MSR_TYPE_R)
4823                         /* read-high */
4824                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4825
4826                 if (type & MSR_TYPE_W)
4827                         /* write-high */
4828                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4829
4830         }
4831 }
4832
4833 /*
4834  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4835  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4836  */
4837 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4838                                                unsigned long *msr_bitmap_nested,
4839                                                u32 msr, int type)
4840 {
4841         int f = sizeof(unsigned long);
4842
4843         if (!cpu_has_vmx_msr_bitmap()) {
4844                 WARN_ON(1);
4845                 return;
4846         }
4847
4848         /*
4849          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4850          * have the write-low and read-high bitmap offsets the wrong way round.
4851          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4852          */
4853         if (msr <= 0x1fff) {
4854                 if (type & MSR_TYPE_R &&
4855                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4856                         /* read-low */
4857                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4858
4859                 if (type & MSR_TYPE_W &&
4860                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4861                         /* write-low */
4862                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4863
4864         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4865                 msr &= 0x1fff;
4866                 if (type & MSR_TYPE_R &&
4867                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4868                         /* read-high */
4869                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4870
4871                 if (type & MSR_TYPE_W &&
4872                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4873                         /* write-high */
4874                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4875
4876         }
4877 }
4878
4879 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4880 {
4881         if (!longmode_only)
4882                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4883                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4884         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4885                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4886 }
4887
4888 static void vmx_disable_intercept_msr_x2apic(u32 msr, int type, bool apicv_active)
4889 {
4890         if (apicv_active) {
4891                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv,
4892                                 msr, type);
4893                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv,
4894                                 msr, type);
4895         } else {
4896                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4897                                 msr, type);
4898                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4899                                 msr, type);
4900         }
4901 }
4902
4903 static bool vmx_get_enable_apicv(void)
4904 {
4905         return enable_apicv;
4906 }
4907
4908 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4909 {
4910         struct vcpu_vmx *vmx = to_vmx(vcpu);
4911         int max_irr;
4912         void *vapic_page;
4913         u16 status;
4914
4915         if (vmx->nested.pi_desc &&
4916             vmx->nested.pi_pending) {
4917                 vmx->nested.pi_pending = false;
4918                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4919                         return;
4920
4921                 max_irr = find_last_bit(
4922                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4923
4924                 if (max_irr == 256)
4925                         return;
4926
4927                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4928                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4929                 kunmap(vmx->nested.virtual_apic_page);
4930
4931                 status = vmcs_read16(GUEST_INTR_STATUS);
4932                 if ((u8)max_irr > ((u8)status & 0xff)) {
4933                         status &= ~0xff;
4934                         status |= (u8)max_irr;
4935                         vmcs_write16(GUEST_INTR_STATUS, status);
4936                 }
4937         }
4938 }
4939
4940 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4941 {
4942 #ifdef CONFIG_SMP
4943         if (vcpu->mode == IN_GUEST_MODE) {
4944                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4945
4946                 /*
4947                  * Currently, we don't support urgent interrupt,
4948                  * all interrupts are recognized as non-urgent
4949                  * interrupt, so we cannot post interrupts when
4950                  * 'SN' is set.
4951                  *
4952                  * If the vcpu is in guest mode, it means it is
4953                  * running instead of being scheduled out and
4954                  * waiting in the run queue, and that's the only
4955                  * case when 'SN' is set currently, warning if
4956                  * 'SN' is set.
4957                  */
4958                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4959
4960                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4961                                 POSTED_INTR_VECTOR);
4962                 return true;
4963         }
4964 #endif
4965         return false;
4966 }
4967
4968 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4969                                                 int vector)
4970 {
4971         struct vcpu_vmx *vmx = to_vmx(vcpu);
4972
4973         if (is_guest_mode(vcpu) &&
4974             vector == vmx->nested.posted_intr_nv) {
4975                 /* the PIR and ON have been set by L1. */
4976                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4977                 /*
4978                  * If a posted intr is not recognized by hardware,
4979                  * we will accomplish it in the next vmentry.
4980                  */
4981                 vmx->nested.pi_pending = true;
4982                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4983                 return 0;
4984         }
4985         return -1;
4986 }
4987 /*
4988  * Send interrupt to vcpu via posted interrupt way.
4989  * 1. If target vcpu is running(non-root mode), send posted interrupt
4990  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4991  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4992  * interrupt from PIR in next vmentry.
4993  */
4994 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4995 {
4996         struct vcpu_vmx *vmx = to_vmx(vcpu);
4997         int r;
4998
4999         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
5000         if (!r)
5001                 return;
5002
5003         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
5004                 return;
5005
5006         /* If a previous notification has sent the IPI, nothing to do.  */
5007         if (pi_test_and_set_on(&vmx->pi_desc))
5008                 return;
5009
5010         if (!kvm_vcpu_trigger_posted_interrupt(vcpu))
5011                 kvm_vcpu_kick(vcpu);
5012 }
5013
5014 /*
5015  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5016  * will not change in the lifetime of the guest.
5017  * Note that host-state that does change is set elsewhere. E.g., host-state
5018  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5019  */
5020 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
5021 {
5022         u32 low32, high32;
5023         unsigned long tmpl;
5024         struct desc_ptr dt;
5025         unsigned long cr0, cr3, cr4;
5026
5027         cr0 = read_cr0();
5028         WARN_ON(cr0 & X86_CR0_TS);
5029         vmcs_writel(HOST_CR0, cr0);  /* 22.2.3 */
5030
5031         /*
5032          * Save the most likely value for this task's CR3 in the VMCS.
5033          * We can't use __get_current_cr3_fast() because we're not atomic.
5034          */
5035         cr3 = __read_cr3();
5036         vmcs_writel(HOST_CR3, cr3);             /* 22.2.3  FIXME: shadow tables */
5037         vmx->host_state.vmcs_host_cr3 = cr3;
5038
5039         /* Save the most likely value for this task's CR4 in the VMCS. */
5040         cr4 = cr4_read_shadow();
5041         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
5042         vmx->host_state.vmcs_host_cr4 = cr4;
5043
5044         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
5045 #ifdef CONFIG_X86_64
5046         /*
5047          * Load null selectors, so we can avoid reloading them in
5048          * __vmx_load_host_state(), in case userspace uses the null selectors
5049          * too (the expected case).
5050          */
5051         vmcs_write16(HOST_DS_SELECTOR, 0);
5052         vmcs_write16(HOST_ES_SELECTOR, 0);
5053 #else
5054         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5055         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5056 #endif
5057         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
5058         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
5059
5060         native_store_idt(&dt);
5061         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
5062         vmx->host_idt_base = dt.address;
5063
5064         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
5065
5066         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
5067         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
5068         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
5069         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
5070
5071         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
5072                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
5073                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
5074         }
5075 }
5076
5077 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
5078 {
5079         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
5080         if (enable_ept)
5081                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
5082         if (is_guest_mode(&vmx->vcpu))
5083                 vmx->vcpu.arch.cr4_guest_owned_bits &=
5084                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
5085         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
5086 }
5087
5088 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
5089 {
5090         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
5091
5092         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5093                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
5094         /* Enable the preemption timer dynamically */
5095         pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
5096         return pin_based_exec_ctrl;
5097 }
5098
5099 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
5100 {
5101         struct vcpu_vmx *vmx = to_vmx(vcpu);
5102
5103         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5104         if (cpu_has_secondary_exec_ctrls()) {
5105                 if (kvm_vcpu_apicv_active(vcpu))
5106                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
5107                                       SECONDARY_EXEC_APIC_REGISTER_VIRT |
5108                                       SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5109                 else
5110                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
5111                                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
5112                                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5113         }
5114
5115         if (cpu_has_vmx_msr_bitmap())
5116                 vmx_set_msr_bitmap(vcpu);
5117 }
5118
5119 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
5120 {
5121         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
5122
5123         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
5124                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5125
5126         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
5127                 exec_control &= ~CPU_BASED_TPR_SHADOW;
5128 #ifdef CONFIG_X86_64
5129                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
5130                                 CPU_BASED_CR8_LOAD_EXITING;
5131 #endif
5132         }
5133         if (!enable_ept)
5134                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
5135                                 CPU_BASED_CR3_LOAD_EXITING  |
5136                                 CPU_BASED_INVLPG_EXITING;
5137         return exec_control;
5138 }
5139
5140 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
5141 {
5142         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
5143         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
5144                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5145         if (vmx->vpid == 0)
5146                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
5147         if (!enable_ept) {
5148                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
5149                 enable_unrestricted_guest = 0;
5150                 /* Enable INVPCID for non-ept guests may cause performance regression. */
5151                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
5152         }
5153         if (!enable_unrestricted_guest)
5154                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
5155         if (!ple_gap)
5156                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
5157         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
5158                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
5159                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
5160         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5161         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5162            (handle_vmptrld).
5163            We can NOT enable shadow_vmcs here because we don't have yet
5164            a current VMCS12
5165         */
5166         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5167
5168         if (!enable_pml)
5169                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
5170
5171         return exec_control;
5172 }
5173
5174 static void ept_set_mmio_spte_mask(void)
5175 {
5176         /*
5177          * EPT Misconfigurations can be generated if the value of bits 2:0
5178          * of an EPT paging-structure entry is 110b (write/execute).
5179          */
5180         kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
5181                                    VMX_EPT_MISCONFIG_WX_VALUE);
5182 }
5183
5184 #define VMX_XSS_EXIT_BITMAP 0
5185 /*
5186  * Sets up the vmcs for emulated real mode.
5187  */
5188 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
5189 {
5190 #ifdef CONFIG_X86_64
5191         unsigned long a;
5192 #endif
5193         int i;
5194
5195         /* I/O */
5196         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
5197         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
5198
5199         if (enable_shadow_vmcs) {
5200                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
5201                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
5202         }
5203         if (cpu_has_vmx_msr_bitmap())
5204                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
5205
5206         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
5207
5208         /* Control */
5209         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
5210         vmx->hv_deadline_tsc = -1;
5211
5212         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
5213
5214         if (cpu_has_secondary_exec_ctrls()) {
5215                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5216                                 vmx_secondary_exec_control(vmx));
5217         }
5218
5219         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
5220                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
5221                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
5222                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
5223                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
5224
5225                 vmcs_write16(GUEST_INTR_STATUS, 0);
5226
5227                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
5228                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
5229         }
5230
5231         if (ple_gap) {
5232                 vmcs_write32(PLE_GAP, ple_gap);
5233                 vmx->ple_window = ple_window;
5234                 vmx->ple_window_dirty = true;
5235         }
5236
5237         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
5238         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
5239         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
5240
5241         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
5242         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
5243         vmx_set_constant_host_state(vmx);
5244 #ifdef CONFIG_X86_64
5245         rdmsrl(MSR_FS_BASE, a);
5246         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
5247         rdmsrl(MSR_GS_BASE, a);
5248         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
5249 #else
5250         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
5251         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
5252 #endif
5253
5254         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
5255         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
5256         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
5257         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
5258         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
5259
5260         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
5261                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
5262
5263         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
5264                 u32 index = vmx_msr_index[i];
5265                 u32 data_low, data_high;
5266                 int j = vmx->nmsrs;
5267
5268                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
5269                         continue;
5270                 if (wrmsr_safe(index, data_low, data_high) < 0)
5271                         continue;
5272                 vmx->guest_msrs[j].index = i;
5273                 vmx->guest_msrs[j].data = 0;
5274                 vmx->guest_msrs[j].mask = -1ull;
5275                 ++vmx->nmsrs;
5276         }
5277
5278
5279         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
5280
5281         /* 22.2.1, 20.8.1 */
5282         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
5283
5284         vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
5285         vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
5286
5287         set_cr4_guest_host_mask(vmx);
5288
5289         if (vmx_xsaves_supported())
5290                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
5291
5292         if (enable_pml) {
5293                 ASSERT(vmx->pml_pg);
5294                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
5295                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
5296         }
5297
5298         return 0;
5299 }
5300
5301 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
5302 {
5303         struct vcpu_vmx *vmx = to_vmx(vcpu);
5304         struct msr_data apic_base_msr;
5305         u64 cr0;
5306
5307         vmx->rmode.vm86_active = 0;
5308
5309         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
5310         kvm_set_cr8(vcpu, 0);
5311
5312         if (!init_event) {
5313                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
5314                                      MSR_IA32_APICBASE_ENABLE;
5315                 if (kvm_vcpu_is_reset_bsp(vcpu))
5316                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
5317                 apic_base_msr.host_initiated = true;
5318                 kvm_set_apic_base(vcpu, &apic_base_msr);
5319         }
5320
5321         vmx_segment_cache_clear(vmx);
5322
5323         seg_setup(VCPU_SREG_CS);
5324         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
5325         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
5326
5327         seg_setup(VCPU_SREG_DS);
5328         seg_setup(VCPU_SREG_ES);
5329         seg_setup(VCPU_SREG_FS);
5330         seg_setup(VCPU_SREG_GS);
5331         seg_setup(VCPU_SREG_SS);
5332
5333         vmcs_write16(GUEST_TR_SELECTOR, 0);
5334         vmcs_writel(GUEST_TR_BASE, 0);
5335         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
5336         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
5337
5338         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
5339         vmcs_writel(GUEST_LDTR_BASE, 0);
5340         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5341         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5342
5343         if (!init_event) {
5344                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5345                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5346                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5347                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5348         }
5349
5350         vmcs_writel(GUEST_RFLAGS, 0x02);
5351         kvm_rip_write(vcpu, 0xfff0);
5352
5353         vmcs_writel(GUEST_GDTR_BASE, 0);
5354         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5355
5356         vmcs_writel(GUEST_IDTR_BASE, 0);
5357         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5358
5359         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5360         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5361         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5362
5363         setup_msrs(vmx);
5364
5365         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5366
5367         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5368                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5369                 if (cpu_need_tpr_shadow(vcpu))
5370                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5371                                      __pa(vcpu->arch.apic->regs));
5372                 vmcs_write32(TPR_THRESHOLD, 0);
5373         }
5374
5375         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5376
5377         if (kvm_vcpu_apicv_active(vcpu))
5378                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5379
5380         if (vmx->vpid != 0)
5381                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5382
5383         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5384         vmx->vcpu.arch.cr0 = cr0;
5385         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5386         vmx_set_cr4(vcpu, 0);
5387         vmx_set_efer(vcpu, 0);
5388
5389         update_exception_bitmap(vcpu);
5390
5391         vpid_sync_context(vmx->vpid);
5392 }
5393
5394 /*
5395  * In nested virtualization, check if L1 asked to exit on external interrupts.
5396  * For most existing hypervisors, this will always return true.
5397  */
5398 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5399 {
5400         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5401                 PIN_BASED_EXT_INTR_MASK;
5402 }
5403
5404 /*
5405  * In nested virtualization, check if L1 has set
5406  * VM_EXIT_ACK_INTR_ON_EXIT
5407  */
5408 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5409 {
5410         return get_vmcs12(vcpu)->vm_exit_controls &
5411                 VM_EXIT_ACK_INTR_ON_EXIT;
5412 }
5413
5414 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5415 {
5416         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5417                 PIN_BASED_NMI_EXITING;
5418 }
5419
5420 static void enable_irq_window(struct kvm_vcpu *vcpu)
5421 {
5422         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5423                       CPU_BASED_VIRTUAL_INTR_PENDING);
5424 }
5425
5426 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5427 {
5428         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5429                 enable_irq_window(vcpu);
5430                 return;
5431         }
5432
5433         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
5434                       CPU_BASED_VIRTUAL_NMI_PENDING);
5435 }
5436
5437 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5438 {
5439         struct vcpu_vmx *vmx = to_vmx(vcpu);
5440         uint32_t intr;
5441         int irq = vcpu->arch.interrupt.nr;
5442
5443         trace_kvm_inj_virq(irq);
5444
5445         ++vcpu->stat.irq_injections;
5446         if (vmx->rmode.vm86_active) {
5447                 int inc_eip = 0;
5448                 if (vcpu->arch.interrupt.soft)
5449                         inc_eip = vcpu->arch.event_exit_inst_len;
5450                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5451                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5452                 return;
5453         }
5454         intr = irq | INTR_INFO_VALID_MASK;
5455         if (vcpu->arch.interrupt.soft) {
5456                 intr |= INTR_TYPE_SOFT_INTR;
5457                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5458                              vmx->vcpu.arch.event_exit_inst_len);
5459         } else
5460                 intr |= INTR_TYPE_EXT_INTR;
5461         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5462 }
5463
5464 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5465 {
5466         struct vcpu_vmx *vmx = to_vmx(vcpu);
5467
5468         if (!is_guest_mode(vcpu)) {
5469                 ++vcpu->stat.nmi_injections;
5470                 vmx->nmi_known_unmasked = false;
5471         }
5472
5473         if (vmx->rmode.vm86_active) {
5474                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5475                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5476                 return;
5477         }
5478
5479         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5480                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5481 }
5482
5483 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5484 {
5485         if (to_vmx(vcpu)->nmi_known_unmasked)
5486                 return false;
5487         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5488 }
5489
5490 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5491 {
5492         struct vcpu_vmx *vmx = to_vmx(vcpu);
5493
5494         vmx->nmi_known_unmasked = !masked;
5495         if (masked)
5496                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5497                               GUEST_INTR_STATE_NMI);
5498         else
5499                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5500                                 GUEST_INTR_STATE_NMI);
5501 }
5502
5503 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5504 {
5505         if (to_vmx(vcpu)->nested.nested_run_pending)
5506                 return 0;
5507
5508         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5509                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5510                    | GUEST_INTR_STATE_NMI));
5511 }
5512
5513 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5514 {
5515         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5516                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5517                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5518                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5519 }
5520
5521 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5522 {
5523         int ret;
5524
5525         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5526                                     PAGE_SIZE * 3);
5527         if (ret)
5528                 return ret;
5529         kvm->arch.tss_addr = addr;
5530         return init_rmode_tss(kvm);
5531 }
5532
5533 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5534 {
5535         switch (vec) {
5536         case BP_VECTOR:
5537                 /*
5538                  * Update instruction length as we may reinject the exception
5539                  * from user space while in guest debugging mode.
5540                  */
5541                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5542                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5543                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5544                         return false;
5545                 /* fall through */
5546         case DB_VECTOR:
5547                 if (vcpu->guest_debug &
5548                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5549                         return false;
5550                 /* fall through */
5551         case DE_VECTOR:
5552         case OF_VECTOR:
5553         case BR_VECTOR:
5554         case UD_VECTOR:
5555         case DF_VECTOR:
5556         case SS_VECTOR:
5557         case GP_VECTOR:
5558         case MF_VECTOR:
5559                 return true;
5560         break;
5561         }
5562         return false;
5563 }
5564
5565 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5566                                   int vec, u32 err_code)
5567 {
5568         /*
5569          * Instruction with address size override prefix opcode 0x67
5570          * Cause the #SS fault with 0 error code in VM86 mode.
5571          */
5572         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5573                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5574                         if (vcpu->arch.halt_request) {
5575                                 vcpu->arch.halt_request = 0;
5576                                 return kvm_vcpu_halt(vcpu);
5577                         }
5578                         return 1;
5579                 }
5580                 return 0;
5581         }
5582
5583         /*
5584          * Forward all other exceptions that are valid in real mode.
5585          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5586          *        the required debugging infrastructure rework.
5587          */
5588         kvm_queue_exception(vcpu, vec);
5589         return 1;
5590 }
5591
5592 /*
5593  * Trigger machine check on the host. We assume all the MSRs are already set up
5594  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5595  * We pass a fake environment to the machine check handler because we want
5596  * the guest to be always treated like user space, no matter what context
5597  * it used internally.
5598  */
5599 static void kvm_machine_check(void)
5600 {
5601 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5602         struct pt_regs regs = {
5603                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5604                 .flags = X86_EFLAGS_IF,
5605         };
5606
5607         do_machine_check(&regs, 0);
5608 #endif
5609 }
5610
5611 static int handle_machine_check(struct kvm_vcpu *vcpu)
5612 {
5613         /* already handled by vcpu_run */
5614         return 1;
5615 }
5616
5617 static int handle_exception(struct kvm_vcpu *vcpu)
5618 {
5619         struct vcpu_vmx *vmx = to_vmx(vcpu);
5620         struct kvm_run *kvm_run = vcpu->run;
5621         u32 intr_info, ex_no, error_code;
5622         unsigned long cr2, rip, dr6;
5623         u32 vect_info;
5624         enum emulation_result er;
5625
5626         vect_info = vmx->idt_vectoring_info;
5627         intr_info = vmx->exit_intr_info;
5628
5629         if (is_machine_check(intr_info))
5630                 return handle_machine_check(vcpu);
5631
5632         if (is_nmi(intr_info))
5633                 return 1;  /* already handled by vmx_vcpu_run() */
5634
5635         if (is_invalid_opcode(intr_info)) {
5636                 if (is_guest_mode(vcpu)) {
5637                         kvm_queue_exception(vcpu, UD_VECTOR);
5638                         return 1;
5639                 }
5640                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5641                 if (er != EMULATE_DONE)
5642                         kvm_queue_exception(vcpu, UD_VECTOR);
5643                 return 1;
5644         }
5645
5646         error_code = 0;
5647         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5648                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5649
5650         /*
5651          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5652          * MMIO, it is better to report an internal error.
5653          * See the comments in vmx_handle_exit.
5654          */
5655         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5656             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5657                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5658                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5659                 vcpu->run->internal.ndata = 3;
5660                 vcpu->run->internal.data[0] = vect_info;
5661                 vcpu->run->internal.data[1] = intr_info;
5662                 vcpu->run->internal.data[2] = error_code;
5663                 return 0;
5664         }
5665
5666         if (is_page_fault(intr_info)) {
5667                 /* EPT won't cause page fault directly */
5668                 BUG_ON(enable_ept);
5669                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5670                 trace_kvm_page_fault(cr2, error_code);
5671
5672                 if (kvm_event_needs_reinjection(vcpu))
5673                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5674                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5675         }
5676
5677         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5678
5679         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5680                 return handle_rmode_exception(vcpu, ex_no, error_code);
5681
5682         switch (ex_no) {
5683         case AC_VECTOR:
5684                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5685                 return 1;
5686         case DB_VECTOR:
5687                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5688                 if (!(vcpu->guest_debug &
5689                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5690                         vcpu->arch.dr6 &= ~15;
5691                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5692                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5693                                 skip_emulated_instruction(vcpu);
5694
5695                         kvm_queue_exception(vcpu, DB_VECTOR);
5696                         return 1;
5697                 }
5698                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5699                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5700                 /* fall through */
5701         case BP_VECTOR:
5702                 /*
5703                  * Update instruction length as we may reinject #BP from
5704                  * user space while in guest debugging mode. Reading it for
5705                  * #DB as well causes no harm, it is not used in that case.
5706                  */
5707                 vmx->vcpu.arch.event_exit_inst_len =
5708                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5709                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5710                 rip = kvm_rip_read(vcpu);
5711                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5712                 kvm_run->debug.arch.exception = ex_no;
5713                 break;
5714         default:
5715                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5716                 kvm_run->ex.exception = ex_no;
5717                 kvm_run->ex.error_code = error_code;
5718                 break;
5719         }
5720         return 0;
5721 }
5722
5723 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5724 {
5725         ++vcpu->stat.irq_exits;
5726         return 1;
5727 }
5728
5729 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5730 {
5731         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5732         return 0;
5733 }
5734
5735 static int handle_io(struct kvm_vcpu *vcpu)
5736 {
5737         unsigned long exit_qualification;
5738         int size, in, string, ret;
5739         unsigned port;
5740
5741         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5742         string = (exit_qualification & 16) != 0;
5743         in = (exit_qualification & 8) != 0;
5744
5745         ++vcpu->stat.io_exits;
5746
5747         if (string || in)
5748                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5749
5750         port = exit_qualification >> 16;
5751         size = (exit_qualification & 7) + 1;
5752
5753         ret = kvm_skip_emulated_instruction(vcpu);
5754
5755         /*
5756          * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5757          * KVM_EXIT_DEBUG here.
5758          */
5759         return kvm_fast_pio_out(vcpu, size, port) && ret;
5760 }
5761
5762 static void
5763 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5764 {
5765         /*
5766          * Patch in the VMCALL instruction:
5767          */
5768         hypercall[0] = 0x0f;
5769         hypercall[1] = 0x01;
5770         hypercall[2] = 0xc1;
5771 }
5772
5773 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5774 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5775 {
5776         if (is_guest_mode(vcpu)) {
5777                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5778                 unsigned long orig_val = val;
5779
5780                 /*
5781                  * We get here when L2 changed cr0 in a way that did not change
5782                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5783                  * but did change L0 shadowed bits. So we first calculate the
5784                  * effective cr0 value that L1 would like to write into the
5785                  * hardware. It consists of the L2-owned bits from the new
5786                  * value combined with the L1-owned bits from L1's guest_cr0.
5787                  */
5788                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5789                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5790
5791                 if (!nested_guest_cr0_valid(vcpu, val))
5792                         return 1;
5793
5794                 if (kvm_set_cr0(vcpu, val))
5795                         return 1;
5796                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5797                 return 0;
5798         } else {
5799                 if (to_vmx(vcpu)->nested.vmxon &&
5800                     !nested_host_cr0_valid(vcpu, val))
5801                         return 1;
5802
5803                 return kvm_set_cr0(vcpu, val);
5804         }
5805 }
5806
5807 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5808 {
5809         if (is_guest_mode(vcpu)) {
5810                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5811                 unsigned long orig_val = val;
5812
5813                 /* analogously to handle_set_cr0 */
5814                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5815                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5816                 if (kvm_set_cr4(vcpu, val))
5817                         return 1;
5818                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5819                 return 0;
5820         } else
5821                 return kvm_set_cr4(vcpu, val);
5822 }
5823
5824 static int handle_cr(struct kvm_vcpu *vcpu)
5825 {
5826         unsigned long exit_qualification, val;
5827         int cr;
5828         int reg;
5829         int err;
5830         int ret;
5831
5832         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5833         cr = exit_qualification & 15;
5834         reg = (exit_qualification >> 8) & 15;
5835         switch ((exit_qualification >> 4) & 3) {
5836         case 0: /* mov to cr */
5837                 val = kvm_register_readl(vcpu, reg);
5838                 trace_kvm_cr_write(cr, val);
5839                 switch (cr) {
5840                 case 0:
5841                         err = handle_set_cr0(vcpu, val);
5842                         return kvm_complete_insn_gp(vcpu, err);
5843                 case 3:
5844                         err = kvm_set_cr3(vcpu, val);
5845                         return kvm_complete_insn_gp(vcpu, err);
5846                 case 4:
5847                         err = handle_set_cr4(vcpu, val);
5848                         return kvm_complete_insn_gp(vcpu, err);
5849                 case 8: {
5850                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5851                                 u8 cr8 = (u8)val;
5852                                 err = kvm_set_cr8(vcpu, cr8);
5853                                 ret = kvm_complete_insn_gp(vcpu, err);
5854                                 if (lapic_in_kernel(vcpu))
5855                                         return ret;
5856                                 if (cr8_prev <= cr8)
5857                                         return ret;
5858                                 /*
5859                                  * TODO: we might be squashing a
5860                                  * KVM_GUESTDBG_SINGLESTEP-triggered
5861                                  * KVM_EXIT_DEBUG here.
5862                                  */
5863                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5864                                 return 0;
5865                         }
5866                 }
5867                 break;
5868         case 2: /* clts */
5869                 WARN_ONCE(1, "Guest should always own CR0.TS");
5870                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5871                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5872                 return kvm_skip_emulated_instruction(vcpu);
5873         case 1: /*mov from cr*/
5874                 switch (cr) {
5875                 case 3:
5876                         val = kvm_read_cr3(vcpu);
5877                         kvm_register_write(vcpu, reg, val);
5878                         trace_kvm_cr_read(cr, val);
5879                         return kvm_skip_emulated_instruction(vcpu);
5880                 case 8:
5881                         val = kvm_get_cr8(vcpu);
5882                         kvm_register_write(vcpu, reg, val);
5883                         trace_kvm_cr_read(cr, val);
5884                         return kvm_skip_emulated_instruction(vcpu);
5885                 }
5886                 break;
5887         case 3: /* lmsw */
5888                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5889                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5890                 kvm_lmsw(vcpu, val);
5891
5892                 return kvm_skip_emulated_instruction(vcpu);
5893         default:
5894                 break;
5895         }
5896         vcpu->run->exit_reason = 0;
5897         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5898                (int)(exit_qualification >> 4) & 3, cr);
5899         return 0;
5900 }
5901
5902 static int handle_dr(struct kvm_vcpu *vcpu)
5903 {
5904         unsigned long exit_qualification;
5905         int dr, dr7, reg;
5906
5907         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5908         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5909
5910         /* First, if DR does not exist, trigger UD */
5911         if (!kvm_require_dr(vcpu, dr))
5912                 return 1;
5913
5914         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5915         if (!kvm_require_cpl(vcpu, 0))
5916                 return 1;
5917         dr7 = vmcs_readl(GUEST_DR7);
5918         if (dr7 & DR7_GD) {
5919                 /*
5920                  * As the vm-exit takes precedence over the debug trap, we
5921                  * need to emulate the latter, either for the host or the
5922                  * guest debugging itself.
5923                  */
5924                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5925                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5926                         vcpu->run->debug.arch.dr7 = dr7;
5927                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5928                         vcpu->run->debug.arch.exception = DB_VECTOR;
5929                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5930                         return 0;
5931                 } else {
5932                         vcpu->arch.dr6 &= ~15;
5933                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5934                         kvm_queue_exception(vcpu, DB_VECTOR);
5935                         return 1;
5936                 }
5937         }
5938
5939         if (vcpu->guest_debug == 0) {
5940                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5941                                 CPU_BASED_MOV_DR_EXITING);
5942
5943                 /*
5944                  * No more DR vmexits; force a reload of the debug registers
5945                  * and reenter on this instruction.  The next vmexit will
5946                  * retrieve the full state of the debug registers.
5947                  */
5948                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5949                 return 1;
5950         }
5951
5952         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5953         if (exit_qualification & TYPE_MOV_FROM_DR) {
5954                 unsigned long val;
5955
5956                 if (kvm_get_dr(vcpu, dr, &val))
5957                         return 1;
5958                 kvm_register_write(vcpu, reg, val);
5959         } else
5960                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5961                         return 1;
5962
5963         return kvm_skip_emulated_instruction(vcpu);
5964 }
5965
5966 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5967 {
5968         return vcpu->arch.dr6;
5969 }
5970
5971 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5972 {
5973 }
5974
5975 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5976 {
5977         get_debugreg(vcpu->arch.db[0], 0);
5978         get_debugreg(vcpu->arch.db[1], 1);
5979         get_debugreg(vcpu->arch.db[2], 2);
5980         get_debugreg(vcpu->arch.db[3], 3);
5981         get_debugreg(vcpu->arch.dr6, 6);
5982         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5983
5984         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5985         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5986 }
5987
5988 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5989 {
5990         vmcs_writel(GUEST_DR7, val);
5991 }
5992
5993 static int handle_cpuid(struct kvm_vcpu *vcpu)
5994 {
5995         return kvm_emulate_cpuid(vcpu);
5996 }
5997
5998 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5999 {
6000         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6001         struct msr_data msr_info;
6002
6003         msr_info.index = ecx;
6004         msr_info.host_initiated = false;
6005         if (vmx_get_msr(vcpu, &msr_info)) {
6006                 trace_kvm_msr_read_ex(ecx);
6007                 kvm_inject_gp(vcpu, 0);
6008                 return 1;
6009         }
6010
6011         trace_kvm_msr_read(ecx, msr_info.data);
6012
6013         /* FIXME: handling of bits 32:63 of rax, rdx */
6014         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
6015         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6016         return kvm_skip_emulated_instruction(vcpu);
6017 }
6018
6019 static int handle_wrmsr(struct kvm_vcpu *vcpu)
6020 {
6021         struct msr_data msr;
6022         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6023         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
6024                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6025
6026         msr.data = data;
6027         msr.index = ecx;
6028         msr.host_initiated = false;
6029         if (kvm_set_msr(vcpu, &msr) != 0) {
6030                 trace_kvm_msr_write_ex(ecx, data);
6031                 kvm_inject_gp(vcpu, 0);
6032                 return 1;
6033         }
6034
6035         trace_kvm_msr_write(ecx, data);
6036         return kvm_skip_emulated_instruction(vcpu);
6037 }
6038
6039 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6040 {
6041         kvm_apic_update_ppr(vcpu);
6042         return 1;
6043 }
6044
6045 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6046 {
6047         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6048                         CPU_BASED_VIRTUAL_INTR_PENDING);
6049
6050         kvm_make_request(KVM_REQ_EVENT, vcpu);
6051
6052         ++vcpu->stat.irq_window_exits;
6053         return 1;
6054 }
6055
6056 static int handle_halt(struct kvm_vcpu *vcpu)
6057 {
6058         return kvm_emulate_halt(vcpu);
6059 }
6060
6061 static int handle_vmcall(struct kvm_vcpu *vcpu)
6062 {
6063         return kvm_emulate_hypercall(vcpu);
6064 }
6065
6066 static int handle_invd(struct kvm_vcpu *vcpu)
6067 {
6068         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6069 }
6070
6071 static int handle_invlpg(struct kvm_vcpu *vcpu)
6072 {
6073         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6074
6075         kvm_mmu_invlpg(vcpu, exit_qualification);
6076         return kvm_skip_emulated_instruction(vcpu);
6077 }
6078
6079 static int handle_rdpmc(struct kvm_vcpu *vcpu)
6080 {
6081         int err;
6082
6083         err = kvm_rdpmc(vcpu);
6084         return kvm_complete_insn_gp(vcpu, err);
6085 }
6086
6087 static int handle_wbinvd(struct kvm_vcpu *vcpu)
6088 {
6089         return kvm_emulate_wbinvd(vcpu);
6090 }
6091
6092 static int handle_xsetbv(struct kvm_vcpu *vcpu)
6093 {
6094         u64 new_bv = kvm_read_edx_eax(vcpu);
6095         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
6096
6097         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6098                 return kvm_skip_emulated_instruction(vcpu);
6099         return 1;
6100 }
6101
6102 static int handle_xsaves(struct kvm_vcpu *vcpu)
6103 {
6104         kvm_skip_emulated_instruction(vcpu);
6105         WARN(1, "this should never happen\n");
6106         return 1;
6107 }
6108
6109 static int handle_xrstors(struct kvm_vcpu *vcpu)
6110 {
6111         kvm_skip_emulated_instruction(vcpu);
6112         WARN(1, "this should never happen\n");
6113         return 1;
6114 }
6115
6116 static int handle_apic_access(struct kvm_vcpu *vcpu)
6117 {
6118         if (likely(fasteoi)) {
6119                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6120                 int access_type, offset;
6121
6122                 access_type = exit_qualification & APIC_ACCESS_TYPE;
6123                 offset = exit_qualification & APIC_ACCESS_OFFSET;
6124                 /*
6125                  * Sane guest uses MOV to write EOI, with written value
6126                  * not cared. So make a short-circuit here by avoiding
6127                  * heavy instruction emulation.
6128                  */
6129                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
6130                     (offset == APIC_EOI)) {
6131                         kvm_lapic_set_eoi(vcpu);
6132                         return kvm_skip_emulated_instruction(vcpu);
6133                 }
6134         }
6135         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
6136 }
6137
6138 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
6139 {
6140         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6141         int vector = exit_qualification & 0xff;
6142
6143         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6144         kvm_apic_set_eoi_accelerated(vcpu, vector);
6145         return 1;
6146 }
6147
6148 static int handle_apic_write(struct kvm_vcpu *vcpu)
6149 {
6150         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6151         u32 offset = exit_qualification & 0xfff;
6152
6153         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6154         kvm_apic_write_nodecode(vcpu, offset);
6155         return 1;
6156 }
6157
6158 static int handle_task_switch(struct kvm_vcpu *vcpu)
6159 {
6160         struct vcpu_vmx *vmx = to_vmx(vcpu);
6161         unsigned long exit_qualification;
6162         bool has_error_code = false;
6163         u32 error_code = 0;
6164         u16 tss_selector;
6165         int reason, type, idt_v, idt_index;
6166
6167         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
6168         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
6169         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
6170
6171         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6172
6173         reason = (u32)exit_qualification >> 30;
6174         if (reason == TASK_SWITCH_GATE && idt_v) {
6175                 switch (type) {
6176                 case INTR_TYPE_NMI_INTR:
6177                         vcpu->arch.nmi_injected = false;
6178                         vmx_set_nmi_mask(vcpu, true);
6179                         break;
6180                 case INTR_TYPE_EXT_INTR:
6181                 case INTR_TYPE_SOFT_INTR:
6182                         kvm_clear_interrupt_queue(vcpu);
6183                         break;
6184                 case INTR_TYPE_HARD_EXCEPTION:
6185                         if (vmx->idt_vectoring_info &
6186                             VECTORING_INFO_DELIVER_CODE_MASK) {
6187                                 has_error_code = true;
6188                                 error_code =
6189                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
6190                         }
6191                         /* fall through */
6192                 case INTR_TYPE_SOFT_EXCEPTION:
6193                         kvm_clear_exception_queue(vcpu);
6194                         break;
6195                 default:
6196                         break;
6197                 }
6198         }
6199         tss_selector = exit_qualification;
6200
6201         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
6202                        type != INTR_TYPE_EXT_INTR &&
6203                        type != INTR_TYPE_NMI_INTR))
6204                 skip_emulated_instruction(vcpu);
6205
6206         if (kvm_task_switch(vcpu, tss_selector,
6207                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
6208                             has_error_code, error_code) == EMULATE_FAIL) {
6209                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6210                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6211                 vcpu->run->internal.ndata = 0;
6212                 return 0;
6213         }
6214
6215         /*
6216          * TODO: What about debug traps on tss switch?
6217          *       Are we supposed to inject them and update dr6?
6218          */
6219
6220         return 1;
6221 }
6222
6223 static int handle_ept_violation(struct kvm_vcpu *vcpu)
6224 {
6225         unsigned long exit_qualification;
6226         gpa_t gpa;
6227         u32 error_code;
6228
6229         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6230
6231         /*
6232          * EPT violation happened while executing iret from NMI,
6233          * "blocked by NMI" bit has to be set before next VM entry.
6234          * There are errata that may cause this bit to not be set:
6235          * AAK134, BY25.
6236          */
6237         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
6238                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
6239                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
6240
6241         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6242         trace_kvm_page_fault(gpa, exit_qualification);
6243
6244         /* Is it a read fault? */
6245         error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
6246                      ? PFERR_USER_MASK : 0;
6247         /* Is it a write fault? */
6248         error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
6249                       ? PFERR_WRITE_MASK : 0;
6250         /* Is it a fetch fault? */
6251         error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
6252                       ? PFERR_FETCH_MASK : 0;
6253         /* ept page table entry is present? */
6254         error_code |= (exit_qualification &
6255                        (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
6256                         EPT_VIOLATION_EXECUTABLE))
6257                       ? PFERR_PRESENT_MASK : 0;
6258
6259         vcpu->arch.gpa_available = true;
6260         vcpu->arch.exit_qualification = exit_qualification;
6261
6262         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6263 }
6264
6265 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6266 {
6267         int ret;
6268         gpa_t gpa;
6269
6270         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6271         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6272                 trace_kvm_fast_mmio(gpa);
6273                 return kvm_skip_emulated_instruction(vcpu);
6274         }
6275
6276         ret = handle_mmio_page_fault(vcpu, gpa, true);
6277         vcpu->arch.gpa_available = true;
6278         if (likely(ret == RET_MMIO_PF_EMULATE))
6279                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6280                                               EMULATE_DONE;
6281
6282         if (unlikely(ret == RET_MMIO_PF_INVALID))
6283                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6284
6285         if (unlikely(ret == RET_MMIO_PF_RETRY))
6286                 return 1;
6287
6288         /* It is the real ept misconfig */
6289         WARN_ON(1);
6290
6291         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6292         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6293
6294         return 0;
6295 }
6296
6297 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6298 {
6299         vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
6300                         CPU_BASED_VIRTUAL_NMI_PENDING);
6301         ++vcpu->stat.nmi_window_exits;
6302         kvm_make_request(KVM_REQ_EVENT, vcpu);
6303
6304         return 1;
6305 }
6306
6307 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6308 {
6309         struct vcpu_vmx *vmx = to_vmx(vcpu);
6310         enum emulation_result err = EMULATE_DONE;
6311         int ret = 1;
6312         u32 cpu_exec_ctrl;
6313         bool intr_window_requested;
6314         unsigned count = 130;
6315
6316         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6317         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6318
6319         while (vmx->emulation_required && count-- != 0) {
6320                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6321                         return handle_interrupt_window(&vmx->vcpu);
6322
6323                 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
6324                         return 1;
6325
6326                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6327
6328                 if (err == EMULATE_USER_EXIT) {
6329                         ++vcpu->stat.mmio_exits;
6330                         ret = 0;
6331                         goto out;
6332                 }
6333
6334                 if (err != EMULATE_DONE) {
6335                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6336                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6337                         vcpu->run->internal.ndata = 0;
6338                         return 0;
6339                 }
6340
6341                 if (vcpu->arch.halt_request) {
6342                         vcpu->arch.halt_request = 0;
6343                         ret = kvm_vcpu_halt(vcpu);
6344                         goto out;
6345                 }
6346
6347                 if (signal_pending(current))
6348                         goto out;
6349                 if (need_resched())
6350                         schedule();
6351         }
6352
6353 out:
6354         return ret;
6355 }
6356
6357 static int __grow_ple_window(int val)
6358 {
6359         if (ple_window_grow < 1)
6360                 return ple_window;
6361
6362         val = min(val, ple_window_actual_max);
6363
6364         if (ple_window_grow < ple_window)
6365                 val *= ple_window_grow;
6366         else
6367                 val += ple_window_grow;
6368
6369         return val;
6370 }
6371
6372 static int __shrink_ple_window(int val, int modifier, int minimum)
6373 {
6374         if (modifier < 1)
6375                 return ple_window;
6376
6377         if (modifier < ple_window)
6378                 val /= modifier;
6379         else
6380                 val -= modifier;
6381
6382         return max(val, minimum);
6383 }
6384
6385 static void grow_ple_window(struct kvm_vcpu *vcpu)
6386 {
6387         struct vcpu_vmx *vmx = to_vmx(vcpu);
6388         int old = vmx->ple_window;
6389
6390         vmx->ple_window = __grow_ple_window(old);
6391
6392         if (vmx->ple_window != old)
6393                 vmx->ple_window_dirty = true;
6394
6395         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6396 }
6397
6398 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6399 {
6400         struct vcpu_vmx *vmx = to_vmx(vcpu);
6401         int old = vmx->ple_window;
6402
6403         vmx->ple_window = __shrink_ple_window(old,
6404                                               ple_window_shrink, ple_window);
6405
6406         if (vmx->ple_window != old)
6407                 vmx->ple_window_dirty = true;
6408
6409         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6410 }
6411
6412 /*
6413  * ple_window_actual_max is computed to be one grow_ple_window() below
6414  * ple_window_max. (See __grow_ple_window for the reason.)
6415  * This prevents overflows, because ple_window_max is int.
6416  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6417  * this process.
6418  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6419  */
6420 static void update_ple_window_actual_max(void)
6421 {
6422         ple_window_actual_max =
6423                         __shrink_ple_window(max(ple_window_max, ple_window),
6424                                             ple_window_grow, INT_MIN);
6425 }
6426
6427 /*
6428  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6429  */
6430 static void wakeup_handler(void)
6431 {
6432         struct kvm_vcpu *vcpu;
6433         int cpu = smp_processor_id();
6434
6435         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6436         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6437                         blocked_vcpu_list) {
6438                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6439
6440                 if (pi_test_on(pi_desc) == 1)
6441                         kvm_vcpu_kick(vcpu);
6442         }
6443         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6444 }
6445
6446 void vmx_enable_tdp(void)
6447 {
6448         kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
6449                 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
6450                 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
6451                 0ull, VMX_EPT_EXECUTABLE_MASK,
6452                 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
6453                 VMX_EPT_RWX_MASK);
6454
6455         ept_set_mmio_spte_mask();
6456         kvm_enable_tdp();
6457 }
6458
6459 static __init int hardware_setup(void)
6460 {
6461         int r = -ENOMEM, i, msr;
6462
6463         rdmsrl_safe(MSR_EFER, &host_efer);
6464
6465         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6466                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6467
6468         for (i = 0; i < VMX_BITMAP_NR; i++) {
6469                 vmx_bitmap[i] = (unsigned long *)__get_free_page(GFP_KERNEL);
6470                 if (!vmx_bitmap[i])
6471                         goto out;
6472         }
6473
6474         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6475         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6476         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6477
6478         /*
6479          * Allow direct access to the PC debug port (it is often used for I/O
6480          * delays, but the vmexits simply slow things down).
6481          */
6482         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6483         clear_bit(0x80, vmx_io_bitmap_a);
6484
6485         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6486
6487         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6488         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6489
6490         if (setup_vmcs_config(&vmcs_config) < 0) {
6491                 r = -EIO;
6492                 goto out;
6493         }
6494
6495         if (boot_cpu_has(X86_FEATURE_NX))
6496                 kvm_enable_efer_bits(EFER_NX);
6497
6498         if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6499                 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6500                 enable_vpid = 0;
6501
6502         if (!cpu_has_vmx_shadow_vmcs())
6503                 enable_shadow_vmcs = 0;
6504         if (enable_shadow_vmcs)
6505                 init_vmcs_shadow_fields();
6506
6507         if (!cpu_has_vmx_ept() ||
6508             !cpu_has_vmx_ept_4levels()) {
6509                 enable_ept = 0;
6510                 enable_unrestricted_guest = 0;
6511                 enable_ept_ad_bits = 0;
6512         }
6513
6514         if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
6515                 enable_ept_ad_bits = 0;
6516
6517         if (!cpu_has_vmx_unrestricted_guest())
6518                 enable_unrestricted_guest = 0;
6519
6520         if (!cpu_has_vmx_flexpriority())
6521                 flexpriority_enabled = 0;
6522
6523         /*
6524          * set_apic_access_page_addr() is used to reload apic access
6525          * page upon invalidation.  No need to do anything if not
6526          * using the APIC_ACCESS_ADDR VMCS field.
6527          */
6528         if (!flexpriority_enabled)
6529                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6530
6531         if (!cpu_has_vmx_tpr_shadow())
6532                 kvm_x86_ops->update_cr8_intercept = NULL;
6533
6534         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6535                 kvm_disable_largepages();
6536
6537         if (!cpu_has_vmx_ple())
6538                 ple_gap = 0;
6539
6540         if (!cpu_has_vmx_apicv()) {
6541                 enable_apicv = 0;
6542                 kvm_x86_ops->sync_pir_to_irr = NULL;
6543         }
6544
6545         if (cpu_has_vmx_tsc_scaling()) {
6546                 kvm_has_tsc_control = true;
6547                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6548                 kvm_tsc_scaling_ratio_frac_bits = 48;
6549         }
6550
6551         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6552         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6553         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6554         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6555         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6556         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6557
6558         memcpy(vmx_msr_bitmap_legacy_x2apic_apicv,
6559                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6560         memcpy(vmx_msr_bitmap_longmode_x2apic_apicv,
6561                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6562         memcpy(vmx_msr_bitmap_legacy_x2apic,
6563                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6564         memcpy(vmx_msr_bitmap_longmode_x2apic,
6565                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6566
6567         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6568
6569         for (msr = 0x800; msr <= 0x8ff; msr++) {
6570                 if (msr == 0x839 /* TMCCT */)
6571                         continue;
6572                 vmx_disable_intercept_msr_x2apic(msr, MSR_TYPE_R, true);
6573         }
6574
6575         /*
6576          * TPR reads and writes can be virtualized even if virtual interrupt
6577          * delivery is not in use.
6578          */
6579         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W, true);
6580         vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R | MSR_TYPE_W, false);
6581
6582         /* EOI */
6583         vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W, true);
6584         /* SELF-IPI */
6585         vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W, true);
6586
6587         if (enable_ept)
6588                 vmx_enable_tdp();
6589         else
6590                 kvm_disable_tdp();
6591
6592         update_ple_window_actual_max();
6593
6594         /*
6595          * Only enable PML when hardware supports PML feature, and both EPT
6596          * and EPT A/D bit features are enabled -- PML depends on them to work.
6597          */
6598         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6599                 enable_pml = 0;
6600
6601         if (!enable_pml) {
6602                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6603                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6604                 kvm_x86_ops->flush_log_dirty = NULL;
6605                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6606         }
6607
6608         if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
6609                 u64 vmx_msr;
6610
6611                 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
6612                 cpu_preemption_timer_multi =
6613                          vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
6614         } else {
6615                 kvm_x86_ops->set_hv_timer = NULL;
6616                 kvm_x86_ops->cancel_hv_timer = NULL;
6617         }
6618
6619         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6620
6621         kvm_mce_cap_supported |= MCG_LMCE_P;
6622
6623         return alloc_kvm_area();
6624
6625 out:
6626         for (i = 0; i < VMX_BITMAP_NR; i++)
6627                 free_page((unsigned long)vmx_bitmap[i]);
6628
6629     return r;
6630 }
6631
6632 static __exit void hardware_unsetup(void)
6633 {
6634         int i;
6635
6636         for (i = 0; i < VMX_BITMAP_NR; i++)
6637                 free_page((unsigned long)vmx_bitmap[i]);
6638
6639         free_kvm_area();
6640 }
6641
6642 /*
6643  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6644  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6645  */
6646 static int handle_pause(struct kvm_vcpu *vcpu)
6647 {
6648         if (ple_gap)
6649                 grow_ple_window(vcpu);
6650
6651         kvm_vcpu_on_spin(vcpu);
6652         return kvm_skip_emulated_instruction(vcpu);
6653 }
6654
6655 static int handle_nop(struct kvm_vcpu *vcpu)
6656 {
6657         return kvm_skip_emulated_instruction(vcpu);
6658 }
6659
6660 static int handle_mwait(struct kvm_vcpu *vcpu)
6661 {
6662         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6663         return handle_nop(vcpu);
6664 }
6665
6666 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6667 {
6668         return 1;
6669 }
6670
6671 static int handle_monitor(struct kvm_vcpu *vcpu)
6672 {
6673         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6674         return handle_nop(vcpu);
6675 }
6676
6677 /*
6678  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6679  * We could reuse a single VMCS for all the L2 guests, but we also want the
6680  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6681  * allows keeping them loaded on the processor, and in the future will allow
6682  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6683  * every entry if they never change.
6684  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6685  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6686  *
6687  * The following functions allocate and free a vmcs02 in this pool.
6688  */
6689
6690 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6691 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6692 {
6693         struct vmcs02_list *item;
6694         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6695                 if (item->vmptr == vmx->nested.current_vmptr) {
6696                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6697                         return &item->vmcs02;
6698                 }
6699
6700         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6701                 /* Recycle the least recently used VMCS. */
6702                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6703                                        struct vmcs02_list, list);
6704                 item->vmptr = vmx->nested.current_vmptr;
6705                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6706                 return &item->vmcs02;
6707         }
6708
6709         /* Create a new VMCS */
6710         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6711         if (!item)
6712                 return NULL;
6713         item->vmcs02.vmcs = alloc_vmcs();
6714         item->vmcs02.shadow_vmcs = NULL;
6715         if (!item->vmcs02.vmcs) {
6716                 kfree(item);
6717                 return NULL;
6718         }
6719         loaded_vmcs_init(&item->vmcs02);
6720         item->vmptr = vmx->nested.current_vmptr;
6721         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6722         vmx->nested.vmcs02_num++;
6723         return &item->vmcs02;
6724 }
6725
6726 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6727 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6728 {
6729         struct vmcs02_list *item;
6730         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6731                 if (item->vmptr == vmptr) {
6732                         free_loaded_vmcs(&item->vmcs02);
6733                         list_del(&item->list);
6734                         kfree(item);
6735                         vmx->nested.vmcs02_num--;
6736                         return;
6737                 }
6738 }
6739
6740 /*
6741  * Free all VMCSs saved for this vcpu, except the one pointed by
6742  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6743  * must be &vmx->vmcs01.
6744  */
6745 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6746 {
6747         struct vmcs02_list *item, *n;
6748
6749         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6750         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6751                 /*
6752                  * Something will leak if the above WARN triggers.  Better than
6753                  * a use-after-free.
6754                  */
6755                 if (vmx->loaded_vmcs == &item->vmcs02)
6756                         continue;
6757
6758                 free_loaded_vmcs(&item->vmcs02);
6759                 list_del(&item->list);
6760                 kfree(item);
6761                 vmx->nested.vmcs02_num--;
6762         }
6763 }
6764
6765 /*
6766  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6767  * set the success or error code of an emulated VMX instruction, as specified
6768  * by Vol 2B, VMX Instruction Reference, "Conventions".
6769  */
6770 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6771 {
6772         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6773                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6774                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6775 }
6776
6777 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6778 {
6779         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6780                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6781                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6782                         | X86_EFLAGS_CF);
6783 }
6784
6785 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6786                                         u32 vm_instruction_error)
6787 {
6788         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6789                 /*
6790                  * failValid writes the error number to the current VMCS, which
6791                  * can't be done there isn't a current VMCS.
6792                  */
6793                 nested_vmx_failInvalid(vcpu);
6794                 return;
6795         }
6796         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6797                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6798                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6799                         | X86_EFLAGS_ZF);
6800         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6801         /*
6802          * We don't need to force a shadow sync because
6803          * VM_INSTRUCTION_ERROR is not shadowed
6804          */
6805 }
6806
6807 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6808 {
6809         /* TODO: not to reset guest simply here. */
6810         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6811         pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator);
6812 }
6813
6814 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6815 {
6816         struct vcpu_vmx *vmx =
6817                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6818
6819         vmx->nested.preemption_timer_expired = true;
6820         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6821         kvm_vcpu_kick(&vmx->vcpu);
6822
6823         return HRTIMER_NORESTART;
6824 }
6825
6826 /*
6827  * Decode the memory-address operand of a vmx instruction, as recorded on an
6828  * exit caused by such an instruction (run by a guest hypervisor).
6829  * On success, returns 0. When the operand is invalid, returns 1 and throws
6830  * #UD or #GP.
6831  */
6832 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6833                                  unsigned long exit_qualification,
6834                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6835 {
6836         gva_t off;
6837         bool exn;
6838         struct kvm_segment s;
6839
6840         /*
6841          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6842          * Execution", on an exit, vmx_instruction_info holds most of the
6843          * addressing components of the operand. Only the displacement part
6844          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6845          * For how an actual address is calculated from all these components,
6846          * refer to Vol. 1, "Operand Addressing".
6847          */
6848         int  scaling = vmx_instruction_info & 3;
6849         int  addr_size = (vmx_instruction_info >> 7) & 7;
6850         bool is_reg = vmx_instruction_info & (1u << 10);
6851         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6852         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6853         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6854         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6855         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6856
6857         if (is_reg) {
6858                 kvm_queue_exception(vcpu, UD_VECTOR);
6859                 return 1;
6860         }
6861
6862         /* Addr = segment_base + offset */
6863         /* offset = base + [index * scale] + displacement */
6864         off = exit_qualification; /* holds the displacement */
6865         if (base_is_valid)
6866                 off += kvm_register_read(vcpu, base_reg);
6867         if (index_is_valid)
6868                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6869         vmx_get_segment(vcpu, &s, seg_reg);
6870         *ret = s.base + off;
6871
6872         if (addr_size == 1) /* 32 bit */
6873                 *ret &= 0xffffffff;
6874
6875         /* Checks for #GP/#SS exceptions. */
6876         exn = false;
6877         if (is_long_mode(vcpu)) {
6878                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6879                  * non-canonical form. This is the only check on the memory
6880                  * destination for long mode!
6881                  */
6882                 exn = is_noncanonical_address(*ret);
6883         } else if (is_protmode(vcpu)) {
6884                 /* Protected mode: apply checks for segment validity in the
6885                  * following order:
6886                  * - segment type check (#GP(0) may be thrown)
6887                  * - usability check (#GP(0)/#SS(0))
6888                  * - limit check (#GP(0)/#SS(0))
6889                  */
6890                 if (wr)
6891                         /* #GP(0) if the destination operand is located in a
6892                          * read-only data segment or any code segment.
6893                          */
6894                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6895                 else
6896                         /* #GP(0) if the source operand is located in an
6897                          * execute-only code segment
6898                          */
6899                         exn = ((s.type & 0xa) == 8);
6900                 if (exn) {
6901                         kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6902                         return 1;
6903                 }
6904                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6905                  */
6906                 exn = (s.unusable != 0);
6907                 /* Protected mode: #GP(0)/#SS(0) if the memory
6908                  * operand is outside the segment limit.
6909                  */
6910                 exn = exn || (off + sizeof(u64) > s.limit);
6911         }
6912         if (exn) {
6913                 kvm_queue_exception_e(vcpu,
6914                                       seg_reg == VCPU_SREG_SS ?
6915                                                 SS_VECTOR : GP_VECTOR,
6916                                       0);
6917                 return 1;
6918         }
6919
6920         return 0;
6921 }
6922
6923 static int nested_vmx_get_vmptr(struct kvm_vcpu *vcpu, gpa_t *vmpointer)
6924 {
6925         gva_t gva;
6926         struct x86_exception e;
6927
6928         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6929                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6930                 return 1;
6931
6932         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, vmpointer,
6933                                 sizeof(*vmpointer), &e)) {
6934                 kvm_inject_page_fault(vcpu, &e);
6935                 return 1;
6936         }
6937
6938         return 0;
6939 }
6940
6941 static int enter_vmx_operation(struct kvm_vcpu *vcpu)
6942 {
6943         struct vcpu_vmx *vmx = to_vmx(vcpu);
6944         struct vmcs *shadow_vmcs;
6945
6946         if (cpu_has_vmx_msr_bitmap()) {
6947                 vmx->nested.msr_bitmap =
6948                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6949                 if (!vmx->nested.msr_bitmap)
6950                         goto out_msr_bitmap;
6951         }
6952
6953         vmx->nested.cached_vmcs12 = kmalloc(VMCS12_SIZE, GFP_KERNEL);
6954         if (!vmx->nested.cached_vmcs12)
6955                 goto out_cached_vmcs12;
6956
6957         if (enable_shadow_vmcs) {
6958                 shadow_vmcs = alloc_vmcs();
6959                 if (!shadow_vmcs)
6960                         goto out_shadow_vmcs;
6961                 /* mark vmcs as shadow */
6962                 shadow_vmcs->revision_id |= (1u << 31);
6963                 /* init shadow vmcs */
6964                 vmcs_clear(shadow_vmcs);
6965                 vmx->vmcs01.shadow_vmcs = shadow_vmcs;
6966         }
6967
6968         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6969         vmx->nested.vmcs02_num = 0;
6970
6971         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6972                      HRTIMER_MODE_REL_PINNED);
6973         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6974
6975         vmx->nested.vmxon = true;
6976         return 0;
6977
6978 out_shadow_vmcs:
6979         kfree(vmx->nested.cached_vmcs12);
6980
6981 out_cached_vmcs12:
6982         free_page((unsigned long)vmx->nested.msr_bitmap);
6983
6984 out_msr_bitmap:
6985         return -ENOMEM;
6986 }
6987
6988 /*
6989  * Emulate the VMXON instruction.
6990  * Currently, we just remember that VMX is active, and do not save or even
6991  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6992  * do not currently need to store anything in that guest-allocated memory
6993  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6994  * argument is different from the VMXON pointer (which the spec says they do).
6995  */
6996 static int handle_vmon(struct kvm_vcpu *vcpu)
6997 {
6998         int ret;
6999         gpa_t vmptr;
7000         struct page *page;
7001         struct vcpu_vmx *vmx = to_vmx(vcpu);
7002         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
7003                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
7004
7005         /*
7006          * The Intel VMX Instruction Reference lists a bunch of bits that are
7007          * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7008          * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7009          * Otherwise, we should fail with #UD.  But most faulting conditions
7010          * have already been checked by hardware, prior to the VM-exit for
7011          * VMXON.  We do test guest cr4.VMXE because processor CR4 always has
7012          * that bit set to 1 in non-root mode.
7013          */
7014         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
7015                 kvm_queue_exception(vcpu, UD_VECTOR);
7016                 return 1;
7017         }
7018
7019         if (vmx->nested.vmxon) {
7020                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
7021                 return kvm_skip_emulated_instruction(vcpu);
7022         }
7023
7024         if ((vmx->msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
7025                         != VMXON_NEEDED_FEATURES) {
7026                 kvm_inject_gp(vcpu, 0);
7027                 return 1;
7028         }
7029
7030         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7031                 return 1;
7032
7033         /*
7034          * SDM 3: 24.11.5
7035          * The first 4 bytes of VMXON region contain the supported
7036          * VMCS revision identifier
7037          *
7038          * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7039          * which replaces physical address width with 32
7040          */
7041         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7042                 nested_vmx_failInvalid(vcpu);
7043                 return kvm_skip_emulated_instruction(vcpu);
7044         }
7045
7046         page = nested_get_page(vcpu, vmptr);
7047         if (page == NULL) {
7048                 nested_vmx_failInvalid(vcpu);
7049                 return kvm_skip_emulated_instruction(vcpu);
7050         }
7051         if (*(u32 *)kmap(page) != VMCS12_REVISION) {
7052                 kunmap(page);
7053                 nested_release_page_clean(page);
7054                 nested_vmx_failInvalid(vcpu);
7055                 return kvm_skip_emulated_instruction(vcpu);
7056         }
7057         kunmap(page);
7058         nested_release_page_clean(page);
7059
7060         vmx->nested.vmxon_ptr = vmptr;
7061         ret = enter_vmx_operation(vcpu);
7062         if (ret)
7063                 return ret;
7064
7065         nested_vmx_succeed(vcpu);
7066         return kvm_skip_emulated_instruction(vcpu);
7067 }
7068
7069 /*
7070  * Intel's VMX Instruction Reference specifies a common set of prerequisites
7071  * for running VMX instructions (except VMXON, whose prerequisites are
7072  * slightly different). It also specifies what exception to inject otherwise.
7073  * Note that many of these exceptions have priority over VM exits, so they
7074  * don't have to be checked again here.
7075  */
7076 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
7077 {
7078         if (!to_vmx(vcpu)->nested.vmxon) {
7079                 kvm_queue_exception(vcpu, UD_VECTOR);
7080                 return 0;
7081         }
7082         return 1;
7083 }
7084
7085 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
7086 {
7087         if (vmx->nested.current_vmptr == -1ull)
7088                 return;
7089
7090         /* current_vmptr and current_vmcs12 are always set/reset together */
7091         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
7092                 return;
7093
7094         if (enable_shadow_vmcs) {
7095                 /* copy to memory all shadowed fields in case
7096                    they were modified */
7097                 copy_shadow_to_vmcs12(vmx);
7098                 vmx->nested.sync_shadow_vmcs = false;
7099                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
7100                                 SECONDARY_EXEC_SHADOW_VMCS);
7101                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7102         }
7103         vmx->nested.posted_intr_nv = -1;
7104
7105         /* Flush VMCS12 to guest memory */
7106         memcpy(vmx->nested.current_vmcs12, vmx->nested.cached_vmcs12,
7107                VMCS12_SIZE);
7108
7109         kunmap(vmx->nested.current_vmcs12_page);
7110         nested_release_page(vmx->nested.current_vmcs12_page);
7111         vmx->nested.current_vmptr = -1ull;
7112         vmx->nested.current_vmcs12 = NULL;
7113 }
7114
7115 /*
7116  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7117  * just stops using VMX.
7118  */
7119 static void free_nested(struct vcpu_vmx *vmx)
7120 {
7121         if (!vmx->nested.vmxon)
7122                 return;
7123
7124         vmx->nested.vmxon = false;
7125         free_vpid(vmx->nested.vpid02);
7126         nested_release_vmcs12(vmx);
7127         if (vmx->nested.msr_bitmap) {
7128                 free_page((unsigned long)vmx->nested.msr_bitmap);
7129                 vmx->nested.msr_bitmap = NULL;
7130         }
7131         if (enable_shadow_vmcs) {
7132                 vmcs_clear(vmx->vmcs01.shadow_vmcs);
7133                 free_vmcs(vmx->vmcs01.shadow_vmcs);
7134                 vmx->vmcs01.shadow_vmcs = NULL;
7135         }
7136         kfree(vmx->nested.cached_vmcs12);
7137         /* Unpin physical memory we referred to in current vmcs02 */
7138         if (vmx->nested.apic_access_page) {
7139                 nested_release_page(vmx->nested.apic_access_page);
7140                 vmx->nested.apic_access_page = NULL;
7141         }
7142         if (vmx->nested.virtual_apic_page) {
7143                 nested_release_page(vmx->nested.virtual_apic_page);
7144                 vmx->nested.virtual_apic_page = NULL;
7145         }
7146         if (vmx->nested.pi_desc_page) {
7147                 kunmap(vmx->nested.pi_desc_page);
7148                 nested_release_page(vmx->nested.pi_desc_page);
7149                 vmx->nested.pi_desc_page = NULL;
7150                 vmx->nested.pi_desc = NULL;
7151         }
7152
7153         nested_free_all_saved_vmcss(vmx);
7154 }
7155
7156 /* Emulate the VMXOFF instruction */
7157 static int handle_vmoff(struct kvm_vcpu *vcpu)
7158 {
7159         if (!nested_vmx_check_permission(vcpu))
7160                 return 1;
7161         free_nested(to_vmx(vcpu));
7162         nested_vmx_succeed(vcpu);
7163         return kvm_skip_emulated_instruction(vcpu);
7164 }
7165
7166 /* Emulate the VMCLEAR instruction */
7167 static int handle_vmclear(struct kvm_vcpu *vcpu)
7168 {
7169         struct vcpu_vmx *vmx = to_vmx(vcpu);
7170         u32 zero = 0;
7171         gpa_t vmptr;
7172
7173         if (!nested_vmx_check_permission(vcpu))
7174                 return 1;
7175
7176         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7177                 return 1;
7178
7179         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7180                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
7181                 return kvm_skip_emulated_instruction(vcpu);
7182         }
7183
7184         if (vmptr == vmx->nested.vmxon_ptr) {
7185                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_VMXON_POINTER);
7186                 return kvm_skip_emulated_instruction(vcpu);
7187         }
7188
7189         if (vmptr == vmx->nested.current_vmptr)
7190                 nested_release_vmcs12(vmx);
7191
7192         kvm_vcpu_write_guest(vcpu,
7193                         vmptr + offsetof(struct vmcs12, launch_state),
7194                         &zero, sizeof(zero));
7195
7196         nested_free_vmcs02(vmx, vmptr);
7197
7198         nested_vmx_succeed(vcpu);
7199         return kvm_skip_emulated_instruction(vcpu);
7200 }
7201
7202 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7203
7204 /* Emulate the VMLAUNCH instruction */
7205 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7206 {
7207         return nested_vmx_run(vcpu, true);
7208 }
7209
7210 /* Emulate the VMRESUME instruction */
7211 static int handle_vmresume(struct kvm_vcpu *vcpu)
7212 {
7213
7214         return nested_vmx_run(vcpu, false);
7215 }
7216
7217 enum vmcs_field_type {
7218         VMCS_FIELD_TYPE_U16 = 0,
7219         VMCS_FIELD_TYPE_U64 = 1,
7220         VMCS_FIELD_TYPE_U32 = 2,
7221         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7222 };
7223
7224 static inline int vmcs_field_type(unsigned long field)
7225 {
7226         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7227                 return VMCS_FIELD_TYPE_U32;
7228         return (field >> 13) & 0x3 ;
7229 }
7230
7231 static inline int vmcs_field_readonly(unsigned long field)
7232 {
7233         return (((field >> 10) & 0x3) == 1);
7234 }
7235
7236 /*
7237  * Read a vmcs12 field. Since these can have varying lengths and we return
7238  * one type, we chose the biggest type (u64) and zero-extend the return value
7239  * to that size. Note that the caller, handle_vmread, might need to use only
7240  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7241  * 64-bit fields are to be returned).
7242  */
7243 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7244                                   unsigned long field, u64 *ret)
7245 {
7246         short offset = vmcs_field_to_offset(field);
7247         char *p;
7248
7249         if (offset < 0)
7250                 return offset;
7251
7252         p = ((char *)(get_vmcs12(vcpu))) + offset;
7253
7254         switch (vmcs_field_type(field)) {
7255         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7256                 *ret = *((natural_width *)p);
7257                 return 0;
7258         case VMCS_FIELD_TYPE_U16:
7259                 *ret = *((u16 *)p);
7260                 return 0;
7261         case VMCS_FIELD_TYPE_U32:
7262                 *ret = *((u32 *)p);
7263                 return 0;
7264         case VMCS_FIELD_TYPE_U64:
7265                 *ret = *((u64 *)p);
7266                 return 0;
7267         default:
7268                 WARN_ON(1);
7269                 return -ENOENT;
7270         }
7271 }
7272
7273
7274 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7275                                    unsigned long field, u64 field_value){
7276         short offset = vmcs_field_to_offset(field);
7277         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7278         if (offset < 0)
7279                 return offset;
7280
7281         switch (vmcs_field_type(field)) {
7282         case VMCS_FIELD_TYPE_U16:
7283                 *(u16 *)p = field_value;
7284                 return 0;
7285         case VMCS_FIELD_TYPE_U32:
7286                 *(u32 *)p = field_value;
7287                 return 0;
7288         case VMCS_FIELD_TYPE_U64:
7289                 *(u64 *)p = field_value;
7290                 return 0;
7291         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7292                 *(natural_width *)p = field_value;
7293                 return 0;
7294         default:
7295                 WARN_ON(1);
7296                 return -ENOENT;
7297         }
7298
7299 }
7300
7301 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7302 {
7303         int i;
7304         unsigned long field;
7305         u64 field_value;
7306         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7307         const unsigned long *fields = shadow_read_write_fields;
7308         const int num_fields = max_shadow_read_write_fields;
7309
7310         preempt_disable();
7311
7312         vmcs_load(shadow_vmcs);
7313
7314         for (i = 0; i < num_fields; i++) {
7315                 field = fields[i];
7316                 switch (vmcs_field_type(field)) {
7317                 case VMCS_FIELD_TYPE_U16:
7318                         field_value = vmcs_read16(field);
7319                         break;
7320                 case VMCS_FIELD_TYPE_U32:
7321                         field_value = vmcs_read32(field);
7322                         break;
7323                 case VMCS_FIELD_TYPE_U64:
7324                         field_value = vmcs_read64(field);
7325                         break;
7326                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7327                         field_value = vmcs_readl(field);
7328                         break;
7329                 default:
7330                         WARN_ON(1);
7331                         continue;
7332                 }
7333                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7334         }
7335
7336         vmcs_clear(shadow_vmcs);
7337         vmcs_load(vmx->loaded_vmcs->vmcs);
7338
7339         preempt_enable();
7340 }
7341
7342 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7343 {
7344         const unsigned long *fields[] = {
7345                 shadow_read_write_fields,
7346                 shadow_read_only_fields
7347         };
7348         const int max_fields[] = {
7349                 max_shadow_read_write_fields,
7350                 max_shadow_read_only_fields
7351         };
7352         int i, q;
7353         unsigned long field;
7354         u64 field_value = 0;
7355         struct vmcs *shadow_vmcs = vmx->vmcs01.shadow_vmcs;
7356
7357         vmcs_load(shadow_vmcs);
7358
7359         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7360                 for (i = 0; i < max_fields[q]; i++) {
7361                         field = fields[q][i];
7362                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7363
7364                         switch (vmcs_field_type(field)) {
7365                         case VMCS_FIELD_TYPE_U16:
7366                                 vmcs_write16(field, (u16)field_value);
7367                                 break;
7368                         case VMCS_FIELD_TYPE_U32:
7369                                 vmcs_write32(field, (u32)field_value);
7370                                 break;
7371                         case VMCS_FIELD_TYPE_U64:
7372                                 vmcs_write64(field, (u64)field_value);
7373                                 break;
7374                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7375                                 vmcs_writel(field, (long)field_value);
7376                                 break;
7377                         default:
7378                                 WARN_ON(1);
7379                                 break;
7380                         }
7381                 }
7382         }
7383
7384         vmcs_clear(shadow_vmcs);
7385         vmcs_load(vmx->loaded_vmcs->vmcs);
7386 }
7387
7388 /*
7389  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7390  * used before) all generate the same failure when it is missing.
7391  */
7392 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7393 {
7394         struct vcpu_vmx *vmx = to_vmx(vcpu);
7395         if (vmx->nested.current_vmptr == -1ull) {
7396                 nested_vmx_failInvalid(vcpu);
7397                 return 0;
7398         }
7399         return 1;
7400 }
7401
7402 static int handle_vmread(struct kvm_vcpu *vcpu)
7403 {
7404         unsigned long field;
7405         u64 field_value;
7406         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7407         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7408         gva_t gva = 0;
7409
7410         if (!nested_vmx_check_permission(vcpu))
7411                 return 1;
7412
7413         if (!nested_vmx_check_vmcs12(vcpu))
7414                 return kvm_skip_emulated_instruction(vcpu);
7415
7416         /* Decode instruction info and find the field to read */
7417         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7418         /* Read the field, zero-extended to a u64 field_value */
7419         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7420                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7421                 return kvm_skip_emulated_instruction(vcpu);
7422         }
7423         /*
7424          * Now copy part of this value to register or memory, as requested.
7425          * Note that the number of bits actually copied is 32 or 64 depending
7426          * on the guest's mode (32 or 64 bit), not on the given field's length.
7427          */
7428         if (vmx_instruction_info & (1u << 10)) {
7429                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7430                         field_value);
7431         } else {
7432                 if (get_vmx_mem_address(vcpu, exit_qualification,
7433                                 vmx_instruction_info, true, &gva))
7434                         return 1;
7435                 /* _system ok, as hardware has verified cpl=0 */
7436                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7437                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7438         }
7439
7440         nested_vmx_succeed(vcpu);
7441         return kvm_skip_emulated_instruction(vcpu);
7442 }
7443
7444
7445 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7446 {
7447         unsigned long field;
7448         gva_t gva;
7449         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7450         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7451         /* The value to write might be 32 or 64 bits, depending on L1's long
7452          * mode, and eventually we need to write that into a field of several
7453          * possible lengths. The code below first zero-extends the value to 64
7454          * bit (field_value), and then copies only the appropriate number of
7455          * bits into the vmcs12 field.
7456          */
7457         u64 field_value = 0;
7458         struct x86_exception e;
7459
7460         if (!nested_vmx_check_permission(vcpu))
7461                 return 1;
7462
7463         if (!nested_vmx_check_vmcs12(vcpu))
7464                 return kvm_skip_emulated_instruction(vcpu);
7465
7466         if (vmx_instruction_info & (1u << 10))
7467                 field_value = kvm_register_readl(vcpu,
7468                         (((vmx_instruction_info) >> 3) & 0xf));
7469         else {
7470                 if (get_vmx_mem_address(vcpu, exit_qualification,
7471                                 vmx_instruction_info, false, &gva))
7472                         return 1;
7473                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7474                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7475                         kvm_inject_page_fault(vcpu, &e);
7476                         return 1;
7477                 }
7478         }
7479
7480
7481         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7482         if (vmcs_field_readonly(field)) {
7483                 nested_vmx_failValid(vcpu,
7484                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7485                 return kvm_skip_emulated_instruction(vcpu);
7486         }
7487
7488         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7489                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7490                 return kvm_skip_emulated_instruction(vcpu);
7491         }
7492
7493         nested_vmx_succeed(vcpu);
7494         return kvm_skip_emulated_instruction(vcpu);
7495 }
7496
7497 static void set_current_vmptr(struct vcpu_vmx *vmx, gpa_t vmptr)
7498 {
7499         vmx->nested.current_vmptr = vmptr;
7500         if (enable_shadow_vmcs) {
7501                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7502                               SECONDARY_EXEC_SHADOW_VMCS);
7503                 vmcs_write64(VMCS_LINK_POINTER,
7504                              __pa(vmx->vmcs01.shadow_vmcs));
7505                 vmx->nested.sync_shadow_vmcs = true;
7506         }
7507 }
7508
7509 /* Emulate the VMPTRLD instruction */
7510 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7511 {
7512         struct vcpu_vmx *vmx = to_vmx(vcpu);
7513         gpa_t vmptr;
7514
7515         if (!nested_vmx_check_permission(vcpu))
7516                 return 1;
7517
7518         if (nested_vmx_get_vmptr(vcpu, &vmptr))
7519                 return 1;
7520
7521         if (!PAGE_ALIGNED(vmptr) || (vmptr >> cpuid_maxphyaddr(vcpu))) {
7522                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
7523                 return kvm_skip_emulated_instruction(vcpu);
7524         }
7525
7526         if (vmptr == vmx->nested.vmxon_ptr) {
7527                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_VMXON_POINTER);
7528                 return kvm_skip_emulated_instruction(vcpu);
7529         }
7530
7531         if (vmx->nested.current_vmptr != vmptr) {
7532                 struct vmcs12 *new_vmcs12;
7533                 struct page *page;
7534                 page = nested_get_page(vcpu, vmptr);
7535                 if (page == NULL) {
7536                         nested_vmx_failInvalid(vcpu);
7537                         return kvm_skip_emulated_instruction(vcpu);
7538                 }
7539                 new_vmcs12 = kmap(page);
7540                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7541                         kunmap(page);
7542                         nested_release_page_clean(page);
7543                         nested_vmx_failValid(vcpu,
7544                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7545                         return kvm_skip_emulated_instruction(vcpu);
7546                 }
7547
7548                 nested_release_vmcs12(vmx);
7549                 vmx->nested.current_vmcs12 = new_vmcs12;
7550                 vmx->nested.current_vmcs12_page = page;
7551                 /*
7552                  * Load VMCS12 from guest memory since it is not already
7553                  * cached.
7554                  */
7555                 memcpy(vmx->nested.cached_vmcs12,
7556                        vmx->nested.current_vmcs12, VMCS12_SIZE);
7557                 set_current_vmptr(vmx, vmptr);
7558         }
7559
7560         nested_vmx_succeed(vcpu);
7561         return kvm_skip_emulated_instruction(vcpu);
7562 }
7563
7564 /* Emulate the VMPTRST instruction */
7565 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7566 {
7567         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7568         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7569         gva_t vmcs_gva;
7570         struct x86_exception e;
7571
7572         if (!nested_vmx_check_permission(vcpu))
7573                 return 1;
7574
7575         if (get_vmx_mem_address(vcpu, exit_qualification,
7576                         vmx_instruction_info, true, &vmcs_gva))
7577                 return 1;
7578         /* ok to use *_system, as hardware has verified cpl=0 */
7579         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7580                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7581                                  sizeof(u64), &e)) {
7582                 kvm_inject_page_fault(vcpu, &e);
7583                 return 1;
7584         }
7585         nested_vmx_succeed(vcpu);
7586         return kvm_skip_emulated_instruction(vcpu);
7587 }
7588
7589 /* Emulate the INVEPT instruction */
7590 static int handle_invept(struct kvm_vcpu *vcpu)
7591 {
7592         struct vcpu_vmx *vmx = to_vmx(vcpu);
7593         u32 vmx_instruction_info, types;
7594         unsigned long type;
7595         gva_t gva;
7596         struct x86_exception e;
7597         struct {
7598                 u64 eptp, gpa;
7599         } operand;
7600
7601         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7602               SECONDARY_EXEC_ENABLE_EPT) ||
7603             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7604                 kvm_queue_exception(vcpu, UD_VECTOR);
7605                 return 1;
7606         }
7607
7608         if (!nested_vmx_check_permission(vcpu))
7609                 return 1;
7610
7611         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7612         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7613
7614         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7615
7616         if (type >= 32 || !(types & (1 << type))) {
7617                 nested_vmx_failValid(vcpu,
7618                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7619                 return kvm_skip_emulated_instruction(vcpu);
7620         }
7621
7622         /* According to the Intel VMX instruction reference, the memory
7623          * operand is read even if it isn't needed (e.g., for type==global)
7624          */
7625         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7626                         vmx_instruction_info, false, &gva))
7627                 return 1;
7628         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7629                                 sizeof(operand), &e)) {
7630                 kvm_inject_page_fault(vcpu, &e);
7631                 return 1;
7632         }
7633
7634         switch (type) {
7635         case VMX_EPT_EXTENT_GLOBAL:
7636         /*
7637          * TODO: track mappings and invalidate
7638          * single context requests appropriately
7639          */
7640         case VMX_EPT_EXTENT_CONTEXT:
7641                 kvm_mmu_sync_roots(vcpu);
7642                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7643                 nested_vmx_succeed(vcpu);
7644                 break;
7645         default:
7646                 BUG_ON(1);
7647                 break;
7648         }
7649
7650         return kvm_skip_emulated_instruction(vcpu);
7651 }
7652
7653 static int handle_invvpid(struct kvm_vcpu *vcpu)
7654 {
7655         struct vcpu_vmx *vmx = to_vmx(vcpu);
7656         u32 vmx_instruction_info;
7657         unsigned long type, types;
7658         gva_t gva;
7659         struct x86_exception e;
7660         struct {
7661                 u64 vpid;
7662                 u64 gla;
7663         } operand;
7664
7665         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7666               SECONDARY_EXEC_ENABLE_VPID) ||
7667                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7668                 kvm_queue_exception(vcpu, UD_VECTOR);
7669                 return 1;
7670         }
7671
7672         if (!nested_vmx_check_permission(vcpu))
7673                 return 1;
7674
7675         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7676         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7677
7678         types = (vmx->nested.nested_vmx_vpid_caps &
7679                         VMX_VPID_EXTENT_SUPPORTED_MASK) >> 8;
7680
7681         if (type >= 32 || !(types & (1 << type))) {
7682                 nested_vmx_failValid(vcpu,
7683                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7684                 return kvm_skip_emulated_instruction(vcpu);
7685         }
7686
7687         /* according to the intel vmx instruction reference, the memory
7688          * operand is read even if it isn't needed (e.g., for type==global)
7689          */
7690         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7691                         vmx_instruction_info, false, &gva))
7692                 return 1;
7693         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7694                                 sizeof(operand), &e)) {
7695                 kvm_inject_page_fault(vcpu, &e);
7696                 return 1;
7697         }
7698         if (operand.vpid >> 16) {
7699                 nested_vmx_failValid(vcpu,
7700                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7701                 return kvm_skip_emulated_instruction(vcpu);
7702         }
7703
7704         switch (type) {
7705         case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
7706                 if (is_noncanonical_address(operand.gla)) {
7707                         nested_vmx_failValid(vcpu,
7708                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7709                         return kvm_skip_emulated_instruction(vcpu);
7710                 }
7711                 /* fall through */
7712         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7713         case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL:
7714                 if (!operand.vpid) {
7715                         nested_vmx_failValid(vcpu,
7716                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7717                         return kvm_skip_emulated_instruction(vcpu);
7718                 }
7719                 break;
7720         case VMX_VPID_EXTENT_ALL_CONTEXT:
7721                 break;
7722         default:
7723                 WARN_ON_ONCE(1);
7724                 return kvm_skip_emulated_instruction(vcpu);
7725         }
7726
7727         __vmx_flush_tlb(vcpu, vmx->nested.vpid02);
7728         nested_vmx_succeed(vcpu);
7729
7730         return kvm_skip_emulated_instruction(vcpu);
7731 }
7732
7733 static int handle_pml_full(struct kvm_vcpu *vcpu)
7734 {
7735         unsigned long exit_qualification;
7736
7737         trace_kvm_pml_full(vcpu->vcpu_id);
7738
7739         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7740
7741         /*
7742          * PML buffer FULL happened while executing iret from NMI,
7743          * "blocked by NMI" bit has to be set before next VM entry.
7744          */
7745         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7746                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7747                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7748                                 GUEST_INTR_STATE_NMI);
7749
7750         /*
7751          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7752          * here.., and there's no userspace involvement needed for PML.
7753          */
7754         return 1;
7755 }
7756
7757 static int handle_preemption_timer(struct kvm_vcpu *vcpu)
7758 {
7759         kvm_lapic_expired_hv_timer(vcpu);
7760         return 1;
7761 }
7762
7763 /*
7764  * The exit handlers return 1 if the exit was handled fully and guest execution
7765  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7766  * to be done to userspace and return 0.
7767  */
7768 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7769         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7770         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7771         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7772         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7773         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7774         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7775         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7776         [EXIT_REASON_CPUID]                   = handle_cpuid,
7777         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7778         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7779         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7780         [EXIT_REASON_HLT]                     = handle_halt,
7781         [EXIT_REASON_INVD]                    = handle_invd,
7782         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7783         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7784         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7785         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7786         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7787         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7788         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7789         [EXIT_REASON_VMREAD]                  = handle_vmread,
7790         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7791         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7792         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7793         [EXIT_REASON_VMON]                    = handle_vmon,
7794         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7795         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7796         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7797         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7798         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7799         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7800         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7801         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7802         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7803         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7804         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7805         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7806         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7807         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7808         [EXIT_REASON_INVEPT]                  = handle_invept,
7809         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7810         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7811         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7812         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7813         [EXIT_REASON_PREEMPTION_TIMER]        = handle_preemption_timer,
7814 };
7815
7816 static const int kvm_vmx_max_exit_handlers =
7817         ARRAY_SIZE(kvm_vmx_exit_handlers);
7818
7819 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7820                                        struct vmcs12 *vmcs12)
7821 {
7822         unsigned long exit_qualification;
7823         gpa_t bitmap, last_bitmap;
7824         unsigned int port;
7825         int size;
7826         u8 b;
7827
7828         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7829                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7830
7831         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7832
7833         port = exit_qualification >> 16;
7834         size = (exit_qualification & 7) + 1;
7835
7836         last_bitmap = (gpa_t)-1;
7837         b = -1;
7838
7839         while (size > 0) {
7840                 if (port < 0x8000)
7841                         bitmap = vmcs12->io_bitmap_a;
7842                 else if (port < 0x10000)
7843                         bitmap = vmcs12->io_bitmap_b;
7844                 else
7845                         return true;
7846                 bitmap += (port & 0x7fff) / 8;
7847
7848                 if (last_bitmap != bitmap)
7849                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7850                                 return true;
7851                 if (b & (1 << (port & 7)))
7852                         return true;
7853
7854                 port++;
7855                 size--;
7856                 last_bitmap = bitmap;
7857         }
7858
7859         return false;
7860 }
7861
7862 /*
7863  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7864  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7865  * disinterest in the current event (read or write a specific MSR) by using an
7866  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7867  */
7868 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7869         struct vmcs12 *vmcs12, u32 exit_reason)
7870 {
7871         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7872         gpa_t bitmap;
7873
7874         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7875                 return true;
7876
7877         /*
7878          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7879          * for the four combinations of read/write and low/high MSR numbers.
7880          * First we need to figure out which of the four to use:
7881          */
7882         bitmap = vmcs12->msr_bitmap;
7883         if (exit_reason == EXIT_REASON_MSR_WRITE)
7884                 bitmap += 2048;
7885         if (msr_index >= 0xc0000000) {
7886                 msr_index -= 0xc0000000;
7887                 bitmap += 1024;
7888         }
7889
7890         /* Then read the msr_index'th bit from this bitmap: */
7891         if (msr_index < 1024*8) {
7892                 unsigned char b;
7893                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7894                         return true;
7895                 return 1 & (b >> (msr_index & 7));
7896         } else
7897                 return true; /* let L1 handle the wrong parameter */
7898 }
7899
7900 /*
7901  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7902  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7903  * intercept (via guest_host_mask etc.) the current event.
7904  */
7905 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7906         struct vmcs12 *vmcs12)
7907 {
7908         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7909         int cr = exit_qualification & 15;
7910         int reg;
7911         unsigned long val;
7912
7913         switch ((exit_qualification >> 4) & 3) {
7914         case 0: /* mov to cr */
7915                 reg = (exit_qualification >> 8) & 15;
7916                 val = kvm_register_readl(vcpu, reg);
7917                 switch (cr) {
7918                 case 0:
7919                         if (vmcs12->cr0_guest_host_mask &
7920                             (val ^ vmcs12->cr0_read_shadow))
7921                                 return true;
7922                         break;
7923                 case 3:
7924                         if ((vmcs12->cr3_target_count >= 1 &&
7925                                         vmcs12->cr3_target_value0 == val) ||
7926                                 (vmcs12->cr3_target_count >= 2 &&
7927                                         vmcs12->cr3_target_value1 == val) ||
7928                                 (vmcs12->cr3_target_count >= 3 &&
7929                                         vmcs12->cr3_target_value2 == val) ||
7930                                 (vmcs12->cr3_target_count >= 4 &&
7931                                         vmcs12->cr3_target_value3 == val))
7932                                 return false;
7933                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7934                                 return true;
7935                         break;
7936                 case 4:
7937                         if (vmcs12->cr4_guest_host_mask &
7938                             (vmcs12->cr4_read_shadow ^ val))
7939                                 return true;
7940                         break;
7941                 case 8:
7942                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7943                                 return true;
7944                         break;
7945                 }
7946                 break;
7947         case 2: /* clts */
7948                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7949                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7950                         return true;
7951                 break;
7952         case 1: /* mov from cr */
7953                 switch (cr) {
7954                 case 3:
7955                         if (vmcs12->cpu_based_vm_exec_control &
7956                             CPU_BASED_CR3_STORE_EXITING)
7957                                 return true;
7958                         break;
7959                 case 8:
7960                         if (vmcs12->cpu_based_vm_exec_control &
7961                             CPU_BASED_CR8_STORE_EXITING)
7962                                 return true;
7963                         break;
7964                 }
7965                 break;
7966         case 3: /* lmsw */
7967                 /*
7968                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7969                  * cr0. Other attempted changes are ignored, with no exit.
7970                  */
7971                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
7972                 if (vmcs12->cr0_guest_host_mask & 0xe &
7973                     (val ^ vmcs12->cr0_read_shadow))
7974                         return true;
7975                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7976                     !(vmcs12->cr0_read_shadow & 0x1) &&
7977                     (val & 0x1))
7978                         return true;
7979                 break;
7980         }
7981         return false;
7982 }
7983
7984 /*
7985  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7986  * should handle it ourselves in L0 (and then continue L2). Only call this
7987  * when in is_guest_mode (L2).
7988  */
7989 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7990 {
7991         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7992         struct vcpu_vmx *vmx = to_vmx(vcpu);
7993         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7994         u32 exit_reason = vmx->exit_reason;
7995
7996         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7997                                 vmcs_readl(EXIT_QUALIFICATION),
7998                                 vmx->idt_vectoring_info,
7999                                 intr_info,
8000                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8001                                 KVM_ISA_VMX);
8002
8003         if (vmx->nested.nested_run_pending)
8004                 return false;
8005
8006         if (unlikely(vmx->fail)) {
8007                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
8008                                     vmcs_read32(VM_INSTRUCTION_ERROR));
8009                 return true;
8010         }
8011
8012         switch (exit_reason) {
8013         case EXIT_REASON_EXCEPTION_NMI:
8014                 if (is_nmi(intr_info))
8015                         return false;
8016                 else if (is_page_fault(intr_info))
8017                         return enable_ept;
8018                 else if (is_no_device(intr_info) &&
8019                          !(vmcs12->guest_cr0 & X86_CR0_TS))
8020                         return false;
8021                 else if (is_debug(intr_info) &&
8022                          vcpu->guest_debug &
8023                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
8024                         return false;
8025                 else if (is_breakpoint(intr_info) &&
8026                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
8027                         return false;
8028                 return vmcs12->exception_bitmap &
8029                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
8030         case EXIT_REASON_EXTERNAL_INTERRUPT:
8031                 return false;
8032         case EXIT_REASON_TRIPLE_FAULT:
8033                 return true;
8034         case EXIT_REASON_PENDING_INTERRUPT:
8035                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
8036         case EXIT_REASON_NMI_WINDOW:
8037                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
8038         case EXIT_REASON_TASK_SWITCH:
8039                 return true;
8040         case EXIT_REASON_CPUID:
8041                 return true;
8042         case EXIT_REASON_HLT:
8043                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
8044         case EXIT_REASON_INVD:
8045                 return true;
8046         case EXIT_REASON_INVLPG:
8047                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
8048         case EXIT_REASON_RDPMC:
8049                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
8050         case EXIT_REASON_RDRAND:
8051                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDRAND);
8052         case EXIT_REASON_RDSEED:
8053                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDSEED);
8054         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
8055                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
8056         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
8057         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
8058         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
8059         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
8060         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
8061         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
8062                 /*
8063                  * VMX instructions trap unconditionally. This allows L1 to
8064                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
8065                  */
8066                 return true;
8067         case EXIT_REASON_CR_ACCESS:
8068                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
8069         case EXIT_REASON_DR_ACCESS:
8070                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
8071         case EXIT_REASON_IO_INSTRUCTION:
8072                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
8073         case EXIT_REASON_GDTR_IDTR: case EXIT_REASON_LDTR_TR:
8074                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_DESC);
8075         case EXIT_REASON_MSR_READ:
8076         case EXIT_REASON_MSR_WRITE:
8077                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
8078         case EXIT_REASON_INVALID_STATE:
8079                 return true;
8080         case EXIT_REASON_MWAIT_INSTRUCTION:
8081                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
8082         case EXIT_REASON_MONITOR_TRAP_FLAG:
8083                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
8084         case EXIT_REASON_MONITOR_INSTRUCTION:
8085                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
8086         case EXIT_REASON_PAUSE_INSTRUCTION:
8087                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
8088                         nested_cpu_has2(vmcs12,
8089                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
8090         case EXIT_REASON_MCE_DURING_VMENTRY:
8091                 return false;
8092         case EXIT_REASON_TPR_BELOW_THRESHOLD:
8093                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
8094         case EXIT_REASON_APIC_ACCESS:
8095                 return nested_cpu_has2(vmcs12,
8096                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
8097         case EXIT_REASON_APIC_WRITE:
8098         case EXIT_REASON_EOI_INDUCED:
8099                 /* apic_write and eoi_induced should exit unconditionally. */
8100                 return true;
8101         case EXIT_REASON_EPT_VIOLATION:
8102                 /*
8103                  * L0 always deals with the EPT violation. If nested EPT is
8104                  * used, and the nested mmu code discovers that the address is
8105                  * missing in the guest EPT table (EPT12), the EPT violation
8106                  * will be injected with nested_ept_inject_page_fault()
8107                  */
8108                 return false;
8109         case EXIT_REASON_EPT_MISCONFIG:
8110                 /*
8111                  * L2 never uses directly L1's EPT, but rather L0's own EPT
8112                  * table (shadow on EPT) or a merged EPT table that L0 built
8113                  * (EPT on EPT). So any problems with the structure of the
8114                  * table is L0's fault.
8115                  */
8116                 return false;
8117         case EXIT_REASON_WBINVD:
8118                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
8119         case EXIT_REASON_XSETBV:
8120                 return true;
8121         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
8122                 /*
8123                  * This should never happen, since it is not possible to
8124                  * set XSS to a non-zero value---neither in L1 nor in L2.
8125                  * If if it were, XSS would have to be checked against
8126                  * the XSS exit bitmap in vmcs12.
8127                  */
8128                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
8129         case EXIT_REASON_PREEMPTION_TIMER:
8130                 return false;
8131         case EXIT_REASON_PML_FULL:
8132                 /* We emulate PML support to L1. */
8133                 return false;
8134         default:
8135                 return true;
8136         }
8137 }
8138
8139 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
8140 {
8141         *info1 = vmcs_readl(EXIT_QUALIFICATION);
8142         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
8143 }
8144
8145 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
8146 {
8147         if (vmx->pml_pg) {
8148                 __free_page(vmx->pml_pg);
8149                 vmx->pml_pg = NULL;
8150         }
8151 }
8152
8153 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
8154 {
8155         struct vcpu_vmx *vmx = to_vmx(vcpu);
8156         u64 *pml_buf;
8157         u16 pml_idx;
8158
8159         pml_idx = vmcs_read16(GUEST_PML_INDEX);
8160
8161         /* Do nothing if PML buffer is empty */
8162         if (pml_idx == (PML_ENTITY_NUM - 1))
8163                 return;
8164
8165         /* PML index always points to next available PML buffer entity */
8166         if (pml_idx >= PML_ENTITY_NUM)
8167                 pml_idx = 0;
8168         else
8169                 pml_idx++;
8170
8171         pml_buf = page_address(vmx->pml_pg);
8172         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
8173                 u64 gpa;
8174
8175                 gpa = pml_buf[pml_idx];
8176                 WARN_ON(gpa & (PAGE_SIZE - 1));
8177                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
8178         }
8179
8180         /* reset PML index */
8181         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
8182 }
8183
8184 /*
8185  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8186  * Called before reporting dirty_bitmap to userspace.
8187  */
8188 static void kvm_flush_pml_buffers(struct kvm *kvm)
8189 {
8190         int i;
8191         struct kvm_vcpu *vcpu;
8192         /*
8193          * We only need to kick vcpu out of guest mode here, as PML buffer
8194          * is flushed at beginning of all VMEXITs, and it's obvious that only
8195          * vcpus running in guest are possible to have unflushed GPAs in PML
8196          * buffer.
8197          */
8198         kvm_for_each_vcpu(i, vcpu, kvm)
8199                 kvm_vcpu_kick(vcpu);
8200 }
8201
8202 static void vmx_dump_sel(char *name, uint32_t sel)
8203 {
8204         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8205                name, vmcs_read16(sel),
8206                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
8207                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
8208                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
8209 }
8210
8211 static void vmx_dump_dtsel(char *name, uint32_t limit)
8212 {
8213         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8214                name, vmcs_read32(limit),
8215                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8216 }
8217
8218 static void dump_vmcs(void)
8219 {
8220         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8221         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8222         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8223         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8224         u32 secondary_exec_control = 0;
8225         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8226         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8227         int i, n;
8228
8229         if (cpu_has_secondary_exec_ctrls())
8230                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8231
8232         pr_err("*** Guest State ***\n");
8233         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8234                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8235                vmcs_readl(CR0_GUEST_HOST_MASK));
8236         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8237                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8238         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8239         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8240             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8241         {
8242                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8243                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8244                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8245                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8246         }
8247         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8248                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8249         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8250                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8251         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8252                vmcs_readl(GUEST_SYSENTER_ESP),
8253                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8254         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8255         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8256         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8257         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8258         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8259         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8260         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8261         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8262         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8263         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8264         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8265             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8266                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8267                        efer, vmcs_read64(GUEST_IA32_PAT));
8268         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8269                vmcs_read64(GUEST_IA32_DEBUGCTL),
8270                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8271         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8272                 pr_err("PerfGlobCtl = 0x%016llx\n",
8273                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8274         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8275                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8276         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8277                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8278                vmcs_read32(GUEST_ACTIVITY_STATE));
8279         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8280                 pr_err("InterruptStatus = %04x\n",
8281                        vmcs_read16(GUEST_INTR_STATUS));
8282
8283         pr_err("*** Host State ***\n");
8284         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8285                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8286         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8287                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8288                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8289                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8290                vmcs_read16(HOST_TR_SELECTOR));
8291         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8292                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8293                vmcs_readl(HOST_TR_BASE));
8294         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8295                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8296         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8297                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8298                vmcs_readl(HOST_CR4));
8299         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8300                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8301                vmcs_read32(HOST_IA32_SYSENTER_CS),
8302                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8303         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8304                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8305                        vmcs_read64(HOST_IA32_EFER),
8306                        vmcs_read64(HOST_IA32_PAT));
8307         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8308                 pr_err("PerfGlobCtl = 0x%016llx\n",
8309                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8310
8311         pr_err("*** Control State ***\n");
8312         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8313                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8314         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8315         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8316                vmcs_read32(EXCEPTION_BITMAP),
8317                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8318                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8319         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8320                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8321                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8322                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8323         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8324                vmcs_read32(VM_EXIT_INTR_INFO),
8325                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8326                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8327         pr_err("        reason=%08x qualification=%016lx\n",
8328                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8329         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8330                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8331                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8332         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8333         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8334                 pr_err("TSC Multiplier = 0x%016llx\n",
8335                        vmcs_read64(TSC_MULTIPLIER));
8336         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8337                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8338         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8339                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8340         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8341                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8342         n = vmcs_read32(CR3_TARGET_COUNT);
8343         for (i = 0; i + 1 < n; i += 4)
8344                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8345                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8346                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8347         if (i < n)
8348                 pr_err("CR3 target%u=%016lx\n",
8349                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8350         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8351                 pr_err("PLE Gap=%08x Window=%08x\n",
8352                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8353         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8354                 pr_err("Virtual processor ID = 0x%04x\n",
8355                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8356 }
8357
8358 /*
8359  * The guest has exited.  See if we can fix it or if we need userspace
8360  * assistance.
8361  */
8362 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8363 {
8364         struct vcpu_vmx *vmx = to_vmx(vcpu);
8365         u32 exit_reason = vmx->exit_reason;
8366         u32 vectoring_info = vmx->idt_vectoring_info;
8367
8368         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8369         vcpu->arch.gpa_available = false;
8370
8371         /*
8372          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8373          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8374          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8375          * mode as if vcpus is in root mode, the PML buffer must has been
8376          * flushed already.
8377          */
8378         if (enable_pml)
8379                 vmx_flush_pml_buffer(vcpu);
8380
8381         /* If guest state is invalid, start emulating */
8382         if (vmx->emulation_required)
8383                 return handle_invalid_guest_state(vcpu);
8384
8385         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8386                 nested_vmx_vmexit(vcpu, exit_reason,
8387                                   vmcs_read32(VM_EXIT_INTR_INFO),
8388                                   vmcs_readl(EXIT_QUALIFICATION));
8389                 return 1;
8390         }
8391
8392         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8393                 dump_vmcs();
8394                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8395                 vcpu->run->fail_entry.hardware_entry_failure_reason
8396                         = exit_reason;
8397                 return 0;
8398         }
8399
8400         if (unlikely(vmx->fail)) {
8401                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8402                 vcpu->run->fail_entry.hardware_entry_failure_reason
8403                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8404                 return 0;
8405         }
8406
8407         /*
8408          * Note:
8409          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8410          * delivery event since it indicates guest is accessing MMIO.
8411          * The vm-exit can be triggered again after return to guest that
8412          * will cause infinite loop.
8413          */
8414         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8415                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8416                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8417                         exit_reason != EXIT_REASON_PML_FULL &&
8418                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8419                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8420                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8421                 vcpu->run->internal.ndata = 2;
8422                 vcpu->run->internal.data[0] = vectoring_info;
8423                 vcpu->run->internal.data[1] = exit_reason;
8424                 return 0;
8425         }
8426
8427         if (exit_reason < kvm_vmx_max_exit_handlers
8428             && kvm_vmx_exit_handlers[exit_reason])
8429                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8430         else {
8431                 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
8432                                 exit_reason);
8433                 kvm_queue_exception(vcpu, UD_VECTOR);
8434                 return 1;
8435         }
8436 }
8437
8438 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8439 {
8440         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8441
8442         if (is_guest_mode(vcpu) &&
8443                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8444                 return;
8445
8446         if (irr == -1 || tpr < irr) {
8447                 vmcs_write32(TPR_THRESHOLD, 0);
8448                 return;
8449         }
8450
8451         vmcs_write32(TPR_THRESHOLD, irr);
8452 }
8453
8454 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8455 {
8456         u32 sec_exec_control;
8457
8458         /* Postpone execution until vmcs01 is the current VMCS. */
8459         if (is_guest_mode(vcpu)) {
8460                 to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
8461                 return;
8462         }
8463
8464         if (!cpu_has_vmx_virtualize_x2apic_mode())
8465                 return;
8466
8467         if (!cpu_need_tpr_shadow(vcpu))
8468                 return;
8469
8470         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8471
8472         if (set) {
8473                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8474                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8475         } else {
8476                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8477                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8478                 vmx_flush_tlb_ept_only(vcpu);
8479         }
8480         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8481
8482         vmx_set_msr_bitmap(vcpu);
8483 }
8484
8485 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8486 {
8487         struct vcpu_vmx *vmx = to_vmx(vcpu);
8488
8489         /*
8490          * Currently we do not handle the nested case where L2 has an
8491          * APIC access page of its own; that page is still pinned.
8492          * Hence, we skip the case where the VCPU is in guest mode _and_
8493          * L1 prepared an APIC access page for L2.
8494          *
8495          * For the case where L1 and L2 share the same APIC access page
8496          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8497          * in the vmcs12), this function will only update either the vmcs01
8498          * or the vmcs02.  If the former, the vmcs02 will be updated by
8499          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8500          * the next L2->L1 exit.
8501          */
8502         if (!is_guest_mode(vcpu) ||
8503             !nested_cpu_has2(get_vmcs12(&vmx->vcpu),
8504                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
8505                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8506                 vmx_flush_tlb_ept_only(vcpu);
8507         }
8508 }
8509
8510 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
8511 {
8512         u16 status;
8513         u8 old;
8514
8515         if (max_isr == -1)
8516                 max_isr = 0;
8517
8518         status = vmcs_read16(GUEST_INTR_STATUS);
8519         old = status >> 8;
8520         if (max_isr != old) {
8521                 status &= 0xff;
8522                 status |= max_isr << 8;
8523                 vmcs_write16(GUEST_INTR_STATUS, status);
8524         }
8525 }
8526
8527 static void vmx_set_rvi(int vector)
8528 {
8529         u16 status;
8530         u8 old;
8531
8532         if (vector == -1)
8533                 vector = 0;
8534
8535         status = vmcs_read16(GUEST_INTR_STATUS);
8536         old = (u8)status & 0xff;
8537         if ((u8)vector != old) {
8538                 status &= ~0xff;
8539                 status |= (u8)vector;
8540                 vmcs_write16(GUEST_INTR_STATUS, status);
8541         }
8542 }
8543
8544 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8545 {
8546         if (!is_guest_mode(vcpu)) {
8547                 vmx_set_rvi(max_irr);
8548                 return;
8549         }
8550
8551         if (max_irr == -1)
8552                 return;
8553
8554         /*
8555          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8556          * handles it.
8557          */
8558         if (nested_exit_on_intr(vcpu))
8559                 return;
8560
8561         /*
8562          * Else, fall back to pre-APICv interrupt injection since L2
8563          * is run without virtual interrupt delivery.
8564          */
8565         if (!kvm_event_needs_reinjection(vcpu) &&
8566             vmx_interrupt_allowed(vcpu)) {
8567                 kvm_queue_interrupt(vcpu, max_irr, false);
8568                 vmx_inject_irq(vcpu);
8569         }
8570 }
8571
8572 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
8573 {
8574         struct vcpu_vmx *vmx = to_vmx(vcpu);
8575         int max_irr;
8576
8577         WARN_ON(!vcpu->arch.apicv_active);
8578         if (pi_test_on(&vmx->pi_desc)) {
8579                 pi_clear_on(&vmx->pi_desc);
8580                 /*
8581                  * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8582                  * But on x86 this is just a compiler barrier anyway.
8583                  */
8584                 smp_mb__after_atomic();
8585                 max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
8586         } else {
8587                 max_irr = kvm_lapic_find_highest_irr(vcpu);
8588         }
8589         vmx_hwapic_irr_update(vcpu, max_irr);
8590         return max_irr;
8591 }
8592
8593 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8594 {
8595         if (!kvm_vcpu_apicv_active(vcpu))
8596                 return;
8597
8598         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8599         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8600         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8601         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8602 }
8603
8604 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8605 {
8606         struct vcpu_vmx *vmx = to_vmx(vcpu);
8607
8608         pi_clear_on(&vmx->pi_desc);
8609         memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
8610 }
8611
8612 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8613 {
8614         u32 exit_intr_info;
8615
8616         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8617               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8618                 return;
8619
8620         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8621         exit_intr_info = vmx->exit_intr_info;
8622
8623         /* Handle machine checks before interrupts are enabled */
8624         if (is_machine_check(exit_intr_info))
8625                 kvm_machine_check();
8626
8627         /* We need to handle NMIs before interrupts are enabled */
8628         if (is_nmi(exit_intr_info)) {
8629                 kvm_before_handle_nmi(&vmx->vcpu);
8630                 asm("int $2");
8631                 kvm_after_handle_nmi(&vmx->vcpu);
8632         }
8633 }
8634
8635 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8636 {
8637         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8638         register void *__sp asm(_ASM_SP);
8639
8640         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8641                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8642                 unsigned int vector;
8643                 unsigned long entry;
8644                 gate_desc *desc;
8645                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8646 #ifdef CONFIG_X86_64
8647                 unsigned long tmp;
8648 #endif
8649
8650                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8651                 desc = (gate_desc *)vmx->host_idt_base + vector;
8652                 entry = gate_offset(*desc);
8653                 asm volatile(
8654 #ifdef CONFIG_X86_64
8655                         "mov %%" _ASM_SP ", %[sp]\n\t"
8656                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8657                         "push $%c[ss]\n\t"
8658                         "push %[sp]\n\t"
8659 #endif
8660                         "pushf\n\t"
8661                         __ASM_SIZE(push) " $%c[cs]\n\t"
8662                         "call *%[entry]\n\t"
8663                         :
8664 #ifdef CONFIG_X86_64
8665                         [sp]"=&r"(tmp),
8666 #endif
8667                         "+r"(__sp)
8668                         :
8669                         [entry]"r"(entry),
8670                         [ss]"i"(__KERNEL_DS),
8671                         [cs]"i"(__KERNEL_CS)
8672                         );
8673         }
8674 }
8675 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
8676
8677 static bool vmx_has_high_real_mode_segbase(void)
8678 {
8679         return enable_unrestricted_guest || emulate_invalid_guest_state;
8680 }
8681
8682 static bool vmx_mpx_supported(void)
8683 {
8684         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8685                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8686 }
8687
8688 static bool vmx_xsaves_supported(void)
8689 {
8690         return vmcs_config.cpu_based_2nd_exec_ctrl &
8691                 SECONDARY_EXEC_XSAVES;
8692 }
8693
8694 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8695 {
8696         u32 exit_intr_info;
8697         bool unblock_nmi;
8698         u8 vector;
8699         bool idtv_info_valid;
8700
8701         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8702
8703         if (vmx->nmi_known_unmasked)
8704                 return;
8705         /*
8706          * Can't use vmx->exit_intr_info since we're not sure what
8707          * the exit reason is.
8708          */
8709         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8710         unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8711         vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8712         /*
8713          * SDM 3: 27.7.1.2 (September 2008)
8714          * Re-set bit "block by NMI" before VM entry if vmexit caused by
8715          * a guest IRET fault.
8716          * SDM 3: 23.2.2 (September 2008)
8717          * Bit 12 is undefined in any of the following cases:
8718          *  If the VM exit sets the valid bit in the IDT-vectoring
8719          *   information field.
8720          *  If the VM exit is due to a double fault.
8721          */
8722         if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8723             vector != DF_VECTOR && !idtv_info_valid)
8724                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8725                               GUEST_INTR_STATE_NMI);
8726         else
8727                 vmx->nmi_known_unmasked =
8728                         !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8729                           & GUEST_INTR_STATE_NMI);
8730 }
8731
8732 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8733                                       u32 idt_vectoring_info,
8734                                       int instr_len_field,
8735                                       int error_code_field)
8736 {
8737         u8 vector;
8738         int type;
8739         bool idtv_info_valid;
8740
8741         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8742
8743         vcpu->arch.nmi_injected = false;
8744         kvm_clear_exception_queue(vcpu);
8745         kvm_clear_interrupt_queue(vcpu);
8746
8747         if (!idtv_info_valid)
8748                 return;
8749
8750         kvm_make_request(KVM_REQ_EVENT, vcpu);
8751
8752         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8753         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8754
8755         switch (type) {
8756         case INTR_TYPE_NMI_INTR:
8757                 vcpu->arch.nmi_injected = true;
8758                 /*
8759                  * SDM 3: 27.7.1.2 (September 2008)
8760                  * Clear bit "block by NMI" before VM entry if a NMI
8761                  * delivery faulted.
8762                  */
8763                 vmx_set_nmi_mask(vcpu, false);
8764                 break;
8765         case INTR_TYPE_SOFT_EXCEPTION:
8766                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8767                 /* fall through */
8768         case INTR_TYPE_HARD_EXCEPTION:
8769                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8770                         u32 err = vmcs_read32(error_code_field);
8771                         kvm_requeue_exception_e(vcpu, vector, err);
8772                 } else
8773                         kvm_requeue_exception(vcpu, vector);
8774                 break;
8775         case INTR_TYPE_SOFT_INTR:
8776                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8777                 /* fall through */
8778         case INTR_TYPE_EXT_INTR:
8779                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8780                 break;
8781         default:
8782                 break;
8783         }
8784 }
8785
8786 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8787 {
8788         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8789                                   VM_EXIT_INSTRUCTION_LEN,
8790                                   IDT_VECTORING_ERROR_CODE);
8791 }
8792
8793 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8794 {
8795         __vmx_complete_interrupts(vcpu,
8796                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8797                                   VM_ENTRY_INSTRUCTION_LEN,
8798                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8799
8800         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8801 }
8802
8803 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8804 {
8805         int i, nr_msrs;
8806         struct perf_guest_switch_msr *msrs;
8807
8808         msrs = perf_guest_get_msrs(&nr_msrs);
8809
8810         if (!msrs)
8811                 return;
8812
8813         for (i = 0; i < nr_msrs; i++)
8814                 if (msrs[i].host == msrs[i].guest)
8815                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8816                 else
8817                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8818                                         msrs[i].host);
8819 }
8820
8821 static void vmx_arm_hv_timer(struct kvm_vcpu *vcpu)
8822 {
8823         struct vcpu_vmx *vmx = to_vmx(vcpu);
8824         u64 tscl;
8825         u32 delta_tsc;
8826
8827         if (vmx->hv_deadline_tsc == -1)
8828                 return;
8829
8830         tscl = rdtsc();
8831         if (vmx->hv_deadline_tsc > tscl)
8832                 /* sure to be 32 bit only because checked on set_hv_timer */
8833                 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
8834                         cpu_preemption_timer_multi);
8835         else
8836                 delta_tsc = 0;
8837
8838         vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc);
8839 }
8840
8841 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8842 {
8843         struct vcpu_vmx *vmx = to_vmx(vcpu);
8844         unsigned long debugctlmsr, cr3, cr4;
8845
8846         /* Don't enter VMX if guest state is invalid, let the exit handler
8847            start emulation until we arrive back to a valid state */
8848         if (vmx->emulation_required)
8849                 return;
8850
8851         if (vmx->ple_window_dirty) {
8852                 vmx->ple_window_dirty = false;
8853                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8854         }
8855
8856         if (vmx->nested.sync_shadow_vmcs) {
8857                 copy_vmcs12_to_shadow(vmx);
8858                 vmx->nested.sync_shadow_vmcs = false;
8859         }
8860
8861         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8862                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8863         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8864                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8865
8866         cr3 = __get_current_cr3_fast();
8867         if (unlikely(cr3 != vmx->host_state.vmcs_host_cr3)) {
8868                 vmcs_writel(HOST_CR3, cr3);
8869                 vmx->host_state.vmcs_host_cr3 = cr3;
8870         }
8871
8872         cr4 = cr4_read_shadow();
8873         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8874                 vmcs_writel(HOST_CR4, cr4);
8875                 vmx->host_state.vmcs_host_cr4 = cr4;
8876         }
8877
8878         /* When single-stepping over STI and MOV SS, we must clear the
8879          * corresponding interruptibility bits in the guest state. Otherwise
8880          * vmentry fails as it then expects bit 14 (BS) in pending debug
8881          * exceptions being set, but that's not correct for the guest debugging
8882          * case. */
8883         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8884                 vmx_set_interrupt_shadow(vcpu, 0);
8885
8886         if (vmx->guest_pkru_valid)
8887                 __write_pkru(vmx->guest_pkru);
8888
8889         atomic_switch_perf_msrs(vmx);
8890         debugctlmsr = get_debugctlmsr();
8891
8892         vmx_arm_hv_timer(vcpu);
8893
8894         vmx->__launched = vmx->loaded_vmcs->launched;
8895         asm(
8896                 /* Store host registers */
8897                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8898                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8899                 "push %%" _ASM_CX " \n\t"
8900                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8901                 "je 1f \n\t"
8902                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8903                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8904                 "1: \n\t"
8905                 /* Reload cr2 if changed */
8906                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8907                 "mov %%cr2, %%" _ASM_DX " \n\t"
8908                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8909                 "je 2f \n\t"
8910                 "mov %%" _ASM_AX", %%cr2 \n\t"
8911                 "2: \n\t"
8912                 /* Check if vmlaunch of vmresume is needed */
8913                 "cmpl $0, %c[launched](%0) \n\t"
8914                 /* Load guest registers.  Don't clobber flags. */
8915                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8916                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8917                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8918                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8919                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8920                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8921 #ifdef CONFIG_X86_64
8922                 "mov %c[r8](%0),  %%r8  \n\t"
8923                 "mov %c[r9](%0),  %%r9  \n\t"
8924                 "mov %c[r10](%0), %%r10 \n\t"
8925                 "mov %c[r11](%0), %%r11 \n\t"
8926                 "mov %c[r12](%0), %%r12 \n\t"
8927                 "mov %c[r13](%0), %%r13 \n\t"
8928                 "mov %c[r14](%0), %%r14 \n\t"
8929                 "mov %c[r15](%0), %%r15 \n\t"
8930 #endif
8931                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8932
8933                 /* Enter guest mode */
8934                 "jne 1f \n\t"
8935                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8936                 "jmp 2f \n\t"
8937                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8938                 "2: "
8939                 /* Save guest registers, load host registers, keep flags */
8940                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8941                 "pop %0 \n\t"
8942                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8943                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8944                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8945                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8946                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8947                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8948                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8949 #ifdef CONFIG_X86_64
8950                 "mov %%r8,  %c[r8](%0) \n\t"
8951                 "mov %%r9,  %c[r9](%0) \n\t"
8952                 "mov %%r10, %c[r10](%0) \n\t"
8953                 "mov %%r11, %c[r11](%0) \n\t"
8954                 "mov %%r12, %c[r12](%0) \n\t"
8955                 "mov %%r13, %c[r13](%0) \n\t"
8956                 "mov %%r14, %c[r14](%0) \n\t"
8957                 "mov %%r15, %c[r15](%0) \n\t"
8958 #endif
8959                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8960                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8961
8962                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8963                 "setbe %c[fail](%0) \n\t"
8964                 ".pushsection .rodata \n\t"
8965                 ".global vmx_return \n\t"
8966                 "vmx_return: " _ASM_PTR " 2b \n\t"
8967                 ".popsection"
8968               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8969                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8970                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8971                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8972                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8973                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8974                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8975                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8976                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8977                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8978                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8979 #ifdef CONFIG_X86_64
8980                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8981                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8982                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8983                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8984                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8985                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8986                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8987                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8988 #endif
8989                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8990                 [wordsize]"i"(sizeof(ulong))
8991               : "cc", "memory"
8992 #ifdef CONFIG_X86_64
8993                 , "rax", "rbx", "rdi", "rsi"
8994                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8995 #else
8996                 , "eax", "ebx", "edi", "esi"
8997 #endif
8998               );
8999
9000         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9001         if (debugctlmsr)
9002                 update_debugctlmsr(debugctlmsr);
9003
9004 #ifndef CONFIG_X86_64
9005         /*
9006          * The sysexit path does not restore ds/es, so we must set them to
9007          * a reasonable value ourselves.
9008          *
9009          * We can't defer this to vmx_load_host_state() since that function
9010          * may be executed in interrupt context, which saves and restore segments
9011          * around it, nullifying its effect.
9012          */
9013         loadsegment(ds, __USER_DS);
9014         loadsegment(es, __USER_DS);
9015 #endif
9016
9017         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
9018                                   | (1 << VCPU_EXREG_RFLAGS)
9019                                   | (1 << VCPU_EXREG_PDPTR)
9020                                   | (1 << VCPU_EXREG_SEGMENTS)
9021                                   | (1 << VCPU_EXREG_CR3));
9022         vcpu->arch.regs_dirty = 0;
9023
9024         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
9025
9026         vmx->loaded_vmcs->launched = 1;
9027
9028         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
9029
9030         /*
9031          * eager fpu is enabled if PKEY is supported and CR4 is switched
9032          * back on host, so it is safe to read guest PKRU from current
9033          * XSAVE.
9034          */
9035         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
9036                 vmx->guest_pkru = __read_pkru();
9037                 if (vmx->guest_pkru != vmx->host_pkru) {
9038                         vmx->guest_pkru_valid = true;
9039                         __write_pkru(vmx->host_pkru);
9040                 } else
9041                         vmx->guest_pkru_valid = false;
9042         }
9043
9044         /*
9045          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9046          * we did not inject a still-pending event to L1 now because of
9047          * nested_run_pending, we need to re-enable this bit.
9048          */
9049         if (vmx->nested.nested_run_pending)
9050                 kvm_make_request(KVM_REQ_EVENT, vcpu);
9051
9052         vmx->nested.nested_run_pending = 0;
9053
9054         vmx_complete_atomic_exit(vmx);
9055         vmx_recover_nmi_blocking(vmx);
9056         vmx_complete_interrupts(vmx);
9057 }
9058 STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
9059
9060 static void vmx_switch_vmcs(struct kvm_vcpu *vcpu, struct loaded_vmcs *vmcs)
9061 {
9062         struct vcpu_vmx *vmx = to_vmx(vcpu);
9063         int cpu;
9064
9065         if (vmx->loaded_vmcs == vmcs)
9066                 return;
9067
9068         cpu = get_cpu();
9069         vmx->loaded_vmcs = vmcs;
9070         vmx_vcpu_put(vcpu);
9071         vmx_vcpu_load(vcpu, cpu);
9072         vcpu->cpu = cpu;
9073         put_cpu();
9074 }
9075
9076 /*
9077  * Ensure that the current vmcs of the logical processor is the
9078  * vmcs01 of the vcpu before calling free_nested().
9079  */
9080 static void vmx_free_vcpu_nested(struct kvm_vcpu *vcpu)
9081 {
9082        struct vcpu_vmx *vmx = to_vmx(vcpu);
9083        int r;
9084
9085        r = vcpu_load(vcpu);
9086        BUG_ON(r);
9087        vmx_switch_vmcs(vcpu, &vmx->vmcs01);
9088        free_nested(vmx);
9089        vcpu_put(vcpu);
9090 }
9091
9092 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
9093 {
9094         struct vcpu_vmx *vmx = to_vmx(vcpu);
9095
9096         if (enable_pml)
9097                 vmx_destroy_pml_buffer(vmx);
9098         free_vpid(vmx->vpid);
9099         leave_guest_mode(vcpu);
9100         vmx_free_vcpu_nested(vcpu);
9101         free_loaded_vmcs(vmx->loaded_vmcs);
9102         kfree(vmx->guest_msrs);
9103         kvm_vcpu_uninit(vcpu);
9104         kmem_cache_free(kvm_vcpu_cache, vmx);
9105 }
9106
9107 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
9108 {
9109         int err;
9110         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
9111         int cpu;
9112
9113         if (!vmx)
9114                 return ERR_PTR(-ENOMEM);
9115
9116         vmx->vpid = allocate_vpid();
9117
9118         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
9119         if (err)
9120                 goto free_vcpu;
9121
9122         err = -ENOMEM;
9123
9124         /*
9125          * If PML is turned on, failure on enabling PML just results in failure
9126          * of creating the vcpu, therefore we can simplify PML logic (by
9127          * avoiding dealing with cases, such as enabling PML partially on vcpus
9128          * for the guest, etc.
9129          */
9130         if (enable_pml) {
9131                 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
9132                 if (!vmx->pml_pg)
9133                         goto uninit_vcpu;
9134         }
9135
9136         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
9137         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
9138                      > PAGE_SIZE);
9139
9140         if (!vmx->guest_msrs)
9141                 goto free_pml;
9142
9143         vmx->loaded_vmcs = &vmx->vmcs01;
9144         vmx->loaded_vmcs->vmcs = alloc_vmcs();
9145         vmx->loaded_vmcs->shadow_vmcs = NULL;
9146         if (!vmx->loaded_vmcs->vmcs)
9147                 goto free_msrs;
9148         loaded_vmcs_init(vmx->loaded_vmcs);
9149
9150         cpu = get_cpu();
9151         vmx_vcpu_load(&vmx->vcpu, cpu);
9152         vmx->vcpu.cpu = cpu;
9153         err = vmx_vcpu_setup(vmx);
9154         vmx_vcpu_put(&vmx->vcpu);
9155         put_cpu();
9156         if (err)
9157                 goto free_vmcs;
9158         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9159                 err = alloc_apic_access_page(kvm);
9160                 if (err)
9161                         goto free_vmcs;
9162         }
9163
9164         if (enable_ept) {
9165                 if (!kvm->arch.ept_identity_map_addr)
9166                         kvm->arch.ept_identity_map_addr =
9167                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
9168                 err = init_rmode_identity_map(kvm);
9169                 if (err)
9170                         goto free_vmcs;
9171         }
9172
9173         if (nested) {
9174                 nested_vmx_setup_ctls_msrs(vmx);
9175                 vmx->nested.vpid02 = allocate_vpid();
9176         }
9177
9178         vmx->nested.posted_intr_nv = -1;
9179         vmx->nested.current_vmptr = -1ull;
9180         vmx->nested.current_vmcs12 = NULL;
9181
9182         vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
9183
9184         return &vmx->vcpu;
9185
9186 free_vmcs:
9187         free_vpid(vmx->nested.vpid02);
9188         free_loaded_vmcs(vmx->loaded_vmcs);
9189 free_msrs:
9190         kfree(vmx->guest_msrs);
9191 free_pml:
9192         vmx_destroy_pml_buffer(vmx);
9193 uninit_vcpu:
9194         kvm_vcpu_uninit(&vmx->vcpu);
9195 free_vcpu:
9196         free_vpid(vmx->vpid);
9197         kmem_cache_free(kvm_vcpu_cache, vmx);
9198         return ERR_PTR(err);
9199 }
9200
9201 static void __init vmx_check_processor_compat(void *rtn)
9202 {
9203         struct vmcs_config vmcs_conf;
9204
9205         *(int *)rtn = 0;
9206         if (setup_vmcs_config(&vmcs_conf) < 0)
9207                 *(int *)rtn = -EIO;
9208         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
9209                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
9210                                 smp_processor_id());
9211                 *(int *)rtn = -EIO;
9212         }
9213 }
9214
9215 static int get_ept_level(void)
9216 {
9217         return VMX_EPT_DEFAULT_GAW + 1;
9218 }
9219
9220 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
9221 {
9222         u8 cache;
9223         u64 ipat = 0;
9224
9225         /* For VT-d and EPT combination
9226          * 1. MMIO: always map as UC
9227          * 2. EPT with VT-d:
9228          *   a. VT-d without snooping control feature: can't guarantee the
9229          *      result, try to trust guest.
9230          *   b. VT-d with snooping control feature: snooping control feature of
9231          *      VT-d engine can guarantee the cache correctness. Just set it
9232          *      to WB to keep consistent with host. So the same as item 3.
9233          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9234          *    consistent with host MTRR
9235          */
9236         if (is_mmio) {
9237                 cache = MTRR_TYPE_UNCACHABLE;
9238                 goto exit;
9239         }
9240
9241         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
9242                 ipat = VMX_EPT_IPAT_BIT;
9243                 cache = MTRR_TYPE_WRBACK;
9244                 goto exit;
9245         }
9246
9247         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
9248                 ipat = VMX_EPT_IPAT_BIT;
9249                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
9250                         cache = MTRR_TYPE_WRBACK;
9251                 else
9252                         cache = MTRR_TYPE_UNCACHABLE;
9253                 goto exit;
9254         }
9255
9256         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9257
9258 exit:
9259         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9260 }
9261
9262 static int vmx_get_lpage_level(void)
9263 {
9264         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9265                 return PT_DIRECTORY_LEVEL;
9266         else
9267                 /* For shadow and EPT supported 1GB page */
9268                 return PT_PDPE_LEVEL;
9269 }
9270
9271 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9272 {
9273         /*
9274          * These bits in the secondary execution controls field
9275          * are dynamic, the others are mostly based on the hypervisor
9276          * architecture and the guest's CPUID.  Do not touch the
9277          * dynamic bits.
9278          */
9279         u32 mask =
9280                 SECONDARY_EXEC_SHADOW_VMCS |
9281                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9282                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9283
9284         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9285
9286         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9287                      (new_ctl & ~mask) | (cur_ctl & mask));
9288 }
9289
9290 /*
9291  * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9292  * (indicating "allowed-1") if they are supported in the guest's CPUID.
9293  */
9294 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
9295 {
9296         struct vcpu_vmx *vmx = to_vmx(vcpu);
9297         struct kvm_cpuid_entry2 *entry;
9298
9299         vmx->nested.nested_vmx_cr0_fixed1 = 0xffffffff;
9300         vmx->nested.nested_vmx_cr4_fixed1 = X86_CR4_PCE;
9301
9302 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do {            \
9303         if (entry && (entry->_reg & (_cpuid_mask)))                     \
9304                 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask);       \
9305 } while (0)
9306
9307         entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
9308         cr4_fixed1_update(X86_CR4_VME,        edx, bit(X86_FEATURE_VME));
9309         cr4_fixed1_update(X86_CR4_PVI,        edx, bit(X86_FEATURE_VME));
9310         cr4_fixed1_update(X86_CR4_TSD,        edx, bit(X86_FEATURE_TSC));
9311         cr4_fixed1_update(X86_CR4_DE,         edx, bit(X86_FEATURE_DE));
9312         cr4_fixed1_update(X86_CR4_PSE,        edx, bit(X86_FEATURE_PSE));
9313         cr4_fixed1_update(X86_CR4_PAE,        edx, bit(X86_FEATURE_PAE));
9314         cr4_fixed1_update(X86_CR4_MCE,        edx, bit(X86_FEATURE_MCE));
9315         cr4_fixed1_update(X86_CR4_PGE,        edx, bit(X86_FEATURE_PGE));
9316         cr4_fixed1_update(X86_CR4_OSFXSR,     edx, bit(X86_FEATURE_FXSR));
9317         cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
9318         cr4_fixed1_update(X86_CR4_VMXE,       ecx, bit(X86_FEATURE_VMX));
9319         cr4_fixed1_update(X86_CR4_SMXE,       ecx, bit(X86_FEATURE_SMX));
9320         cr4_fixed1_update(X86_CR4_PCIDE,      ecx, bit(X86_FEATURE_PCID));
9321         cr4_fixed1_update(X86_CR4_OSXSAVE,    ecx, bit(X86_FEATURE_XSAVE));
9322
9323         entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9324         cr4_fixed1_update(X86_CR4_FSGSBASE,   ebx, bit(X86_FEATURE_FSGSBASE));
9325         cr4_fixed1_update(X86_CR4_SMEP,       ebx, bit(X86_FEATURE_SMEP));
9326         cr4_fixed1_update(X86_CR4_SMAP,       ebx, bit(X86_FEATURE_SMAP));
9327         cr4_fixed1_update(X86_CR4_PKE,        ecx, bit(X86_FEATURE_PKU));
9328         /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9329         cr4_fixed1_update(bit(11),            ecx, bit(2));
9330
9331 #undef cr4_fixed1_update
9332 }
9333
9334 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9335 {
9336         struct kvm_cpuid_entry2 *best;
9337         struct vcpu_vmx *vmx = to_vmx(vcpu);
9338         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9339
9340         if (vmx_rdtscp_supported()) {
9341                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9342                 if (!rdtscp_enabled)
9343                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9344
9345                 if (nested) {
9346                         if (rdtscp_enabled)
9347                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9348                                         SECONDARY_EXEC_RDTSCP;
9349                         else
9350                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9351                                         ~SECONDARY_EXEC_RDTSCP;
9352                 }
9353         }
9354
9355         /* Exposing INVPCID only when PCID is exposed */
9356         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9357         if (vmx_invpcid_supported() &&
9358             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9359             !guest_cpuid_has_pcid(vcpu))) {
9360                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9361
9362                 if (best)
9363                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9364         }
9365
9366         if (cpu_has_secondary_exec_ctrls())
9367                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9368
9369         if (nested_vmx_allowed(vcpu))
9370                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
9371                         FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9372         else
9373                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
9374                         ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
9375
9376         if (nested_vmx_allowed(vcpu))
9377                 nested_vmx_cr_fixed1_bits_update(vcpu);
9378 }
9379
9380 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9381 {
9382         if (func == 1 && nested)
9383                 entry->ecx |= bit(X86_FEATURE_VMX);
9384 }
9385
9386 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9387                 struct x86_exception *fault)
9388 {
9389         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9390         struct vcpu_vmx *vmx = to_vmx(vcpu);
9391         u32 exit_reason;
9392         unsigned long exit_qualification = vcpu->arch.exit_qualification;
9393
9394         if (vmx->nested.pml_full) {
9395                 exit_reason = EXIT_REASON_PML_FULL;
9396                 vmx->nested.pml_full = false;
9397                 exit_qualification &= INTR_INFO_UNBLOCK_NMI;
9398         } else if (fault->error_code & PFERR_RSVD_MASK)
9399                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9400         else
9401                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9402
9403         nested_vmx_vmexit(vcpu, exit_reason, 0, exit_qualification);
9404         vmcs12->guest_physical_address = fault->address;
9405 }
9406
9407 static bool nested_ept_ad_enabled(struct kvm_vcpu *vcpu)
9408 {
9409         return nested_ept_get_cr3(vcpu) & VMX_EPT_AD_ENABLE_BIT;
9410 }
9411
9412 /* Callbacks for nested_ept_init_mmu_context: */
9413
9414 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9415 {
9416         /* return the page table to be shadowed - in our case, EPT12 */
9417         return get_vmcs12(vcpu)->ept_pointer;
9418 }
9419
9420 static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9421 {
9422         bool wants_ad;
9423
9424         WARN_ON(mmu_is_nested(vcpu));
9425         wants_ad = nested_ept_ad_enabled(vcpu);
9426         if (wants_ad && !enable_ept_ad_bits)
9427                 return 1;
9428
9429         kvm_mmu_unload(vcpu);
9430         kvm_init_shadow_ept_mmu(vcpu,
9431                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9432                         VMX_EPT_EXECUTE_ONLY_BIT,
9433                         wants_ad);
9434         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9435         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9436         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9437
9438         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9439         return 0;
9440 }
9441
9442 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9443 {
9444         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9445 }
9446
9447 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9448                                             u16 error_code)
9449 {
9450         bool inequality, bit;
9451
9452         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9453         inequality =
9454                 (error_code & vmcs12->page_fault_error_code_mask) !=
9455                  vmcs12->page_fault_error_code_match;
9456         return inequality ^ bit;
9457 }
9458
9459 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9460                 struct x86_exception *fault)
9461 {
9462         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9463
9464         WARN_ON(!is_guest_mode(vcpu));
9465
9466         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9467                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9468                                   vmcs_read32(VM_EXIT_INTR_INFO),
9469                                   vmcs_readl(EXIT_QUALIFICATION));
9470         else
9471                 kvm_inject_page_fault(vcpu, fault);
9472 }
9473
9474 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9475                                                struct vmcs12 *vmcs12);
9476
9477 static void nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9478                                         struct vmcs12 *vmcs12)
9479 {
9480         struct vcpu_vmx *vmx = to_vmx(vcpu);
9481         u64 hpa;
9482
9483         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9484                 /*
9485                  * Translate L1 physical address to host physical
9486                  * address for vmcs02. Keep the page pinned, so this
9487                  * physical address remains valid. We keep a reference
9488                  * to it so we can release it later.
9489                  */
9490                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9491                         nested_release_page(vmx->nested.apic_access_page);
9492                 vmx->nested.apic_access_page =
9493                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9494                 /*
9495                  * If translation failed, no matter: This feature asks
9496                  * to exit when accessing the given address, and if it
9497                  * can never be accessed, this feature won't do
9498                  * anything anyway.
9499                  */
9500                 if (vmx->nested.apic_access_page) {
9501                         hpa = page_to_phys(vmx->nested.apic_access_page);
9502                         vmcs_write64(APIC_ACCESS_ADDR, hpa);
9503                 } else {
9504                         vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
9505                                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9506                 }
9507         } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9508                    cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9509                 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
9510                               SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
9511                 kvm_vcpu_reload_apic_access_page(vcpu);
9512         }
9513
9514         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9515                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9516                         nested_release_page(vmx->nested.virtual_apic_page);
9517                 vmx->nested.virtual_apic_page =
9518                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9519
9520                 /*
9521                  * If translation failed, VM entry will fail because
9522                  * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9523                  * Failing the vm entry is _not_ what the processor
9524                  * does but it's basically the only possibility we
9525                  * have.  We could still enter the guest if CR8 load
9526                  * exits are enabled, CR8 store exits are enabled, and
9527                  * virtualize APIC access is disabled; in this case
9528                  * the processor would never use the TPR shadow and we
9529                  * could simply clear the bit from the execution
9530                  * control.  But such a configuration is useless, so
9531                  * let's keep the code simple.
9532                  */
9533                 if (vmx->nested.virtual_apic_page) {
9534                         hpa = page_to_phys(vmx->nested.virtual_apic_page);
9535                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, hpa);
9536                 }
9537         }
9538
9539         if (nested_cpu_has_posted_intr(vmcs12)) {
9540                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9541                         kunmap(vmx->nested.pi_desc_page);
9542                         nested_release_page(vmx->nested.pi_desc_page);
9543                 }
9544                 vmx->nested.pi_desc_page =
9545                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9546                 vmx->nested.pi_desc =
9547                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9548                 if (!vmx->nested.pi_desc) {
9549                         nested_release_page_clean(vmx->nested.pi_desc_page);
9550                         return;
9551                 }
9552                 vmx->nested.pi_desc =
9553                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9554                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9555                         (PAGE_SIZE - 1)));
9556                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9557                         page_to_phys(vmx->nested.pi_desc_page) +
9558                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9559                         (PAGE_SIZE - 1)));
9560         }
9561         if (cpu_has_vmx_msr_bitmap() &&
9562             nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS) &&
9563             nested_vmx_merge_msr_bitmap(vcpu, vmcs12))
9564                 ;
9565         else
9566                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
9567                                 CPU_BASED_USE_MSR_BITMAPS);
9568 }
9569
9570 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9571 {
9572         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9573         struct vcpu_vmx *vmx = to_vmx(vcpu);
9574
9575         if (vcpu->arch.virtual_tsc_khz == 0)
9576                 return;
9577
9578         /* Make sure short timeouts reliably trigger an immediate vmexit.
9579          * hrtimer_start does not guarantee this. */
9580         if (preemption_timeout <= 1) {
9581                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9582                 return;
9583         }
9584
9585         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9586         preemption_timeout *= 1000000;
9587         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9588         hrtimer_start(&vmx->nested.preemption_timer,
9589                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9590 }
9591
9592 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9593                                                 struct vmcs12 *vmcs12)
9594 {
9595         int maxphyaddr;
9596         u64 addr;
9597
9598         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9599                 return 0;
9600
9601         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9602                 WARN_ON(1);
9603                 return -EINVAL;
9604         }
9605         maxphyaddr = cpuid_maxphyaddr(vcpu);
9606
9607         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9608            ((addr + PAGE_SIZE) >> maxphyaddr))
9609                 return -EINVAL;
9610
9611         return 0;
9612 }
9613
9614 /*
9615  * Merge L0's and L1's MSR bitmap, return false to indicate that
9616  * we do not use the hardware.
9617  */
9618 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9619                                                struct vmcs12 *vmcs12)
9620 {
9621         int msr;
9622         struct page *page;
9623         unsigned long *msr_bitmap_l1;
9624         unsigned long *msr_bitmap_l0 = to_vmx(vcpu)->nested.msr_bitmap;
9625
9626         /* This shortcut is ok because we support only x2APIC MSRs so far. */
9627         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9628                 return false;
9629
9630         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9631         if (!page)
9632                 return false;
9633         msr_bitmap_l1 = (unsigned long *)kmap(page);
9634
9635         memset(msr_bitmap_l0, 0xff, PAGE_SIZE);
9636
9637         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9638                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9639                         for (msr = 0x800; msr <= 0x8ff; msr++)
9640                                 nested_vmx_disable_intercept_for_msr(
9641                                         msr_bitmap_l1, msr_bitmap_l0,
9642                                         msr, MSR_TYPE_R);
9643
9644                 nested_vmx_disable_intercept_for_msr(
9645                                 msr_bitmap_l1, msr_bitmap_l0,
9646                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9647                                 MSR_TYPE_R | MSR_TYPE_W);
9648
9649                 if (nested_cpu_has_vid(vmcs12)) {
9650                         nested_vmx_disable_intercept_for_msr(
9651                                 msr_bitmap_l1, msr_bitmap_l0,
9652                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9653                                 MSR_TYPE_W);
9654                         nested_vmx_disable_intercept_for_msr(
9655                                 msr_bitmap_l1, msr_bitmap_l0,
9656                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9657                                 MSR_TYPE_W);
9658                 }
9659         }
9660         kunmap(page);
9661         nested_release_page_clean(page);
9662
9663         return true;
9664 }
9665
9666 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9667                                            struct vmcs12 *vmcs12)
9668 {
9669         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9670             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9671             !nested_cpu_has_vid(vmcs12) &&
9672             !nested_cpu_has_posted_intr(vmcs12))
9673                 return 0;
9674
9675         /*
9676          * If virtualize x2apic mode is enabled,
9677          * virtualize apic access must be disabled.
9678          */
9679         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9680             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9681                 return -EINVAL;
9682
9683         /*
9684          * If virtual interrupt delivery is enabled,
9685          * we must exit on external interrupts.
9686          */
9687         if (nested_cpu_has_vid(vmcs12) &&
9688            !nested_exit_on_intr(vcpu))
9689                 return -EINVAL;
9690
9691         /*
9692          * bits 15:8 should be zero in posted_intr_nv,
9693          * the descriptor address has been already checked
9694          * in nested_get_vmcs12_pages.
9695          */
9696         if (nested_cpu_has_posted_intr(vmcs12) &&
9697            (!nested_cpu_has_vid(vmcs12) ||
9698             !nested_exit_intr_ack_set(vcpu) ||
9699             vmcs12->posted_intr_nv & 0xff00))
9700                 return -EINVAL;
9701
9702         /* tpr shadow is needed by all apicv features. */
9703         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9704                 return -EINVAL;
9705
9706         return 0;
9707 }
9708
9709 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9710                                        unsigned long count_field,
9711                                        unsigned long addr_field)
9712 {
9713         int maxphyaddr;
9714         u64 count, addr;
9715
9716         if (vmcs12_read_any(vcpu, count_field, &count) ||
9717             vmcs12_read_any(vcpu, addr_field, &addr)) {
9718                 WARN_ON(1);
9719                 return -EINVAL;
9720         }
9721         if (count == 0)
9722                 return 0;
9723         maxphyaddr = cpuid_maxphyaddr(vcpu);
9724         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9725             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9726                 pr_debug_ratelimited(
9727                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9728                         addr_field, maxphyaddr, count, addr);
9729                 return -EINVAL;
9730         }
9731         return 0;
9732 }
9733
9734 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9735                                                 struct vmcs12 *vmcs12)
9736 {
9737         if (vmcs12->vm_exit_msr_load_count == 0 &&
9738             vmcs12->vm_exit_msr_store_count == 0 &&
9739             vmcs12->vm_entry_msr_load_count == 0)
9740                 return 0; /* Fast path */
9741         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9742                                         VM_EXIT_MSR_LOAD_ADDR) ||
9743             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9744                                         VM_EXIT_MSR_STORE_ADDR) ||
9745             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9746                                         VM_ENTRY_MSR_LOAD_ADDR))
9747                 return -EINVAL;
9748         return 0;
9749 }
9750
9751 static int nested_vmx_check_pml_controls(struct kvm_vcpu *vcpu,
9752                                          struct vmcs12 *vmcs12)
9753 {
9754         u64 address = vmcs12->pml_address;
9755         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9756
9757         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_PML)) {
9758                 if (!nested_cpu_has_ept(vmcs12) ||
9759                     !IS_ALIGNED(address, 4096)  ||
9760                     address >> maxphyaddr)
9761                         return -EINVAL;
9762         }
9763
9764         return 0;
9765 }
9766
9767 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9768                                        struct vmx_msr_entry *e)
9769 {
9770         /* x2APIC MSR accesses are not allowed */
9771         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9772                 return -EINVAL;
9773         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9774             e->index == MSR_IA32_UCODE_REV)
9775                 return -EINVAL;
9776         if (e->reserved != 0)
9777                 return -EINVAL;
9778         return 0;
9779 }
9780
9781 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9782                                      struct vmx_msr_entry *e)
9783 {
9784         if (e->index == MSR_FS_BASE ||
9785             e->index == MSR_GS_BASE ||
9786             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9787             nested_vmx_msr_check_common(vcpu, e))
9788                 return -EINVAL;
9789         return 0;
9790 }
9791
9792 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9793                                       struct vmx_msr_entry *e)
9794 {
9795         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9796             nested_vmx_msr_check_common(vcpu, e))
9797                 return -EINVAL;
9798         return 0;
9799 }
9800
9801 /*
9802  * Load guest's/host's msr at nested entry/exit.
9803  * return 0 for success, entry index for failure.
9804  */
9805 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9806 {
9807         u32 i;
9808         struct vmx_msr_entry e;
9809         struct msr_data msr;
9810
9811         msr.host_initiated = false;
9812         for (i = 0; i < count; i++) {
9813                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9814                                         &e, sizeof(e))) {
9815                         pr_debug_ratelimited(
9816                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9817                                 __func__, i, gpa + i * sizeof(e));
9818                         goto fail;
9819                 }
9820                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9821                         pr_debug_ratelimited(
9822                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9823                                 __func__, i, e.index, e.reserved);
9824                         goto fail;
9825                 }
9826                 msr.index = e.index;
9827                 msr.data = e.value;
9828                 if (kvm_set_msr(vcpu, &msr)) {
9829                         pr_debug_ratelimited(
9830                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9831                                 __func__, i, e.index, e.value);
9832                         goto fail;
9833                 }
9834         }
9835         return 0;
9836 fail:
9837         return i + 1;
9838 }
9839
9840 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9841 {
9842         u32 i;
9843         struct vmx_msr_entry e;
9844
9845         for (i = 0; i < count; i++) {
9846                 struct msr_data msr_info;
9847                 if (kvm_vcpu_read_guest(vcpu,
9848                                         gpa + i * sizeof(e),
9849                                         &e, 2 * sizeof(u32))) {
9850                         pr_debug_ratelimited(
9851                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9852                                 __func__, i, gpa + i * sizeof(e));
9853                         return -EINVAL;
9854                 }
9855                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9856                         pr_debug_ratelimited(
9857                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9858                                 __func__, i, e.index, e.reserved);
9859                         return -EINVAL;
9860                 }
9861                 msr_info.host_initiated = false;
9862                 msr_info.index = e.index;
9863                 if (kvm_get_msr(vcpu, &msr_info)) {
9864                         pr_debug_ratelimited(
9865                                 "%s cannot read MSR (%u, 0x%x)\n",
9866                                 __func__, i, e.index);
9867                         return -EINVAL;
9868                 }
9869                 if (kvm_vcpu_write_guest(vcpu,
9870                                          gpa + i * sizeof(e) +
9871                                              offsetof(struct vmx_msr_entry, value),
9872                                          &msr_info.data, sizeof(msr_info.data))) {
9873                         pr_debug_ratelimited(
9874                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9875                                 __func__, i, e.index, msr_info.data);
9876                         return -EINVAL;
9877                 }
9878         }
9879         return 0;
9880 }
9881
9882 static bool nested_cr3_valid(struct kvm_vcpu *vcpu, unsigned long val)
9883 {
9884         unsigned long invalid_mask;
9885
9886         invalid_mask = (~0ULL) << cpuid_maxphyaddr(vcpu);
9887         return (val & invalid_mask) == 0;
9888 }
9889
9890 /*
9891  * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9892  * emulating VM entry into a guest with EPT enabled.
9893  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9894  * is assigned to entry_failure_code on failure.
9895  */
9896 static int nested_vmx_load_cr3(struct kvm_vcpu *vcpu, unsigned long cr3, bool nested_ept,
9897                                u32 *entry_failure_code)
9898 {
9899         if (cr3 != kvm_read_cr3(vcpu) || (!nested_ept && pdptrs_changed(vcpu))) {
9900                 if (!nested_cr3_valid(vcpu, cr3)) {
9901                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
9902                         return 1;
9903                 }
9904
9905                 /*
9906                  * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9907                  * must not be dereferenced.
9908                  */
9909                 if (!is_long_mode(vcpu) && is_pae(vcpu) && is_paging(vcpu) &&
9910                     !nested_ept) {
9911                         if (!load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3)) {
9912                                 *entry_failure_code = ENTRY_FAIL_PDPTE;
9913                                 return 1;
9914                         }
9915                 }
9916
9917                 vcpu->arch.cr3 = cr3;
9918                 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
9919         }
9920
9921         kvm_mmu_reset_context(vcpu);
9922         return 0;
9923 }
9924
9925 /*
9926  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9927  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9928  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9929  * guest in a way that will both be appropriate to L1's requests, and our
9930  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9931  * function also has additional necessary side-effects, like setting various
9932  * vcpu->arch fields.
9933  * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9934  * is assigned to entry_failure_code on failure.
9935  */
9936 static int prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
9937                           bool from_vmentry, u32 *entry_failure_code)
9938 {
9939         struct vcpu_vmx *vmx = to_vmx(vcpu);
9940         u32 exec_control, vmcs12_exec_ctrl;
9941
9942         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9943         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9944         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9945         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9946         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9947         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9948         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9949         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9950         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9951         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9952         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9953         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9954         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9955         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9956         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9957         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9958         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9959         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9960         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9961         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9962         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9963         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9964         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9965         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9966         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9967         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9968         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9969         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9970         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9971         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9972         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9973         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9974         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9975         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9976         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9977         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9978
9979         if (from_vmentry &&
9980             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS)) {
9981                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9982                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9983         } else {
9984                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9985                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9986         }
9987         if (from_vmentry) {
9988                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9989                              vmcs12->vm_entry_intr_info_field);
9990                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9991                              vmcs12->vm_entry_exception_error_code);
9992                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9993                              vmcs12->vm_entry_instruction_len);
9994                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9995                              vmcs12->guest_interruptibility_info);
9996         } else {
9997                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
9998         }
9999         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
10000         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
10001         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
10002                 vmcs12->guest_pending_dbg_exceptions);
10003         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
10004         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
10005
10006         if (nested_cpu_has_xsaves(vmcs12))
10007                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
10008         vmcs_write64(VMCS_LINK_POINTER, -1ull);
10009
10010         exec_control = vmcs12->pin_based_vm_exec_control;
10011
10012         /* Preemption timer setting is only taken from vmcs01.  */
10013         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10014         exec_control |= vmcs_config.pin_based_exec_ctrl;
10015         if (vmx->hv_deadline_tsc == -1)
10016                 exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
10017
10018         /* Posted interrupts setting is only taken from vmcs12.  */
10019         if (nested_cpu_has_posted_intr(vmcs12)) {
10020                 /*
10021                  * Note that we use L0's vector here and in
10022                  * vmx_deliver_nested_posted_interrupt.
10023                  */
10024                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
10025                 vmx->nested.pi_pending = false;
10026                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
10027         } else {
10028                 exec_control &= ~PIN_BASED_POSTED_INTR;
10029         }
10030
10031         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
10032
10033         vmx->nested.preemption_timer_expired = false;
10034         if (nested_cpu_has_preemption_timer(vmcs12))
10035                 vmx_start_preemption_timer(vcpu);
10036
10037         /*
10038          * Whether page-faults are trapped is determined by a combination of
10039          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10040          * If enable_ept, L0 doesn't care about page faults and we should
10041          * set all of these to L1's desires. However, if !enable_ept, L0 does
10042          * care about (at least some) page faults, and because it is not easy
10043          * (if at all possible?) to merge L0 and L1's desires, we simply ask
10044          * to exit on each and every L2 page fault. This is done by setting
10045          * MASK=MATCH=0 and (see below) EB.PF=1.
10046          * Note that below we don't need special code to set EB.PF beyond the
10047          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10048          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10049          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10050          *
10051          * A problem with this approach (when !enable_ept) is that L1 may be
10052          * injected with more page faults than it asked for. This could have
10053          * caused problems, but in practice existing hypervisors don't care.
10054          * To fix this, we will need to emulate the PFEC checking (on the L1
10055          * page tables), using walk_addr(), when injecting PFs to L1.
10056          */
10057         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
10058                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
10059         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
10060                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
10061
10062         if (cpu_has_secondary_exec_ctrls()) {
10063                 exec_control = vmx_secondary_exec_control(vmx);
10064
10065                 /* Take the following fields only from vmcs12 */
10066                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
10067                                   SECONDARY_EXEC_RDTSCP |
10068                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
10069                                   SECONDARY_EXEC_APIC_REGISTER_VIRT);
10070                 if (nested_cpu_has(vmcs12,
10071                                    CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)) {
10072                         vmcs12_exec_ctrl = vmcs12->secondary_vm_exec_control &
10073                                 ~SECONDARY_EXEC_ENABLE_PML;
10074                         exec_control |= vmcs12_exec_ctrl;
10075                 }
10076
10077                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
10078                         vmcs_write64(EOI_EXIT_BITMAP0,
10079                                 vmcs12->eoi_exit_bitmap0);
10080                         vmcs_write64(EOI_EXIT_BITMAP1,
10081                                 vmcs12->eoi_exit_bitmap1);
10082                         vmcs_write64(EOI_EXIT_BITMAP2,
10083                                 vmcs12->eoi_exit_bitmap2);
10084                         vmcs_write64(EOI_EXIT_BITMAP3,
10085                                 vmcs12->eoi_exit_bitmap3);
10086                         vmcs_write16(GUEST_INTR_STATUS,
10087                                 vmcs12->guest_intr_status);
10088                 }
10089
10090                 /*
10091                  * Write an illegal value to APIC_ACCESS_ADDR. Later,
10092                  * nested_get_vmcs12_pages will either fix it up or
10093                  * remove the VM execution control.
10094                  */
10095                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
10096                         vmcs_write64(APIC_ACCESS_ADDR, -1ull);
10097
10098                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
10099         }
10100
10101
10102         /*
10103          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10104          * Some constant fields are set here by vmx_set_constant_host_state().
10105          * Other fields are different per CPU, and will be set later when
10106          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10107          */
10108         vmx_set_constant_host_state(vmx);
10109
10110         /*
10111          * Set the MSR load/store lists to match L0's settings.
10112          */
10113         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
10114         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10115         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
10116         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
10117         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
10118
10119         /*
10120          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10121          * entry, but only if the current (host) sp changed from the value
10122          * we wrote last (vmx->host_rsp). This cache is no longer relevant
10123          * if we switch vmcs, and rather than hold a separate cache per vmcs,
10124          * here we just force the write to happen on entry.
10125          */
10126         vmx->host_rsp = 0;
10127
10128         exec_control = vmx_exec_control(vmx); /* L0's desires */
10129         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
10130         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
10131         exec_control &= ~CPU_BASED_TPR_SHADOW;
10132         exec_control |= vmcs12->cpu_based_vm_exec_control;
10133
10134         /*
10135          * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10136          * nested_get_vmcs12_pages can't fix it up, the illegal value
10137          * will result in a VM entry failure.
10138          */
10139         if (exec_control & CPU_BASED_TPR_SHADOW) {
10140                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, -1ull);
10141                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
10142         }
10143
10144         /*
10145          * Merging of IO bitmap not currently supported.
10146          * Rather, exit every time.
10147          */
10148         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
10149         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
10150
10151         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
10152
10153         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10154          * bitwise-or of what L1 wants to trap for L2, and what we want to
10155          * trap. Note that CR0.TS also needs updating - we do this later.
10156          */
10157         update_exception_bitmap(vcpu);
10158         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
10159         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10160
10161         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10162          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10163          * bits are further modified by vmx_set_efer() below.
10164          */
10165         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
10166
10167         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10168          * emulated by vmx_set_efer(), below.
10169          */
10170         vm_entry_controls_init(vmx,
10171                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
10172                         ~VM_ENTRY_IA32E_MODE) |
10173                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
10174
10175         if (from_vmentry &&
10176             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)) {
10177                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
10178                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
10179         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
10180                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
10181         }
10182
10183         set_cr4_guest_host_mask(vmx);
10184
10185         if (from_vmentry &&
10186             vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
10187                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
10188
10189         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
10190                 vmcs_write64(TSC_OFFSET,
10191                         vcpu->arch.tsc_offset + vmcs12->tsc_offset);
10192         else
10193                 vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
10194         if (kvm_has_tsc_control)
10195                 decache_tsc_multiplier(vmx);
10196
10197         if (enable_vpid) {
10198                 /*
10199                  * There is no direct mapping between vpid02 and vpid12, the
10200                  * vpid02 is per-vCPU for L0 and reused while the value of
10201                  * vpid12 is changed w/ one invvpid during nested vmentry.
10202                  * The vpid12 is allocated by L1 for L2, so it will not
10203                  * influence global bitmap(for vpid01 and vpid02 allocation)
10204                  * even if spawn a lot of nested vCPUs.
10205                  */
10206                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
10207                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
10208                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
10209                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
10210                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
10211                         }
10212                 } else {
10213                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
10214                         vmx_flush_tlb(vcpu);
10215                 }
10216
10217         }
10218
10219         if (enable_pml) {
10220                 /*
10221                  * Conceptually we want to copy the PML address and index from
10222                  * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10223                  * since we always flush the log on each vmexit, this happens
10224                  * to be equivalent to simply resetting the fields in vmcs02.
10225                  */
10226                 ASSERT(vmx->pml_pg);
10227                 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
10228                 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
10229         }
10230
10231         if (nested_cpu_has_ept(vmcs12)) {
10232                 if (nested_ept_init_mmu_context(vcpu)) {
10233                         *entry_failure_code = ENTRY_FAIL_DEFAULT;
10234                         return 1;
10235                 }
10236         } else if (nested_cpu_has2(vmcs12,
10237                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
10238                 vmx_flush_tlb_ept_only(vcpu);
10239         }
10240
10241         /*
10242          * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10243          * bits which we consider mandatory enabled.
10244          * The CR0_READ_SHADOW is what L2 should have expected to read given
10245          * the specifications by L1; It's not enough to take
10246          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10247          * have more bits than L1 expected.
10248          */
10249         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
10250         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
10251
10252         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
10253         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
10254
10255         if (from_vmentry &&
10256             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER))
10257                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
10258         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
10259                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10260         else
10261                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10262         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10263         vmx_set_efer(vcpu, vcpu->arch.efer);
10264
10265         /* Shadow page tables on either EPT or shadow page tables. */
10266         if (nested_vmx_load_cr3(vcpu, vmcs12->guest_cr3, nested_cpu_has_ept(vmcs12),
10267                                 entry_failure_code))
10268                 return 1;
10269
10270         if (!enable_ept)
10271                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
10272
10273         /*
10274          * L1 may access the L2's PDPTR, so save them to construct vmcs12
10275          */
10276         if (enable_ept) {
10277                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
10278                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
10279                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
10280                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
10281         }
10282
10283         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
10284         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
10285         return 0;
10286 }
10287
10288 static int check_vmentry_prereqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10289 {
10290         struct vcpu_vmx *vmx = to_vmx(vcpu);
10291
10292         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
10293             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT)
10294                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10295
10296         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12))
10297                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10298
10299         if (nested_vmx_check_apicv_controls(vcpu, vmcs12))
10300                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10301
10302         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12))
10303                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10304
10305         if (nested_vmx_check_pml_controls(vcpu, vmcs12))
10306                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10307
10308         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
10309                                 vmx->nested.nested_vmx_procbased_ctls_low,
10310                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
10311             (nested_cpu_has(vmcs12, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
10312              !vmx_control_verify(vmcs12->secondary_vm_exec_control,
10313                                  vmx->nested.nested_vmx_secondary_ctls_low,
10314                                  vmx->nested.nested_vmx_secondary_ctls_high)) ||
10315             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
10316                                 vmx->nested.nested_vmx_pinbased_ctls_low,
10317                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
10318             !vmx_control_verify(vmcs12->vm_exit_controls,
10319                                 vmx->nested.nested_vmx_exit_ctls_low,
10320                                 vmx->nested.nested_vmx_exit_ctls_high) ||
10321             !vmx_control_verify(vmcs12->vm_entry_controls,
10322                                 vmx->nested.nested_vmx_entry_ctls_low,
10323                                 vmx->nested.nested_vmx_entry_ctls_high))
10324                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10325
10326         if (vmcs12->cr3_target_count > nested_cpu_vmx_misc_cr3_count(vcpu))
10327                 return VMXERR_ENTRY_INVALID_CONTROL_FIELD;
10328
10329         if (!nested_host_cr0_valid(vcpu, vmcs12->host_cr0) ||
10330             !nested_host_cr4_valid(vcpu, vmcs12->host_cr4) ||
10331             !nested_cr3_valid(vcpu, vmcs12->host_cr3))
10332                 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD;
10333
10334         return 0;
10335 }
10336
10337 static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10338                                   u32 *exit_qual)
10339 {
10340         bool ia32e;
10341
10342         *exit_qual = ENTRY_FAIL_DEFAULT;
10343
10344         if (!nested_guest_cr0_valid(vcpu, vmcs12->guest_cr0) ||
10345             !nested_guest_cr4_valid(vcpu, vmcs12->guest_cr4))
10346                 return 1;
10347
10348         if (!nested_cpu_has2(vmcs12, SECONDARY_EXEC_SHADOW_VMCS) &&
10349             vmcs12->vmcs_link_pointer != -1ull) {
10350                 *exit_qual = ENTRY_FAIL_VMCS_LINK_PTR;
10351                 return 1;
10352         }
10353
10354         /*
10355          * If the load IA32_EFER VM-entry control is 1, the following checks
10356          * are performed on the field for the IA32_EFER MSR:
10357          * - Bits reserved in the IA32_EFER MSR must be 0.
10358          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10359          *   the IA-32e mode guest VM-exit control. It must also be identical
10360          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10361          *   CR0.PG) is 1.
10362          */
10363         if (to_vmx(vcpu)->nested.nested_run_pending &&
10364             (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) {
10365                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10366                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10367                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10368                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10369                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME)))
10370                         return 1;
10371         }
10372
10373         /*
10374          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10375          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10376          * the values of the LMA and LME bits in the field must each be that of
10377          * the host address-space size VM-exit control.
10378          */
10379         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10380                 ia32e = (vmcs12->vm_exit_controls &
10381                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10382                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10383                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10384                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME))
10385                         return 1;
10386         }
10387
10388         return 0;
10389 }
10390
10391 static int enter_vmx_non_root_mode(struct kvm_vcpu *vcpu, bool from_vmentry)
10392 {
10393         struct vcpu_vmx *vmx = to_vmx(vcpu);
10394         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10395         struct loaded_vmcs *vmcs02;
10396         u32 msr_entry_idx;
10397         u32 exit_qual;
10398
10399         vmcs02 = nested_get_current_vmcs02(vmx);
10400         if (!vmcs02)
10401                 return -ENOMEM;
10402
10403         enter_guest_mode(vcpu);
10404
10405         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10406                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10407
10408         vmx_switch_vmcs(vcpu, vmcs02);
10409         vmx_segment_cache_clear(vmx);
10410
10411         if (prepare_vmcs02(vcpu, vmcs12, from_vmentry, &exit_qual)) {
10412                 leave_guest_mode(vcpu);
10413                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10414                 nested_vmx_entry_failure(vcpu, vmcs12,
10415                                          EXIT_REASON_INVALID_STATE, exit_qual);
10416                 return 1;
10417         }
10418
10419         nested_get_vmcs12_pages(vcpu, vmcs12);
10420
10421         msr_entry_idx = nested_vmx_load_msr(vcpu,
10422                                             vmcs12->vm_entry_msr_load_addr,
10423                                             vmcs12->vm_entry_msr_load_count);
10424         if (msr_entry_idx) {
10425                 leave_guest_mode(vcpu);
10426                 vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10427                 nested_vmx_entry_failure(vcpu, vmcs12,
10428                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10429                 return 1;
10430         }
10431
10432         vmcs12->launch_state = 1;
10433
10434         /*
10435          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10436          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10437          * returned as far as L1 is concerned. It will only return (and set
10438          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10439          */
10440         return 0;
10441 }
10442
10443 /*
10444  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10445  * for running an L2 nested guest.
10446  */
10447 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
10448 {
10449         struct vmcs12 *vmcs12;
10450         struct vcpu_vmx *vmx = to_vmx(vcpu);
10451         u32 exit_qual;
10452         int ret;
10453
10454         if (!nested_vmx_check_permission(vcpu))
10455                 return 1;
10456
10457         if (!nested_vmx_check_vmcs12(vcpu))
10458                 goto out;
10459
10460         vmcs12 = get_vmcs12(vcpu);
10461
10462         if (enable_shadow_vmcs)
10463                 copy_shadow_to_vmcs12(vmx);
10464
10465         /*
10466          * The nested entry process starts with enforcing various prerequisites
10467          * on vmcs12 as required by the Intel SDM, and act appropriately when
10468          * they fail: As the SDM explains, some conditions should cause the
10469          * instruction to fail, while others will cause the instruction to seem
10470          * to succeed, but return an EXIT_REASON_INVALID_STATE.
10471          * To speed up the normal (success) code path, we should avoid checking
10472          * for misconfigurations which will anyway be caught by the processor
10473          * when using the merged vmcs02.
10474          */
10475         if (vmcs12->launch_state == launch) {
10476                 nested_vmx_failValid(vcpu,
10477                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10478                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
10479                 goto out;
10480         }
10481
10482         ret = check_vmentry_prereqs(vcpu, vmcs12);
10483         if (ret) {
10484                 nested_vmx_failValid(vcpu, ret);
10485                 goto out;
10486         }
10487
10488         /*
10489          * After this point, the trap flag no longer triggers a singlestep trap
10490          * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10491          * This is not 100% correct; for performance reasons, we delegate most
10492          * of the checks on host state to the processor.  If those fail,
10493          * the singlestep trap is missed.
10494          */
10495         skip_emulated_instruction(vcpu);
10496
10497         ret = check_vmentry_postreqs(vcpu, vmcs12, &exit_qual);
10498         if (ret) {
10499                 nested_vmx_entry_failure(vcpu, vmcs12,
10500                                          EXIT_REASON_INVALID_STATE, exit_qual);
10501                 return 1;
10502         }
10503
10504         /*
10505          * We're finally done with prerequisite checking, and can start with
10506          * the nested entry.
10507          */
10508
10509         ret = enter_vmx_non_root_mode(vcpu, true);
10510         if (ret)
10511                 return ret;
10512
10513         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10514                 return kvm_vcpu_halt(vcpu);
10515
10516         vmx->nested.nested_run_pending = 1;
10517
10518         return 1;
10519
10520 out:
10521         return kvm_skip_emulated_instruction(vcpu);
10522 }
10523
10524 /*
10525  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10526  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10527  * This function returns the new value we should put in vmcs12.guest_cr0.
10528  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10529  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10530  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10531  *     didn't trap the bit, because if L1 did, so would L0).
10532  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10533  *     been modified by L2, and L1 knows it. So just leave the old value of
10534  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10535  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10536  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10537  *     changed these bits, and therefore they need to be updated, but L0
10538  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10539  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10540  */
10541 static inline unsigned long
10542 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10543 {
10544         return
10545         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10546         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10547         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10548                         vcpu->arch.cr0_guest_owned_bits));
10549 }
10550
10551 static inline unsigned long
10552 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10553 {
10554         return
10555         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10556         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10557         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10558                         vcpu->arch.cr4_guest_owned_bits));
10559 }
10560
10561 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10562                                        struct vmcs12 *vmcs12)
10563 {
10564         u32 idt_vectoring;
10565         unsigned int nr;
10566
10567         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10568                 nr = vcpu->arch.exception.nr;
10569                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10570
10571                 if (kvm_exception_is_soft(nr)) {
10572                         vmcs12->vm_exit_instruction_len =
10573                                 vcpu->arch.event_exit_inst_len;
10574                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10575                 } else
10576                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10577
10578                 if (vcpu->arch.exception.has_error_code) {
10579                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10580                         vmcs12->idt_vectoring_error_code =
10581                                 vcpu->arch.exception.error_code;
10582                 }
10583
10584                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10585         } else if (vcpu->arch.nmi_injected) {
10586                 vmcs12->idt_vectoring_info_field =
10587                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10588         } else if (vcpu->arch.interrupt.pending) {
10589                 nr = vcpu->arch.interrupt.nr;
10590                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10591
10592                 if (vcpu->arch.interrupt.soft) {
10593                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10594                         vmcs12->vm_entry_instruction_len =
10595                                 vcpu->arch.event_exit_inst_len;
10596                 } else
10597                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10598
10599                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10600         }
10601 }
10602
10603 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10604 {
10605         struct vcpu_vmx *vmx = to_vmx(vcpu);
10606
10607         if (vcpu->arch.exception.pending ||
10608                 vcpu->arch.nmi_injected ||
10609                 vcpu->arch.interrupt.pending)
10610                 return -EBUSY;
10611
10612         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10613             vmx->nested.preemption_timer_expired) {
10614                 if (vmx->nested.nested_run_pending)
10615                         return -EBUSY;
10616                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10617                 return 0;
10618         }
10619
10620         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10621                 if (vmx->nested.nested_run_pending)
10622                         return -EBUSY;
10623                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10624                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10625                                   INTR_INFO_VALID_MASK, 0);
10626                 /*
10627                  * The NMI-triggered VM exit counts as injection:
10628                  * clear this one and block further NMIs.
10629                  */
10630                 vcpu->arch.nmi_pending = 0;
10631                 vmx_set_nmi_mask(vcpu, true);
10632                 return 0;
10633         }
10634
10635         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10636             nested_exit_on_intr(vcpu)) {
10637                 if (vmx->nested.nested_run_pending)
10638                         return -EBUSY;
10639                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10640                 return 0;
10641         }
10642
10643         vmx_complete_nested_posted_interrupt(vcpu);
10644         return 0;
10645 }
10646
10647 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10648 {
10649         ktime_t remaining =
10650                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10651         u64 value;
10652
10653         if (ktime_to_ns(remaining) <= 0)
10654                 return 0;
10655
10656         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10657         do_div(value, 1000000);
10658         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10659 }
10660
10661 /*
10662  * Update the guest state fields of vmcs12 to reflect changes that
10663  * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10664  * VM-entry controls is also updated, since this is really a guest
10665  * state bit.)
10666  */
10667 static void sync_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10668 {
10669         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10670         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10671
10672         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10673         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10674         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10675
10676         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10677         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10678         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10679         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10680         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10681         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10682         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10683         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10684         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10685         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10686         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10687         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10688         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10689         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10690         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10691         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10692         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10693         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10694         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10695         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10696         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10697         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10698         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10699         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10700         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10701         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10702         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10703         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10704         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10705         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10706         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10707         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10708         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10709         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10710         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10711         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10712
10713         vmcs12->guest_interruptibility_info =
10714                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10715         vmcs12->guest_pending_dbg_exceptions =
10716                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10717         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10718                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10719         else
10720                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10721
10722         if (nested_cpu_has_preemption_timer(vmcs12)) {
10723                 if (vmcs12->vm_exit_controls &
10724                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10725                         vmcs12->vmx_preemption_timer_value =
10726                                 vmx_get_preemption_timer_value(vcpu);
10727                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10728         }
10729
10730         /*
10731          * In some cases (usually, nested EPT), L2 is allowed to change its
10732          * own CR3 without exiting. If it has changed it, we must keep it.
10733          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10734          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10735          *
10736          * Additionally, restore L2's PDPTR to vmcs12.
10737          */
10738         if (enable_ept) {
10739                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10740                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10741                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10742                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10743                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10744         }
10745
10746         vmcs12->guest_linear_address = vmcs_readl(GUEST_LINEAR_ADDRESS);
10747
10748         if (nested_cpu_has_vid(vmcs12))
10749                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10750
10751         vmcs12->vm_entry_controls =
10752                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10753                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10754
10755         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10756                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10757                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10758         }
10759
10760         /* TODO: These cannot have changed unless we have MSR bitmaps and
10761          * the relevant bit asks not to trap the change */
10762         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10763                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10764         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10765                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10766         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10767         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10768         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10769         if (kvm_mpx_supported())
10770                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10771 }
10772
10773 /*
10774  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10775  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10776  * and this function updates it to reflect the changes to the guest state while
10777  * L2 was running (and perhaps made some exits which were handled directly by L0
10778  * without going back to L1), and to reflect the exit reason.
10779  * Note that we do not have to copy here all VMCS fields, just those that
10780  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10781  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10782  * which already writes to vmcs12 directly.
10783  */
10784 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10785                            u32 exit_reason, u32 exit_intr_info,
10786                            unsigned long exit_qualification)
10787 {
10788         /* update guest state fields: */
10789         sync_vmcs12(vcpu, vmcs12);
10790
10791         /* update exit information fields: */
10792
10793         vmcs12->vm_exit_reason = exit_reason;
10794         vmcs12->exit_qualification = exit_qualification;
10795
10796         vmcs12->vm_exit_intr_info = exit_intr_info;
10797         if ((vmcs12->vm_exit_intr_info &
10798              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10799             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10800                 vmcs12->vm_exit_intr_error_code =
10801                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10802         vmcs12->idt_vectoring_info_field = 0;
10803         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10804         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10805
10806         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10807                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10808                  * instead of reading the real value. */
10809                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10810
10811                 /*
10812                  * Transfer the event that L0 or L1 may wanted to inject into
10813                  * L2 to IDT_VECTORING_INFO_FIELD.
10814                  */
10815                 vmcs12_save_pending_event(vcpu, vmcs12);
10816         }
10817
10818         /*
10819          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10820          * preserved above and would only end up incorrectly in L1.
10821          */
10822         vcpu->arch.nmi_injected = false;
10823         kvm_clear_exception_queue(vcpu);
10824         kvm_clear_interrupt_queue(vcpu);
10825 }
10826
10827 /*
10828  * A part of what we need to when the nested L2 guest exits and we want to
10829  * run its L1 parent, is to reset L1's guest state to the host state specified
10830  * in vmcs12.
10831  * This function is to be called not only on normal nested exit, but also on
10832  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10833  * Failures During or After Loading Guest State").
10834  * This function should be called when the active VMCS is L1's (vmcs01).
10835  */
10836 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10837                                    struct vmcs12 *vmcs12)
10838 {
10839         struct kvm_segment seg;
10840         u32 entry_failure_code;
10841
10842         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10843                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10844         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10845                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10846         else
10847                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10848         vmx_set_efer(vcpu, vcpu->arch.efer);
10849
10850         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10851         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10852         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10853         /*
10854          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10855          * actually changed, because vmx_set_cr0 refers to efer set above.
10856          *
10857          * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10858          * (KVM doesn't change it);
10859          */
10860         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
10861         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10862
10863         /* Same as above - no reason to call set_cr4_guest_host_mask().  */
10864         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10865         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10866
10867         nested_ept_uninit_mmu_context(vcpu);
10868
10869         /*
10870          * Only PDPTE load can fail as the value of cr3 was checked on entry and
10871          * couldn't have changed.
10872          */
10873         if (nested_vmx_load_cr3(vcpu, vmcs12->host_cr3, false, &entry_failure_code))
10874                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_PDPTE_FAIL);
10875
10876         if (!enable_ept)
10877                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10878
10879         if (enable_vpid) {
10880                 /*
10881                  * Trivially support vpid by letting L2s share their parent
10882                  * L1's vpid. TODO: move to a more elaborate solution, giving
10883                  * each L2 its own vpid and exposing the vpid feature to L1.
10884                  */
10885                 vmx_flush_tlb(vcpu);
10886         }
10887
10888
10889         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10890         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10891         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10892         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10893         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10894
10895         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10896         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10897                 vmcs_write64(GUEST_BNDCFGS, 0);
10898
10899         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10900                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10901                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10902         }
10903         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10904                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10905                         vmcs12->host_ia32_perf_global_ctrl);
10906
10907         /* Set L1 segment info according to Intel SDM
10908             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10909         seg = (struct kvm_segment) {
10910                 .base = 0,
10911                 .limit = 0xFFFFFFFF,
10912                 .selector = vmcs12->host_cs_selector,
10913                 .type = 11,
10914                 .present = 1,
10915                 .s = 1,
10916                 .g = 1
10917         };
10918         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10919                 seg.l = 1;
10920         else
10921                 seg.db = 1;
10922         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10923         seg = (struct kvm_segment) {
10924                 .base = 0,
10925                 .limit = 0xFFFFFFFF,
10926                 .type = 3,
10927                 .present = 1,
10928                 .s = 1,
10929                 .db = 1,
10930                 .g = 1
10931         };
10932         seg.selector = vmcs12->host_ds_selector;
10933         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10934         seg.selector = vmcs12->host_es_selector;
10935         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10936         seg.selector = vmcs12->host_ss_selector;
10937         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10938         seg.selector = vmcs12->host_fs_selector;
10939         seg.base = vmcs12->host_fs_base;
10940         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10941         seg.selector = vmcs12->host_gs_selector;
10942         seg.base = vmcs12->host_gs_base;
10943         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10944         seg = (struct kvm_segment) {
10945                 .base = vmcs12->host_tr_base,
10946                 .limit = 0x67,
10947                 .selector = vmcs12->host_tr_selector,
10948                 .type = 11,
10949                 .present = 1
10950         };
10951         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10952
10953         kvm_set_dr(vcpu, 7, 0x400);
10954         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10955
10956         if (cpu_has_vmx_msr_bitmap())
10957                 vmx_set_msr_bitmap(vcpu);
10958
10959         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10960                                 vmcs12->vm_exit_msr_load_count))
10961                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10962 }
10963
10964 /*
10965  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10966  * and modify vmcs12 to make it see what it would expect to see there if
10967  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10968  */
10969 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10970                               u32 exit_intr_info,
10971                               unsigned long exit_qualification)
10972 {
10973         struct vcpu_vmx *vmx = to_vmx(vcpu);
10974         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10975         u32 vm_inst_error = 0;
10976
10977         /* trying to cancel vmlaunch/vmresume is a bug */
10978         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10979
10980         leave_guest_mode(vcpu);
10981         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10982                        exit_qualification);
10983
10984         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10985                                  vmcs12->vm_exit_msr_store_count))
10986                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10987
10988         if (unlikely(vmx->fail))
10989                 vm_inst_error = vmcs_read32(VM_INSTRUCTION_ERROR);
10990
10991         vmx_switch_vmcs(vcpu, &vmx->vmcs01);
10992
10993         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10994             && nested_exit_intr_ack_set(vcpu)) {
10995                 int irq = kvm_cpu_get_interrupt(vcpu);
10996                 WARN_ON(irq < 0);
10997                 vmcs12->vm_exit_intr_info = irq |
10998                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10999         }
11000
11001         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
11002                                        vmcs12->exit_qualification,
11003                                        vmcs12->idt_vectoring_info_field,
11004                                        vmcs12->vm_exit_intr_info,
11005                                        vmcs12->vm_exit_intr_error_code,
11006                                        KVM_ISA_VMX);
11007
11008         vm_entry_controls_reset_shadow(vmx);
11009         vm_exit_controls_reset_shadow(vmx);
11010         vmx_segment_cache_clear(vmx);
11011
11012         /* if no vmcs02 cache requested, remove the one we used */
11013         if (VMCS02_POOL_SIZE == 0)
11014                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
11015
11016         load_vmcs12_host_state(vcpu, vmcs12);
11017
11018         /* Update any VMCS fields that might have changed while L2 ran */
11019         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11020         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, vmx->msr_autoload.nr);
11021         vmcs_write64(TSC_OFFSET, vcpu->arch.tsc_offset);
11022         if (vmx->hv_deadline_tsc == -1)
11023                 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11024                                 PIN_BASED_VMX_PREEMPTION_TIMER);
11025         else
11026                 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11027                               PIN_BASED_VMX_PREEMPTION_TIMER);
11028         if (kvm_has_tsc_control)
11029                 decache_tsc_multiplier(vmx);
11030
11031         if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
11032                 vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
11033                 vmx_set_virtual_x2apic_mode(vcpu,
11034                                 vcpu->arch.apic_base & X2APIC_ENABLE);
11035         } else if (!nested_cpu_has_ept(vmcs12) &&
11036                    nested_cpu_has2(vmcs12,
11037                                    SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
11038                 vmx_flush_tlb_ept_only(vcpu);
11039         }
11040
11041         /* This is needed for same reason as it was needed in prepare_vmcs02 */
11042         vmx->host_rsp = 0;
11043
11044         /* Unpin physical memory we referred to in vmcs02 */
11045         if (vmx->nested.apic_access_page) {
11046                 nested_release_page(vmx->nested.apic_access_page);
11047                 vmx->nested.apic_access_page = NULL;
11048         }
11049         if (vmx->nested.virtual_apic_page) {
11050                 nested_release_page(vmx->nested.virtual_apic_page);
11051                 vmx->nested.virtual_apic_page = NULL;
11052         }
11053         if (vmx->nested.pi_desc_page) {
11054                 kunmap(vmx->nested.pi_desc_page);
11055                 nested_release_page(vmx->nested.pi_desc_page);
11056                 vmx->nested.pi_desc_page = NULL;
11057                 vmx->nested.pi_desc = NULL;
11058         }
11059
11060         /*
11061          * We are now running in L2, mmu_notifier will force to reload the
11062          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11063          */
11064         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
11065
11066         /*
11067          * Exiting from L2 to L1, we're now back to L1 which thinks it just
11068          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11069          * success or failure flag accordingly.
11070          */
11071         if (unlikely(vmx->fail)) {
11072                 vmx->fail = 0;
11073                 nested_vmx_failValid(vcpu, vm_inst_error);
11074         } else
11075                 nested_vmx_succeed(vcpu);
11076         if (enable_shadow_vmcs)
11077                 vmx->nested.sync_shadow_vmcs = true;
11078
11079         /* in case we halted in L2 */
11080         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11081 }
11082
11083 /*
11084  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11085  */
11086 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
11087 {
11088         if (is_guest_mode(vcpu)) {
11089                 to_vmx(vcpu)->nested.nested_run_pending = 0;
11090                 nested_vmx_vmexit(vcpu, -1, 0, 0);
11091         }
11092         free_nested(to_vmx(vcpu));
11093 }
11094
11095 /*
11096  * L1's failure to enter L2 is a subset of a normal exit, as explained in
11097  * 23.7 "VM-entry failures during or after loading guest state" (this also
11098  * lists the acceptable exit-reason and exit-qualification parameters).
11099  * It should only be called before L2 actually succeeded to run, and when
11100  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11101  */
11102 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
11103                         struct vmcs12 *vmcs12,
11104                         u32 reason, unsigned long qualification)
11105 {
11106         load_vmcs12_host_state(vcpu, vmcs12);
11107         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
11108         vmcs12->exit_qualification = qualification;
11109         nested_vmx_succeed(vcpu);
11110         if (enable_shadow_vmcs)
11111                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
11112 }
11113
11114 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
11115                                struct x86_instruction_info *info,
11116                                enum x86_intercept_stage stage)
11117 {
11118         return X86EMUL_CONTINUE;
11119 }
11120
11121 #ifdef CONFIG_X86_64
11122 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11123 static inline int u64_shl_div_u64(u64 a, unsigned int shift,
11124                                   u64 divisor, u64 *result)
11125 {
11126         u64 low = a << shift, high = a >> (64 - shift);
11127
11128         /* To avoid the overflow on divq */
11129         if (high >= divisor)
11130                 return 1;
11131
11132         /* Low hold the result, high hold rem which is discarded */
11133         asm("divq %2\n\t" : "=a" (low), "=d" (high) :
11134             "rm" (divisor), "0" (low), "1" (high));
11135         *result = low;
11136
11137         return 0;
11138 }
11139
11140 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
11141 {
11142         struct vcpu_vmx *vmx = to_vmx(vcpu);
11143         u64 tscl = rdtsc();
11144         u64 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
11145         u64 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
11146
11147         /* Convert to host delta tsc if tsc scaling is enabled */
11148         if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
11149                         u64_shl_div_u64(delta_tsc,
11150                                 kvm_tsc_scaling_ratio_frac_bits,
11151                                 vcpu->arch.tsc_scaling_ratio,
11152                                 &delta_tsc))
11153                 return -ERANGE;
11154
11155         /*
11156          * If the delta tsc can't fit in the 32 bit after the multi shift,
11157          * we can't use the preemption timer.
11158          * It's possible that it fits on later vmentries, but checking
11159          * on every vmentry is costly so we just use an hrtimer.
11160          */
11161         if (delta_tsc >> (cpu_preemption_timer_multi + 32))
11162                 return -ERANGE;
11163
11164         vmx->hv_deadline_tsc = tscl + delta_tsc;
11165         vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
11166                         PIN_BASED_VMX_PREEMPTION_TIMER);
11167
11168         return delta_tsc == 0;
11169 }
11170
11171 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
11172 {
11173         struct vcpu_vmx *vmx = to_vmx(vcpu);
11174         vmx->hv_deadline_tsc = -1;
11175         vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
11176                         PIN_BASED_VMX_PREEMPTION_TIMER);
11177 }
11178 #endif
11179
11180 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
11181 {
11182         if (ple_gap)
11183                 shrink_ple_window(vcpu);
11184 }
11185
11186 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
11187                                      struct kvm_memory_slot *slot)
11188 {
11189         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
11190         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
11191 }
11192
11193 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
11194                                        struct kvm_memory_slot *slot)
11195 {
11196         kvm_mmu_slot_set_dirty(kvm, slot);
11197 }
11198
11199 static void vmx_flush_log_dirty(struct kvm *kvm)
11200 {
11201         kvm_flush_pml_buffers(kvm);
11202 }
11203
11204 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
11205 {
11206         struct vmcs12 *vmcs12;
11207         struct vcpu_vmx *vmx = to_vmx(vcpu);
11208         gpa_t gpa;
11209         struct page *page = NULL;
11210         u64 *pml_address;
11211
11212         if (is_guest_mode(vcpu)) {
11213                 WARN_ON_ONCE(vmx->nested.pml_full);
11214
11215                 /*
11216                  * Check if PML is enabled for the nested guest.
11217                  * Whether eptp bit 6 is set is already checked
11218                  * as part of A/D emulation.
11219                  */
11220                 vmcs12 = get_vmcs12(vcpu);
11221                 if (!nested_cpu_has_pml(vmcs12))
11222                         return 0;
11223
11224                 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
11225                         vmx->nested.pml_full = true;
11226                         return 1;
11227                 }
11228
11229                 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
11230
11231                 page = nested_get_page(vcpu, vmcs12->pml_address);
11232                 if (!page)
11233                         return 0;
11234
11235                 pml_address = kmap(page);
11236                 pml_address[vmcs12->guest_pml_index--] = gpa;
11237                 kunmap(page);
11238                 nested_release_page_clean(page);
11239         }
11240
11241         return 0;
11242 }
11243
11244 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
11245                                            struct kvm_memory_slot *memslot,
11246                                            gfn_t offset, unsigned long mask)
11247 {
11248         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
11249 }
11250
11251 /*
11252  * This routine does the following things for vCPU which is going
11253  * to be blocked if VT-d PI is enabled.
11254  * - Store the vCPU to the wakeup list, so when interrupts happen
11255  *   we can find the right vCPU to wake up.
11256  * - Change the Posted-interrupt descriptor as below:
11257  *      'NDST' <-- vcpu->pre_pcpu
11258  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11259  * - If 'ON' is set during this process, which means at least one
11260  *   interrupt is posted for this vCPU, we cannot block it, in
11261  *   this case, return 1, otherwise, return 0.
11262  *
11263  */
11264 static int pi_pre_block(struct kvm_vcpu *vcpu)
11265 {
11266         unsigned long flags;
11267         unsigned int dest;
11268         struct pi_desc old, new;
11269         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11270
11271         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11272                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11273                 !kvm_vcpu_apicv_active(vcpu))
11274                 return 0;
11275
11276         vcpu->pre_pcpu = vcpu->cpu;
11277         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11278                           vcpu->pre_pcpu), flags);
11279         list_add_tail(&vcpu->blocked_vcpu_list,
11280                       &per_cpu(blocked_vcpu_on_cpu,
11281                       vcpu->pre_pcpu));
11282         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
11283                                vcpu->pre_pcpu), flags);
11284
11285         do {
11286                 old.control = new.control = pi_desc->control;
11287
11288                 /*
11289                  * We should not block the vCPU if
11290                  * an interrupt is posted for it.
11291                  */
11292                 if (pi_test_on(pi_desc) == 1) {
11293                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
11294                                           vcpu->pre_pcpu), flags);
11295                         list_del(&vcpu->blocked_vcpu_list);
11296                         spin_unlock_irqrestore(
11297                                         &per_cpu(blocked_vcpu_on_cpu_lock,
11298                                         vcpu->pre_pcpu), flags);
11299                         vcpu->pre_pcpu = -1;
11300
11301                         return 1;
11302                 }
11303
11304                 WARN((pi_desc->sn == 1),
11305                      "Warning: SN field of posted-interrupts "
11306                      "is set before blocking\n");
11307
11308                 /*
11309                  * Since vCPU can be preempted during this process,
11310                  * vcpu->cpu could be different with pre_pcpu, we
11311                  * need to set pre_pcpu as the destination of wakeup
11312                  * notification event, then we can find the right vCPU
11313                  * to wakeup in wakeup handler if interrupts happen
11314                  * when the vCPU is in blocked state.
11315                  */
11316                 dest = cpu_physical_id(vcpu->pre_pcpu);
11317
11318                 if (x2apic_enabled())
11319                         new.ndst = dest;
11320                 else
11321                         new.ndst = (dest << 8) & 0xFF00;
11322
11323                 /* set 'NV' to 'wakeup vector' */
11324                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
11325         } while (cmpxchg(&pi_desc->control, old.control,
11326                         new.control) != old.control);
11327
11328         return 0;
11329 }
11330
11331 static int vmx_pre_block(struct kvm_vcpu *vcpu)
11332 {
11333         if (pi_pre_block(vcpu))
11334                 return 1;
11335
11336         if (kvm_lapic_hv_timer_in_use(vcpu))
11337                 kvm_lapic_switch_to_sw_timer(vcpu);
11338
11339         return 0;
11340 }
11341
11342 static void pi_post_block(struct kvm_vcpu *vcpu)
11343 {
11344         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
11345         struct pi_desc old, new;
11346         unsigned int dest;
11347         unsigned long flags;
11348
11349         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
11350                 !irq_remapping_cap(IRQ_POSTING_CAP)  ||
11351                 !kvm_vcpu_apicv_active(vcpu))
11352                 return;
11353
11354         do {
11355                 old.control = new.control = pi_desc->control;
11356
11357                 dest = cpu_physical_id(vcpu->cpu);
11358
11359                 if (x2apic_enabled())
11360                         new.ndst = dest;
11361                 else
11362                         new.ndst = (dest << 8) & 0xFF00;
11363
11364                 /* Allow posting non-urgent interrupts */
11365                 new.sn = 0;
11366
11367                 /* set 'NV' to 'notification vector' */
11368                 new.nv = POSTED_INTR_VECTOR;
11369         } while (cmpxchg(&pi_desc->control, old.control,
11370                         new.control) != old.control);
11371
11372         if(vcpu->pre_pcpu != -1) {
11373                 spin_lock_irqsave(
11374                         &per_cpu(blocked_vcpu_on_cpu_lock,
11375                         vcpu->pre_pcpu), flags);
11376                 list_del(&vcpu->blocked_vcpu_list);
11377                 spin_unlock_irqrestore(
11378                         &per_cpu(blocked_vcpu_on_cpu_lock,
11379                         vcpu->pre_pcpu), flags);
11380                 vcpu->pre_pcpu = -1;
11381         }
11382 }
11383
11384 static void vmx_post_block(struct kvm_vcpu *vcpu)
11385 {
11386         if (kvm_x86_ops->set_hv_timer)
11387                 kvm_lapic_switch_to_hv_timer(vcpu);
11388
11389         pi_post_block(vcpu);
11390 }
11391
11392 /*
11393  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11394  *
11395  * @kvm: kvm
11396  * @host_irq: host irq of the interrupt
11397  * @guest_irq: gsi of the interrupt
11398  * @set: set or unset PI
11399  * returns 0 on success, < 0 on failure
11400  */
11401 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
11402                               uint32_t guest_irq, bool set)
11403 {
11404         struct kvm_kernel_irq_routing_entry *e;
11405         struct kvm_irq_routing_table *irq_rt;
11406         struct kvm_lapic_irq irq;
11407         struct kvm_vcpu *vcpu;
11408         struct vcpu_data vcpu_info;
11409         int idx, ret = -EINVAL;
11410
11411         if (!kvm_arch_has_assigned_device(kvm) ||
11412                 !irq_remapping_cap(IRQ_POSTING_CAP) ||
11413                 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
11414                 return 0;
11415
11416         idx = srcu_read_lock(&kvm->irq_srcu);
11417         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
11418         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
11419
11420         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
11421                 if (e->type != KVM_IRQ_ROUTING_MSI)
11422                         continue;
11423                 /*
11424                  * VT-d PI cannot support posting multicast/broadcast
11425                  * interrupts to a vCPU, we still use interrupt remapping
11426                  * for these kind of interrupts.
11427                  *
11428                  * For lowest-priority interrupts, we only support
11429                  * those with single CPU as the destination, e.g. user
11430                  * configures the interrupts via /proc/irq or uses
11431                  * irqbalance to make the interrupts single-CPU.
11432                  *
11433                  * We will support full lowest-priority interrupt later.
11434                  */
11435
11436                 kvm_set_msi_irq(kvm, e, &irq);
11437                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
11438                         /*
11439                          * Make sure the IRTE is in remapped mode if
11440                          * we don't handle it in posted mode.
11441                          */
11442                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11443                         if (ret < 0) {
11444                                 printk(KERN_INFO
11445                                    "failed to back to remapped mode, irq: %u\n",
11446                                    host_irq);
11447                                 goto out;
11448                         }
11449
11450                         continue;
11451                 }
11452
11453                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
11454                 vcpu_info.vector = irq.vector;
11455
11456                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
11457                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
11458
11459                 if (set)
11460                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
11461                 else {
11462                         /* suppress notification event before unposting */
11463                         pi_set_sn(vcpu_to_pi_desc(vcpu));
11464                         ret = irq_set_vcpu_affinity(host_irq, NULL);
11465                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
11466                 }
11467
11468                 if (ret < 0) {
11469                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
11470                                         __func__);
11471                         goto out;
11472                 }
11473         }
11474
11475         ret = 0;
11476 out:
11477         srcu_read_unlock(&kvm->irq_srcu, idx);
11478         return ret;
11479 }
11480
11481 static void vmx_setup_mce(struct kvm_vcpu *vcpu)
11482 {
11483         if (vcpu->arch.mcg_cap & MCG_LMCE_P)
11484                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
11485                         FEATURE_CONTROL_LMCE;
11486         else
11487                 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
11488                         ~FEATURE_CONTROL_LMCE;
11489 }
11490
11491 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
11492         .cpu_has_kvm_support = cpu_has_kvm_support,
11493         .disabled_by_bios = vmx_disabled_by_bios,
11494         .hardware_setup = hardware_setup,
11495         .hardware_unsetup = hardware_unsetup,
11496         .check_processor_compatibility = vmx_check_processor_compat,
11497         .hardware_enable = hardware_enable,
11498         .hardware_disable = hardware_disable,
11499         .cpu_has_accelerated_tpr = report_flexpriority,
11500         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
11501
11502         .vcpu_create = vmx_create_vcpu,
11503         .vcpu_free = vmx_free_vcpu,
11504         .vcpu_reset = vmx_vcpu_reset,
11505
11506         .prepare_guest_switch = vmx_save_host_state,
11507         .vcpu_load = vmx_vcpu_load,
11508         .vcpu_put = vmx_vcpu_put,
11509
11510         .update_bp_intercept = update_exception_bitmap,
11511         .get_msr = vmx_get_msr,
11512         .set_msr = vmx_set_msr,
11513         .get_segment_base = vmx_get_segment_base,
11514         .get_segment = vmx_get_segment,
11515         .set_segment = vmx_set_segment,
11516         .get_cpl = vmx_get_cpl,
11517         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
11518         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
11519         .decache_cr3 = vmx_decache_cr3,
11520         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
11521         .set_cr0 = vmx_set_cr0,
11522         .set_cr3 = vmx_set_cr3,
11523         .set_cr4 = vmx_set_cr4,
11524         .set_efer = vmx_set_efer,
11525         .get_idt = vmx_get_idt,
11526         .set_idt = vmx_set_idt,
11527         .get_gdt = vmx_get_gdt,
11528         .set_gdt = vmx_set_gdt,
11529         .get_dr6 = vmx_get_dr6,
11530         .set_dr6 = vmx_set_dr6,
11531         .set_dr7 = vmx_set_dr7,
11532         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
11533         .cache_reg = vmx_cache_reg,
11534         .get_rflags = vmx_get_rflags,
11535         .set_rflags = vmx_set_rflags,
11536
11537         .get_pkru = vmx_get_pkru,
11538
11539         .tlb_flush = vmx_flush_tlb,
11540
11541         .run = vmx_vcpu_run,
11542         .handle_exit = vmx_handle_exit,
11543         .skip_emulated_instruction = skip_emulated_instruction,
11544         .set_interrupt_shadow = vmx_set_interrupt_shadow,
11545         .get_interrupt_shadow = vmx_get_interrupt_shadow,
11546         .patch_hypercall = vmx_patch_hypercall,
11547         .set_irq = vmx_inject_irq,
11548         .set_nmi = vmx_inject_nmi,
11549         .queue_exception = vmx_queue_exception,
11550         .cancel_injection = vmx_cancel_injection,
11551         .interrupt_allowed = vmx_interrupt_allowed,
11552         .nmi_allowed = vmx_nmi_allowed,
11553         .get_nmi_mask = vmx_get_nmi_mask,
11554         .set_nmi_mask = vmx_set_nmi_mask,
11555         .enable_nmi_window = enable_nmi_window,
11556         .enable_irq_window = enable_irq_window,
11557         .update_cr8_intercept = update_cr8_intercept,
11558         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
11559         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
11560         .get_enable_apicv = vmx_get_enable_apicv,
11561         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
11562         .load_eoi_exitmap = vmx_load_eoi_exitmap,
11563         .apicv_post_state_restore = vmx_apicv_post_state_restore,
11564         .hwapic_irr_update = vmx_hwapic_irr_update,
11565         .hwapic_isr_update = vmx_hwapic_isr_update,
11566         .sync_pir_to_irr = vmx_sync_pir_to_irr,
11567         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
11568
11569         .set_tss_addr = vmx_set_tss_addr,
11570         .get_tdp_level = get_ept_level,
11571         .get_mt_mask = vmx_get_mt_mask,
11572
11573         .get_exit_info = vmx_get_exit_info,
11574
11575         .get_lpage_level = vmx_get_lpage_level,
11576
11577         .cpuid_update = vmx_cpuid_update,
11578
11579         .rdtscp_supported = vmx_rdtscp_supported,
11580         .invpcid_supported = vmx_invpcid_supported,
11581
11582         .set_supported_cpuid = vmx_set_supported_cpuid,
11583
11584         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
11585
11586         .write_tsc_offset = vmx_write_tsc_offset,
11587
11588         .set_tdp_cr3 = vmx_set_cr3,
11589
11590         .check_intercept = vmx_check_intercept,
11591         .handle_external_intr = vmx_handle_external_intr,
11592         .mpx_supported = vmx_mpx_supported,
11593         .xsaves_supported = vmx_xsaves_supported,
11594
11595         .check_nested_events = vmx_check_nested_events,
11596
11597         .sched_in = vmx_sched_in,
11598
11599         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
11600         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
11601         .flush_log_dirty = vmx_flush_log_dirty,
11602         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
11603         .write_log_dirty = vmx_write_pml_buffer,
11604
11605         .pre_block = vmx_pre_block,
11606         .post_block = vmx_post_block,
11607
11608         .pmu_ops = &intel_pmu_ops,
11609
11610         .update_pi_irte = vmx_update_pi_irte,
11611
11612 #ifdef CONFIG_X86_64
11613         .set_hv_timer = vmx_set_hv_timer,
11614         .cancel_hv_timer = vmx_cancel_hv_timer,
11615 #endif
11616
11617         .setup_mce = vmx_setup_mce,
11618 };
11619
11620 static int __init vmx_init(void)
11621 {
11622         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11623                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11624         if (r)
11625                 return r;
11626
11627 #ifdef CONFIG_KEXEC_CORE
11628         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11629                            crash_vmclear_local_loaded_vmcss);
11630 #endif
11631
11632         return 0;
11633 }
11634
11635 static void __exit vmx_exit(void)
11636 {
11637 #ifdef CONFIG_KEXEC_CORE
11638         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11639         synchronize_rcu();
11640 #endif
11641
11642         kvm_exit();
11643 }
11644
11645 module_init(vmx_init)
11646 module_exit(vmx_exit)