drivers/cpufreq/intel_pstate.c

   1 /*
   2  * intel_pstate.c: Native P state management for Intel processors
   3  *
   4  * (C) Copyright 2012 Intel Corporation
   5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  */
  12
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/kernel_stat.h>
  17 #include <linux/module.h>
  18 #include <linux/ktime.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/tick.h>
  21 #include <linux/slab.h>
  22 #include <linux/sched/cpufreq.h>
  23 #include <linux/list.h>
  24 #include <linux/cpu.h>
  25 #include <linux/cpufreq.h>
  26 #include <linux/sysfs.h>
  27 #include <linux/types.h>
  28 #include <linux/fs.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/acpi.h>
  31 #include <linux/vmalloc.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/div64.h>
  35 #include <asm/msr.h>
  36 #include <asm/cpu_device_id.h>
  37 #include <asm/cpufeature.h>
  38 #include <asm/intel-family.h>
  39
  40 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  41
  42 #ifdef CONFIG_ACPI
  43 #include <acpi/processor.h>
  44 #include <acpi/cppc_acpi.h>
  45 #endif
  46
  47 #define FRAC_BITS 8
  48 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  49 #define fp_toint(X) ((X) >> FRAC_BITS)
  50
  51 #define EXT_BITS 6
  52 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  53 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  54 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  55
  56 static inline int32_t mul_fp(int32_t x, int32_t y)
  57 {
  58         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  59 }
  60
  61 static inline int32_t div_fp(s64 x, s64 y)
  62 {
  63         return div64_s64((int64_t)x << FRAC_BITS, y);
  64 }
  65
  66 static inline int ceiling_fp(int32_t x)
  67 {
  68         int mask, ret;
  69
  70         ret = fp_toint(x);
  71         mask = (1 << FRAC_BITS) - 1;
  72         if (x & mask)
  73                 ret += 1;
  74         return ret;
  75 }
  76
  77 static inline u64 mul_ext_fp(u64 x, u64 y)
  78 {
  79         return (x * y) >> EXT_FRAC_BITS;
  80 }
  81
  82 static inline u64 div_ext_fp(u64 x, u64 y)
  83 {
  84         return div64_u64(x << EXT_FRAC_BITS, y);
  85 }
  86
  87 /**
  88  * struct sample -      Store performance sample
  89  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
  90  *                      performance during last sample period
  91  * @busy_scaled:        Scaled busy value which is used to calculate next
  92  *                      P state. This can be different than core_avg_perf
  93  *                      to account for cpu idle period
  94  * @aperf:              Difference of actual performance frequency clock count
  95  *                      read from APERF MSR between last and current sample
  96  * @mperf:              Difference of maximum performance frequency clock count
  97  *                      read from MPERF MSR between last and current sample
  98  * @tsc:                Difference of time stamp counter between last and
  99  *                      current sample
 100  * @time:               Current time from scheduler
 101  *
 102  * This structure is used in the cpudata structure to store performance sample
 103  * data for choosing next P State.
 104  */
 105 struct sample {
 106         int32_t core_avg_perf;
 107         int32_t busy_scaled;
 108         u64 aperf;
 109         u64 mperf;
 110         u64 tsc;
 111         u64 time;
 112 };
 113
 114 /**
 115  * struct pstate_data - Store P state data
 116  * @current_pstate:     Current requested P state
 117  * @min_pstate:         Min P state possible for this platform
 118  * @max_pstate:         Max P state possible for this platform
 119  * @max_pstate_physical:This is physical Max P state for a processor
 120  *                      This can be higher than the max_pstate which can
 121  *                      be limited by platform thermal design power limits
 122  * @scaling:            Scaling factor to  convert frequency to cpufreq
 123  *                      frequency units
 124  * @turbo_pstate:       Max Turbo P state possible for this platform
 125  * @max_freq:           @max_pstate frequency in cpufreq units
 126  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 127  *
 128  * Stores the per cpu model P state limits and current P state.
 129  */
 130 struct pstate_data {
 131         int     current_pstate;
 132         int     min_pstate;
 133         int     max_pstate;
 134         int     max_pstate_physical;
 135         int     scaling;
 136         int     turbo_pstate;
 137         unsigned int max_freq;
 138         unsigned int turbo_freq;
 139 };
 140
 141 /**
 142  * struct vid_data -    Stores voltage information data
 143  * @min:                VID data for this platform corresponding to
 144  *                      the lowest P state
 145  * @max:                VID data corresponding to the highest P State.
 146  * @turbo:              VID data for turbo P state
 147  * @ratio:              Ratio of (vid max - vid min) /
 148  *                      (max P state - Min P State)
 149  *
 150  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 151  * This data is used in Atom platforms, where in addition to target P state,
 152  * the voltage data needs to be specified to select next P State.
 153  */
 154 struct vid_data {
 155         int min;
 156         int max;
 157         int turbo;
 158         int32_t ratio;
 159 };
 160
 161 /**
 162  * struct _pid -        Stores PID data
 163  * @setpoint:           Target set point for busyness or performance
 164  * @integral:           Storage for accumulated error values
 165  * @p_gain:             PID proportional gain
 166  * @i_gain:             PID integral gain
 167  * @d_gain:             PID derivative gain
 168  * @deadband:           PID deadband
 169  * @last_err:           Last error storage for integral part of PID calculation
 170  *
 171  * Stores PID coefficients and last error for PID controller.
 172  */
 173 struct _pid {
 174         int setpoint;
 175         int32_t integral;
 176         int32_t p_gain;
 177         int32_t i_gain;
 178         int32_t d_gain;
 179         int deadband;
 180         int32_t last_err;
 181 };
 182
 183 /**
 184  * struct perf_limits - Store user and policy limits
 185  * @no_turbo:           User requested turbo state from intel_pstate sysfs
 186  * @turbo_disabled:     Platform turbo status either from msr
 187  *                      MSR_IA32_MISC_ENABLE or when maximum available pstate
 188  *                      matches the maximum turbo pstate
 189  * @max_perf_pct:       Effective maximum performance limit in percentage, this
 190  *                      is minimum of either limits enforced by cpufreq policy
 191  *                      or limits from user set limits via intel_pstate sysfs
 192  * @min_perf_pct:       Effective minimum performance limit in percentage, this
 193  *                      is maximum of either limits enforced by cpufreq policy
 194  *                      or limits from user set limits via intel_pstate sysfs
 195  * @max_perf:           This is a scaled value between 0 to 255 for max_perf_pct
 196  *                      This value is used to limit max pstate
 197  * @min_perf:           This is a scaled value between 0 to 255 for min_perf_pct
 198  *                      This value is used to limit min pstate
 199  * @max_policy_pct:     The maximum performance in percentage enforced by
 200  *                      cpufreq setpolicy interface
 201  * @max_sysfs_pct:      The maximum performance in percentage enforced by
 202  *                      intel pstate sysfs interface, unused when per cpu
 203  *                      controls are enforced
 204  * @min_policy_pct:     The minimum performance in percentage enforced by
 205  *                      cpufreq setpolicy interface
 206  * @min_sysfs_pct:      The minimum performance in percentage enforced by
 207  *                      intel pstate sysfs interface, unused when per cpu
 208  *                      controls are enforced
 209  *
 210  * Storage for user and policy defined limits.
 211  */
 212 struct perf_limits {
 213         int no_turbo;
 214         int turbo_disabled;
 215         int max_perf_pct;
 216         int min_perf_pct;
 217         int32_t max_perf;
 218         int32_t min_perf;
 219         int max_policy_pct;
 220         int max_sysfs_pct;
 221         int min_policy_pct;
 222         int min_sysfs_pct;
 223 };
 224
 225 /**
 226  * struct cpudata -     Per CPU instance data storage
 227  * @cpu:                CPU number for this instance data
 228  * @policy:             CPUFreq policy value
 229  * @update_util:        CPUFreq utility callback information
 230  * @update_util_set:    CPUFreq utility callback is set
 231  * @iowait_boost:       iowait-related boost fraction
 232  * @last_update:        Time of the last update.
 233  * @pstate:             Stores P state limits for this CPU
 234  * @vid:                Stores VID limits for this CPU
 235  * @pid:                Stores PID parameters for this CPU
 236  * @last_sample_time:   Last Sample time
 237  * @prev_aperf:         Last APERF value read from APERF MSR
 238  * @prev_mperf:         Last MPERF value read from MPERF MSR
 239  * @prev_tsc:           Last timestamp counter (TSC) value
 240  * @prev_cummulative_iowait: IO Wait time difference from last and
 241  *                      current sample
 242  * @sample:             Storage for storing last Sample data
 243  * @perf_limits:        Pointer to perf_limit unique to this CPU
 244  *                      Not all field in the structure are applicable
 245  *                      when per cpu controls are enforced
 246  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 247  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 248  * @epp_powersave:      Last saved HWP energy performance preference
 249  *                      (EPP) or energy performance bias (EPB),
 250  *                      when policy switched to performance
 251  * @epp_policy:         Last saved policy used to set EPP/EPB
 252  * @epp_default:        Power on default HWP energy performance
 253  *                      preference/bias
 254  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
 255  *                      operation
 256  *
 257  * This structure stores per CPU instance data for all CPUs.
 258  */
 259 struct cpudata {
 260         int cpu;
 261
 262         unsigned int policy;
 263         struct update_util_data update_util;
 264         bool   update_util_set;
 265
 266         struct pstate_data pstate;
 267         struct vid_data vid;
 268         struct _pid pid;
 269
 270         u64     last_update;
 271         u64     last_sample_time;
 272         u64     prev_aperf;
 273         u64     prev_mperf;
 274         u64     prev_tsc;
 275         u64     prev_cummulative_iowait;
 276         struct sample sample;
 277         struct perf_limits *perf_limits;
 278 #ifdef CONFIG_ACPI
 279         struct acpi_processor_performance acpi_perf_data;
 280         bool valid_pss_table;
 281 #endif
 282         unsigned int iowait_boost;
 283         s16 epp_powersave;
 284         s16 epp_policy;
 285         s16 epp_default;
 286         s16 epp_saved;
 287 };
 288
 289 static struct cpudata **all_cpu_data;
 290
 291 /**
 292  * struct pstate_adjust_policy - Stores static PID configuration data
 293  * @sample_rate_ms:     PID calculation sample rate in ms
 294  * @sample_rate_ns:     Sample rate calculation in ns
 295  * @deadband:           PID deadband
 296  * @setpoint:           PID Setpoint
 297  * @p_gain_pct:         PID proportional gain
 298  * @i_gain_pct:         PID integral gain
 299  * @d_gain_pct:         PID derivative gain
 300  *
 301  * Stores per CPU model static PID configuration data.
 302  */
 303 struct pstate_adjust_policy {
 304         int sample_rate_ms;
 305         s64 sample_rate_ns;
 306         int deadband;
 307         int setpoint;
 308         int p_gain_pct;
 309         int d_gain_pct;
 310         int i_gain_pct;
 311 };
 312
 313 /**
 314  * struct pstate_funcs - Per CPU model specific callbacks
 315  * @get_max:            Callback to get maximum non turbo effective P state
 316  * @get_max_physical:   Callback to get maximum non turbo physical P state
 317  * @get_min:            Callback to get minimum P state
 318  * @get_turbo:          Callback to get turbo P state
 319  * @get_scaling:        Callback to get frequency scaling factor
 320  * @get_val:            Callback to convert P state to actual MSR write value
 321  * @get_vid:            Callback to get VID data for Atom platforms
 322  * @get_target_pstate:  Callback to a function to calculate next P state to use
 323  *
 324  * Core and Atom CPU models have different way to get P State limits. This
 325  * structure is used to store those callbacks.
 326  */
 327 struct pstate_funcs {
 328         int (*get_max)(void);
 329         int (*get_max_physical)(void);
 330         int (*get_min)(void);
 331         int (*get_turbo)(void);
 332         int (*get_scaling)(void);
 333         u64 (*get_val)(struct cpudata*, int pstate);
 334         void (*get_vid)(struct cpudata *);
 335         int32_t (*get_target_pstate)(struct cpudata *);
 336 };
 337
 338 /**
 339  * struct cpu_defaults- Per CPU model default config data
 340  * @pid_policy: PID config data
 341  * @funcs:              Callback function data
 342  */
 343 struct cpu_defaults {
 344         struct pstate_adjust_policy pid_policy;
 345         struct pstate_funcs funcs;
 346 };
 347
 348 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
 349 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
 350
 351 static struct pstate_adjust_policy pid_params __read_mostly;
 352 static struct pstate_funcs pstate_funcs __read_mostly;
 353 static int hwp_active __read_mostly;
 354 static bool per_cpu_limits __read_mostly;
 355
 356 static bool driver_registered __read_mostly;
 357
 358 #ifdef CONFIG_ACPI
 359 static bool acpi_ppc;
 360 #endif
 361
 362 static struct perf_limits performance_limits;
 363 static struct perf_limits powersave_limits;
 364 static struct perf_limits *limits;
 365
 366 static void intel_pstate_init_limits(struct perf_limits *limits)
 367 {
 368         memset(limits, 0, sizeof(*limits));
 369         limits->max_perf_pct = 100;
 370         limits->max_perf = int_ext_tofp(1);
 371         limits->max_policy_pct = 100;
 372         limits->max_sysfs_pct = 100;
 373 }
 374
 375 static void intel_pstate_set_performance_limits(struct perf_limits *limits)
 376 {
 377         intel_pstate_init_limits(limits);
 378         limits->min_perf_pct = 100;
 379         limits->min_perf = int_ext_tofp(1);
 380         limits->min_sysfs_pct = 100;
 381 }
 382
 383 static DEFINE_MUTEX(intel_pstate_driver_lock);
 384 static DEFINE_MUTEX(intel_pstate_limits_lock);
 385
 386 #ifdef CONFIG_ACPI
 387
 388 static bool intel_pstate_get_ppc_enable_status(void)
 389 {
 390         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 391             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 392                 return true;
 393
 394         return acpi_ppc;
 395 }
 396
 397 #ifdef CONFIG_ACPI_CPPC_LIB
 398
 399 /* The work item is needed to avoid CPU hotplug locking issues */
 400 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 401 {
 402         sched_set_itmt_support();
 403 }
 404
 405 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 406
 407 static void intel_pstate_set_itmt_prio(int cpu)
 408 {
 409         struct cppc_perf_caps cppc_perf;
 410         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
 411         int ret;
 412
 413         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 414         if (ret)
 415                 return;
 416
 417         /*
 418          * The priorities can be set regardless of whether or not
 419          * sched_set_itmt_support(true) has been called and it is valid to
 420          * update them at any time after it has been called.
 421          */
 422         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
 423
 424         if (max_highest_perf <= min_highest_perf) {
 425                 if (cppc_perf.highest_perf > max_highest_perf)
 426                         max_highest_perf = cppc_perf.highest_perf;
 427
 428                 if (cppc_perf.highest_perf < min_highest_perf)
 429                         min_highest_perf = cppc_perf.highest_perf;
 430
 431                 if (max_highest_perf > min_highest_perf) {
 432                         /*
 433                          * This code can be run during CPU online under the
 434                          * CPU hotplug locks, so sched_set_itmt_support()
 435                          * cannot be called from here.  Queue up a work item
 436                          * to invoke it.
 437                          */
 438                         schedule_work(&sched_itmt_work);
 439                 }
 440         }
 441 }
 442 #else
 443 static void intel_pstate_set_itmt_prio(int cpu)
 444 {
 445 }
 446 #endif
 447
 448 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 449 {
 450         struct cpudata *cpu;
 451         int ret;
 452         int i;
 453
 454         if (hwp_active) {
 455                 intel_pstate_set_itmt_prio(policy->cpu);
 456                 return;
 457         }
 458
 459         if (!intel_pstate_get_ppc_enable_status())
 460                 return;
 461
 462         cpu = all_cpu_data[policy->cpu];
 463
 464         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 465                                                   policy->cpu);
 466         if (ret)
 467                 return;
 468
 469         /*
 470          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 471          * guarantee that the states returned by it map to the states in our
 472          * list directly.
 473          */
 474         if (cpu->acpi_perf_data.control_register.space_id !=
 475                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 476                 goto err;
 477
 478         /*
 479          * If there is only one entry _PSS, simply ignore _PSS and continue as
 480          * usual without taking _PSS into account
 481          */
 482         if (cpu->acpi_perf_data.state_count < 2)
 483                 goto err;
 484
 485         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 486         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 487                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 488                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 489                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 490                          (u32) cpu->acpi_perf_data.states[i].power,
 491                          (u32) cpu->acpi_perf_data.states[i].control);
 492         }
 493
 494         /*
 495          * The _PSS table doesn't contain whole turbo frequency range.
 496          * This just contains +1 MHZ above the max non turbo frequency,
 497          * with control value corresponding to max turbo ratio. But
 498          * when cpufreq set policy is called, it will call with this
 499          * max frequency, which will cause a reduced performance as
 500          * this driver uses real max turbo frequency as the max
 501          * frequency. So correct this frequency in _PSS table to
 502          * correct max turbo frequency based on the turbo state.
 503          * Also need to convert to MHz as _PSS freq is in MHz.
 504          */
 505         if (!limits->turbo_disabled)
 506                 cpu->acpi_perf_data.states[0].core_frequency =
 507                                         policy->cpuinfo.max_freq / 1000;
 508         cpu->valid_pss_table = true;
 509         pr_debug("_PPC limits will be enforced\n");
 510
 511         return;
 512
 513  err:
 514         cpu->valid_pss_table = false;
 515         acpi_processor_unregister_performance(policy->cpu);
 516 }
 517
 518 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 519 {
 520         struct cpudata *cpu;
 521
 522         cpu = all_cpu_data[policy->cpu];
 523         if (!cpu->valid_pss_table)
 524                 return;
 525
 526         acpi_processor_unregister_performance(policy->cpu);
 527 }
 528 #else
 529 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 530 {
 531 }
 532
 533 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 534 {
 535 }
 536 #endif
 537
 538 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
 539                              int deadband, int integral) {
 540         pid->setpoint = int_tofp(setpoint);
 541         pid->deadband  = int_tofp(deadband);
 542         pid->integral  = int_tofp(integral);
 543         pid->last_err  = int_tofp(setpoint) - int_tofp(busy);
 544 }
 545
 546 static inline void pid_p_gain_set(struct _pid *pid, int percent)
 547 {
 548         pid->p_gain = div_fp(percent, 100);
 549 }
 550
 551 static inline void pid_i_gain_set(struct _pid *pid, int percent)
 552 {
 553         pid->i_gain = div_fp(percent, 100);
 554 }
 555
 556 static inline void pid_d_gain_set(struct _pid *pid, int percent)
 557 {
 558         pid->d_gain = div_fp(percent, 100);
 559 }
 560
 561 static signed int pid_calc(struct _pid *pid, int32_t busy)
 562 {
 563         signed int result;
 564         int32_t pterm, dterm, fp_error;
 565         int32_t integral_limit;
 566
 567         fp_error = pid->setpoint - busy;
 568
 569         if (abs(fp_error) <= pid->deadband)
 570                 return 0;
 571
 572         pterm = mul_fp(pid->p_gain, fp_error);
 573
 574         pid->integral += fp_error;
 575
 576         /*
 577          * We limit the integral here so that it will never
 578          * get higher than 30.  This prevents it from becoming
 579          * too large an input over long periods of time and allows
 580          * it to get factored out sooner.
 581          *
 582          * The value of 30 was chosen through experimentation.
 583          */
 584         integral_limit = int_tofp(30);
 585         if (pid->integral > integral_limit)
 586                 pid->integral = integral_limit;
 587         if (pid->integral < -integral_limit)
 588                 pid->integral = -integral_limit;
 589
 590         dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
 591         pid->last_err = fp_error;
 592
 593         result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
 594         result = result + (1 << (FRAC_BITS-1));
 595         return (signed int)fp_toint(result);
 596 }
 597
 598 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
 599 {
 600         pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
 601         pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
 602         pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
 603
 604         pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
 605 }
 606
 607 static inline void intel_pstate_reset_all_pid(void)
 608 {
 609         unsigned int cpu;
 610
 611         for_each_online_cpu(cpu) {
 612                 if (all_cpu_data[cpu])
 613                         intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
 614         }
 615 }
 616
 617 static inline void update_turbo_state(void)
 618 {
 619         u64 misc_en;
 620         struct cpudata *cpu;
 621
 622         cpu = all_cpu_data[0];
 623         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 624         limits->turbo_disabled =
 625                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 626                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 627 }
 628
 629 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 630 {
 631         u64 epb;
 632         int ret;
 633
 634         if (!static_cpu_has(X86_FEATURE_EPB))
 635                 return -ENXIO;
 636
 637         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 638         if (ret)
 639                 return (s16)ret;
 640
 641         return (s16)(epb & 0x0f);
 642 }
 643
 644 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 645 {
 646         s16 epp;
 647
 648         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 649                 /*
 650                  * When hwp_req_data is 0, means that caller didn't read
 651                  * MSR_HWP_REQUEST, so need to read and get EPP.
 652                  */
 653                 if (!hwp_req_data) {
 654                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 655                                             &hwp_req_data);
 656                         if (epp)
 657                                 return epp;
 658                 }
 659                 epp = (hwp_req_data >> 24) & 0xff;
 660         } else {
 661                 /* When there is no EPP present, HWP uses EPB settings */
 662                 epp = intel_pstate_get_epb(cpu_data);
 663         }
 664
 665         return epp;
 666 }
 667
 668 static int intel_pstate_set_epb(int cpu, s16 pref)
 669 {
 670         u64 epb;
 671         int ret;
 672
 673         if (!static_cpu_has(X86_FEATURE_EPB))
 674                 return -ENXIO;
 675
 676         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 677         if (ret)
 678                 return ret;
 679
 680         epb = (epb & ~0x0f) | pref;
 681         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 682
 683         return 0;
 684 }
 685
 686 /*
 687  * EPP/EPB display strings corresponding to EPP index in the
 688  * energy_perf_strings[]
 689  *      index           String
 690  *-------------------------------------
 691  *      0               default
 692  *      1               performance
 693  *      2               balance_performance
 694  *      3               balance_power
 695  *      4               power
 696  */
 697 static const char * const energy_perf_strings[] = {
 698         "default",
 699         "performance",
 700         "balance_performance",
 701         "balance_power",
 702         "power",
 703         NULL
 704 };
 705
 706 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
 707 {
 708         s16 epp;
 709         int index = -EINVAL;
 710
 711         epp = intel_pstate_get_epp(cpu_data, 0);
 712         if (epp < 0)
 713                 return epp;
 714
 715         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 716                 /*
 717                  * Range:
 718                  *      0x00-0x3F       :       Performance
 719                  *      0x40-0x7F       :       Balance performance
 720                  *      0x80-0xBF       :       Balance power
 721                  *      0xC0-0xFF       :       Power
 722                  * The EPP is a 8 bit value, but our ranges restrict the
 723                  * value which can be set. Here only using top two bits
 724                  * effectively.
 725                  */
 726                 index = (epp >> 6) + 1;
 727         } else if (static_cpu_has(X86_FEATURE_EPB)) {
 728                 /*
 729                  * Range:
 730                  *      0x00-0x03       :       Performance
 731                  *      0x04-0x07       :       Balance performance
 732                  *      0x08-0x0B       :       Balance power
 733                  *      0x0C-0x0F       :       Power
 734                  * The EPB is a 4 bit value, but our ranges restrict the
 735                  * value which can be set. Here only using top two bits
 736                  * effectively.
 737                  */
 738                 index = (epp >> 2) + 1;
 739         }
 740
 741         return index;
 742 }
 743
 744 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 745                                               int pref_index)
 746 {
 747         int epp = -EINVAL;
 748         int ret;
 749
 750         if (!pref_index)
 751                 epp = cpu_data->epp_default;
 752
 753         mutex_lock(&intel_pstate_limits_lock);
 754
 755         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 756                 u64 value;
 757
 758                 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
 759                 if (ret)
 760                         goto return_pref;
 761
 762                 value &= ~GENMASK_ULL(31, 24);
 763
 764                 /*
 765                  * If epp is not default, convert from index into
 766                  * energy_perf_strings to epp value, by shifting 6
 767                  * bits left to use only top two bits in epp.
 768                  * The resultant epp need to shifted by 24 bits to
 769                  * epp position in MSR_HWP_REQUEST.
 770                  */
 771                 if (epp == -EINVAL)
 772                         epp = (pref_index - 1) << 6;
 773
 774                 value |= (u64)epp << 24;
 775                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
 776         } else {
 777                 if (epp == -EINVAL)
 778                         epp = (pref_index - 1) << 2;
 779                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 780         }
 781 return_pref:
 782         mutex_unlock(&intel_pstate_limits_lock);
 783
 784         return ret;
 785 }
 786
 787 static ssize_t show_energy_performance_available_preferences(
 788                                 struct cpufreq_policy *policy, char *buf)
 789 {
 790         int i = 0;
 791         int ret = 0;
 792
 793         while (energy_perf_strings[i] != NULL)
 794                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 795
 796         ret += sprintf(&buf[ret], "\n");
 797
 798         return ret;
 799 }
 800
 801 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 802
 803 static ssize_t store_energy_performance_preference(
 804                 struct cpufreq_policy *policy, const char *buf, size_t count)
 805 {
 806         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 807         char str_preference[21];
 808         int ret, i = 0;
 809
 810         ret = sscanf(buf, "%20s", str_preference);
 811         if (ret != 1)
 812                 return -EINVAL;
 813
 814         while (energy_perf_strings[i] != NULL) {
 815                 if (!strcmp(str_preference, energy_perf_strings[i])) {
 816                         intel_pstate_set_energy_pref_index(cpu_data, i);
 817                         return count;
 818                 }
 819                 ++i;
 820         }
 821
 822         return -EINVAL;
 823 }
 824
 825 static ssize_t show_energy_performance_preference(
 826                                 struct cpufreq_policy *policy, char *buf)
 827 {
 828         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 829         int preference;
 830
 831         preference = intel_pstate_get_energy_pref_index(cpu_data);
 832         if (preference < 0)
 833                 return preference;
 834
 835         return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 836 }
 837
 838 cpufreq_freq_attr_rw(energy_performance_preference);
 839
 840 static struct freq_attr *hwp_cpufreq_attrs[] = {
 841         &energy_performance_preference,
 842         &energy_performance_available_preferences,
 843         NULL,
 844 };
 845
 846 static void intel_pstate_hwp_set(struct cpufreq_policy *policy)
 847 {
 848         int min, hw_min, max, hw_max, cpu, range, adj_range;
 849         struct perf_limits *perf_limits = limits;
 850         u64 value, cap;
 851
 852         for_each_cpu(cpu, policy->cpus) {
 853                 int max_perf_pct, min_perf_pct;
 854                 struct cpudata *cpu_data = all_cpu_data[cpu];
 855                 s16 epp;
 856
 857                 if (per_cpu_limits)
 858                         perf_limits = all_cpu_data[cpu]->perf_limits;
 859
 860                 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
 861                 hw_min = HWP_LOWEST_PERF(cap);
 862                 if (limits->no_turbo)
 863                         hw_max = HWP_GUARANTEED_PERF(cap);
 864                 else
 865                         hw_max = HWP_HIGHEST_PERF(cap);
 866                 range = hw_max - hw_min;
 867
 868                 max_perf_pct = perf_limits->max_perf_pct;
 869                 min_perf_pct = perf_limits->min_perf_pct;
 870
 871                 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 872                 adj_range = min_perf_pct * range / 100;
 873                 min = hw_min + adj_range;
 874                 value &= ~HWP_MIN_PERF(~0L);
 875                 value |= HWP_MIN_PERF(min);
 876
 877                 adj_range = max_perf_pct * range / 100;
 878                 max = hw_min + adj_range;
 879
 880                 value &= ~HWP_MAX_PERF(~0L);
 881                 value |= HWP_MAX_PERF(max);
 882
 883                 if (cpu_data->epp_policy == cpu_data->policy)
 884                         goto skip_epp;
 885
 886                 cpu_data->epp_policy = cpu_data->policy;
 887
 888                 if (cpu_data->epp_saved >= 0) {
 889                         epp = cpu_data->epp_saved;
 890                         cpu_data->epp_saved = -EINVAL;
 891                         goto update_epp;
 892                 }
 893
 894                 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 895                         epp = intel_pstate_get_epp(cpu_data, value);
 896                         cpu_data->epp_powersave = epp;
 897                         /* If EPP read was failed, then don't try to write */
 898                         if (epp < 0)
 899                                 goto skip_epp;
 900
 901
 902                         epp = 0;
 903                 } else {
 904                         /* skip setting EPP, when saved value is invalid */
 905                         if (cpu_data->epp_powersave < 0)
 906                                 goto skip_epp;
 907
 908                         /*
 909                          * No need to restore EPP when it is not zero. This
 910                          * means:
 911                          *  - Policy is not changed
 912                          *  - user has manually changed
 913                          *  - Error reading EPB
 914                          */
 915                         epp = intel_pstate_get_epp(cpu_data, value);
 916                         if (epp)
 917                                 goto skip_epp;
 918
 919                         epp = cpu_data->epp_powersave;
 920                 }
 921 update_epp:
 922                 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 923                         value &= ~GENMASK_ULL(31, 24);
 924                         value |= (u64)epp << 24;
 925                 } else {
 926                         intel_pstate_set_epb(cpu, epp);
 927                 }
 928 skip_epp:
 929                 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 930         }
 931 }
 932
 933 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
 934 {
 935         if (hwp_active)
 936                 intel_pstate_hwp_set(policy);
 937
 938         return 0;
 939 }
 940
 941 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
 942 {
 943         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 944
 945         if (!hwp_active)
 946                 return 0;
 947
 948         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
 949
 950         return 0;
 951 }
 952
 953 static int intel_pstate_resume(struct cpufreq_policy *policy)
 954 {
 955         int ret;
 956
 957         if (!hwp_active)
 958                 return 0;
 959
 960         mutex_lock(&intel_pstate_limits_lock);
 961
 962         all_cpu_data[policy->cpu]->epp_policy = 0;
 963
 964         ret = intel_pstate_hwp_set_policy(policy);
 965
 966         mutex_unlock(&intel_pstate_limits_lock);
 967
 968         return ret;
 969 }
 970
 971 static void intel_pstate_update_policies(void)
 972         __releases(&intel_pstate_limits_lock)
 973         __acquires(&intel_pstate_limits_lock)
 974 {
 975         struct perf_limits *saved_limits = limits;
 976         int cpu;
 977
 978         mutex_unlock(&intel_pstate_limits_lock);
 979
 980         for_each_possible_cpu(cpu)
 981                 cpufreq_update_policy(cpu);
 982
 983         mutex_lock(&intel_pstate_limits_lock);
 984
 985         limits = saved_limits;
 986 }
 987
 988 /************************** debugfs begin ************************/
 989 static int pid_param_set(void *data, u64 val)
 990 {
 991         *(u32 *)data = val;
 992         intel_pstate_reset_all_pid();
 993         return 0;
 994 }
 995
 996 static int pid_param_get(void *data, u64 *val)
 997 {
 998         *val = *(u32 *)data;
 999         return 0;
1000 }
1001 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
1002
1003 static struct dentry *debugfs_parent;
1004
1005 struct pid_param {
1006         char *name;
1007         void *value;
1008         struct dentry *dentry;
1009 };
1010
1011 static struct pid_param pid_files[] = {
1012         {"sample_rate_ms", &pid_params.sample_rate_ms, },
1013         {"d_gain_pct", &pid_params.d_gain_pct, },
1014         {"i_gain_pct", &pid_params.i_gain_pct, },
1015         {"deadband", &pid_params.deadband, },
1016         {"setpoint", &pid_params.setpoint, },
1017         {"p_gain_pct", &pid_params.p_gain_pct, },
1018         {NULL, NULL, }
1019 };
1020
1021 static void intel_pstate_debug_expose_params(void)
1022 {
1023         int i;
1024
1025         debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
1026         if (IS_ERR_OR_NULL(debugfs_parent))
1027                 return;
1028
1029         for (i = 0; pid_files[i].name; i++) {
1030                 struct dentry *dentry;
1031
1032                 dentry = debugfs_create_file(pid_files[i].name, 0660,
1033                                              debugfs_parent, pid_files[i].value,
1034                                              &fops_pid_param);
1035                 if (!IS_ERR(dentry))
1036                         pid_files[i].dentry = dentry;
1037         }
1038 }
1039
1040 static void intel_pstate_debug_hide_params(void)
1041 {
1042         int i;
1043
1044         if (IS_ERR_OR_NULL(debugfs_parent))
1045                 return;
1046
1047         for (i = 0; pid_files[i].name; i++) {
1048                 debugfs_remove(pid_files[i].dentry);
1049                 pid_files[i].dentry = NULL;
1050         }
1051
1052         debugfs_remove(debugfs_parent);
1053         debugfs_parent = NULL;
1054 }
1055
1056 /************************** debugfs end ************************/
1057
1058 /************************** sysfs begin ************************/
1059 #define show_one(file_name, object)                                     \
1060         static ssize_t show_##file_name                                 \
1061         (struct kobject *kobj, struct attribute *attr, char *buf)       \
1062         {                                                               \
1063                 return sprintf(buf, "%u\n", limits->object);            \
1064         }
1065
1066 static ssize_t intel_pstate_show_status(char *buf);
1067 static int intel_pstate_update_status(const char *buf, size_t size);
1068
1069 static ssize_t show_status(struct kobject *kobj,
1070                            struct attribute *attr, char *buf)
1071 {
1072         ssize_t ret;
1073
1074         mutex_lock(&intel_pstate_driver_lock);
1075         ret = intel_pstate_show_status(buf);
1076         mutex_unlock(&intel_pstate_driver_lock);
1077
1078         return ret;
1079 }
1080
1081 static ssize_t store_status(struct kobject *a, struct attribute *b,
1082                             const char *buf, size_t count)
1083 {
1084         char *p = memchr(buf, '\n', count);
1085         int ret;
1086
1087         mutex_lock(&intel_pstate_driver_lock);
1088         ret = intel_pstate_update_status(buf, p ? p - buf : count);
1089         mutex_unlock(&intel_pstate_driver_lock);
1090
1091         return ret < 0 ? ret : count;
1092 }
1093
1094 static ssize_t show_turbo_pct(struct kobject *kobj,
1095                                 struct attribute *attr, char *buf)
1096 {
1097         struct cpudata *cpu;
1098         int total, no_turbo, turbo_pct;
1099         uint32_t turbo_fp;
1100
1101         mutex_lock(&intel_pstate_driver_lock);
1102
1103         if (!driver_registered) {
1104                 mutex_unlock(&intel_pstate_driver_lock);
1105                 return -EAGAIN;
1106         }
1107
1108         cpu = all_cpu_data[0];
1109
1110         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1111         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1112         turbo_fp = div_fp(no_turbo, total);
1113         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1114
1115         mutex_unlock(&intel_pstate_driver_lock);
1116
1117         return sprintf(buf, "%u\n", turbo_pct);
1118 }
1119
1120 static ssize_t show_num_pstates(struct kobject *kobj,
1121                                 struct attribute *attr, char *buf)
1122 {
1123         struct cpudata *cpu;
1124         int total;
1125
1126         mutex_lock(&intel_pstate_driver_lock);
1127
1128         if (!driver_registered) {
1129                 mutex_unlock(&intel_pstate_driver_lock);
1130                 return -EAGAIN;
1131         }
1132
1133         cpu = all_cpu_data[0];
1134         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1135
1136         mutex_unlock(&intel_pstate_driver_lock);
1137
1138         return sprintf(buf, "%u\n", total);
1139 }
1140
1141 static ssize_t show_no_turbo(struct kobject *kobj,
1142                              struct attribute *attr, char *buf)
1143 {
1144         ssize_t ret;
1145
1146         mutex_lock(&intel_pstate_driver_lock);
1147
1148         if (!driver_registered) {
1149                 mutex_unlock(&intel_pstate_driver_lock);
1150                 return -EAGAIN;
1151         }
1152
1153         update_turbo_state();
1154         if (limits->turbo_disabled)
1155                 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
1156         else
1157                 ret = sprintf(buf, "%u\n", limits->no_turbo);
1158
1159         mutex_unlock(&intel_pstate_driver_lock);
1160
1161         return ret;
1162 }
1163
1164 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1165                               const char *buf, size_t count)
1166 {
1167         unsigned int input;
1168         int ret;
1169
1170         ret = sscanf(buf, "%u", &input);
1171         if (ret != 1)
1172                 return -EINVAL;
1173
1174         mutex_lock(&intel_pstate_driver_lock);
1175
1176         if (!driver_registered) {
1177                 mutex_unlock(&intel_pstate_driver_lock);
1178                 return -EAGAIN;
1179         }
1180
1181         mutex_lock(&intel_pstate_limits_lock);
1182
1183         update_turbo_state();
1184         if (limits->turbo_disabled) {
1185                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1186                 mutex_unlock(&intel_pstate_limits_lock);
1187                 mutex_unlock(&intel_pstate_driver_lock);
1188                 return -EPERM;
1189         }
1190
1191         limits->no_turbo = clamp_t(int, input, 0, 1);
1192
1193         intel_pstate_update_policies();
1194
1195         mutex_unlock(&intel_pstate_limits_lock);
1196
1197         mutex_unlock(&intel_pstate_driver_lock);
1198
1199         return count;
1200 }
1201
1202 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1203                                   const char *buf, size_t count)
1204 {
1205         unsigned int input;
1206         int ret;
1207
1208         ret = sscanf(buf, "%u", &input);
1209         if (ret != 1)
1210                 return -EINVAL;
1211
1212         mutex_lock(&intel_pstate_driver_lock);
1213
1214         if (!driver_registered) {
1215                 mutex_unlock(&intel_pstate_driver_lock);
1216                 return -EAGAIN;
1217         }
1218
1219         mutex_lock(&intel_pstate_limits_lock);
1220
1221         limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
1222         limits->max_perf_pct = min(limits->max_policy_pct,
1223                                    limits->max_sysfs_pct);
1224         limits->max_perf_pct = max(limits->min_policy_pct,
1225                                    limits->max_perf_pct);
1226         limits->max_perf_pct = max(limits->min_perf_pct,
1227                                    limits->max_perf_pct);
1228         limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
1229
1230         intel_pstate_update_policies();
1231
1232         mutex_unlock(&intel_pstate_limits_lock);
1233
1234         mutex_unlock(&intel_pstate_driver_lock);
1235
1236         return count;
1237 }
1238
1239 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1240                                   const char *buf, size_t count)
1241 {
1242         unsigned int input;
1243         int ret;
1244
1245         ret = sscanf(buf, "%u", &input);
1246         if (ret != 1)
1247                 return -EINVAL;
1248
1249         mutex_lock(&intel_pstate_driver_lock);
1250
1251         if (!driver_registered) {
1252                 mutex_unlock(&intel_pstate_driver_lock);
1253                 return -EAGAIN;
1254         }
1255
1256         mutex_lock(&intel_pstate_limits_lock);
1257
1258         limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
1259         limits->min_perf_pct = max(limits->min_policy_pct,
1260                                    limits->min_sysfs_pct);
1261         limits->min_perf_pct = min(limits->max_policy_pct,
1262                                    limits->min_perf_pct);
1263         limits->min_perf_pct = min(limits->max_perf_pct,
1264                                    limits->min_perf_pct);
1265         limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1266
1267         intel_pstate_update_policies();
1268
1269         mutex_unlock(&intel_pstate_limits_lock);
1270
1271         mutex_unlock(&intel_pstate_driver_lock);
1272
1273         return count;
1274 }
1275
1276 show_one(max_perf_pct, max_perf_pct);
1277 show_one(min_perf_pct, min_perf_pct);
1278
1279 define_one_global_rw(status);
1280 define_one_global_rw(no_turbo);
1281 define_one_global_rw(max_perf_pct);
1282 define_one_global_rw(min_perf_pct);
1283 define_one_global_ro(turbo_pct);
1284 define_one_global_ro(num_pstates);
1285
1286 static struct attribute *intel_pstate_attributes[] = {
1287         &status.attr,
1288         &no_turbo.attr,
1289         &turbo_pct.attr,
1290         &num_pstates.attr,
1291         NULL
1292 };
1293
1294 static struct attribute_group intel_pstate_attr_group = {
1295         .attrs = intel_pstate_attributes,
1296 };
1297
1298 static void __init intel_pstate_sysfs_expose_params(void)
1299 {
1300         struct kobject *intel_pstate_kobject;
1301         int rc;
1302
1303         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1304                                                 &cpu_subsys.dev_root->kobj);
1305         if (WARN_ON(!intel_pstate_kobject))
1306                 return;
1307
1308         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1309         if (WARN_ON(rc))
1310                 return;
1311
1312         /*
1313          * If per cpu limits are enforced there are no global limits, so
1314          * return without creating max/min_perf_pct attributes
1315          */
1316         if (per_cpu_limits)
1317                 return;
1318
1319         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1320         WARN_ON(rc);
1321
1322         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1323         WARN_ON(rc);
1324
1325 }
1326 /************************** sysfs end ************************/
1327
1328 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1329 {
1330         /* First disable HWP notification interrupt as we don't process them */
1331         if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1332                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1333
1334         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1335         cpudata->epp_policy = 0;
1336         if (cpudata->epp_default == -EINVAL)
1337                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1338 }
1339
1340 #define MSR_IA32_POWER_CTL_BIT_EE       19
1341
1342 /* Disable energy efficiency optimization */
1343 static void intel_pstate_disable_ee(int cpu)
1344 {
1345         u64 power_ctl;
1346         int ret;
1347
1348         ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1349         if (ret)
1350                 return;
1351
1352         if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1353                 pr_info("Disabling energy efficiency optimization\n");
1354                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1355                 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1356         }
1357 }
1358
1359 static int atom_get_min_pstate(void)
1360 {
1361         u64 value;
1362
1363         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1364         return (value >> 8) & 0x7F;
1365 }
1366
1367 static int atom_get_max_pstate(void)
1368 {
1369         u64 value;
1370
1371         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1372         return (value >> 16) & 0x7F;
1373 }
1374
1375 static int atom_get_turbo_pstate(void)
1376 {
1377         u64 value;
1378
1379         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1380         return value & 0x7F;
1381 }
1382
1383 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1384 {
1385         u64 val;
1386         int32_t vid_fp;
1387         u32 vid;
1388
1389         val = (u64)pstate << 8;
1390         if (limits->no_turbo && !limits->turbo_disabled)
1391                 val |= (u64)1 << 32;
1392
1393         vid_fp = cpudata->vid.min + mul_fp(
1394                 int_tofp(pstate - cpudata->pstate.min_pstate),
1395                 cpudata->vid.ratio);
1396
1397         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1398         vid = ceiling_fp(vid_fp);
1399
1400         if (pstate > cpudata->pstate.max_pstate)
1401                 vid = cpudata->vid.turbo;
1402
1403         return val | vid;
1404 }
1405
1406 static int silvermont_get_scaling(void)
1407 {
1408         u64 value;
1409         int i;
1410         /* Defined in Table 35-6 from SDM (Sept 2015) */
1411         static int silvermont_freq_table[] = {
1412                 83300, 100000, 133300, 116700, 80000};
1413
1414         rdmsrl(MSR_FSB_FREQ, value);
1415         i = value & 0x7;
1416         WARN_ON(i > 4);
1417
1418         return silvermont_freq_table[i];
1419 }
1420
1421 static int airmont_get_scaling(void)
1422 {
1423         u64 value;
1424         int i;
1425         /* Defined in Table 35-10 from SDM (Sept 2015) */
1426         static int airmont_freq_table[] = {
1427                 83300, 100000, 133300, 116700, 80000,
1428                 93300, 90000, 88900, 87500};
1429
1430         rdmsrl(MSR_FSB_FREQ, value);
1431         i = value & 0xF;
1432         WARN_ON(i > 8);
1433
1434         return airmont_freq_table[i];
1435 }
1436
1437 static void atom_get_vid(struct cpudata *cpudata)
1438 {
1439         u64 value;
1440
1441         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1442         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1443         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1444         cpudata->vid.ratio = div_fp(
1445                 cpudata->vid.max - cpudata->vid.min,
1446                 int_tofp(cpudata->pstate.max_pstate -
1447                         cpudata->pstate.min_pstate));
1448
1449         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1450         cpudata->vid.turbo = value & 0x7f;
1451 }
1452
1453 static int core_get_min_pstate(void)
1454 {
1455         u64 value;
1456
1457         rdmsrl(MSR_PLATFORM_INFO, value);
1458         return (value >> 40) & 0xFF;
1459 }
1460
1461 static int core_get_max_pstate_physical(void)
1462 {
1463         u64 value;
1464
1465         rdmsrl(MSR_PLATFORM_INFO, value);
1466         return (value >> 8) & 0xFF;
1467 }
1468
1469 static int core_get_tdp_ratio(u64 plat_info)
1470 {
1471         /* Check how many TDP levels present */
1472         if (plat_info & 0x600000000) {
1473                 u64 tdp_ctrl;
1474                 u64 tdp_ratio;
1475                 int tdp_msr;
1476                 int err;
1477
1478                 /* Get the TDP level (0, 1, 2) to get ratios */
1479                 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1480                 if (err)
1481                         return err;
1482
1483                 /* TDP MSR are continuous starting at 0x648 */
1484                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1485                 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1486                 if (err)
1487                         return err;
1488
1489                 /* For level 1 and 2, bits[23:16] contain the ratio */
1490                 if (tdp_ctrl & 0x03)
1491                         tdp_ratio >>= 16;
1492
1493                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1494                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1495
1496                 return (int)tdp_ratio;
1497         }
1498
1499         return -ENXIO;
1500 }
1501
1502 static int core_get_max_pstate(void)
1503 {
1504         u64 tar;
1505         u64 plat_info;
1506         int max_pstate;
1507         int tdp_ratio;
1508         int err;
1509
1510         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1511         max_pstate = (plat_info >> 8) & 0xFF;
1512
1513         tdp_ratio = core_get_tdp_ratio(plat_info);
1514         if (tdp_ratio <= 0)
1515                 return max_pstate;
1516
1517         if (hwp_active) {
1518                 /* Turbo activation ratio is not used on HWP platforms */
1519                 return tdp_ratio;
1520         }
1521
1522         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1523         if (!err) {
1524                 int tar_levels;
1525
1526                 /* Do some sanity checking for safety */
1527                 tar_levels = tar & 0xff;
1528                 if (tdp_ratio - 1 == tar_levels) {
1529                         max_pstate = tar_levels;
1530                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1531                 }
1532         }
1533
1534         return max_pstate;
1535 }
1536
1537 static int core_get_turbo_pstate(void)
1538 {
1539         u64 value;
1540         int nont, ret;
1541
1542         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1543         nont = core_get_max_pstate();
1544         ret = (value) & 255;
1545         if (ret <= nont)
1546                 ret = nont;
1547         return ret;
1548 }
1549
1550 static inline int core_get_scaling(void)
1551 {
1552         return 100000;
1553 }
1554
1555 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1556 {
1557         u64 val;
1558
1559         val = (u64)pstate << 8;
1560         if (limits->no_turbo && !limits->turbo_disabled)
1561                 val |= (u64)1 << 32;
1562
1563         return val;
1564 }
1565
1566 static int knl_get_turbo_pstate(void)
1567 {
1568         u64 value;
1569         int nont, ret;
1570
1571         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1572         nont = core_get_max_pstate();
1573         ret = (((value) >> 8) & 0xFF);
1574         if (ret <= nont)
1575                 ret = nont;
1576         return ret;
1577 }
1578
1579 static struct cpu_defaults core_params = {
1580         .pid_policy = {
1581                 .sample_rate_ms = 10,
1582                 .deadband = 0,
1583                 .setpoint = 97,
1584                 .p_gain_pct = 20,
1585                 .d_gain_pct = 0,
1586                 .i_gain_pct = 0,
1587         },
1588         .funcs = {
1589                 .get_max = core_get_max_pstate,
1590                 .get_max_physical = core_get_max_pstate_physical,
1591                 .get_min = core_get_min_pstate,
1592                 .get_turbo = core_get_turbo_pstate,
1593                 .get_scaling = core_get_scaling,
1594                 .get_val = core_get_val,
1595                 .get_target_pstate = get_target_pstate_use_performance,
1596         },
1597 };
1598
1599 static const struct cpu_defaults silvermont_params = {
1600         .pid_policy = {
1601                 .sample_rate_ms = 10,
1602                 .deadband = 0,
1603                 .setpoint = 60,
1604                 .p_gain_pct = 14,
1605                 .d_gain_pct = 0,
1606                 .i_gain_pct = 4,
1607         },
1608         .funcs = {
1609                 .get_max = atom_get_max_pstate,
1610                 .get_max_physical = atom_get_max_pstate,
1611                 .get_min = atom_get_min_pstate,
1612                 .get_turbo = atom_get_turbo_pstate,
1613                 .get_val = atom_get_val,
1614                 .get_scaling = silvermont_get_scaling,
1615                 .get_vid = atom_get_vid,
1616                 .get_target_pstate = get_target_pstate_use_cpu_load,
1617         },
1618 };
1619
1620 static const struct cpu_defaults airmont_params = {
1621         .pid_policy = {
1622                 .sample_rate_ms = 10,
1623                 .deadband = 0,
1624                 .setpoint = 60,
1625                 .p_gain_pct = 14,
1626                 .d_gain_pct = 0,
1627                 .i_gain_pct = 4,
1628         },
1629         .funcs = {
1630                 .get_max = atom_get_max_pstate,
1631                 .get_max_physical = atom_get_max_pstate,
1632                 .get_min = atom_get_min_pstate,
1633                 .get_turbo = atom_get_turbo_pstate,
1634                 .get_val = atom_get_val,
1635                 .get_scaling = airmont_get_scaling,
1636                 .get_vid = atom_get_vid,
1637                 .get_target_pstate = get_target_pstate_use_cpu_load,
1638         },
1639 };
1640
1641 static const struct cpu_defaults knl_params = {
1642         .pid_policy = {
1643                 .sample_rate_ms = 10,
1644                 .deadband = 0,
1645                 .setpoint = 97,
1646                 .p_gain_pct = 20,
1647                 .d_gain_pct = 0,
1648                 .i_gain_pct = 0,
1649         },
1650         .funcs = {
1651                 .get_max = core_get_max_pstate,
1652                 .get_max_physical = core_get_max_pstate_physical,
1653                 .get_min = core_get_min_pstate,
1654                 .get_turbo = knl_get_turbo_pstate,
1655                 .get_scaling = core_get_scaling,
1656                 .get_val = core_get_val,
1657                 .get_target_pstate = get_target_pstate_use_performance,
1658         },
1659 };
1660
1661 static const struct cpu_defaults bxt_params = {
1662         .pid_policy = {
1663                 .sample_rate_ms = 10,
1664                 .deadband = 0,
1665                 .setpoint = 60,
1666                 .p_gain_pct = 14,
1667                 .d_gain_pct = 0,
1668                 .i_gain_pct = 4,
1669         },
1670         .funcs = {
1671                 .get_max = core_get_max_pstate,
1672                 .get_max_physical = core_get_max_pstate_physical,
1673                 .get_min = core_get_min_pstate,
1674                 .get_turbo = core_get_turbo_pstate,
1675                 .get_scaling = core_get_scaling,
1676                 .get_val = core_get_val,
1677                 .get_target_pstate = get_target_pstate_use_cpu_load,
1678         },
1679 };
1680
1681 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1682 {
1683         int max_perf = cpu->pstate.turbo_pstate;
1684         int max_perf_adj;
1685         int min_perf;
1686         struct perf_limits *perf_limits = limits;
1687
1688         if (limits->no_turbo || limits->turbo_disabled)
1689                 max_perf = cpu->pstate.max_pstate;
1690
1691         if (per_cpu_limits)
1692                 perf_limits = cpu->perf_limits;
1693
1694         /*
1695          * performance can be limited by user through sysfs, by cpufreq
1696          * policy, or by cpu specific default values determined through
1697          * experimentation.
1698          */
1699         max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf);
1700         *max = clamp_t(int, max_perf_adj,
1701                         cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1702
1703         min_perf = fp_ext_toint(max_perf * perf_limits->min_perf);
1704         *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1705 }
1706
1707 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1708 {
1709         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1710         cpu->pstate.current_pstate = pstate;
1711         /*
1712          * Generally, there is no guarantee that this code will always run on
1713          * the CPU being updated, so force the register update to run on the
1714          * right CPU.
1715          */
1716         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1717                       pstate_funcs.get_val(cpu, pstate));
1718 }
1719
1720 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1721 {
1722         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1723 }
1724
1725 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1726 {
1727         int min_pstate, max_pstate;
1728
1729         update_turbo_state();
1730         intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1731         intel_pstate_set_pstate(cpu, max_pstate);
1732 }
1733
1734 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1735 {
1736         cpu->pstate.min_pstate = pstate_funcs.get_min();
1737         cpu->pstate.max_pstate = pstate_funcs.get_max();
1738         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1739         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1740         cpu->pstate.scaling = pstate_funcs.get_scaling();
1741         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1742         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1743
1744         if (pstate_funcs.get_vid)
1745                 pstate_funcs.get_vid(cpu);
1746
1747         intel_pstate_set_min_pstate(cpu);
1748 }
1749
1750 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1751 {
1752         struct sample *sample = &cpu->sample;
1753
1754         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1755 }
1756
1757 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1758 {
1759         u64 aperf, mperf;
1760         unsigned long flags;
1761         u64 tsc;
1762
1763         local_irq_save(flags);
1764         rdmsrl(MSR_IA32_APERF, aperf);
1765         rdmsrl(MSR_IA32_MPERF, mperf);
1766         tsc = rdtsc();
1767         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1768                 local_irq_restore(flags);
1769                 return false;
1770         }
1771         local_irq_restore(flags);
1772
1773         cpu->last_sample_time = cpu->sample.time;
1774         cpu->sample.time = time;
1775         cpu->sample.aperf = aperf;
1776         cpu->sample.mperf = mperf;
1777         cpu->sample.tsc =  tsc;
1778         cpu->sample.aperf -= cpu->prev_aperf;
1779         cpu->sample.mperf -= cpu->prev_mperf;
1780         cpu->sample.tsc -= cpu->prev_tsc;
1781
1782         cpu->prev_aperf = aperf;
1783         cpu->prev_mperf = mperf;
1784         cpu->prev_tsc = tsc;
1785         /*
1786          * First time this function is invoked in a given cycle, all of the
1787          * previous sample data fields are equal to zero or stale and they must
1788          * be populated with meaningful numbers for things to work, so assume
1789          * that sample.time will always be reset before setting the utilization
1790          * update hook and make the caller skip the sample then.
1791          */
1792         return !!cpu->last_sample_time;
1793 }
1794
1795 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1796 {
1797         return mul_ext_fp(cpu->sample.core_avg_perf,
1798                           cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1799 }
1800
1801 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1802 {
1803         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1804                           cpu->sample.core_avg_perf);
1805 }
1806
1807 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1808 {
1809         struct sample *sample = &cpu->sample;
1810         int32_t busy_frac, boost;
1811         int target, avg_pstate;
1812
1813         busy_frac = div_fp(sample->mperf, sample->tsc);
1814
1815         boost = cpu->iowait_boost;
1816         cpu->iowait_boost >>= 1;
1817
1818         if (busy_frac < boost)
1819                 busy_frac = boost;
1820
1821         sample->busy_scaled = busy_frac * 100;
1822
1823         target = limits->no_turbo || limits->turbo_disabled ?
1824                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1825         target += target >> 2;
1826         target = mul_fp(target, busy_frac);
1827         if (target < cpu->pstate.min_pstate)
1828                 target = cpu->pstate.min_pstate;
1829
1830         /*
1831          * If the average P-state during the previous cycle was higher than the
1832          * current target, add 50% of the difference to the target to reduce
1833          * possible performance oscillations and offset possible performance
1834          * loss related to moving the workload from one CPU to another within
1835          * a package/module.
1836          */
1837         avg_pstate = get_avg_pstate(cpu);
1838         if (avg_pstate > target)
1839                 target += (avg_pstate - target) >> 1;
1840
1841         return target;
1842 }
1843
1844 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1845 {
1846         int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1847         u64 duration_ns;
1848
1849         /*
1850          * perf_scaled is the ratio of the average P-state during the last
1851          * sampling period to the P-state requested last time (in percent).
1852          *
1853          * That measures the system's response to the previous P-state
1854          * selection.
1855          */
1856         max_pstate = cpu->pstate.max_pstate_physical;
1857         current_pstate = cpu->pstate.current_pstate;
1858         perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1859                                div_fp(100 * max_pstate, current_pstate));
1860
1861         /*
1862          * Since our utilization update callback will not run unless we are
1863          * in C0, check if the actual elapsed time is significantly greater (3x)
1864          * than our sample interval.  If it is, then we were idle for a long
1865          * enough period of time to adjust our performance metric.
1866          */
1867         duration_ns = cpu->sample.time - cpu->last_sample_time;
1868         if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1869                 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1870                 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1871         } else {
1872                 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1873                 if (sample_ratio < int_tofp(1))
1874                         perf_scaled = 0;
1875         }
1876
1877         cpu->sample.busy_scaled = perf_scaled;
1878         return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1879 }
1880
1881 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1882 {
1883         int max_perf, min_perf;
1884
1885         intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1886         pstate = clamp_t(int, pstate, min_perf, max_perf);
1887         return pstate;
1888 }
1889
1890 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1891 {
1892         if (pstate == cpu->pstate.current_pstate)
1893                 return;
1894
1895         cpu->pstate.current_pstate = pstate;
1896         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1897 }
1898
1899 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1900 {
1901         int from, target_pstate;
1902         struct sample *sample;
1903
1904         from = cpu->pstate.current_pstate;
1905
1906         target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1907                 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
1908
1909         update_turbo_state();
1910
1911         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1912         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1913         intel_pstate_update_pstate(cpu, target_pstate);
1914
1915         sample = &cpu->sample;
1916         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1917                 fp_toint(sample->busy_scaled),
1918                 from,
1919                 cpu->pstate.current_pstate,
1920                 sample->mperf,
1921                 sample->aperf,
1922                 sample->tsc,
1923                 get_avg_frequency(cpu),
1924                 fp_toint(cpu->iowait_boost * 100));
1925 }
1926
1927 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1928                                      unsigned int flags)
1929 {
1930         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1931         u64 delta_ns;
1932
1933         if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
1934                 if (flags & SCHED_CPUFREQ_IOWAIT) {
1935                         cpu->iowait_boost = int_tofp(1);
1936                 } else if (cpu->iowait_boost) {
1937                         /* Clear iowait_boost if the CPU may have been idle. */
1938                         delta_ns = time - cpu->last_update;
1939                         if (delta_ns > TICK_NSEC)
1940                                 cpu->iowait_boost = 0;
1941                 }
1942                 cpu->last_update = time;
1943         }
1944
1945         delta_ns = time - cpu->sample.time;
1946         if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1947                 bool sample_taken = intel_pstate_sample(cpu, time);
1948
1949                 if (sample_taken) {
1950                         intel_pstate_calc_avg_perf(cpu);
1951                         if (!hwp_active)
1952                                 intel_pstate_adjust_busy_pstate(cpu);
1953                 }
1954         }
1955 }
1956
1957 #define ICPU(model, policy) \
1958         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1959                         (unsigned long)&policy }
1960
1961 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1962         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_params),
1963         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_params),
1964         ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       silvermont_params),
1965         ICPU(INTEL_FAM6_IVYBRIDGE,              core_params),
1966         ICPU(INTEL_FAM6_HASWELL_CORE,           core_params),
1967         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_params),
1968         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_params),
1969         ICPU(INTEL_FAM6_HASWELL_X,              core_params),
1970         ICPU(INTEL_FAM6_HASWELL_ULT,            core_params),
1971         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_params),
1972         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_params),
1973         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_params),
1974         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_params),
1975         ICPU(INTEL_FAM6_BROADWELL_X,            core_params),
1976         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_params),
1977         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_params),
1978         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_params),
1979         ICPU(INTEL_FAM6_XEON_PHI_KNM,           knl_params),
1980         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          bxt_params),
1981         {}
1982 };
1983 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1984
1985 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1986         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1987         ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1988         ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
1989         {}
1990 };
1991
1992 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1993         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params),
1994         {}
1995 };
1996
1997 static int intel_pstate_init_cpu(unsigned int cpunum)
1998 {
1999         struct cpudata *cpu;
2000
2001         cpu = all_cpu_data[cpunum];
2002
2003         if (!cpu) {
2004                 unsigned int size = sizeof(struct cpudata);
2005
2006                 if (per_cpu_limits)
2007                         size += sizeof(struct perf_limits);
2008
2009                 cpu = kzalloc(size, GFP_KERNEL);
2010                 if (!cpu)
2011                         return -ENOMEM;
2012
2013                 all_cpu_data[cpunum] = cpu;
2014                 if (per_cpu_limits)
2015                         cpu->perf_limits = (struct perf_limits *)(cpu + 1);
2016
2017                 cpu->epp_default = -EINVAL;
2018                 cpu->epp_powersave = -EINVAL;
2019                 cpu->epp_saved = -EINVAL;
2020         }
2021
2022         cpu = all_cpu_data[cpunum];
2023
2024         cpu->cpu = cpunum;
2025
2026         if (hwp_active) {
2027                 const struct x86_cpu_id *id;
2028
2029                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
2030                 if (id)
2031                         intel_pstate_disable_ee(cpunum);
2032
2033                 intel_pstate_hwp_enable(cpu);
2034                 pid_params.sample_rate_ms = 50;
2035                 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
2036         }
2037
2038         intel_pstate_get_cpu_pstates(cpu);
2039
2040         intel_pstate_busy_pid_reset(cpu);
2041
2042         pr_debug("controlling: cpu %d\n", cpunum);
2043
2044         return 0;
2045 }
2046
2047 static unsigned int intel_pstate_get(unsigned int cpu_num)
2048 {
2049         struct cpudata *cpu = all_cpu_data[cpu_num];
2050
2051         return cpu ? get_avg_frequency(cpu) : 0;
2052 }
2053
2054 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2055 {
2056         struct cpudata *cpu = all_cpu_data[cpu_num];
2057
2058         if (cpu->update_util_set)
2059                 return;
2060
2061         /* Prevent intel_pstate_update_util() from using stale data. */
2062         cpu->sample.time = 0;
2063         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2064                                      intel_pstate_update_util);
2065         cpu->update_util_set = true;
2066 }
2067
2068 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2069 {
2070         struct cpudata *cpu_data = all_cpu_data[cpu];
2071
2072         if (!cpu_data->update_util_set)
2073                 return;
2074
2075         cpufreq_remove_update_util_hook(cpu);
2076         cpu_data->update_util_set = false;
2077         synchronize_sched();
2078 }
2079
2080 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
2081                                             struct perf_limits *limits)
2082 {
2083
2084         limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
2085                                               policy->cpuinfo.max_freq);
2086         limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100);
2087         if (policy->max == policy->min) {
2088                 limits->min_policy_pct = limits->max_policy_pct;
2089         } else {
2090                 limits->min_policy_pct = DIV_ROUND_UP(policy->min * 100,
2091                                                       policy->cpuinfo.max_freq);
2092                 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct,
2093                                                  0, 100);
2094         }
2095
2096         /* Normalize user input to [min_policy_pct, max_policy_pct] */
2097         limits->min_perf_pct = max(limits->min_policy_pct,
2098                                    limits->min_sysfs_pct);
2099         limits->min_perf_pct = min(limits->max_policy_pct,
2100                                    limits->min_perf_pct);
2101         limits->max_perf_pct = min(limits->max_policy_pct,
2102                                    limits->max_sysfs_pct);
2103         limits->max_perf_pct = max(limits->min_policy_pct,
2104                                    limits->max_perf_pct);
2105
2106         /* Make sure min_perf_pct <= max_perf_pct */
2107         limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
2108
2109         limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
2110         limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
2111         limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);
2112         limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);
2113
2114         pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
2115                  limits->max_perf_pct, limits->min_perf_pct);
2116 }
2117
2118 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2119 {
2120         struct cpudata *cpu;
2121         struct perf_limits *perf_limits = NULL;
2122
2123         if (!policy->cpuinfo.max_freq)
2124                 return -ENODEV;
2125
2126         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2127                  policy->cpuinfo.max_freq, policy->max);
2128
2129         cpu = all_cpu_data[policy->cpu];
2130         cpu->policy = policy->policy;
2131
2132         if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2133             policy->max < policy->cpuinfo.max_freq &&
2134             policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
2135                 pr_debug("policy->max > max non turbo frequency\n");
2136                 policy->max = policy->cpuinfo.max_freq;
2137         }
2138
2139         if (per_cpu_limits)
2140                 perf_limits = cpu->perf_limits;
2141
2142         mutex_lock(&intel_pstate_limits_lock);
2143
2144         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
2145                 pr_debug("set performance\n");
2146                 if (!perf_limits) {
2147                         limits = &performance_limits;
2148                         perf_limits = limits;
2149                 }
2150         } else {
2151                 pr_debug("set powersave\n");
2152                 if (!perf_limits) {
2153                         limits = &powersave_limits;
2154                         perf_limits = limits;
2155                 }
2156
2157         }
2158
2159         intel_pstate_update_perf_limits(policy, perf_limits);
2160
2161         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2162                 /*
2163                  * NOHZ_FULL CPUs need this as the governor callback may not
2164                  * be invoked on them.
2165                  */
2166                 intel_pstate_clear_update_util_hook(policy->cpu);
2167                 intel_pstate_max_within_limits(cpu);
2168         }
2169
2170         intel_pstate_set_update_util_hook(policy->cpu);
2171
2172         intel_pstate_hwp_set_policy(policy);
2173
2174         mutex_unlock(&intel_pstate_limits_lock);
2175
2176         return 0;
2177 }
2178
2179 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2180 {
2181         struct cpudata *cpu = all_cpu_data[policy->cpu];
2182         struct perf_limits *perf_limits;
2183
2184         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE)
2185                 perf_limits = &performance_limits;
2186         else
2187                 perf_limits = &powersave_limits;
2188
2189         update_turbo_state();
2190         policy->cpuinfo.max_freq = perf_limits->turbo_disabled ||
2191                                         perf_limits->no_turbo ?
2192                                         cpu->pstate.max_freq :
2193                                         cpu->pstate.turbo_freq;
2194
2195         cpufreq_verify_within_cpu_limits(policy);
2196
2197         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2198             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2199                 return -EINVAL;
2200
2201         /* When per-CPU limits are used, sysfs limits are not used */
2202         if (!per_cpu_limits) {
2203                 unsigned int max_freq, min_freq;
2204
2205                 max_freq = policy->cpuinfo.max_freq *
2206                                         perf_limits->max_sysfs_pct / 100;
2207                 min_freq = policy->cpuinfo.max_freq *
2208                                         perf_limits->min_sysfs_pct / 100;
2209                 cpufreq_verify_within_limits(policy, min_freq, max_freq);
2210         }
2211
2212         return 0;
2213 }
2214
2215 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2216 {
2217         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2218 }
2219
2220 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2221 {
2222         pr_debug("CPU %d exiting\n", policy->cpu);
2223
2224         intel_pstate_clear_update_util_hook(policy->cpu);
2225         if (hwp_active)
2226                 intel_pstate_hwp_save_state(policy);
2227         else
2228                 intel_cpufreq_stop_cpu(policy);
2229 }
2230
2231 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2232 {
2233         intel_pstate_exit_perf_limits(policy);
2234
2235         policy->fast_switch_possible = false;
2236
2237         return 0;
2238 }
2239
2240 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2241 {
2242         struct cpudata *cpu;
2243         int rc;
2244
2245         rc = intel_pstate_init_cpu(policy->cpu);
2246         if (rc)
2247                 return rc;
2248
2249         cpu = all_cpu_data[policy->cpu];
2250
2251         if (per_cpu_limits)
2252                 intel_pstate_init_limits(cpu->perf_limits);
2253
2254         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2255         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2256
2257         /* cpuinfo and default policy values */
2258         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2259         update_turbo_state();
2260         policy->cpuinfo.max_freq = limits->turbo_disabled ?
2261                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2262         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2263
2264         intel_pstate_init_acpi_perf_limits(policy);
2265         cpumask_set_cpu(policy->cpu, policy->cpus);
2266
2267         policy->fast_switch_possible = true;
2268
2269         return 0;
2270 }
2271
2272 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2273 {
2274         int ret = __intel_pstate_cpu_init(policy);
2275
2276         if (ret)
2277                 return ret;
2278
2279         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2280         if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
2281                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2282         else
2283                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2284
2285         return 0;
2286 }
2287
2288 static struct cpufreq_driver intel_pstate = {
2289         .flags          = CPUFREQ_CONST_LOOPS,
2290         .verify         = intel_pstate_verify_policy,
2291         .setpolicy      = intel_pstate_set_policy,
2292         .suspend        = intel_pstate_hwp_save_state,
2293         .resume         = intel_pstate_resume,
2294         .get            = intel_pstate_get,
2295         .init           = intel_pstate_cpu_init,
2296         .exit           = intel_pstate_cpu_exit,
2297         .stop_cpu       = intel_pstate_stop_cpu,
2298         .name           = "intel_pstate",
2299 };
2300
2301 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2302 {
2303         struct cpudata *cpu = all_cpu_data[policy->cpu];
2304
2305         update_turbo_state();
2306         policy->cpuinfo.max_freq = limits->turbo_disabled ?
2307                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2308
2309         cpufreq_verify_within_cpu_limits(policy);
2310
2311         return 0;
2312 }
2313
2314 static unsigned int intel_cpufreq_turbo_update(struct cpudata *cpu,
2315                                                struct cpufreq_policy *policy,
2316                                                unsigned int target_freq)
2317 {
2318         unsigned int max_freq;
2319
2320         update_turbo_state();
2321
2322         max_freq = limits->no_turbo || limits->turbo_disabled ?
2323                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2324         policy->cpuinfo.max_freq = max_freq;
2325         if (policy->max > max_freq)
2326                 policy->max = max_freq;
2327
2328         if (target_freq > max_freq)
2329                 target_freq = max_freq;
2330
2331         return target_freq;
2332 }
2333
2334 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2335                                 unsigned int target_freq,
2336                                 unsigned int relation)
2337 {
2338         struct cpudata *cpu = all_cpu_data[policy->cpu];
2339         struct cpufreq_freqs freqs;
2340         int target_pstate;
2341
2342         freqs.old = policy->cur;
2343         freqs.new = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2344
2345         cpufreq_freq_transition_begin(policy, &freqs);
2346         switch (relation) {
2347         case CPUFREQ_RELATION_L:
2348                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2349                 break;
2350         case CPUFREQ_RELATION_H:
2351                 target_pstate = freqs.new / cpu->pstate.scaling;
2352                 break;
2353         default:
2354                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2355                 break;
2356         }
2357         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2358         if (target_pstate != cpu->pstate.current_pstate) {
2359                 cpu->pstate.current_pstate = target_pstate;
2360                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2361                               pstate_funcs.get_val(cpu, target_pstate));
2362         }
2363         freqs.new = target_pstate * cpu->pstate.scaling;
2364         cpufreq_freq_transition_end(policy, &freqs, false);
2365
2366         return 0;
2367 }
2368
2369 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2370                                               unsigned int target_freq)
2371 {
2372         struct cpudata *cpu = all_cpu_data[policy->cpu];
2373         int target_pstate;
2374
2375         target_freq = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2376         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2377         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2378         intel_pstate_update_pstate(cpu, target_pstate);
2379         return target_pstate * cpu->pstate.scaling;
2380 }
2381
2382 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2383 {
2384         int ret = __intel_pstate_cpu_init(policy);
2385
2386         if (ret)
2387                 return ret;
2388
2389         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2390         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2391         policy->cur = policy->cpuinfo.min_freq;
2392
2393         return 0;
2394 }
2395
2396 static struct cpufreq_driver intel_cpufreq = {
2397         .flags          = CPUFREQ_CONST_LOOPS,
2398         .verify         = intel_cpufreq_verify_policy,
2399         .target         = intel_cpufreq_target,
2400         .fast_switch    = intel_cpufreq_fast_switch,
2401         .init           = intel_cpufreq_cpu_init,
2402         .exit           = intel_pstate_cpu_exit,
2403         .stop_cpu       = intel_cpufreq_stop_cpu,
2404         .name           = "intel_cpufreq",
2405 };
2406
2407 static struct cpufreq_driver *intel_pstate_driver = &intel_pstate;
2408
2409 static void intel_pstate_driver_cleanup(void)
2410 {
2411         unsigned int cpu;
2412
2413         get_online_cpus();
2414         for_each_online_cpu(cpu) {
2415                 if (all_cpu_data[cpu]) {
2416                         if (intel_pstate_driver == &intel_pstate)
2417                                 intel_pstate_clear_update_util_hook(cpu);
2418
2419                         kfree(all_cpu_data[cpu]);
2420                         all_cpu_data[cpu] = NULL;
2421                 }
2422         }
2423         put_online_cpus();
2424 }
2425
2426 static int intel_pstate_register_driver(void)
2427 {
2428         int ret;
2429
2430         intel_pstate_init_limits(&powersave_limits);
2431         intel_pstate_set_performance_limits(&performance_limits);
2432         if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE) &&
2433             intel_pstate_driver == &intel_pstate)
2434                 limits = &performance_limits;
2435         else
2436                 limits = &powersave_limits;
2437
2438         ret = cpufreq_register_driver(intel_pstate_driver);
2439         if (ret) {
2440                 intel_pstate_driver_cleanup();
2441                 return ret;
2442         }
2443
2444         mutex_lock(&intel_pstate_limits_lock);
2445         driver_registered = true;
2446         mutex_unlock(&intel_pstate_limits_lock);
2447
2448         if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2449             pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2450                 intel_pstate_debug_expose_params();
2451
2452         return 0;
2453 }
2454
2455 static int intel_pstate_unregister_driver(void)
2456 {
2457         if (hwp_active)
2458                 return -EBUSY;
2459
2460         if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2461             pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2462                 intel_pstate_debug_hide_params();
2463
2464         mutex_lock(&intel_pstate_limits_lock);
2465         driver_registered = false;
2466         mutex_unlock(&intel_pstate_limits_lock);
2467
2468         cpufreq_unregister_driver(intel_pstate_driver);
2469         intel_pstate_driver_cleanup();
2470
2471         return 0;
2472 }
2473
2474 static ssize_t intel_pstate_show_status(char *buf)
2475 {
2476         if (!driver_registered)
2477                 return sprintf(buf, "off\n");
2478
2479         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2480                                         "active" : "passive");
2481 }
2482
2483 static int intel_pstate_update_status(const char *buf, size_t size)
2484 {
2485         int ret;
2486
2487         if (size == 3 && !strncmp(buf, "off", size))
2488                 return driver_registered ?
2489                         intel_pstate_unregister_driver() : -EINVAL;
2490
2491         if (size == 6 && !strncmp(buf, "active", size)) {
2492                 if (driver_registered) {
2493                         if (intel_pstate_driver == &intel_pstate)
2494                                 return 0;
2495
2496                         ret = intel_pstate_unregister_driver();
2497                         if (ret)
2498                                 return ret;
2499                 }
2500
2501                 intel_pstate_driver = &intel_pstate;
2502                 return intel_pstate_register_driver();
2503         }
2504
2505         if (size == 7 && !strncmp(buf, "passive", size)) {
2506                 if (driver_registered) {
2507                         if (intel_pstate_driver != &intel_pstate)
2508                                 return 0;
2509
2510                         ret = intel_pstate_unregister_driver();
2511                         if (ret)
2512                                 return ret;
2513                 }
2514
2515                 intel_pstate_driver = &intel_cpufreq;
2516                 return intel_pstate_register_driver();
2517         }
2518
2519         return -EINVAL;
2520 }
2521
2522 static int no_load __initdata;
2523 static int no_hwp __initdata;
2524 static int hwp_only __initdata;
2525 static unsigned int force_load __initdata;
2526
2527 static int __init intel_pstate_msrs_not_valid(void)
2528 {
2529         if (!pstate_funcs.get_max() ||
2530             !pstate_funcs.get_min() ||
2531             !pstate_funcs.get_turbo())
2532                 return -ENODEV;
2533
2534         return 0;
2535 }
2536
2537 static void __init copy_pid_params(struct pstate_adjust_policy *policy)
2538 {
2539         pid_params.sample_rate_ms = policy->sample_rate_ms;
2540         pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
2541         pid_params.p_gain_pct = policy->p_gain_pct;
2542         pid_params.i_gain_pct = policy->i_gain_pct;
2543         pid_params.d_gain_pct = policy->d_gain_pct;
2544         pid_params.deadband = policy->deadband;
2545         pid_params.setpoint = policy->setpoint;
2546 }
2547
2548 #ifdef CONFIG_ACPI
2549 static void intel_pstate_use_acpi_profile(void)
2550 {
2551         if (acpi_gbl_FADT.preferred_profile == PM_MOBILE)
2552                 pstate_funcs.get_target_pstate =
2553                                 get_target_pstate_use_cpu_load;
2554 }
2555 #else
2556 static void intel_pstate_use_acpi_profile(void)
2557 {
2558 }
2559 #endif
2560
2561 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2562 {
2563         pstate_funcs.get_max   = funcs->get_max;
2564         pstate_funcs.get_max_physical = funcs->get_max_physical;
2565         pstate_funcs.get_min   = funcs->get_min;
2566         pstate_funcs.get_turbo = funcs->get_turbo;
2567         pstate_funcs.get_scaling = funcs->get_scaling;
2568         pstate_funcs.get_val   = funcs->get_val;
2569         pstate_funcs.get_vid   = funcs->get_vid;
2570         pstate_funcs.get_target_pstate = funcs->get_target_pstate;
2571
2572         intel_pstate_use_acpi_profile();
2573 }
2574
2575 #ifdef CONFIG_ACPI
2576
2577 static bool __init intel_pstate_no_acpi_pss(void)
2578 {
2579         int i;
2580
2581         for_each_possible_cpu(i) {
2582                 acpi_status status;
2583                 union acpi_object *pss;
2584                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2585                 struct acpi_processor *pr = per_cpu(processors, i);
2586
2587                 if (!pr)
2588                         continue;
2589
2590                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2591                 if (ACPI_FAILURE(status))
2592                         continue;
2593
2594                 pss = buffer.pointer;
2595                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2596                         kfree(pss);
2597                         return false;
2598                 }
2599
2600                 kfree(pss);
2601         }
2602
2603         return true;
2604 }
2605
2606 static bool __init intel_pstate_has_acpi_ppc(void)
2607 {
2608         int i;
2609
2610         for_each_possible_cpu(i) {
2611                 struct acpi_processor *pr = per_cpu(processors, i);
2612
2613                 if (!pr)
2614                         continue;
2615                 if (acpi_has_method(pr->handle, "_PPC"))
2616                         return true;
2617         }
2618         return false;
2619 }
2620
2621 enum {
2622         PSS,
2623         PPC,
2624 };
2625
2626 struct hw_vendor_info {
2627         u16  valid;
2628         char oem_id[ACPI_OEM_ID_SIZE];
2629         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2630         int  oem_pwr_table;
2631 };
2632
2633 /* Hardware vendor-specific info that has its own power management modes */
2634 static struct hw_vendor_info vendor_info[] __initdata = {
2635         {1, "HP    ", "ProLiant", PSS},
2636         {1, "ORACLE", "X4-2    ", PPC},
2637         {1, "ORACLE", "X4-2L   ", PPC},
2638         {1, "ORACLE", "X4-2B   ", PPC},
2639         {1, "ORACLE", "X3-2    ", PPC},
2640         {1, "ORACLE", "X3-2L   ", PPC},
2641         {1, "ORACLE", "X3-2B   ", PPC},
2642         {1, "ORACLE", "X4470M2 ", PPC},
2643         {1, "ORACLE", "X4270M3 ", PPC},
2644         {1, "ORACLE", "X4270M2 ", PPC},
2645         {1, "ORACLE", "X4170M2 ", PPC},
2646         {1, "ORACLE", "X4170 M3", PPC},
2647         {1, "ORACLE", "X4275 M3", PPC},
2648         {1, "ORACLE", "X6-2    ", PPC},
2649         {1, "ORACLE", "Sudbury ", PPC},
2650         {0, "", ""},
2651 };
2652
2653 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2654 {
2655         struct acpi_table_header hdr;
2656         struct hw_vendor_info *v_info;
2657         const struct x86_cpu_id *id;
2658         u64 misc_pwr;
2659
2660         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2661         if (id) {
2662                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2663                 if ( misc_pwr & (1 << 8))
2664                         return true;
2665         }
2666
2667         if (acpi_disabled ||
2668             ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2669                 return false;
2670
2671         for (v_info = vendor_info; v_info->valid; v_info++) {
2672                 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2673                         !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2674                                                 ACPI_OEM_TABLE_ID_SIZE))
2675                         switch (v_info->oem_pwr_table) {
2676                         case PSS:
2677                                 return intel_pstate_no_acpi_pss();
2678                         case PPC:
2679                                 return intel_pstate_has_acpi_ppc() &&
2680                                         (!force_load);
2681                         }
2682         }
2683
2684         return false;
2685 }
2686
2687 static void intel_pstate_request_control_from_smm(void)
2688 {
2689         /*
2690          * It may be unsafe to request P-states control from SMM if _PPC support
2691          * has not been enabled.
2692          */
2693         if (acpi_ppc)
2694                 acpi_processor_pstate_control();
2695 }
2696 #else /* CONFIG_ACPI not enabled */
2697 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2698 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2699 static inline void intel_pstate_request_control_from_smm(void) {}
2700 #endif /* CONFIG_ACPI */
2701
2702 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2703         { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2704         {}
2705 };
2706
2707 static int __init intel_pstate_init(void)
2708 {
2709         const struct x86_cpu_id *id;
2710         struct cpu_defaults *cpu_def;
2711         int rc = 0;
2712
2713         if (no_load)
2714                 return -ENODEV;
2715
2716         if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
2717                 copy_cpu_funcs(&core_params.funcs);
2718                 hwp_active++;
2719                 intel_pstate.attr = hwp_cpufreq_attrs;
2720                 goto hwp_cpu_matched;
2721         }
2722
2723         id = x86_match_cpu(intel_pstate_cpu_ids);
2724         if (!id)
2725                 return -ENODEV;
2726
2727         cpu_def = (struct cpu_defaults *)id->driver_data;
2728
2729         copy_pid_params(&cpu_def->pid_policy);
2730         copy_cpu_funcs(&cpu_def->funcs);
2731
2732         if (intel_pstate_msrs_not_valid())
2733                 return -ENODEV;
2734
2735 hwp_cpu_matched:
2736         /*
2737          * The Intel pstate driver will be ignored if the platform
2738          * firmware has its own power management modes.
2739          */
2740         if (intel_pstate_platform_pwr_mgmt_exists())
2741                 return -ENODEV;
2742
2743         if (!hwp_active && hwp_only)
2744                 return -ENOTSUPP;
2745
2746         pr_info("Intel P-state driver initializing\n");
2747
2748         all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2749         if (!all_cpu_data)
2750                 return -ENOMEM;
2751
2752         intel_pstate_request_control_from_smm();
2753
2754         intel_pstate_sysfs_expose_params();
2755
2756         mutex_lock(&intel_pstate_driver_lock);
2757         rc = intel_pstate_register_driver();
2758         mutex_unlock(&intel_pstate_driver_lock);
2759         if (rc)
2760                 return rc;
2761
2762         if (hwp_active)
2763                 pr_info("HWP enabled\n");
2764
2765         return 0;
2766 }
2767 device_initcall(intel_pstate_init);
2768
2769 static int __init intel_pstate_setup(char *str)
2770 {
2771         if (!str)
2772                 return -EINVAL;
2773
2774         if (!strcmp(str, "disable")) {
2775                 no_load = 1;
2776         } else if (!strcmp(str, "passive")) {
2777                 pr_info("Passive mode enabled\n");
2778                 intel_pstate_driver = &intel_cpufreq;
2779                 no_hwp = 1;
2780         }
2781         if (!strcmp(str, "no_hwp")) {
2782                 pr_info("HWP disabled\n");
2783                 no_hwp = 1;
2784         }
2785         if (!strcmp(str, "force"))
2786                 force_load = 1;
2787         if (!strcmp(str, "hwp_only"))
2788                 hwp_only = 1;
2789         if (!strcmp(str, "per_cpu_perf_limits"))
2790                 per_cpu_limits = true;
2791
2792 #ifdef CONFIG_ACPI
2793         if (!strcmp(str, "support_acpi_ppc"))
2794                 acpi_ppc = true;
2795 #endif
2796
2797         return 0;
2798 }
2799 early_param("intel_pstate", intel_pstate_setup);
2800
2801 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2802 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2803 MODULE_LICENSE("GPL");