drivers/crypto/caam/caamhash.c

   1 /*
   2  * caam - Freescale FSL CAAM support for ahash functions of crypto API
   3  *
   4  * Copyright 2011 Freescale Semiconductor, Inc.
   5  *
   6  * Based on caamalg.c crypto API driver.
   7  *
   8  * relationship of digest job descriptor or first job descriptor after init to
   9  * shared descriptors:
  10  *
  11  * ---------------                     ---------------
  12  * | JobDesc #1  |-------------------->|  ShareDesc  |
  13  * | *(packet 1) |                     |  (hashKey)  |
  14  * ---------------                     | (operation) |
  15  *                                     ---------------
  16  *
  17  * relationship of subsequent job descriptors to shared descriptors:
  18  *
  19  * ---------------                     ---------------
  20  * | JobDesc #2  |-------------------->|  ShareDesc  |
  21  * | *(packet 2) |      |------------->|  (hashKey)  |
  22  * ---------------      |    |-------->| (operation) |
  23  *       .              |    |         | (load ctx2) |
  24  *       .              |    |         ---------------
  25  * ---------------      |    |
  26  * | JobDesc #3  |------|    |
  27  * | *(packet 3) |           |
  28  * ---------------           |
  29  *       .                   |
  30  *       .                   |
  31  * ---------------           |
  32  * | JobDesc #4  |------------
  33  * | *(packet 4) |
  34  * ---------------
  35  *
  36  * The SharedDesc never changes for a connection unless rekeyed, but
  37  * each packet will likely be in a different place. So all we need
  38  * to know to process the packet is where the input is, where the
  39  * output goes, and what context we want to process with. Context is
  40  * in the SharedDesc, packet references in the JobDesc.
  41  *
  42  * So, a job desc looks like:
  43  *
  44  * ---------------------
  45  * | Header            |
  46  * | ShareDesc Pointer |
  47  * | SEQ_OUT_PTR       |
  48  * | (output buffer)   |
  49  * | (output length)   |
  50  * | SEQ_IN_PTR        |
  51  * | (input buffer)    |
  52  * | (input length)    |
  53  * ---------------------
  54  */
  55
  56 #include "compat.h"
  57
  58 #include "regs.h"
  59 #include "intern.h"
  60 #include "desc_constr.h"
  61 #include "jr.h"
  62 #include "error.h"
  63 #include "sg_sw_sec4.h"
  64 #include "key_gen.h"
  65
  66 #define CAAM_CRA_PRIORITY               3000
  67
  68 /* max hash key is max split key size */
  69 #define CAAM_MAX_HASH_KEY_SIZE          (SHA512_DIGEST_SIZE * 2)
  70
  71 #define CAAM_MAX_HASH_BLOCK_SIZE        SHA512_BLOCK_SIZE
  72 #define CAAM_MAX_HASH_DIGEST_SIZE       SHA512_DIGEST_SIZE
  73
  74 /* length of descriptors text */
  75 #define DESC_AHASH_BASE                 (4 * CAAM_CMD_SZ)
  76 #define DESC_AHASH_UPDATE_LEN           (6 * CAAM_CMD_SZ)
  77 #define DESC_AHASH_UPDATE_FIRST_LEN     (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
  78 #define DESC_AHASH_FINAL_LEN            (DESC_AHASH_BASE + 5 * CAAM_CMD_SZ)
  79 #define DESC_AHASH_FINUP_LEN            (DESC_AHASH_BASE + 5 * CAAM_CMD_SZ)
  80 #define DESC_AHASH_DIGEST_LEN           (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ)
  81
  82 #define DESC_HASH_MAX_USED_BYTES        (DESC_AHASH_FINAL_LEN + \
  83                                          CAAM_MAX_HASH_KEY_SIZE)
  84 #define DESC_HASH_MAX_USED_LEN          (DESC_HASH_MAX_USED_BYTES / CAAM_CMD_SZ)
  85
  86 /* caam context sizes for hashes: running digest + 8 */
  87 #define HASH_MSG_LEN                    8
  88 #define MAX_CTX_LEN                     (HASH_MSG_LEN + SHA512_DIGEST_SIZE)
  89
  90 #ifdef DEBUG
  91 /* for print_hex_dumps with line references */
  92 #define debug(format, arg...) printk(format, arg)
  93 #else
  94 #define debug(format, arg...)
  95 #endif
  96
  97
  98 static struct list_head hash_list;
  99
 100 /* ahash per-session context */
 101 struct caam_hash_ctx {
 102         struct device *jrdev;
 103         u32 sh_desc_update[DESC_HASH_MAX_USED_LEN];
 104         u32 sh_desc_update_first[DESC_HASH_MAX_USED_LEN];
 105         u32 sh_desc_fin[DESC_HASH_MAX_USED_LEN];
 106         u32 sh_desc_digest[DESC_HASH_MAX_USED_LEN];
 107         u32 sh_desc_finup[DESC_HASH_MAX_USED_LEN];
 108         dma_addr_t sh_desc_update_dma;
 109         dma_addr_t sh_desc_update_first_dma;
 110         dma_addr_t sh_desc_fin_dma;
 111         dma_addr_t sh_desc_digest_dma;
 112         dma_addr_t sh_desc_finup_dma;
 113         u32 alg_type;
 114         u32 alg_op;
 115         u8 key[CAAM_MAX_HASH_KEY_SIZE];
 116         dma_addr_t key_dma;
 117         int ctx_len;
 118         unsigned int split_key_len;
 119         unsigned int split_key_pad_len;
 120 };
 121
 122 /* ahash state */
 123 struct caam_hash_state {
 124         dma_addr_t buf_dma;
 125         dma_addr_t ctx_dma;
 126         u8 buf_0[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
 127         int buflen_0;
 128         u8 buf_1[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
 129         int buflen_1;
 130         u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned;
 131         int (*update)(struct ahash_request *req);
 132         int (*final)(struct ahash_request *req);
 133         int (*finup)(struct ahash_request *req);
 134         int current_buf;
 135 };
 136
 137 struct caam_export_state {
 138         u8 buf[CAAM_MAX_HASH_BLOCK_SIZE];
 139         u8 caam_ctx[MAX_CTX_LEN];
 140         int buflen;
 141         int (*update)(struct ahash_request *req);
 142         int (*final)(struct ahash_request *req);
 143         int (*finup)(struct ahash_request *req);
 144 };
 145
 146 /* Common job descriptor seq in/out ptr routines */
 147
 148 /* Map state->caam_ctx, and append seq_out_ptr command that points to it */
 149 static inline int map_seq_out_ptr_ctx(u32 *desc, struct device *jrdev,
 150                                       struct caam_hash_state *state,
 151                                       int ctx_len)
 152 {
 153         state->ctx_dma = dma_map_single(jrdev, state->caam_ctx,
 154                                         ctx_len, DMA_FROM_DEVICE);
 155         if (dma_mapping_error(jrdev, state->ctx_dma)) {
 156                 dev_err(jrdev, "unable to map ctx\n");
 157                 return -ENOMEM;
 158         }
 159
 160         append_seq_out_ptr(desc, state->ctx_dma, ctx_len, 0);
 161
 162         return 0;
 163 }
 164
 165 /* Map req->result, and append seq_out_ptr command that points to it */
 166 static inline dma_addr_t map_seq_out_ptr_result(u32 *desc, struct device *jrdev,
 167                                                 u8 *result, int digestsize)
 168 {
 169         dma_addr_t dst_dma;
 170
 171         dst_dma = dma_map_single(jrdev, result, digestsize, DMA_FROM_DEVICE);
 172         append_seq_out_ptr(desc, dst_dma, digestsize, 0);
 173
 174         return dst_dma;
 175 }
 176
 177 /* Map current buffer in state and put it in link table */
 178 static inline dma_addr_t buf_map_to_sec4_sg(struct device *jrdev,
 179                                             struct sec4_sg_entry *sec4_sg,
 180                                             u8 *buf, int buflen)
 181 {
 182         dma_addr_t buf_dma;
 183
 184         buf_dma = dma_map_single(jrdev, buf, buflen, DMA_TO_DEVICE);
 185         dma_to_sec4_sg_one(sec4_sg, buf_dma, buflen, 0);
 186
 187         return buf_dma;
 188 }
 189
 190 /* Map req->src and put it in link table */
 191 static inline void src_map_to_sec4_sg(struct device *jrdev,
 192                                       struct scatterlist *src, int src_nents,
 193                                       struct sec4_sg_entry *sec4_sg)
 194 {
 195         dma_map_sg(jrdev, src, src_nents, DMA_TO_DEVICE);
 196         sg_to_sec4_sg_last(src, src_nents, sec4_sg, 0);
 197 }
 198
 199 /*
 200  * Only put buffer in link table if it contains data, which is possible,
 201  * since a buffer has previously been used, and needs to be unmapped,
 202  */
 203 static inline dma_addr_t
 204 try_buf_map_to_sec4_sg(struct device *jrdev, struct sec4_sg_entry *sec4_sg,
 205                        u8 *buf, dma_addr_t buf_dma, int buflen,
 206                        int last_buflen)
 207 {
 208         if (buf_dma && !dma_mapping_error(jrdev, buf_dma))
 209                 dma_unmap_single(jrdev, buf_dma, last_buflen, DMA_TO_DEVICE);
 210         if (buflen)
 211                 buf_dma = buf_map_to_sec4_sg(jrdev, sec4_sg, buf, buflen);
 212         else
 213                 buf_dma = 0;
 214
 215         return buf_dma;
 216 }
 217
 218 /* Map state->caam_ctx, and add it to link table */
 219 static inline int ctx_map_to_sec4_sg(u32 *desc, struct device *jrdev,
 220                                      struct caam_hash_state *state, int ctx_len,
 221                                      struct sec4_sg_entry *sec4_sg, u32 flag)
 222 {
 223         state->ctx_dma = dma_map_single(jrdev, state->caam_ctx, ctx_len, flag);
 224         if (dma_mapping_error(jrdev, state->ctx_dma)) {
 225                 dev_err(jrdev, "unable to map ctx\n");
 226                 return -ENOMEM;
 227         }
 228
 229         dma_to_sec4_sg_one(sec4_sg, state->ctx_dma, ctx_len, 0);
 230
 231         return 0;
 232 }
 233
 234 /* Common shared descriptor commands */
 235 static inline void append_key_ahash(u32 *desc, struct caam_hash_ctx *ctx)
 236 {
 237         append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len,
 238                           ctx->split_key_len, CLASS_2 |
 239                           KEY_DEST_MDHA_SPLIT | KEY_ENC);
 240 }
 241
 242 /* Append key if it has been set */
 243 static inline void init_sh_desc_key_ahash(u32 *desc, struct caam_hash_ctx *ctx)
 244 {
 245         u32 *key_jump_cmd;
 246
 247         init_sh_desc(desc, HDR_SHARE_SERIAL);
 248
 249         if (ctx->split_key_len) {
 250                 /* Skip if already shared */
 251                 key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
 252                                            JUMP_COND_SHRD);
 253
 254                 append_key_ahash(desc, ctx);
 255
 256                 set_jump_tgt_here(desc, key_jump_cmd);
 257         }
 258
 259         /* Propagate errors from shared to job descriptor */
 260         append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
 261 }
 262
 263 /*
 264  * For ahash read data from seqin following state->caam_ctx,
 265  * and write resulting class2 context to seqout, which may be state->caam_ctx
 266  * or req->result
 267  */
 268 static inline void ahash_append_load_str(u32 *desc, int digestsize)
 269 {
 270         /* Calculate remaining bytes to read */
 271         append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
 272
 273         /* Read remaining bytes */
 274         append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_LAST2 |
 275                              FIFOLD_TYPE_MSG | KEY_VLF);
 276
 277         /* Store class2 context bytes */
 278         append_seq_store(desc, digestsize, LDST_CLASS_2_CCB |
 279                          LDST_SRCDST_BYTE_CONTEXT);
 280 }
 281
 282 /*
 283  * For ahash update, final and finup, import context, read and write to seqout
 284  */
 285 static inline void ahash_ctx_data_to_out(u32 *desc, u32 op, u32 state,
 286                                          int digestsize,
 287                                          struct caam_hash_ctx *ctx)
 288 {
 289         init_sh_desc_key_ahash(desc, ctx);
 290
 291         /* Import context from software */
 292         append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
 293                    LDST_CLASS_2_CCB | ctx->ctx_len);
 294
 295         /* Class 2 operation */
 296         append_operation(desc, op | state | OP_ALG_ENCRYPT);
 297
 298         /*
 299          * Load from buf and/or src and write to req->result or state->context
 300          */
 301         ahash_append_load_str(desc, digestsize);
 302 }
 303
 304 /* For ahash firsts and digest, read and write to seqout */
 305 static inline void ahash_data_to_out(u32 *desc, u32 op, u32 state,
 306                                      int digestsize, struct caam_hash_ctx *ctx)
 307 {
 308         init_sh_desc_key_ahash(desc, ctx);
 309
 310         /* Class 2 operation */
 311         append_operation(desc, op | state | OP_ALG_ENCRYPT);
 312
 313         /*
 314          * Load from buf and/or src and write to req->result or state->context
 315          */
 316         ahash_append_load_str(desc, digestsize);
 317 }
 318
 319 static int ahash_set_sh_desc(struct crypto_ahash *ahash)
 320 {
 321         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 322         int digestsize = crypto_ahash_digestsize(ahash);
 323         struct device *jrdev = ctx->jrdev;
 324         u32 have_key = 0;
 325         u32 *desc;
 326
 327         if (ctx->split_key_len)
 328                 have_key = OP_ALG_AAI_HMAC_PRECOMP;
 329
 330         /* ahash_update shared descriptor */
 331         desc = ctx->sh_desc_update;
 332
 333         init_sh_desc(desc, HDR_SHARE_SERIAL);
 334
 335         /* Import context from software */
 336         append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
 337                    LDST_CLASS_2_CCB | ctx->ctx_len);
 338
 339         /* Class 2 operation */
 340         append_operation(desc, ctx->alg_type | OP_ALG_AS_UPDATE |
 341                          OP_ALG_ENCRYPT);
 342
 343         /* Load data and write to result or context */
 344         ahash_append_load_str(desc, ctx->ctx_len);
 345
 346         ctx->sh_desc_update_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
 347                                                  DMA_TO_DEVICE);
 348         if (dma_mapping_error(jrdev, ctx->sh_desc_update_dma)) {
 349                 dev_err(jrdev, "unable to map shared descriptor\n");
 350                 return -ENOMEM;
 351         }
 352 #ifdef DEBUG
 353         print_hex_dump(KERN_ERR,
 354                        "ahash update shdesc@"__stringify(__LINE__)": ",
 355                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
 356 #endif
 357
 358         /* ahash_update_first shared descriptor */
 359         desc = ctx->sh_desc_update_first;
 360
 361         ahash_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INIT,
 362                           ctx->ctx_len, ctx);
 363
 364         ctx->sh_desc_update_first_dma = dma_map_single(jrdev, desc,
 365                                                        desc_bytes(desc),
 366                                                        DMA_TO_DEVICE);
 367         if (dma_mapping_error(jrdev, ctx->sh_desc_update_first_dma)) {
 368                 dev_err(jrdev, "unable to map shared descriptor\n");
 369                 return -ENOMEM;
 370         }
 371 #ifdef DEBUG
 372         print_hex_dump(KERN_ERR,
 373                        "ahash update first shdesc@"__stringify(__LINE__)": ",
 374                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
 375 #endif
 376
 377         /* ahash_final shared descriptor */
 378         desc = ctx->sh_desc_fin;
 379
 380         ahash_ctx_data_to_out(desc, have_key | ctx->alg_type,
 381                               OP_ALG_AS_FINALIZE, digestsize, ctx);
 382
 383         ctx->sh_desc_fin_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
 384                                               DMA_TO_DEVICE);
 385         if (dma_mapping_error(jrdev, ctx->sh_desc_fin_dma)) {
 386                 dev_err(jrdev, "unable to map shared descriptor\n");
 387                 return -ENOMEM;
 388         }
 389 #ifdef DEBUG
 390         print_hex_dump(KERN_ERR, "ahash final shdesc@"__stringify(__LINE__)": ",
 391                        DUMP_PREFIX_ADDRESS, 16, 4, desc,
 392                        desc_bytes(desc), 1);
 393 #endif
 394
 395         /* ahash_finup shared descriptor */
 396         desc = ctx->sh_desc_finup;
 397
 398         ahash_ctx_data_to_out(desc, have_key | ctx->alg_type,
 399                               OP_ALG_AS_FINALIZE, digestsize, ctx);
 400
 401         ctx->sh_desc_finup_dma = dma_map_single(jrdev, desc, desc_bytes(desc),
 402                                                 DMA_TO_DEVICE);
 403         if (dma_mapping_error(jrdev, ctx->sh_desc_finup_dma)) {
 404                 dev_err(jrdev, "unable to map shared descriptor\n");
 405                 return -ENOMEM;
 406         }
 407 #ifdef DEBUG
 408         print_hex_dump(KERN_ERR, "ahash finup shdesc@"__stringify(__LINE__)": ",
 409                        DUMP_PREFIX_ADDRESS, 16, 4, desc,
 410                        desc_bytes(desc), 1);
 411 #endif
 412
 413         /* ahash_digest shared descriptor */
 414         desc = ctx->sh_desc_digest;
 415
 416         ahash_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INITFINAL,
 417                           digestsize, ctx);
 418
 419         ctx->sh_desc_digest_dma = dma_map_single(jrdev, desc,
 420                                                  desc_bytes(desc),
 421                                                  DMA_TO_DEVICE);
 422         if (dma_mapping_error(jrdev, ctx->sh_desc_digest_dma)) {
 423                 dev_err(jrdev, "unable to map shared descriptor\n");
 424                 return -ENOMEM;
 425         }
 426 #ifdef DEBUG
 427         print_hex_dump(KERN_ERR,
 428                        "ahash digest shdesc@"__stringify(__LINE__)": ",
 429                        DUMP_PREFIX_ADDRESS, 16, 4, desc,
 430                        desc_bytes(desc), 1);
 431 #endif
 432
 433         return 0;
 434 }
 435
 436 static int gen_split_hash_key(struct caam_hash_ctx *ctx, const u8 *key_in,
 437                               u32 keylen)
 438 {
 439         return gen_split_key(ctx->jrdev, ctx->key, ctx->split_key_len,
 440                                ctx->split_key_pad_len, key_in, keylen,
 441                                ctx->alg_op);
 442 }
 443
 444 /* Digest hash size if it is too large */
 445 static int hash_digest_key(struct caam_hash_ctx *ctx, const u8 *key_in,
 446                            u32 *keylen, u8 *key_out, u32 digestsize)
 447 {
 448         struct device *jrdev = ctx->jrdev;
 449         u32 *desc;
 450         struct split_key_result result;
 451         dma_addr_t src_dma, dst_dma;
 452         int ret = 0;
 453
 454         desc = kmalloc(CAAM_CMD_SZ * 8 + CAAM_PTR_SZ * 2, GFP_KERNEL | GFP_DMA);
 455         if (!desc) {
 456                 dev_err(jrdev, "unable to allocate key input memory\n");
 457                 return -ENOMEM;
 458         }
 459
 460         init_job_desc(desc, 0);
 461
 462         src_dma = dma_map_single(jrdev, (void *)key_in, *keylen,
 463                                  DMA_TO_DEVICE);
 464         if (dma_mapping_error(jrdev, src_dma)) {
 465                 dev_err(jrdev, "unable to map key input memory\n");
 466                 kfree(desc);
 467                 return -ENOMEM;
 468         }
 469         dst_dma = dma_map_single(jrdev, (void *)key_out, digestsize,
 470                                  DMA_FROM_DEVICE);
 471         if (dma_mapping_error(jrdev, dst_dma)) {
 472                 dev_err(jrdev, "unable to map key output memory\n");
 473                 dma_unmap_single(jrdev, src_dma, *keylen, DMA_TO_DEVICE);
 474                 kfree(desc);
 475                 return -ENOMEM;
 476         }
 477
 478         /* Job descriptor to perform unkeyed hash on key_in */
 479         append_operation(desc, ctx->alg_type | OP_ALG_ENCRYPT |
 480                          OP_ALG_AS_INITFINAL);
 481         append_seq_in_ptr(desc, src_dma, *keylen, 0);
 482         append_seq_fifo_load(desc, *keylen, FIFOLD_CLASS_CLASS2 |
 483                              FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_MSG);
 484         append_seq_out_ptr(desc, dst_dma, digestsize, 0);
 485         append_seq_store(desc, digestsize, LDST_CLASS_2_CCB |
 486                          LDST_SRCDST_BYTE_CONTEXT);
 487
 488 #ifdef DEBUG
 489         print_hex_dump(KERN_ERR, "key_in@"__stringify(__LINE__)": ",
 490                        DUMP_PREFIX_ADDRESS, 16, 4, key_in, *keylen, 1);
 491         print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
 492                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
 493 #endif
 494
 495         result.err = 0;
 496         init_completion(&result.completion);
 497
 498         ret = caam_jr_enqueue(jrdev, desc, split_key_done, &result);
 499         if (!ret) {
 500                 /* in progress */
 501                 wait_for_completion_interruptible(&result.completion);
 502                 ret = result.err;
 503 #ifdef DEBUG
 504                 print_hex_dump(KERN_ERR,
 505                                "digested key@"__stringify(__LINE__)": ",
 506                                DUMP_PREFIX_ADDRESS, 16, 4, key_in,
 507                                digestsize, 1);
 508 #endif
 509         }
 510         dma_unmap_single(jrdev, src_dma, *keylen, DMA_TO_DEVICE);
 511         dma_unmap_single(jrdev, dst_dma, digestsize, DMA_FROM_DEVICE);
 512
 513         *keylen = digestsize;
 514
 515         kfree(desc);
 516
 517         return ret;
 518 }
 519
 520 static int ahash_setkey(struct crypto_ahash *ahash,
 521                         const u8 *key, unsigned int keylen)
 522 {
 523         /* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
 524         static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 };
 525         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 526         struct device *jrdev = ctx->jrdev;
 527         int blocksize = crypto_tfm_alg_blocksize(&ahash->base);
 528         int digestsize = crypto_ahash_digestsize(ahash);
 529         int ret = 0;
 530         u8 *hashed_key = NULL;
 531
 532 #ifdef DEBUG
 533         printk(KERN_ERR "keylen %d\n", keylen);
 534 #endif
 535
 536         if (keylen > blocksize) {
 537                 hashed_key = kmalloc(sizeof(u8) * digestsize, GFP_KERNEL |
 538                                      GFP_DMA);
 539                 if (!hashed_key)
 540                         return -ENOMEM;
 541                 ret = hash_digest_key(ctx, key, &keylen, hashed_key,
 542                                       digestsize);
 543                 if (ret)
 544                         goto badkey;
 545                 key = hashed_key;
 546         }
 547
 548         /* Pick class 2 key length from algorithm submask */
 549         ctx->split_key_len = mdpadlen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
 550                                       OP_ALG_ALGSEL_SHIFT] * 2;
 551         ctx->split_key_pad_len = ALIGN(ctx->split_key_len, 16);
 552
 553 #ifdef DEBUG
 554         printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n",
 555                ctx->split_key_len, ctx->split_key_pad_len);
 556         print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
 557                        DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
 558 #endif
 559
 560         ret = gen_split_hash_key(ctx, key, keylen);
 561         if (ret)
 562                 goto badkey;
 563
 564         ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len,
 565                                       DMA_TO_DEVICE);
 566         if (dma_mapping_error(jrdev, ctx->key_dma)) {
 567                 dev_err(jrdev, "unable to map key i/o memory\n");
 568                 ret = -ENOMEM;
 569                 goto map_err;
 570         }
 571 #ifdef DEBUG
 572         print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
 573                        DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
 574                        ctx->split_key_pad_len, 1);
 575 #endif
 576
 577         ret = ahash_set_sh_desc(ahash);
 578         if (ret) {
 579                 dma_unmap_single(jrdev, ctx->key_dma, ctx->split_key_pad_len,
 580                                  DMA_TO_DEVICE);
 581         }
 582
 583 map_err:
 584         kfree(hashed_key);
 585         return ret;
 586 badkey:
 587         kfree(hashed_key);
 588         crypto_ahash_set_flags(ahash, CRYPTO_TFM_RES_BAD_KEY_LEN);
 589         return -EINVAL;
 590 }
 591
 592 /*
 593  * ahash_edesc - s/w-extended ahash descriptor
 594  * @dst_dma: physical mapped address of req->result
 595  * @sec4_sg_dma: physical mapped address of h/w link table
 596  * @src_nents: number of segments in input scatterlist
 597  * @sec4_sg_bytes: length of dma mapped sec4_sg space
 598  * @sec4_sg: pointer to h/w link table
 599  * @hw_desc: the h/w job descriptor followed by any referenced link tables
 600  */
 601 struct ahash_edesc {
 602         dma_addr_t dst_dma;
 603         dma_addr_t sec4_sg_dma;
 604         int src_nents;
 605         int sec4_sg_bytes;
 606         struct sec4_sg_entry *sec4_sg;
 607         u32 hw_desc[0];
 608 };
 609
 610 static inline void ahash_unmap(struct device *dev,
 611                         struct ahash_edesc *edesc,
 612                         struct ahash_request *req, int dst_len)
 613 {
 614         if (edesc->src_nents)
 615                 dma_unmap_sg(dev, req->src, edesc->src_nents, DMA_TO_DEVICE);
 616         if (edesc->dst_dma)
 617                 dma_unmap_single(dev, edesc->dst_dma, dst_len, DMA_FROM_DEVICE);
 618
 619         if (edesc->sec4_sg_bytes)
 620                 dma_unmap_single(dev, edesc->sec4_sg_dma,
 621                                  edesc->sec4_sg_bytes, DMA_TO_DEVICE);
 622 }
 623
 624 static inline void ahash_unmap_ctx(struct device *dev,
 625                         struct ahash_edesc *edesc,
 626                         struct ahash_request *req, int dst_len, u32 flag)
 627 {
 628         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 629         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 630         struct caam_hash_state *state = ahash_request_ctx(req);
 631
 632         if (state->ctx_dma)
 633                 dma_unmap_single(dev, state->ctx_dma, ctx->ctx_len, flag);
 634         ahash_unmap(dev, edesc, req, dst_len);
 635 }
 636
 637 static void ahash_done(struct device *jrdev, u32 *desc, u32 err,
 638                        void *context)
 639 {
 640         struct ahash_request *req = context;
 641         struct ahash_edesc *edesc;
 642         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 643         int digestsize = crypto_ahash_digestsize(ahash);
 644 #ifdef DEBUG
 645         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 646         struct caam_hash_state *state = ahash_request_ctx(req);
 647
 648         dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
 649 #endif
 650
 651         edesc = (struct ahash_edesc *)((char *)desc -
 652                  offsetof(struct ahash_edesc, hw_desc));
 653         if (err)
 654                 caam_jr_strstatus(jrdev, err);
 655
 656         ahash_unmap(jrdev, edesc, req, digestsize);
 657         kfree(edesc);
 658
 659 #ifdef DEBUG
 660         print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
 661                        DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
 662                        ctx->ctx_len, 1);
 663         if (req->result)
 664                 print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
 665                                DUMP_PREFIX_ADDRESS, 16, 4, req->result,
 666                                digestsize, 1);
 667 #endif
 668
 669         req->base.complete(&req->base, err);
 670 }
 671
 672 static void ahash_done_bi(struct device *jrdev, u32 *desc, u32 err,
 673                             void *context)
 674 {
 675         struct ahash_request *req = context;
 676         struct ahash_edesc *edesc;
 677         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 678         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 679 #ifdef DEBUG
 680         struct caam_hash_state *state = ahash_request_ctx(req);
 681         int digestsize = crypto_ahash_digestsize(ahash);
 682
 683         dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
 684 #endif
 685
 686         edesc = (struct ahash_edesc *)((char *)desc -
 687                  offsetof(struct ahash_edesc, hw_desc));
 688         if (err)
 689                 caam_jr_strstatus(jrdev, err);
 690
 691         ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL);
 692         kfree(edesc);
 693
 694 #ifdef DEBUG
 695         print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
 696                        DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
 697                        ctx->ctx_len, 1);
 698         if (req->result)
 699                 print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
 700                                DUMP_PREFIX_ADDRESS, 16, 4, req->result,
 701                                digestsize, 1);
 702 #endif
 703
 704         req->base.complete(&req->base, err);
 705 }
 706
 707 static void ahash_done_ctx_src(struct device *jrdev, u32 *desc, u32 err,
 708                                void *context)
 709 {
 710         struct ahash_request *req = context;
 711         struct ahash_edesc *edesc;
 712         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 713         int digestsize = crypto_ahash_digestsize(ahash);
 714 #ifdef DEBUG
 715         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 716         struct caam_hash_state *state = ahash_request_ctx(req);
 717
 718         dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
 719 #endif
 720
 721         edesc = (struct ahash_edesc *)((char *)desc -
 722                  offsetof(struct ahash_edesc, hw_desc));
 723         if (err)
 724                 caam_jr_strstatus(jrdev, err);
 725
 726         ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_TO_DEVICE);
 727         kfree(edesc);
 728
 729 #ifdef DEBUG
 730         print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
 731                        DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
 732                        ctx->ctx_len, 1);
 733         if (req->result)
 734                 print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
 735                                DUMP_PREFIX_ADDRESS, 16, 4, req->result,
 736                                digestsize, 1);
 737 #endif
 738
 739         req->base.complete(&req->base, err);
 740 }
 741
 742 static void ahash_done_ctx_dst(struct device *jrdev, u32 *desc, u32 err,
 743                                void *context)
 744 {
 745         struct ahash_request *req = context;
 746         struct ahash_edesc *edesc;
 747         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 748         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 749 #ifdef DEBUG
 750         struct caam_hash_state *state = ahash_request_ctx(req);
 751         int digestsize = crypto_ahash_digestsize(ahash);
 752
 753         dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
 754 #endif
 755
 756         edesc = (struct ahash_edesc *)((char *)desc -
 757                  offsetof(struct ahash_edesc, hw_desc));
 758         if (err)
 759                 caam_jr_strstatus(jrdev, err);
 760
 761         ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_FROM_DEVICE);
 762         kfree(edesc);
 763
 764 #ifdef DEBUG
 765         print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ",
 766                        DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
 767                        ctx->ctx_len, 1);
 768         if (req->result)
 769                 print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ",
 770                                DUMP_PREFIX_ADDRESS, 16, 4, req->result,
 771                                digestsize, 1);
 772 #endif
 773
 774         req->base.complete(&req->base, err);
 775 }
 776
 777 /* submit update job descriptor */
 778 static int ahash_update_ctx(struct ahash_request *req)
 779 {
 780         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 781         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 782         struct caam_hash_state *state = ahash_request_ctx(req);
 783         struct device *jrdev = ctx->jrdev;
 784         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
 785                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
 786         u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
 787         int *buflen = state->current_buf ? &state->buflen_1 : &state->buflen_0;
 788         u8 *next_buf = state->current_buf ? state->buf_0 : state->buf_1;
 789         int *next_buflen = state->current_buf ? &state->buflen_0 :
 790                            &state->buflen_1, last_buflen;
 791         int in_len = *buflen + req->nbytes, to_hash;
 792         u32 *sh_desc = ctx->sh_desc_update, *desc;
 793         dma_addr_t ptr = ctx->sh_desc_update_dma;
 794         int src_nents, sec4_sg_bytes, sec4_sg_src_index;
 795         struct ahash_edesc *edesc;
 796         int ret = 0;
 797         int sh_len;
 798
 799         last_buflen = *next_buflen;
 800         *next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1);
 801         to_hash = in_len - *next_buflen;
 802
 803         if (to_hash) {
 804                 src_nents = sg_nents_for_len(req->src,
 805                                              req->nbytes - (*next_buflen));
 806                 if (src_nents < 0) {
 807                         dev_err(jrdev, "Invalid number of src SG.\n");
 808                         return src_nents;
 809                 }
 810                 sec4_sg_src_index = 1 + (*buflen ? 1 : 0);
 811                 sec4_sg_bytes = (sec4_sg_src_index + src_nents) *
 812                                  sizeof(struct sec4_sg_entry);
 813
 814                 /*
 815                  * allocate space for base edesc and hw desc commands,
 816                  * link tables
 817                  */
 818                 edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN +
 819                                 sec4_sg_bytes, GFP_DMA | flags);
 820                 if (!edesc) {
 821                         dev_err(jrdev,
 822                                 "could not allocate extended descriptor\n");
 823                         return -ENOMEM;
 824                 }
 825
 826                 edesc->src_nents = src_nents;
 827                 edesc->sec4_sg_bytes = sec4_sg_bytes;
 828                 edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
 829                                  DESC_JOB_IO_LEN;
 830
 831                 ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
 832                                          edesc->sec4_sg, DMA_BIDIRECTIONAL);
 833                 if (ret)
 834                         return ret;
 835
 836                 state->buf_dma = try_buf_map_to_sec4_sg(jrdev,
 837                                                         edesc->sec4_sg + 1,
 838                                                         buf, state->buf_dma,
 839                                                         *buflen, last_buflen);
 840
 841                 if (src_nents) {
 842                         src_map_to_sec4_sg(jrdev, req->src, src_nents,
 843                                            edesc->sec4_sg + sec4_sg_src_index);
 844                         if (*next_buflen)
 845                                 scatterwalk_map_and_copy(next_buf, req->src,
 846                                                          to_hash - *buflen,
 847                                                          *next_buflen, 0);
 848                 } else {
 849                         (edesc->sec4_sg + sec4_sg_src_index - 1)->len |=
 850                                                         SEC4_SG_LEN_FIN;
 851                 }
 852
 853                 state->current_buf = !state->current_buf;
 854
 855                 sh_len = desc_len(sh_desc);
 856                 desc = edesc->hw_desc;
 857                 init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER |
 858                                      HDR_REVERSE);
 859
 860                 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
 861                                                      sec4_sg_bytes,
 862                                                      DMA_TO_DEVICE);
 863                 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
 864                         dev_err(jrdev, "unable to map S/G table\n");
 865                         return -ENOMEM;
 866                 }
 867
 868                 append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len +
 869                                        to_hash, LDST_SGF);
 870
 871                 append_seq_out_ptr(desc, state->ctx_dma, ctx->ctx_len, 0);
 872
 873 #ifdef DEBUG
 874                 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
 875                                DUMP_PREFIX_ADDRESS, 16, 4, desc,
 876                                desc_bytes(desc), 1);
 877 #endif
 878
 879                 ret = caam_jr_enqueue(jrdev, desc, ahash_done_bi, req);
 880                 if (!ret) {
 881                         ret = -EINPROGRESS;
 882                 } else {
 883                         ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len,
 884                                            DMA_BIDIRECTIONAL);
 885                         kfree(edesc);
 886                 }
 887         } else if (*next_buflen) {
 888                 scatterwalk_map_and_copy(buf + *buflen, req->src, 0,
 889                                          req->nbytes, 0);
 890                 *buflen = *next_buflen;
 891                 *next_buflen = last_buflen;
 892         }
 893 #ifdef DEBUG
 894         print_hex_dump(KERN_ERR, "buf@"__stringify(__LINE__)": ",
 895                        DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1);
 896         print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ",
 897                        DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
 898                        *next_buflen, 1);
 899 #endif
 900
 901         return ret;
 902 }
 903
 904 static int ahash_final_ctx(struct ahash_request *req)
 905 {
 906         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 907         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 908         struct caam_hash_state *state = ahash_request_ctx(req);
 909         struct device *jrdev = ctx->jrdev;
 910         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
 911                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
 912         u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
 913         int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
 914         int last_buflen = state->current_buf ? state->buflen_0 :
 915                           state->buflen_1;
 916         u32 *sh_desc = ctx->sh_desc_fin, *desc;
 917         dma_addr_t ptr = ctx->sh_desc_fin_dma;
 918         int sec4_sg_bytes, sec4_sg_src_index;
 919         int digestsize = crypto_ahash_digestsize(ahash);
 920         struct ahash_edesc *edesc;
 921         int ret = 0;
 922         int sh_len;
 923
 924         sec4_sg_src_index = 1 + (buflen ? 1 : 0);
 925         sec4_sg_bytes = sec4_sg_src_index * sizeof(struct sec4_sg_entry);
 926
 927         /* allocate space for base edesc and hw desc commands, link tables */
 928         edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN + sec4_sg_bytes,
 929                         GFP_DMA | flags);
 930         if (!edesc) {
 931                 dev_err(jrdev, "could not allocate extended descriptor\n");
 932                 return -ENOMEM;
 933         }
 934
 935         sh_len = desc_len(sh_desc);
 936         desc = edesc->hw_desc;
 937         init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | HDR_REVERSE);
 938
 939         edesc->sec4_sg_bytes = sec4_sg_bytes;
 940         edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
 941                          DESC_JOB_IO_LEN;
 942         edesc->src_nents = 0;
 943
 944         ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
 945                                  edesc->sec4_sg, DMA_TO_DEVICE);
 946         if (ret)
 947                 return ret;
 948
 949         state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1,
 950                                                 buf, state->buf_dma, buflen,
 951                                                 last_buflen);
 952         (edesc->sec4_sg + sec4_sg_src_index - 1)->len |= SEC4_SG_LEN_FIN;
 953
 954         edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
 955                                             sec4_sg_bytes, DMA_TO_DEVICE);
 956         if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
 957                 dev_err(jrdev, "unable to map S/G table\n");
 958                 return -ENOMEM;
 959         }
 960
 961         append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len + buflen,
 962                           LDST_SGF);
 963
 964         edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
 965                                                 digestsize);
 966         if (dma_mapping_error(jrdev, edesc->dst_dma)) {
 967                 dev_err(jrdev, "unable to map dst\n");
 968                 return -ENOMEM;
 969         }
 970
 971 #ifdef DEBUG
 972         print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
 973                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
 974 #endif
 975
 976         ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_src, req);
 977         if (!ret) {
 978                 ret = -EINPROGRESS;
 979         } else {
 980                 ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE);
 981                 kfree(edesc);
 982         }
 983
 984         return ret;
 985 }
 986
 987 static int ahash_finup_ctx(struct ahash_request *req)
 988 {
 989         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
 990         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 991         struct caam_hash_state *state = ahash_request_ctx(req);
 992         struct device *jrdev = ctx->jrdev;
 993         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
 994                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
 995         u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
 996         int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
 997         int last_buflen = state->current_buf ? state->buflen_0 :
 998                           state->buflen_1;
 999         u32 *sh_desc = ctx->sh_desc_finup, *desc;
1000         dma_addr_t ptr = ctx->sh_desc_finup_dma;
1001         int sec4_sg_bytes, sec4_sg_src_index;
1002         int src_nents;
1003         int digestsize = crypto_ahash_digestsize(ahash);
1004         struct ahash_edesc *edesc;
1005         int ret = 0;
1006         int sh_len;
1007
1008         src_nents = sg_nents_for_len(req->src, req->nbytes);
1009         if (src_nents < 0) {
1010                 dev_err(jrdev, "Invalid number of src SG.\n");
1011                 return src_nents;
1012         }
1013         sec4_sg_src_index = 1 + (buflen ? 1 : 0);
1014         sec4_sg_bytes = (sec4_sg_src_index + src_nents) *
1015                          sizeof(struct sec4_sg_entry);
1016
1017         /* allocate space for base edesc and hw desc commands, link tables */
1018         edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN + sec4_sg_bytes,
1019                         GFP_DMA | flags);
1020         if (!edesc) {
1021                 dev_err(jrdev, "could not allocate extended descriptor\n");
1022                 return -ENOMEM;
1023         }
1024
1025         sh_len = desc_len(sh_desc);
1026         desc = edesc->hw_desc;
1027         init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | HDR_REVERSE);
1028
1029         edesc->src_nents = src_nents;
1030         edesc->sec4_sg_bytes = sec4_sg_bytes;
1031         edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
1032                          DESC_JOB_IO_LEN;
1033
1034         ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len,
1035                                  edesc->sec4_sg, DMA_TO_DEVICE);
1036         if (ret)
1037                 return ret;
1038
1039         state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1,
1040                                                 buf, state->buf_dma, buflen,
1041                                                 last_buflen);
1042
1043         src_map_to_sec4_sg(jrdev, req->src, src_nents, edesc->sec4_sg +
1044                            sec4_sg_src_index);
1045
1046         edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1047                                             sec4_sg_bytes, DMA_TO_DEVICE);
1048         if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1049                 dev_err(jrdev, "unable to map S/G table\n");
1050                 return -ENOMEM;
1051         }
1052
1053         append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len +
1054                                buflen + req->nbytes, LDST_SGF);
1055
1056         edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
1057                                                 digestsize);
1058         if (dma_mapping_error(jrdev, edesc->dst_dma)) {
1059                 dev_err(jrdev, "unable to map dst\n");
1060                 return -ENOMEM;
1061         }
1062
1063 #ifdef DEBUG
1064         print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
1065                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
1066 #endif
1067
1068         ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_src, req);
1069         if (!ret) {
1070                 ret = -EINPROGRESS;
1071         } else {
1072                 ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE);
1073                 kfree(edesc);
1074         }
1075
1076         return ret;
1077 }
1078
1079 static int ahash_digest(struct ahash_request *req)
1080 {
1081         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1082         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1083         struct device *jrdev = ctx->jrdev;
1084         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1085                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1086         u32 *sh_desc = ctx->sh_desc_digest, *desc;
1087         dma_addr_t ptr = ctx->sh_desc_digest_dma;
1088         int digestsize = crypto_ahash_digestsize(ahash);
1089         int src_nents, sec4_sg_bytes;
1090         dma_addr_t src_dma;
1091         struct ahash_edesc *edesc;
1092         int ret = 0;
1093         u32 options;
1094         int sh_len;
1095
1096         src_nents = sg_count(req->src, req->nbytes);
1097         if (src_nents < 0) {
1098                 dev_err(jrdev, "Invalid number of src SG.\n");
1099                 return src_nents;
1100         }
1101         dma_map_sg(jrdev, req->src, src_nents ? : 1, DMA_TO_DEVICE);
1102         sec4_sg_bytes = src_nents * sizeof(struct sec4_sg_entry);
1103
1104         /* allocate space for base edesc and hw desc commands, link tables */
1105         edesc = kzalloc(sizeof(*edesc) + sec4_sg_bytes + DESC_JOB_IO_LEN,
1106                         GFP_DMA | flags);
1107         if (!edesc) {
1108                 dev_err(jrdev, "could not allocate extended descriptor\n");
1109                 return -ENOMEM;
1110         }
1111         edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
1112                           DESC_JOB_IO_LEN;
1113         edesc->sec4_sg_bytes = sec4_sg_bytes;
1114         edesc->src_nents = src_nents;
1115
1116         sh_len = desc_len(sh_desc);
1117         desc = edesc->hw_desc;
1118         init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | HDR_REVERSE);
1119
1120         if (src_nents) {
1121                 sg_to_sec4_sg_last(req->src, src_nents, edesc->sec4_sg, 0);
1122                 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1123                                             sec4_sg_bytes, DMA_TO_DEVICE);
1124                 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1125                         dev_err(jrdev, "unable to map S/G table\n");
1126                         return -ENOMEM;
1127                 }
1128                 src_dma = edesc->sec4_sg_dma;
1129                 options = LDST_SGF;
1130         } else {
1131                 src_dma = sg_dma_address(req->src);
1132                 options = 0;
1133         }
1134         append_seq_in_ptr(desc, src_dma, req->nbytes, options);
1135
1136         edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
1137                                                 digestsize);
1138         if (dma_mapping_error(jrdev, edesc->dst_dma)) {
1139                 dev_err(jrdev, "unable to map dst\n");
1140                 return -ENOMEM;
1141         }
1142
1143 #ifdef DEBUG
1144         print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
1145                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
1146 #endif
1147
1148         ret = caam_jr_enqueue(jrdev, desc, ahash_done, req);
1149         if (!ret) {
1150                 ret = -EINPROGRESS;
1151         } else {
1152                 ahash_unmap(jrdev, edesc, req, digestsize);
1153                 kfree(edesc);
1154         }
1155
1156         return ret;
1157 }
1158
1159 /* submit ahash final if it the first job descriptor */
1160 static int ahash_final_no_ctx(struct ahash_request *req)
1161 {
1162         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1163         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1164         struct caam_hash_state *state = ahash_request_ctx(req);
1165         struct device *jrdev = ctx->jrdev;
1166         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1167                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1168         u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
1169         int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
1170         u32 *sh_desc = ctx->sh_desc_digest, *desc;
1171         dma_addr_t ptr = ctx->sh_desc_digest_dma;
1172         int digestsize = crypto_ahash_digestsize(ahash);
1173         struct ahash_edesc *edesc;
1174         int ret = 0;
1175         int sh_len;
1176
1177         /* allocate space for base edesc and hw desc commands, link tables */
1178         edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN, GFP_DMA | flags);
1179         if (!edesc) {
1180                 dev_err(jrdev, "could not allocate extended descriptor\n");
1181                 return -ENOMEM;
1182         }
1183
1184         edesc->sec4_sg_bytes = 0;
1185         sh_len = desc_len(sh_desc);
1186         desc = edesc->hw_desc;
1187         init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | HDR_REVERSE);
1188
1189         state->buf_dma = dma_map_single(jrdev, buf, buflen, DMA_TO_DEVICE);
1190         if (dma_mapping_error(jrdev, state->buf_dma)) {
1191                 dev_err(jrdev, "unable to map src\n");
1192                 return -ENOMEM;
1193         }
1194
1195         append_seq_in_ptr(desc, state->buf_dma, buflen, 0);
1196
1197         edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
1198                                                 digestsize);
1199         if (dma_mapping_error(jrdev, edesc->dst_dma)) {
1200                 dev_err(jrdev, "unable to map dst\n");
1201                 return -ENOMEM;
1202         }
1203         edesc->src_nents = 0;
1204
1205 #ifdef DEBUG
1206         print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
1207                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
1208 #endif
1209
1210         ret = caam_jr_enqueue(jrdev, desc, ahash_done, req);
1211         if (!ret) {
1212                 ret = -EINPROGRESS;
1213         } else {
1214                 ahash_unmap(jrdev, edesc, req, digestsize);
1215                 kfree(edesc);
1216         }
1217
1218         return ret;
1219 }
1220
1221 /* submit ahash update if it the first job descriptor after update */
1222 static int ahash_update_no_ctx(struct ahash_request *req)
1223 {
1224         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1225         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1226         struct caam_hash_state *state = ahash_request_ctx(req);
1227         struct device *jrdev = ctx->jrdev;
1228         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1229                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1230         u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
1231         int *buflen = state->current_buf ? &state->buflen_1 : &state->buflen_0;
1232         u8 *next_buf = state->current_buf ? state->buf_0 : state->buf_1;
1233         int *next_buflen = state->current_buf ? &state->buflen_0 :
1234                            &state->buflen_1;
1235         int in_len = *buflen + req->nbytes, to_hash;
1236         int sec4_sg_bytes, src_nents;
1237         struct ahash_edesc *edesc;
1238         u32 *desc, *sh_desc = ctx->sh_desc_update_first;
1239         dma_addr_t ptr = ctx->sh_desc_update_first_dma;
1240         int ret = 0;
1241         int sh_len;
1242
1243         *next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1);
1244         to_hash = in_len - *next_buflen;
1245
1246         if (to_hash) {
1247                 src_nents = sg_nents_for_len(req->src,
1248                                              req->nbytes - (*next_buflen));
1249                 if (src_nents < 0) {
1250                         dev_err(jrdev, "Invalid number of src SG.\n");
1251                         return src_nents;
1252                 }
1253                 sec4_sg_bytes = (1 + src_nents) *
1254                                 sizeof(struct sec4_sg_entry);
1255
1256                 /*
1257                  * allocate space for base edesc and hw desc commands,
1258                  * link tables
1259                  */
1260                 edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN +
1261                                 sec4_sg_bytes, GFP_DMA | flags);
1262                 if (!edesc) {
1263                         dev_err(jrdev,
1264                                 "could not allocate extended descriptor\n");
1265                         return -ENOMEM;
1266                 }
1267
1268                 edesc->src_nents = src_nents;
1269                 edesc->sec4_sg_bytes = sec4_sg_bytes;
1270                 edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
1271                                  DESC_JOB_IO_LEN;
1272                 edesc->dst_dma = 0;
1273
1274                 state->buf_dma = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg,
1275                                                     buf, *buflen);
1276                 src_map_to_sec4_sg(jrdev, req->src, src_nents,
1277                                    edesc->sec4_sg + 1);
1278                 if (*next_buflen) {
1279                         scatterwalk_map_and_copy(next_buf, req->src,
1280                                                  to_hash - *buflen,
1281                                                  *next_buflen, 0);
1282                 }
1283
1284                 state->current_buf = !state->current_buf;
1285
1286                 sh_len = desc_len(sh_desc);
1287                 desc = edesc->hw_desc;
1288                 init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER |
1289                                      HDR_REVERSE);
1290
1291                 edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1292                                                     sec4_sg_bytes,
1293                                                     DMA_TO_DEVICE);
1294                 if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1295                         dev_err(jrdev, "unable to map S/G table\n");
1296                         return -ENOMEM;
1297                 }
1298
1299                 append_seq_in_ptr(desc, edesc->sec4_sg_dma, to_hash, LDST_SGF);
1300
1301                 ret = map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len);
1302                 if (ret)
1303                         return ret;
1304
1305 #ifdef DEBUG
1306                 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
1307                                DUMP_PREFIX_ADDRESS, 16, 4, desc,
1308                                desc_bytes(desc), 1);
1309 #endif
1310
1311                 ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_dst, req);
1312                 if (!ret) {
1313                         ret = -EINPROGRESS;
1314                         state->update = ahash_update_ctx;
1315                         state->finup = ahash_finup_ctx;
1316                         state->final = ahash_final_ctx;
1317                 } else {
1318                         ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len,
1319                                         DMA_TO_DEVICE);
1320                         kfree(edesc);
1321                 }
1322         } else if (*next_buflen) {
1323                 scatterwalk_map_and_copy(buf + *buflen, req->src, 0,
1324                                          req->nbytes, 0);
1325                 *buflen = *next_buflen;
1326                 *next_buflen = 0;
1327         }
1328 #ifdef DEBUG
1329         print_hex_dump(KERN_ERR, "buf@"__stringify(__LINE__)": ",
1330                        DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1);
1331         print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ",
1332                        DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
1333                        *next_buflen, 1);
1334 #endif
1335
1336         return ret;
1337 }
1338
1339 /* submit ahash finup if it the first job descriptor after update */
1340 static int ahash_finup_no_ctx(struct ahash_request *req)
1341 {
1342         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1343         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1344         struct caam_hash_state *state = ahash_request_ctx(req);
1345         struct device *jrdev = ctx->jrdev;
1346         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1347                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1348         u8 *buf = state->current_buf ? state->buf_1 : state->buf_0;
1349         int buflen = state->current_buf ? state->buflen_1 : state->buflen_0;
1350         int last_buflen = state->current_buf ? state->buflen_0 :
1351                           state->buflen_1;
1352         u32 *sh_desc = ctx->sh_desc_digest, *desc;
1353         dma_addr_t ptr = ctx->sh_desc_digest_dma;
1354         int sec4_sg_bytes, sec4_sg_src_index, src_nents;
1355         int digestsize = crypto_ahash_digestsize(ahash);
1356         struct ahash_edesc *edesc;
1357         int sh_len;
1358         int ret = 0;
1359
1360         src_nents = sg_nents_for_len(req->src, req->nbytes);
1361         if (src_nents < 0) {
1362                 dev_err(jrdev, "Invalid number of src SG.\n");
1363                 return src_nents;
1364         }
1365         sec4_sg_src_index = 2;
1366         sec4_sg_bytes = (sec4_sg_src_index + src_nents) *
1367                          sizeof(struct sec4_sg_entry);
1368
1369         /* allocate space for base edesc and hw desc commands, link tables */
1370         edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN + sec4_sg_bytes,
1371                         GFP_DMA | flags);
1372         if (!edesc) {
1373                 dev_err(jrdev, "could not allocate extended descriptor\n");
1374                 return -ENOMEM;
1375         }
1376
1377         sh_len = desc_len(sh_desc);
1378         desc = edesc->hw_desc;
1379         init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | HDR_REVERSE);
1380
1381         edesc->src_nents = src_nents;
1382         edesc->sec4_sg_bytes = sec4_sg_bytes;
1383         edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
1384                          DESC_JOB_IO_LEN;
1385
1386         state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg, buf,
1387                                                 state->buf_dma, buflen,
1388                                                 last_buflen);
1389
1390         src_map_to_sec4_sg(jrdev, req->src, src_nents, edesc->sec4_sg + 1);
1391
1392         edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
1393                                             sec4_sg_bytes, DMA_TO_DEVICE);
1394         if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1395                 dev_err(jrdev, "unable to map S/G table\n");
1396                 return -ENOMEM;
1397         }
1398
1399         append_seq_in_ptr(desc, edesc->sec4_sg_dma, buflen +
1400                                req->nbytes, LDST_SGF);
1401
1402         edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result,
1403                                                 digestsize);
1404         if (dma_mapping_error(jrdev, edesc->dst_dma)) {
1405                 dev_err(jrdev, "unable to map dst\n");
1406                 return -ENOMEM;
1407         }
1408
1409 #ifdef DEBUG
1410         print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
1411                        DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1);
1412 #endif
1413
1414         ret = caam_jr_enqueue(jrdev, desc, ahash_done, req);
1415         if (!ret) {
1416                 ret = -EINPROGRESS;
1417         } else {
1418                 ahash_unmap(jrdev, edesc, req, digestsize);
1419                 kfree(edesc);
1420         }
1421
1422         return ret;
1423 }
1424
1425 /* submit first update job descriptor after init */
1426 static int ahash_update_first(struct ahash_request *req)
1427 {
1428         struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
1429         struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
1430         struct caam_hash_state *state = ahash_request_ctx(req);
1431         struct device *jrdev = ctx->jrdev;
1432         gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
1433                        CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
1434         u8 *next_buf = state->current_buf ? state->buf_1 : state->buf_0;
1435         int *next_buflen = state->current_buf ?
1436                 &state->buflen_1 : &state->buflen_0;
1437         int to_hash;
1438         u32 *sh_desc = ctx->sh_desc_update_first, *desc;
1439         dma_addr_t ptr = ctx->sh_desc_update_first_dma;
1440         int sec4_sg_bytes, src_nents;
1441         dma_addr_t src_dma;
1442         u32 options;
1443         struct ahash_edesc *edesc;
1444         int ret = 0;
1445         int sh_len;
1446
1447         *next_buflen = req->nbytes & (crypto_tfm_alg_blocksize(&ahash->base) -
1448                                       1);
1449         to_hash = req->nbytes - *next_buflen;
1450
1451         if (to_hash) {
1452                 src_nents = sg_count(req->src, req->nbytes - (*next_buflen));
1453                 if (src_nents < 0) {
1454                         dev_err(jrdev, "Invalid number of src SG.\n");
1455                         return src_nents;
1456                 }
1457                 dma_map_sg(jrdev, req->src, src_nents ? : 1, DMA_TO_DEVICE);
1458                 sec4_sg_bytes = src_nents * sizeof(struct sec4_sg_entry);
1459
1460                 /*
1461                  * allocate space for base edesc and hw desc commands,
1462                  * link tables
1463                  */
1464                 edesc = kzalloc(sizeof(*edesc) + DESC_JOB_IO_LEN +
1465                                 sec4_sg_bytes, GFP_DMA | flags);
1466                 if (!edesc) {
1467                         dev_err(jrdev,
1468                                 "could not allocate extended descriptor\n");
1469                         return -ENOMEM;
1470                 }
1471
1472                 edesc->src_nents = src_nents;
1473                 edesc->sec4_sg_bytes = sec4_sg_bytes;
1474                 edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) +
1475                                  DESC_JOB_IO_LEN;
1476                 edesc->dst_dma = 0;
1477
1478                 if (src_nents) {
1479                         sg_to_sec4_sg_last(req->src, src_nents,
1480                                            edesc->sec4_sg, 0);
1481                         edesc->sec4_sg_dma = dma_map_single(jrdev,
1482                                                             edesc->sec4_sg,
1483                                                             sec4_sg_bytes,
1484                                                             DMA_TO_DEVICE);
1485                         if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) {
1486                                 dev_err(jrdev, "unable to map S/G table\n");
1487                                 return -ENOMEM;
1488                         }
1489                         src_dma = edesc->sec4_sg_dma;
1490                         options = LDST_SGF;
1491                 } else {
1492                         src_dma = sg_dma_address(req->src);
1493                         options = 0;
1494                 }
1495
1496                 if (*next_buflen)
1497                         scatterwalk_map_and_copy(next_buf, req->src, to_hash,
1498                                                  *next_buflen, 0);
1499
1500                 sh_len = desc_len(sh_desc);
1501                 desc = edesc->hw_desc;
1502                 init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER |
1503                                      HDR_REVERSE);
1504
1505                 append_seq_in_ptr(desc, src_dma, to_hash, options);
1506
1507                 ret = map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len);
1508                 if (ret)
1509                         return ret;
1510
1511 #ifdef DEBUG
1512                 print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ",
1513                                DUMP_PREFIX_ADDRESS, 16, 4, desc,
1514                                desc_bytes(desc), 1);
1515 #endif
1516
1517                 ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_dst,
1518                                       req);
1519                 if (!ret) {
1520                         ret = -EINPROGRESS;
1521                         state->update = ahash_update_ctx;
1522                         state->finup = ahash_finup_ctx;
1523                         state->final = ahash_final_ctx;
1524                 } else {
1525                         ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len,
1526                                         DMA_TO_DEVICE);
1527                         kfree(edesc);
1528                 }
1529         } else if (*next_buflen) {
1530                 state->update = ahash_update_no_ctx;
1531                 state->finup = ahash_finup_no_ctx;
1532                 state->final = ahash_final_no_ctx;
1533                 scatterwalk_map_and_copy(next_buf, req->src, 0,
1534                                          req->nbytes, 0);
1535         }
1536 #ifdef DEBUG
1537         print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ",
1538                        DUMP_PREFIX_ADDRESS, 16, 4, next_buf,
1539                        *next_buflen, 1);
1540 #endif
1541
1542         return ret;
1543 }
1544
1545 static int ahash_finup_first(struct ahash_request *req)
1546 {
1547         return ahash_digest(req);
1548 }
1549
1550 static int ahash_init(struct ahash_request *req)
1551 {
1552         struct caam_hash_state *state = ahash_request_ctx(req);
1553
1554         state->update = ahash_update_first;
1555         state->finup = ahash_finup_first;
1556         state->final = ahash_final_no_ctx;
1557
1558         state->current_buf = 0;
1559         state->buf_dma = 0;
1560         state->buflen_0 = 0;
1561         state->buflen_1 = 0;
1562
1563         return 0;
1564 }
1565
1566 static int ahash_update(struct ahash_request *req)
1567 {
1568         struct caam_hash_state *state = ahash_request_ctx(req);
1569
1570         return state->update(req);
1571 }
1572
1573 static int ahash_finup(struct ahash_request *req)
1574 {
1575         struct caam_hash_state *state = ahash_request_ctx(req);
1576
1577         return state->finup(req);
1578 }
1579
1580 static int ahash_final(struct ahash_request *req)
1581 {
1582         struct caam_hash_state *state = ahash_request_ctx(req);
1583
1584         return state->final(req);
1585 }
1586
1587 static int ahash_export(struct ahash_request *req, void *out)
1588 {
1589         struct caam_hash_state *state = ahash_request_ctx(req);
1590         struct caam_export_state *export = out;
1591         int len;
1592         u8 *buf;
1593
1594         if (state->current_buf) {
1595                 buf = state->buf_1;
1596                 len = state->buflen_1;
1597         } else {
1598                 buf = state->buf_0;
1599                 len = state->buflen_0;
1600         }
1601
1602         memcpy(export->buf, buf, len);
1603         memcpy(export->caam_ctx, state->caam_ctx, sizeof(export->caam_ctx));
1604         export->buflen = len;
1605         export->update = state->update;
1606         export->final = state->final;
1607         export->finup = state->finup;
1608
1609         return 0;
1610 }
1611
1612 static int ahash_import(struct ahash_request *req, const void *in)
1613 {
1614         struct caam_hash_state *state = ahash_request_ctx(req);
1615         const struct caam_export_state *export = in;
1616
1617         memset(state, 0, sizeof(*state));
1618         memcpy(state->buf_0, export->buf, export->buflen);
1619         memcpy(state->caam_ctx, export->caam_ctx, sizeof(state->caam_ctx));
1620         state->buflen_0 = export->buflen;
1621         state->update = export->update;
1622         state->final = export->final;
1623         state->finup = export->finup;
1624
1625         return 0;
1626 }
1627
1628 struct caam_hash_template {
1629         char name[CRYPTO_MAX_ALG_NAME];
1630         char driver_name[CRYPTO_MAX_ALG_NAME];
1631         char hmac_name[CRYPTO_MAX_ALG_NAME];
1632         char hmac_driver_name[CRYPTO_MAX_ALG_NAME];
1633         unsigned int blocksize;
1634         struct ahash_alg template_ahash;
1635         u32 alg_type;
1636         u32 alg_op;
1637 };
1638
1639 /* ahash descriptors */
1640 static struct caam_hash_template driver_hash[] = {
1641         {
1642                 .name = "sha1",
1643                 .driver_name = "sha1-caam",
1644                 .hmac_name = "hmac(sha1)",
1645                 .hmac_driver_name = "hmac-sha1-caam",
1646                 .blocksize = SHA1_BLOCK_SIZE,
1647                 .template_ahash = {
1648                         .init = ahash_init,
1649                         .update = ahash_update,
1650                         .final = ahash_final,
1651                         .finup = ahash_finup,
1652                         .digest = ahash_digest,
1653                         .export = ahash_export,
1654                         .import = ahash_import,
1655                         .setkey = ahash_setkey,
1656                         .halg = {
1657                                 .digestsize = SHA1_DIGEST_SIZE,
1658                                 .statesize = sizeof(struct caam_export_state),
1659                         },
1660                 },
1661                 .alg_type = OP_ALG_ALGSEL_SHA1,
1662                 .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
1663         }, {
1664                 .name = "sha224",
1665                 .driver_name = "sha224-caam",
1666                 .hmac_name = "hmac(sha224)",
1667                 .hmac_driver_name = "hmac-sha224-caam",
1668                 .blocksize = SHA224_BLOCK_SIZE,
1669                 .template_ahash = {
1670                         .init = ahash_init,
1671                         .update = ahash_update,
1672                         .final = ahash_final,
1673                         .finup = ahash_finup,
1674                         .digest = ahash_digest,
1675                         .export = ahash_export,
1676                         .import = ahash_import,
1677                         .setkey = ahash_setkey,
1678                         .halg = {
1679                                 .digestsize = SHA224_DIGEST_SIZE,
1680                                 .statesize = sizeof(struct caam_export_state),
1681                         },
1682                 },
1683                 .alg_type = OP_ALG_ALGSEL_SHA224,
1684                 .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
1685         }, {
1686                 .name = "sha256",
1687                 .driver_name = "sha256-caam",
1688                 .hmac_name = "hmac(sha256)",
1689                 .hmac_driver_name = "hmac-sha256-caam",
1690                 .blocksize = SHA256_BLOCK_SIZE,
1691                 .template_ahash = {
1692                         .init = ahash_init,
1693                         .update = ahash_update,
1694                         .final = ahash_final,
1695                         .finup = ahash_finup,
1696                         .digest = ahash_digest,
1697                         .export = ahash_export,
1698                         .import = ahash_import,
1699                         .setkey = ahash_setkey,
1700                         .halg = {
1701                                 .digestsize = SHA256_DIGEST_SIZE,
1702                                 .statesize = sizeof(struct caam_export_state),
1703                         },
1704                 },
1705                 .alg_type = OP_ALG_ALGSEL_SHA256,
1706                 .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
1707         }, {
1708                 .name = "sha384",
1709                 .driver_name = "sha384-caam",
1710                 .hmac_name = "hmac(sha384)",
1711                 .hmac_driver_name = "hmac-sha384-caam",
1712                 .blocksize = SHA384_BLOCK_SIZE,
1713                 .template_ahash = {
1714                         .init = ahash_init,
1715                         .update = ahash_update,
1716                         .final = ahash_final,
1717                         .finup = ahash_finup,
1718                         .digest = ahash_digest,
1719                         .export = ahash_export,
1720                         .import = ahash_import,
1721                         .setkey = ahash_setkey,
1722                         .halg = {
1723                                 .digestsize = SHA384_DIGEST_SIZE,
1724                                 .statesize = sizeof(struct caam_export_state),
1725                         },
1726                 },
1727                 .alg_type = OP_ALG_ALGSEL_SHA384,
1728                 .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
1729         }, {
1730                 .name = "sha512",
1731                 .driver_name = "sha512-caam",
1732                 .hmac_name = "hmac(sha512)",
1733                 .hmac_driver_name = "hmac-sha512-caam",
1734                 .blocksize = SHA512_BLOCK_SIZE,
1735                 .template_ahash = {
1736                         .init = ahash_init,
1737                         .update = ahash_update,
1738                         .final = ahash_final,
1739                         .finup = ahash_finup,
1740                         .digest = ahash_digest,
1741                         .export = ahash_export,
1742                         .import = ahash_import,
1743                         .setkey = ahash_setkey,
1744                         .halg = {
1745                                 .digestsize = SHA512_DIGEST_SIZE,
1746                                 .statesize = sizeof(struct caam_export_state),
1747                         },
1748                 },
1749                 .alg_type = OP_ALG_ALGSEL_SHA512,
1750                 .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
1751         }, {
1752                 .name = "md5",
1753                 .driver_name = "md5-caam",
1754                 .hmac_name = "hmac(md5)",
1755                 .hmac_driver_name = "hmac-md5-caam",
1756                 .blocksize = MD5_BLOCK_WORDS * 4,
1757                 .template_ahash = {
1758                         .init = ahash_init,
1759                         .update = ahash_update,
1760                         .final = ahash_final,
1761                         .finup = ahash_finup,
1762                         .digest = ahash_digest,
1763                         .export = ahash_export,
1764                         .import = ahash_import,
1765                         .setkey = ahash_setkey,
1766                         .halg = {
1767                                 .digestsize = MD5_DIGEST_SIZE,
1768                                 .statesize = sizeof(struct caam_export_state),
1769                         },
1770                 },
1771                 .alg_type = OP_ALG_ALGSEL_MD5,
1772                 .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
1773         },
1774 };
1775
1776 struct caam_hash_alg {
1777         struct list_head entry;
1778         int alg_type;
1779         int alg_op;
1780         struct ahash_alg ahash_alg;
1781 };
1782
1783 static int caam_hash_cra_init(struct crypto_tfm *tfm)
1784 {
1785         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
1786         struct crypto_alg *base = tfm->__crt_alg;
1787         struct hash_alg_common *halg =
1788                  container_of(base, struct hash_alg_common, base);
1789         struct ahash_alg *alg =
1790                  container_of(halg, struct ahash_alg, halg);
1791         struct caam_hash_alg *caam_hash =
1792                  container_of(alg, struct caam_hash_alg, ahash_alg);
1793         struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
1794         /* Sizes for MDHA running digests: MD5, SHA1, 224, 256, 384, 512 */
1795         static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE,
1796                                          HASH_MSG_LEN + SHA1_DIGEST_SIZE,
1797                                          HASH_MSG_LEN + 32,
1798                                          HASH_MSG_LEN + SHA256_DIGEST_SIZE,
1799                                          HASH_MSG_LEN + 64,
1800                                          HASH_MSG_LEN + SHA512_DIGEST_SIZE };
1801         int ret = 0;
1802
1803         /*
1804          * Get a Job ring from Job Ring driver to ensure in-order
1805          * crypto request processing per tfm
1806          */
1807         ctx->jrdev = caam_jr_alloc();
1808         if (IS_ERR(ctx->jrdev)) {
1809                 pr_err("Job Ring Device allocation for transform failed\n");
1810                 return PTR_ERR(ctx->jrdev);
1811         }
1812         /* copy descriptor header template value */
1813         ctx->alg_type = OP_TYPE_CLASS2_ALG | caam_hash->alg_type;
1814         ctx->alg_op = OP_TYPE_CLASS2_ALG | caam_hash->alg_op;
1815
1816         ctx->ctx_len = runninglen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
1817                                   OP_ALG_ALGSEL_SHIFT];
1818
1819         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
1820                                  sizeof(struct caam_hash_state));
1821
1822         ret = ahash_set_sh_desc(ahash);
1823
1824         return ret;
1825 }
1826
1827 static void caam_hash_cra_exit(struct crypto_tfm *tfm)
1828 {
1829         struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
1830
1831         if (ctx->sh_desc_update_dma &&
1832             !dma_mapping_error(ctx->jrdev, ctx->sh_desc_update_dma))
1833                 dma_unmap_single(ctx->jrdev, ctx->sh_desc_update_dma,
1834                                  desc_bytes(ctx->sh_desc_update),
1835                                  DMA_TO_DEVICE);
1836         if (ctx->sh_desc_update_first_dma &&
1837             !dma_mapping_error(ctx->jrdev, ctx->sh_desc_update_first_dma))
1838                 dma_unmap_single(ctx->jrdev, ctx->sh_desc_update_first_dma,
1839                                  desc_bytes(ctx->sh_desc_update_first),
1840                                  DMA_TO_DEVICE);
1841         if (ctx->sh_desc_fin_dma &&
1842             !dma_mapping_error(ctx->jrdev, ctx->sh_desc_fin_dma))
1843                 dma_unmap_single(ctx->jrdev, ctx->sh_desc_fin_dma,
1844                                  desc_bytes(ctx->sh_desc_fin), DMA_TO_DEVICE);
1845         if (ctx->sh_desc_digest_dma &&
1846             !dma_mapping_error(ctx->jrdev, ctx->sh_desc_digest_dma))
1847                 dma_unmap_single(ctx->jrdev, ctx->sh_desc_digest_dma,
1848                                  desc_bytes(ctx->sh_desc_digest),
1849                                  DMA_TO_DEVICE);
1850         if (ctx->sh_desc_finup_dma &&
1851             !dma_mapping_error(ctx->jrdev, ctx->sh_desc_finup_dma))
1852                 dma_unmap_single(ctx->jrdev, ctx->sh_desc_finup_dma,
1853                                  desc_bytes(ctx->sh_desc_finup), DMA_TO_DEVICE);
1854
1855         caam_jr_free(ctx->jrdev);
1856 }
1857
1858 static void __exit caam_algapi_hash_exit(void)
1859 {
1860         struct caam_hash_alg *t_alg, *n;
1861
1862         if (!hash_list.next)
1863                 return;
1864
1865         list_for_each_entry_safe(t_alg, n, &hash_list, entry) {
1866                 crypto_unregister_ahash(&t_alg->ahash_alg);
1867                 list_del(&t_alg->entry);
1868                 kfree(t_alg);
1869         }
1870 }
1871
1872 static struct caam_hash_alg *
1873 caam_hash_alloc(struct caam_hash_template *template,
1874                 bool keyed)
1875 {
1876         struct caam_hash_alg *t_alg;
1877         struct ahash_alg *halg;
1878         struct crypto_alg *alg;
1879
1880         t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL);
1881         if (!t_alg) {
1882                 pr_err("failed to allocate t_alg\n");
1883                 return ERR_PTR(-ENOMEM);
1884         }
1885
1886         t_alg->ahash_alg = template->template_ahash;
1887         halg = &t_alg->ahash_alg;
1888         alg = &halg->halg.base;
1889
1890         if (keyed) {
1891                 snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s",
1892                          template->hmac_name);
1893                 snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
1894                          template->hmac_driver_name);
1895         } else {
1896                 snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s",
1897                          template->name);
1898                 snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
1899                          template->driver_name);
1900         }
1901         alg->cra_module = THIS_MODULE;
1902         alg->cra_init = caam_hash_cra_init;
1903         alg->cra_exit = caam_hash_cra_exit;
1904         alg->cra_ctxsize = sizeof(struct caam_hash_ctx);
1905         alg->cra_priority = CAAM_CRA_PRIORITY;
1906         alg->cra_blocksize = template->blocksize;
1907         alg->cra_alignmask = 0;
1908         alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_TYPE_AHASH;
1909         alg->cra_type = &crypto_ahash_type;
1910
1911         t_alg->alg_type = template->alg_type;
1912         t_alg->alg_op = template->alg_op;
1913
1914         return t_alg;
1915 }
1916
1917 static int __init caam_algapi_hash_init(void)
1918 {
1919         struct device_node *dev_node;
1920         struct platform_device *pdev;
1921         struct device *ctrldev;
1922         int i = 0, err = 0;
1923         struct caam_drv_private *priv;
1924         unsigned int md_limit = SHA512_DIGEST_SIZE;
1925         u32 cha_inst, cha_vid;
1926
1927         dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
1928         if (!dev_node) {
1929                 dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0");
1930                 if (!dev_node)
1931                         return -ENODEV;
1932         }
1933
1934         pdev = of_find_device_by_node(dev_node);
1935         if (!pdev) {
1936                 of_node_put(dev_node);
1937                 return -ENODEV;
1938         }
1939
1940         ctrldev = &pdev->dev;
1941         priv = dev_get_drvdata(ctrldev);
1942         of_node_put(dev_node);
1943
1944         /*
1945          * If priv is NULL, it's probably because the caam driver wasn't
1946          * properly initialized (e.g. RNG4 init failed). Thus, bail out here.
1947          */
1948         if (!priv)
1949                 return -ENODEV;
1950
1951         /*
1952          * Register crypto algorithms the device supports.  First, identify
1953          * presence and attributes of MD block.
1954          */
1955         cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
1956         cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
1957
1958         /*
1959          * Skip registration of any hashing algorithms if MD block
1960          * is not present.
1961          */
1962         if (!((cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT))
1963                 return -ENODEV;
1964
1965         /* Limit digest size based on LP256 */
1966         if ((cha_vid & CHA_ID_LS_MD_MASK) == CHA_ID_LS_MD_LP256)
1967                 md_limit = SHA256_DIGEST_SIZE;
1968
1969         INIT_LIST_HEAD(&hash_list);
1970
1971         /* register crypto algorithms the device supports */
1972         for (i = 0; i < ARRAY_SIZE(driver_hash); i++) {
1973                 struct caam_hash_alg *t_alg;
1974                 struct caam_hash_template *alg = driver_hash + i;
1975
1976                 /* If MD size is not supported by device, skip registration */
1977                 if (alg->template_ahash.halg.digestsize > md_limit)
1978                         continue;
1979
1980                 /* register hmac version */
1981                 t_alg = caam_hash_alloc(alg, true);
1982                 if (IS_ERR(t_alg)) {
1983                         err = PTR_ERR(t_alg);
1984                         pr_warn("%s alg allocation failed\n", alg->driver_name);
1985                         continue;
1986                 }
1987
1988                 err = crypto_register_ahash(&t_alg->ahash_alg);
1989                 if (err) {
1990                         pr_warn("%s alg registration failed: %d\n",
1991                                 t_alg->ahash_alg.halg.base.cra_driver_name,
1992                                 err);
1993                         kfree(t_alg);
1994                 } else
1995                         list_add_tail(&t_alg->entry, &hash_list);
1996
1997                 /* register unkeyed version */
1998                 t_alg = caam_hash_alloc(alg, false);
1999                 if (IS_ERR(t_alg)) {
2000                         err = PTR_ERR(t_alg);
2001                         pr_warn("%s alg allocation failed\n", alg->driver_name);
2002                         continue;
2003                 }
2004
2005                 err = crypto_register_ahash(&t_alg->ahash_alg);
2006                 if (err) {
2007                         pr_warn("%s alg registration failed: %d\n",
2008                                 t_alg->ahash_alg.halg.base.cra_driver_name,
2009                                 err);
2010                         kfree(t_alg);
2011                 } else
2012                         list_add_tail(&t_alg->entry, &hash_list);
2013         }
2014
2015         return err;
2016 }
2017
2018 module_init(caam_algapi_hash_init);
2019 module_exit(caam_algapi_hash_exit);
2020
2021 MODULE_LICENSE("GPL");
2022 MODULE_DESCRIPTION("FSL CAAM support for ahash functions of crypto API");
2023 MODULE_AUTHOR("Freescale Semiconductor - NMG");