drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39
  40
  41 int amdgpu_ttm_init(struct amdgpu_device *adev);
  42 void amdgpu_ttm_fini(struct amdgpu_device *adev);
  43
  44 static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev,
  45                                                 struct ttm_mem_reg *mem)
  46 {
  47         u64 ret = 0;
  48         if (mem->start << PAGE_SHIFT < adev->mc.visible_vram_size) {
  49                 ret = (u64)((mem->start << PAGE_SHIFT) + mem->size) >
  50                            adev->mc.visible_vram_size ?
  51                            adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) :
  52                            mem->size;
  53         }
  54         return ret;
  55 }
  56
  57 static void amdgpu_update_memory_usage(struct amdgpu_device *adev,
  58                        struct ttm_mem_reg *old_mem,
  59                        struct ttm_mem_reg *new_mem)
  60 {
  61         u64 vis_size;
  62         if (!adev)
  63                 return;
  64
  65         if (new_mem) {
  66                 switch (new_mem->mem_type) {
  67                 case TTM_PL_TT:
  68                         atomic64_add(new_mem->size, &adev->gtt_usage);
  69                         break;
  70                 case TTM_PL_VRAM:
  71                         atomic64_add(new_mem->size, &adev->vram_usage);
  72                         vis_size = amdgpu_get_vis_part_size(adev, new_mem);
  73                         atomic64_add(vis_size, &adev->vram_vis_usage);
  74                         break;
  75                 }
  76         }
  77
  78         if (old_mem) {
  79                 switch (old_mem->mem_type) {
  80                 case TTM_PL_TT:
  81                         atomic64_sub(old_mem->size, &adev->gtt_usage);
  82                         break;
  83                 case TTM_PL_VRAM:
  84                         atomic64_sub(old_mem->size, &adev->vram_usage);
  85                         vis_size = amdgpu_get_vis_part_size(adev, old_mem);
  86                         atomic64_sub(vis_size, &adev->vram_vis_usage);
  87                         break;
  88                 }
  89         }
  90 }
  91
  92 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  93 {
  94         struct amdgpu_bo *bo;
  95
  96         bo = container_of(tbo, struct amdgpu_bo, tbo);
  97
  98         amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL);
  99
 100         drm_gem_object_release(&bo->gem_base);
 101         amdgpu_bo_unref(&bo->parent);
 102         kfree(bo->metadata);
 103         kfree(bo);
 104 }
 105
 106 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
 107 {
 108         if (bo->destroy == &amdgpu_ttm_bo_destroy)
 109                 return true;
 110         return false;
 111 }
 112
 113 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
 114                                       struct ttm_placement *placement,
 115                                       struct ttm_place *placements,
 116                                       u32 domain, u64 flags)
 117 {
 118         u32 c = 0, i;
 119
 120         placement->placement = placements;
 121         placement->busy_placement = placements;
 122
 123         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 124                 if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&
 125                         adev->mc.visible_vram_size < adev->mc.real_vram_size) {
 126                         placements[c].fpfn =
 127                                 adev->mc.visible_vram_size >> PAGE_SHIFT;
 128                         placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
 129                                 TTM_PL_FLAG_VRAM | TTM_PL_FLAG_TOPDOWN;
 130                 }
 131                 placements[c].fpfn = 0;
 132                 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
 133                         TTM_PL_FLAG_VRAM;
 134                 if (!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED))
 135                         placements[c - 1].flags |= TTM_PL_FLAG_TOPDOWN;
 136         }
 137
 138         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 139                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
 140                         placements[c].fpfn = 0;
 141                         placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT |
 142                                 TTM_PL_FLAG_UNCACHED;
 143                 } else {
 144                         placements[c].fpfn = 0;
 145                         placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
 146                 }
 147         }
 148
 149         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 150                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
 151                         placements[c].fpfn = 0;
 152                         placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM |
 153                                 TTM_PL_FLAG_UNCACHED;
 154                 } else {
 155                         placements[c].fpfn = 0;
 156                         placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
 157                 }
 158         }
 159
 160         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 161                 placements[c].fpfn = 0;
 162                 placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 163                         AMDGPU_PL_FLAG_GDS;
 164         }
 165         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 166                 placements[c].fpfn = 0;
 167                 placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 168                         AMDGPU_PL_FLAG_GWS;
 169         }
 170         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 171                 placements[c].fpfn = 0;
 172                 placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 173                         AMDGPU_PL_FLAG_OA;
 174         }
 175
 176         if (!c) {
 177                 placements[c].fpfn = 0;
 178                 placements[c++].flags = TTM_PL_MASK_CACHING |
 179                         TTM_PL_FLAG_SYSTEM;
 180         }
 181         placement->num_placement = c;
 182         placement->num_busy_placement = c;
 183
 184         for (i = 0; i < c; i++) {
 185                 if ((flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 186                         (placements[i].flags & TTM_PL_FLAG_VRAM) &&
 187                         !placements[i].fpfn)
 188                         placements[i].lpfn =
 189                                 adev->mc.visible_vram_size >> PAGE_SHIFT;
 190                 else
 191                         placements[i].lpfn = 0;
 192         }
 193 }
 194
 195 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain)
 196 {
 197         amdgpu_ttm_placement_init(rbo->adev, &rbo->placement,
 198                                   rbo->placements, domain, rbo->flags);
 199 }
 200
 201 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo,
 202                                         struct ttm_placement *placement)
 203 {
 204         BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1));
 205
 206         memcpy(bo->placements, placement->placement,
 207                placement->num_placement * sizeof(struct ttm_place));
 208         bo->placement.num_placement = placement->num_placement;
 209         bo->placement.num_busy_placement = placement->num_busy_placement;
 210         bo->placement.placement = bo->placements;
 211         bo->placement.busy_placement = bo->placements;
 212 }
 213
 214 /**
 215  * amdgpu_bo_create_kernel - create BO for kernel use
 216  *
 217  * @adev: amdgpu device object
 218  * @size: size for the new BO
 219  * @align: alignment for the new BO
 220  * @domain: where to place it
 221  * @bo_ptr: resulting BO
 222  * @gpu_addr: GPU addr of the pinned BO
 223  * @cpu_addr: optional CPU address mapping
 224  *
 225  * Allocates and pins a BO for kernel internal use.
 226  *
 227  * Returns 0 on success, negative error code otherwise.
 228  */
 229 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 230                             unsigned long size, int align,
 231                             u32 domain, struct amdgpu_bo **bo_ptr,
 232                             u64 *gpu_addr, void **cpu_addr)
 233 {
 234         int r;
 235
 236         r = amdgpu_bo_create(adev, size, align, true, domain,
 237                              AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
 238                              NULL, NULL, bo_ptr);
 239         if (r) {
 240                 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", r);
 241                 return r;
 242         }
 243
 244         r = amdgpu_bo_reserve(*bo_ptr, false);
 245         if (r) {
 246                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 247                 goto error_free;
 248         }
 249
 250         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 251         if (r) {
 252                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 253                 goto error_unreserve;
 254         }
 255
 256         if (cpu_addr) {
 257                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 258                 if (r) {
 259                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 260                         goto error_unreserve;
 261                 }
 262         }
 263
 264         amdgpu_bo_unreserve(*bo_ptr);
 265
 266         return 0;
 267
 268 error_unreserve:
 269         amdgpu_bo_unreserve(*bo_ptr);
 270
 271 error_free:
 272         amdgpu_bo_unref(bo_ptr);
 273
 274         return r;
 275 }
 276
 277 int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
 278                                 unsigned long size, int byte_align,
 279                                 bool kernel, u32 domain, u64 flags,
 280                                 struct sg_table *sg,
 281                                 struct ttm_placement *placement,
 282                                 struct reservation_object *resv,
 283                                 struct amdgpu_bo **bo_ptr)
 284 {
 285         struct amdgpu_bo *bo;
 286         enum ttm_bo_type type;
 287         unsigned long page_align;
 288         size_t acc_size;
 289         int r;
 290
 291         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 292         size = ALIGN(size, PAGE_SIZE);
 293
 294         if (kernel) {
 295                 type = ttm_bo_type_kernel;
 296         } else if (sg) {
 297                 type = ttm_bo_type_sg;
 298         } else {
 299                 type = ttm_bo_type_device;
 300         }
 301         *bo_ptr = NULL;
 302
 303         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 304                                        sizeof(struct amdgpu_bo));
 305
 306         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 307         if (bo == NULL)
 308                 return -ENOMEM;
 309         r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
 310         if (unlikely(r)) {
 311                 kfree(bo);
 312                 return r;
 313         }
 314         bo->adev = adev;
 315         INIT_LIST_HEAD(&bo->list);
 316         INIT_LIST_HEAD(&bo->va);
 317         bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 318                                          AMDGPU_GEM_DOMAIN_GTT |
 319                                          AMDGPU_GEM_DOMAIN_CPU |
 320                                          AMDGPU_GEM_DOMAIN_GDS |
 321                                          AMDGPU_GEM_DOMAIN_GWS |
 322                                          AMDGPU_GEM_DOMAIN_OA);
 323         bo->allowed_domains = bo->prefered_domains;
 324         if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 325                 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 326
 327         bo->flags = flags;
 328
 329         /* For architectures that don't support WC memory,
 330          * mask out the WC flag from the BO
 331          */
 332         if (!drm_arch_can_wc_memory())
 333                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 334
 335         amdgpu_fill_placement_to_bo(bo, placement);
 336         /* Kernel allocation are uninterruptible */
 337         r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type,
 338                         &bo->placement, page_align, !kernel, NULL,
 339                         acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
 340         if (unlikely(r != 0)) {
 341                 return r;
 342         }
 343
 344         if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 345             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 346                 struct fence *fence;
 347
 348                 if (adev->mman.buffer_funcs_ring == NULL ||
 349                    !adev->mman.buffer_funcs_ring->ready) {
 350                         r = -EBUSY;
 351                         goto fail_free;
 352                 }
 353
 354                 r = amdgpu_bo_reserve(bo, false);
 355                 if (unlikely(r != 0))
 356                         goto fail_free;
 357
 358                 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
 359                 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 360                 if (unlikely(r != 0))
 361                         goto fail_unreserve;
 362
 363                 amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
 364                 amdgpu_bo_fence(bo, fence, false);
 365                 amdgpu_bo_unreserve(bo);
 366                 fence_put(bo->tbo.moving);
 367                 bo->tbo.moving = fence_get(fence);
 368                 fence_put(fence);
 369         }
 370         *bo_ptr = bo;
 371
 372         trace_amdgpu_bo_create(bo);
 373
 374         return 0;
 375
 376 fail_unreserve:
 377         amdgpu_bo_unreserve(bo);
 378 fail_free:
 379         amdgpu_bo_unref(&bo);
 380         return r;
 381 }
 382
 383 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 384                                    unsigned long size, int byte_align,
 385                                    struct amdgpu_bo *bo)
 386 {
 387         struct ttm_placement placement = {0};
 388         struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
 389         int r;
 390
 391         if (bo->shadow)
 392                 return 0;
 393
 394         bo->flags |= AMDGPU_GEM_CREATE_SHADOW;
 395         memset(&placements, 0,
 396                (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
 397
 398         amdgpu_ttm_placement_init(adev, &placement,
 399                                   placements, AMDGPU_GEM_DOMAIN_GTT,
 400                                   AMDGPU_GEM_CREATE_CPU_GTT_USWC);
 401
 402         r = amdgpu_bo_create_restricted(adev, size, byte_align, true,
 403                                         AMDGPU_GEM_DOMAIN_GTT,
 404                                         AMDGPU_GEM_CREATE_CPU_GTT_USWC,
 405                                         NULL, &placement,
 406                                         bo->tbo.resv,
 407                                         &bo->shadow);
 408         if (!r)
 409                 bo->shadow->parent = amdgpu_bo_ref(bo);
 410
 411         return r;
 412 }
 413
 414 int amdgpu_bo_create(struct amdgpu_device *adev,
 415                      unsigned long size, int byte_align,
 416                      bool kernel, u32 domain, u64 flags,
 417                      struct sg_table *sg,
 418                      struct reservation_object *resv,
 419                      struct amdgpu_bo **bo_ptr)
 420 {
 421         struct ttm_placement placement = {0};
 422         struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
 423         int r;
 424
 425         memset(&placements, 0,
 426                (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place));
 427
 428         amdgpu_ttm_placement_init(adev, &placement,
 429                                   placements, domain, flags);
 430
 431         r = amdgpu_bo_create_restricted(adev, size, byte_align, kernel,
 432                                         domain, flags, sg, &placement,
 433                                         resv, bo_ptr);
 434         if (r)
 435                 return r;
 436
 437         if (flags & AMDGPU_GEM_CREATE_SHADOW) {
 438                 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 439                 if (r)
 440                         amdgpu_bo_unref(bo_ptr);
 441         }
 442
 443         return r;
 444 }
 445
 446 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 447 {
 448         bool is_iomem;
 449         long r;
 450
 451         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 452                 return -EPERM;
 453
 454         if (bo->kptr) {
 455                 if (ptr) {
 456                         *ptr = bo->kptr;
 457                 }
 458                 return 0;
 459         }
 460
 461         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 462                                                 MAX_SCHEDULE_TIMEOUT);
 463         if (r < 0)
 464                 return r;
 465
 466         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 467         if (r)
 468                 return r;
 469
 470         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 471         if (ptr)
 472                 *ptr = bo->kptr;
 473
 474         return 0;
 475 }
 476
 477 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 478 {
 479         if (bo->kptr == NULL)
 480                 return;
 481         bo->kptr = NULL;
 482         ttm_bo_kunmap(&bo->kmap);
 483 }
 484
 485 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 486 {
 487         if (bo == NULL)
 488                 return NULL;
 489
 490         ttm_bo_reference(&bo->tbo);
 491         return bo;
 492 }
 493
 494 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 495 {
 496         struct ttm_buffer_object *tbo;
 497
 498         if ((*bo) == NULL)
 499                 return;
 500
 501         tbo = &((*bo)->tbo);
 502         ttm_bo_unref(&tbo);
 503         if (tbo == NULL)
 504                 *bo = NULL;
 505 }
 506
 507 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 508                              u64 min_offset, u64 max_offset,
 509                              u64 *gpu_addr)
 510 {
 511         int r, i;
 512         unsigned fpfn, lpfn;
 513
 514         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 515                 return -EPERM;
 516
 517         if (WARN_ON_ONCE(min_offset > max_offset))
 518                 return -EINVAL;
 519
 520         if (bo->pin_count) {
 521                 bo->pin_count++;
 522                 if (gpu_addr)
 523                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 524
 525                 if (max_offset != 0) {
 526                         u64 domain_start;
 527                         if (domain == AMDGPU_GEM_DOMAIN_VRAM)
 528                                 domain_start = bo->adev->mc.vram_start;
 529                         else
 530                                 domain_start = bo->adev->mc.gtt_start;
 531                         WARN_ON_ONCE(max_offset <
 532                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 533                 }
 534
 535                 return 0;
 536         }
 537         amdgpu_ttm_placement_from_domain(bo, domain);
 538         for (i = 0; i < bo->placement.num_placement; i++) {
 539                 /* force to pin into visible video ram */
 540                 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 541                     !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) &&
 542                     (!max_offset || max_offset > bo->adev->mc.visible_vram_size)) {
 543                         if (WARN_ON_ONCE(min_offset >
 544                                          bo->adev->mc.visible_vram_size))
 545                                 return -EINVAL;
 546                         fpfn = min_offset >> PAGE_SHIFT;
 547                         lpfn = bo->adev->mc.visible_vram_size >> PAGE_SHIFT;
 548                 } else {
 549                         fpfn = min_offset >> PAGE_SHIFT;
 550                         lpfn = max_offset >> PAGE_SHIFT;
 551                 }
 552                 if (fpfn > bo->placements[i].fpfn)
 553                         bo->placements[i].fpfn = fpfn;
 554                 if (!bo->placements[i].lpfn ||
 555                     (lpfn && lpfn < bo->placements[i].lpfn))
 556                         bo->placements[i].lpfn = lpfn;
 557                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 558         }
 559
 560         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 561         if (likely(r == 0)) {
 562                 bo->pin_count = 1;
 563                 if (gpu_addr != NULL)
 564                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 565                 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 566                         bo->adev->vram_pin_size += amdgpu_bo_size(bo);
 567                         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 568                                 bo->adev->invisible_pin_size += amdgpu_bo_size(bo);
 569                 } else
 570                         bo->adev->gart_pin_size += amdgpu_bo_size(bo);
 571         } else {
 572                 dev_err(bo->adev->dev, "%p pin failed\n", bo);
 573         }
 574         return r;
 575 }
 576
 577 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 578 {
 579         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 580 }
 581
 582 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 583 {
 584         int r, i;
 585
 586         if (!bo->pin_count) {
 587                 dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo);
 588                 return 0;
 589         }
 590         bo->pin_count--;
 591         if (bo->pin_count)
 592                 return 0;
 593         for (i = 0; i < bo->placement.num_placement; i++) {
 594                 bo->placements[i].lpfn = 0;
 595                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 596         }
 597         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
 598         if (likely(r == 0)) {
 599                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 600                         bo->adev->vram_pin_size -= amdgpu_bo_size(bo);
 601                         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 602                                 bo->adev->invisible_pin_size -= amdgpu_bo_size(bo);
 603                 } else
 604                         bo->adev->gart_pin_size -= amdgpu_bo_size(bo);
 605         } else {
 606                 dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo);
 607         }
 608         return r;
 609 }
 610
 611 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 612 {
 613         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 614         if (0 && (adev->flags & AMD_IS_APU)) {
 615                 /* Useless to evict on IGP chips */
 616                 return 0;
 617         }
 618         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 619 }
 620
 621 static const char *amdgpu_vram_names[] = {
 622         "UNKNOWN",
 623         "GDDR1",
 624         "DDR2",
 625         "GDDR3",
 626         "GDDR4",
 627         "GDDR5",
 628         "HBM",
 629         "DDR3"
 630 };
 631
 632 int amdgpu_bo_init(struct amdgpu_device *adev)
 633 {
 634         /* Add an MTRR for the VRAM */
 635         adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
 636                                               adev->mc.aper_size);
 637         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 638                 adev->mc.mc_vram_size >> 20,
 639                 (unsigned long long)adev->mc.aper_size >> 20);
 640         DRM_INFO("RAM width %dbits %s\n",
 641                  adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
 642         return amdgpu_ttm_init(adev);
 643 }
 644
 645 void amdgpu_bo_fini(struct amdgpu_device *adev)
 646 {
 647         amdgpu_ttm_fini(adev);
 648         arch_phys_wc_del(adev->mc.vram_mtrr);
 649 }
 650
 651 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 652                              struct vm_area_struct *vma)
 653 {
 654         return ttm_fbdev_mmap(vma, &bo->tbo);
 655 }
 656
 657 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 658 {
 659         if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 660                 return -EINVAL;
 661
 662         bo->tiling_flags = tiling_flags;
 663         return 0;
 664 }
 665
 666 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 667 {
 668         lockdep_assert_held(&bo->tbo.resv->lock.base);
 669
 670         if (tiling_flags)
 671                 *tiling_flags = bo->tiling_flags;
 672 }
 673
 674 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 675                             uint32_t metadata_size, uint64_t flags)
 676 {
 677         void *buffer;
 678
 679         if (!metadata_size) {
 680                 if (bo->metadata_size) {
 681                         kfree(bo->metadata);
 682                         bo->metadata = NULL;
 683                         bo->metadata_size = 0;
 684                 }
 685                 return 0;
 686         }
 687
 688         if (metadata == NULL)
 689                 return -EINVAL;
 690
 691         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 692         if (buffer == NULL)
 693                 return -ENOMEM;
 694
 695         kfree(bo->metadata);
 696         bo->metadata_flags = flags;
 697         bo->metadata = buffer;
 698         bo->metadata_size = metadata_size;
 699
 700         return 0;
 701 }
 702
 703 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 704                            size_t buffer_size, uint32_t *metadata_size,
 705                            uint64_t *flags)
 706 {
 707         if (!buffer && !metadata_size)
 708                 return -EINVAL;
 709
 710         if (buffer) {
 711                 if (buffer_size < bo->metadata_size)
 712                         return -EINVAL;
 713
 714                 if (bo->metadata_size)
 715                         memcpy(buffer, bo->metadata, bo->metadata_size);
 716         }
 717
 718         if (metadata_size)
 719                 *metadata_size = bo->metadata_size;
 720         if (flags)
 721                 *flags = bo->metadata_flags;
 722
 723         return 0;
 724 }
 725
 726 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 727                            struct ttm_mem_reg *new_mem)
 728 {
 729         struct amdgpu_bo *rbo;
 730         struct ttm_mem_reg *old_mem = &bo->mem;
 731
 732         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 733                 return;
 734
 735         rbo = container_of(bo, struct amdgpu_bo, tbo);
 736         amdgpu_vm_bo_invalidate(rbo->adev, rbo);
 737
 738         /* update statistics */
 739         if (!new_mem)
 740                 return;
 741
 742         /* move_notify is called before move happens */
 743         amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem);
 744
 745         trace_amdgpu_ttm_bo_move(rbo, new_mem->mem_type, old_mem->mem_type);
 746 }
 747
 748 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 749 {
 750         struct amdgpu_device *adev;
 751         struct amdgpu_bo *abo;
 752         unsigned long offset, size, lpfn;
 753         int i, r;
 754
 755         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 756                 return 0;
 757
 758         abo = container_of(bo, struct amdgpu_bo, tbo);
 759         adev = abo->adev;
 760         if (bo->mem.mem_type != TTM_PL_VRAM)
 761                 return 0;
 762
 763         size = bo->mem.num_pages << PAGE_SHIFT;
 764         offset = bo->mem.start << PAGE_SHIFT;
 765         if ((offset + size) <= adev->mc.visible_vram_size)
 766                 return 0;
 767
 768         /* Can't move a pinned BO to visible VRAM */
 769         if (abo->pin_count > 0)
 770                 return -EINVAL;
 771
 772         /* hurrah the memory is not visible ! */
 773         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
 774         lpfn =  adev->mc.visible_vram_size >> PAGE_SHIFT;
 775         for (i = 0; i < abo->placement.num_placement; i++) {
 776                 /* Force into visible VRAM */
 777                 if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
 778                     (!abo->placements[i].lpfn || abo->placements[i].lpfn > lpfn))
 779                         abo->placements[i].lpfn = lpfn;
 780         }
 781         r = ttm_bo_validate(bo, &abo->placement, false, false);
 782         if (unlikely(r == -ENOMEM)) {
 783                 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 784                 return ttm_bo_validate(bo, &abo->placement, false, false);
 785         } else if (unlikely(r != 0)) {
 786                 return r;
 787         }
 788
 789         offset = bo->mem.start << PAGE_SHIFT;
 790         /* this should never happen */
 791         if ((offset + size) > adev->mc.visible_vram_size)
 792                 return -EINVAL;
 793
 794         return 0;
 795 }
 796
 797 /**
 798  * amdgpu_bo_fence - add fence to buffer object
 799  *
 800  * @bo: buffer object in question
 801  * @fence: fence to add
 802  * @shared: true if fence should be added shared
 803  *
 804  */
 805 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence,
 806                      bool shared)
 807 {
 808         struct reservation_object *resv = bo->tbo.resv;
 809
 810         if (shared)
 811                 reservation_object_add_shared_fence(resv, fence);
 812         else
 813                 reservation_object_add_excl_fence(resv, fence);
 814 }
 815
 816 /**
 817  * amdgpu_bo_gpu_offset - return GPU offset of bo
 818  * @bo: amdgpu object for which we query the offset
 819  *
 820  * Returns current GPU offset of the object.
 821  *
 822  * Note: object should either be pinned or reserved when calling this
 823  * function, it might be useful to add check for this for debugging.
 824  */
 825 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
 826 {
 827         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
 828         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
 829                      !bo->pin_count);
 830
 831         return bo->tbo.offset;
 832 }