drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include "drmP.h"
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33
  34 static void psp_set_funcs(struct amdgpu_device *adev);
  35
  36 static int psp_early_init(void *handle)
  37 {
  38         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  39
  40         psp_set_funcs(adev);
  41
  42         return 0;
  43 }
  44
  45 static int psp_sw_init(void *handle)
  46 {
  47         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  48         struct psp_context *psp = &adev->psp;
  49         int ret;
  50
  51         switch (adev->asic_type) {
  52         case CHIP_VEGA10:
  53                 psp->init_microcode = psp_v3_1_init_microcode;
  54                 psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
  55                 psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
  56                 psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
  57                 psp->ring_init = psp_v3_1_ring_init;
  58                 psp->ring_create = psp_v3_1_ring_create;
  59                 psp->ring_destroy = psp_v3_1_ring_destroy;
  60                 psp->cmd_submit = psp_v3_1_cmd_submit;
  61                 psp->compare_sram_data = psp_v3_1_compare_sram_data;
  62                 psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
  63                 break;
  64         default:
  65                 return -EINVAL;
  66         }
  67
  68         psp->adev = adev;
  69
  70         ret = psp_init_microcode(psp);
  71         if (ret) {
  72                 DRM_ERROR("Failed to load psp firmware!\n");
  73                 return ret;
  74         }
  75
  76         return 0;
  77 }
  78
  79 static int psp_sw_fini(void *handle)
  80 {
  81         return 0;
  82 }
  83
  84 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
  85                  uint32_t reg_val, uint32_t mask, bool check_changed)
  86 {
  87         uint32_t val;
  88         int i;
  89         struct amdgpu_device *adev = psp->adev;
  90
  91         val = RREG32(reg_index);
  92
  93         for (i = 0; i < adev->usec_timeout; i++) {
  94                 if (check_changed) {
  95                         if (val != reg_val)
  96                                 return 0;
  97                 } else {
  98                         if ((val & mask) == reg_val)
  99                                 return 0;
 100                 }
 101                 udelay(1);
 102         }
 103
 104         return -ETIME;
 105 }
 106
 107 static int
 108 psp_cmd_submit_buf(struct psp_context *psp,
 109                    struct amdgpu_firmware_info *ucode,
 110                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
 111                    int index)
 112 {
 113         int ret;
 114         struct amdgpu_bo *cmd_buf_bo;
 115         uint64_t cmd_buf_mc_addr;
 116         struct psp_gfx_cmd_resp *cmd_buf_mem;
 117         struct amdgpu_device *adev = psp->adev;
 118
 119         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 120                                       AMDGPU_GEM_DOMAIN_VRAM,
 121                                       &cmd_buf_bo, &cmd_buf_mc_addr,
 122                                       (void **)&cmd_buf_mem);
 123         if (ret)
 124                 return ret;
 125
 126         memset(cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 127
 128         memcpy(cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 129
 130         ret = psp_cmd_submit(psp, ucode, cmd_buf_mc_addr,
 131                              fence_mc_addr, index);
 132
 133         while (*((unsigned int *)psp->fence_buf) != index) {
 134                 msleep(1);
 135         }
 136
 137         amdgpu_bo_free_kernel(&cmd_buf_bo,
 138                               &cmd_buf_mc_addr,
 139                               (void **)&cmd_buf_mem);
 140
 141         return ret;
 142 }
 143
 144 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 145                                  uint64_t tmr_mc, uint32_t size)
 146 {
 147         cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 148         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = (uint32_t)tmr_mc;
 149         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = (uint32_t)(tmr_mc >> 32);
 150         cmd->cmd.cmd_setup_tmr.buf_size = size;
 151 }
 152
 153 /* Set up Trusted Memory Region */
 154 static int psp_tmr_init(struct psp_context *psp)
 155 {
 156         int ret;
 157
 158         /*
 159          * Allocate 3M memory aligned to 1M from Frame Buffer (local
 160          * physical).
 161          *
 162          * Note: this memory need be reserved till the driver
 163          * uninitializes.
 164          */
 165         ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
 166                                       AMDGPU_GEM_DOMAIN_VRAM,
 167                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 168
 169         return ret;
 170 }
 171
 172 static int psp_tmr_load(struct psp_context *psp)
 173 {
 174         int ret;
 175         struct psp_gfx_cmd_resp *cmd;
 176
 177         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 178         if (!cmd)
 179                 return -ENOMEM;
 180
 181         psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
 182
 183         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 184                                  psp->fence_buf_mc_addr, 1);
 185         if (ret)
 186                 goto failed;
 187
 188         kfree(cmd);
 189
 190         return 0;
 191
 192 failed:
 193         kfree(cmd);
 194         return ret;
 195 }
 196
 197 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 198                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 199                                  uint32_t size, uint32_t shared_size)
 200 {
 201         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 202         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 203         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 204         cmd->cmd.cmd_load_ta.app_len = size;
 205
 206         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 207         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 208         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 209 }
 210
 211 static int psp_asd_init(struct psp_context *psp)
 212 {
 213         int ret;
 214
 215         /*
 216          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 217          * physical) for shared ASD <-> Driver
 218          */
 219         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 220                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 221                                       &psp->asd_shared_bo,
 222                                       &psp->asd_shared_mc_addr,
 223                                       &psp->asd_shared_buf);
 224
 225         return ret;
 226 }
 227
 228 static int psp_asd_load(struct psp_context *psp)
 229 {
 230         int ret;
 231         struct psp_gfx_cmd_resp *cmd;
 232
 233         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 234         if (!cmd)
 235                 return -ENOMEM;
 236
 237         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 238         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 239
 240         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 241                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 242
 243         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 244                                  psp->fence_buf_mc_addr, 2);
 245
 246         kfree(cmd);
 247
 248         return ret;
 249 }
 250
 251 static int psp_hw_start(struct psp_context *psp)
 252 {
 253         int ret;
 254
 255         ret = psp_bootloader_load_sysdrv(psp);
 256         if (ret)
 257                 return ret;
 258
 259         ret = psp_bootloader_load_sos(psp);
 260         if (ret)
 261                 return ret;
 262
 263         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
 264         if (ret)
 265                 return ret;
 266
 267         ret = psp_tmr_load(psp);
 268         if (ret)
 269                 return ret;
 270
 271         ret = psp_asd_load(psp);
 272         if (ret)
 273                 return ret;
 274
 275         return 0;
 276 }
 277
 278 static int psp_np_fw_load(struct psp_context *psp)
 279 {
 280         int i, ret;
 281         struct amdgpu_firmware_info *ucode;
 282         struct amdgpu_device* adev = psp->adev;
 283
 284         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 285                 ucode = &adev->firmware.ucode[i];
 286                 if (!ucode->fw)
 287                         continue;
 288
 289                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
 290                     psp_smu_reload_quirk(psp))
 291                         continue;
 292                 if (amdgpu_sriov_vf(adev) &&
 293                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
 294                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
 295                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
 296                         /*skip ucode loading in SRIOV VF */
 297                         continue;
 298
 299                 ret = psp_prep_cmd_buf(ucode, psp->cmd);
 300                 if (ret)
 301                         return ret;
 302
 303                 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
 304                                          psp->fence_buf_mc_addr, i + 3);
 305                 if (ret)
 306                         return ret;
 307
 308 #if 0
 309                 /* check if firmware loaded sucessfully */
 310                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
 311                         return -EINVAL;
 312 #endif
 313         }
 314
 315         return 0;
 316 }
 317
 318 static int psp_load_fw(struct amdgpu_device *adev)
 319 {
 320         int ret;
 321         struct psp_context *psp = &adev->psp;
 322         struct psp_gfx_cmd_resp *cmd;
 323
 324         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 325         if (!cmd)
 326                 return -ENOMEM;
 327
 328         psp->cmd = cmd;
 329
 330         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 331                                       AMDGPU_GEM_DOMAIN_GTT,
 332                                       &psp->fw_pri_bo,
 333                                       &psp->fw_pri_mc_addr,
 334                                       &psp->fw_pri_buf);
 335         if (ret)
 336                 goto failed;
 337
 338         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 339                                       AMDGPU_GEM_DOMAIN_VRAM,
 340                                       &psp->fence_buf_bo,
 341                                       &psp->fence_buf_mc_addr,
 342                                       &psp->fence_buf);
 343         if (ret)
 344                 goto failed_mem1;
 345
 346         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
 347
 348         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
 349         if (ret)
 350                 goto failed_mem1;
 351
 352         ret = psp_tmr_init(psp);
 353         if (ret)
 354                 goto failed_mem;
 355
 356         ret = psp_asd_init(psp);
 357         if (ret)
 358                 goto failed_mem;
 359
 360         ret = psp_hw_start(psp);
 361         if (ret)
 362                 goto failed_mem;
 363
 364         ret = psp_np_fw_load(psp);
 365         if (ret)
 366                 goto failed_mem;
 367
 368         kfree(cmd);
 369
 370         return 0;
 371
 372 failed_mem:
 373         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 374                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 375 failed_mem1:
 376         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 377                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 378 failed:
 379         kfree(cmd);
 380         return ret;
 381 }
 382
 383 static int psp_hw_init(void *handle)
 384 {
 385         int ret;
 386         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 387
 388
 389         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 390                 return 0;
 391
 392         mutex_lock(&adev->firmware.mutex);
 393         /*
 394          * This sequence is just used on hw_init only once, no need on
 395          * resume.
 396          */
 397         ret = amdgpu_ucode_init_bo(adev);
 398         if (ret)
 399                 goto failed;
 400
 401         ret = psp_load_fw(adev);
 402         if (ret) {
 403                 DRM_ERROR("PSP firmware loading failed\n");
 404                 goto failed;
 405         }
 406
 407         mutex_unlock(&adev->firmware.mutex);
 408         return 0;
 409
 410 failed:
 411         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
 412         mutex_unlock(&adev->firmware.mutex);
 413         return -EINVAL;
 414 }
 415
 416 static int psp_hw_fini(void *handle)
 417 {
 418         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 419         struct psp_context *psp = &adev->psp;
 420
 421         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 422                 return 0;
 423
 424         amdgpu_ucode_fini_bo(adev);
 425
 426         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 427
 428         if (psp->tmr_buf)
 429                 amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 430
 431         if (psp->fw_pri_buf)
 432                 amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 433                                       &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 434
 435         if (psp->fence_buf_bo)
 436                 amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 437                                       &psp->fence_buf_mc_addr, &psp->fence_buf);
 438
 439         return 0;
 440 }
 441
 442 static int psp_suspend(void *handle)
 443 {
 444         return 0;
 445 }
 446
 447 static int psp_resume(void *handle)
 448 {
 449         int ret;
 450         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 451         struct psp_context *psp = &adev->psp;
 452
 453         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 454                 return 0;
 455
 456         DRM_INFO("PSP is resuming...\n");
 457
 458         mutex_lock(&adev->firmware.mutex);
 459
 460         ret = psp_hw_start(psp);
 461         if (ret)
 462                 goto failed;
 463
 464         ret = psp_np_fw_load(psp);
 465         if (ret)
 466                 goto failed;
 467
 468         mutex_unlock(&adev->firmware.mutex);
 469
 470         return 0;
 471
 472 failed:
 473         DRM_ERROR("PSP resume failed\n");
 474         mutex_unlock(&adev->firmware.mutex);
 475         return ret;
 476 }
 477
 478 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 479                                         enum AMDGPU_UCODE_ID ucode_type)
 480 {
 481         struct amdgpu_firmware_info *ucode = NULL;
 482
 483         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 484                 DRM_INFO("firmware is not loaded by PSP\n");
 485                 return true;
 486         }
 487
 488         if (!adev->firmware.fw_size)
 489                 return false;
 490
 491         ucode = &adev->firmware.ucode[ucode_type];
 492         if (!ucode->fw || !ucode->ucode_size)
 493                 return false;
 494
 495         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
 496 }
 497
 498 static int psp_set_clockgating_state(void *handle,
 499                                      enum amd_clockgating_state state)
 500 {
 501         return 0;
 502 }
 503
 504 static int psp_set_powergating_state(void *handle,
 505                                      enum amd_powergating_state state)
 506 {
 507         return 0;
 508 }
 509
 510 const struct amd_ip_funcs psp_ip_funcs = {
 511         .name = "psp",
 512         .early_init = psp_early_init,
 513         .late_init = NULL,
 514         .sw_init = psp_sw_init,
 515         .sw_fini = psp_sw_fini,
 516         .hw_init = psp_hw_init,
 517         .hw_fini = psp_hw_fini,
 518         .suspend = psp_suspend,
 519         .resume = psp_resume,
 520         .is_idle = NULL,
 521         .wait_for_idle = NULL,
 522         .soft_reset = NULL,
 523         .set_clockgating_state = psp_set_clockgating_state,
 524         .set_powergating_state = psp_set_powergating_state,
 525 };
 526
 527 static const struct amdgpu_psp_funcs psp_funcs = {
 528         .check_fw_loading_status = psp_check_fw_loading_status,
 529 };
 530
 531 static void psp_set_funcs(struct amdgpu_device *adev)
 532 {
 533         if (NULL == adev->firmware.funcs)
 534                 adev->firmware.funcs = &psp_funcs;
 535 }
 536
 537 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
 538 {
 539         .type = AMD_IP_BLOCK_TYPE_PSP,
 540         .major = 3,
 541         .minor = 1,
 542         .rev = 0,
 543         .funcs = &psp_ip_funcs,
 544 };