drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include "pp_instance.h"
  27 #include "smumgr.h"
  28 #include "cgs_common.h"
  29 #include "linux/delay.h"
  30 #include "cz_smumgr.h"
  31 #include "tonga_smumgr.h"
  32 #include "fiji_smumgr.h"
  33 #include "polaris10_smumgr.h"
  34
  35 int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
  36 {
  37         struct pp_smumgr *smumgr;
  38
  39         if ((handle == NULL) || (pp_init == NULL))
  40                 return -EINVAL;
  41
  42         smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL);
  43         if (smumgr == NULL)
  44                 return -ENOMEM;
  45
  46         smumgr->device = pp_init->device;
  47         smumgr->chip_family = pp_init->chip_family;
  48         smumgr->chip_id = pp_init->chip_id;
  49         smumgr->hw_revision = pp_init->rev_id;
  50         smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
  51         smumgr->reload_fw = 1;
  52         handle->smu_mgr = smumgr;
  53
  54         switch (smumgr->chip_family) {
  55         case AMD_FAMILY_CZ:
  56                 cz_smum_init(smumgr);
  57                 break;
  58         case AMD_FAMILY_VI:
  59                 switch (smumgr->chip_id) {
  60                 case CHIP_TONGA:
  61                         tonga_smum_init(smumgr);
  62                         break;
  63                 case CHIP_FIJI:
  64                         fiji_smum_init(smumgr);
  65                         break;
  66                 case CHIP_POLARIS11:
  67                 case CHIP_POLARIS10:
  68                         polaris10_smum_init(smumgr);
  69                         break;
  70                 default:
  71                         return -EINVAL;
  72                 }
  73                 break;
  74         default:
  75                 kfree(smumgr);
  76                 return -EINVAL;
  77         }
  78
  79         return 0;
  80 }
  81
  82 int smum_fini(struct pp_smumgr *smumgr)
  83 {
  84         kfree(smumgr->device);
  85         kfree(smumgr);
  86         return 0;
  87 }
  88
  89 int smum_get_argument(struct pp_smumgr *smumgr)
  90 {
  91         if (NULL != smumgr->smumgr_funcs->get_argument)
  92                 return smumgr->smumgr_funcs->get_argument(smumgr);
  93
  94         return 0;
  95 }
  96
  97 int smum_download_powerplay_table(struct pp_smumgr *smumgr,
  98                                                                 void **table)
  99 {
 100         if (NULL != smumgr->smumgr_funcs->download_pptable_settings)
 101                 return smumgr->smumgr_funcs->download_pptable_settings(smumgr,
 102                                                                         table);
 103
 104         return 0;
 105 }
 106
 107 int smum_upload_powerplay_table(struct pp_smumgr *smumgr)
 108 {
 109         if (NULL != smumgr->smumgr_funcs->upload_pptable_settings)
 110                 return smumgr->smumgr_funcs->upload_pptable_settings(smumgr);
 111
 112         return 0;
 113 }
 114
 115 int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
 116 {
 117         if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL)
 118                 return -EINVAL;
 119
 120         return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg);
 121 }
 122
 123 int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
 124                                         uint16_t msg, uint32_t parameter)
 125 {
 126         if (smumgr == NULL ||
 127                 smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
 128                 return -EINVAL;
 129         return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter(
 130                                                 smumgr, msg, parameter);
 131 }
 132
 133 /*
 134  * Returns once the part of the register indicated by the mask has
 135  * reached the given value.
 136  */
 137 int smum_wait_on_register(struct pp_smumgr *smumgr,
 138                                 uint32_t index,
 139                                 uint32_t value, uint32_t mask)
 140 {
 141         uint32_t i;
 142         uint32_t cur_value;
 143
 144         if (smumgr == NULL || smumgr->device == NULL)
 145                 return -EINVAL;
 146
 147         for (i = 0; i < smumgr->usec_timeout; i++) {
 148                 cur_value = cgs_read_register(smumgr->device, index);
 149                 if ((cur_value & mask) == (value & mask))
 150                         break;
 151                 udelay(1);
 152         }
 153
 154         /* timeout means wrong logic*/
 155         if (i == smumgr->usec_timeout)
 156                 return -1;
 157
 158         return 0;
 159 }
 160
 161 int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
 162                                         uint32_t index,
 163                                         uint32_t value, uint32_t mask)
 164 {
 165         uint32_t i;
 166         uint32_t cur_value;
 167
 168         if (smumgr == NULL)
 169                 return -EINVAL;
 170
 171         for (i = 0; i < smumgr->usec_timeout; i++) {
 172                 cur_value = cgs_read_register(smumgr->device,
 173                                                                         index);
 174                 if ((cur_value & mask) != (value & mask))
 175                         break;
 176                 udelay(1);
 177         }
 178
 179         /* timeout means wrong logic */
 180         if (i == smumgr->usec_timeout)
 181                 return -1;
 182
 183         return 0;
 184 }
 185
 186
 187 /*
 188  * Returns once the part of the register indicated by the mask
 189  * has reached the given value.The indirect space is described by
 190  * giving the memory-mapped index of the indirect index register.
 191  */
 192 int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
 193                                         uint32_t indirect_port,
 194                                         uint32_t index,
 195                                         uint32_t value,
 196                                         uint32_t mask)
 197 {
 198         if (smumgr == NULL || smumgr->device == NULL)
 199                 return -EINVAL;
 200
 201         cgs_write_register(smumgr->device, indirect_port, index);
 202         return smum_wait_on_register(smumgr, indirect_port + 1,
 203                                                 mask, value);
 204 }
 205
 206 void smum_wait_for_indirect_register_unequal(
 207                                                 struct pp_smumgr *smumgr,
 208                                                 uint32_t indirect_port,
 209                                                 uint32_t index,
 210                                                 uint32_t value,
 211                                                 uint32_t mask)
 212 {
 213         if (smumgr == NULL || smumgr->device == NULL)
 214                 return;
 215         cgs_write_register(smumgr->device, indirect_port, index);
 216         smum_wait_for_register_unequal(smumgr, indirect_port + 1,
 217                                                 value, mask);
 218 }
 219
 220 int smu_allocate_memory(void *device, uint32_t size,
 221                          enum cgs_gpu_mem_type type,
 222                          uint32_t byte_align, uint64_t *mc_addr,
 223                          void **kptr, void *handle)
 224 {
 225         int ret = 0;
 226         cgs_handle_t cgs_handle;
 227
 228         if (device == NULL || handle == NULL ||
 229             mc_addr == NULL || kptr == NULL)
 230                 return -EINVAL;
 231
 232         ret = cgs_alloc_gpu_mem(device, type, size, byte_align,
 233                                 0, 0, (cgs_handle_t *)handle);
 234         if (ret)
 235                 return -ENOMEM;
 236
 237         cgs_handle = *(cgs_handle_t *)handle;
 238
 239         ret = cgs_gmap_gpu_mem(device, cgs_handle, mc_addr);
 240         if (ret)
 241                 goto error_gmap;
 242
 243         ret = cgs_kmap_gpu_mem(device, cgs_handle, kptr);
 244         if (ret)
 245                 goto error_kmap;
 246
 247         return 0;
 248
 249 error_kmap:
 250         cgs_gunmap_gpu_mem(device, cgs_handle);
 251
 252 error_gmap:
 253         cgs_free_gpu_mem(device, cgs_handle);
 254         return ret;
 255 }
 256
 257 int smu_free_memory(void *device, void *handle)
 258 {
 259         cgs_handle_t cgs_handle = (cgs_handle_t)handle;
 260
 261         if (device == NULL || handle == NULL)
 262                 return -EINVAL;
 263
 264         cgs_kunmap_gpu_mem(device, cgs_handle);
 265         cgs_gunmap_gpu_mem(device, cgs_handle);
 266         cgs_free_gpu_mem(device, cgs_handle);
 267
 268         return 0;
 269 }