drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/types.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <drm/amdgpu_drm.h>
  27 #include "pp_instance.h"
  28 #include "smumgr.h"
  29 #include "cgs_common.h"
  30 #include "linux/delay.h"
  31
  32
  33 int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle)
  34 {
  35         struct pp_smumgr *smumgr;
  36
  37         if ((handle == NULL) || (pp_init == NULL))
  38                 return -EINVAL;
  39
  40         smumgr = kzalloc(sizeof(struct pp_smumgr), GFP_KERNEL);
  41         if (smumgr == NULL)
  42                 return -ENOMEM;
  43
  44         smumgr->device = pp_init->device;
  45         smumgr->chip_family = pp_init->chip_family;
  46         smumgr->chip_id = pp_init->chip_id;
  47         smumgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
  48         smumgr->reload_fw = 1;
  49         handle->smu_mgr = smumgr;
  50
  51         switch (smumgr->chip_family) {
  52         case AMDGPU_FAMILY_CZ:
  53                 cz_smum_init(smumgr);
  54                 break;
  55         case AMDGPU_FAMILY_VI:
  56                 switch (smumgr->chip_id) {
  57                 case CHIP_TOPAZ:
  58                         iceland_smum_init(smumgr);
  59                         break;
  60                 case CHIP_TONGA:
  61                         tonga_smum_init(smumgr);
  62                         break;
  63                 case CHIP_FIJI:
  64                         fiji_smum_init(smumgr);
  65                         break;
  66                 case CHIP_POLARIS11:
  67                 case CHIP_POLARIS10:
  68                 case CHIP_POLARIS12:
  69                         polaris10_smum_init(smumgr);
  70                         break;
  71                 default:
  72                         return -EINVAL;
  73                 }
  74                 break;
  75         default:
  76                 kfree(smumgr);
  77                 return -EINVAL;
  78         }
  79
  80         return 0;
  81 }
  82
  83 int smum_fini(struct pp_smumgr *smumgr)
  84 {
  85         kfree(smumgr->device);
  86         kfree(smumgr);
  87         return 0;
  88 }
  89
  90 int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr,
  91                 void *input, void *output, void *storage, int result)
  92 {
  93         if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable)
  94                 return hwmgr->smumgr->smumgr_funcs->thermal_avfs_enable(hwmgr);
  95
  96         return 0;
  97 }
  98
  99 int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr,
 100                 void *input, void *output, void *storage, int result)
 101 {
 102         if (NULL != hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table)
 103                 return hwmgr->smumgr->smumgr_funcs->thermal_setup_fan_table(hwmgr);
 104
 105         return 0;
 106 }
 107
 108 int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr)
 109 {
 110
 111         if (NULL != hwmgr->smumgr->smumgr_funcs->update_sclk_threshold)
 112                 return hwmgr->smumgr->smumgr_funcs->update_sclk_threshold(hwmgr);
 113
 114         return 0;
 115 }
 116
 117 int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
 118 {
 119
 120         if (NULL != hwmgr->smumgr->smumgr_funcs->update_smc_table)
 121                 return hwmgr->smumgr->smumgr_funcs->update_smc_table(hwmgr, type);
 122
 123         return 0;
 124 }
 125
 126 uint32_t smum_get_offsetof(struct pp_smumgr *smumgr, uint32_t type, uint32_t member)
 127 {
 128         if (NULL != smumgr->smumgr_funcs->get_offsetof)
 129                 return smumgr->smumgr_funcs->get_offsetof(type, member);
 130
 131         return 0;
 132 }
 133
 134 int smum_process_firmware_header(struct pp_hwmgr *hwmgr)
 135 {
 136         if (NULL != hwmgr->smumgr->smumgr_funcs->process_firmware_header)
 137                 return hwmgr->smumgr->smumgr_funcs->process_firmware_header(hwmgr);
 138         return 0;
 139 }
 140
 141 int smum_get_argument(struct pp_smumgr *smumgr)
 142 {
 143         if (NULL != smumgr->smumgr_funcs->get_argument)
 144                 return smumgr->smumgr_funcs->get_argument(smumgr);
 145
 146         return 0;
 147 }
 148
 149 uint32_t smum_get_mac_definition(struct pp_smumgr *smumgr, uint32_t value)
 150 {
 151         if (NULL != smumgr->smumgr_funcs->get_mac_definition)
 152                 return smumgr->smumgr_funcs->get_mac_definition(value);
 153
 154         return 0;
 155 }
 156
 157 int smum_download_powerplay_table(struct pp_smumgr *smumgr,
 158                                                                 void **table)
 159 {
 160         if (NULL != smumgr->smumgr_funcs->download_pptable_settings)
 161                 return smumgr->smumgr_funcs->download_pptable_settings(smumgr,
 162                                                                         table);
 163         return 0;
 164 }
 165
 166 int smum_upload_powerplay_table(struct pp_smumgr *smumgr)
 167 {
 168         if (NULL != smumgr->smumgr_funcs->upload_pptable_settings)
 169                 return smumgr->smumgr_funcs->upload_pptable_settings(smumgr);
 170
 171         return 0;
 172 }
 173
 174 int smum_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg)
 175 {
 176         if (smumgr == NULL || smumgr->smumgr_funcs->send_msg_to_smc == NULL)
 177                 return -EINVAL;
 178
 179         return smumgr->smumgr_funcs->send_msg_to_smc(smumgr, msg);
 180 }
 181
 182 int smum_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr,
 183                                         uint16_t msg, uint32_t parameter)
 184 {
 185         if (smumgr == NULL ||
 186                 smumgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
 187                 return -EINVAL;
 188         return smumgr->smumgr_funcs->send_msg_to_smc_with_parameter(
 189                                                 smumgr, msg, parameter);
 190 }
 191
 192 /*
 193  * Returns once the part of the register indicated by the mask has
 194  * reached the given value.
 195  */
 196 int smum_wait_on_register(struct pp_smumgr *smumgr,
 197                                 uint32_t index,
 198                                 uint32_t value, uint32_t mask)
 199 {
 200         uint32_t i;
 201         uint32_t cur_value;
 202
 203         if (smumgr == NULL || smumgr->device == NULL)
 204                 return -EINVAL;
 205
 206         for (i = 0; i < smumgr->usec_timeout; i++) {
 207                 cur_value = cgs_read_register(smumgr->device, index);
 208                 if ((cur_value & mask) == (value & mask))
 209                         break;
 210                 udelay(1);
 211         }
 212
 213         /* timeout means wrong logic*/
 214         if (i == smumgr->usec_timeout)
 215                 return -1;
 216
 217         return 0;
 218 }
 219
 220 int smum_wait_for_register_unequal(struct pp_smumgr *smumgr,
 221                                         uint32_t index,
 222                                         uint32_t value, uint32_t mask)
 223 {
 224         uint32_t i;
 225         uint32_t cur_value;
 226
 227         if (smumgr == NULL)
 228                 return -EINVAL;
 229
 230         for (i = 0; i < smumgr->usec_timeout; i++) {
 231                 cur_value = cgs_read_register(smumgr->device,
 232                                                                         index);
 233                 if ((cur_value & mask) != (value & mask))
 234                         break;
 235                 udelay(1);
 236         }
 237
 238         /* timeout means wrong logic */
 239         if (i == smumgr->usec_timeout)
 240                 return -1;
 241
 242         return 0;
 243 }
 244
 245
 246 /*
 247  * Returns once the part of the register indicated by the mask
 248  * has reached the given value.The indirect space is described by
 249  * giving the memory-mapped index of the indirect index register.
 250  */
 251 int smum_wait_on_indirect_register(struct pp_smumgr *smumgr,
 252                                         uint32_t indirect_port,
 253                                         uint32_t index,
 254                                         uint32_t value,
 255                                         uint32_t mask)
 256 {
 257         if (smumgr == NULL || smumgr->device == NULL)
 258                 return -EINVAL;
 259
 260         cgs_write_register(smumgr->device, indirect_port, index);
 261         return smum_wait_on_register(smumgr, indirect_port + 1,
 262                                                 mask, value);
 263 }
 264
 265 void smum_wait_for_indirect_register_unequal(
 266                                                 struct pp_smumgr *smumgr,
 267                                                 uint32_t indirect_port,
 268                                                 uint32_t index,
 269                                                 uint32_t value,
 270                                                 uint32_t mask)
 271 {
 272         if (smumgr == NULL || smumgr->device == NULL)
 273                 return;
 274         cgs_write_register(smumgr->device, indirect_port, index);
 275         smum_wait_for_register_unequal(smumgr, indirect_port + 1,
 276                                                 value, mask);
 277 }
 278
 279 int smu_allocate_memory(void *device, uint32_t size,
 280                          enum cgs_gpu_mem_type type,
 281                          uint32_t byte_align, uint64_t *mc_addr,
 282                          void **kptr, void *handle)
 283 {
 284         int ret = 0;
 285         cgs_handle_t cgs_handle;
 286
 287         if (device == NULL || handle == NULL ||
 288             mc_addr == NULL || kptr == NULL)
 289                 return -EINVAL;
 290
 291         ret = cgs_alloc_gpu_mem(device, type, size, byte_align,
 292                                 0, 0, (cgs_handle_t *)handle);
 293         if (ret)
 294                 return -ENOMEM;
 295
 296         cgs_handle = *(cgs_handle_t *)handle;
 297
 298         ret = cgs_gmap_gpu_mem(device, cgs_handle, mc_addr);
 299         if (ret)
 300                 goto error_gmap;
 301
 302         ret = cgs_kmap_gpu_mem(device, cgs_handle, kptr);
 303         if (ret)
 304                 goto error_kmap;
 305
 306         return 0;
 307
 308 error_kmap:
 309         cgs_gunmap_gpu_mem(device, cgs_handle);
 310
 311 error_gmap:
 312         cgs_free_gpu_mem(device, cgs_handle);
 313         return ret;
 314 }
 315
 316 int smu_free_memory(void *device, void *handle)
 317 {
 318         cgs_handle_t cgs_handle = (cgs_handle_t)handle;
 319
 320         if (device == NULL || handle == NULL)
 321                 return -EINVAL;
 322
 323         cgs_kunmap_gpu_mem(device, cgs_handle);
 324         cgs_gunmap_gpu_mem(device, cgs_handle);
 325         cgs_free_gpu_mem(device, cgs_handle);
 326
 327         return 0;
 328 }
 329
 330 int smum_init_smc_table(struct pp_hwmgr *hwmgr)
 331 {
 332         if (NULL != hwmgr->smumgr->smumgr_funcs->init_smc_table)
 333                 return hwmgr->smumgr->smumgr_funcs->init_smc_table(hwmgr);
 334
 335         return 0;
 336 }
 337
 338 int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
 339 {
 340         if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels)
 341                 return hwmgr->smumgr->smumgr_funcs->populate_all_graphic_levels(hwmgr);
 342
 343         return 0;
 344 }
 345
 346 int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
 347 {
 348         if (NULL != hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels)
 349                 return hwmgr->smumgr->smumgr_funcs->populate_all_memory_levels(hwmgr);
 350
 351         return 0;
 352 }
 353
 354 /*this interface is needed by island ci/vi */
 355 int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
 356 {
 357         if (NULL != hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table)
 358                 return hwmgr->smumgr->smumgr_funcs->initialize_mc_reg_table(hwmgr);
 359
 360         return 0;
 361 }
 362
 363 bool smum_is_dpm_running(struct pp_hwmgr *hwmgr)
 364 {
 365         if (NULL != hwmgr->smumgr->smumgr_funcs->is_dpm_running)
 366                 return hwmgr->smumgr->smumgr_funcs->is_dpm_running(hwmgr);
 367
 368         return true;
 369 }