2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Zhiyuan Lv <zhiyuan.lv@intel.com>
25 * Zhi Wang <zhi.a.wang@intel.com>
28 * Min He <min.he@intel.com>
29 * Bing Niu <bing.niu@intel.com>
30 * Ping Gao <ping.a.gao@intel.com>
31 * Tina Zhang <tina.zhang@intel.com>
35 #ifndef _GVT_EXECLIST_H_
36 #define _GVT_EXECLIST_H_
38 struct execlist_ctx_descriptor_format {
47 u32 force_pd_restore : 1;
48 u32 force_restore : 1;
49 u32 addressing_mode : 2;
50 u32 llc_coherency : 1;
51 u32 fault_handling : 2;
52 u32 privilege_access : 1;
59 struct execlist_status_format {
63 u32 current_execlist_pointer :1;
64 u32 execlist_write_pointer :1;
65 u32 execlist_queue_full :1;
66 u32 execlist_1_valid :1;
67 u32 execlist_0_valid :1;
68 u32 last_ctx_switch_reason :9;
69 u32 current_active_elm_status :2;
70 u32 arbitration_enable :1;
71 u32 execlist_1_active :1;
72 u32 execlist_0_active :1;
82 struct execlist_context_status_pointer_format {
95 struct execlist_context_status_format {
99 u32 idle_to_active :1;
101 u32 element_switch :1;
102 u32 active_to_idle :1;
103 u32 context_complete :1;
104 u32 wait_on_sync_flip :1;
105 u32 wait_on_vblank :1;
106 u32 wait_on_semaphore :1;
107 u32 wait_on_scanline :1;
109 u32 semaphore_wait_mode :1;
110 u32 display_plane :3;
121 struct execlist_mmio_pair {
126 /* The first 52 dwords in register state context */
127 struct execlist_ring_context {
130 struct execlist_mmio_pair ctx_ctrl;
131 struct execlist_mmio_pair ring_header;
132 struct execlist_mmio_pair ring_tail;
133 struct execlist_mmio_pair rb_start;
134 struct execlist_mmio_pair rb_ctrl;
135 struct execlist_mmio_pair bb_cur_head_UDW;
136 struct execlist_mmio_pair bb_cur_head_LDW;
137 struct execlist_mmio_pair bb_state;
138 struct execlist_mmio_pair second_bb_addr_UDW;
139 struct execlist_mmio_pair second_bb_addr_LDW;
140 struct execlist_mmio_pair second_bb_state;
141 struct execlist_mmio_pair bb_per_ctx_ptr;
142 struct execlist_mmio_pair rcs_indirect_ctx;
143 struct execlist_mmio_pair rcs_indirect_ctx_offset;
148 struct execlist_mmio_pair ctx_timestamp;
149 struct execlist_mmio_pair pdp3_UDW;
150 struct execlist_mmio_pair pdp3_LDW;
151 struct execlist_mmio_pair pdp2_UDW;
152 struct execlist_mmio_pair pdp2_LDW;
153 struct execlist_mmio_pair pdp1_UDW;
154 struct execlist_mmio_pair pdp1_LDW;
155 struct execlist_mmio_pair pdp0_UDW;
156 struct execlist_mmio_pair pdp0_LDW;
159 struct intel_vgpu_elsp_dwords {
164 struct intel_vgpu_execlist_slot {
165 struct execlist_ctx_descriptor_format ctx[2];
169 struct intel_vgpu_execlist {
170 struct intel_vgpu_execlist_slot slot[2];
171 struct intel_vgpu_execlist_slot *running_slot;
172 struct intel_vgpu_execlist_slot *pending_slot;
173 struct execlist_ctx_descriptor_format *running_context;
175 struct intel_vgpu *vgpu;
176 struct intel_vgpu_elsp_dwords elsp_dwords;
179 void intel_vgpu_clean_execlist(struct intel_vgpu *vgpu);
181 int intel_vgpu_init_execlist(struct intel_vgpu *vgpu);
183 int intel_vgpu_submit_execlist(struct intel_vgpu *vgpu, int ring_id);
185 void intel_vgpu_reset_execlist(struct intel_vgpu *vgpu,
186 unsigned long engine_mask);
188 #endif /*_GVT_EXECLIST_H_*/