drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include "intel_frontbuffer.h"
  38 #include <drm/i915_drm.h>
  39 #include "i915_drv.h"
  40 #include "i915_gem_clflush.h"
  41 #include "intel_dsi.h"
  42 #include "i915_trace.h"
  43 #include <drm/drm_atomic.h>
  44 #include <drm/drm_atomic_helper.h>
  45 #include <drm/drm_dp_helper.h>
  46 #include <drm/drm_crtc_helper.h>
  47 #include <drm/drm_plane_helper.h>
  48 #include <drm/drm_rect.h>
  49 #include <linux/dma_remapping.h>
  50 #include <linux/reservation.h>
  51
  52 static bool is_mmio_work(struct intel_flip_work *work)
  53 {
  54         return work->mmio_work.func;
  55 }
  56
  57 /* Primary plane formats for gen <= 3 */
  58 static const uint32_t i8xx_primary_formats[] = {
  59         DRM_FORMAT_C8,
  60         DRM_FORMAT_RGB565,
  61         DRM_FORMAT_XRGB1555,
  62         DRM_FORMAT_XRGB8888,
  63 };
  64
  65 /* Primary plane formats for gen >= 4 */
  66 static const uint32_t i965_primary_formats[] = {
  67         DRM_FORMAT_C8,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_XBGR8888,
  71         DRM_FORMAT_XRGB2101010,
  72         DRM_FORMAT_XBGR2101010,
  73 };
  74
  75 static const uint32_t skl_primary_formats[] = {
  76         DRM_FORMAT_C8,
  77         DRM_FORMAT_RGB565,
  78         DRM_FORMAT_XRGB8888,
  79         DRM_FORMAT_XBGR8888,
  80         DRM_FORMAT_ARGB8888,
  81         DRM_FORMAT_ABGR8888,
  82         DRM_FORMAT_XRGB2101010,
  83         DRM_FORMAT_XBGR2101010,
  84         DRM_FORMAT_YUYV,
  85         DRM_FORMAT_YVYU,
  86         DRM_FORMAT_UYVY,
  87         DRM_FORMAT_VYUY,
  88 };
  89
  90 /* Cursor formats */
  91 static const uint32_t intel_cursor_formats[] = {
  92         DRM_FORMAT_ARGB8888,
  93 };
  94
  95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
  96                                 struct intel_crtc_state *pipe_config);
  97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
  98                                    struct intel_crtc_state *pipe_config);
  99
 100 static int intel_framebuffer_init(struct intel_framebuffer *ifb,
 101                                   struct drm_i915_gem_object *obj,
 102                                   struct drm_mode_fb_cmd2 *mode_cmd);
 103 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
 104 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
 105 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
 106 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
 107                                          struct intel_link_m_n *m_n,
 108                                          struct intel_link_m_n *m2_n2);
 109 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
 110 static void haswell_set_pipeconf(struct drm_crtc *crtc);
 111 static void haswell_set_pipemisc(struct drm_crtc *crtc);
 112 static void vlv_prepare_pll(struct intel_crtc *crtc,
 113                             const struct intel_crtc_state *pipe_config);
 114 static void chv_prepare_pll(struct intel_crtc *crtc,
 115                             const struct intel_crtc_state *pipe_config);
 116 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 117 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
 118 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
 119                                     struct intel_crtc_state *crtc_state);
 120 static void skylake_pfit_enable(struct intel_crtc *crtc);
 121 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
 122 static void ironlake_pfit_enable(struct intel_crtc *crtc);
 123 static void intel_modeset_setup_hw_state(struct drm_device *dev);
 124 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
 125
 126 struct intel_limit {
 127         struct {
 128                 int min, max;
 129         } dot, vco, n, m, m1, m2, p, p1;
 130
 131         struct {
 132                 int dot_limit;
 133                 int p2_slow, p2_fast;
 134         } p2;
 135 };
 136
 137 /* returns HPLL frequency in kHz */
 138 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 139 {
 140         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 141
 142         /* Obtain SKU information */
 143         mutex_lock(&dev_priv->sb_lock);
 144         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 145                 CCK_FUSE_HPLL_FREQ_MASK;
 146         mutex_unlock(&dev_priv->sb_lock);
 147
 148         return vco_freq[hpll_freq] * 1000;
 149 }
 150
 151 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 152                       const char *name, u32 reg, int ref_freq)
 153 {
 154         u32 val;
 155         int divider;
 156
 157         mutex_lock(&dev_priv->sb_lock);
 158         val = vlv_cck_read(dev_priv, reg);
 159         mutex_unlock(&dev_priv->sb_lock);
 160
 161         divider = val & CCK_FREQUENCY_VALUES;
 162
 163         WARN((val & CCK_FREQUENCY_STATUS) !=
 164              (divider << CCK_FREQUENCY_STATUS_SHIFT),
 165              "%s change in progress\n", name);
 166
 167         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 168 }
 169
 170 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 171                            const char *name, u32 reg)
 172 {
 173         if (dev_priv->hpll_freq == 0)
 174                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 175
 176         return vlv_get_cck_clock(dev_priv, name, reg,
 177                                  dev_priv->hpll_freq);
 178 }
 179
 180 static void intel_update_czclk(struct drm_i915_private *dev_priv)
 181 {
 182         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 183                 return;
 184
 185         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 186                                                       CCK_CZ_CLOCK_CONTROL);
 187
 188         DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
 189 }
 190
 191 static inline u32 /* units of 100MHz */
 192 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
 193                     const struct intel_crtc_state *pipe_config)
 194 {
 195         if (HAS_DDI(dev_priv))
 196                 return pipe_config->port_clock; /* SPLL */
 197         else if (IS_GEN5(dev_priv))
 198                 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
 199         else
 200                 return 270000;
 201 }
 202
 203 static const struct intel_limit intel_limits_i8xx_dac = {
 204         .dot = { .min = 25000, .max = 350000 },
 205         .vco = { .min = 908000, .max = 1512000 },
 206         .n = { .min = 2, .max = 16 },
 207         .m = { .min = 96, .max = 140 },
 208         .m1 = { .min = 18, .max = 26 },
 209         .m2 = { .min = 6, .max = 16 },
 210         .p = { .min = 4, .max = 128 },
 211         .p1 = { .min = 2, .max = 33 },
 212         .p2 = { .dot_limit = 165000,
 213                 .p2_slow = 4, .p2_fast = 2 },
 214 };
 215
 216 static const struct intel_limit intel_limits_i8xx_dvo = {
 217         .dot = { .min = 25000, .max = 350000 },
 218         .vco = { .min = 908000, .max = 1512000 },
 219         .n = { .min = 2, .max = 16 },
 220         .m = { .min = 96, .max = 140 },
 221         .m1 = { .min = 18, .max = 26 },
 222         .m2 = { .min = 6, .max = 16 },
 223         .p = { .min = 4, .max = 128 },
 224         .p1 = { .min = 2, .max = 33 },
 225         .p2 = { .dot_limit = 165000,
 226                 .p2_slow = 4, .p2_fast = 4 },
 227 };
 228
 229 static const struct intel_limit intel_limits_i8xx_lvds = {
 230         .dot = { .min = 25000, .max = 350000 },
 231         .vco = { .min = 908000, .max = 1512000 },
 232         .n = { .min = 2, .max = 16 },
 233         .m = { .min = 96, .max = 140 },
 234         .m1 = { .min = 18, .max = 26 },
 235         .m2 = { .min = 6, .max = 16 },
 236         .p = { .min = 4, .max = 128 },
 237         .p1 = { .min = 1, .max = 6 },
 238         .p2 = { .dot_limit = 165000,
 239                 .p2_slow = 14, .p2_fast = 7 },
 240 };
 241
 242 static const struct intel_limit intel_limits_i9xx_sdvo = {
 243         .dot = { .min = 20000, .max = 400000 },
 244         .vco = { .min = 1400000, .max = 2800000 },
 245         .n = { .min = 1, .max = 6 },
 246         .m = { .min = 70, .max = 120 },
 247         .m1 = { .min = 8, .max = 18 },
 248         .m2 = { .min = 3, .max = 7 },
 249         .p = { .min = 5, .max = 80 },
 250         .p1 = { .min = 1, .max = 8 },
 251         .p2 = { .dot_limit = 200000,
 252                 .p2_slow = 10, .p2_fast = 5 },
 253 };
 254
 255 static const struct intel_limit intel_limits_i9xx_lvds = {
 256         .dot = { .min = 20000, .max = 400000 },
 257         .vco = { .min = 1400000, .max = 2800000 },
 258         .n = { .min = 1, .max = 6 },
 259         .m = { .min = 70, .max = 120 },
 260         .m1 = { .min = 8, .max = 18 },
 261         .m2 = { .min = 3, .max = 7 },
 262         .p = { .min = 7, .max = 98 },
 263         .p1 = { .min = 1, .max = 8 },
 264         .p2 = { .dot_limit = 112000,
 265                 .p2_slow = 14, .p2_fast = 7 },
 266 };
 267
 268
 269 static const struct intel_limit intel_limits_g4x_sdvo = {
 270         .dot = { .min = 25000, .max = 270000 },
 271         .vco = { .min = 1750000, .max = 3500000},
 272         .n = { .min = 1, .max = 4 },
 273         .m = { .min = 104, .max = 138 },
 274         .m1 = { .min = 17, .max = 23 },
 275         .m2 = { .min = 5, .max = 11 },
 276         .p = { .min = 10, .max = 30 },
 277         .p1 = { .min = 1, .max = 3},
 278         .p2 = { .dot_limit = 270000,
 279                 .p2_slow = 10,
 280                 .p2_fast = 10
 281         },
 282 };
 283
 284 static const struct intel_limit intel_limits_g4x_hdmi = {
 285         .dot = { .min = 22000, .max = 400000 },
 286         .vco = { .min = 1750000, .max = 3500000},
 287         .n = { .min = 1, .max = 4 },
 288         .m = { .min = 104, .max = 138 },
 289         .m1 = { .min = 16, .max = 23 },
 290         .m2 = { .min = 5, .max = 11 },
 291         .p = { .min = 5, .max = 80 },
 292         .p1 = { .min = 1, .max = 8},
 293         .p2 = { .dot_limit = 165000,
 294                 .p2_slow = 10, .p2_fast = 5 },
 295 };
 296
 297 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
 298         .dot = { .min = 20000, .max = 115000 },
 299         .vco = { .min = 1750000, .max = 3500000 },
 300         .n = { .min = 1, .max = 3 },
 301         .m = { .min = 104, .max = 138 },
 302         .m1 = { .min = 17, .max = 23 },
 303         .m2 = { .min = 5, .max = 11 },
 304         .p = { .min = 28, .max = 112 },
 305         .p1 = { .min = 2, .max = 8 },
 306         .p2 = { .dot_limit = 0,
 307                 .p2_slow = 14, .p2_fast = 14
 308         },
 309 };
 310
 311 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
 312         .dot = { .min = 80000, .max = 224000 },
 313         .vco = { .min = 1750000, .max = 3500000 },
 314         .n = { .min = 1, .max = 3 },
 315         .m = { .min = 104, .max = 138 },
 316         .m1 = { .min = 17, .max = 23 },
 317         .m2 = { .min = 5, .max = 11 },
 318         .p = { .min = 14, .max = 42 },
 319         .p1 = { .min = 2, .max = 6 },
 320         .p2 = { .dot_limit = 0,
 321                 .p2_slow = 7, .p2_fast = 7
 322         },
 323 };
 324
 325 static const struct intel_limit intel_limits_pineview_sdvo = {
 326         .dot = { .min = 20000, .max = 400000},
 327         .vco = { .min = 1700000, .max = 3500000 },
 328         /* Pineview's Ncounter is a ring counter */
 329         .n = { .min = 3, .max = 6 },
 330         .m = { .min = 2, .max = 256 },
 331         /* Pineview only has one combined m divider, which we treat as m2. */
 332         .m1 = { .min = 0, .max = 0 },
 333         .m2 = { .min = 0, .max = 254 },
 334         .p = { .min = 5, .max = 80 },
 335         .p1 = { .min = 1, .max = 8 },
 336         .p2 = { .dot_limit = 200000,
 337                 .p2_slow = 10, .p2_fast = 5 },
 338 };
 339
 340 static const struct intel_limit intel_limits_pineview_lvds = {
 341         .dot = { .min = 20000, .max = 400000 },
 342         .vco = { .min = 1700000, .max = 3500000 },
 343         .n = { .min = 3, .max = 6 },
 344         .m = { .min = 2, .max = 256 },
 345         .m1 = { .min = 0, .max = 0 },
 346         .m2 = { .min = 0, .max = 254 },
 347         .p = { .min = 7, .max = 112 },
 348         .p1 = { .min = 1, .max = 8 },
 349         .p2 = { .dot_limit = 112000,
 350                 .p2_slow = 14, .p2_fast = 14 },
 351 };
 352
 353 /* Ironlake / Sandybridge
 354  *
 355  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 356  * the range value for them is (actual_value - 2).
 357  */
 358 static const struct intel_limit intel_limits_ironlake_dac = {
 359         .dot = { .min = 25000, .max = 350000 },
 360         .vco = { .min = 1760000, .max = 3510000 },
 361         .n = { .min = 1, .max = 5 },
 362         .m = { .min = 79, .max = 127 },
 363         .m1 = { .min = 12, .max = 22 },
 364         .m2 = { .min = 5, .max = 9 },
 365         .p = { .min = 5, .max = 80 },
 366         .p1 = { .min = 1, .max = 8 },
 367         .p2 = { .dot_limit = 225000,
 368                 .p2_slow = 10, .p2_fast = 5 },
 369 };
 370
 371 static const struct intel_limit intel_limits_ironlake_single_lvds = {
 372         .dot = { .min = 25000, .max = 350000 },
 373         .vco = { .min = 1760000, .max = 3510000 },
 374         .n = { .min = 1, .max = 3 },
 375         .m = { .min = 79, .max = 118 },
 376         .m1 = { .min = 12, .max = 22 },
 377         .m2 = { .min = 5, .max = 9 },
 378         .p = { .min = 28, .max = 112 },
 379         .p1 = { .min = 2, .max = 8 },
 380         .p2 = { .dot_limit = 225000,
 381                 .p2_slow = 14, .p2_fast = 14 },
 382 };
 383
 384 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
 385         .dot = { .min = 25000, .max = 350000 },
 386         .vco = { .min = 1760000, .max = 3510000 },
 387         .n = { .min = 1, .max = 3 },
 388         .m = { .min = 79, .max = 127 },
 389         .m1 = { .min = 12, .max = 22 },
 390         .m2 = { .min = 5, .max = 9 },
 391         .p = { .min = 14, .max = 56 },
 392         .p1 = { .min = 2, .max = 8 },
 393         .p2 = { .dot_limit = 225000,
 394                 .p2_slow = 7, .p2_fast = 7 },
 395 };
 396
 397 /* LVDS 100mhz refclk limits. */
 398 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
 399         .dot = { .min = 25000, .max = 350000 },
 400         .vco = { .min = 1760000, .max = 3510000 },
 401         .n = { .min = 1, .max = 2 },
 402         .m = { .min = 79, .max = 126 },
 403         .m1 = { .min = 12, .max = 22 },
 404         .m2 = { .min = 5, .max = 9 },
 405         .p = { .min = 28, .max = 112 },
 406         .p1 = { .min = 2, .max = 8 },
 407         .p2 = { .dot_limit = 225000,
 408                 .p2_slow = 14, .p2_fast = 14 },
 409 };
 410
 411 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
 412         .dot = { .min = 25000, .max = 350000 },
 413         .vco = { .min = 1760000, .max = 3510000 },
 414         .n = { .min = 1, .max = 3 },
 415         .m = { .min = 79, .max = 126 },
 416         .m1 = { .min = 12, .max = 22 },
 417         .m2 = { .min = 5, .max = 9 },
 418         .p = { .min = 14, .max = 42 },
 419         .p1 = { .min = 2, .max = 6 },
 420         .p2 = { .dot_limit = 225000,
 421                 .p2_slow = 7, .p2_fast = 7 },
 422 };
 423
 424 static const struct intel_limit intel_limits_vlv = {
 425          /*
 426           * These are the data rate limits (measured in fast clocks)
 427           * since those are the strictest limits we have. The fast
 428           * clock and actual rate limits are more relaxed, so checking
 429           * them would make no difference.
 430           */
 431         .dot = { .min = 25000 * 5, .max = 270000 * 5 },
 432         .vco = { .min = 4000000, .max = 6000000 },
 433         .n = { .min = 1, .max = 7 },
 434         .m1 = { .min = 2, .max = 3 },
 435         .m2 = { .min = 11, .max = 156 },
 436         .p1 = { .min = 2, .max = 3 },
 437         .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
 438 };
 439
 440 static const struct intel_limit intel_limits_chv = {
 441         /*
 442          * These are the data rate limits (measured in fast clocks)
 443          * since those are the strictest limits we have.  The fast
 444          * clock and actual rate limits are more relaxed, so checking
 445          * them would make no difference.
 446          */
 447         .dot = { .min = 25000 * 5, .max = 540000 * 5},
 448         .vco = { .min = 4800000, .max = 6480000 },
 449         .n = { .min = 1, .max = 1 },
 450         .m1 = { .min = 2, .max = 2 },
 451         .m2 = { .min = 24 << 22, .max = 175 << 22 },
 452         .p1 = { .min = 2, .max = 4 },
 453         .p2 = { .p2_slow = 1, .p2_fast = 14 },
 454 };
 455
 456 static const struct intel_limit intel_limits_bxt = {
 457         /* FIXME: find real dot limits */
 458         .dot = { .min = 0, .max = INT_MAX },
 459         .vco = { .min = 4800000, .max = 6700000 },
 460         .n = { .min = 1, .max = 1 },
 461         .m1 = { .min = 2, .max = 2 },
 462         /* FIXME: find real m2 limits */
 463         .m2 = { .min = 2 << 22, .max = 255 << 22 },
 464         .p1 = { .min = 2, .max = 4 },
 465         .p2 = { .p2_slow = 1, .p2_fast = 20 },
 466 };
 467
 468 static bool
 469 needs_modeset(struct drm_crtc_state *state)
 470 {
 471         return drm_atomic_crtc_needs_modeset(state);
 472 }
 473
 474 /*
 475  * Platform specific helpers to calculate the port PLL loopback- (clock.m),
 476  * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
 477  * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
 478  * The helpers' return value is the rate of the clock that is fed to the
 479  * display engine's pipe which can be the above fast dot clock rate or a
 480  * divided-down version of it.
 481  */
 482 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 483 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
 484 {
 485         clock->m = clock->m2 + 2;
 486         clock->p = clock->p1 * clock->p2;
 487         if (WARN_ON(clock->n == 0 || clock->p == 0))
 488                 return 0;
 489         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 490         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 491
 492         return clock->dot;
 493 }
 494
 495 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 496 {
 497         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 498 }
 499
 500 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
 501 {
 502         clock->m = i9xx_dpll_compute_m(clock);
 503         clock->p = clock->p1 * clock->p2;
 504         if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
 505                 return 0;
 506         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
 507         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 508
 509         return clock->dot;
 510 }
 511
 512 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
 513 {
 514         clock->m = clock->m1 * clock->m2;
 515         clock->p = clock->p1 * clock->p2;
 516         if (WARN_ON(clock->n == 0 || clock->p == 0))
 517                 return 0;
 518         clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
 519         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 520
 521         return clock->dot / 5;
 522 }
 523
 524 int chv_calc_dpll_params(int refclk, struct dpll *clock)
 525 {
 526         clock->m = clock->m1 * clock->m2;
 527         clock->p = clock->p1 * clock->p2;
 528         if (WARN_ON(clock->n == 0 || clock->p == 0))
 529                 return 0;
 530         clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
 531                         clock->n << 22);
 532         clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
 533
 534         return clock->dot / 5;
 535 }
 536
 537 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 538 /**
 539  * Returns whether the given set of divisors are valid for a given refclk with
 540  * the given connectors.
 541  */
 542
 543 static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
 544                                const struct intel_limit *limit,
 545                                const struct dpll *clock)
 546 {
 547         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 548                 INTELPllInvalid("n out of range\n");
 549         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 550                 INTELPllInvalid("p1 out of range\n");
 551         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 552                 INTELPllInvalid("m2 out of range\n");
 553         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 554                 INTELPllInvalid("m1 out of range\n");
 555
 556         if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
 557             !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
 558                 if (clock->m1 <= clock->m2)
 559                         INTELPllInvalid("m1 <= m2\n");
 560
 561         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 562             !IS_GEN9_LP(dev_priv)) {
 563                 if (clock->p < limit->p.min || limit->p.max < clock->p)
 564                         INTELPllInvalid("p out of range\n");
 565                 if (clock->m < limit->m.min || limit->m.max < clock->m)
 566                         INTELPllInvalid("m out of range\n");
 567         }
 568
 569         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 570                 INTELPllInvalid("vco out of range\n");
 571         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 572          * connector, etc., rather than just a single range.
 573          */
 574         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 575                 INTELPllInvalid("dot out of range\n");
 576
 577         return true;
 578 }
 579
 580 static int
 581 i9xx_select_p2_div(const struct intel_limit *limit,
 582                    const struct intel_crtc_state *crtc_state,
 583                    int target)
 584 {
 585         struct drm_device *dev = crtc_state->base.crtc->dev;
 586
 587         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         return limit->p2.p2_fast;
 595                 else
 596                         return limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         return limit->p2.p2_slow;
 600                 else
 601                         return limit->p2.p2_fast;
 602         }
 603 }
 604
 605 /*
 606  * Returns a set of divisors for the desired target clock with the given
 607  * refclk, or FALSE.  The returned values represent the clock equation:
 608  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 609  *
 610  * Target and reference clocks are specified in kHz.
 611  *
 612  * If match_clock is provided, then best_clock P divider must match the P
 613  * divider from @match_clock used for LVDS downclocking.
 614  */
 615 static bool
 616 i9xx_find_best_dpll(const struct intel_limit *limit,
 617                     struct intel_crtc_state *crtc_state,
 618                     int target, int refclk, struct dpll *match_clock,
 619                     struct dpll *best_clock)
 620 {
 621         struct drm_device *dev = crtc_state->base.crtc->dev;
 622         struct dpll clock;
 623         int err = target;
 624
 625         memset(best_clock, 0, sizeof(*best_clock));
 626
 627         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 628
 629         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 630              clock.m1++) {
 631                 for (clock.m2 = limit->m2.min;
 632                      clock.m2 <= limit->m2.max; clock.m2++) {
 633                         if (clock.m2 >= clock.m1)
 634                                 break;
 635                         for (clock.n = limit->n.min;
 636                              clock.n <= limit->n.max; clock.n++) {
 637                                 for (clock.p1 = limit->p1.min;
 638                                         clock.p1 <= limit->p1.max; clock.p1++) {
 639                                         int this_err;
 640
 641                                         i9xx_calc_dpll_params(refclk, &clock);
 642                                         if (!intel_PLL_is_valid(to_i915(dev),
 643                                                                 limit,
 644                                                                 &clock))
 645                                                 continue;
 646                                         if (match_clock &&
 647                                             clock.p != match_clock->p)
 648                                                 continue;
 649
 650                                         this_err = abs(clock.dot - target);
 651                                         if (this_err < err) {
 652                                                 *best_clock = clock;
 653                                                 err = this_err;
 654                                         }
 655                                 }
 656                         }
 657                 }
 658         }
 659
 660         return (err != target);
 661 }
 662
 663 /*
 664  * Returns a set of divisors for the desired target clock with the given
 665  * refclk, or FALSE.  The returned values represent the clock equation:
 666  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 667  *
 668  * Target and reference clocks are specified in kHz.
 669  *
 670  * If match_clock is provided, then best_clock P divider must match the P
 671  * divider from @match_clock used for LVDS downclocking.
 672  */
 673 static bool
 674 pnv_find_best_dpll(const struct intel_limit *limit,
 675                    struct intel_crtc_state *crtc_state,
 676                    int target, int refclk, struct dpll *match_clock,
 677                    struct dpll *best_clock)
 678 {
 679         struct drm_device *dev = crtc_state->base.crtc->dev;
 680         struct dpll clock;
 681         int err = target;
 682
 683         memset(best_clock, 0, sizeof(*best_clock));
 684
 685         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 686
 687         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 688              clock.m1++) {
 689                 for (clock.m2 = limit->m2.min;
 690                      clock.m2 <= limit->m2.max; clock.m2++) {
 691                         for (clock.n = limit->n.min;
 692                              clock.n <= limit->n.max; clock.n++) {
 693                                 for (clock.p1 = limit->p1.min;
 694                                         clock.p1 <= limit->p1.max; clock.p1++) {
 695                                         int this_err;
 696
 697                                         pnv_calc_dpll_params(refclk, &clock);
 698                                         if (!intel_PLL_is_valid(to_i915(dev),
 699                                                                 limit,
 700                                                                 &clock))
 701                                                 continue;
 702                                         if (match_clock &&
 703                                             clock.p != match_clock->p)
 704                                                 continue;
 705
 706                                         this_err = abs(clock.dot - target);
 707                                         if (this_err < err) {
 708                                                 *best_clock = clock;
 709                                                 err = this_err;
 710                                         }
 711                                 }
 712                         }
 713                 }
 714         }
 715
 716         return (err != target);
 717 }
 718
 719 /*
 720  * Returns a set of divisors for the desired target clock with the given
 721  * refclk, or FALSE.  The returned values represent the clock equation:
 722  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 723  *
 724  * Target and reference clocks are specified in kHz.
 725  *
 726  * If match_clock is provided, then best_clock P divider must match the P
 727  * divider from @match_clock used for LVDS downclocking.
 728  */
 729 static bool
 730 g4x_find_best_dpll(const struct intel_limit *limit,
 731                    struct intel_crtc_state *crtc_state,
 732                    int target, int refclk, struct dpll *match_clock,
 733                    struct dpll *best_clock)
 734 {
 735         struct drm_device *dev = crtc_state->base.crtc->dev;
 736         struct dpll clock;
 737         int max_n;
 738         bool found = false;
 739         /* approximately equals target * 0.00585 */
 740         int err_most = (target >> 8) + (target >> 9);
 741
 742         memset(best_clock, 0, sizeof(*best_clock));
 743
 744         clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
 745
 746         max_n = limit->n.max;
 747         /* based on hardware requirement, prefer smaller n to precision */
 748         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 749                 /* based on hardware requirement, prefere larger m1,m2 */
 750                 for (clock.m1 = limit->m1.max;
 751                      clock.m1 >= limit->m1.min; clock.m1--) {
 752                         for (clock.m2 = limit->m2.max;
 753                              clock.m2 >= limit->m2.min; clock.m2--) {
 754                                 for (clock.p1 = limit->p1.max;
 755                                      clock.p1 >= limit->p1.min; clock.p1--) {
 756                                         int this_err;
 757
 758                                         i9xx_calc_dpll_params(refclk, &clock);
 759                                         if (!intel_PLL_is_valid(to_i915(dev),
 760                                                                 limit,
 761                                                                 &clock))
 762                                                 continue;
 763
 764                                         this_err = abs(clock.dot - target);
 765                                         if (this_err < err_most) {
 766                                                 *best_clock = clock;
 767                                                 err_most = this_err;
 768                                                 max_n = clock.n;
 769                                                 found = true;
 770                                         }
 771                                 }
 772                         }
 773                 }
 774         }
 775         return found;
 776 }
 777
 778 /*
 779  * Check if the calculated PLL configuration is more optimal compared to the
 780  * best configuration and error found so far. Return the calculated error.
 781  */
 782 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
 783                                const struct dpll *calculated_clock,
 784                                const struct dpll *best_clock,
 785                                unsigned int best_error_ppm,
 786                                unsigned int *error_ppm)
 787 {
 788         /*
 789          * For CHV ignore the error and consider only the P value.
 790          * Prefer a bigger P value based on HW requirements.
 791          */
 792         if (IS_CHERRYVIEW(to_i915(dev))) {
 793                 *error_ppm = 0;
 794
 795                 return calculated_clock->p > best_clock->p;
 796         }
 797
 798         if (WARN_ON_ONCE(!target_freq))
 799                 return false;
 800
 801         *error_ppm = div_u64(1000000ULL *
 802                                 abs(target_freq - calculated_clock->dot),
 803                              target_freq);
 804         /*
 805          * Prefer a better P value over a better (smaller) error if the error
 806          * is small. Ensure this preference for future configurations too by
 807          * setting the error to 0.
 808          */
 809         if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
 810                 *error_ppm = 0;
 811
 812                 return true;
 813         }
 814
 815         return *error_ppm + 10 < best_error_ppm;
 816 }
 817
 818 /*
 819  * Returns a set of divisors for the desired target clock with the given
 820  * refclk, or FALSE.  The returned values represent the clock equation:
 821  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 822  */
 823 static bool
 824 vlv_find_best_dpll(const struct intel_limit *limit,
 825                    struct intel_crtc_state *crtc_state,
 826                    int target, int refclk, struct dpll *match_clock,
 827                    struct dpll *best_clock)
 828 {
 829         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 830         struct drm_device *dev = crtc->base.dev;
 831         struct dpll clock;
 832         unsigned int bestppm = 1000000;
 833         /* min update 19.2 MHz */
 834         int max_n = min(limit->n.max, refclk / 19200);
 835         bool found = false;
 836
 837         target *= 5; /* fast clock */
 838
 839         memset(best_clock, 0, sizeof(*best_clock));
 840
 841         /* based on hardware requirement, prefer smaller n to precision */
 842         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 843                 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 844                         for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
 845                              clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 846                                 clock.p = clock.p1 * clock.p2;
 847                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 848                                 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 849                                         unsigned int ppm;
 850
 851                                         clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
 852                                                                      refclk * clock.m1);
 853
 854                                         vlv_calc_dpll_params(refclk, &clock);
 855
 856                                         if (!intel_PLL_is_valid(to_i915(dev),
 857                                                                 limit,
 858                                                                 &clock))
 859                                                 continue;
 860
 861                                         if (!vlv_PLL_is_optimal(dev, target,
 862                                                                 &clock,
 863                                                                 best_clock,
 864                                                                 bestppm, &ppm))
 865                                                 continue;
 866
 867                                         *best_clock = clock;
 868                                         bestppm = ppm;
 869                                         found = true;
 870                                 }
 871                         }
 872                 }
 873         }
 874
 875         return found;
 876 }
 877
 878 /*
 879  * Returns a set of divisors for the desired target clock with the given
 880  * refclk, or FALSE.  The returned values represent the clock equation:
 881  * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
 882  */
 883 static bool
 884 chv_find_best_dpll(const struct intel_limit *limit,
 885                    struct intel_crtc_state *crtc_state,
 886                    int target, int refclk, struct dpll *match_clock,
 887                    struct dpll *best_clock)
 888 {
 889         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
 890         struct drm_device *dev = crtc->base.dev;
 891         unsigned int best_error_ppm;
 892         struct dpll clock;
 893         uint64_t m2;
 894         int found = false;
 895
 896         memset(best_clock, 0, sizeof(*best_clock));
 897         best_error_ppm = 1000000;
 898
 899         /*
 900          * Based on hardware doc, the n always set to 1, and m1 always
 901          * set to 2.  If requires to support 200Mhz refclk, we need to
 902          * revisit this because n may not 1 anymore.
 903          */
 904         clock.n = 1, clock.m1 = 2;
 905         target *= 5;    /* fast clock */
 906
 907         for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
 908                 for (clock.p2 = limit->p2.p2_fast;
 909                                 clock.p2 >= limit->p2.p2_slow;
 910                                 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
 911                         unsigned int error_ppm;
 912
 913                         clock.p = clock.p1 * clock.p2;
 914
 915                         m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
 916                                         clock.n) << 22, refclk * clock.m1);
 917
 918                         if (m2 > INT_MAX/clock.m1)
 919                                 continue;
 920
 921                         clock.m2 = m2;
 922
 923                         chv_calc_dpll_params(refclk, &clock);
 924
 925                         if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
 926                                 continue;
 927
 928                         if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
 929                                                 best_error_ppm, &error_ppm))
 930                                 continue;
 931
 932                         *best_clock = clock;
 933                         best_error_ppm = error_ppm;
 934                         found = true;
 935                 }
 936         }
 937
 938         return found;
 939 }
 940
 941 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
 942                         struct dpll *best_clock)
 943 {
 944         int refclk = 100000;
 945         const struct intel_limit *limit = &intel_limits_bxt;
 946
 947         return chv_find_best_dpll(limit, crtc_state,
 948                                   target_clock, refclk, NULL, best_clock);
 949 }
 950
 951 bool intel_crtc_active(struct intel_crtc *crtc)
 952 {
 953         /* Be paranoid as we can arrive here with only partial
 954          * state retrieved from the hardware during setup.
 955          *
 956          * We can ditch the adjusted_mode.crtc_clock check as soon
 957          * as Haswell has gained clock readout/fastboot support.
 958          *
 959          * We can ditch the crtc->primary->fb check as soon as we can
 960          * properly reconstruct framebuffers.
 961          *
 962          * FIXME: The intel_crtc->active here should be switched to
 963          * crtc->state->active once we have proper CRTC states wired up
 964          * for atomic.
 965          */
 966         return crtc->active && crtc->base.primary->state->fb &&
 967                 crtc->config->base.adjusted_mode.crtc_clock;
 968 }
 969
 970 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 971                                              enum pipe pipe)
 972 {
 973         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 974
 975         return crtc->config->cpu_transcoder;
 976 }
 977
 978 static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
 979 {
 980         i915_reg_t reg = PIPEDSL(pipe);
 981         u32 line1, line2;
 982         u32 line_mask;
 983
 984         if (IS_GEN2(dev_priv))
 985                 line_mask = DSL_LINEMASK_GEN2;
 986         else
 987                 line_mask = DSL_LINEMASK_GEN3;
 988
 989         line1 = I915_READ(reg) & line_mask;
 990         msleep(5);
 991         line2 = I915_READ(reg) & line_mask;
 992
 993         return line1 == line2;
 994 }
 995
 996 /*
 997  * intel_wait_for_pipe_off - wait for pipe to turn off
 998  * @crtc: crtc whose pipe to wait for
 999  *
1000  * After disabling a pipe, we can't wait for vblank in the usual way,
1001  * spinning on the vblank interrupt status bit, since we won't actually
1002  * see an interrupt when the pipe is disabled.
1003  *
1004  * On Gen4 and above:
1005  *   wait for the pipe register state bit to turn off
1006  *
1007  * Otherwise:
1008  *   wait for the display line value to settle (it usually
1009  *   ends up stopping at the start of the next frame).
1010  *
1011  */
1012 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1013 {
1014         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1015         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1016         enum pipe pipe = crtc->pipe;
1017
1018         if (INTEL_GEN(dev_priv) >= 4) {
1019                 i915_reg_t reg = PIPECONF(cpu_transcoder);
1020
1021                 /* Wait for the Pipe State to go off */
1022                 if (intel_wait_for_register(dev_priv,
1023                                             reg, I965_PIPECONF_ACTIVE, 0,
1024                                             100))
1025                         WARN(1, "pipe_off wait timed out\n");
1026         } else {
1027                 /* Wait for the display line to settle */
1028                 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
1029                         WARN(1, "pipe_off wait timed out\n");
1030         }
1031 }
1032
1033 /* Only for pre-ILK configs */
1034 void assert_pll(struct drm_i915_private *dev_priv,
1035                 enum pipe pipe, bool state)
1036 {
1037         u32 val;
1038         bool cur_state;
1039
1040         val = I915_READ(DPLL(pipe));
1041         cur_state = !!(val & DPLL_VCO_ENABLE);
1042         I915_STATE_WARN(cur_state != state,
1043              "PLL state assertion failure (expected %s, current %s)\n",
1044                         onoff(state), onoff(cur_state));
1045 }
1046
1047 /* XXX: the dsi pll is shared between MIPI DSI ports */
1048 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1049 {
1050         u32 val;
1051         bool cur_state;
1052
1053         mutex_lock(&dev_priv->sb_lock);
1054         val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1055         mutex_unlock(&dev_priv->sb_lock);
1056
1057         cur_state = val & DSI_PLL_VCO_EN;
1058         I915_STATE_WARN(cur_state != state,
1059              "DSI PLL state assertion failure (expected %s, current %s)\n",
1060                         onoff(state), onoff(cur_state));
1061 }
1062
1063 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1064                           enum pipe pipe, bool state)
1065 {
1066         bool cur_state;
1067         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1068                                                                       pipe);
1069
1070         if (HAS_DDI(dev_priv)) {
1071                 /* DDI does not have a specific FDI_TX register */
1072                 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1073                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1074         } else {
1075                 u32 val = I915_READ(FDI_TX_CTL(pipe));
1076                 cur_state = !!(val & FDI_TX_ENABLE);
1077         }
1078         I915_STATE_WARN(cur_state != state,
1079              "FDI TX state assertion failure (expected %s, current %s)\n",
1080                         onoff(state), onoff(cur_state));
1081 }
1082 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086                           enum pipe pipe, bool state)
1087 {
1088         u32 val;
1089         bool cur_state;
1090
1091         val = I915_READ(FDI_RX_CTL(pipe));
1092         cur_state = !!(val & FDI_RX_ENABLE);
1093         I915_STATE_WARN(cur_state != state,
1094              "FDI RX state assertion failure (expected %s, current %s)\n",
1095                         onoff(state), onoff(cur_state));
1096 }
1097 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1098 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1099
1100 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1101                                       enum pipe pipe)
1102 {
1103         u32 val;
1104
1105         /* ILK FDI PLL is always enabled */
1106         if (IS_GEN5(dev_priv))
1107                 return;
1108
1109         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1110         if (HAS_DDI(dev_priv))
1111                 return;
1112
1113         val = I915_READ(FDI_TX_CTL(pipe));
1114         I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1115 }
1116
1117 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1118                        enum pipe pipe, bool state)
1119 {
1120         u32 val;
1121         bool cur_state;
1122
1123         val = I915_READ(FDI_RX_CTL(pipe));
1124         cur_state = !!(val & FDI_RX_PLL_ENABLE);
1125         I915_STATE_WARN(cur_state != state,
1126              "FDI RX PLL assertion failure (expected %s, current %s)\n",
1127                         onoff(state), onoff(cur_state));
1128 }
1129
1130 void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
1131 {
1132         i915_reg_t pp_reg;
1133         u32 val;
1134         enum pipe panel_pipe = PIPE_A;
1135         bool locked = true;
1136
1137         if (WARN_ON(HAS_DDI(dev_priv)))
1138                 return;
1139
1140         if (HAS_PCH_SPLIT(dev_priv)) {
1141                 u32 port_sel;
1142
1143                 pp_reg = PP_CONTROL(0);
1144                 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1145
1146                 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1147                     I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1148                         panel_pipe = PIPE_B;
1149                 /* XXX: else fix for eDP */
1150         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1151                 /* presumably write lock depends on pipe, not port select */
1152                 pp_reg = PP_CONTROL(pipe);
1153                 panel_pipe = pipe;
1154         } else {
1155                 pp_reg = PP_CONTROL(0);
1156                 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1157                         panel_pipe = PIPE_B;
1158         }
1159
1160         val = I915_READ(pp_reg);
1161         if (!(val & PANEL_POWER_ON) ||
1162             ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1163                 locked = false;
1164
1165         I915_STATE_WARN(panel_pipe == pipe && locked,
1166              "panel assertion failure, pipe %c regs locked\n",
1167              pipe_name(pipe));
1168 }
1169
1170 static void assert_cursor(struct drm_i915_private *dev_priv,
1171                           enum pipe pipe, bool state)
1172 {
1173         bool cur_state;
1174
1175         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
1176                 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1177         else
1178                 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1179
1180         I915_STATE_WARN(cur_state != state,
1181              "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1182                         pipe_name(pipe), onoff(state), onoff(cur_state));
1183 }
1184 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1185 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1186
1187 void assert_pipe(struct drm_i915_private *dev_priv,
1188                  enum pipe pipe, bool state)
1189 {
1190         bool cur_state;
1191         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192                                                                       pipe);
1193         enum intel_display_power_domain power_domain;
1194
1195         /* if we need the pipe quirk it must be always on */
1196         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1197             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1198                 state = true;
1199
1200         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1202                 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1203                 cur_state = !!(val & PIPECONF_ENABLE);
1204
1205                 intel_display_power_put(dev_priv, power_domain);
1206         } else {
1207                 cur_state = false;
1208         }
1209
1210         I915_STATE_WARN(cur_state != state,
1211              "pipe %c assertion failure (expected %s, current %s)\n",
1212                         pipe_name(pipe), onoff(state), onoff(cur_state));
1213 }
1214
1215 static void assert_plane(struct drm_i915_private *dev_priv,
1216                          enum plane plane, bool state)
1217 {
1218         u32 val;
1219         bool cur_state;
1220
1221         val = I915_READ(DSPCNTR(plane));
1222         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1223         I915_STATE_WARN(cur_state != state,
1224              "plane %c assertion failure (expected %s, current %s)\n",
1225                         plane_name(plane), onoff(state), onoff(cur_state));
1226 }
1227
1228 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
1231 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232                                    enum pipe pipe)
1233 {
1234         int i;
1235
1236         /* Primary planes are fixed to pipes on gen4+ */
1237         if (INTEL_GEN(dev_priv) >= 4) {
1238                 u32 val = I915_READ(DSPCNTR(pipe));
1239                 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1240                      "plane %c assertion failure, should be disabled but not\n",
1241                      plane_name(pipe));
1242                 return;
1243         }
1244
1245         /* Need to check both planes against the pipe */
1246         for_each_pipe(dev_priv, i) {
1247                 u32 val = I915_READ(DSPCNTR(i));
1248                 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1249                         DISPPLANE_SEL_PIPE_SHIFT;
1250                 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1251                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252                      plane_name(i), pipe_name(pipe));
1253         }
1254 }
1255
1256 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257                                     enum pipe pipe)
1258 {
1259         int sprite;
1260
1261         if (INTEL_GEN(dev_priv) >= 9) {
1262                 for_each_sprite(dev_priv, pipe, sprite) {
1263                         u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1264                         I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1265                              "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266                              sprite, pipe_name(pipe));
1267                 }
1268         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1269                 for_each_sprite(dev_priv, pipe, sprite) {
1270                         u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
1271                         I915_STATE_WARN(val & SP_ENABLE,
1272                              "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1273                              sprite_name(pipe, sprite), pipe_name(pipe));
1274                 }
1275         } else if (INTEL_GEN(dev_priv) >= 7) {
1276                 u32 val = I915_READ(SPRCTL(pipe));
1277                 I915_STATE_WARN(val & SPRITE_ENABLE,
1278                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1279                      plane_name(pipe), pipe_name(pipe));
1280         } else if (INTEL_GEN(dev_priv) >= 5) {
1281                 u32 val = I915_READ(DVSCNTR(pipe));
1282                 I915_STATE_WARN(val & DVS_ENABLE,
1283                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1284                      plane_name(pipe), pipe_name(pipe));
1285         }
1286 }
1287
1288 static void assert_vblank_disabled(struct drm_crtc *crtc)
1289 {
1290         if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1291                 drm_crtc_vblank_put(crtc);
1292 }
1293
1294 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295                                     enum pipe pipe)
1296 {
1297         u32 val;
1298         bool enabled;
1299
1300         val = I915_READ(PCH_TRANSCONF(pipe));
1301         enabled = !!(val & TRANS_ENABLE);
1302         I915_STATE_WARN(enabled,
1303              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304              pipe_name(pipe));
1305 }
1306
1307 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308                             enum pipe pipe, u32 port_sel, u32 val)
1309 {
1310         if ((val & DP_PORT_EN) == 0)
1311                 return false;
1312
1313         if (HAS_PCH_CPT(dev_priv)) {
1314                 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1315                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316                         return false;
1317         } else if (IS_CHERRYVIEW(dev_priv)) {
1318                 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319                         return false;
1320         } else {
1321                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322                         return false;
1323         }
1324         return true;
1325 }
1326
1327 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328                               enum pipe pipe, u32 val)
1329 {
1330         if ((val & SDVO_ENABLE) == 0)
1331                 return false;
1332
1333         if (HAS_PCH_CPT(dev_priv)) {
1334                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1335                         return false;
1336         } else if (IS_CHERRYVIEW(dev_priv)) {
1337                 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338                         return false;
1339         } else {
1340                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1341                         return false;
1342         }
1343         return true;
1344 }
1345
1346 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347                               enum pipe pipe, u32 val)
1348 {
1349         if ((val & LVDS_PORT_EN) == 0)
1350                 return false;
1351
1352         if (HAS_PCH_CPT(dev_priv)) {
1353                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354                         return false;
1355         } else {
1356                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357                         return false;
1358         }
1359         return true;
1360 }
1361
1362 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363                               enum pipe pipe, u32 val)
1364 {
1365         if ((val & ADPA_DAC_ENABLE) == 0)
1366                 return false;
1367         if (HAS_PCH_CPT(dev_priv)) {
1368                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369                         return false;
1370         } else {
1371                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372                         return false;
1373         }
1374         return true;
1375 }
1376
1377 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1378                                    enum pipe pipe, i915_reg_t reg,
1379                                    u32 port_sel)
1380 {
1381         u32 val = I915_READ(reg);
1382         I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1383              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1384              i915_mmio_reg_offset(reg), pipe_name(pipe));
1385
1386         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1387              && (val & DP_PIPEB_SELECT),
1388              "IBX PCH dp port still using transcoder B\n");
1389 }
1390
1391 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1392                                      enum pipe pipe, i915_reg_t reg)
1393 {
1394         u32 val = I915_READ(reg);
1395         I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1396              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1397              i915_mmio_reg_offset(reg), pipe_name(pipe));
1398
1399         I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1400              && (val & SDVO_PIPE_B_SELECT),
1401              "IBX PCH hdmi port still using transcoder B\n");
1402 }
1403
1404 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405                                       enum pipe pipe)
1406 {
1407         u32 val;
1408
1409         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1412
1413         val = I915_READ(PCH_ADPA);
1414         I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1415              "PCH VGA enabled on transcoder %c, should be disabled\n",
1416              pipe_name(pipe));
1417
1418         val = I915_READ(PCH_LVDS);
1419         I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1420              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1421              pipe_name(pipe));
1422
1423         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1426 }
1427
1428 static void _vlv_enable_pll(struct intel_crtc *crtc,
1429                             const struct intel_crtc_state *pipe_config)
1430 {
1431         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432         enum pipe pipe = crtc->pipe;
1433
1434         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435         POSTING_READ(DPLL(pipe));
1436         udelay(150);
1437
1438         if (intel_wait_for_register(dev_priv,
1439                                     DPLL(pipe),
1440                                     DPLL_LOCK_VLV,
1441                                     DPLL_LOCK_VLV,
1442                                     1))
1443                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444 }
1445
1446 static void vlv_enable_pll(struct intel_crtc *crtc,
1447                            const struct intel_crtc_state *pipe_config)
1448 {
1449         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1450         enum pipe pipe = crtc->pipe;
1451
1452         assert_pipe_disabled(dev_priv, pipe);
1453
1454         /* PLL is protected by panel, make sure we can write it */
1455         assert_panel_unlocked(dev_priv, pipe);
1456
1457         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458                 _vlv_enable_pll(crtc, pipe_config);
1459
1460         I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461         POSTING_READ(DPLL_MD(pipe));
1462 }
1463
1464
1465 static void _chv_enable_pll(struct intel_crtc *crtc,
1466                             const struct intel_crtc_state *pipe_config)
1467 {
1468         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1469         enum pipe pipe = crtc->pipe;
1470         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1471         u32 tmp;
1472
1473         mutex_lock(&dev_priv->sb_lock);
1474
1475         /* Enable back the 10bit clock to display controller */
1476         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477         tmp |= DPIO_DCLKP_EN;
1478         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
1480         mutex_unlock(&dev_priv->sb_lock);
1481
1482         /*
1483          * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484          */
1485         udelay(1);
1486
1487         /* Enable PLL */
1488         I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1489
1490         /* Check PLL is locked */
1491         if (intel_wait_for_register(dev_priv,
1492                                     DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493                                     1))
1494                 DRM_ERROR("PLL %d failed to lock\n", pipe);
1495 }
1496
1497 static void chv_enable_pll(struct intel_crtc *crtc,
1498                            const struct intel_crtc_state *pipe_config)
1499 {
1500         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501         enum pipe pipe = crtc->pipe;
1502
1503         assert_pipe_disabled(dev_priv, pipe);
1504
1505         /* PLL is protected by panel, make sure we can write it */
1506         assert_panel_unlocked(dev_priv, pipe);
1507
1508         if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509                 _chv_enable_pll(crtc, pipe_config);
1510
1511         if (pipe != PIPE_A) {
1512                 /*
1513                  * WaPixelRepeatModeFixForC0:chv
1514                  *
1515                  * DPLLCMD is AWOL. Use chicken bits to propagate
1516                  * the value from DPLLBMD to either pipe B or C.
1517                  */
1518                 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519                 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520                 I915_WRITE(CBR4_VLV, 0);
1521                 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523                 /*
1524                  * DPLLB VGA mode also seems to cause problems.
1525                  * We should always have it disabled.
1526                  */
1527                 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528         } else {
1529                 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530                 POSTING_READ(DPLL_MD(pipe));
1531         }
1532 }
1533
1534 static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1535 {
1536         struct intel_crtc *crtc;
1537         int count = 0;
1538
1539         for_each_intel_crtc(&dev_priv->drm, crtc) {
1540                 count += crtc->base.state->active &&
1541                         intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542         }
1543
1544         return count;
1545 }
1546
1547 static void i9xx_enable_pll(struct intel_crtc *crtc)
1548 {
1549         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1550         i915_reg_t reg = DPLL(crtc->pipe);
1551         u32 dpll = crtc->config->dpll_hw_state.dpll;
1552
1553         assert_pipe_disabled(dev_priv, crtc->pipe);
1554
1555         /* PLL is protected by panel, make sure we can write it */
1556         if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
1557                 assert_panel_unlocked(dev_priv, crtc->pipe);
1558
1559         /* Enable DVO 2x clock on both PLLs if necessary */
1560         if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1561                 /*
1562                  * It appears to be important that we don't enable this
1563                  * for the current pipe before otherwise configuring the
1564                  * PLL. No idea how this should be handled if multiple
1565                  * DVO outputs are enabled simultaneosly.
1566                  */
1567                 dpll |= DPLL_DVO_2X_MODE;
1568                 I915_WRITE(DPLL(!crtc->pipe),
1569                            I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1570         }
1571
1572         /*
1573          * Apparently we need to have VGA mode enabled prior to changing
1574          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1575          * dividers, even though the register value does change.
1576          */
1577         I915_WRITE(reg, 0);
1578
1579         I915_WRITE(reg, dpll);
1580
1581         /* Wait for the clocks to stabilize. */
1582         POSTING_READ(reg);
1583         udelay(150);
1584
1585         if (INTEL_GEN(dev_priv) >= 4) {
1586                 I915_WRITE(DPLL_MD(crtc->pipe),
1587                            crtc->config->dpll_hw_state.dpll_md);
1588         } else {
1589                 /* The pixel multiplier can only be updated once the
1590                  * DPLL is enabled and the clocks are stable.
1591                  *
1592                  * So write it again.
1593                  */
1594                 I915_WRITE(reg, dpll);
1595         }
1596
1597         /* We do this three times for luck */
1598         I915_WRITE(reg, dpll);
1599         POSTING_READ(reg);
1600         udelay(150); /* wait for warmup */
1601         I915_WRITE(reg, dpll);
1602         POSTING_READ(reg);
1603         udelay(150); /* wait for warmup */
1604         I915_WRITE(reg, dpll);
1605         POSTING_READ(reg);
1606         udelay(150); /* wait for warmup */
1607 }
1608
1609 /**
1610  * i9xx_disable_pll - disable a PLL
1611  * @dev_priv: i915 private structure
1612  * @pipe: pipe PLL to disable
1613  *
1614  * Disable the PLL for @pipe, making sure the pipe is off first.
1615  *
1616  * Note!  This is for pre-ILK only.
1617  */
1618 static void i9xx_disable_pll(struct intel_crtc *crtc)
1619 {
1620         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1621         enum pipe pipe = crtc->pipe;
1622
1623         /* Disable DVO 2x clock on both PLLs if necessary */
1624         if (IS_I830(dev_priv) &&
1625             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1626             !intel_num_dvo_pipes(dev_priv)) {
1627                 I915_WRITE(DPLL(PIPE_B),
1628                            I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1629                 I915_WRITE(DPLL(PIPE_A),
1630                            I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1631         }
1632
1633         /* Don't disable pipe or pipe PLLs if needed */
1634         if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1635             (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1636                 return;
1637
1638         /* Make sure the pipe isn't still relying on us */
1639         assert_pipe_disabled(dev_priv, pipe);
1640
1641         I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1642         POSTING_READ(DPLL(pipe));
1643 }
1644
1645 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1646 {
1647         u32 val;
1648
1649         /* Make sure the pipe isn't still relying on us */
1650         assert_pipe_disabled(dev_priv, pipe);
1651
1652         val = DPLL_INTEGRATED_REF_CLK_VLV |
1653                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1654         if (pipe != PIPE_A)
1655                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1656
1657         I915_WRITE(DPLL(pipe), val);
1658         POSTING_READ(DPLL(pipe));
1659 }
1660
1661 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662 {
1663         enum dpio_channel port = vlv_pipe_to_channel(pipe);
1664         u32 val;
1665
1666         /* Make sure the pipe isn't still relying on us */
1667         assert_pipe_disabled(dev_priv, pipe);
1668
1669         val = DPLL_SSC_REF_CLK_CHV |
1670                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1671         if (pipe != PIPE_A)
1672                 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1673
1674         I915_WRITE(DPLL(pipe), val);
1675         POSTING_READ(DPLL(pipe));
1676
1677         mutex_lock(&dev_priv->sb_lock);
1678
1679         /* Disable 10bit clock to display controller */
1680         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1681         val &= ~DPIO_DCLKP_EN;
1682         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1683
1684         mutex_unlock(&dev_priv->sb_lock);
1685 }
1686
1687 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1688                          struct intel_digital_port *dport,
1689                          unsigned int expected_mask)
1690 {
1691         u32 port_mask;
1692         i915_reg_t dpll_reg;
1693
1694         switch (dport->port) {
1695         case PORT_B:
1696                 port_mask = DPLL_PORTB_READY_MASK;
1697                 dpll_reg = DPLL(0);
1698                 break;
1699         case PORT_C:
1700                 port_mask = DPLL_PORTC_READY_MASK;
1701                 dpll_reg = DPLL(0);
1702                 expected_mask <<= 4;
1703                 break;
1704         case PORT_D:
1705                 port_mask = DPLL_PORTD_READY_MASK;
1706                 dpll_reg = DPIO_PHY_STATUS;
1707                 break;
1708         default:
1709                 BUG();
1710         }
1711
1712         if (intel_wait_for_register(dev_priv,
1713                                     dpll_reg, port_mask, expected_mask,
1714                                     1000))
1715                 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1716                      port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1717 }
1718
1719 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1720                                            enum pipe pipe)
1721 {
1722         struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1723                                                                 pipe);
1724         i915_reg_t reg;
1725         uint32_t val, pipeconf_val;
1726
1727         /* Make sure PCH DPLL is enabled */
1728         assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1729
1730         /* FDI must be feeding us bits for PCH ports */
1731         assert_fdi_tx_enabled(dev_priv, pipe);
1732         assert_fdi_rx_enabled(dev_priv, pipe);
1733
1734         if (HAS_PCH_CPT(dev_priv)) {
1735                 /* Workaround: Set the timing override bit before enabling the
1736                  * pch transcoder. */
1737                 reg = TRANS_CHICKEN2(pipe);
1738                 val = I915_READ(reg);
1739                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1740                 I915_WRITE(reg, val);
1741         }
1742
1743         reg = PCH_TRANSCONF(pipe);
1744         val = I915_READ(reg);
1745         pipeconf_val = I915_READ(PIPECONF(pipe));
1746
1747         if (HAS_PCH_IBX(dev_priv)) {
1748                 /*
1749                  * Make the BPC in transcoder be consistent with
1750                  * that in pipeconf reg. For HDMI we must use 8bpc
1751                  * here for both 8bpc and 12bpc.
1752                  */
1753                 val &= ~PIPECONF_BPC_MASK;
1754                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1755                         val |= PIPECONF_8BPC;
1756                 else
1757                         val |= pipeconf_val & PIPECONF_BPC_MASK;
1758         }
1759
1760         val &= ~TRANS_INTERLACE_MASK;
1761         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1762                 if (HAS_PCH_IBX(dev_priv) &&
1763                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1764                         val |= TRANS_LEGACY_INTERLACED_ILK;
1765                 else
1766                         val |= TRANS_INTERLACED;
1767         else
1768                 val |= TRANS_PROGRESSIVE;
1769
1770         I915_WRITE(reg, val | TRANS_ENABLE);
1771         if (intel_wait_for_register(dev_priv,
1772                                     reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1773                                     100))
1774                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1775 }
1776
1777 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1778                                       enum transcoder cpu_transcoder)
1779 {
1780         u32 val, pipeconf_val;
1781
1782         /* FDI must be feeding us bits for PCH ports */
1783         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1784         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1785
1786         /* Workaround: set timing override bit. */
1787         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1788         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1789         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1790
1791         val = TRANS_ENABLE;
1792         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1793
1794         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1795             PIPECONF_INTERLACED_ILK)
1796                 val |= TRANS_INTERLACED;
1797         else
1798                 val |= TRANS_PROGRESSIVE;
1799
1800         I915_WRITE(LPT_TRANSCONF, val);
1801         if (intel_wait_for_register(dev_priv,
1802                                     LPT_TRANSCONF,
1803                                     TRANS_STATE_ENABLE,
1804                                     TRANS_STATE_ENABLE,
1805                                     100))
1806                 DRM_ERROR("Failed to enable PCH transcoder\n");
1807 }
1808
1809 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1810                                             enum pipe pipe)
1811 {
1812         i915_reg_t reg;
1813         uint32_t val;
1814
1815         /* FDI relies on the transcoder */
1816         assert_fdi_tx_disabled(dev_priv, pipe);
1817         assert_fdi_rx_disabled(dev_priv, pipe);
1818
1819         /* Ports must be off as well */
1820         assert_pch_ports_disabled(dev_priv, pipe);
1821
1822         reg = PCH_TRANSCONF(pipe);
1823         val = I915_READ(reg);
1824         val &= ~TRANS_ENABLE;
1825         I915_WRITE(reg, val);
1826         /* wait for PCH transcoder off, transcoder state */
1827         if (intel_wait_for_register(dev_priv,
1828                                     reg, TRANS_STATE_ENABLE, 0,
1829                                     50))
1830                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1831
1832         if (HAS_PCH_CPT(dev_priv)) {
1833                 /* Workaround: Clear the timing override chicken bit again. */
1834                 reg = TRANS_CHICKEN2(pipe);
1835                 val = I915_READ(reg);
1836                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1837                 I915_WRITE(reg, val);
1838         }
1839 }
1840
1841 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1842 {
1843         u32 val;
1844
1845         val = I915_READ(LPT_TRANSCONF);
1846         val &= ~TRANS_ENABLE;
1847         I915_WRITE(LPT_TRANSCONF, val);
1848         /* wait for PCH transcoder off, transcoder state */
1849         if (intel_wait_for_register(dev_priv,
1850                                     LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1851                                     50))
1852                 DRM_ERROR("Failed to disable PCH transcoder\n");
1853
1854         /* Workaround: clear timing override bit. */
1855         val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1857         I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1858 }
1859
1860 enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1861 {
1862         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1863
1864         WARN_ON(!crtc->config->has_pch_encoder);
1865
1866         if (HAS_PCH_LPT(dev_priv))
1867                 return TRANSCODER_A;
1868         else
1869                 return (enum transcoder) crtc->pipe;
1870 }
1871
1872 /**
1873  * intel_enable_pipe - enable a pipe, asserting requirements
1874  * @crtc: crtc responsible for the pipe
1875  *
1876  * Enable @crtc's pipe, making sure that various hardware specific requirements
1877  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1878  */
1879 static void intel_enable_pipe(struct intel_crtc *crtc)
1880 {
1881         struct drm_device *dev = crtc->base.dev;
1882         struct drm_i915_private *dev_priv = to_i915(dev);
1883         enum pipe pipe = crtc->pipe;
1884         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1885         i915_reg_t reg;
1886         u32 val;
1887
1888         DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1889
1890         assert_planes_disabled(dev_priv, pipe);
1891         assert_cursor_disabled(dev_priv, pipe);
1892         assert_sprites_disabled(dev_priv, pipe);
1893
1894         /*
1895          * A pipe without a PLL won't actually be able to drive bits from
1896          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1897          * need the check.
1898          */
1899         if (HAS_GMCH_DISPLAY(dev_priv)) {
1900                 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1901                         assert_dsi_pll_enabled(dev_priv);
1902                 else
1903                         assert_pll_enabled(dev_priv, pipe);
1904         } else {
1905                 if (crtc->config->has_pch_encoder) {
1906                         /* if driving the PCH, we need FDI enabled */
1907                         assert_fdi_rx_pll_enabled(dev_priv,
1908                                                   (enum pipe) intel_crtc_pch_transcoder(crtc));
1909                         assert_fdi_tx_pll_enabled(dev_priv,
1910                                                   (enum pipe) cpu_transcoder);
1911                 }
1912                 /* FIXME: assert CPU port conditions for SNB+ */
1913         }
1914
1915         reg = PIPECONF(cpu_transcoder);
1916         val = I915_READ(reg);
1917         if (val & PIPECONF_ENABLE) {
1918                 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1919                           (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1920                 return;
1921         }
1922
1923         I915_WRITE(reg, val | PIPECONF_ENABLE);
1924         POSTING_READ(reg);
1925
1926         /*
1927          * Until the pipe starts DSL will read as 0, which would cause
1928          * an apparent vblank timestamp jump, which messes up also the
1929          * frame count when it's derived from the timestamps. So let's
1930          * wait for the pipe to start properly before we call
1931          * drm_crtc_vblank_on()
1932          */
1933         if (dev->max_vblank_count == 0 &&
1934             wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1935                 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
1936 }
1937
1938 /**
1939  * intel_disable_pipe - disable a pipe, asserting requirements
1940  * @crtc: crtc whose pipes is to be disabled
1941  *
1942  * Disable the pipe of @crtc, making sure that various hardware
1943  * specific requirements are met, if applicable, e.g. plane
1944  * disabled, panel fitter off, etc.
1945  *
1946  * Will wait until the pipe has shut down before returning.
1947  */
1948 static void intel_disable_pipe(struct intel_crtc *crtc)
1949 {
1950         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1951         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1952         enum pipe pipe = crtc->pipe;
1953         i915_reg_t reg;
1954         u32 val;
1955
1956         DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1957
1958         /*
1959          * Make sure planes won't keep trying to pump pixels to us,
1960          * or we might hang the display.
1961          */
1962         assert_planes_disabled(dev_priv, pipe);
1963         assert_cursor_disabled(dev_priv, pipe);
1964         assert_sprites_disabled(dev_priv, pipe);
1965
1966         reg = PIPECONF(cpu_transcoder);
1967         val = I915_READ(reg);
1968         if ((val & PIPECONF_ENABLE) == 0)
1969                 return;
1970
1971         /*
1972          * Double wide has implications for planes
1973          * so best keep it disabled when not needed.
1974          */
1975         if (crtc->config->double_wide)
1976                 val &= ~PIPECONF_DOUBLE_WIDE;
1977
1978         /* Don't disable pipe or pipe PLLs if needed */
1979         if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
1980             !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1981                 val &= ~PIPECONF_ENABLE;
1982
1983         I915_WRITE(reg, val);
1984         if ((val & PIPECONF_ENABLE) == 0)
1985                 intel_wait_for_pipe_off(crtc);
1986 }
1987
1988 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1989 {
1990         return IS_GEN2(dev_priv) ? 2048 : 4096;
1991 }
1992
1993 static unsigned int
1994 intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
1995 {
1996         struct drm_i915_private *dev_priv = to_i915(fb->dev);
1997         unsigned int cpp = fb->format->cpp[plane];
1998
1999         switch (fb->modifier) {
2000         case DRM_FORMAT_MOD_NONE:
2001                 return cpp;
2002         case I915_FORMAT_MOD_X_TILED:
2003                 if (IS_GEN2(dev_priv))
2004                         return 128;
2005                 else
2006                         return 512;
2007         case I915_FORMAT_MOD_Y_TILED:
2008                 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2009                         return 128;
2010                 else
2011                         return 512;
2012         case I915_FORMAT_MOD_Yf_TILED:
2013                 switch (cpp) {
2014                 case 1:
2015                         return 64;
2016                 case 2:
2017                 case 4:
2018                         return 128;
2019                 case 8:
2020                 case 16:
2021                         return 256;
2022                 default:
2023                         MISSING_CASE(cpp);
2024                         return cpp;
2025                 }
2026                 break;
2027         default:
2028                 MISSING_CASE(fb->modifier);
2029                 return cpp;
2030         }
2031 }
2032
2033 static unsigned int
2034 intel_tile_height(const struct drm_framebuffer *fb, int plane)
2035 {
2036         if (fb->modifier == DRM_FORMAT_MOD_NONE)
2037                 return 1;
2038         else
2039                 return intel_tile_size(to_i915(fb->dev)) /
2040                         intel_tile_width_bytes(fb, plane);
2041 }
2042
2043 /* Return the tile dimensions in pixel units */
2044 static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
2045                             unsigned int *tile_width,
2046                             unsigned int *tile_height)
2047 {
2048         unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2049         unsigned int cpp = fb->format->cpp[plane];
2050
2051         *tile_width = tile_width_bytes / cpp;
2052         *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
2053 }
2054
2055 unsigned int
2056 intel_fb_align_height(const struct drm_framebuffer *fb,
2057                       int plane, unsigned int height)
2058 {
2059         unsigned int tile_height = intel_tile_height(fb, plane);
2060
2061         return ALIGN(height, tile_height);
2062 }
2063
2064 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2065 {
2066         unsigned int size = 0;
2067         int i;
2068
2069         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2070                 size += rot_info->plane[i].width * rot_info->plane[i].height;
2071
2072         return size;
2073 }
2074
2075 static void
2076 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2077                         const struct drm_framebuffer *fb,
2078                         unsigned int rotation)
2079 {
2080         view->type = I915_GGTT_VIEW_NORMAL;
2081         if (drm_rotation_90_or_270(rotation)) {
2082                 view->type = I915_GGTT_VIEW_ROTATED;
2083                 view->rotated = to_intel_framebuffer(fb)->rot_info;
2084         }
2085 }
2086
2087 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2088 {
2089         if (INTEL_INFO(dev_priv)->gen >= 9)
2090                 return 256 * 1024;
2091         else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
2092                  IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2093                 return 128 * 1024;
2094         else if (INTEL_INFO(dev_priv)->gen >= 4)
2095                 return 4 * 1024;
2096         else
2097                 return 0;
2098 }
2099
2100 static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2101                                          int plane)
2102 {
2103         struct drm_i915_private *dev_priv = to_i915(fb->dev);
2104
2105         /* AUX_DIST needs only 4K alignment */
2106         if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2107                 return 4096;
2108
2109         switch (fb->modifier) {
2110         case DRM_FORMAT_MOD_NONE:
2111                 return intel_linear_alignment(dev_priv);
2112         case I915_FORMAT_MOD_X_TILED:
2113                 if (INTEL_GEN(dev_priv) >= 9)
2114                         return 256 * 1024;
2115                 return 0;
2116         case I915_FORMAT_MOD_Y_TILED:
2117         case I915_FORMAT_MOD_Yf_TILED:
2118                 return 1 * 1024 * 1024;
2119         default:
2120                 MISSING_CASE(fb->modifier);
2121                 return 0;
2122         }
2123 }
2124
2125 struct i915_vma *
2126 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2127 {
2128         struct drm_device *dev = fb->dev;
2129         struct drm_i915_private *dev_priv = to_i915(dev);
2130         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2131         struct i915_ggtt_view view;
2132         struct i915_vma *vma;
2133         u32 alignment;
2134
2135         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2136
2137         alignment = intel_surf_alignment(fb, 0);
2138
2139         intel_fill_fb_ggtt_view(&view, fb, rotation);
2140
2141         /* Note that the w/a also requires 64 PTE of padding following the
2142          * bo. We currently fill all unused PTE with the shadow page and so
2143          * we should always have valid PTE following the scanout preventing
2144          * the VT-d warning.
2145          */
2146         if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2147                 alignment = 256 * 1024;
2148
2149         /*
2150          * Global gtt pte registers are special registers which actually forward
2151          * writes to a chunk of system memory. Which means that there is no risk
2152          * that the register values disappear as soon as we call
2153          * intel_runtime_pm_put(), so it is correct to wrap only the
2154          * pin/unpin/fence and not more.
2155          */
2156         intel_runtime_pm_get(dev_priv);
2157
2158         vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2159         if (IS_ERR(vma))
2160                 goto err;
2161
2162         if (i915_vma_is_map_and_fenceable(vma)) {
2163                 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2164                  * fence, whereas 965+ only requires a fence if using
2165                  * framebuffer compression.  For simplicity, we always, when
2166                  * possible, install a fence as the cost is not that onerous.
2167                  *
2168                  * If we fail to fence the tiled scanout, then either the
2169                  * modeset will reject the change (which is highly unlikely as
2170                  * the affected systems, all but one, do not have unmappable
2171                  * space) or we will not be able to enable full powersaving
2172                  * techniques (also likely not to apply due to various limits
2173                  * FBC and the like impose on the size of the buffer, which
2174                  * presumably we violated anyway with this unmappable buffer).
2175                  * Anyway, it is presumably better to stumble onwards with
2176                  * something and try to run the system in a "less than optimal"
2177                  * mode that matches the user configuration.
2178                  */
2179                 if (i915_vma_get_fence(vma) == 0)
2180                         i915_vma_pin_fence(vma);
2181         }
2182
2183         i915_vma_get(vma);
2184 err:
2185         intel_runtime_pm_put(dev_priv);
2186         return vma;
2187 }
2188
2189 void intel_unpin_fb_vma(struct i915_vma *vma)
2190 {
2191         lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
2192
2193         i915_vma_unpin_fence(vma);
2194         i915_gem_object_unpin_from_display_plane(vma);
2195         i915_vma_put(vma);
2196 }
2197
2198 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2199                           unsigned int rotation)
2200 {
2201         if (drm_rotation_90_or_270(rotation))
2202                 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2203         else
2204                 return fb->pitches[plane];
2205 }
2206
2207 /*
2208  * Convert the x/y offsets into a linear offset.
2209  * Only valid with 0/180 degree rotation, which is fine since linear
2210  * offset is only used with linear buffers on pre-hsw and tiled buffers
2211  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2212  */
2213 u32 intel_fb_xy_to_linear(int x, int y,
2214                           const struct intel_plane_state *state,
2215                           int plane)
2216 {
2217         const struct drm_framebuffer *fb = state->base.fb;
2218         unsigned int cpp = fb->format->cpp[plane];
2219         unsigned int pitch = fb->pitches[plane];
2220
2221         return y * pitch + x * cpp;
2222 }
2223
2224 /*
2225  * Add the x/y offsets derived from fb->offsets[] to the user
2226  * specified plane src x/y offsets. The resulting x/y offsets
2227  * specify the start of scanout from the beginning of the gtt mapping.
2228  */
2229 void intel_add_fb_offsets(int *x, int *y,
2230                           const struct intel_plane_state *state,
2231                           int plane)
2232
2233 {
2234         const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2235         unsigned int rotation = state->base.rotation;
2236
2237         if (drm_rotation_90_or_270(rotation)) {
2238                 *x += intel_fb->rotated[plane].x;
2239                 *y += intel_fb->rotated[plane].y;
2240         } else {
2241                 *x += intel_fb->normal[plane].x;
2242                 *y += intel_fb->normal[plane].y;
2243         }
2244 }
2245
2246 /*
2247  * Input tile dimensions and pitch must already be
2248  * rotated to match x and y, and in pixel units.
2249  */
2250 static u32 _intel_adjust_tile_offset(int *x, int *y,
2251                                      unsigned int tile_width,
2252                                      unsigned int tile_height,
2253                                      unsigned int tile_size,
2254                                      unsigned int pitch_tiles,
2255                                      u32 old_offset,
2256                                      u32 new_offset)
2257 {
2258         unsigned int pitch_pixels = pitch_tiles * tile_width;
2259         unsigned int tiles;
2260
2261         WARN_ON(old_offset & (tile_size - 1));
2262         WARN_ON(new_offset & (tile_size - 1));
2263         WARN_ON(new_offset > old_offset);
2264
2265         tiles = (old_offset - new_offset) / tile_size;
2266
2267         *y += tiles / pitch_tiles * tile_height;
2268         *x += tiles % pitch_tiles * tile_width;
2269
2270         /* minimize x in case it got needlessly big */
2271         *y += *x / pitch_pixels * tile_height;
2272         *x %= pitch_pixels;
2273
2274         return new_offset;
2275 }
2276
2277 /*
2278  * Adjust the tile offset by moving the difference into
2279  * the x/y offsets.
2280  */
2281 static u32 intel_adjust_tile_offset(int *x, int *y,
2282                                     const struct intel_plane_state *state, int plane,
2283                                     u32 old_offset, u32 new_offset)
2284 {
2285         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2286         const struct drm_framebuffer *fb = state->base.fb;
2287         unsigned int cpp = fb->format->cpp[plane];
2288         unsigned int rotation = state->base.rotation;
2289         unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2290
2291         WARN_ON(new_offset > old_offset);
2292
2293         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2294                 unsigned int tile_size, tile_width, tile_height;
2295                 unsigned int pitch_tiles;
2296
2297                 tile_size = intel_tile_size(dev_priv);
2298                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2299
2300                 if (drm_rotation_90_or_270(rotation)) {
2301                         pitch_tiles = pitch / tile_height;
2302                         swap(tile_width, tile_height);
2303                 } else {
2304                         pitch_tiles = pitch / (tile_width * cpp);
2305                 }
2306
2307                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2308                                           tile_size, pitch_tiles,
2309                                           old_offset, new_offset);
2310         } else {
2311                 old_offset += *y * pitch + *x * cpp;
2312
2313                 *y = (old_offset - new_offset) / pitch;
2314                 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2315         }
2316
2317         return new_offset;
2318 }
2319
2320 /*
2321  * Computes the linear offset to the base tile and adjusts
2322  * x, y. bytes per pixel is assumed to be a power-of-two.
2323  *
2324  * In the 90/270 rotated case, x and y are assumed
2325  * to be already rotated to match the rotated GTT view, and
2326  * pitch is the tile_height aligned framebuffer height.
2327  *
2328  * This function is used when computing the derived information
2329  * under intel_framebuffer, so using any of that information
2330  * here is not allowed. Anything under drm_framebuffer can be
2331  * used. This is why the user has to pass in the pitch since it
2332  * is specified in the rotated orientation.
2333  */
2334 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2335                                       int *x, int *y,
2336                                       const struct drm_framebuffer *fb, int plane,
2337                                       unsigned int pitch,
2338                                       unsigned int rotation,
2339                                       u32 alignment)
2340 {
2341         uint64_t fb_modifier = fb->modifier;
2342         unsigned int cpp = fb->format->cpp[plane];
2343         u32 offset, offset_aligned;
2344
2345         if (alignment)
2346                 alignment--;
2347
2348         if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2349                 unsigned int tile_size, tile_width, tile_height;
2350                 unsigned int tile_rows, tiles, pitch_tiles;
2351
2352                 tile_size = intel_tile_size(dev_priv);
2353                 intel_tile_dims(fb, plane, &tile_width, &tile_height);
2354
2355                 if (drm_rotation_90_or_270(rotation)) {
2356                         pitch_tiles = pitch / tile_height;
2357                         swap(tile_width, tile_height);
2358                 } else {
2359                         pitch_tiles = pitch / (tile_width * cpp);
2360                 }
2361
2362                 tile_rows = *y / tile_height;
2363                 *y %= tile_height;
2364
2365                 tiles = *x / tile_width;
2366                 *x %= tile_width;
2367
2368                 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2369                 offset_aligned = offset & ~alignment;
2370
2371                 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2372                                           tile_size, pitch_tiles,
2373                                           offset, offset_aligned);
2374         } else {
2375                 offset = *y * pitch + *x * cpp;
2376                 offset_aligned = offset & ~alignment;
2377
2378                 *y = (offset & alignment) / pitch;
2379                 *x = ((offset & alignment) - *y * pitch) / cpp;
2380         }
2381
2382         return offset_aligned;
2383 }
2384
2385 u32 intel_compute_tile_offset(int *x, int *y,
2386                               const struct intel_plane_state *state,
2387                               int plane)
2388 {
2389         const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2390         const struct drm_framebuffer *fb = state->base.fb;
2391         unsigned int rotation = state->base.rotation;
2392         int pitch = intel_fb_pitch(fb, plane, rotation);
2393         u32 alignment = intel_surf_alignment(fb, plane);
2394
2395         return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2396                                           rotation, alignment);
2397 }
2398
2399 /* Convert the fb->offset[] linear offset into x/y offsets */
2400 static void intel_fb_offset_to_xy(int *x, int *y,
2401                                   const struct drm_framebuffer *fb, int plane)
2402 {
2403         unsigned int cpp = fb->format->cpp[plane];
2404         unsigned int pitch = fb->pitches[plane];
2405         u32 linear_offset = fb->offsets[plane];
2406
2407         *y = linear_offset / pitch;
2408         *x = linear_offset % pitch / cpp;
2409 }
2410
2411 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2412 {
2413         switch (fb_modifier) {
2414         case I915_FORMAT_MOD_X_TILED:
2415                 return I915_TILING_X;
2416         case I915_FORMAT_MOD_Y_TILED:
2417                 return I915_TILING_Y;
2418         default:
2419                 return I915_TILING_NONE;
2420         }
2421 }
2422
2423 static int
2424 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2425                    struct drm_framebuffer *fb)
2426 {
2427         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2428         struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2429         u32 gtt_offset_rotated = 0;
2430         unsigned int max_size = 0;
2431         int i, num_planes = fb->format->num_planes;
2432         unsigned int tile_size = intel_tile_size(dev_priv);
2433
2434         for (i = 0; i < num_planes; i++) {
2435                 unsigned int width, height;
2436                 unsigned int cpp, size;
2437                 u32 offset;
2438                 int x, y;
2439
2440                 cpp = fb->format->cpp[i];
2441                 width = drm_framebuffer_plane_width(fb->width, fb, i);
2442                 height = drm_framebuffer_plane_height(fb->height, fb, i);
2443
2444                 intel_fb_offset_to_xy(&x, &y, fb, i);
2445
2446                 /*
2447                  * The fence (if used) is aligned to the start of the object
2448                  * so having the framebuffer wrap around across the edge of the
2449                  * fenced region doesn't really work. We have no API to configure
2450                  * the fence start offset within the object (nor could we probably
2451                  * on gen2/3). So it's just easier if we just require that the
2452                  * fb layout agrees with the fence layout. We already check that the
2453                  * fb stride matches the fence stride elsewhere.
2454                  */
2455                 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2456                     (x + width) * cpp > fb->pitches[i]) {
2457                         DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2458                                       i, fb->offsets[i]);
2459                         return -EINVAL;
2460                 }
2461
2462                 /*
2463                  * First pixel of the framebuffer from
2464                  * the start of the normal gtt mapping.
2465                  */
2466                 intel_fb->normal[i].x = x;
2467                 intel_fb->normal[i].y = y;
2468
2469                 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2470                                                     fb, i, fb->pitches[i],
2471                                                     DRM_ROTATE_0, tile_size);
2472                 offset /= tile_size;
2473
2474                 if (fb->modifier != DRM_FORMAT_MOD_NONE) {
2475                         unsigned int tile_width, tile_height;
2476                         unsigned int pitch_tiles;
2477                         struct drm_rect r;
2478
2479                         intel_tile_dims(fb, i, &tile_width, &tile_height);
2480
2481                         rot_info->plane[i].offset = offset;
2482                         rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2483                         rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2484                         rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2485
2486                         intel_fb->rotated[i].pitch =
2487                                 rot_info->plane[i].height * tile_height;
2488
2489                         /* how many tiles does this plane need */
2490                         size = rot_info->plane[i].stride * rot_info->plane[i].height;
2491                         /*
2492                          * If the plane isn't horizontally tile aligned,
2493                          * we need one more tile.
2494                          */
2495                         if (x != 0)
2496                                 size++;
2497
2498                         /* rotate the x/y offsets to match the GTT view */
2499                         r.x1 = x;
2500                         r.y1 = y;
2501                         r.x2 = x + width;
2502                         r.y2 = y + height;
2503                         drm_rect_rotate(&r,
2504                                         rot_info->plane[i].width * tile_width,
2505                                         rot_info->plane[i].height * tile_height,
2506                                         DRM_ROTATE_270);
2507                         x = r.x1;
2508                         y = r.y1;
2509
2510                         /* rotate the tile dimensions to match the GTT view */
2511                         pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2512                         swap(tile_width, tile_height);
2513
2514                         /*
2515                          * We only keep the x/y offsets, so push all of the
2516                          * gtt offset into the x/y offsets.
2517                          */
2518                         _intel_adjust_tile_offset(&x, &y,
2519                                                   tile_width, tile_height,
2520                                                   tile_size, pitch_tiles,
2521                                                   gtt_offset_rotated * tile_size, 0);
2522
2523                         gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2524
2525                         /*
2526                          * First pixel of the framebuffer from
2527                          * the start of the rotated gtt mapping.
2528                          */
2529                         intel_fb->rotated[i].x = x;
2530                         intel_fb->rotated[i].y = y;
2531                 } else {
2532                         size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2533                                             x * cpp, tile_size);
2534                 }
2535
2536                 /* how many tiles in total needed in the bo */
2537                 max_size = max(max_size, offset + size);
2538         }
2539
2540         if (max_size * tile_size > intel_fb->obj->base.size) {
2541                 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2542                               max_size * tile_size, intel_fb->obj->base.size);
2543                 return -EINVAL;
2544         }
2545
2546         return 0;
2547 }
2548
2549 static int i9xx_format_to_fourcc(int format)
2550 {
2551         switch (format) {
2552         case DISPPLANE_8BPP:
2553                 return DRM_FORMAT_C8;
2554         case DISPPLANE_BGRX555:
2555                 return DRM_FORMAT_XRGB1555;
2556         case DISPPLANE_BGRX565:
2557                 return DRM_FORMAT_RGB565;
2558         default:
2559         case DISPPLANE_BGRX888:
2560                 return DRM_FORMAT_XRGB8888;
2561         case DISPPLANE_RGBX888:
2562                 return DRM_FORMAT_XBGR8888;
2563         case DISPPLANE_BGRX101010:
2564                 return DRM_FORMAT_XRGB2101010;
2565         case DISPPLANE_RGBX101010:
2566                 return DRM_FORMAT_XBGR2101010;
2567         }
2568 }
2569
2570 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2571 {
2572         switch (format) {
2573         case PLANE_CTL_FORMAT_RGB_565:
2574                 return DRM_FORMAT_RGB565;
2575         default:
2576         case PLANE_CTL_FORMAT_XRGB_8888:
2577                 if (rgb_order) {
2578                         if (alpha)
2579                                 return DRM_FORMAT_ABGR8888;
2580                         else
2581                                 return DRM_FORMAT_XBGR8888;
2582                 } else {
2583                         if (alpha)
2584                                 return DRM_FORMAT_ARGB8888;
2585                         else
2586                                 return DRM_FORMAT_XRGB8888;
2587                 }
2588         case PLANE_CTL_FORMAT_XRGB_2101010:
2589                 if (rgb_order)
2590                         return DRM_FORMAT_XBGR2101010;
2591                 else
2592                         return DRM_FORMAT_XRGB2101010;
2593         }
2594 }
2595
2596 static bool
2597 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2598                               struct intel_initial_plane_config *plane_config)
2599 {
2600         struct drm_device *dev = crtc->base.dev;
2601         struct drm_i915_private *dev_priv = to_i915(dev);
2602         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2603         struct drm_i915_gem_object *obj = NULL;
2604         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2605         struct drm_framebuffer *fb = &plane_config->fb->base;
2606         u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2607         u32 size_aligned = round_up(plane_config->base + plane_config->size,
2608                                     PAGE_SIZE);
2609
2610         size_aligned -= base_aligned;
2611
2612         if (plane_config->size == 0)
2613                 return false;
2614
2615         /* If the FB is too big, just don't use it since fbdev is not very
2616          * important and we should probably use that space with FBC or other
2617          * features. */
2618         if (size_aligned * 2 > ggtt->stolen_usable_size)
2619                 return false;
2620
2621         mutex_lock(&dev->struct_mutex);
2622         obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
2623                                                              base_aligned,
2624                                                              base_aligned,
2625                                                              size_aligned);
2626         mutex_unlock(&dev->struct_mutex);
2627         if (!obj)
2628                 return false;
2629
2630         if (plane_config->tiling == I915_TILING_X)
2631                 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2632
2633         mode_cmd.pixel_format = fb->format->format;
2634         mode_cmd.width = fb->width;
2635         mode_cmd.height = fb->height;
2636         mode_cmd.pitches[0] = fb->pitches[0];
2637         mode_cmd.modifier[0] = fb->modifier;
2638         mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2639
2640         if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
2641                 DRM_DEBUG_KMS("intel fb init failed\n");
2642                 goto out_unref_obj;
2643         }
2644
2645
2646         DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2647         return true;
2648
2649 out_unref_obj:
2650         i915_gem_object_put(obj);
2651         return false;
2652 }
2653
2654 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2655 static void
2656 update_state_fb(struct drm_plane *plane)
2657 {
2658         if (plane->fb == plane->state->fb)
2659                 return;
2660
2661         if (plane->state->fb)
2662                 drm_framebuffer_unreference(plane->state->fb);
2663         plane->state->fb = plane->fb;
2664         if (plane->state->fb)
2665                 drm_framebuffer_reference(plane->state->fb);
2666 }
2667
2668 static void
2669 intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2670                         struct intel_plane_state *plane_state,
2671                         bool visible)
2672 {
2673         struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2674
2675         plane_state->base.visible = visible;
2676
2677         /* FIXME pre-g4x don't work like this */
2678         if (visible) {
2679                 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2680                 crtc_state->active_planes |= BIT(plane->id);
2681         } else {
2682                 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2683                 crtc_state->active_planes &= ~BIT(plane->id);
2684         }
2685
2686         DRM_DEBUG_KMS("%s active planes 0x%x\n",
2687                       crtc_state->base.crtc->name,
2688                       crtc_state->active_planes);
2689 }
2690
2691 static void
2692 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2693                              struct intel_initial_plane_config *plane_config)
2694 {
2695         struct drm_device *dev = intel_crtc->base.dev;
2696         struct drm_i915_private *dev_priv = to_i915(dev);
2697         struct drm_crtc *c;
2698         struct drm_i915_gem_object *obj;
2699         struct drm_plane *primary = intel_crtc->base.primary;
2700         struct drm_plane_state *plane_state = primary->state;
2701         struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2702         struct intel_plane *intel_plane = to_intel_plane(primary);
2703         struct intel_plane_state *intel_state =
2704                 to_intel_plane_state(plane_state);
2705         struct drm_framebuffer *fb;
2706
2707         if (!plane_config->fb)
2708                 return;
2709
2710         if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2711                 fb = &plane_config->fb->base;
2712                 goto valid_fb;
2713         }
2714
2715         kfree(plane_config->fb);
2716
2717         /*
2718          * Failed to alloc the obj, check to see if we should share
2719          * an fb with another CRTC instead
2720          */
2721         for_each_crtc(dev, c) {
2722                 struct intel_plane_state *state;
2723
2724                 if (c == &intel_crtc->base)
2725                         continue;
2726
2727                 if (!to_intel_crtc(c)->active)
2728                         continue;
2729
2730                 state = to_intel_plane_state(c->primary->state);
2731                 if (!state->vma)
2732                         continue;
2733
2734                 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2735                         fb = c->primary->fb;
2736                         drm_framebuffer_reference(fb);
2737                         goto valid_fb;
2738                 }
2739         }
2740
2741         /*
2742          * We've failed to reconstruct the BIOS FB.  Current display state
2743          * indicates that the primary plane is visible, but has a NULL FB,
2744          * which will lead to problems later if we don't fix it up.  The
2745          * simplest solution is to just disable the primary plane now and
2746          * pretend the BIOS never had it enabled.
2747          */
2748         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2749                                 to_intel_plane_state(plane_state),
2750                                 false);
2751         intel_pre_disable_primary_noatomic(&intel_crtc->base);
2752         trace_intel_disable_plane(primary, intel_crtc);
2753         intel_plane->disable_plane(primary, &intel_crtc->base);
2754
2755         return;
2756
2757 valid_fb:
2758         mutex_lock(&dev->struct_mutex);
2759         intel_state->vma =
2760                 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2761         mutex_unlock(&dev->struct_mutex);
2762         if (IS_ERR(intel_state->vma)) {
2763                 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2764                           intel_crtc->pipe, PTR_ERR(intel_state->vma));
2765
2766                 intel_state->vma = NULL;
2767                 drm_framebuffer_unreference(fb);
2768                 return;
2769         }
2770
2771         plane_state->src_x = 0;
2772         plane_state->src_y = 0;
2773         plane_state->src_w = fb->width << 16;
2774         plane_state->src_h = fb->height << 16;
2775
2776         plane_state->crtc_x = 0;
2777         plane_state->crtc_y = 0;
2778         plane_state->crtc_w = fb->width;
2779         plane_state->crtc_h = fb->height;
2780
2781         intel_state->base.src = drm_plane_state_src(plane_state);
2782         intel_state->base.dst = drm_plane_state_dest(plane_state);
2783
2784         obj = intel_fb_obj(fb);
2785         if (i915_gem_object_is_tiled(obj))
2786                 dev_priv->preserve_bios_swizzle = true;
2787
2788         drm_framebuffer_reference(fb);
2789         primary->fb = primary->state->fb = fb;
2790         primary->crtc = primary->state->crtc = &intel_crtc->base;
2791
2792         intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2793                                 to_intel_plane_state(plane_state),
2794                                 true);
2795
2796         atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2797                   &obj->frontbuffer_bits);
2798 }
2799
2800 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2801                                unsigned int rotation)
2802 {
2803         int cpp = fb->format->cpp[plane];
2804
2805         switch (fb->modifier) {
2806         case DRM_FORMAT_MOD_NONE:
2807         case I915_FORMAT_MOD_X_TILED:
2808                 switch (cpp) {
2809                 case 8:
2810                         return 4096;
2811                 case 4:
2812                 case 2:
2813                 case 1:
2814                         return 8192;
2815                 default:
2816                         MISSING_CASE(cpp);
2817                         break;
2818                 }
2819                 break;
2820         case I915_FORMAT_MOD_Y_TILED:
2821         case I915_FORMAT_MOD_Yf_TILED:
2822                 switch (cpp) {
2823                 case 8:
2824                         return 2048;
2825                 case 4:
2826                         return 4096;
2827                 case 2:
2828                 case 1:
2829                         return 8192;
2830                 default:
2831                         MISSING_CASE(cpp);
2832                         break;
2833                 }
2834                 break;
2835         default:
2836                 MISSING_CASE(fb->modifier);
2837         }
2838
2839         return 2048;
2840 }
2841
2842 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2843 {
2844         const struct drm_framebuffer *fb = plane_state->base.fb;
2845         unsigned int rotation = plane_state->base.rotation;
2846         int x = plane_state->base.src.x1 >> 16;
2847         int y = plane_state->base.src.y1 >> 16;
2848         int w = drm_rect_width(&plane_state->base.src) >> 16;
2849         int h = drm_rect_height(&plane_state->base.src) >> 16;
2850         int max_width = skl_max_plane_width(fb, 0, rotation);
2851         int max_height = 4096;
2852         u32 alignment, offset, aux_offset = plane_state->aux.offset;
2853
2854         if (w > max_width || h > max_height) {
2855                 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2856                               w, h, max_width, max_height);
2857                 return -EINVAL;
2858         }
2859
2860         intel_add_fb_offsets(&x, &y, plane_state, 0);
2861         offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2862         alignment = intel_surf_alignment(fb, 0);
2863
2864         /*
2865          * AUX surface offset is specified as the distance from the
2866          * main surface offset, and it must be non-negative. Make
2867          * sure that is what we will get.
2868          */
2869         if (offset > aux_offset)
2870                 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2871                                                   offset, aux_offset & ~(alignment - 1));
2872
2873         /*
2874          * When using an X-tiled surface, the plane blows up
2875          * if the x offset + width exceed the stride.
2876          *
2877          * TODO: linear and Y-tiled seem fine, Yf untested,
2878          */
2879         if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
2880                 int cpp = fb->format->cpp[0];
2881
2882                 while ((x + w) * cpp > fb->pitches[0]) {
2883                         if (offset == 0) {
2884                                 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2885                                 return -EINVAL;
2886                         }
2887
2888                         offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2889                                                           offset, offset - alignment);
2890                 }
2891         }
2892
2893         plane_state->main.offset = offset;
2894         plane_state->main.x = x;
2895         plane_state->main.y = y;
2896
2897         return 0;
2898 }
2899
2900 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2901 {
2902         const struct drm_framebuffer *fb = plane_state->base.fb;
2903         unsigned int rotation = plane_state->base.rotation;
2904         int max_width = skl_max_plane_width(fb, 1, rotation);
2905         int max_height = 4096;
2906         int x = plane_state->base.src.x1 >> 17;
2907         int y = plane_state->base.src.y1 >> 17;
2908         int w = drm_rect_width(&plane_state->base.src) >> 17;
2909         int h = drm_rect_height(&plane_state->base.src) >> 17;
2910         u32 offset;
2911
2912         intel_add_fb_offsets(&x, &y, plane_state, 1);
2913         offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2914
2915         /* FIXME not quite sure how/if these apply to the chroma plane */
2916         if (w > max_width || h > max_height) {
2917                 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2918                               w, h, max_width, max_height);
2919                 return -EINVAL;
2920         }
2921
2922         plane_state->aux.offset = offset;
2923         plane_state->aux.x = x;
2924         plane_state->aux.y = y;
2925
2926         return 0;
2927 }
2928
2929 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2930 {
2931         const struct drm_framebuffer *fb = plane_state->base.fb;
2932         unsigned int rotation = plane_state->base.rotation;
2933         int ret;
2934
2935         if (!plane_state->base.visible)
2936                 return 0;
2937
2938         /* Rotate src coordinates to match rotated GTT view */
2939         if (drm_rotation_90_or_270(rotation))
2940                 drm_rect_rotate(&plane_state->base.src,
2941                                 fb->width << 16, fb->height << 16,
2942                                 DRM_ROTATE_270);
2943
2944         /*
2945          * Handle the AUX surface first since
2946          * the main surface setup depends on it.
2947          */
2948         if (fb->format->format == DRM_FORMAT_NV12) {
2949                 ret = skl_check_nv12_aux_surface(plane_state);
2950                 if (ret)
2951                         return ret;
2952         } else {
2953                 plane_state->aux.offset = ~0xfff;
2954                 plane_state->aux.x = 0;
2955                 plane_state->aux.y = 0;
2956         }
2957
2958         ret = skl_check_main_surface(plane_state);
2959         if (ret)
2960                 return ret;
2961
2962         return 0;
2963 }
2964
2965 static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2966                           const struct intel_plane_state *plane_state)
2967 {
2968         struct drm_i915_private *dev_priv =
2969                 to_i915(plane_state->base.plane->dev);
2970         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2971         const struct drm_framebuffer *fb = plane_state->base.fb;
2972         unsigned int rotation = plane_state->base.rotation;
2973         u32 dspcntr;
2974
2975         dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
2976
2977         if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2978             IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2979                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2980
2981         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2982                 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2983
2984         if (INTEL_GEN(dev_priv) < 4) {
2985                 if (crtc->pipe == PIPE_B)
2986                         dspcntr |= DISPPLANE_SEL_PIPE_B;
2987         }
2988
2989         switch (fb->format->format) {
2990         case DRM_FORMAT_C8:
2991                 dspcntr |= DISPPLANE_8BPP;
2992                 break;
2993         case DRM_FORMAT_XRGB1555:
2994                 dspcntr |= DISPPLANE_BGRX555;
2995                 break;
2996         case DRM_FORMAT_RGB565:
2997                 dspcntr |= DISPPLANE_BGRX565;
2998                 break;
2999         case DRM_FORMAT_XRGB8888:
3000                 dspcntr |= DISPPLANE_BGRX888;
3001                 break;
3002         case DRM_FORMAT_XBGR8888:
3003                 dspcntr |= DISPPLANE_RGBX888;
3004                 break;
3005         case DRM_FORMAT_XRGB2101010:
3006                 dspcntr |= DISPPLANE_BGRX101010;
3007                 break;
3008         case DRM_FORMAT_XBGR2101010:
3009                 dspcntr |= DISPPLANE_RGBX101010;
3010                 break;
3011         default:
3012                 MISSING_CASE(fb->format->format);
3013                 return 0;
3014         }
3015
3016         if (INTEL_GEN(dev_priv) >= 4 &&
3017             fb->modifier == I915_FORMAT_MOD_X_TILED)
3018                 dspcntr |= DISPPLANE_TILED;
3019
3020         if (rotation & DRM_ROTATE_180)
3021                 dspcntr |= DISPPLANE_ROTATE_180;
3022
3023         if (rotation & DRM_REFLECT_X)
3024                 dspcntr |= DISPPLANE_MIRROR;
3025
3026         return dspcntr;
3027 }
3028
3029 static int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
3030 {
3031         struct drm_i915_private *dev_priv =
3032                 to_i915(plane_state->base.plane->dev);
3033         int src_x = plane_state->base.src.x1 >> 16;
3034         int src_y = plane_state->base.src.y1 >> 16;
3035         u32 offset;
3036
3037         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3038
3039         if (INTEL_GEN(dev_priv) >= 4)
3040                 offset = intel_compute_tile_offset(&src_x, &src_y,
3041                                                    plane_state, 0);
3042         else
3043                 offset = 0;
3044
3045         /* HSW/BDW do this automagically in hardware */
3046         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3047                 unsigned int rotation = plane_state->base.rotation;
3048                 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3049                 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3050
3051                 if (rotation & DRM_ROTATE_180) {
3052                         src_x += src_w - 1;
3053                         src_y += src_h - 1;
3054                 } else if (rotation & DRM_REFLECT_X) {
3055                         src_x += src_w - 1;
3056                 }
3057         }
3058
3059         plane_state->main.offset = offset;
3060         plane_state->main.x = src_x;
3061         plane_state->main.y = src_y;
3062
3063         return 0;
3064 }
3065
3066 static void i9xx_update_primary_plane(struct drm_plane *primary,
3067                                       const struct intel_crtc_state *crtc_state,
3068                                       const struct intel_plane_state *plane_state)
3069 {
3070         struct drm_i915_private *dev_priv = to_i915(primary->dev);
3071         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3072         struct drm_framebuffer *fb = plane_state->base.fb;
3073         int plane = intel_crtc->plane;
3074         u32 linear_offset;
3075         u32 dspcntr = plane_state->ctl;
3076         i915_reg_t reg = DSPCNTR(plane);
3077         int x = plane_state->main.x;
3078         int y = plane_state->main.y;
3079         unsigned long irqflags;
3080
3081         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3082
3083         if (INTEL_GEN(dev_priv) >= 4)
3084                 intel_crtc->dspaddr_offset = plane_state->main.offset;
3085         else
3086                 intel_crtc->dspaddr_offset = linear_offset;
3087
3088         intel_crtc->adjusted_x = x;
3089         intel_crtc->adjusted_y = y;
3090
3091         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3092
3093         if (INTEL_GEN(dev_priv) < 4) {
3094                 /* pipesrc and dspsize control the size that is scaled from,
3095                  * which should always be the user's requested size.
3096                  */
3097                 I915_WRITE_FW(DSPSIZE(plane),
3098                               ((crtc_state->pipe_src_h - 1) << 16) |
3099                               (crtc_state->pipe_src_w - 1));
3100                 I915_WRITE_FW(DSPPOS(plane), 0);
3101         } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
3102                 I915_WRITE_FW(PRIMSIZE(plane),
3103                               ((crtc_state->pipe_src_h - 1) << 16) |
3104                               (crtc_state->pipe_src_w - 1));
3105                 I915_WRITE_FW(PRIMPOS(plane), 0);
3106                 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
3107         }
3108
3109         I915_WRITE_FW(reg, dspcntr);
3110
3111         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3112         if (INTEL_GEN(dev_priv) >= 4) {
3113                 I915_WRITE_FW(DSPSURF(plane),
3114                               intel_plane_ggtt_offset(plane_state) +
3115                               intel_crtc->dspaddr_offset);
3116                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3117                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3118         } else {
3119                 I915_WRITE_FW(DSPADDR(plane),
3120                               intel_plane_ggtt_offset(plane_state) +
3121                               intel_crtc->dspaddr_offset);
3122         }
3123         POSTING_READ_FW(reg);
3124
3125         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3126 }
3127
3128 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3129                                        struct drm_crtc *crtc)
3130 {
3131         struct drm_device *dev = crtc->dev;
3132         struct drm_i915_private *dev_priv = to_i915(dev);
3133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3134         int plane = intel_crtc->plane;
3135         unsigned long irqflags;
3136
3137         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3138
3139         I915_WRITE_FW(DSPCNTR(plane), 0);
3140         if (INTEL_INFO(dev_priv)->gen >= 4)
3141                 I915_WRITE_FW(DSPSURF(plane), 0);
3142         else
3143                 I915_WRITE_FW(DSPADDR(plane), 0);
3144         POSTING_READ_FW(DSPCNTR(plane));
3145
3146         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3147 }
3148
3149 static void ironlake_update_primary_plane(struct drm_plane *primary,
3150                                           const struct intel_crtc_state *crtc_state,
3151                                           const struct intel_plane_state *plane_state)
3152 {
3153         struct drm_device *dev = primary->dev;
3154         struct drm_i915_private *dev_priv = to_i915(dev);
3155         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3156         struct drm_framebuffer *fb = plane_state->base.fb;
3157         int plane = intel_crtc->plane;
3158         u32 linear_offset;
3159         u32 dspcntr = plane_state->ctl;
3160         i915_reg_t reg = DSPCNTR(plane);
3161         int x = plane_state->main.x;
3162         int y = plane_state->main.y;
3163         unsigned long irqflags;
3164
3165         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3166
3167         intel_crtc->dspaddr_offset = plane_state->main.offset;
3168
3169         intel_crtc->adjusted_x = x;
3170         intel_crtc->adjusted_y = y;
3171
3172         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3173
3174         I915_WRITE_FW(reg, dspcntr);
3175
3176         I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3177         I915_WRITE_FW(DSPSURF(plane),
3178                       intel_plane_ggtt_offset(plane_state) +
3179                       intel_crtc->dspaddr_offset);
3180         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3181                 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3182         } else {
3183                 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3184                 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
3185         }
3186         POSTING_READ_FW(reg);
3187
3188         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3189 }
3190
3191 static u32
3192 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
3193 {
3194         if (fb->modifier == DRM_FORMAT_MOD_NONE)
3195                 return 64;
3196         else
3197                 return intel_tile_width_bytes(fb, plane);
3198 }
3199
3200 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3201 {
3202         struct drm_device *dev = intel_crtc->base.dev;
3203         struct drm_i915_private *dev_priv = to_i915(dev);
3204
3205         I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3206         I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3207         I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3208 }
3209
3210 /*
3211  * This function detaches (aka. unbinds) unused scalers in hardware
3212  */
3213 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3214 {
3215         struct intel_crtc_scaler_state *scaler_state;
3216         int i;
3217
3218         scaler_state = &intel_crtc->config->scaler_state;
3219
3220         /* loop through and disable scalers that aren't in use */
3221         for (i = 0; i < intel_crtc->num_scalers; i++) {
3222                 if (!scaler_state->scalers[i].in_use)
3223                         skl_detach_scaler(intel_crtc, i);
3224         }
3225 }
3226
3227 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3228                      unsigned int rotation)
3229 {
3230         u32 stride;
3231
3232         if (plane >= fb->format->num_planes)
3233                 return 0;
3234
3235         stride = intel_fb_pitch(fb, plane, rotation);
3236
3237         /*
3238          * The stride is either expressed as a multiple of 64 bytes chunks for
3239          * linear buffers or in number of tiles for tiled buffers.
3240          */
3241         if (drm_rotation_90_or_270(rotation))
3242                 stride /= intel_tile_height(fb, plane);
3243         else
3244                 stride /= intel_fb_stride_alignment(fb, plane);
3245
3246         return stride;
3247 }
3248
3249 static u32 skl_plane_ctl_format(uint32_t pixel_format)
3250 {
3251         switch (pixel_format) {
3252         case DRM_FORMAT_C8:
3253                 return PLANE_CTL_FORMAT_INDEXED;
3254         case DRM_FORMAT_RGB565:
3255                 return PLANE_CTL_FORMAT_RGB_565;
3256         case DRM_FORMAT_XBGR8888:
3257                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3258         case DRM_FORMAT_XRGB8888:
3259                 return PLANE_CTL_FORMAT_XRGB_8888;
3260         /*
3261          * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3262          * to be already pre-multiplied. We need to add a knob (or a different
3263          * DRM_FORMAT) for user-space to configure that.
3264          */
3265         case DRM_FORMAT_ABGR8888:
3266                 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3267                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3268         case DRM_FORMAT_ARGB8888:
3269                 return PLANE_CTL_FORMAT_XRGB_8888 |
3270                         PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3271         case DRM_FORMAT_XRGB2101010:
3272                 return PLANE_CTL_FORMAT_XRGB_2101010;
3273         case DRM_FORMAT_XBGR2101010:
3274                 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3275         case DRM_FORMAT_YUYV:
3276                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3277         case DRM_FORMAT_YVYU:
3278                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3279         case DRM_FORMAT_UYVY:
3280                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3281         case DRM_FORMAT_VYUY:
3282                 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3283         default:
3284                 MISSING_CASE(pixel_format);
3285         }
3286
3287         return 0;
3288 }
3289
3290 static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3291 {
3292         switch (fb_modifier) {
3293         case DRM_FORMAT_MOD_NONE:
3294                 break;
3295         case I915_FORMAT_MOD_X_TILED:
3296                 return PLANE_CTL_TILED_X;
3297         case I915_FORMAT_MOD_Y_TILED:
3298                 return PLANE_CTL_TILED_Y;
3299         case I915_FORMAT_MOD_Yf_TILED:
3300                 return PLANE_CTL_TILED_YF;
3301         default:
3302                 MISSING_CASE(fb_modifier);
3303         }
3304
3305         return 0;
3306 }
3307
3308 static u32 skl_plane_ctl_rotation(unsigned int rotation)
3309 {
3310         switch (rotation) {
3311         case DRM_ROTATE_0:
3312                 break;
3313         /*
3314          * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3315          * while i915 HW rotation is clockwise, thats why this swapping.
3316          */
3317         case DRM_ROTATE_90:
3318                 return PLANE_CTL_ROTATE_270;
3319         case DRM_ROTATE_180:
3320                 return PLANE_CTL_ROTATE_180;
3321         case DRM_ROTATE_270:
3322                 return PLANE_CTL_ROTATE_90;
3323         default:
3324                 MISSING_CASE(rotation);
3325         }
3326
3327         return 0;
3328 }
3329
3330 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3331                   const struct intel_plane_state *plane_state)
3332 {
3333         struct drm_i915_private *dev_priv =
3334                 to_i915(plane_state->base.plane->dev);
3335         const struct drm_framebuffer *fb = plane_state->base.fb;
3336         unsigned int rotation = plane_state->base.rotation;
3337         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
3338         u32 plane_ctl;
3339
3340         plane_ctl = PLANE_CTL_ENABLE;
3341
3342         if (!IS_GEMINILAKE(dev_priv)) {
3343                 plane_ctl |=
3344                         PLANE_CTL_PIPE_GAMMA_ENABLE |
3345                         PLANE_CTL_PIPE_CSC_ENABLE |
3346                         PLANE_CTL_PLANE_GAMMA_DISABLE;
3347         }
3348
3349         plane_ctl |= skl_plane_ctl_format(fb->format->format);
3350         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3351         plane_ctl |= skl_plane_ctl_rotation(rotation);
3352
3353         if (key->flags & I915_SET_COLORKEY_DESTINATION)
3354                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3355         else if (key->flags & I915_SET_COLORKEY_SOURCE)
3356                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3357
3358         return plane_ctl;
3359 }
3360
3361 static void skylake_update_primary_plane(struct drm_plane *plane,
3362                                          const struct intel_crtc_state *crtc_state,
3363                                          const struct intel_plane_state *plane_state)
3364 {
3365         struct drm_device *dev = plane->dev;
3366         struct drm_i915_private *dev_priv = to_i915(dev);
3367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3368         struct drm_framebuffer *fb = plane_state->base.fb;
3369         enum plane_id plane_id = to_intel_plane(plane)->id;
3370         enum pipe pipe = to_intel_plane(plane)->pipe;
3371         u32 plane_ctl = plane_state->ctl;
3372         unsigned int rotation = plane_state->base.rotation;
3373         u32 stride = skl_plane_stride(fb, 0, rotation);
3374         u32 surf_addr = plane_state->main.offset;
3375         int scaler_id = plane_state->scaler_id;
3376         int src_x = plane_state->main.x;
3377         int src_y = plane_state->main.y;
3378         int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3379         int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3380         int dst_x = plane_state->base.dst.x1;
3381         int dst_y = plane_state->base.dst.y1;
3382         int dst_w = drm_rect_width(&plane_state->base.dst);
3383         int dst_h = drm_rect_height(&plane_state->base.dst);
3384         unsigned long irqflags;
3385
3386         /* Sizes are 0 based */
3387         src_w--;
3388         src_h--;
3389         dst_w--;
3390         dst_h--;
3391
3392         intel_crtc->dspaddr_offset = surf_addr;
3393
3394         intel_crtc->adjusted_x = src_x;
3395         intel_crtc->adjusted_y = src_y;
3396
3397         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3398
3399         if (IS_GEMINILAKE(dev_priv)) {
3400                 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3401                               PLANE_COLOR_PIPE_GAMMA_ENABLE |
3402                               PLANE_COLOR_PIPE_CSC_ENABLE |
3403                               PLANE_COLOR_PLANE_GAMMA_DISABLE);
3404         }
3405
3406         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3407         I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3408         I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3409         I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
3410
3411         if (scaler_id >= 0) {
3412                 uint32_t ps_ctrl = 0;
3413
3414                 WARN_ON(!dst_w || !dst_h);
3415                 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
3416                         crtc_state->scaler_state.scalers[scaler_id].mode;
3417                 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3418                 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3419                 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3420                 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3421                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
3422         } else {
3423                 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
3424         }
3425
3426         I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3427                       intel_plane_ggtt_offset(plane_state) + surf_addr);
3428
3429         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3430
3431         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3432 }
3433
3434 static void skylake_disable_primary_plane(struct drm_plane *primary,
3435                                           struct drm_crtc *crtc)
3436 {
3437         struct drm_device *dev = crtc->dev;
3438         struct drm_i915_private *dev_priv = to_i915(dev);
3439         enum plane_id plane_id = to_intel_plane(primary)->id;
3440         enum pipe pipe = to_intel_plane(primary)->pipe;
3441         unsigned long irqflags;
3442
3443         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3444
3445         I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3446         I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3447         POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3448
3449         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
3450 }
3451
3452 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3453 static int
3454 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3455                            int x, int y, enum mode_set_atomic state)
3456 {
3457         /* Support for kgdboc is disabled, this needs a major rework. */
3458         DRM_ERROR("legacy panic handler not supported any more.\n");
3459
3460         return -ENODEV;
3461 }
3462
3463 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3464 {
3465         struct intel_crtc *crtc;
3466
3467         for_each_intel_crtc(&dev_priv->drm, crtc)
3468                 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3469 }
3470
3471 static void intel_update_primary_planes(struct drm_device *dev)
3472 {
3473         struct drm_crtc *crtc;
3474
3475         for_each_crtc(dev, crtc) {
3476                 struct intel_plane *plane = to_intel_plane(crtc->primary);
3477                 struct intel_plane_state *plane_state =
3478                         to_intel_plane_state(plane->base.state);
3479
3480                 if (plane_state->base.visible) {
3481                         trace_intel_update_plane(&plane->base,
3482                                                  to_intel_crtc(crtc));
3483
3484                         plane->update_plane(&plane->base,
3485                                             to_intel_crtc_state(crtc->state),
3486                                             plane_state);
3487                 }
3488         }
3489 }
3490
3491 static int
3492 __intel_display_resume(struct drm_device *dev,
3493                        struct drm_atomic_state *state,
3494                        struct drm_modeset_acquire_ctx *ctx)
3495 {
3496         struct drm_crtc_state *crtc_state;
3497         struct drm_crtc *crtc;
3498         int i, ret;
3499
3500         intel_modeset_setup_hw_state(dev);
3501         i915_redisable_vga(to_i915(dev));
3502
3503         if (!state)
3504                 return 0;
3505
3506         /*
3507          * We've duplicated the state, pointers to the old state are invalid.
3508          *
3509          * Don't attempt to use the old state until we commit the duplicated state.
3510          */
3511         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
3512                 /*
3513                  * Force recalculation even if we restore
3514                  * current state. With fast modeset this may not result
3515                  * in a modeset when the state is compatible.
3516                  */
3517                 crtc_state->mode_changed = true;
3518         }
3519
3520         /* ignore any reset values/BIOS leftovers in the WM registers */
3521         if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3522                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3523
3524         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
3525
3526         WARN_ON(ret == -EDEADLK);
3527         return ret;
3528 }
3529
3530 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3531 {
3532         return intel_has_gpu_reset(dev_priv) &&
3533                 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3534 }
3535
3536 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3537 {
3538         struct drm_device *dev = &dev_priv->drm;
3539         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3540         struct drm_atomic_state *state;
3541         int ret;
3542
3543         /*
3544          * Need mode_config.mutex so that we don't
3545          * trample ongoing ->detect() and whatnot.
3546          */
3547         mutex_lock(&dev->mode_config.mutex);
3548         drm_modeset_acquire_init(ctx, 0);
3549         while (1) {
3550                 ret = drm_modeset_lock_all_ctx(dev, ctx);
3551                 if (ret != -EDEADLK)
3552                         break;
3553
3554                 drm_modeset_backoff(ctx);
3555         }
3556
3557         /* reset doesn't touch the display, but flips might get nuked anyway, */
3558         if (!i915.force_reset_modeset_test &&
3559             !gpu_reset_clobbers_display(dev_priv))
3560                 return;
3561
3562         /*
3563          * Disabling the crtcs gracefully seems nicer. Also the
3564          * g33 docs say we should at least disable all the planes.
3565          */
3566         state = drm_atomic_helper_duplicate_state(dev, ctx);
3567         if (IS_ERR(state)) {
3568                 ret = PTR_ERR(state);
3569                 DRM_ERROR("Duplicating state failed with %i\n", ret);
3570                 return;
3571         }
3572
3573         ret = drm_atomic_helper_disable_all(dev, ctx);
3574         if (ret) {
3575                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3576                 drm_atomic_state_put(state);
3577                 return;
3578         }
3579
3580         dev_priv->modeset_restore_state = state;
3581         state->acquire_ctx = ctx;
3582 }
3583
3584 void intel_finish_reset(struct drm_i915_private *dev_priv)
3585 {
3586         struct drm_device *dev = &dev_priv->drm;
3587         struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3588         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3589         int ret;
3590
3591         /*
3592          * Flips in the rings will be nuked by the reset,
3593          * so complete all pending flips so that user space
3594          * will get its events and not get stuck.
3595          */
3596         intel_complete_page_flips(dev_priv);
3597
3598         dev_priv->modeset_restore_state = NULL;
3599
3600         /* reset doesn't touch the display */
3601         if (!gpu_reset_clobbers_display(dev_priv)) {
3602                 if (!state) {
3603                         /*
3604                          * Flips in the rings have been nuked by the reset,
3605                          * so update the base address of all primary
3606                          * planes to the the last fb to make sure we're
3607                          * showing the correct fb after a reset.
3608                          *
3609                          * FIXME: Atomic will make this obsolete since we won't schedule
3610                          * CS-based flips (which might get lost in gpu resets) any more.
3611                          */
3612                         intel_update_primary_planes(dev);
3613                 } else {
3614                         ret = __intel_display_resume(dev, state, ctx);
3615                         if (ret)
3616                                 DRM_ERROR("Restoring old state failed with %i\n", ret);
3617                 }
3618         } else {
3619                 /*
3620                  * The display has been reset as well,
3621                  * so need a full re-initialization.
3622                  */
3623                 intel_runtime_pm_disable_interrupts(dev_priv);
3624                 intel_runtime_pm_enable_interrupts(dev_priv);
3625
3626                 intel_pps_unlock_regs_wa(dev_priv);
3627                 intel_modeset_init_hw(dev);
3628
3629                 spin_lock_irq(&dev_priv->irq_lock);
3630                 if (dev_priv->display.hpd_irq_setup)
3631                         dev_priv->display.hpd_irq_setup(dev_priv);
3632                 spin_unlock_irq(&dev_priv->irq_lock);
3633
3634                 ret = __intel_display_resume(dev, state, ctx);
3635                 if (ret)
3636                         DRM_ERROR("Restoring old state failed with %i\n", ret);
3637
3638                 intel_hpd_init(dev_priv);
3639         }
3640
3641         if (state)
3642                 drm_atomic_state_put(state);
3643         drm_modeset_drop_locks(ctx);
3644         drm_modeset_acquire_fini(ctx);
3645         mutex_unlock(&dev->mode_config.mutex);
3646 }
3647
3648 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3649 {
3650         struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3651
3652         if (i915_reset_backoff(error))
3653                 return true;
3654
3655         if (crtc->reset_count != i915_reset_count(error))
3656                 return true;
3657
3658         return false;
3659 }
3660
3661 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3662 {
3663         struct drm_device *dev = crtc->dev;
3664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3665         bool pending;
3666
3667         if (abort_flip_on_reset(intel_crtc))
3668                 return false;
3669
3670         spin_lock_irq(&dev->event_lock);
3671         pending = to_intel_crtc(crtc)->flip_work != NULL;
3672         spin_unlock_irq(&dev->event_lock);
3673
3674         return pending;
3675 }
3676
3677 static void intel_update_pipe_config(struct intel_crtc *crtc,
3678                                      struct intel_crtc_state *old_crtc_state)
3679 {
3680         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3681         struct intel_crtc_state *pipe_config =
3682                 to_intel_crtc_state(crtc->base.state);
3683
3684         /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3685         crtc->base.mode = crtc->base.state->mode;
3686
3687         /*
3688          * Update pipe size and adjust fitter if needed: the reason for this is
3689          * that in compute_mode_changes we check the native mode (not the pfit
3690          * mode) to see if we can flip rather than do a full mode set. In the
3691          * fastboot case, we'll flip, but if we don't update the pipesrc and
3692          * pfit state, we'll end up with a big fb scanned out into the wrong
3693          * sized surface.
3694          */
3695
3696         I915_WRITE(PIPESRC(crtc->pipe),
3697                    ((pipe_config->pipe_src_w - 1) << 16) |
3698                    (pipe_config->pipe_src_h - 1));
3699
3700         /* on skylake this is done by detaching scalers */
3701         if (INTEL_GEN(dev_priv) >= 9) {
3702                 skl_detach_scalers(crtc);
3703
3704                 if (pipe_config->pch_pfit.enabled)
3705                         skylake_pfit_enable(crtc);
3706         } else if (HAS_PCH_SPLIT(dev_priv)) {
3707                 if (pipe_config->pch_pfit.enabled)
3708                         ironlake_pfit_enable(crtc);
3709                 else if (old_crtc_state->pch_pfit.enabled)
3710                         ironlake_pfit_disable(crtc, true);
3711         }
3712 }
3713
3714 static void intel_fdi_normal_train(struct intel_crtc *crtc)
3715 {
3716         struct drm_device *dev = crtc->base.dev;
3717         struct drm_i915_private *dev_priv = to_i915(dev);
3718         int pipe = crtc->pipe;
3719         i915_reg_t reg;
3720         u32 temp;
3721
3722         /* enable normal train */
3723         reg = FDI_TX_CTL(pipe);
3724         temp = I915_READ(reg);
3725         if (IS_IVYBRIDGE(dev_priv)) {
3726                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3727                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3728         } else {
3729                 temp &= ~FDI_LINK_TRAIN_NONE;
3730                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3731         }
3732         I915_WRITE(reg, temp);
3733
3734         reg = FDI_RX_CTL(pipe);
3735         temp = I915_READ(reg);
3736         if (HAS_PCH_CPT(dev_priv)) {
3737                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3738                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3739         } else {
3740                 temp &= ~FDI_LINK_TRAIN_NONE;
3741                 temp |= FDI_LINK_TRAIN_NONE;
3742         }
3743         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3744
3745         /* wait one idle pattern time */
3746         POSTING_READ(reg);
3747         udelay(1000);
3748
3749         /* IVB wants error correction enabled */
3750         if (IS_IVYBRIDGE(dev_priv))
3751                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3752                            FDI_FE_ERRC_ENABLE);
3753 }
3754
3755 /* The FDI link training functions for ILK/Ibexpeak. */
3756 static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3757                                     const struct intel_crtc_state *crtc_state)
3758 {
3759         struct drm_device *dev = crtc->base.dev;
3760         struct drm_i915_private *dev_priv = to_i915(dev);
3761         int pipe = crtc->pipe;
3762         i915_reg_t reg;
3763         u32 temp, tries;
3764
3765         /* FDI needs bits from pipe first */
3766         assert_pipe_enabled(dev_priv, pipe);
3767
3768         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3769            for train result */
3770         reg = FDI_RX_IMR(pipe);
3771         temp = I915_READ(reg);
3772         temp &= ~FDI_RX_SYMBOL_LOCK;
3773         temp &= ~FDI_RX_BIT_LOCK;
3774         I915_WRITE(reg, temp);
3775         I915_READ(reg);
3776         udelay(150);
3777
3778         /* enable CPU FDI TX and PCH FDI RX */
3779         reg = FDI_TX_CTL(pipe);
3780         temp = I915_READ(reg);
3781         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3782         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3783         temp &= ~FDI_LINK_TRAIN_NONE;
3784         temp |= FDI_LINK_TRAIN_PATTERN_1;
3785         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3786
3787         reg = FDI_RX_CTL(pipe);
3788         temp = I915_READ(reg);
3789         temp &= ~FDI_LINK_TRAIN_NONE;
3790         temp |= FDI_LINK_TRAIN_PATTERN_1;
3791         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3792
3793         POSTING_READ(reg);
3794         udelay(150);
3795
3796         /* Ironlake workaround, enable clock pointer after FDI enable*/
3797         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3798         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3799                    FDI_RX_PHASE_SYNC_POINTER_EN);
3800
3801         reg = FDI_RX_IIR(pipe);
3802         for (tries = 0; tries < 5; tries++) {
3803                 temp = I915_READ(reg);
3804                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3805
3806                 if ((temp & FDI_RX_BIT_LOCK)) {
3807                         DRM_DEBUG_KMS("FDI train 1 done.\n");
3808                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3809                         break;
3810                 }
3811         }
3812         if (tries == 5)
3813                 DRM_ERROR("FDI train 1 fail!\n");
3814
3815         /* Train 2 */
3816         reg = FDI_TX_CTL(pipe);
3817         temp = I915_READ(reg);
3818         temp &= ~FDI_LINK_TRAIN_NONE;
3819         temp |= FDI_LINK_TRAIN_PATTERN_2;
3820         I915_WRITE(reg, temp);
3821
3822         reg = FDI_RX_CTL(pipe);
3823         temp = I915_READ(reg);
3824         temp &= ~FDI_LINK_TRAIN_NONE;
3825         temp |= FDI_LINK_TRAIN_PATTERN_2;
3826         I915_WRITE(reg, temp);
3827
3828         POSTING_READ(reg);
3829         udelay(150);
3830
3831         reg = FDI_RX_IIR(pipe);
3832         for (tries = 0; tries < 5; tries++) {
3833                 temp = I915_READ(reg);
3834                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3835
3836                 if (temp & FDI_RX_SYMBOL_LOCK) {
3837                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3838                         DRM_DEBUG_KMS("FDI train 2 done.\n");
3839                         break;
3840                 }
3841         }
3842         if (tries == 5)
3843                 DRM_ERROR("FDI train 2 fail!\n");
3844
3845         DRM_DEBUG_KMS("FDI train done\n");
3846
3847 }
3848
3849 static const int snb_b_fdi_train_param[] = {
3850         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3851         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3852         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3853         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3854 };
3855
3856 /* The FDI link training functions for SNB/Cougarpoint. */
3857 static void gen6_fdi_link_train(struct intel_crtc *crtc,
3858                                 const struct intel_crtc_state *crtc_state)
3859 {
3860         struct drm_device *dev = crtc->base.dev;
3861         struct drm_i915_private *dev_priv = to_i915(dev);
3862         int pipe = crtc->pipe;
3863         i915_reg_t reg;
3864         u32 temp, i, retry;
3865
3866         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3867            for train result */
3868         reg = FDI_RX_IMR(pipe);
3869         temp = I915_READ(reg);
3870         temp &= ~FDI_RX_SYMBOL_LOCK;
3871         temp &= ~FDI_RX_BIT_LOCK;
3872         I915_WRITE(reg, temp);
3873
3874         POSTING_READ(reg);
3875         udelay(150);
3876
3877         /* enable CPU FDI TX and PCH FDI RX */
3878         reg = FDI_TX_CTL(pipe);
3879         temp = I915_READ(reg);
3880         temp &= ~FDI_DP_PORT_WIDTH_MASK;
3881         temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
3882         temp &= ~FDI_LINK_TRAIN_NONE;
3883         temp |= FDI_LINK_TRAIN_PATTERN_1;
3884         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3885         /* SNB-B */
3886         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3887         I915_WRITE(reg, temp | FDI_TX_ENABLE);
3888
3889         I915_WRITE(FDI_RX_MISC(pipe),
3890                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3891
3892         reg = FDI_RX_CTL(pipe);
3893         temp = I915_READ(reg);
3894         if (HAS_PCH_CPT(dev_priv)) {
3895                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3896                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3897         } else {
3898                 temp &= ~FDI_LINK_TRAIN_NONE;
3899                 temp |= FDI_LINK_TRAIN_PATTERN_1;
3900         }
3901         I915_WRITE(reg, temp | FDI_RX_ENABLE);
3902
3903         POSTING_READ(reg);
3904         udelay(150);
3905
3906         for (i = 0; i < 4; i++) {
3907                 reg = FDI_TX_CTL(pipe);
3908                 temp = I915_READ(reg);
3909                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3910                 temp |= snb_b_fdi_train_param[i];
3911                 I915_WRITE(reg, temp);
3912
3913                 POSTING_READ(reg);
3914                 udelay(500);
3915
3916                 for (retry = 0; retry < 5; retry++) {
3917                         reg = FDI_RX_IIR(pipe);
3918                         temp = I915_READ(reg);
3919                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3920                         if (temp & FDI_RX_BIT_LOCK) {
3921                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3922                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
3923                                 break;
3924                         }
3925                         udelay(50);
3926                 }
3927                 if (retry < 5)
3928                         break;
3929         }
3930         if (i == 4)
3931                 DRM_ERROR("FDI train 1 fail!\n");
3932
3933         /* Train 2 */
3934         reg = FDI_TX_CTL(pipe);
3935         temp = I915_READ(reg);
3936         temp &= ~FDI_LINK_TRAIN_NONE;
3937         temp |= FDI_LINK_TRAIN_PATTERN_2;
3938         if (IS_GEN6(dev_priv)) {
3939                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3940                 /* SNB-B */
3941                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3942         }
3943         I915_WRITE(reg, temp);
3944
3945         reg = FDI_RX_CTL(pipe);
3946         temp = I915_READ(reg);
3947         if (HAS_PCH_CPT(dev_priv)) {
3948                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3949                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3950         } else {
3951                 temp &= ~FDI_LINK_TRAIN_NONE;
3952                 temp |= FDI_LINK_TRAIN_PATTERN_2;
3953         }
3954         I915_WRITE(reg, temp);
3955
3956         POSTING_READ(reg);
3957         udelay(150);
3958
3959         for (i = 0; i < 4; i++) {
3960                 reg = FDI_TX_CTL(pipe);
3961                 temp = I915_READ(reg);
3962                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3963                 temp |= snb_b_fdi_train_param[i];
3964                 I915_WRITE(reg, temp);
3965
3966                 POSTING_READ(reg);
3967                 udelay(500);
3968
3969                 for (retry = 0; retry < 5; retry++) {
3970                         reg = FDI_RX_IIR(pipe);
3971                         temp = I915_READ(reg);
3972                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3973                         if (temp & FDI_RX_SYMBOL_LOCK) {
3974                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3975                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
3976                                 break;
3977                         }
3978                         udelay(50);
3979                 }
3980                 if (retry < 5)
3981                         break;
3982         }
3983         if (i == 4)
3984                 DRM_ERROR("FDI train 2 fail!\n");
3985
3986         DRM_DEBUG_KMS("FDI train done.\n");
3987 }
3988
3989 /* Manual link training for Ivy Bridge A0 parts */
3990 static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3991                                       const struct intel_crtc_state *crtc_state)
3992 {
3993         struct drm_device *dev = crtc->base.dev;
3994         struct drm_i915_private *dev_priv = to_i915(dev);
3995         int pipe = crtc->pipe;
3996         i915_reg_t reg;
3997         u32 temp, i, j;
3998
3999         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4000            for train result */
4001         reg = FDI_RX_IMR(pipe);
4002         temp = I915_READ(reg);
4003         temp &= ~FDI_RX_SYMBOL_LOCK;
4004         temp &= ~FDI_RX_BIT_LOCK;
4005         I915_WRITE(reg, temp);
4006
4007         POSTING_READ(reg);
4008         udelay(150);
4009
4010         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4011                       I915_READ(FDI_RX_IIR(pipe)));
4012
4013         /* Try each vswing and preemphasis setting twice before moving on */
4014         for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4015                 /* disable first in case we need to retry */
4016                 reg = FDI_TX_CTL(pipe);
4017                 temp = I915_READ(reg);
4018                 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4019                 temp &= ~FDI_TX_ENABLE;
4020                 I915_WRITE(reg, temp);
4021
4022                 reg = FDI_RX_CTL(pipe);
4023                 temp = I915_READ(reg);
4024                 temp &= ~FDI_LINK_TRAIN_AUTO;
4025                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4026                 temp &= ~FDI_RX_ENABLE;
4027                 I915_WRITE(reg, temp);
4028
4029                 /* enable CPU FDI TX and PCH FDI RX */
4030                 reg = FDI_TX_CTL(pipe);
4031                 temp = I915_READ(reg);
4032                 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4033                 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
4034                 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4035                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4036                 temp |= snb_b_fdi_train_param[j/2];
4037                 temp |= FDI_COMPOSITE_SYNC;
4038                 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4039
4040                 I915_WRITE(FDI_RX_MISC(pipe),
4041                            FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4042
4043                 reg = FDI_RX_CTL(pipe);
4044                 temp = I915_READ(reg);
4045                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4046                 temp |= FDI_COMPOSITE_SYNC;
4047                 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4048
4049                 POSTING_READ(reg);
4050                 udelay(1); /* should be 0.5us */
4051
4052                 for (i = 0; i < 4; i++) {
4053                         reg = FDI_RX_IIR(pipe);
4054                         temp = I915_READ(reg);
4055                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4056
4057                         if (temp & FDI_RX_BIT_LOCK ||
4058                             (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4059                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4060                                 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4061                                               i);
4062                                 break;
4063                         }
4064                         udelay(1); /* should be 0.5us */
4065                 }
4066                 if (i == 4) {
4067                         DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4068                         continue;
4069                 }
4070
4071                 /* Train 2 */
4072                 reg = FDI_TX_CTL(pipe);
4073                 temp = I915_READ(reg);
4074                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4075                 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4076                 I915_WRITE(reg, temp);
4077
4078                 reg = FDI_RX_CTL(pipe);
4079                 temp = I915_READ(reg);
4080                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4081                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4082                 I915_WRITE(reg, temp);
4083
4084                 POSTING_READ(reg);
4085                 udelay(2); /* should be 1.5us */
4086
4087                 for (i = 0; i < 4; i++) {
4088                         reg = FDI_RX_IIR(pipe);
4089                         temp = I915_READ(reg);
4090                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4091
4092                         if (temp & FDI_RX_SYMBOL_LOCK ||
4093                             (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4094                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4095                                 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4096                                               i);
4097                                 goto train_done;
4098                         }
4099                         udelay(2); /* should be 1.5us */
4100                 }
4101                 if (i == 4)
4102                         DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4103         }
4104
4105 train_done:
4106         DRM_DEBUG_KMS("FDI train done.\n");
4107 }
4108
4109 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4110 {
4111         struct drm_device *dev = intel_crtc->base.dev;
4112         struct drm_i915_private *dev_priv = to_i915(dev);
4113         int pipe = intel_crtc->pipe;
4114         i915_reg_t reg;
4115         u32 temp;
4116
4117         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4118         reg = FDI_RX_CTL(pipe);
4119         temp = I915_READ(reg);
4120         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4121         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4122         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4123         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4124
4125         POSTING_READ(reg);
4126         udelay(200);
4127
4128         /* Switch from Rawclk to PCDclk */
4129         temp = I915_READ(reg);
4130         I915_WRITE(reg, temp | FDI_PCDCLK);
4131
4132         POSTING_READ(reg);
4133         udelay(200);
4134
4135         /* Enable CPU FDI TX PLL, always on for Ironlake */
4136         reg = FDI_TX_CTL(pipe);
4137         temp = I915_READ(reg);
4138         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4139                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4140
4141                 POSTING_READ(reg);
4142                 udelay(100);
4143         }
4144 }
4145
4146 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4147 {
4148         struct drm_device *dev = intel_crtc->base.dev;
4149         struct drm_i915_private *dev_priv = to_i915(dev);
4150         int pipe = intel_crtc->pipe;
4151         i915_reg_t reg;
4152         u32 temp;
4153
4154         /* Switch from PCDclk to Rawclk */
4155         reg = FDI_RX_CTL(pipe);
4156         temp = I915_READ(reg);
4157         I915_WRITE(reg, temp & ~FDI_PCDCLK);
4158
4159         /* Disable CPU FDI TX PLL */
4160         reg = FDI_TX_CTL(pipe);
4161         temp = I915_READ(reg);
4162         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4163
4164         POSTING_READ(reg);
4165         udelay(100);
4166
4167         reg = FDI_RX_CTL(pipe);
4168         temp = I915_READ(reg);
4169         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4170
4171         /* Wait for the clocks to turn off. */
4172         POSTING_READ(reg);
4173         udelay(100);
4174 }
4175
4176 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4177 {
4178         struct drm_device *dev = crtc->dev;
4179         struct drm_i915_private *dev_priv = to_i915(dev);
4180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4181         int pipe = intel_crtc->pipe;
4182         i915_reg_t reg;
4183         u32 temp;
4184
4185         /* disable CPU FDI tx and PCH FDI rx */
4186         reg = FDI_TX_CTL(pipe);
4187         temp = I915_READ(reg);
4188         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4189         POSTING_READ(reg);
4190
4191         reg = FDI_RX_CTL(pipe);
4192         temp = I915_READ(reg);
4193         temp &= ~(0x7 << 16);
4194         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4195         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4196
4197         POSTING_READ(reg);
4198         udelay(100);
4199
4200         /* Ironlake workaround, disable clock pointer after downing FDI */
4201         if (HAS_PCH_IBX(dev_priv))
4202                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4203
4204         /* still set train pattern 1 */
4205         reg = FDI_TX_CTL(pipe);
4206         temp = I915_READ(reg);
4207         temp &= ~FDI_LINK_TRAIN_NONE;
4208         temp |= FDI_LINK_TRAIN_PATTERN_1;
4209         I915_WRITE(reg, temp);
4210
4211         reg = FDI_RX_CTL(pipe);
4212         temp = I915_READ(reg);
4213         if (HAS_PCH_CPT(dev_priv)) {
4214                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4215                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4216         } else {
4217                 temp &= ~FDI_LINK_TRAIN_NONE;
4218                 temp |= FDI_LINK_TRAIN_PATTERN_1;
4219         }
4220         /* BPC in FDI rx is consistent with that in PIPECONF */
4221         temp &= ~(0x07 << 16);
4222         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4223         I915_WRITE(reg, temp);
4224
4225         POSTING_READ(reg);
4226         udelay(100);
4227 }
4228
4229 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
4230 {
4231         struct intel_crtc *crtc;
4232
4233         /* Note that we don't need to be called with mode_config.lock here
4234          * as our list of CRTC objects is static for the lifetime of the
4235          * device and so cannot disappear as we iterate. Similarly, we can
4236          * happily treat the predicates as racy, atomic checks as userspace
4237          * cannot claim and pin a new fb without at least acquring the
4238          * struct_mutex and so serialising with us.
4239          */
4240         for_each_intel_crtc(&dev_priv->drm, crtc) {
4241                 if (atomic_read(&crtc->unpin_work_count) == 0)
4242                         continue;
4243
4244                 if (crtc->flip_work)
4245                         intel_wait_for_vblank(dev_priv, crtc->pipe);
4246
4247                 return true;
4248         }
4249
4250         return false;
4251 }
4252
4253 static void page_flip_completed(struct intel_crtc *intel_crtc)
4254 {
4255         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4256         struct intel_flip_work *work = intel_crtc->flip_work;
4257
4258         intel_crtc->flip_work = NULL;
4259
4260         if (work->event)
4261                 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4262
4263         drm_crtc_vblank_put(&intel_crtc->base);
4264
4265         wake_up_all(&dev_priv->pending_flip_queue);
4266         trace_i915_flip_complete(intel_crtc->plane,
4267                                  work->pending_flip_obj);
4268
4269         queue_work(dev_priv->wq, &work->unpin_work);
4270 }
4271
4272 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4273 {
4274         struct drm_device *dev = crtc->dev;
4275         struct drm_i915_private *dev_priv = to_i915(dev);
4276         long ret;
4277
4278         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4279
4280         ret = wait_event_interruptible_timeout(
4281                                         dev_priv->pending_flip_queue,
4282                                         !intel_crtc_has_pending_flip(crtc),
4283                                         60*HZ);
4284
4285         if (ret < 0)
4286                 return ret;
4287
4288         if (ret == 0) {
4289                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4290                 struct intel_flip_work *work;
4291
4292                 spin_lock_irq(&dev->event_lock);
4293                 work = intel_crtc->flip_work;
4294                 if (work && !is_mmio_work(work)) {
4295                         WARN_ONCE(1, "Removing stuck page flip\n");
4296                         page_flip_completed(intel_crtc);
4297                 }
4298                 spin_unlock_irq(&dev->event_lock);
4299         }
4300
4301         return 0;
4302 }
4303
4304 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4305 {
4306         u32 temp;
4307
4308         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4309
4310         mutex_lock(&dev_priv->sb_lock);
4311
4312         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4313         temp |= SBI_SSCCTL_DISABLE;
4314         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4315
4316         mutex_unlock(&dev_priv->sb_lock);
4317 }
4318
4319 /* Program iCLKIP clock to the desired frequency */
4320 static void lpt_program_iclkip(struct intel_crtc *crtc)
4321 {
4322         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4323         int clock = crtc->config->base.adjusted_mode.crtc_clock;
4324         u32 divsel, phaseinc, auxdiv, phasedir = 0;
4325         u32 temp;
4326
4327         lpt_disable_iclkip(dev_priv);
4328
4329         /* The iCLK virtual clock root frequency is in MHz,
4330          * but the adjusted_mode->crtc_clock in in KHz. To get the
4331          * divisors, it is necessary to divide one by another, so we
4332          * convert the virtual clock precision to KHz here for higher
4333          * precision.
4334          */
4335         for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4336                 u32 iclk_virtual_root_freq = 172800 * 1000;
4337                 u32 iclk_pi_range = 64;
4338                 u32 desired_divisor;
4339
4340                 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4341                                                     clock << auxdiv);
4342                 divsel = (desired_divisor / iclk_pi_range) - 2;
4343                 phaseinc = desired_divisor % iclk_pi_range;
4344
4345                 /*
4346                  * Near 20MHz is a corner case which is
4347                  * out of range for the 7-bit divisor
4348                  */
4349                 if (divsel <= 0x7f)
4350                         break;
4351         }
4352
4353         /* This should not happen with any sane values */
4354         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4355                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4356         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4357                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4358
4359         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4360                         clock,
4361                         auxdiv,
4362                         divsel,
4363                         phasedir,
4364                         phaseinc);
4365
4366         mutex_lock(&dev_priv->sb_lock);
4367
4368         /* Program SSCDIVINTPHASE6 */
4369         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4370         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4371         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4372         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4373         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4374         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4375         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4376         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4377
4378         /* Program SSCAUXDIV */
4379         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4380         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4381         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4382         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4383
4384         /* Enable modulator and associated divider */
4385         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4386         temp &= ~SBI_SSCCTL_DISABLE;
4387         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4388
4389         mutex_unlock(&dev_priv->sb_lock);
4390
4391         /* Wait for initialization time */
4392         udelay(24);
4393
4394         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4395 }
4396
4397 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4398 {
4399         u32 divsel, phaseinc, auxdiv;
4400         u32 iclk_virtual_root_freq = 172800 * 1000;
4401         u32 iclk_pi_range = 64;
4402         u32 desired_divisor;
4403         u32 temp;
4404
4405         if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4406                 return 0;
4407
4408         mutex_lock(&dev_priv->sb_lock);
4409
4410         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4411         if (temp & SBI_SSCCTL_DISABLE) {
4412                 mutex_unlock(&dev_priv->sb_lock);
4413                 return 0;
4414         }
4415
4416         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4417         divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4418                 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4419         phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4420                 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4421
4422         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4423         auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4424                 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4425
4426         mutex_unlock(&dev_priv->sb_lock);
4427
4428         desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4429
4430         return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4431                                  desired_divisor << auxdiv);
4432 }
4433
4434 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4435                                                 enum pipe pch_transcoder)
4436 {
4437         struct drm_device *dev = crtc->base.dev;
4438         struct drm_i915_private *dev_priv = to_i915(dev);
4439         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4440
4441         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4442                    I915_READ(HTOTAL(cpu_transcoder)));
4443         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4444                    I915_READ(HBLANK(cpu_transcoder)));
4445         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4446                    I915_READ(HSYNC(cpu_transcoder)));
4447
4448         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4449                    I915_READ(VTOTAL(cpu_transcoder)));
4450         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4451                    I915_READ(VBLANK(cpu_transcoder)));
4452         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4453                    I915_READ(VSYNC(cpu_transcoder)));
4454         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4455                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
4456 }
4457
4458 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4459 {
4460         struct drm_i915_private *dev_priv = to_i915(dev);
4461         uint32_t temp;
4462
4463         temp = I915_READ(SOUTH_CHICKEN1);
4464         if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4465                 return;
4466
4467         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4468         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4469
4470         temp &= ~FDI_BC_BIFURCATION_SELECT;
4471         if (enable)
4472                 temp |= FDI_BC_BIFURCATION_SELECT;
4473
4474         DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4475         I915_WRITE(SOUTH_CHICKEN1, temp);
4476         POSTING_READ(SOUTH_CHICKEN1);
4477 }
4478
4479 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4480 {
4481         struct drm_device *dev = intel_crtc->base.dev;
4482
4483         switch (intel_crtc->pipe) {
4484         case PIPE_A:
4485                 break;
4486         case PIPE_B:
4487                 if (intel_crtc->config->fdi_lanes > 2)
4488                         cpt_set_fdi_bc_bifurcation(dev, false);
4489                 else
4490                         cpt_set_fdi_bc_bifurcation(dev, true);
4491
4492                 break;
4493         case PIPE_C:
4494                 cpt_set_fdi_bc_bifurcation(dev, true);
4495
4496                 break;
4497         default:
4498                 BUG();
4499         }
4500 }
4501
4502 /* Return which DP Port should be selected for Transcoder DP control */
4503 static enum port
4504 intel_trans_dp_port_sel(struct intel_crtc *crtc)
4505 {
4506         struct drm_device *dev = crtc->base.dev;
4507         struct intel_encoder *encoder;
4508
4509         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
4510                 if (encoder->type == INTEL_OUTPUT_DP ||
4511                     encoder->type == INTEL_OUTPUT_EDP)
4512                         return enc_to_dig_port(&encoder->base)->port;
4513         }
4514
4515         return -1;
4516 }
4517
4518 /*
4519  * Enable PCH resources required for PCH ports:
4520  *   - PCH PLLs
4521  *   - FDI training & RX/TX
4522  *   - update transcoder timings
4523  *   - DP transcoding bits
4524  *   - transcoder
4525  */
4526 static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
4527 {
4528         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4529         struct drm_device *dev = crtc->base.dev;
4530         struct drm_i915_private *dev_priv = to_i915(dev);
4531         int pipe = crtc->pipe;
4532         u32 temp;
4533
4534         assert_pch_transcoder_disabled(dev_priv, pipe);
4535
4536         if (IS_IVYBRIDGE(dev_priv))
4537                 ivybridge_update_fdi_bc_bifurcation(crtc);
4538
4539         /* Write the TU size bits before fdi link training, so that error
4540          * detection works. */
4541         I915_WRITE(FDI_RX_TUSIZE1(pipe),
4542                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4543
4544         /* For PCH output, training FDI link */
4545         dev_priv->display.fdi_link_train(crtc, crtc_state);
4546
4547         /* We need to program the right clock selection before writing the pixel
4548          * mutliplier into the DPLL. */
4549         if (HAS_PCH_CPT(dev_priv)) {
4550                 u32 sel;
4551
4552                 temp = I915_READ(PCH_DPLL_SEL);
4553                 temp |= TRANS_DPLL_ENABLE(pipe);
4554                 sel = TRANS_DPLLB_SEL(pipe);
4555                 if (crtc_state->shared_dpll ==
4556                     intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4557                         temp |= sel;
4558                 else
4559                         temp &= ~sel;
4560                 I915_WRITE(PCH_DPLL_SEL, temp);
4561         }
4562
4563         /* XXX: pch pll's can be enabled any time before we enable the PCH
4564          * transcoder, and we actually should do this to not upset any PCH
4565          * transcoder that already use the clock when we share it.
4566          *
4567          * Note that enable_shared_dpll tries to do the right thing, but
4568          * get_shared_dpll unconditionally resets the pll - we need that to have
4569          * the right LVDS enable sequence. */
4570         intel_enable_shared_dpll(crtc);
4571
4572         /* set transcoder timing, panel must allow it */
4573         assert_panel_unlocked(dev_priv, pipe);
4574         ironlake_pch_transcoder_set_timings(crtc, pipe);
4575
4576         intel_fdi_normal_train(crtc);
4577
4578         /* For PCH DP, enable TRANS_DP_CTL */
4579         if (HAS_PCH_CPT(dev_priv) &&
4580             intel_crtc_has_dp_encoder(crtc_state)) {
4581                 const struct drm_display_mode *adjusted_mode =
4582                         &crtc_state->base.adjusted_mode;
4583                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4584                 i915_reg_t reg = TRANS_DP_CTL(pipe);
4585                 temp = I915_READ(reg);
4586                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4587                           TRANS_DP_SYNC_MASK |
4588                           TRANS_DP_BPC_MASK);
4589                 temp |= TRANS_DP_OUTPUT_ENABLE;
4590                 temp |= bpc << 9; /* same format but at 11:9 */
4591
4592                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4593                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4594                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4595                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4596
4597                 switch (intel_trans_dp_port_sel(crtc)) {
4598                 case PORT_B:
4599                         temp |= TRANS_DP_PORT_SEL_B;
4600                         break;
4601                 case PORT_C:
4602                         temp |= TRANS_DP_PORT_SEL_C;
4603                         break;
4604                 case PORT_D:
4605                         temp |= TRANS_DP_PORT_SEL_D;
4606                         break;
4607                 default:
4608                         BUG();
4609                 }
4610
4611                 I915_WRITE(reg, temp);
4612         }
4613
4614         ironlake_enable_pch_transcoder(dev_priv, pipe);
4615 }
4616
4617 static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
4618 {
4619         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4620         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4621         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4622
4623         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4624
4625         lpt_program_iclkip(crtc);
4626
4627         /* Set transcoder timing. */
4628         ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
4629
4630         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4631 }
4632
4633 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4634 {
4635         struct drm_i915_private *dev_priv = to_i915(dev);
4636         i915_reg_t dslreg = PIPEDSL(pipe);
4637         u32 temp;
4638
4639         temp = I915_READ(dslreg);
4640         udelay(500);
4641         if (wait_for(I915_READ(dslreg) != temp, 5)) {
4642                 if (wait_for(I915_READ(dslreg) != temp, 5))
4643                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4644         }
4645 }
4646
4647 static int
4648 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4649                   unsigned scaler_user, int *scaler_id, unsigned int rotation,
4650                   int src_w, int src_h, int dst_w, int dst_h)
4651 {
4652         struct intel_crtc_scaler_state *scaler_state =
4653                 &crtc_state->scaler_state;
4654         struct intel_crtc *intel_crtc =
4655                 to_intel_crtc(crtc_state->base.crtc);
4656         int need_scaling;
4657
4658         need_scaling = drm_rotation_90_or_270(rotation) ?
4659                 (src_h != dst_w || src_w != dst_h):
4660                 (src_w != dst_w || src_h != dst_h);
4661
4662         /*
4663          * if plane is being disabled or scaler is no more required or force detach
4664          *  - free scaler binded to this plane/crtc
4665          *  - in order to do this, update crtc->scaler_usage
4666          *
4667          * Here scaler state in crtc_state is set free so that
4668          * scaler can be assigned to other user. Actual register
4669          * update to free the scaler is done in plane/panel-fit programming.
4670          * For this purpose crtc/plane_state->scaler_id isn't reset here.
4671          */
4672         if (force_detach || !need_scaling) {
4673                 if (*scaler_id >= 0) {
4674                         scaler_state->scaler_users &= ~(1 << scaler_user);
4675                         scaler_state->scalers[*scaler_id].in_use = 0;
4676
4677                         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4678                                 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4679                                 intel_crtc->pipe, scaler_user, *scaler_id,
4680                                 scaler_state->scaler_users);
4681                         *scaler_id = -1;
4682                 }
4683                 return 0;
4684         }
4685
4686         /* range checks */
4687         if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4688                 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4689
4690                 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4691                 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4692                 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4693                         "size is out of scaler range\n",
4694                         intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4695                 return -EINVAL;
4696         }
4697
4698         /* mark this plane as a scaler user in crtc_state */
4699         scaler_state->scaler_users |= (1 << scaler_user);
4700         DRM_DEBUG_KMS("scaler_user index %u.%u: "
4701                 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4702                 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4703                 scaler_state->scaler_users);
4704
4705         return 0;
4706 }
4707
4708 /**
4709  * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4710  *
4711  * @state: crtc's scaler state
4712  *
4713  * Return
4714  *     0 - scaler_usage updated successfully
4715  *    error - requested scaling cannot be supported or other error condition
4716  */
4717 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4718 {
4719         const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4720
4721         return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4722                 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4723                 state->pipe_src_w, state->pipe_src_h,
4724                 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4725 }
4726
4727 /**
4728  * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4729  *
4730  * @state: crtc's scaler state
4731  * @plane_state: atomic plane state to update
4732  *
4733  * Return
4734  *     0 - scaler_usage updated successfully
4735  *    error - requested scaling cannot be supported or other error condition
4736  */
4737 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4738                                    struct intel_plane_state *plane_state)
4739 {
4740
4741         struct intel_plane *intel_plane =
4742                 to_intel_plane(plane_state->base.plane);
4743         struct drm_framebuffer *fb = plane_state->base.fb;
4744         int ret;
4745
4746         bool force_detach = !fb || !plane_state->base.visible;
4747
4748         ret = skl_update_scaler(crtc_state, force_detach,
4749                                 drm_plane_index(&intel_plane->base),
4750                                 &plane_state->scaler_id,
4751                                 plane_state->base.rotation,
4752                                 drm_rect_width(&plane_state->base.src) >> 16,
4753                                 drm_rect_height(&plane_state->base.src) >> 16,
4754                                 drm_rect_width(&plane_state->base.dst),
4755                                 drm_rect_height(&plane_state->base.dst));
4756
4757         if (ret || plane_state->scaler_id < 0)
4758                 return ret;
4759
4760         /* check colorkey */
4761         if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4762                 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4763                               intel_plane->base.base.id,
4764                               intel_plane->base.name);
4765                 return -EINVAL;
4766         }
4767
4768         /* Check src format */
4769         switch (fb->format->format) {
4770         case DRM_FORMAT_RGB565:
4771         case DRM_FORMAT_XBGR8888:
4772         case DRM_FORMAT_XRGB8888:
4773         case DRM_FORMAT_ABGR8888:
4774         case DRM_FORMAT_ARGB8888:
4775         case DRM_FORMAT_XRGB2101010:
4776         case DRM_FORMAT_XBGR2101010:
4777         case DRM_FORMAT_YUYV:
4778         case DRM_FORMAT_YVYU:
4779         case DRM_FORMAT_UYVY:
4780         case DRM_FORMAT_VYUY:
4781                 break;
4782         default:
4783                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4784                               intel_plane->base.base.id, intel_plane->base.name,
4785                               fb->base.id, fb->format->format);
4786                 return -EINVAL;
4787         }
4788
4789         return 0;
4790 }
4791
4792 static void skylake_scaler_disable(struct intel_crtc *crtc)
4793 {
4794         int i;
4795
4796         for (i = 0; i < crtc->num_scalers; i++)
4797                 skl_detach_scaler(crtc, i);
4798 }
4799
4800 static void skylake_pfit_enable(struct intel_crtc *crtc)
4801 {
4802         struct drm_device *dev = crtc->base.dev;
4803         struct drm_i915_private *dev_priv = to_i915(dev);
4804         int pipe = crtc->pipe;
4805         struct intel_crtc_scaler_state *scaler_state =
4806                 &crtc->config->scaler_state;
4807
4808         if (crtc->config->pch_pfit.enabled) {
4809                 int id;
4810
4811                 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4812                         return;
4813
4814                 id = scaler_state->scaler_id;
4815                 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4816                         PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4817                 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4818                 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4819         }
4820 }
4821
4822 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4823 {
4824         struct drm_device *dev = crtc->base.dev;
4825         struct drm_i915_private *dev_priv = to_i915(dev);
4826         int pipe = crtc->pipe;
4827
4828         if (crtc->config->pch_pfit.enabled) {
4829                 /* Force use of hard-coded filter coefficients
4830                  * as some pre-programmed values are broken,
4831                  * e.g. x201.
4832                  */
4833                 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
4834                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4835                                                  PF_PIPE_SEL_IVB(pipe));
4836                 else
4837                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4838                 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4839                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4840         }
4841 }
4842
4843 void hsw_enable_ips(struct intel_crtc *crtc)
4844 {
4845         struct drm_device *dev = crtc->base.dev;
4846         struct drm_i915_private *dev_priv = to_i915(dev);
4847
4848         if (!crtc->config->ips_enabled)
4849                 return;
4850
4851         /*
4852          * We can only enable IPS after we enable a plane and wait for a vblank
4853          * This function is called from post_plane_update, which is run after
4854          * a vblank wait.
4855          */
4856
4857         assert_plane_enabled(dev_priv, crtc->plane);
4858         if (IS_BROADWELL(dev_priv)) {
4859                 mutex_lock(&dev_priv->rps.hw_lock);
4860                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4861                 mutex_unlock(&dev_priv->rps.hw_lock);
4862                 /* Quoting Art Runyan: "its not safe to expect any particular
4863                  * value in IPS_CTL bit 31 after enabling IPS through the
4864                  * mailbox." Moreover, the mailbox may return a bogus state,
4865                  * so we need to just enable it and continue on.
4866                  */
4867         } else {
4868                 I915_WRITE(IPS_CTL, IPS_ENABLE);
4869                 /* The bit only becomes 1 in the next vblank, so this wait here
4870                  * is essentially intel_wait_for_vblank. If we don't have this
4871                  * and don't wait for vblanks until the end of crtc_enable, then
4872                  * the HW state readout code will complain that the expected
4873                  * IPS_CTL value is not the one we read. */
4874                 if (intel_wait_for_register(dev_priv,
4875                                             IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4876                                             50))
4877                         DRM_ERROR("Timed out waiting for IPS enable\n");
4878         }
4879 }
4880
4881 void hsw_disable_ips(struct intel_crtc *crtc)
4882 {
4883         struct drm_device *dev = crtc->base.dev;
4884         struct drm_i915_private *dev_priv = to_i915(dev);
4885
4886         if (!crtc->config->ips_enabled)
4887                 return;
4888
4889         assert_plane_enabled(dev_priv, crtc->plane);
4890         if (IS_BROADWELL(dev_priv)) {
4891                 mutex_lock(&dev_priv->rps.hw_lock);
4892                 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4893                 mutex_unlock(&dev_priv->rps.hw_lock);
4894                 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4895                 if (intel_wait_for_register(dev_priv,
4896                                             IPS_CTL, IPS_ENABLE, 0,
4897                                             42))
4898                         DRM_ERROR("Timed out waiting for IPS disable\n");
4899         } else {
4900                 I915_WRITE(IPS_CTL, 0);
4901                 POSTING_READ(IPS_CTL);
4902         }
4903
4904         /* We need to wait for a vblank before we can disable the plane. */
4905         intel_wait_for_vblank(dev_priv, crtc->pipe);
4906 }
4907
4908 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4909 {
4910         if (intel_crtc->overlay) {
4911                 struct drm_device *dev = intel_crtc->base.dev;
4912                 struct drm_i915_private *dev_priv = to_i915(dev);
4913
4914                 mutex_lock(&dev->struct_mutex);
4915                 dev_priv->mm.interruptible = false;
4916                 (void) intel_overlay_switch_off(intel_crtc->overlay);
4917                 dev_priv->mm.interruptible = true;
4918                 mutex_unlock(&dev->struct_mutex);
4919         }
4920
4921         /* Let userspace switch the overlay on again. In most cases userspace
4922          * has to recompute where to put it anyway.
4923          */
4924 }
4925
4926 /**
4927  * intel_post_enable_primary - Perform operations after enabling primary plane
4928  * @crtc: the CRTC whose primary plane was just enabled
4929  *
4930  * Performs potentially sleeping operations that must be done after the primary
4931  * plane is enabled, such as updating FBC and IPS.  Note that this may be
4932  * called due to an explicit primary plane update, or due to an implicit
4933  * re-enable that is caused when a sprite plane is updated to no longer
4934  * completely hide the primary plane.
4935  */
4936 static void
4937 intel_post_enable_primary(struct drm_crtc *crtc)
4938 {
4939         struct drm_device *dev = crtc->dev;
4940         struct drm_i915_private *dev_priv = to_i915(dev);
4941         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4942         int pipe = intel_crtc->pipe;
4943
4944         /*
4945          * FIXME IPS should be fine as long as one plane is
4946          * enabled, but in practice it seems to have problems
4947          * when going from primary only to sprite only and vice
4948          * versa.
4949          */
4950         hsw_enable_ips(intel_crtc);
4951
4952         /*
4953          * Gen2 reports pipe underruns whenever all planes are disabled.
4954          * So don't enable underrun reporting before at least some planes
4955          * are enabled.
4956          * FIXME: Need to fix the logic to work when we turn off all planes
4957          * but leave the pipe running.
4958          */
4959         if (IS_GEN2(dev_priv))
4960                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4961
4962         /* Underruns don't always raise interrupts, so check manually. */
4963         intel_check_cpu_fifo_underruns(dev_priv);
4964         intel_check_pch_fifo_underruns(dev_priv);
4965 }
4966
4967 /* FIXME move all this to pre_plane_update() with proper state tracking */
4968 static void
4969 intel_pre_disable_primary(struct drm_crtc *crtc)
4970 {
4971         struct drm_device *dev = crtc->dev;
4972         struct drm_i915_private *dev_priv = to_i915(dev);
4973         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4974         int pipe = intel_crtc->pipe;
4975
4976         /*
4977          * Gen2 reports pipe underruns whenever all planes are disabled.
4978          * So diasble underrun reporting before all the planes get disabled.
4979          * FIXME: Need to fix the logic to work when we turn off all planes
4980          * but leave the pipe running.
4981          */
4982         if (IS_GEN2(dev_priv))
4983                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4984
4985         /*
4986          * FIXME IPS should be fine as long as one plane is
4987          * enabled, but in practice it seems to have problems
4988          * when going from primary only to sprite only and vice
4989          * versa.
4990          */
4991         hsw_disable_ips(intel_crtc);
4992 }
4993
4994 /* FIXME get rid of this and use pre_plane_update */
4995 static void
4996 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4997 {
4998         struct drm_device *dev = crtc->dev;
4999         struct drm_i915_private *dev_priv = to_i915(dev);
5000         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5001         int pipe = intel_crtc->pipe;
5002
5003         intel_pre_disable_primary(crtc);
5004
5005         /*
5006          * Vblank time updates from the shadow to live plane control register
5007          * are blocked if the memory self-refresh mode is active at that
5008          * moment. So to make sure the plane gets truly disabled, disable
5009          * first the self-refresh mode. The self-refresh enable bit in turn
5010          * will be checked/applied by the HW only at the next frame start
5011          * event which is after the vblank start event, so we need to have a
5012          * wait-for-vblank between disabling the plane and the pipe.
5013          */
5014         if (HAS_GMCH_DISPLAY(dev_priv) &&
5015             intel_set_memory_cxsr(dev_priv, false))
5016                 intel_wait_for_vblank(dev_priv, pipe);
5017 }
5018
5019 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5020 {
5021         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5022         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5023         struct intel_crtc_state *pipe_config =
5024                 to_intel_crtc_state(crtc->base.state);
5025         struct drm_plane *primary = crtc->base.primary;
5026         struct drm_plane_state *old_pri_state =
5027                 drm_atomic_get_existing_plane_state(old_state, primary);
5028
5029         intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5030
5031         if (pipe_config->update_wm_post && pipe_config->base.active)
5032                 intel_update_watermarks(crtc);
5033
5034         if (old_pri_state) {
5035                 struct intel_plane_state *primary_state =
5036                         to_intel_plane_state(primary->state);
5037                 struct intel_plane_state *old_primary_state =
5038                         to_intel_plane_state(old_pri_state);
5039
5040                 intel_fbc_post_update(crtc);
5041
5042                 if (primary_state->base.visible &&
5043                     (needs_modeset(&pipe_config->base) ||
5044                      !old_primary_state->base.visible))
5045                         intel_post_enable_primary(&crtc->base);
5046         }
5047 }
5048
5049 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
5050                                    struct intel_crtc_state *pipe_config)
5051 {
5052         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5053         struct drm_device *dev = crtc->base.dev;
5054         struct drm_i915_private *dev_priv = to_i915(dev);
5055         struct drm_atomic_state *old_state = old_crtc_state->base.state;
5056         struct drm_plane *primary = crtc->base.primary;
5057         struct drm_plane_state *old_pri_state =
5058                 drm_atomic_get_existing_plane_state(old_state, primary);
5059         bool modeset = needs_modeset(&pipe_config->base);
5060         struct intel_atomic_state *old_intel_state =
5061                 to_intel_atomic_state(old_state);
5062
5063         if (old_pri_state) {
5064                 struct intel_plane_state *primary_state =
5065                         to_intel_plane_state(primary->state);
5066                 struct intel_plane_state *old_primary_state =
5067                         to_intel_plane_state(old_pri_state);
5068
5069                 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5070
5071                 if (old_primary_state->base.visible &&
5072                     (modeset || !primary_state->base.visible))
5073                         intel_pre_disable_primary(&crtc->base);
5074         }
5075
5076         /*
5077          * Vblank time updates from the shadow to live plane control register
5078          * are blocked if the memory self-refresh mode is active at that
5079          * moment. So to make sure the plane gets truly disabled, disable
5080          * first the self-refresh mode. The self-refresh enable bit in turn
5081          * will be checked/applied by the HW only at the next frame start
5082          * event which is after the vblank start event, so we need to have a
5083          * wait-for-vblank between disabling the plane and the pipe.
5084          */
5085         if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5086             pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5087                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5088
5089         /*
5090          * IVB workaround: must disable low power watermarks for at least
5091          * one frame before enabling scaling.  LP watermarks can be re-enabled
5092          * when scaling is disabled.
5093          *
5094          * WaCxSRDisabledForSpriteScaling:ivb
5095          */
5096         if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
5097                 intel_wait_for_vblank(dev_priv, crtc->pipe);
5098
5099         /*
5100          * If we're doing a modeset, we're done.  No need to do any pre-vblank
5101          * watermark programming here.
5102          */
5103         if (needs_modeset(&pipe_config->base))
5104                 return;
5105
5106         /*
5107          * For platforms that support atomic watermarks, program the
5108          * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
5109          * will be the intermediate values that are safe for both pre- and
5110          * post- vblank; when vblank happens, the 'active' values will be set
5111          * to the final 'target' values and we'll do this again to get the
5112          * optimal watermarks.  For gen9+ platforms, the values we program here
5113          * will be the final target values which will get automatically latched
5114          * at vblank time; no further programming will be necessary.
5115          *
5116          * If a platform hasn't been transitioned to atomic watermarks yet,
5117          * we'll continue to update watermarks the old way, if flags tell
5118          * us to.
5119          */
5120         if (dev_priv->display.initial_watermarks != NULL)
5121                 dev_priv->display.initial_watermarks(old_intel_state,
5122                                                      pipe_config);
5123         else if (pipe_config->update_wm_pre)
5124                 intel_update_watermarks(crtc);
5125 }
5126
5127 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5128 {
5129         struct drm_device *dev = crtc->dev;
5130         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5131         struct drm_plane *p;
5132         int pipe = intel_crtc->pipe;
5133
5134         intel_crtc_dpms_overlay_disable(intel_crtc);
5135
5136         drm_for_each_plane_mask(p, dev, plane_mask)
5137                 to_intel_plane(p)->disable_plane(p, crtc);
5138
5139         /*
5140          * FIXME: Once we grow proper nuclear flip support out of this we need
5141          * to compute the mask of flip planes precisely. For the time being
5142          * consider this a flip to a NULL plane.
5143          */
5144         intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5145 }
5146
5147 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5148                                           struct intel_crtc_state *crtc_state,
5149                                           struct drm_atomic_state *old_state)
5150 {
5151         struct drm_connector_state *conn_state;
5152         struct drm_connector *conn;
5153         int i;
5154
5155         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5156                 struct intel_encoder *encoder =
5157                         to_intel_encoder(conn_state->best_encoder);
5158
5159                 if (conn_state->crtc != crtc)
5160                         continue;
5161
5162                 if (encoder->pre_pll_enable)
5163                         encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5164         }
5165 }
5166
5167 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5168                                       struct intel_crtc_state *crtc_state,
5169                                       struct drm_atomic_state *old_state)
5170 {
5171         struct drm_connector_state *conn_state;
5172         struct drm_connector *conn;
5173         int i;
5174
5175         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5176                 struct intel_encoder *encoder =
5177                         to_intel_encoder(conn_state->best_encoder);
5178
5179                 if (conn_state->crtc != crtc)
5180                         continue;
5181
5182                 if (encoder->pre_enable)
5183                         encoder->pre_enable(encoder, crtc_state, conn_state);
5184         }
5185 }
5186
5187 static void intel_encoders_enable(struct drm_crtc *crtc,
5188                                   struct intel_crtc_state *crtc_state,
5189                                   struct drm_atomic_state *old_state)
5190 {
5191         struct drm_connector_state *conn_state;
5192         struct drm_connector *conn;
5193         int i;
5194
5195         for_each_new_connector_in_state(old_state, conn, conn_state, i) {
5196                 struct intel_encoder *encoder =
5197                         to_intel_encoder(conn_state->best_encoder);
5198
5199                 if (conn_state->crtc != crtc)
5200                         continue;
5201
5202                 encoder->enable(encoder, crtc_state, conn_state);
5203                 intel_opregion_notify_encoder(encoder, true);
5204         }
5205 }
5206
5207 static void intel_encoders_disable(struct drm_crtc *crtc,
5208                                    struct intel_crtc_state *old_crtc_state,
5209                                    struct drm_atomic_state *old_state)
5210 {
5211         struct drm_connector_state *old_conn_state;
5212         struct drm_connector *conn;
5213         int i;
5214
5215         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5216                 struct intel_encoder *encoder =
5217                         to_intel_encoder(old_conn_state->best_encoder);
5218
5219                 if (old_conn_state->crtc != crtc)
5220                         continue;
5221
5222                 intel_opregion_notify_encoder(encoder, false);
5223                 encoder->disable(encoder, old_crtc_state, old_conn_state);
5224         }
5225 }
5226
5227 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5228                                         struct intel_crtc_state *old_crtc_state,
5229                                         struct drm_atomic_state *old_state)
5230 {
5231         struct drm_connector_state *old_conn_state;
5232         struct drm_connector *conn;
5233         int i;
5234
5235         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5236                 struct intel_encoder *encoder =
5237                         to_intel_encoder(old_conn_state->best_encoder);
5238
5239                 if (old_conn_state->crtc != crtc)
5240                         continue;
5241
5242                 if (encoder->post_disable)
5243                         encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5244         }
5245 }
5246
5247 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5248                                             struct intel_crtc_state *old_crtc_state,
5249                                             struct drm_atomic_state *old_state)
5250 {
5251         struct drm_connector_state *old_conn_state;
5252         struct drm_connector *conn;
5253         int i;
5254
5255         for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
5256                 struct intel_encoder *encoder =
5257                         to_intel_encoder(old_conn_state->best_encoder);
5258
5259                 if (old_conn_state->crtc != crtc)
5260                         continue;
5261
5262                 if (encoder->post_pll_disable)
5263                         encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5264         }
5265 }
5266
5267 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5268                                  struct drm_atomic_state *old_state)
5269 {
5270         struct drm_crtc *crtc = pipe_config->base.crtc;
5271         struct drm_device *dev = crtc->dev;
5272         struct drm_i915_private *dev_priv = to_i915(dev);
5273         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5274         int pipe = intel_crtc->pipe;
5275         struct intel_atomic_state *old_intel_state =
5276                 to_intel_atomic_state(old_state);
5277
5278         if (WARN_ON(intel_crtc->active))
5279                 return;
5280
5281         /*
5282          * Sometimes spurious CPU pipe underruns happen during FDI
5283          * training, at least with VGA+HDMI cloning. Suppress them.
5284          *
5285          * On ILK we get an occasional spurious CPU pipe underruns
5286          * between eDP port A enable and vdd enable. Also PCH port
5287          * enable seems to result in the occasional CPU pipe underrun.
5288          *
5289          * Spurious PCH underruns also occur during PCH enabling.
5290          */
5291         if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5292                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5293         if (intel_crtc->config->has_pch_encoder)
5294                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5295
5296         if (intel_crtc->config->has_pch_encoder)
5297                 intel_prepare_shared_dpll(intel_crtc);
5298
5299         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5300                 intel_dp_set_m_n(intel_crtc, M1_N1);
5301
5302         intel_set_pipe_timings(intel_crtc);
5303         intel_set_pipe_src_size(intel_crtc);
5304
5305         if (intel_crtc->config->has_pch_encoder) {
5306                 intel_cpu_transcoder_set_m_n(intel_crtc,
5307                                      &intel_crtc->config->fdi_m_n, NULL);
5308         }
5309
5310         ironlake_set_pipeconf(crtc);
5311
5312         intel_crtc->active = true;
5313
5314         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5315
5316         if (intel_crtc->config->has_pch_encoder) {
5317                 /* Note: FDI PLL enabling _must_ be done before we enable the
5318                  * cpu pipes, hence this is separate from all the other fdi/pch
5319                  * enabling. */
5320                 ironlake_fdi_pll_enable(intel_crtc);
5321         } else {
5322                 assert_fdi_tx_disabled(dev_priv, pipe);
5323                 assert_fdi_rx_disabled(dev_priv, pipe);
5324         }
5325
5326         ironlake_pfit_enable(intel_crtc);
5327
5328         /*
5329          * On ILK+ LUT must be loaded before the pipe is running but with
5330          * clocks enabled
5331          */
5332         intel_color_load_luts(&pipe_config->base);
5333
5334         if (dev_priv->display.initial_watermarks != NULL)
5335                 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
5336         intel_enable_pipe(intel_crtc);
5337
5338         if (intel_crtc->config->has_pch_encoder)
5339                 ironlake_pch_enable(pipe_config);
5340
5341         assert_vblank_disabled(crtc);
5342         drm_crtc_vblank_on(crtc);
5343
5344         intel_encoders_enable(crtc, pipe_config, old_state);
5345
5346         if (HAS_PCH_CPT(dev_priv))
5347                 cpt_verify_modeset(dev, intel_crtc->pipe);
5348
5349         /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5350         if (intel_crtc->config->has_pch_encoder)
5351                 intel_wait_for_vblank(dev_priv, pipe);
5352         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5353         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5354 }
5355
5356 /* IPS only exists on ULT machines and is tied to pipe A. */
5357 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5358 {
5359         return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
5360 }
5361
5362 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5363                                 struct drm_atomic_state *old_state)
5364 {
5365         struct drm_crtc *crtc = pipe_config->base.crtc;
5366         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5368         int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5369         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5370         struct intel_atomic_state *old_intel_state =
5371                 to_intel_atomic_state(old_state);
5372
5373         if (WARN_ON(intel_crtc->active))
5374                 return;
5375
5376         if (intel_crtc->config->has_pch_encoder)
5377                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5378                                                       false);
5379
5380         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5381
5382         if (intel_crtc->config->shared_dpll)
5383                 intel_enable_shared_dpll(intel_crtc);
5384
5385         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5386                 intel_dp_set_m_n(intel_crtc, M1_N1);
5387
5388         if (!transcoder_is_dsi(cpu_transcoder))
5389                 intel_set_pipe_timings(intel_crtc);
5390
5391         intel_set_pipe_src_size(intel_crtc);
5392
5393         if (cpu_transcoder != TRANSCODER_EDP &&
5394             !transcoder_is_dsi(cpu_transcoder)) {
5395                 I915_WRITE(PIPE_MULT(cpu_transcoder),
5396                            intel_crtc->config->pixel_multiplier - 1);
5397         }
5398
5399         if (intel_crtc->config->has_pch_encoder) {
5400                 intel_cpu_transcoder_set_m_n(intel_crtc,
5401                                      &intel_crtc->config->fdi_m_n, NULL);
5402         }
5403
5404         if (!transcoder_is_dsi(cpu_transcoder))
5405                 haswell_set_pipeconf(crtc);
5406
5407         haswell_set_pipemisc(crtc);
5408
5409         intel_color_set_csc(&pipe_config->base);
5410
5411         intel_crtc->active = true;
5412
5413         if (intel_crtc->config->has_pch_encoder)
5414                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5415         else
5416                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5417
5418         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5419
5420         if (intel_crtc->config->has_pch_encoder)
5421                 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
5422
5423         if (!transcoder_is_dsi(cpu_transcoder))
5424                 intel_ddi_enable_pipe_clock(pipe_config);
5425
5426         if (INTEL_GEN(dev_priv) >= 9)
5427                 skylake_pfit_enable(intel_crtc);
5428         else
5429                 ironlake_pfit_enable(intel_crtc);
5430
5431         /*
5432          * On ILK+ LUT must be loaded before the pipe is running but with
5433          * clocks enabled
5434          */
5435         intel_color_load_luts(&pipe_config->base);
5436
5437         intel_ddi_set_pipe_settings(pipe_config);
5438         if (!transcoder_is_dsi(cpu_transcoder))
5439                 intel_ddi_enable_transcoder_func(pipe_config);
5440
5441         if (dev_priv->display.initial_watermarks != NULL)
5442                 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
5443
5444         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5445         if (!transcoder_is_dsi(cpu_transcoder))
5446                 intel_enable_pipe(intel_crtc);
5447
5448         if (intel_crtc->config->has_pch_encoder)
5449                 lpt_pch_enable(pipe_config);
5450
5451         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5452                 intel_ddi_set_vc_payload_alloc(pipe_config, true);
5453
5454         assert_vblank_disabled(crtc);
5455         drm_crtc_vblank_on(crtc);
5456
5457         intel_encoders_enable(crtc, pipe_config, old_state);
5458
5459         if (intel_crtc->config->has_pch_encoder) {
5460                 intel_wait_for_vblank(dev_priv, pipe);
5461                 intel_wait_for_vblank(dev_priv, pipe);
5462                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5463                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5464                                                       true);
5465         }
5466
5467         /* If we change the relative order between pipe/planes enabling, we need
5468          * to change the workaround. */
5469         hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5470         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
5471                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5472                 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5473         }
5474 }
5475
5476 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5477 {
5478         struct drm_device *dev = crtc->base.dev;
5479         struct drm_i915_private *dev_priv = to_i915(dev);
5480         int pipe = crtc->pipe;
5481
5482         /* To avoid upsetting the power well on haswell only disable the pfit if
5483          * it's in use. The hw state code will make sure we get this right. */
5484         if (force || crtc->config->pch_pfit.enabled) {
5485                 I915_WRITE(PF_CTL(pipe), 0);
5486                 I915_WRITE(PF_WIN_POS(pipe), 0);
5487                 I915_WRITE(PF_WIN_SZ(pipe), 0);
5488         }
5489 }
5490
5491 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5492                                   struct drm_atomic_state *old_state)
5493 {
5494         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5495         struct drm_device *dev = crtc->dev;
5496         struct drm_i915_private *dev_priv = to_i915(dev);
5497         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5498         int pipe = intel_crtc->pipe;
5499
5500         /*
5501          * Sometimes spurious CPU pipe underruns happen when the
5502          * pipe is already disabled, but FDI RX/TX is still enabled.
5503          * Happens at least with VGA+HDMI cloning. Suppress them.
5504          */
5505         if (intel_crtc->config->has_pch_encoder) {
5506                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5507                 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5508         }
5509
5510         intel_encoders_disable(crtc, old_crtc_state, old_state);
5511
5512         drm_crtc_vblank_off(crtc);
5513         assert_vblank_disabled(crtc);
5514
5515         intel_disable_pipe(intel_crtc);
5516
5517         ironlake_pfit_disable(intel_crtc, false);
5518
5519         if (intel_crtc->config->has_pch_encoder)
5520                 ironlake_fdi_disable(crtc);
5521
5522         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5523
5524         if (intel_crtc->config->has_pch_encoder) {
5525                 ironlake_disable_pch_transcoder(dev_priv, pipe);
5526
5527                 if (HAS_PCH_CPT(dev_priv)) {
5528                         i915_reg_t reg;
5529                         u32 temp;
5530
5531                         /* disable TRANS_DP_CTL */
5532                         reg = TRANS_DP_CTL(pipe);
5533                         temp = I915_READ(reg);
5534                         temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5535                                   TRANS_DP_PORT_SEL_MASK);
5536                         temp |= TRANS_DP_PORT_SEL_NONE;
5537                         I915_WRITE(reg, temp);
5538
5539                         /* disable DPLL_SEL */
5540                         temp = I915_READ(PCH_DPLL_SEL);
5541                         temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5542                         I915_WRITE(PCH_DPLL_SEL, temp);
5543                 }
5544
5545                 ironlake_fdi_pll_disable(intel_crtc);
5546         }
5547
5548         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5549         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5550 }
5551
5552 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5553                                  struct drm_atomic_state *old_state)
5554 {
5555         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5556         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5557         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5558         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5559
5560         if (intel_crtc->config->has_pch_encoder)
5561                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5562                                                       false);
5563
5564         intel_encoders_disable(crtc, old_crtc_state, old_state);
5565
5566         drm_crtc_vblank_off(crtc);
5567         assert_vblank_disabled(crtc);
5568
5569         /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5570         if (!transcoder_is_dsi(cpu_transcoder))
5571                 intel_disable_pipe(intel_crtc);
5572
5573         if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
5574                 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
5575
5576         if (!transcoder_is_dsi(cpu_transcoder))
5577                 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5578
5579         if (INTEL_GEN(dev_priv) >= 9)
5580                 skylake_scaler_disable(intel_crtc);
5581         else
5582                 ironlake_pfit_disable(intel_crtc, false);
5583
5584         if (!transcoder_is_dsi(cpu_transcoder))
5585                 intel_ddi_disable_pipe_clock(intel_crtc->config);
5586
5587         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5588
5589         if (old_crtc_state->has_pch_encoder)
5590                 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5591                                                       true);
5592 }
5593
5594 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5595 {
5596         struct drm_device *dev = crtc->base.dev;
5597         struct drm_i915_private *dev_priv = to_i915(dev);
5598         struct intel_crtc_state *pipe_config = crtc->config;
5599
5600         if (!pipe_config->gmch_pfit.control)
5601                 return;
5602
5603         /*
5604          * The panel fitter should only be adjusted whilst the pipe is disabled,
5605          * according to register description and PRM.
5606          */
5607         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5608         assert_pipe_disabled(dev_priv, crtc->pipe);
5609
5610         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5611         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5612
5613         /* Border color in case we don't scale up to the full screen. Black by
5614          * default, change to something else for debugging. */
5615         I915_WRITE(BCLRPAT(crtc->pipe), 0);
5616 }
5617
5618 enum intel_display_power_domain intel_port_to_power_domain(enum port port)
5619 {
5620         switch (port) {
5621         case PORT_A:
5622                 return POWER_DOMAIN_PORT_DDI_A_LANES;
5623         case PORT_B:
5624                 return POWER_DOMAIN_PORT_DDI_B_LANES;
5625         case PORT_C:
5626                 return POWER_DOMAIN_PORT_DDI_C_LANES;
5627         case PORT_D:
5628                 return POWER_DOMAIN_PORT_DDI_D_LANES;
5629         case PORT_E:
5630                 return POWER_DOMAIN_PORT_DDI_E_LANES;
5631         default:
5632                 MISSING_CASE(port);
5633                 return POWER_DOMAIN_PORT_OTHER;
5634         }
5635 }
5636
5637 static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5638                                   struct intel_crtc_state *crtc_state)
5639 {
5640         struct drm_device *dev = crtc->dev;
5641         struct drm_i915_private *dev_priv = to_i915(dev);
5642         struct drm_encoder *encoder;
5643         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5644         enum pipe pipe = intel_crtc->pipe;
5645         u64 mask;
5646         enum transcoder transcoder = crtc_state->cpu_transcoder;
5647
5648         if (!crtc_state->base.active)
5649                 return 0;
5650
5651         mask = BIT(POWER_DOMAIN_PIPE(pipe));
5652         mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5653         if (crtc_state->pch_pfit.enabled ||
5654             crtc_state->pch_pfit.force_thru)
5655                 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5656
5657         drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5658                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5659
5660                 mask |= BIT_ULL(intel_encoder->power_domain);
5661         }
5662
5663         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5664                 mask |= BIT(POWER_DOMAIN_AUDIO);
5665
5666         if (crtc_state->shared_dpll)
5667                 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
5668
5669         return mask;
5670 }
5671
5672 static u64
5673 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5674                                struct intel_crtc_state *crtc_state)
5675 {
5676         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5678         enum intel_display_power_domain domain;
5679         u64 domains, new_domains, old_domains;
5680
5681         old_domains = intel_crtc->enabled_power_domains;
5682         intel_crtc->enabled_power_domains = new_domains =
5683                 get_crtc_power_domains(crtc, crtc_state);
5684
5685         domains = new_domains & ~old_domains;
5686
5687         for_each_power_domain(domain, domains)
5688                 intel_display_power_get(dev_priv, domain);
5689
5690         return old_domains & ~new_domains;
5691 }
5692
5693 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5694                                       u64 domains)
5695 {
5696         enum intel_display_power_domain domain;
5697
5698         for_each_power_domain(domain, domains)
5699                 intel_display_power_put(dev_priv, domain);
5700 }
5701
5702 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5703                                    struct drm_atomic_state *old_state)
5704 {
5705         struct intel_atomic_state *old_intel_state =
5706                 to_intel_atomic_state(old_state);
5707         struct drm_crtc *crtc = pipe_config->base.crtc;
5708         struct drm_device *dev = crtc->dev;
5709         struct drm_i915_private *dev_priv = to_i915(dev);
5710         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5711         int pipe = intel_crtc->pipe;
5712
5713         if (WARN_ON(intel_crtc->active))
5714                 return;
5715
5716         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5717                 intel_dp_set_m_n(intel_crtc, M1_N1);
5718
5719         intel_set_pipe_timings(intel_crtc);
5720         intel_set_pipe_src_size(intel_crtc);
5721
5722         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5723                 struct drm_i915_private *dev_priv = to_i915(dev);
5724
5725                 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5726                 I915_WRITE(CHV_CANVAS(pipe), 0);
5727         }
5728
5729         i9xx_set_pipeconf(intel_crtc);
5730
5731         intel_crtc->active = true;
5732
5733         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5734
5735         intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5736
5737         if (IS_CHERRYVIEW(dev_priv)) {
5738                 chv_prepare_pll(intel_crtc, intel_crtc->config);
5739                 chv_enable_pll(intel_crtc, intel_crtc->config);
5740         } else {
5741                 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5742                 vlv_enable_pll(intel_crtc, intel_crtc->config);
5743         }
5744
5745         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5746
5747         i9xx_pfit_enable(intel_crtc);
5748
5749         intel_color_load_luts(&pipe_config->base);
5750
5751         dev_priv->display.initial_watermarks(old_intel_state,
5752                                              pipe_config);
5753         intel_enable_pipe(intel_crtc);
5754
5755         assert_vblank_disabled(crtc);
5756         drm_crtc_vblank_on(crtc);
5757
5758         intel_encoders_enable(crtc, pipe_config, old_state);
5759 }
5760
5761 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5762 {
5763         struct drm_device *dev = crtc->base.dev;
5764         struct drm_i915_private *dev_priv = to_i915(dev);
5765
5766         I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5767         I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5768 }
5769
5770 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5771                              struct drm_atomic_state *old_state)
5772 {
5773         struct drm_crtc *crtc = pipe_config->base.crtc;
5774         struct drm_device *dev = crtc->dev;
5775         struct drm_i915_private *dev_priv = to_i915(dev);
5776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5777         enum pipe pipe = intel_crtc->pipe;
5778
5779         if (WARN_ON(intel_crtc->active))
5780                 return;
5781
5782         i9xx_set_pll_dividers(intel_crtc);
5783
5784         if (intel_crtc_has_dp_encoder(intel_crtc->config))
5785                 intel_dp_set_m_n(intel_crtc, M1_N1);
5786
5787         intel_set_pipe_timings(intel_crtc);
5788         intel_set_pipe_src_size(intel_crtc);
5789
5790         i9xx_set_pipeconf(intel_crtc);
5791
5792         intel_crtc->active = true;
5793
5794         if (!IS_GEN2(dev_priv))
5795                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5796
5797         intel_encoders_pre_enable(crtc, pipe_config, old_state);
5798
5799         i9xx_enable_pll(intel_crtc);
5800
5801         i9xx_pfit_enable(intel_crtc);
5802
5803         intel_color_load_luts(&pipe_config->base);
5804
5805         intel_update_watermarks(intel_crtc);
5806         intel_enable_pipe(intel_crtc);
5807
5808         assert_vblank_disabled(crtc);
5809         drm_crtc_vblank_on(crtc);
5810
5811         intel_encoders_enable(crtc, pipe_config, old_state);
5812 }
5813
5814 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5815 {
5816         struct drm_device *dev = crtc->base.dev;
5817         struct drm_i915_private *dev_priv = to_i915(dev);
5818
5819         if (!crtc->config->gmch_pfit.control)
5820                 return;
5821
5822         assert_pipe_disabled(dev_priv, crtc->pipe);
5823
5824         DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5825                          I915_READ(PFIT_CONTROL));
5826         I915_WRITE(PFIT_CONTROL, 0);
5827 }
5828
5829 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5830                               struct drm_atomic_state *old_state)
5831 {
5832         struct drm_crtc *crtc = old_crtc_state->base.crtc;
5833         struct drm_device *dev = crtc->dev;
5834         struct drm_i915_private *dev_priv = to_i915(dev);
5835         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5836         int pipe = intel_crtc->pipe;
5837
5838         /*
5839          * On gen2 planes are double buffered but the pipe isn't, so we must
5840          * wait for planes to fully turn off before disabling the pipe.
5841          */
5842         if (IS_GEN2(dev_priv))
5843                 intel_wait_for_vblank(dev_priv, pipe);
5844
5845         intel_encoders_disable(crtc, old_crtc_state, old_state);
5846
5847         drm_crtc_vblank_off(crtc);
5848         assert_vblank_disabled(crtc);
5849
5850         intel_disable_pipe(intel_crtc);
5851
5852         i9xx_pfit_disable(intel_crtc);
5853
5854         intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5855
5856         if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5857                 if (IS_CHERRYVIEW(dev_priv))
5858                         chv_disable_pll(dev_priv, pipe);
5859                 else if (IS_VALLEYVIEW(dev_priv))
5860                         vlv_disable_pll(dev_priv, pipe);
5861                 else
5862                         i9xx_disable_pll(intel_crtc);
5863         }
5864
5865         intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
5866
5867         if (!IS_GEN2(dev_priv))
5868                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5869
5870         if (!dev_priv->display.initial_watermarks)
5871                 intel_update_watermarks(intel_crtc);
5872 }
5873
5874 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
5875 {
5876         struct intel_encoder *encoder;
5877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5878         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5879         enum intel_display_power_domain domain;
5880         u64 domains;
5881         struct drm_atomic_state *state;
5882         struct intel_crtc_state *crtc_state;
5883         int ret;
5884
5885         if (!intel_crtc->active)
5886                 return;
5887
5888         if (crtc->primary->state->visible) {
5889                 WARN_ON(intel_crtc->flip_work);
5890
5891                 intel_pre_disable_primary_noatomic(crtc);
5892
5893                 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5894                 crtc->primary->state->visible = false;
5895         }
5896
5897         state = drm_atomic_state_alloc(crtc->dev);
5898         if (!state) {
5899                 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5900                               crtc->base.id, crtc->name);
5901                 return;
5902         }
5903
5904         state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
5905
5906         /* Everything's already locked, -EDEADLK can't happen. */
5907         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5908         ret = drm_atomic_add_affected_connectors(state, crtc);
5909
5910         WARN_ON(IS_ERR(crtc_state) || ret);
5911
5912         dev_priv->display.crtc_disable(crtc_state, state);
5913
5914         drm_atomic_state_put(state);
5915
5916         DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5917                       crtc->base.id, crtc->name);
5918
5919         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5920         crtc->state->active = false;
5921         intel_crtc->active = false;
5922         crtc->enabled = false;
5923         crtc->state->connector_mask = 0;
5924         crtc->state->encoder_mask = 0;
5925
5926         for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5927                 encoder->base.crtc = NULL;
5928
5929         intel_fbc_disable(intel_crtc);
5930         intel_update_watermarks(intel_crtc);
5931         intel_disable_shared_dpll(intel_crtc);
5932
5933         domains = intel_crtc->enabled_power_domains;
5934         for_each_power_domain(domain, domains)
5935                 intel_display_power_put(dev_priv, domain);
5936         intel_crtc->enabled_power_domains = 0;
5937
5938         dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5939         dev_priv->min_pixclk[intel_crtc->pipe] = 0;
5940 }
5941
5942 /*
5943  * turn all crtc's off, but do not adjust state
5944  * This has to be paired with a call to intel_modeset_setup_hw_state.
5945  */
5946 int intel_display_suspend(struct drm_device *dev)
5947 {
5948         struct drm_i915_private *dev_priv = to_i915(dev);
5949         struct drm_atomic_state *state;
5950         int ret;
5951
5952         state = drm_atomic_helper_suspend(dev);
5953         ret = PTR_ERR_OR_ZERO(state);
5954         if (ret)
5955                 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
5956         else
5957                 dev_priv->modeset_restore_state = state;
5958         return ret;
5959 }
5960
5961 void intel_encoder_destroy(struct drm_encoder *encoder)
5962 {
5963         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5964
5965         drm_encoder_cleanup(encoder);
5966         kfree(intel_encoder);
5967 }
5968
5969 /* Cross check the actual hw state with our own modeset state tracking (and it's
5970  * internal consistency). */
5971 static void intel_connector_verify_state(struct intel_connector *connector)
5972 {
5973         struct drm_crtc *crtc = connector->base.state->crtc;
5974
5975         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5976                       connector->base.base.id,
5977                       connector->base.name);
5978
5979         if (connector->get_hw_state(connector)) {
5980                 struct intel_encoder *encoder = connector->encoder;
5981                 struct drm_connector_state *conn_state = connector->base.state;
5982
5983                 I915_STATE_WARN(!crtc,
5984                          "connector enabled without attached crtc\n");
5985
5986                 if (!crtc)
5987                         return;
5988
5989                 I915_STATE_WARN(!crtc->state->active,
5990                       "connector is active, but attached crtc isn't\n");
5991
5992                 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
5993                         return;
5994
5995                 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
5996                         "atomic encoder doesn't match attached encoder\n");
5997
5998                 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
5999                         "attached encoder crtc differs from connector crtc\n");
6000         } else {
6001                 I915_STATE_WARN(crtc && crtc->state->active,
6002                         "attached crtc is active, but connector isn't\n");
6003                 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6004                         "best encoder set without crtc!\n");
6005         }
6006 }
6007
6008 int intel_connector_init(struct intel_connector *connector)
6009 {
6010         drm_atomic_helper_connector_reset(&connector->base);
6011
6012         if (!connector->base.state)
6013                 return -ENOMEM;
6014
6015         return 0;
6016 }
6017
6018 struct intel_connector *intel_connector_alloc(void)
6019 {
6020         struct intel_connector *connector;
6021
6022         connector = kzalloc(sizeof *connector, GFP_KERNEL);
6023         if (!connector)
6024                 return NULL;
6025
6026         if (intel_connector_init(connector) < 0) {
6027                 kfree(connector);
6028                 return NULL;
6029         }
6030
6031         return connector;
6032 }
6033
6034 /* Simple connector->get_hw_state implementation for encoders that support only
6035  * one connector and no cloning and hence the encoder state determines the state
6036  * of the connector. */
6037 bool intel_connector_get_hw_state(struct intel_connector *connector)
6038 {
6039         enum pipe pipe = 0;
6040         struct intel_encoder *encoder = connector->encoder;
6041
6042         return encoder->get_hw_state(encoder, &pipe);
6043 }
6044
6045 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6046 {
6047         if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6048                 return crtc_state->fdi_lanes;
6049
6050         return 0;
6051 }
6052
6053 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6054                                      struct intel_crtc_state *pipe_config)
6055 {
6056         struct drm_i915_private *dev_priv = to_i915(dev);
6057         struct drm_atomic_state *state = pipe_config->base.state;
6058         struct intel_crtc *other_crtc;
6059         struct intel_crtc_state *other_crtc_state;
6060
6061         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6062                       pipe_name(pipe), pipe_config->fdi_lanes);
6063         if (pipe_config->fdi_lanes > 4) {
6064                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6065                               pipe_name(pipe), pipe_config->fdi_lanes);
6066                 return -EINVAL;
6067         }
6068
6069         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
6070                 if (pipe_config->fdi_lanes > 2) {
6071                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6072                                       pipe_config->fdi_lanes);
6073                         return -EINVAL;
6074                 } else {
6075                         return 0;
6076                 }
6077         }
6078
6079         if (INTEL_INFO(dev_priv)->num_pipes == 2)
6080                 return 0;
6081
6082         /* Ivybridge 3 pipe is really complicated */
6083         switch (pipe) {
6084         case PIPE_A:
6085                 return 0;
6086         case PIPE_B:
6087                 if (pipe_config->fdi_lanes <= 2)
6088                         return 0;
6089
6090                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6091                 other_crtc_state =
6092                         intel_atomic_get_crtc_state(state, other_crtc);
6093                 if (IS_ERR(other_crtc_state))
6094                         return PTR_ERR(other_crtc_state);
6095
6096                 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6097                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6098                                       pipe_name(pipe), pipe_config->fdi_lanes);
6099                         return -EINVAL;
6100                 }
6101                 return 0;
6102         case PIPE_C:
6103                 if (pipe_config->fdi_lanes > 2) {
6104                         DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6105                                       pipe_name(pipe), pipe_config->fdi_lanes);
6106                         return -EINVAL;
6107                 }
6108
6109                 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6110                 other_crtc_state =
6111                         intel_atomic_get_crtc_state(state, other_crtc);
6112                 if (IS_ERR(other_crtc_state))
6113                         return PTR_ERR(other_crtc_state);
6114
6115                 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6116                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6117                         return -EINVAL;
6118                 }
6119                 return 0;
6120         default:
6121                 BUG();
6122         }
6123 }
6124
6125 #define RETRY 1
6126 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6127                                        struct intel_crtc_state *pipe_config)
6128 {
6129         struct drm_device *dev = intel_crtc->base.dev;
6130         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6131         int lane, link_bw, fdi_dotclock, ret;
6132         bool needs_recompute = false;
6133
6134 retry:
6135         /* FDI is a binary signal running at ~2.7GHz, encoding
6136          * each output octet as 10 bits. The actual frequency
6137          * is stored as a divider into a 100MHz clock, and the
6138          * mode pixel clock is stored in units of 1KHz.
6139          * Hence the bw of each lane in terms of the mode signal
6140          * is:
6141          */
6142         link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6143
6144         fdi_dotclock = adjusted_mode->crtc_clock;
6145
6146         lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6147                                            pipe_config->pipe_bpp);
6148
6149         pipe_config->fdi_lanes = lane;
6150
6151         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6152                                link_bw, &pipe_config->fdi_m_n);
6153
6154         ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6155         if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6156                 pipe_config->pipe_bpp -= 2*3;
6157                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6158                               pipe_config->pipe_bpp);
6159                 needs_recompute = true;
6160                 pipe_config->bw_constrained = true;
6161
6162                 goto retry;
6163         }
6164
6165         if (needs_recompute)
6166                 return RETRY;
6167
6168         return ret;
6169 }
6170
6171 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6172                                      struct intel_crtc_state *pipe_config)
6173 {
6174         if (pipe_config->pipe_bpp > 24)
6175                 return false;
6176
6177         /* HSW can handle pixel rate up to cdclk? */
6178         if (IS_HASWELL(dev_priv))
6179                 return true;
6180
6181         /*
6182          * We compare against max which means we must take
6183          * the increased cdclk requirement into account when
6184          * calculating the new cdclk.
6185          *
6186          * Should measure whether using a lower cdclk w/o IPS
6187          */
6188         return pipe_config->pixel_rate <=
6189                 dev_priv->max_cdclk_freq * 95 / 100;
6190 }
6191
6192 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6193                                    struct intel_crtc_state *pipe_config)
6194 {
6195         struct drm_device *dev = crtc->base.dev;
6196         struct drm_i915_private *dev_priv = to_i915(dev);
6197
6198         pipe_config->ips_enabled = i915.enable_ips &&
6199                 hsw_crtc_supports_ips(crtc) &&
6200                 pipe_config_supports_ips(dev_priv, pipe_config);
6201 }
6202
6203 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6204 {
6205         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6206
6207         /* GDG double wide on either pipe, otherwise pipe A only */
6208         return INTEL_INFO(dev_priv)->gen < 4 &&
6209                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6210 }
6211
6212 static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6213 {
6214         uint32_t pixel_rate;
6215
6216         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6217
6218         /*
6219          * We only use IF-ID interlacing. If we ever use
6220          * PF-ID we'll need to adjust the pixel_rate here.
6221          */
6222
6223         if (pipe_config->pch_pfit.enabled) {
6224                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6225                 uint32_t pfit_size = pipe_config->pch_pfit.size;
6226
6227                 pipe_w = pipe_config->pipe_src_w;
6228                 pipe_h = pipe_config->pipe_src_h;
6229
6230                 pfit_w = (pfit_size >> 16) & 0xFFFF;
6231                 pfit_h = pfit_size & 0xFFFF;
6232                 if (pipe_w < pfit_w)
6233                         pipe_w = pfit_w;
6234                 if (pipe_h < pfit_h)
6235                         pipe_h = pfit_h;
6236
6237                 if (WARN_ON(!pfit_w || !pfit_h))
6238                         return pixel_rate;
6239
6240                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6241                                      pfit_w * pfit_h);
6242         }
6243
6244         return pixel_rate;
6245 }
6246
6247 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
6248 {
6249         struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
6250
6251         if (HAS_GMCH_DISPLAY(dev_priv))
6252                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6253                 crtc_state->pixel_rate =
6254                         crtc_state->base.adjusted_mode.crtc_clock;
6255         else
6256                 crtc_state->pixel_rate =
6257                         ilk_pipe_pixel_rate(crtc_state);
6258 }
6259
6260 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6261                                      struct intel_crtc_state *pipe_config)
6262 {
6263         struct drm_device *dev = crtc->base.dev;
6264         struct drm_i915_private *dev_priv = to_i915(dev);
6265         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6266         int clock_limit = dev_priv->max_dotclk_freq;
6267
6268         if (INTEL_GEN(dev_priv) < 4) {
6269                 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6270
6271                 /*
6272                  * Enable double wide mode when the dot clock
6273                  * is > 90% of the (display) core speed.
6274                  */
6275                 if (intel_crtc_supports_double_wide(crtc) &&
6276                     adjusted_mode->crtc_clock > clock_limit) {
6277                         clock_limit = dev_priv->max_dotclk_freq;
6278                         pipe_config->double_wide = true;
6279                 }
6280         }
6281
6282         if (adjusted_mode->crtc_clock > clock_limit) {
6283                 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6284                               adjusted_mode->crtc_clock, clock_limit,
6285                               yesno(pipe_config->double_wide));
6286                 return -EINVAL;
6287         }
6288
6289         /*
6290          * Pipe horizontal size must be even in:
6291          * - DVO ganged mode
6292          * - LVDS dual channel mode
6293          * - Double wide pipe
6294          */
6295         if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6296              intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6297                 pipe_config->pipe_src_w &= ~1;
6298
6299         /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6300          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6301          */
6302         if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6303                 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6304                 return -EINVAL;
6305
6306         intel_crtc_compute_pixel_rate(pipe_config);
6307
6308         if (HAS_IPS(dev_priv))
6309                 hsw_compute_ips_config(crtc, pipe_config);
6310
6311         if (pipe_config->has_pch_encoder)
6312                 return ironlake_fdi_compute_config(crtc, pipe_config);
6313
6314         return 0;
6315 }
6316
6317 static void
6318 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6319 {
6320         while (*num > DATA_LINK_M_N_MASK ||
6321                *den > DATA_LINK_M_N_MASK) {
6322                 *num >>= 1;
6323                 *den >>= 1;
6324         }
6325 }
6326
6327 static void compute_m_n(unsigned int m, unsigned int n,
6328                         uint32_t *ret_m, uint32_t *ret_n)
6329 {
6330         *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6331         *ret_m = div_u64((uint64_t) m * *ret_n, n);
6332         intel_reduce_m_n_ratio(ret_m, ret_n);
6333 }
6334
6335 void
6336 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6337                        int pixel_clock, int link_clock,
6338                        struct intel_link_m_n *m_n)
6339 {
6340         m_n->tu = 64;
6341
6342         compute_m_n(bits_per_pixel * pixel_clock,
6343                     link_clock * nlanes * 8,
6344                     &m_n->gmch_m, &m_n->gmch_n);
6345
6346         compute_m_n(pixel_clock, link_clock,
6347                     &m_n->link_m, &m_n->link_n);
6348 }
6349
6350 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6351 {
6352         if (i915.panel_use_ssc >= 0)
6353                 return i915.panel_use_ssc != 0;
6354         return dev_priv->vbt.lvds_use_ssc
6355                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6356 }
6357
6358 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6359 {
6360         return (1 << dpll->n) << 16 | dpll->m2;
6361 }
6362
6363 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6364 {
6365         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6366 }
6367
6368 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6369                                      struct intel_crtc_state *crtc_state,
6370                                      struct dpll *reduced_clock)
6371 {
6372         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6373         u32 fp, fp2 = 0;
6374
6375         if (IS_PINEVIEW(dev_priv)) {
6376                 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6377                 if (reduced_clock)
6378                         fp2 = pnv_dpll_compute_fp(reduced_clock);
6379         } else {
6380                 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6381                 if (reduced_clock)
6382                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
6383         }
6384
6385         crtc_state->dpll_hw_state.fp0 = fp;
6386
6387         crtc->lowfreq_avail = false;
6388         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6389             reduced_clock) {
6390                 crtc_state->dpll_hw_state.fp1 = fp2;
6391                 crtc->lowfreq_avail = true;
6392         } else {
6393                 crtc_state->dpll_hw_state.fp1 = fp;
6394         }
6395 }
6396
6397 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6398                 pipe)
6399 {
6400         u32 reg_val;
6401
6402         /*
6403          * PLLB opamp always calibrates to max value of 0x3f, force enable it
6404          * and set it to a reasonable value instead.
6405          */
6406         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6407         reg_val &= 0xffffff00;
6408         reg_val |= 0x00000030;
6409         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6410
6411         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6412         reg_val &= 0x8cffffff;
6413         reg_val = 0x8c000000;
6414         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6415
6416         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6417         reg_val &= 0xffffff00;
6418         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6419
6420         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6421         reg_val &= 0x00ffffff;
6422         reg_val |= 0xb0000000;
6423         vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6424 }
6425
6426 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6427                                          struct intel_link_m_n *m_n)
6428 {
6429         struct drm_device *dev = crtc->base.dev;
6430         struct drm_i915_private *dev_priv = to_i915(dev);
6431         int pipe = crtc->pipe;
6432
6433         I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6434         I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6435         I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6436         I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6437 }
6438
6439 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6440                                          struct intel_link_m_n *m_n,
6441                                          struct intel_link_m_n *m2_n2)
6442 {
6443         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6444         int pipe = crtc->pipe;
6445         enum transcoder transcoder = crtc->config->cpu_transcoder;
6446
6447         if (INTEL_GEN(dev_priv) >= 5) {
6448                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6449                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6450                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6451                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6452                 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6453                  * for gen < 8) and if DRRS is supported (to make sure the
6454                  * registers are not unnecessarily accessed).
6455                  */
6456                 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6457                     INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
6458                         I915_WRITE(PIPE_DATA_M2(transcoder),
6459                                         TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6460                         I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6461                         I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6462                         I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6463                 }
6464         } else {
6465                 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6466                 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6467                 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6468                 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6469         }
6470 }
6471
6472 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6473 {
6474         struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6475
6476         if (m_n == M1_N1) {
6477                 dp_m_n = &crtc->config->dp_m_n;
6478                 dp_m2_n2 = &crtc->config->dp_m2_n2;
6479         } else if (m_n == M2_N2) {
6480
6481                 /*
6482                  * M2_N2 registers are not supported. Hence m2_n2 divider value
6483                  * needs to be programmed into M1_N1.
6484                  */
6485                 dp_m_n = &crtc->config->dp_m2_n2;
6486         } else {
6487                 DRM_ERROR("Unsupported divider value\n");
6488                 return;
6489         }
6490
6491         if (crtc->config->has_pch_encoder)
6492                 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6493         else
6494                 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6495 }
6496
6497 static void vlv_compute_dpll(struct intel_crtc *crtc,
6498                              struct intel_crtc_state *pipe_config)
6499 {
6500         pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
6501                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6502         if (crtc->pipe != PIPE_A)
6503                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6504
6505         /* DPLL not used with DSI, but still need the rest set up */
6506         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6507                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6508                         DPLL_EXT_BUFFER_ENABLE_VLV;
6509
6510         pipe_config->dpll_hw_state.dpll_md =
6511                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6512 }
6513
6514 static void chv_compute_dpll(struct intel_crtc *crtc,
6515                              struct intel_crtc_state *pipe_config)
6516 {
6517         pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
6518                 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
6519         if (crtc->pipe != PIPE_A)
6520                 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6521
6522         /* DPLL not used with DSI, but still need the rest set up */
6523         if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
6524                 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6525
6526         pipe_config->dpll_hw_state.dpll_md =
6527                 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6528 }
6529
6530 static void vlv_prepare_pll(struct intel_crtc *crtc,
6531                             const struct intel_crtc_state *pipe_config)
6532 {
6533         struct drm_device *dev = crtc->base.dev;
6534         struct drm_i915_private *dev_priv = to_i915(dev);
6535         enum pipe pipe = crtc->pipe;
6536         u32 mdiv;
6537         u32 bestn, bestm1, bestm2, bestp1, bestp2;
6538         u32 coreclk, reg_val;
6539
6540         /* Enable Refclk */
6541         I915_WRITE(DPLL(pipe),
6542                    pipe_config->dpll_hw_state.dpll &
6543                    ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6544
6545         /* No need to actually set up the DPLL with DSI */
6546         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6547                 return;
6548
6549         mutex_lock(&dev_priv->sb_lock);
6550
6551         bestn = pipe_config->dpll.n;
6552         bestm1 = pipe_config->dpll.m1;
6553         bestm2 = pipe_config->dpll.m2;
6554         bestp1 = pipe_config->dpll.p1;
6555         bestp2 = pipe_config->dpll.p2;
6556
6557         /* See eDP HDMI DPIO driver vbios notes doc */
6558
6559         /* PLL B needs special handling */
6560         if (pipe == PIPE_B)
6561                 vlv_pllb_recal_opamp(dev_priv, pipe);
6562
6563         /* Set up Tx target for periodic Rcomp update */
6564         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6565
6566         /* Disable target IRef on PLL */
6567         reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6568         reg_val &= 0x00ffffff;
6569         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6570
6571         /* Disable fast lock */
6572         vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6573
6574         /* Set idtafcrecal before PLL is enabled */
6575         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6576         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6577         mdiv |= ((bestn << DPIO_N_SHIFT));
6578         mdiv |= (1 << DPIO_K_SHIFT);
6579
6580         /*
6581          * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6582          * but we don't support that).
6583          * Note: don't use the DAC post divider as it seems unstable.
6584          */
6585         mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6586         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6587
6588         mdiv |= DPIO_ENABLE_CALIBRATION;
6589         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6590
6591         /* Set HBR and RBR LPF coefficients */
6592         if (pipe_config->port_clock == 162000 ||
6593             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6594             intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
6595                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6596                                  0x009f0003);
6597         else
6598                 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6599                                  0x00d0000f);
6600
6601         if (intel_crtc_has_dp_encoder(pipe_config)) {
6602                 /* Use SSC source */
6603                 if (pipe == PIPE_A)
6604                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6605                                          0x0df40000);
6606                 else
6607                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6608                                          0x0df70000);
6609         } else { /* HDMI or VGA */
6610                 /* Use bend source */
6611                 if (pipe == PIPE_A)
6612                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6613                                          0x0df70000);
6614                 else
6615                         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6616                                          0x0df40000);
6617         }
6618
6619         coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6620         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6621         if (intel_crtc_has_dp_encoder(crtc->config))
6622                 coreclk |= 0x01000000;
6623         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6624
6625         vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6626         mutex_unlock(&dev_priv->sb_lock);
6627 }
6628
6629 static void chv_prepare_pll(struct intel_crtc *crtc,
6630                             const struct intel_crtc_state *pipe_config)
6631 {
6632         struct drm_device *dev = crtc->base.dev;
6633         struct drm_i915_private *dev_priv = to_i915(dev);
6634         enum pipe pipe = crtc->pipe;
6635         enum dpio_channel port = vlv_pipe_to_channel(pipe);
6636         u32 loopfilter, tribuf_calcntr;
6637         u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6638         u32 dpio_val;
6639         int vco;
6640
6641         /* Enable Refclk and SSC */
6642         I915_WRITE(DPLL(pipe),
6643                    pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6644
6645         /* No need to actually set up the DPLL with DSI */
6646         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6647                 return;
6648
6649         bestn = pipe_config->dpll.n;
6650         bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6651         bestm1 = pipe_config->dpll.m1;
6652         bestm2 = pipe_config->dpll.m2 >> 22;
6653         bestp1 = pipe_config->dpll.p1;
6654         bestp2 = pipe_config->dpll.p2;
6655         vco = pipe_config->dpll.vco;
6656         dpio_val = 0;
6657         loopfilter = 0;
6658
6659         mutex_lock(&dev_priv->sb_lock);
6660
6661         /* p1 and p2 divider */
6662         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6663                         5 << DPIO_CHV_S1_DIV_SHIFT |
6664                         bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6665                         bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6666                         1 << DPIO_CHV_K_DIV_SHIFT);
6667
6668         /* Feedback post-divider - m2 */
6669         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6670
6671         /* Feedback refclk divider - n and m1 */
6672         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6673                         DPIO_CHV_M1_DIV_BY_2 |
6674                         1 << DPIO_CHV_N_DIV_SHIFT);
6675
6676         /* M2 fraction division */
6677         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6678
6679         /* M2 fraction division enable */
6680         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6681         dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6682         dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6683         if (bestm2_frac)
6684                 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6685         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6686
6687         /* Program digital lock detect threshold */
6688         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6689         dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6690                                         DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6691         dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6692         if (!bestm2_frac)
6693                 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6694         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6695
6696         /* Loop filter */
6697         if (vco == 5400000) {
6698                 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6699                 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6700                 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6701                 tribuf_calcntr = 0x9;
6702         } else if (vco <= 6200000) {
6703                 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6704                 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6705                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6706                 tribuf_calcntr = 0x9;
6707         } else if (vco <= 6480000) {
6708                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6709                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6710                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6711                 tribuf_calcntr = 0x8;
6712         } else {
6713                 /* Not supported. Apply the same limits as in the max case */
6714                 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6715                 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6716                 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6717                 tribuf_calcntr = 0;
6718         }
6719         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6720
6721         dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6722         dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6723         dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6724         vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6725
6726         /* AFC Recal */
6727         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6728                         vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6729                         DPIO_AFC_RECAL);
6730
6731         mutex_unlock(&dev_priv->sb_lock);
6732 }
6733
6734 /**
6735  * vlv_force_pll_on - forcibly enable just the PLL
6736  * @dev_priv: i915 private structure
6737  * @pipe: pipe PLL to enable
6738  * @dpll: PLL configuration
6739  *
6740  * Enable the PLL for @pipe using the supplied @dpll config. To be used
6741  * in cases where we need the PLL enabled even when @pipe is not going to
6742  * be enabled.
6743  */
6744 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
6745                      const struct dpll *dpll)
6746 {
6747         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
6748         struct intel_crtc_state *pipe_config;
6749
6750         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6751         if (!pipe_config)
6752                 return -ENOMEM;
6753
6754         pipe_config->base.crtc = &crtc->base;
6755         pipe_config->pixel_multiplier = 1;
6756         pipe_config->dpll = *dpll;
6757
6758         if (IS_CHERRYVIEW(dev_priv)) {
6759                 chv_compute_dpll(crtc, pipe_config);
6760                 chv_prepare_pll(crtc, pipe_config);
6761                 chv_enable_pll(crtc, pipe_config);
6762         } else {
6763                 vlv_compute_dpll(crtc, pipe_config);
6764                 vlv_prepare_pll(crtc, pipe_config);
6765                 vlv_enable_pll(crtc, pipe_config);
6766         }
6767
6768         kfree(pipe_config);
6769
6770         return 0;
6771 }
6772
6773 /**
6774  * vlv_force_pll_off - forcibly disable just the PLL
6775  * @dev_priv: i915 private structure
6776  * @pipe: pipe PLL to disable
6777  *
6778  * Disable the PLL for @pipe. To be used in cases where we need
6779  * the PLL enabled even when @pipe is not going to be enabled.
6780  */
6781 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
6782 {
6783         if (IS_CHERRYVIEW(dev_priv))
6784                 chv_disable_pll(dev_priv, pipe);
6785         else
6786                 vlv_disable_pll(dev_priv, pipe);
6787 }
6788
6789 static void i9xx_compute_dpll(struct intel_crtc *crtc,
6790                               struct intel_crtc_state *crtc_state,
6791                               struct dpll *reduced_clock)
6792 {
6793         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6794         u32 dpll;
6795         struct dpll *clock = &crtc_state->dpll;
6796
6797         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6798
6799         dpll = DPLL_VGA_MODE_DIS;
6800
6801         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
6802                 dpll |= DPLLB_MODE_LVDS;
6803         else
6804                 dpll |= DPLLB_MODE_DAC_SERIAL;
6805
6806         if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6807             IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6808                 dpll |= (crtc_state->pixel_multiplier - 1)
6809                         << SDVO_MULTIPLIER_SHIFT_HIRES;
6810         }
6811
6812         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6813             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
6814                 dpll |= DPLL_SDVO_HIGH_SPEED;
6815
6816         if (intel_crtc_has_dp_encoder(crtc_state))
6817                 dpll |= DPLL_SDVO_HIGH_SPEED;
6818
6819         /* compute bitmask from p1 value */
6820         if (IS_PINEVIEW(dev_priv))
6821                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6822         else {
6823                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6824                 if (IS_G4X(dev_priv) && reduced_clock)
6825                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6826         }
6827         switch (clock->p2) {
6828         case 5:
6829                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6830                 break;
6831         case 7:
6832                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6833                 break;
6834         case 10:
6835                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6836                 break;
6837         case 14:
6838                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6839                 break;
6840         }
6841         if (INTEL_GEN(dev_priv) >= 4)
6842                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6843
6844         if (crtc_state->sdvo_tv_clock)
6845                 dpll |= PLL_REF_INPUT_TVCLKINBC;
6846         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6847                  intel_panel_use_ssc(dev_priv))
6848                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6849         else
6850                 dpll |= PLL_REF_INPUT_DREFCLK;
6851
6852         dpll |= DPLL_VCO_ENABLE;
6853         crtc_state->dpll_hw_state.dpll = dpll;
6854
6855         if (INTEL_GEN(dev_priv) >= 4) {
6856                 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6857                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6858                 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6859         }
6860 }
6861
6862 static void i8xx_compute_dpll(struct intel_crtc *crtc,
6863                               struct intel_crtc_state *crtc_state,
6864                               struct dpll *reduced_clock)
6865 {
6866         struct drm_device *dev = crtc->base.dev;
6867         struct drm_i915_private *dev_priv = to_i915(dev);
6868         u32 dpll;
6869         struct dpll *clock = &crtc_state->dpll;
6870
6871         i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6872
6873         dpll = DPLL_VGA_MODE_DIS;
6874
6875         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
6876                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6877         } else {
6878                 if (clock->p1 == 2)
6879                         dpll |= PLL_P1_DIVIDE_BY_TWO;
6880                 else
6881                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6882                 if (clock->p2 == 4)
6883                         dpll |= PLL_P2_DIVIDE_BY_4;
6884         }
6885
6886         if (!IS_I830(dev_priv) &&
6887             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
6888                 dpll |= DPLL_DVO_2X_MODE;
6889
6890         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6891             intel_panel_use_ssc(dev_priv))
6892                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6893         else
6894                 dpll |= PLL_REF_INPUT_DREFCLK;
6895
6896         dpll |= DPLL_VCO_ENABLE;
6897         crtc_state->dpll_hw_state.dpll = dpll;
6898 }
6899
6900 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6901 {
6902         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6903         enum pipe pipe = intel_crtc->pipe;
6904         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6905         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
6906         uint32_t crtc_vtotal, crtc_vblank_end;
6907         int vsyncshift = 0;
6908
6909         /* We need to be careful not to changed the adjusted mode, for otherwise
6910          * the hw state checker will get angry at the mismatch. */
6911         crtc_vtotal = adjusted_mode->crtc_vtotal;
6912         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6913
6914         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6915                 /* the chip adds 2 halflines automatically */
6916                 crtc_vtotal -= 1;
6917                 crtc_vblank_end -= 1;
6918
6919                 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
6920                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6921                 else
6922                         vsyncshift = adjusted_mode->crtc_hsync_start -
6923                                 adjusted_mode->crtc_htotal / 2;
6924                 if (vsyncshift < 0)
6925                         vsyncshift += adjusted_mode->crtc_htotal;
6926         }
6927
6928         if (INTEL_GEN(dev_priv) > 3)
6929                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6930
6931         I915_WRITE(HTOTAL(cpu_transcoder),
6932                    (adjusted_mode->crtc_hdisplay - 1) |
6933                    ((adjusted_mode->crtc_htotal - 1) << 16));
6934         I915_WRITE(HBLANK(cpu_transcoder),
6935                    (adjusted_mode->crtc_hblank_start - 1) |
6936                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
6937         I915_WRITE(HSYNC(cpu_transcoder),
6938                    (adjusted_mode->crtc_hsync_start - 1) |
6939                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
6940
6941         I915_WRITE(VTOTAL(cpu_transcoder),
6942                    (adjusted_mode->crtc_vdisplay - 1) |
6943                    ((crtc_vtotal - 1) << 16));
6944         I915_WRITE(VBLANK(cpu_transcoder),
6945                    (adjusted_mode->crtc_vblank_start - 1) |
6946                    ((crtc_vblank_end - 1) << 16));
6947         I915_WRITE(VSYNC(cpu_transcoder),
6948                    (adjusted_mode->crtc_vsync_start - 1) |
6949                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
6950
6951         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6952          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6953          * documented on the DDI_FUNC_CTL register description, EDP Input Select
6954          * bits. */
6955         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
6956             (pipe == PIPE_B || pipe == PIPE_C))
6957                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6958
6959 }
6960
6961 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6962 {
6963         struct drm_device *dev = intel_crtc->base.dev;
6964         struct drm_i915_private *dev_priv = to_i915(dev);
6965         enum pipe pipe = intel_crtc->pipe;
6966
6967         /* pipesrc controls the size that is scaled from, which should
6968          * always be the user's requested size.
6969          */
6970         I915_WRITE(PIPESRC(pipe),
6971                    ((intel_crtc->config->pipe_src_w - 1) << 16) |
6972                    (intel_crtc->config->pipe_src_h - 1));
6973 }
6974
6975 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6976                                    struct intel_crtc_state *pipe_config)
6977 {
6978         struct drm_device *dev = crtc->base.dev;
6979         struct drm_i915_private *dev_priv = to_i915(dev);
6980         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6981         uint32_t tmp;
6982
6983         tmp = I915_READ(HTOTAL(cpu_transcoder));
6984         pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6985         pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6986         tmp = I915_READ(HBLANK(cpu_transcoder));
6987         pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6988         pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6989         tmp = I915_READ(HSYNC(cpu_transcoder));
6990         pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6991         pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6992
6993         tmp = I915_READ(VTOTAL(cpu_transcoder));
6994         pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6995         pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6996         tmp = I915_READ(VBLANK(cpu_transcoder));
6997         pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6998         pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6999         tmp = I915_READ(VSYNC(cpu_transcoder));
7000         pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7001         pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7002
7003         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7004                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7005                 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7006                 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7007         }
7008 }
7009
7010 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7011                                     struct intel_crtc_state *pipe_config)
7012 {
7013         struct drm_device *dev = crtc->base.dev;
7014         struct drm_i915_private *dev_priv = to_i915(dev);
7015         u32 tmp;
7016
7017         tmp = I915_READ(PIPESRC(crtc->pipe));
7018         pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7019         pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7020
7021         pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7022         pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7023 }
7024
7025 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7026                                  struct intel_crtc_state *pipe_config)
7027 {
7028         mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7029         mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7030         mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7031         mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7032
7033         mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7034         mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7035         mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7036         mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7037
7038         mode->flags = pipe_config->base.adjusted_mode.flags;
7039         mode->type = DRM_MODE_TYPE_DRIVER;
7040
7041         mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7042
7043         mode->hsync = drm_mode_hsync(mode);
7044         mode->vrefresh = drm_mode_vrefresh(mode);
7045         drm_mode_set_name(mode);
7046 }
7047
7048 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7049 {
7050         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
7051         uint32_t pipeconf;
7052
7053         pipeconf = 0;
7054
7055         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7056             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7057                 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7058
7059         if (intel_crtc->config->double_wide)
7060                 pipeconf |= PIPECONF_DOUBLE_WIDE;
7061
7062         /* only g4x and later have fancy bpc/dither controls */
7063         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7064             IS_CHERRYVIEW(dev_priv)) {
7065                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7066                 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7067                         pipeconf |= PIPECONF_DITHER_EN |
7068                                     PIPECONF_DITHER_TYPE_SP;
7069
7070                 switch (intel_crtc->config->pipe_bpp) {
7071                 case 18:
7072                         pipeconf |= PIPECONF_6BPC;
7073                         break;
7074                 case 24:
7075                         pipeconf |= PIPECONF_8BPC;
7076                         break;
7077                 case 30:
7078                         pipeconf |= PIPECONF_10BPC;
7079                         break;
7080                 default:
7081                         /* Case prevented by intel_choose_pipe_bpp_dither. */
7082                         BUG();
7083                 }
7084         }
7085
7086         if (HAS_PIPE_CXSR(dev_priv)) {
7087                 if (intel_crtc->lowfreq_avail) {
7088                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7089                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7090                 } else {
7091                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7092                 }
7093         }
7094
7095         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7096                 if (INTEL_GEN(dev_priv) < 4 ||
7097                     intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7098                         pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7099                 else
7100                         pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7101         } else
7102                 pipeconf |= PIPECONF_PROGRESSIVE;
7103
7104         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7105              intel_crtc->config->limited_color_range)
7106                 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7107
7108         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7109         POSTING_READ(PIPECONF(intel_crtc->pipe));
7110 }
7111
7112 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7113                                    struct intel_crtc_state *crtc_state)
7114 {
7115         struct drm_device *dev = crtc->base.dev;
7116         struct drm_i915_private *dev_priv = to_i915(dev);
7117         const struct intel_limit *limit;
7118         int refclk = 48000;
7119
7120         memset(&crtc_state->dpll_hw_state, 0,
7121                sizeof(crtc_state->dpll_hw_state));
7122
7123         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7124                 if (intel_panel_use_ssc(dev_priv)) {
7125                         refclk = dev_priv->vbt.lvds_ssc_freq;
7126                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7127                 }
7128
7129                 limit = &intel_limits_i8xx_lvds;
7130         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
7131                 limit = &intel_limits_i8xx_dvo;
7132         } else {
7133                 limit = &intel_limits_i8xx_dac;
7134         }
7135
7136         if (!crtc_state->clock_set &&
7137             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7138                                  refclk, NULL, &crtc_state->dpll)) {
7139                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7140                 return -EINVAL;
7141         }
7142
7143         i8xx_compute_dpll(crtc, crtc_state, NULL);
7144
7145         return 0;
7146 }
7147
7148 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7149                                   struct intel_crtc_state *crtc_state)
7150 {
7151         struct drm_device *dev = crtc->base.dev;
7152         struct drm_i915_private *dev_priv = to_i915(dev);
7153         const struct intel_limit *limit;
7154         int refclk = 96000;
7155
7156         memset(&crtc_state->dpll_hw_state, 0,
7157                sizeof(crtc_state->dpll_hw_state));
7158
7159         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7160                 if (intel_panel_use_ssc(dev_priv)) {
7161                         refclk = dev_priv->vbt.lvds_ssc_freq;
7162                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7163                 }
7164
7165                 if (intel_is_dual_link_lvds(dev))
7166                         limit = &intel_limits_g4x_dual_channel_lvds;
7167                 else
7168                         limit = &intel_limits_g4x_single_channel_lvds;
7169         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7170                    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7171                 limit = &intel_limits_g4x_hdmi;
7172         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7173                 limit = &intel_limits_g4x_sdvo;
7174         } else {
7175                 /* The option is for other outputs */
7176                 limit = &intel_limits_i9xx_sdvo;
7177         }
7178
7179         if (!crtc_state->clock_set &&
7180             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7181                                 refclk, NULL, &crtc_state->dpll)) {
7182                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7183                 return -EINVAL;
7184         }
7185
7186         i9xx_compute_dpll(crtc, crtc_state, NULL);
7187
7188         return 0;
7189 }
7190
7191 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7192                                   struct intel_crtc_state *crtc_state)
7193 {
7194         struct drm_device *dev = crtc->base.dev;
7195         struct drm_i915_private *dev_priv = to_i915(dev);
7196         const struct intel_limit *limit;
7197         int refclk = 96000;
7198
7199         memset(&crtc_state->dpll_hw_state, 0,
7200                sizeof(crtc_state->dpll_hw_state));
7201
7202         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7203                 if (intel_panel_use_ssc(dev_priv)) {
7204                         refclk = dev_priv->vbt.lvds_ssc_freq;
7205                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7206                 }
7207
7208                 limit = &intel_limits_pineview_lvds;
7209         } else {
7210                 limit = &intel_limits_pineview_sdvo;
7211         }
7212
7213         if (!crtc_state->clock_set &&
7214             !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7215                                 refclk, NULL, &crtc_state->dpll)) {
7216                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7217                 return -EINVAL;
7218         }
7219
7220         i9xx_compute_dpll(crtc, crtc_state, NULL);
7221
7222         return 0;
7223 }
7224
7225 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7226                                    struct intel_crtc_state *crtc_state)
7227 {
7228         struct drm_device *dev = crtc->base.dev;
7229         struct drm_i915_private *dev_priv = to_i915(dev);
7230         const struct intel_limit *limit;
7231         int refclk = 96000;
7232
7233         memset(&crtc_state->dpll_hw_state, 0,
7234                sizeof(crtc_state->dpll_hw_state));
7235
7236         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7237                 if (intel_panel_use_ssc(dev_priv)) {
7238                         refclk = dev_priv->vbt.lvds_ssc_freq;
7239                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7240                 }
7241
7242                 limit = &intel_limits_i9xx_lvds;
7243         } else {
7244                 limit = &intel_limits_i9xx_sdvo;
7245         }
7246
7247         if (!crtc_state->clock_set &&
7248             !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7249                                  refclk, NULL, &crtc_state->dpll)) {
7250                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7251                 return -EINVAL;
7252         }
7253
7254         i9xx_compute_dpll(crtc, crtc_state, NULL);
7255
7256         return 0;
7257 }
7258
7259 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7260                                   struct intel_crtc_state *crtc_state)
7261 {
7262         int refclk = 100000;
7263         const struct intel_limit *limit = &intel_limits_chv;
7264
7265         memset(&crtc_state->dpll_hw_state, 0,
7266                sizeof(crtc_state->dpll_hw_state));
7267
7268         if (!crtc_state->clock_set &&
7269             !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7270                                 refclk, NULL, &crtc_state->dpll)) {
7271                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7272                 return -EINVAL;
7273         }
7274
7275         chv_compute_dpll(crtc, crtc_state);
7276
7277         return 0;
7278 }
7279
7280 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7281                                   struct intel_crtc_state *crtc_state)
7282 {
7283         int refclk = 100000;
7284         const struct intel_limit *limit = &intel_limits_vlv;
7285
7286         memset(&crtc_state->dpll_hw_state, 0,
7287                sizeof(crtc_state->dpll_hw_state));
7288
7289         if (!crtc_state->clock_set &&
7290             !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7291                                 refclk, NULL, &crtc_state->dpll)) {
7292                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7293                 return -EINVAL;
7294         }
7295
7296         vlv_compute_dpll(crtc, crtc_state);
7297
7298         return 0;
7299 }
7300
7301 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7302                                  struct intel_crtc_state *pipe_config)
7303 {
7304         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7305         uint32_t tmp;
7306
7307         if (INTEL_GEN(dev_priv) <= 3 &&
7308             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
7309                 return;
7310
7311         tmp = I915_READ(PFIT_CONTROL);
7312         if (!(tmp & PFIT_ENABLE))
7313                 return;
7314
7315         /* Check whether the pfit is attached to our pipe. */
7316         if (INTEL_GEN(dev_priv) < 4) {
7317                 if (crtc->pipe != PIPE_B)
7318                         return;
7319         } else {
7320                 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7321                         return;
7322         }
7323
7324         pipe_config->gmch_pfit.control = tmp;
7325         pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7326 }
7327
7328 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7329                                struct intel_crtc_state *pipe_config)
7330 {
7331         struct drm_device *dev = crtc->base.dev;
7332         struct drm_i915_private *dev_priv = to_i915(dev);
7333         int pipe = pipe_config->cpu_transcoder;
7334         struct dpll clock;
7335         u32 mdiv;
7336         int refclk = 100000;
7337
7338         /* In case of DSI, DPLL will not be used */
7339         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7340                 return;
7341
7342         mutex_lock(&dev_priv->sb_lock);
7343         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7344         mutex_unlock(&dev_priv->sb_lock);
7345
7346         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7347         clock.m2 = mdiv & DPIO_M2DIV_MASK;
7348         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7349         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7350         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7351
7352         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
7353 }
7354
7355 static void
7356 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7357                               struct intel_initial_plane_config *plane_config)
7358 {
7359         struct drm_device *dev = crtc->base.dev;
7360         struct drm_i915_private *dev_priv = to_i915(dev);
7361         u32 val, base, offset;
7362         int pipe = crtc->pipe, plane = crtc->plane;
7363         int fourcc, pixel_format;
7364         unsigned int aligned_height;
7365         struct drm_framebuffer *fb;
7366         struct intel_framebuffer *intel_fb;
7367
7368         val = I915_READ(DSPCNTR(plane));
7369         if (!(val & DISPLAY_PLANE_ENABLE))
7370                 return;
7371
7372         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7373         if (!intel_fb) {
7374                 DRM_DEBUG_KMS("failed to alloc fb\n");
7375                 return;
7376         }
7377
7378         fb = &intel_fb->base;
7379
7380         fb->dev = dev;
7381
7382         if (INTEL_GEN(dev_priv) >= 4) {
7383                 if (val & DISPPLANE_TILED) {
7384                         plane_config->tiling = I915_TILING_X;
7385                         fb->modifier = I915_FORMAT_MOD_X_TILED;
7386                 }
7387         }
7388
7389         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7390         fourcc = i9xx_format_to_fourcc(pixel_format);
7391         fb->format = drm_format_info(fourcc);
7392
7393         if (INTEL_GEN(dev_priv) >= 4) {
7394                 if (plane_config->tiling)
7395                         offset = I915_READ(DSPTILEOFF(plane));
7396                 else
7397                         offset = I915_READ(DSPLINOFF(plane));
7398                 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7399         } else {
7400                 base = I915_READ(DSPADDR(plane));
7401         }
7402         plane_config->base = base;
7403
7404         val = I915_READ(PIPESRC(pipe));
7405         fb->width = ((val >> 16) & 0xfff) + 1;
7406         fb->height = ((val >> 0) & 0xfff) + 1;
7407
7408         val = I915_READ(DSPSTRIDE(pipe));
7409         fb->pitches[0] = val & 0xffffffc0;
7410
7411         aligned_height = intel_fb_align_height(fb, 0, fb->height);
7412
7413         plane_config->size = fb->pitches[0] * aligned_height;
7414
7415         DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7416                       pipe_name(pipe), plane, fb->width, fb->height,
7417                       fb->format->cpp[0] * 8, base, fb->pitches[0],
7418                       plane_config->size);
7419
7420         plane_config->fb = intel_fb;
7421 }
7422
7423 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7424                                struct intel_crtc_state *pipe_config)
7425 {
7426         struct drm_device *dev = crtc->base.dev;
7427         struct drm_i915_private *dev_priv = to_i915(dev);
7428         int pipe = pipe_config->cpu_transcoder;
7429         enum dpio_channel port = vlv_pipe_to_channel(pipe);
7430         struct dpll clock;
7431         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
7432         int refclk = 100000;
7433
7434         /* In case of DSI, DPLL will not be used */
7435         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7436                 return;
7437
7438         mutex_lock(&dev_priv->sb_lock);
7439         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7440         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7441         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7442         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7443         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7444         mutex_unlock(&dev_priv->sb_lock);
7445
7446         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7447         clock.m2 = (pll_dw0 & 0xff) << 22;
7448         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7449                 clock.m2 |= pll_dw2 & 0x3fffff;
7450         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7451         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7452         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7453
7454         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
7455 }
7456
7457 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7458                                  struct intel_crtc_state *pipe_config)
7459 {
7460         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7461         enum intel_display_power_domain power_domain;
7462         uint32_t tmp;
7463         bool ret;
7464
7465         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7466         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
7467                 return false;
7468
7469         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7470         pipe_config->shared_dpll = NULL;
7471
7472         ret = false;
7473
7474         tmp = I915_READ(PIPECONF(crtc->pipe));
7475         if (!(tmp & PIPECONF_ENABLE))
7476                 goto out;
7477
7478         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7479             IS_CHERRYVIEW(dev_priv)) {
7480                 switch (tmp & PIPECONF_BPC_MASK) {
7481                 case PIPECONF_6BPC:
7482                         pipe_config->pipe_bpp = 18;
7483                         break;
7484                 case PIPECONF_8BPC:
7485                         pipe_config->pipe_bpp = 24;
7486                         break;
7487                 case PIPECONF_10BPC:
7488                         pipe_config->pipe_bpp = 30;
7489                         break;
7490                 default:
7491                         break;
7492                 }
7493         }
7494
7495         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
7496             (tmp & PIPECONF_COLOR_RANGE_SELECT))
7497                 pipe_config->limited_color_range = true;
7498
7499         if (INTEL_GEN(dev_priv) < 4)
7500                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7501
7502         intel_get_pipe_timings(crtc, pipe_config);
7503         intel_get_pipe_src_size(crtc, pipe_config);
7504
7505         i9xx_get_pfit_config(crtc, pipe_config);
7506
7507         if (INTEL_GEN(dev_priv) >= 4) {
7508                 /* No way to read it out on pipes B and C */
7509                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
7510                         tmp = dev_priv->chv_dpll_md[crtc->pipe];
7511                 else
7512                         tmp = I915_READ(DPLL_MD(crtc->pipe));
7513                 pipe_config->pixel_multiplier =
7514                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7515                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7516                 pipe_config->dpll_hw_state.dpll_md = tmp;
7517         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
7518                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
7519                 tmp = I915_READ(DPLL(crtc->pipe));
7520                 pipe_config->pixel_multiplier =
7521                         ((tmp & SDVO_MULTIPLIER_MASK)
7522                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7523         } else {
7524                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7525                  * port and will be fixed up in the encoder->get_config
7526                  * function. */
7527                 pipe_config->pixel_multiplier = 1;
7528         }
7529         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7530         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
7531                 /*
7532                  * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7533                  * on 830. Filter it out here so that we don't
7534                  * report errors due to that.
7535                  */
7536                 if (IS_I830(dev_priv))
7537                         pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7538
7539                 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7540                 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7541         } else {
7542                 /* Mask out read-only status bits. */
7543                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7544                                                      DPLL_PORTC_READY_MASK |
7545                                                      DPLL_PORTB_READY_MASK);
7546         }
7547
7548         if (IS_CHERRYVIEW(dev_priv))
7549                 chv_crtc_clock_get(crtc, pipe_config);
7550         else if (IS_VALLEYVIEW(dev_priv))
7551                 vlv_crtc_clock_get(crtc, pipe_config);
7552         else
7553                 i9xx_crtc_clock_get(crtc, pipe_config);
7554
7555         /*
7556          * Normally the dotclock is filled in by the encoder .get_config()
7557          * but in case the pipe is enabled w/o any ports we need a sane
7558          * default.
7559          */
7560         pipe_config->base.adjusted_mode.crtc_clock =
7561                 pipe_config->port_clock / pipe_config->pixel_multiplier;
7562
7563         ret = true;
7564
7565 out:
7566         intel_display_power_put(dev_priv, power_domain);
7567
7568         return ret;
7569 }
7570
7571 static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
7572 {
7573         struct intel_encoder *encoder;
7574         int i;
7575         u32 val, final;
7576         bool has_lvds = false;
7577         bool has_cpu_edp = false;
7578         bool has_panel = false;
7579         bool has_ck505 = false;
7580         bool can_ssc = false;
7581         bool using_ssc_source = false;
7582
7583         /* We need to take the global config into account */
7584         for_each_intel_encoder(&dev_priv->drm, encoder) {
7585                 switch (encoder->type) {
7586                 case INTEL_OUTPUT_LVDS:
7587                         has_panel = true;
7588                         has_lvds = true;
7589                         break;
7590                 case INTEL_OUTPUT_EDP:
7591                         has_panel = true;
7592                         if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7593                                 has_cpu_edp = true;
7594                         break;
7595                 default:
7596                         break;
7597                 }
7598         }
7599
7600         if (HAS_PCH_IBX(dev_priv)) {
7601                 has_ck505 = dev_priv->vbt.display_clock_mode;
7602                 can_ssc = has_ck505;
7603         } else {
7604                 has_ck505 = false;
7605                 can_ssc = true;
7606         }
7607
7608         /* Check if any DPLLs are using the SSC source */
7609         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7610                 u32 temp = I915_READ(PCH_DPLL(i));
7611
7612                 if (!(temp & DPLL_VCO_ENABLE))
7613                         continue;
7614
7615                 if ((temp & PLL_REF_INPUT_MASK) ==
7616                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7617                         using_ssc_source = true;
7618                         break;
7619                 }
7620         }
7621
7622         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7623                       has_panel, has_lvds, has_ck505, using_ssc_source);
7624
7625         /* Ironlake: try to setup display ref clock before DPLL
7626          * enabling. This is only under driver's control after
7627          * PCH B stepping, previous chipset stepping should be
7628          * ignoring this setting.
7629          */
7630         val = I915_READ(PCH_DREF_CONTROL);
7631
7632         /* As we must carefully and slowly disable/enable each source in turn,
7633          * compute the final state we want first and check if we need to
7634          * make any changes at all.
7635          */
7636         final = val;
7637         final &= ~DREF_NONSPREAD_SOURCE_MASK;
7638         if (has_ck505)
7639                 final |= DREF_NONSPREAD_CK505_ENABLE;
7640         else
7641                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7642
7643         final &= ~DREF_SSC_SOURCE_MASK;
7644         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7645         final &= ~DREF_SSC1_ENABLE;
7646
7647         if (has_panel) {
7648                 final |= DREF_SSC_SOURCE_ENABLE;
7649
7650                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7651                         final |= DREF_SSC1_ENABLE;
7652
7653                 if (has_cpu_edp) {
7654                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
7655                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7656                         else
7657                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7658                 } else
7659                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7660         } else if (using_ssc_source) {
7661                 final |= DREF_SSC_SOURCE_ENABLE;
7662                 final |= DREF_SSC1_ENABLE;
7663         }
7664
7665         if (final == val)
7666                 return;
7667
7668         /* Always enable nonspread source */
7669         val &= ~DREF_NONSPREAD_SOURCE_MASK;
7670
7671         if (has_ck505)
7672                 val |= DREF_NONSPREAD_CK505_ENABLE;
7673         else
7674                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7675
7676         if (has_panel) {
7677                 val &= ~DREF_SSC_SOURCE_MASK;
7678                 val |= DREF_SSC_SOURCE_ENABLE;
7679
7680                 /* SSC must be turned on before enabling the CPU output  */
7681                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7682                         DRM_DEBUG_KMS("Using SSC on panel\n");
7683                         val |= DREF_SSC1_ENABLE;
7684                 } else
7685                         val &= ~DREF_SSC1_ENABLE;
7686
7687                 /* Get SSC going before enabling the outputs */
7688                 I915_WRITE(PCH_DREF_CONTROL, val);
7689                 POSTING_READ(PCH_DREF_CONTROL);
7690                 udelay(200);
7691
7692                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7693
7694                 /* Enable CPU source on CPU attached eDP */
7695                 if (has_cpu_edp) {
7696                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7697                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
7698                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7699                         } else
7700                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7701                 } else
7702                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7703
7704                 I915_WRITE(PCH_DREF_CONTROL, val);
7705                 POSTING_READ(PCH_DREF_CONTROL);
7706                 udelay(200);
7707         } else {
7708                 DRM_DEBUG_KMS("Disabling CPU source output\n");
7709
7710                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7711
7712                 /* Turn off CPU output */
7713                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7714
7715                 I915_WRITE(PCH_DREF_CONTROL, val);
7716                 POSTING_READ(PCH_DREF_CONTROL);
7717                 udelay(200);
7718
7719                 if (!using_ssc_source) {
7720                         DRM_DEBUG_KMS("Disabling SSC source\n");
7721
7722                         /* Turn off the SSC source */
7723                         val &= ~DREF_SSC_SOURCE_MASK;
7724                         val |= DREF_SSC_SOURCE_DISABLE;
7725
7726                         /* Turn off SSC1 */
7727                         val &= ~DREF_SSC1_ENABLE;
7728
7729                         I915_WRITE(PCH_DREF_CONTROL, val);
7730                         POSTING_READ(PCH_DREF_CONTROL);
7731                         udelay(200);
7732                 }
7733         }
7734
7735         BUG_ON(val != final);
7736 }
7737
7738 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7739 {
7740         uint32_t tmp;
7741
7742         tmp = I915_READ(SOUTH_CHICKEN2);
7743         tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7744         I915_WRITE(SOUTH_CHICKEN2, tmp);
7745
7746         if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7747                         FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7748                 DRM_ERROR("FDI mPHY reset assert timeout\n");
7749
7750         tmp = I915_READ(SOUTH_CHICKEN2);
7751         tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7752         I915_WRITE(SOUTH_CHICKEN2, tmp);
7753
7754         if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7755                          FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7756                 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7757 }
7758
7759 /* WaMPhyProgramming:hsw */
7760 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7761 {
7762         uint32_t tmp;
7763
7764         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7765         tmp &= ~(0xFF << 24);
7766         tmp |= (0x12 << 24);
7767         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7768
7769         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7770         tmp |= (1 << 11);
7771         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7772
7773         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7774         tmp |= (1 << 11);
7775         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7776
7777         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7778         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7779         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7780
7781         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7782         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7783         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7784
7785         tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7786         tmp &= ~(7 << 13);
7787         tmp |= (5 << 13);
7788         intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7789
7790         tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7791         tmp &= ~(7 << 13);
7792         tmp |= (5 << 13);
7793         intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7794
7795         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7796         tmp &= ~0xFF;
7797         tmp |= 0x1C;
7798         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7799
7800         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7801         tmp &= ~0xFF;
7802         tmp |= 0x1C;
7803         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7804
7805         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7806         tmp &= ~(0xFF << 16);
7807         tmp |= (0x1C << 16);
7808         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7809
7810         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7811         tmp &= ~(0xFF << 16);
7812         tmp |= (0x1C << 16);
7813         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7814
7815         tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7816         tmp |= (1 << 27);
7817         intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7818
7819         tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7820         tmp |= (1 << 27);
7821         intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7822
7823         tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7824         tmp &= ~(0xF << 28);
7825         tmp |= (4 << 28);
7826         intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7827
7828         tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7829         tmp &= ~(0xF << 28);
7830         tmp |= (4 << 28);
7831         intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7832 }
7833
7834 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7835  * Programming" based on the parameters passed:
7836  * - Sequence to enable CLKOUT_DP
7837  * - Sequence to enable CLKOUT_DP without spread
7838  * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7839  */
7840 static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7841                                  bool with_spread, bool with_fdi)
7842 {
7843         uint32_t reg, tmp;
7844
7845         if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7846                 with_spread = true;
7847         if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7848             with_fdi, "LP PCH doesn't have FDI\n"))
7849                 with_fdi = false;
7850
7851         mutex_lock(&dev_priv->sb_lock);
7852
7853         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7854         tmp &= ~SBI_SSCCTL_DISABLE;
7855         tmp |= SBI_SSCCTL_PATHALT;
7856         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7857
7858         udelay(24);
7859
7860         if (with_spread) {
7861                 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7862                 tmp &= ~SBI_SSCCTL_PATHALT;
7863                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7864
7865                 if (with_fdi) {
7866                         lpt_reset_fdi_mphy(dev_priv);
7867                         lpt_program_fdi_mphy(dev_priv);
7868                 }
7869         }
7870
7871         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7872         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7873         tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7874         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7875
7876         mutex_unlock(&dev_priv->sb_lock);
7877 }
7878
7879 /* Sequence to disable CLKOUT_DP */
7880 static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
7881 {
7882         uint32_t reg, tmp;
7883
7884         mutex_lock(&dev_priv->sb_lock);
7885
7886         reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
7887         tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7888         tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7889         intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7890
7891         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7892         if (!(tmp & SBI_SSCCTL_DISABLE)) {
7893                 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7894                         tmp |= SBI_SSCCTL_PATHALT;
7895                         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7896                         udelay(32);
7897                 }
7898                 tmp |= SBI_SSCCTL_DISABLE;
7899                 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7900         }
7901
7902         mutex_unlock(&dev_priv->sb_lock);
7903 }
7904
7905 #define BEND_IDX(steps) ((50 + (steps)) / 5)
7906
7907 static const uint16_t sscdivintphase[] = {
7908         [BEND_IDX( 50)] = 0x3B23,
7909         [BEND_IDX( 45)] = 0x3B23,
7910         [BEND_IDX( 40)] = 0x3C23,
7911         [BEND_IDX( 35)] = 0x3C23,
7912         [BEND_IDX( 30)] = 0x3D23,
7913         [BEND_IDX( 25)] = 0x3D23,
7914         [BEND_IDX( 20)] = 0x3E23,
7915         [BEND_IDX( 15)] = 0x3E23,
7916         [BEND_IDX( 10)] = 0x3F23,
7917         [BEND_IDX(  5)] = 0x3F23,
7918         [BEND_IDX(  0)] = 0x0025,
7919         [BEND_IDX( -5)] = 0x0025,
7920         [BEND_IDX(-10)] = 0x0125,
7921         [BEND_IDX(-15)] = 0x0125,
7922         [BEND_IDX(-20)] = 0x0225,
7923         [BEND_IDX(-25)] = 0x0225,
7924         [BEND_IDX(-30)] = 0x0325,
7925         [BEND_IDX(-35)] = 0x0325,
7926         [BEND_IDX(-40)] = 0x0425,
7927         [BEND_IDX(-45)] = 0x0425,
7928         [BEND_IDX(-50)] = 0x0525,
7929 };
7930
7931 /*
7932  * Bend CLKOUT_DP
7933  * steps -50 to 50 inclusive, in steps of 5
7934  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7935  * change in clock period = -(steps / 10) * 5.787 ps
7936  */
7937 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7938 {
7939         uint32_t tmp;
7940         int idx = BEND_IDX(steps);
7941
7942         if (WARN_ON(steps % 5 != 0))
7943                 return;
7944
7945         if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7946                 return;
7947
7948         mutex_lock(&dev_priv->sb_lock);
7949
7950         if (steps % 10 != 0)
7951                 tmp = 0xAAAAAAAB;
7952         else
7953                 tmp = 0x00000000;
7954         intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7955
7956         tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7957         tmp &= 0xffff0000;
7958         tmp |= sscdivintphase[idx];
7959         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7960
7961         mutex_unlock(&dev_priv->sb_lock);
7962 }
7963
7964 #undef BEND_IDX
7965
7966 static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
7967 {
7968         struct intel_encoder *encoder;
7969         bool has_vga = false;
7970
7971         for_each_intel_encoder(&dev_priv->drm, encoder) {
7972                 switch (encoder->type) {
7973                 case INTEL_OUTPUT_ANALOG:
7974                         has_vga = true;
7975                         break;
7976                 default:
7977                         break;
7978                 }
7979         }
7980
7981         if (has_vga) {
7982                 lpt_bend_clkout_dp(dev_priv, 0);
7983                 lpt_enable_clkout_dp(dev_priv, true, true);
7984         } else {
7985                 lpt_disable_clkout_dp(dev_priv);
7986         }
7987 }
7988
7989 /*
7990  * Initialize reference clocks when the driver loads
7991  */
7992 void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
7993 {
7994         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
7995                 ironlake_init_pch_refclk(dev_priv);
7996         else if (HAS_PCH_LPT(dev_priv))
7997                 lpt_init_pch_refclk(dev_priv);
7998 }
7999
8000 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8001 {
8002         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8004         int pipe = intel_crtc->pipe;
8005         uint32_t val;
8006
8007         val = 0;
8008
8009         switch (intel_crtc->config->pipe_bpp) {
8010         case 18:
8011                 val |= PIPECONF_6BPC;
8012                 break;
8013         case 24:
8014                 val |= PIPECONF_8BPC;
8015                 break;
8016         case 30:
8017                 val |= PIPECONF_10BPC;
8018                 break;
8019         case 36:
8020                 val |= PIPECONF_12BPC;
8021                 break;
8022         default:
8023                 /* Case prevented by intel_choose_pipe_bpp_dither. */
8024                 BUG();
8025         }
8026
8027         if (intel_crtc->config->dither)
8028                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8029
8030         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8031                 val |= PIPECONF_INTERLACED_ILK;
8032         else
8033                 val |= PIPECONF_PROGRESSIVE;
8034
8035         if (intel_crtc->config->limited_color_range)
8036                 val |= PIPECONF_COLOR_RANGE_SELECT;
8037
8038         I915_WRITE(PIPECONF(pipe), val);
8039         POSTING_READ(PIPECONF(pipe));
8040 }
8041
8042 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8043 {
8044         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8045         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8046         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8047         u32 val = 0;
8048
8049         if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8050                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8051
8052         if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8053                 val |= PIPECONF_INTERLACED_ILK;
8054         else
8055                 val |= PIPECONF_PROGRESSIVE;
8056
8057         I915_WRITE(PIPECONF(cpu_transcoder), val);
8058         POSTING_READ(PIPECONF(cpu_transcoder));
8059 }
8060
8061 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8062 {
8063         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
8064         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8065
8066         if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8067                 u32 val = 0;
8068
8069                 switch (intel_crtc->config->pipe_bpp) {
8070                 case 18:
8071                         val |= PIPEMISC_DITHER_6_BPC;
8072                         break;
8073                 case 24:
8074                         val |= PIPEMISC_DITHER_8_BPC;
8075                         break;
8076                 case 30:
8077                         val |= PIPEMISC_DITHER_10_BPC;
8078                         break;
8079                 case 36:
8080                         val |= PIPEMISC_DITHER_12_BPC;
8081                         break;
8082                 default:
8083                         /* Case prevented by pipe_config_set_bpp. */
8084                         BUG();
8085                 }
8086
8087                 if (intel_crtc->config->dither)
8088                         val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8089
8090                 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8091         }
8092 }
8093
8094 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8095 {
8096         /*
8097          * Account for spread spectrum to avoid
8098          * oversubscribing the link. Max center spread
8099          * is 2.5%; use 5% for safety's sake.
8100          */
8101         u32 bps = target_clock * bpp * 21 / 20;
8102         return DIV_ROUND_UP(bps, link_bw * 8);
8103 }
8104
8105 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8106 {
8107         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8108 }
8109
8110 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8111                                   struct intel_crtc_state *crtc_state,
8112                                   struct dpll *reduced_clock)
8113 {
8114         struct drm_crtc *crtc = &intel_crtc->base;
8115         struct drm_device *dev = crtc->dev;
8116         struct drm_i915_private *dev_priv = to_i915(dev);
8117         u32 dpll, fp, fp2;
8118         int factor;
8119
8120         /* Enable autotuning of the PLL clock (if permissible) */
8121         factor = 21;
8122         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8123                 if ((intel_panel_use_ssc(dev_priv) &&
8124                      dev_priv->vbt.lvds_ssc_freq == 100000) ||
8125                     (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8126                         factor = 25;
8127         } else if (crtc_state->sdvo_tv_clock)
8128                 factor = 20;
8129
8130         fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8131
8132         if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8133                 fp |= FP_CB_TUNE;
8134
8135         if (reduced_clock) {
8136                 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8137
8138                 if (reduced_clock->m < factor * reduced_clock->n)
8139                         fp2 |= FP_CB_TUNE;
8140         } else {
8141                 fp2 = fp;
8142         }
8143
8144         dpll = 0;
8145
8146         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8147                 dpll |= DPLLB_MODE_LVDS;
8148         else
8149                 dpll |= DPLLB_MODE_DAC_SERIAL;
8150
8151         dpll |= (crtc_state->pixel_multiplier - 1)
8152                 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8153
8154         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8155             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8156                 dpll |= DPLL_SDVO_HIGH_SPEED;
8157
8158         if (intel_crtc_has_dp_encoder(crtc_state))
8159                 dpll |= DPLL_SDVO_HIGH_SPEED;
8160
8161         /*
8162          * The high speed IO clock is only really required for
8163          * SDVO/HDMI/DP, but we also enable it for CRT to make it
8164          * possible to share the DPLL between CRT and HDMI. Enabling
8165          * the clock needlessly does no real harm, except use up a
8166          * bit of power potentially.
8167          *
8168          * We'll limit this to IVB with 3 pipes, since it has only two
8169          * DPLLs and so DPLL sharing is the only way to get three pipes
8170          * driving PCH ports at the same time. On SNB we could do this,
8171          * and potentially avoid enabling the second DPLL, but it's not
8172          * clear if it''s a win or loss power wise. No point in doing
8173          * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8174          */
8175         if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8176             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8177                 dpll |= DPLL_SDVO_HIGH_SPEED;
8178
8179         /* compute bitmask from p1 value */
8180         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8181         /* also FPA1 */
8182         dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8183
8184         switch (crtc_state->dpll.p2) {
8185         case 5:
8186                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8187                 break;
8188         case 7:
8189                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8190                 break;
8191         case 10:
8192                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8193                 break;
8194         case 14:
8195                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8196                 break;
8197         }
8198
8199         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8200             intel_panel_use_ssc(dev_priv))
8201                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8202         else
8203                 dpll |= PLL_REF_INPUT_DREFCLK;
8204
8205         dpll |= DPLL_VCO_ENABLE;
8206
8207         crtc_state->dpll_hw_state.dpll = dpll;
8208         crtc_state->dpll_hw_state.fp0 = fp;
8209         crtc_state->dpll_hw_state.fp1 = fp2;
8210 }
8211
8212 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8213                                        struct intel_crtc_state *crtc_state)
8214 {
8215         struct drm_device *dev = crtc->base.dev;
8216         struct drm_i915_private *dev_priv = to_i915(dev);
8217         struct dpll reduced_clock;
8218         bool has_reduced_clock = false;
8219         struct intel_shared_dpll *pll;
8220         const struct intel_limit *limit;
8221         int refclk = 120000;
8222
8223         memset(&crtc_state->dpll_hw_state, 0,
8224                sizeof(crtc_state->dpll_hw_state));
8225
8226         crtc->lowfreq_avail = false;
8227
8228         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8229         if (!crtc_state->has_pch_encoder)
8230                 return 0;
8231
8232         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8233                 if (intel_panel_use_ssc(dev_priv)) {
8234                         DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8235                                       dev_priv->vbt.lvds_ssc_freq);
8236                         refclk = dev_priv->vbt.lvds_ssc_freq;
8237                 }
8238
8239                 if (intel_is_dual_link_lvds(dev)) {
8240                         if (refclk == 100000)
8241                                 limit = &intel_limits_ironlake_dual_lvds_100m;
8242                         else
8243                                 limit = &intel_limits_ironlake_dual_lvds;
8244                 } else {
8245                         if (refclk == 100000)
8246                                 limit = &intel_limits_ironlake_single_lvds_100m;
8247                         else
8248                                 limit = &intel_limits_ironlake_single_lvds;
8249                 }
8250         } else {
8251                 limit = &intel_limits_ironlake_dac;
8252         }
8253
8254         if (!crtc_state->clock_set &&
8255             !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8256                                 refclk, NULL, &crtc_state->dpll)) {
8257                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8258                 return -EINVAL;
8259         }
8260
8261         ironlake_compute_dpll(crtc, crtc_state,
8262                               has_reduced_clock ? &reduced_clock : NULL);
8263
8264         pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8265         if (pll == NULL) {
8266                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8267                                  pipe_name(crtc->pipe));
8268                 return -EINVAL;
8269         }
8270
8271         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8272             has_reduced_clock)
8273                 crtc->lowfreq_avail = true;
8274
8275         return 0;
8276 }
8277
8278 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8279                                          struct intel_link_m_n *m_n)
8280 {
8281         struct drm_device *dev = crtc->base.dev;
8282         struct drm_i915_private *dev_priv = to_i915(dev);
8283         enum pipe pipe = crtc->pipe;
8284
8285         m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8286         m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8287         m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8288                 & ~TU_SIZE_MASK;
8289         m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8290         m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8291                     & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8292 }
8293
8294 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8295                                          enum transcoder transcoder,
8296                                          struct intel_link_m_n *m_n,
8297                                          struct intel_link_m_n *m2_n2)
8298 {
8299         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8300         enum pipe pipe = crtc->pipe;
8301
8302         if (INTEL_GEN(dev_priv) >= 5) {
8303                 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8304                 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8305                 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8306                         & ~TU_SIZE_MASK;
8307                 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8308                 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8309                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8310                 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8311                  * gen < 8) and if DRRS is supported (to make sure the
8312                  * registers are not unnecessarily read).
8313                  */
8314                 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
8315                         crtc->config->has_drrs) {
8316                         m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8317                         m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8318                         m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8319                                         & ~TU_SIZE_MASK;
8320                         m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8321                         m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8322                                         & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8323                 }
8324         } else {
8325                 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8326                 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8327                 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8328                         & ~TU_SIZE_MASK;
8329                 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8330                 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8331                             & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8332         }
8333 }
8334
8335 void intel_dp_get_m_n(struct intel_crtc *crtc,
8336                       struct intel_crtc_state *pipe_config)
8337 {
8338         if (pipe_config->has_pch_encoder)
8339                 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8340         else
8341                 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8342                                              &pipe_config->dp_m_n,
8343                                              &pipe_config->dp_m2_n2);
8344 }
8345
8346 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8347                                         struct intel_crtc_state *pipe_config)
8348 {
8349         intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8350                                      &pipe_config->fdi_m_n, NULL);
8351 }
8352
8353 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8354                                     struct intel_crtc_state *pipe_config)
8355 {
8356         struct drm_device *dev = crtc->base.dev;
8357         struct drm_i915_private *dev_priv = to_i915(dev);
8358         struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8359         uint32_t ps_ctrl = 0;
8360         int id = -1;
8361         int i;
8362
8363         /* find scaler attached to this pipe */
8364         for (i = 0; i < crtc->num_scalers; i++) {
8365                 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8366                 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8367                         id = i;
8368                         pipe_config->pch_pfit.enabled = true;
8369                         pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8370                         pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8371                         break;
8372                 }
8373         }
8374
8375         scaler_state->scaler_id = id;
8376         if (id >= 0) {
8377                 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8378         } else {
8379                 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8380         }
8381 }
8382
8383 static void
8384 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8385                                  struct intel_initial_plane_config *plane_config)
8386 {
8387         struct drm_device *dev = crtc->base.dev;
8388         struct drm_i915_private *dev_priv = to_i915(dev);
8389         u32 val, base, offset, stride_mult, tiling;
8390         int pipe = crtc->pipe;
8391         int fourcc, pixel_format;
8392         unsigned int aligned_height;
8393         struct drm_framebuffer *fb;
8394         struct intel_framebuffer *intel_fb;
8395
8396         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8397         if (!intel_fb) {
8398                 DRM_DEBUG_KMS("failed to alloc fb\n");
8399                 return;
8400         }
8401
8402         fb = &intel_fb->base;
8403
8404         fb->dev = dev;
8405
8406         val = I915_READ(PLANE_CTL(pipe, 0));
8407         if (!(val & PLANE_CTL_ENABLE))
8408                 goto error;
8409
8410         pixel_format = val & PLANE_CTL_FORMAT_MASK;
8411         fourcc = skl_format_to_fourcc(pixel_format,
8412                                       val & PLANE_CTL_ORDER_RGBX,
8413                                       val & PLANE_CTL_ALPHA_MASK);
8414         fb->format = drm_format_info(fourcc);
8415
8416         tiling = val & PLANE_CTL_TILED_MASK;
8417         switch (tiling) {
8418         case PLANE_CTL_TILED_LINEAR:
8419                 fb->modifier = DRM_FORMAT_MOD_NONE;
8420                 break;
8421         case PLANE_CTL_TILED_X:
8422                 plane_config->tiling = I915_TILING_X;
8423                 fb->modifier = I915_FORMAT_MOD_X_TILED;
8424                 break;
8425         case PLANE_CTL_TILED_Y:
8426                 fb->modifier = I915_FORMAT_MOD_Y_TILED;
8427                 break;
8428         case PLANE_CTL_TILED_YF:
8429                 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
8430                 break;
8431         default:
8432                 MISSING_CASE(tiling);
8433                 goto error;
8434         }
8435
8436         base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8437         plane_config->base = base;
8438
8439         offset = I915_READ(PLANE_OFFSET(pipe, 0));
8440
8441         val = I915_READ(PLANE_SIZE(pipe, 0));
8442         fb->height = ((val >> 16) & 0xfff) + 1;
8443         fb->width = ((val >> 0) & 0x1fff) + 1;
8444
8445         val = I915_READ(PLANE_STRIDE(pipe, 0));
8446         stride_mult = intel_fb_stride_alignment(fb, 0);
8447         fb->pitches[0] = (val & 0x3ff) * stride_mult;
8448
8449         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8450
8451         plane_config->size = fb->pitches[0] * aligned_height;
8452
8453         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8454                       pipe_name(pipe), fb->width, fb->height,
8455                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8456                       plane_config->size);
8457
8458         plane_config->fb = intel_fb;
8459         return;
8460
8461 error:
8462         kfree(intel_fb);
8463 }
8464
8465 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8466                                      struct intel_crtc_state *pipe_config)
8467 {
8468         struct drm_device *dev = crtc->base.dev;
8469         struct drm_i915_private *dev_priv = to_i915(dev);
8470         uint32_t tmp;
8471
8472         tmp = I915_READ(PF_CTL(crtc->pipe));
8473
8474         if (tmp & PF_ENABLE) {
8475                 pipe_config->pch_pfit.enabled = true;
8476                 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8477                 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8478
8479                 /* We currently do not free assignements of panel fitters on
8480                  * ivb/hsw (since we don't use the higher upscaling modes which
8481                  * differentiates them) so just WARN about this case for now. */
8482                 if (IS_GEN7(dev_priv)) {
8483                         WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8484                                 PF_PIPE_SEL_IVB(crtc->pipe));
8485                 }
8486         }
8487 }
8488
8489 static void
8490 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8491                                   struct intel_initial_plane_config *plane_config)
8492 {
8493         struct drm_device *dev = crtc->base.dev;
8494         struct drm_i915_private *dev_priv = to_i915(dev);
8495         u32 val, base, offset;
8496         int pipe = crtc->pipe;
8497         int fourcc, pixel_format;
8498         unsigned int aligned_height;
8499         struct drm_framebuffer *fb;
8500         struct intel_framebuffer *intel_fb;
8501
8502         val = I915_READ(DSPCNTR(pipe));
8503         if (!(val & DISPLAY_PLANE_ENABLE))
8504                 return;
8505
8506         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8507         if (!intel_fb) {
8508                 DRM_DEBUG_KMS("failed to alloc fb\n");
8509                 return;
8510         }
8511
8512         fb = &intel_fb->base;
8513
8514         fb->dev = dev;
8515
8516         if (INTEL_GEN(dev_priv) >= 4) {
8517                 if (val & DISPPLANE_TILED) {
8518                         plane_config->tiling = I915_TILING_X;
8519                         fb->modifier = I915_FORMAT_MOD_X_TILED;
8520                 }
8521         }
8522
8523         pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8524         fourcc = i9xx_format_to_fourcc(pixel_format);
8525         fb->format = drm_format_info(fourcc);
8526
8527         base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8528         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
8529                 offset = I915_READ(DSPOFFSET(pipe));
8530         } else {
8531                 if (plane_config->tiling)
8532                         offset = I915_READ(DSPTILEOFF(pipe));
8533                 else
8534                         offset = I915_READ(DSPLINOFF(pipe));
8535         }
8536         plane_config->base = base;
8537
8538         val = I915_READ(PIPESRC(pipe));
8539         fb->width = ((val >> 16) & 0xfff) + 1;
8540         fb->height = ((val >> 0) & 0xfff) + 1;
8541
8542         val = I915_READ(DSPSTRIDE(pipe));
8543         fb->pitches[0] = val & 0xffffffc0;
8544
8545         aligned_height = intel_fb_align_height(fb, 0, fb->height);
8546
8547         plane_config->size = fb->pitches[0] * aligned_height;
8548
8549         DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8550                       pipe_name(pipe), fb->width, fb->height,
8551                       fb->format->cpp[0] * 8, base, fb->pitches[0],
8552                       plane_config->size);
8553
8554         plane_config->fb = intel_fb;
8555 }
8556
8557 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8558                                      struct intel_crtc_state *pipe_config)
8559 {
8560         struct drm_device *dev = crtc->base.dev;
8561         struct drm_i915_private *dev_priv = to_i915(dev);
8562         enum intel_display_power_domain power_domain;
8563         uint32_t tmp;
8564         bool ret;
8565
8566         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8567         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8568                 return false;
8569
8570         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8571         pipe_config->shared_dpll = NULL;
8572
8573         ret = false;
8574         tmp = I915_READ(PIPECONF(crtc->pipe));
8575         if (!(tmp & PIPECONF_ENABLE))
8576                 goto out;
8577
8578         switch (tmp & PIPECONF_BPC_MASK) {
8579         case PIPECONF_6BPC:
8580                 pipe_config->pipe_bpp = 18;
8581                 break;
8582         case PIPECONF_8BPC:
8583                 pipe_config->pipe_bpp = 24;
8584                 break;
8585         case PIPECONF_10BPC:
8586                 pipe_config->pipe_bpp = 30;
8587                 break;
8588         case PIPECONF_12BPC:
8589                 pipe_config->pipe_bpp = 36;
8590                 break;
8591         default:
8592                 break;
8593         }
8594
8595         if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8596                 pipe_config->limited_color_range = true;
8597
8598         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8599                 struct intel_shared_dpll *pll;
8600                 enum intel_dpll_id pll_id;
8601
8602                 pipe_config->has_pch_encoder = true;
8603
8604                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8605                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8606                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
8607
8608                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8609
8610                 if (HAS_PCH_IBX(dev_priv)) {
8611                         /*
8612                          * The pipe->pch transcoder and pch transcoder->pll
8613                          * mapping is fixed.
8614                          */
8615                         pll_id = (enum intel_dpll_id) crtc->pipe;
8616                 } else {
8617                         tmp = I915_READ(PCH_DPLL_SEL);
8618                         if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8619                                 pll_id = DPLL_ID_PCH_PLL_B;
8620                         else
8621                                 pll_id= DPLL_ID_PCH_PLL_A;
8622                 }
8623
8624                 pipe_config->shared_dpll =
8625                         intel_get_shared_dpll_by_id(dev_priv, pll_id);
8626                 pll = pipe_config->shared_dpll;
8627
8628                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8629                                                  &pipe_config->dpll_hw_state));
8630
8631                 tmp = pipe_config->dpll_hw_state.dpll;
8632                 pipe_config->pixel_multiplier =
8633                         ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8634                          >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8635
8636                 ironlake_pch_clock_get(crtc, pipe_config);
8637         } else {
8638                 pipe_config->pixel_multiplier = 1;
8639         }
8640
8641         intel_get_pipe_timings(crtc, pipe_config);
8642         intel_get_pipe_src_size(crtc, pipe_config);
8643
8644         ironlake_get_pfit_config(crtc, pipe_config);
8645
8646         ret = true;
8647
8648 out:
8649         intel_display_power_put(dev_priv, power_domain);
8650
8651         return ret;
8652 }
8653
8654 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8655 {
8656         struct drm_device *dev = &dev_priv->drm;
8657         struct intel_crtc *crtc;
8658
8659         for_each_intel_crtc(dev, crtc)
8660                 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8661                      pipe_name(crtc->pipe));
8662
8663         I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8664         I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8665         I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8666         I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8667         I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
8668         I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8669              "CPU PWM1 enabled\n");
8670         if (IS_HASWELL(dev_priv))
8671                 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8672                      "CPU PWM2 enabled\n");
8673         I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8674              "PCH PWM1 enabled\n");
8675         I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8676              "Utility pin enabled\n");
8677         I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8678
8679         /*
8680          * In theory we can still leave IRQs enabled, as long as only the HPD
8681          * interrupts remain enabled. We used to check for that, but since it's
8682          * gen-specific and since we only disable LCPLL after we fully disable
8683          * the interrupts, the check below should be enough.
8684          */
8685         I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8686 }
8687
8688 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8689 {
8690         if (IS_HASWELL(dev_priv))
8691                 return I915_READ(D_COMP_HSW);
8692         else
8693                 return I915_READ(D_COMP_BDW);
8694 }
8695
8696 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8697 {
8698         if (IS_HASWELL(dev_priv)) {
8699                 mutex_lock(&dev_priv->rps.hw_lock);
8700                 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8701                                             val))
8702                         DRM_DEBUG_KMS("Failed to write to D_COMP\n");
8703                 mutex_unlock(&dev_priv->rps.hw_lock);
8704         } else {
8705                 I915_WRITE(D_COMP_BDW, val);
8706                 POSTING_READ(D_COMP_BDW);
8707         }
8708 }
8709
8710 /*
8711  * This function implements pieces of two sequences from BSpec:
8712  * - Sequence for display software to disable LCPLL
8713  * - Sequence for display software to allow package C8+
8714  * The steps implemented here are just the steps that actually touch the LCPLL
8715  * register. Callers should take care of disabling all the display engine
8716  * functions, doing the mode unset, fixing interrupts, etc.
8717  */
8718 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8719                               bool switch_to_fclk, bool allow_power_down)
8720 {
8721         uint32_t val;
8722
8723         assert_can_disable_lcpll(dev_priv);
8724
8725         val = I915_READ(LCPLL_CTL);
8726
8727         if (switch_to_fclk) {
8728                 val |= LCPLL_CD_SOURCE_FCLK;
8729                 I915_WRITE(LCPLL_CTL, val);
8730
8731                 if (wait_for_us(I915_READ(LCPLL_CTL) &
8732                                 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8733                         DRM_ERROR("Switching to FCLK failed\n");
8734
8735                 val = I915_READ(LCPLL_CTL);
8736         }
8737
8738         val |= LCPLL_PLL_DISABLE;
8739         I915_WRITE(LCPLL_CTL, val);
8740         POSTING_READ(LCPLL_CTL);
8741
8742         if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
8743                 DRM_ERROR("LCPLL still locked\n");
8744
8745         val = hsw_read_dcomp(dev_priv);
8746         val |= D_COMP_COMP_DISABLE;
8747         hsw_write_dcomp(dev_priv, val);
8748         ndelay(100);
8749
8750         if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8751                      1))
8752                 DRM_ERROR("D_COMP RCOMP still in progress\n");
8753
8754         if (allow_power_down) {
8755                 val = I915_READ(LCPLL_CTL);
8756                 val |= LCPLL_POWER_DOWN_ALLOW;
8757                 I915_WRITE(LCPLL_CTL, val);
8758                 POSTING_READ(LCPLL_CTL);
8759         }
8760 }
8761
8762 /*
8763  * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8764  * source.
8765  */
8766 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8767 {
8768         uint32_t val;
8769
8770         val = I915_READ(LCPLL_CTL);
8771
8772         if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8773                     LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8774                 return;
8775
8776         /*
8777          * Make sure we're not on PC8 state before disabling PC8, otherwise
8778          * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8779          */
8780         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8781
8782         if (val & LCPLL_POWER_DOWN_ALLOW) {
8783                 val &= ~LCPLL_POWER_DOWN_ALLOW;
8784                 I915_WRITE(LCPLL_CTL, val);
8785                 POSTING_READ(LCPLL_CTL);
8786         }
8787
8788         val = hsw_read_dcomp(dev_priv);
8789         val |= D_COMP_COMP_FORCE;
8790         val &= ~D_COMP_COMP_DISABLE;
8791         hsw_write_dcomp(dev_priv, val);
8792
8793         val = I915_READ(LCPLL_CTL);
8794         val &= ~LCPLL_PLL_DISABLE;
8795         I915_WRITE(LCPLL_CTL, val);
8796
8797         if (intel_wait_for_register(dev_priv,
8798                                     LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8799                                     5))
8800                 DRM_ERROR("LCPLL not locked yet\n");
8801
8802         if (val & LCPLL_CD_SOURCE_FCLK) {
8803                 val = I915_READ(LCPLL_CTL);
8804                 val &= ~LCPLL_CD_SOURCE_FCLK;
8805                 I915_WRITE(LCPLL_CTL, val);
8806
8807                 if (wait_for_us((I915_READ(LCPLL_CTL) &
8808                                  LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8809                         DRM_ERROR("Switching back to LCPLL failed\n");
8810         }
8811
8812         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8813         intel_update_cdclk(dev_priv);
8814 }
8815
8816 /*
8817  * Package states C8 and deeper are really deep PC states that can only be
8818  * reached when all the devices on the system allow it, so even if the graphics
8819  * device allows PC8+, it doesn't mean the system will actually get to these
8820  * states. Our driver only allows PC8+ when going into runtime PM.
8821  *
8822  * The requirements for PC8+ are that all the outputs are disabled, the power
8823  * well is disabled and most interrupts are disabled, and these are also
8824  * requirements for runtime PM. When these conditions are met, we manually do
8825  * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8826  * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8827  * hang the machine.
8828  *
8829  * When we really reach PC8 or deeper states (not just when we allow it) we lose
8830  * the state of some registers, so when we come back from PC8+ we need to
8831  * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8832  * need to take care of the registers kept by RC6. Notice that this happens even
8833  * if we don't put the device in PCI D3 state (which is what currently happens
8834  * because of the runtime PM support).
8835  *
8836  * For more, read "Display Sequences for Package C8" on the hardware
8837  * documentation.
8838  */
8839 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8840 {
8841         uint32_t val;
8842
8843         DRM_DEBUG_KMS("Enabling package C8+\n");
8844
8845         if (HAS_PCH_LPT_LP(dev_priv)) {
8846                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8847                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8848                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8849         }
8850
8851         lpt_disable_clkout_dp(dev_priv);
8852         hsw_disable_lcpll(dev_priv, true, true);
8853 }
8854
8855 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8856 {
8857         uint32_t val;
8858
8859         DRM_DEBUG_KMS("Disabling package C8+\n");
8860
8861         hsw_restore_lcpll(dev_priv);
8862         lpt_init_pch_refclk(dev_priv);
8863
8864         if (HAS_PCH_LPT_LP(dev_priv)) {
8865                 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8866                 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8867                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8868         }
8869 }
8870
8871 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8872                                       struct intel_crtc_state *crtc_state)
8873 {
8874         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
8875                 if (!intel_ddi_pll_select(crtc, crtc_state))
8876                         return -EINVAL;
8877         }
8878
8879         crtc->lowfreq_avail = false;
8880
8881         return 0;
8882 }
8883
8884 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8885                                 enum port port,
8886                                 struct intel_crtc_state *pipe_config)
8887 {
8888         enum intel_dpll_id id;
8889
8890         switch (port) {
8891         case PORT_A:
8892                 id = DPLL_ID_SKL_DPLL0;
8893                 break;
8894         case PORT_B:
8895                 id = DPLL_ID_SKL_DPLL1;
8896                 break;
8897         case PORT_C:
8898                 id = DPLL_ID_SKL_DPLL2;
8899                 break;
8900         default:
8901                 DRM_ERROR("Incorrect port type\n");
8902                 return;
8903         }
8904
8905         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8906 }
8907
8908 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8909                                 enum port port,
8910                                 struct intel_crtc_state *pipe_config)
8911 {
8912         enum intel_dpll_id id;
8913         u32 temp;
8914
8915         temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8916         id = temp >> (port * 3 + 1);
8917
8918         if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8919                 return;
8920
8921         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8922 }
8923
8924 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8925                                 enum port port,
8926                                 struct intel_crtc_state *pipe_config)
8927 {
8928         enum intel_dpll_id id;
8929         uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8930
8931         switch (ddi_pll_sel) {
8932         case PORT_CLK_SEL_WRPLL1:
8933                 id = DPLL_ID_WRPLL1;
8934                 break;
8935         case PORT_CLK_SEL_WRPLL2:
8936                 id = DPLL_ID_WRPLL2;
8937                 break;
8938         case PORT_CLK_SEL_SPLL:
8939                 id = DPLL_ID_SPLL;
8940                 break;
8941         case PORT_CLK_SEL_LCPLL_810:
8942                 id = DPLL_ID_LCPLL_810;
8943                 break;
8944         case PORT_CLK_SEL_LCPLL_1350:
8945                 id = DPLL_ID_LCPLL_1350;
8946                 break;
8947         case PORT_CLK_SEL_LCPLL_2700:
8948                 id = DPLL_ID_LCPLL_2700;
8949                 break;
8950         default:
8951                 MISSING_CASE(ddi_pll_sel);
8952                 /* fall through */
8953         case PORT_CLK_SEL_NONE:
8954                 return;
8955         }
8956
8957         pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
8958 }
8959
8960 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8961                                      struct intel_crtc_state *pipe_config,
8962                                      u64 *power_domain_mask)
8963 {
8964         struct drm_device *dev = crtc->base.dev;
8965         struct drm_i915_private *dev_priv = to_i915(dev);
8966         enum intel_display_power_domain power_domain;
8967         u32 tmp;
8968
8969         /*
8970          * The pipe->transcoder mapping is fixed with the exception of the eDP
8971          * transcoder handled below.
8972          */
8973         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8974
8975         /*
8976          * XXX: Do intel_display_power_get_if_enabled before reading this (for
8977          * consistency and less surprising code; it's in always on power).
8978          */
8979         tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8980         if (tmp & TRANS_DDI_FUNC_ENABLE) {
8981                 enum pipe trans_edp_pipe;
8982                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8983                 default:
8984                         WARN(1, "unknown pipe linked to edp transcoder\n");
8985                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8986                 case TRANS_DDI_EDP_INPUT_A_ON:
8987                         trans_edp_pipe = PIPE_A;
8988                         break;
8989                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8990                         trans_edp_pipe = PIPE_B;
8991                         break;
8992                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8993                         trans_edp_pipe = PIPE_C;
8994                         break;
8995                 }
8996
8997                 if (trans_edp_pipe == crtc->pipe)
8998                         pipe_config->cpu_transcoder = TRANSCODER_EDP;
8999         }
9000
9001         power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9002         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9003                 return false;
9004         *power_domain_mask |= BIT_ULL(power_domain);
9005
9006         tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9007
9008         return tmp & PIPECONF_ENABLE;
9009 }
9010
9011 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9012                                          struct intel_crtc_state *pipe_config,
9013                                          u64 *power_domain_mask)
9014 {
9015         struct drm_device *dev = crtc->base.dev;
9016         struct drm_i915_private *dev_priv = to_i915(dev);
9017         enum intel_display_power_domain power_domain;
9018         enum port port;
9019         enum transcoder cpu_transcoder;
9020         u32 tmp;
9021
9022         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9023                 if (port == PORT_A)
9024                         cpu_transcoder = TRANSCODER_DSI_A;
9025                 else
9026                         cpu_transcoder = TRANSCODER_DSI_C;
9027
9028                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9029                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9030                         continue;
9031                 *power_domain_mask |= BIT_ULL(power_domain);
9032
9033                 /*
9034                  * The PLL needs to be enabled with a valid divider
9035                  * configuration, otherwise accessing DSI registers will hang
9036                  * the machine. See BSpec North Display Engine
9037                  * registers/MIPI[BXT]. We can break out here early, since we
9038                  * need the same DSI PLL to be enabled for both DSI ports.
9039                  */
9040                 if (!intel_dsi_pll_is_enabled(dev_priv))
9041                         break;
9042
9043                 /* XXX: this works for video mode only */
9044                 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9045                 if (!(tmp & DPI_ENABLE))
9046                         continue;
9047
9048                 tmp = I915_READ(MIPI_CTRL(port));
9049                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9050                         continue;
9051
9052                 pipe_config->cpu_transcoder = cpu_transcoder;
9053                 break;
9054         }
9055
9056         return transcoder_is_dsi(pipe_config->cpu_transcoder);
9057 }
9058
9059 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9060                                        struct intel_crtc_state *pipe_config)
9061 {
9062         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9063         struct intel_shared_dpll *pll;
9064         enum port port;
9065         uint32_t tmp;
9066
9067         tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9068
9069         port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9070
9071         if (IS_GEN9_BC(dev_priv))
9072                 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9073         else if (IS_GEN9_LP(dev_priv))
9074                 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9075         else
9076                 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9077
9078         pll = pipe_config->shared_dpll;
9079         if (pll) {
9080                 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9081                                                  &pipe_config->dpll_hw_state));
9082         }
9083
9084         /*
9085          * Haswell has only FDI/PCH transcoder A. It is which is connected to
9086          * DDI E. So just check whether this pipe is wired to DDI E and whether
9087          * the PCH transcoder is on.
9088          */
9089         if (INTEL_GEN(dev_priv) < 9 &&
9090             (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9091                 pipe_config->has_pch_encoder = true;
9092
9093                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9094                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9095                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
9096
9097                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9098         }
9099 }
9100
9101 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9102                                     struct intel_crtc_state *pipe_config)
9103 {
9104         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9105         enum intel_display_power_domain power_domain;
9106         u64 power_domain_mask;
9107         bool active;
9108
9109         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9110         if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9111                 return false;
9112         power_domain_mask = BIT_ULL(power_domain);
9113
9114         pipe_config->shared_dpll = NULL;
9115
9116         active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9117
9118         if (IS_GEN9_LP(dev_priv) &&
9119             bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9120                 WARN_ON(active);
9121                 active = true;
9122         }
9123
9124         if (!active)
9125                 goto out;
9126
9127         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9128                 haswell_get_ddi_port_state(crtc, pipe_config);
9129                 intel_get_pipe_timings(crtc, pipe_config);
9130         }
9131
9132         intel_get_pipe_src_size(crtc, pipe_config);
9133
9134         pipe_config->gamma_mode =
9135                 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9136
9137         if (INTEL_GEN(dev_priv) >= 9) {
9138                 intel_crtc_init_scalers(crtc, pipe_config);
9139
9140                 pipe_config->scaler_state.scaler_id = -1;
9141                 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9142         }
9143
9144         power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9145         if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9146                 power_domain_mask |= BIT_ULL(power_domain);
9147                 if (INTEL_GEN(dev_priv) >= 9)
9148                         skylake_get_pfit_config(crtc, pipe_config);
9149                 else
9150                         ironlake_get_pfit_config(crtc, pipe_config);
9151         }
9152
9153         if (IS_HASWELL(dev_priv))
9154                 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9155                         (I915_READ(IPS_CTL) & IPS_ENABLE);
9156
9157         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9158             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
9159                 pipe_config->pixel_multiplier =
9160                         I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9161         } else {
9162                 pipe_config->pixel_multiplier = 1;
9163         }
9164
9165 out:
9166         for_each_power_domain(power_domain, power_domain_mask)
9167                 intel_display_power_put(dev_priv, power_domain);
9168
9169         return active;
9170 }
9171
9172 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9173                            const struct intel_plane_state *plane_state)
9174 {
9175         unsigned int width = plane_state->base.crtc_w;
9176         unsigned int stride = roundup_pow_of_two(width) * 4;
9177
9178         switch (stride) {
9179         default:
9180                 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9181                           width, stride);
9182                 stride = 256;
9183                 /* fallthrough */
9184         case 256:
9185         case 512:
9186         case 1024:
9187         case 2048:
9188                 break;
9189         }
9190
9191         return CURSOR_ENABLE |
9192                 CURSOR_GAMMA_ENABLE |
9193                 CURSOR_FORMAT_ARGB |
9194                 CURSOR_STRIDE(stride);
9195 }
9196
9197 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9198                                const struct intel_plane_state *plane_state)
9199 {
9200         struct drm_device *dev = crtc->dev;
9201         struct drm_i915_private *dev_priv = to_i915(dev);
9202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9203         uint32_t cntl = 0, size = 0;
9204
9205         if (plane_state && plane_state->base.visible) {
9206                 unsigned int width = plane_state->base.crtc_w;
9207                 unsigned int height = plane_state->base.crtc_h;
9208
9209                 cntl = plane_state->ctl;
9210                 size = (height << 12) | width;
9211         }
9212
9213         if (intel_crtc->cursor_cntl != 0 &&
9214             (intel_crtc->cursor_base != base ||
9215              intel_crtc->cursor_size != size ||
9216              intel_crtc->cursor_cntl != cntl)) {
9217                 /* On these chipsets we can only modify the base/size/stride
9218                  * whilst the cursor is disabled.
9219                  */
9220                 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9221                 POSTING_READ_FW(CURCNTR(PIPE_A));
9222                 intel_crtc->cursor_cntl = 0;
9223         }
9224
9225         if (intel_crtc->cursor_base != base) {
9226                 I915_WRITE_FW(CURBASE(PIPE_A), base);
9227                 intel_crtc->cursor_base = base;
9228         }
9229
9230         if (intel_crtc->cursor_size != size) {
9231                 I915_WRITE_FW(CURSIZE, size);
9232                 intel_crtc->cursor_size = size;
9233         }
9234
9235         if (intel_crtc->cursor_cntl != cntl) {
9236                 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9237                 POSTING_READ_FW(CURCNTR(PIPE_A));
9238                 intel_crtc->cursor_cntl = cntl;
9239         }
9240 }
9241
9242 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9243                            const struct intel_plane_state *plane_state)
9244 {
9245         struct drm_i915_private *dev_priv =
9246                 to_i915(plane_state->base.plane->dev);
9247         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9248         enum pipe pipe = crtc->pipe;
9249         u32 cntl;
9250
9251         cntl = MCURSOR_GAMMA_ENABLE;
9252
9253         if (HAS_DDI(dev_priv))
9254                 cntl |= CURSOR_PIPE_CSC_ENABLE;
9255
9256         cntl |= pipe << 28; /* Connect to correct pipe */
9257
9258         switch (plane_state->base.crtc_w) {
9259         case 64:
9260                 cntl |= CURSOR_MODE_64_ARGB_AX;
9261                 break;
9262         case 128:
9263                 cntl |= CURSOR_MODE_128_ARGB_AX;
9264                 break;
9265         case 256:
9266                 cntl |= CURSOR_MODE_256_ARGB_AX;
9267                 break;
9268         default:
9269                 MISSING_CASE(plane_state->base.crtc_w);
9270                 return 0;
9271         }
9272
9273         if (plane_state->base.rotation & DRM_ROTATE_180)
9274                 cntl |= CURSOR_ROTATE_180;
9275
9276         return cntl;
9277 }
9278
9279 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
9280                                const struct intel_plane_state *plane_state)
9281 {
9282         struct drm_device *dev = crtc->dev;
9283         struct drm_i915_private *dev_priv = to_i915(dev);
9284         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9285         int pipe = intel_crtc->pipe;
9286         uint32_t cntl = 0;
9287
9288         if (plane_state && plane_state->base.visible)
9289                 cntl = plane_state->ctl;
9290
9291         if (intel_crtc->cursor_cntl != cntl) {
9292                 I915_WRITE_FW(CURCNTR(pipe), cntl);
9293                 POSTING_READ_FW(CURCNTR(pipe));
9294                 intel_crtc->cursor_cntl = cntl;
9295         }
9296
9297         /* and commit changes on next vblank */
9298         I915_WRITE_FW(CURBASE(pipe), base);
9299         POSTING_READ_FW(CURBASE(pipe));
9300
9301         intel_crtc->cursor_base = base;
9302 }
9303
9304 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9305 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9306                                      const struct intel_plane_state *plane_state)
9307 {
9308         struct drm_device *dev = crtc->dev;
9309         struct drm_i915_private *dev_priv = to_i915(dev);
9310         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9311         int pipe = intel_crtc->pipe;
9312         u32 base = intel_crtc->cursor_addr;
9313         unsigned long irqflags;
9314         u32 pos = 0;
9315
9316         if (plane_state) {
9317                 int x = plane_state->base.crtc_x;
9318                 int y = plane_state->base.crtc_y;
9319
9320                 if (x < 0) {
9321                         pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9322                         x = -x;
9323                 }
9324                 pos |= x << CURSOR_X_SHIFT;
9325
9326                 if (y < 0) {
9327                         pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9328                         y = -y;
9329                 }
9330                 pos |= y << CURSOR_Y_SHIFT;
9331
9332                 /* ILK+ do this automagically */
9333                 if (HAS_GMCH_DISPLAY(dev_priv) &&
9334                     plane_state->base.rotation & DRM_ROTATE_180) {
9335                         base += (plane_state->base.crtc_h *
9336                                  plane_state->base.crtc_w - 1) * 4;
9337                 }
9338         }
9339
9340         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9341
9342         I915_WRITE_FW(CURPOS(pipe), pos);
9343
9344         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
9345                 i845_update_cursor(crtc, base, plane_state);
9346         else
9347                 i9xx_update_cursor(crtc, base, plane_state);
9348
9349         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
9350 }
9351
9352 static bool cursor_size_ok(struct drm_i915_private *dev_priv,
9353                            uint32_t width, uint32_t height)
9354 {
9355         if (width == 0 || height == 0)
9356                 return false;
9357
9358         /*
9359          * 845g/865g are special in that they are only limited by
9360          * the width of their cursors, the height is arbitrary up to
9361          * the precision of the register. Everything else requires
9362          * square cursors, limited to a few power-of-two sizes.
9363          */
9364         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
9365                 if ((width & 63) != 0)
9366                         return false;
9367
9368                 if (width > (IS_I845G(dev_priv) ? 64 : 512))
9369                         return false;
9370
9371                 if (height > 1023)
9372                         return false;
9373         } else {
9374                 switch (width | height) {
9375                 case 256:
9376                 case 128:
9377                         if (IS_GEN2(dev_priv))
9378                                 return false;
9379                 case 64:
9380                         break;
9381                 default:
9382                         return false;
9383                 }
9384         }
9385
9386         return true;
9387 }
9388
9389 /* VESA 640x480x72Hz mode to set on the pipe */
9390 static struct drm_display_mode load_detect_mode = {
9391         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9392                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9393 };
9394
9395 struct drm_framebuffer *
9396 intel_framebuffer_create(struct drm_i915_gem_object *obj,
9397                          struct drm_mode_fb_cmd2 *mode_cmd)
9398 {
9399         struct intel_framebuffer *intel_fb;
9400         int ret;
9401
9402         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9403         if (!intel_fb)
9404                 return ERR_PTR(-ENOMEM);
9405
9406         ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
9407         if (ret)
9408                 goto err;
9409
9410         return &intel_fb->base;
9411
9412 err:
9413         kfree(intel_fb);
9414         return ERR_PTR(ret);
9415 }
9416
9417 static u32
9418 intel_framebuffer_pitch_for_width(int width, int bpp)
9419 {
9420         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9421         return ALIGN(pitch, 64);
9422 }
9423
9424 static u32
9425 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9426 {
9427         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9428         return PAGE_ALIGN(pitch * mode->vdisplay);
9429 }
9430
9431 static struct drm_framebuffer *
9432 intel_framebuffer_create_for_mode(struct drm_device *dev,
9433                                   struct drm_display_mode *mode,
9434                                   int depth, int bpp)
9435 {
9436         struct drm_framebuffer *fb;
9437         struct drm_i915_gem_object *obj;
9438         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9439
9440         obj = i915_gem_object_create(to_i915(dev),
9441                                     intel_framebuffer_size_for_mode(mode, bpp));
9442         if (IS_ERR(obj))
9443                 return ERR_CAST(obj);
9444
9445         mode_cmd.width = mode->hdisplay;
9446         mode_cmd.height = mode->vdisplay;
9447         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9448                                                                 bpp);
9449         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9450
9451         fb = intel_framebuffer_create(obj, &mode_cmd);
9452         if (IS_ERR(fb))
9453                 i915_gem_object_put(obj);
9454
9455         return fb;
9456 }
9457
9458 static struct drm_framebuffer *
9459 mode_fits_in_fbdev(struct drm_device *dev,
9460                    struct drm_display_mode *mode)
9461 {
9462 #ifdef CONFIG_DRM_FBDEV_EMULATION
9463         struct drm_i915_private *dev_priv = to_i915(dev);
9464         struct drm_i915_gem_object *obj;
9465         struct drm_framebuffer *fb;
9466
9467         if (!dev_priv->fbdev)
9468                 return NULL;
9469
9470         if (!dev_priv->fbdev->fb)
9471                 return NULL;
9472
9473         obj = dev_priv->fbdev->fb->obj;
9474         BUG_ON(!obj);
9475
9476         fb = &dev_priv->fbdev->fb->base;
9477         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9478                                                                fb->format->cpp[0] * 8))
9479                 return NULL;
9480
9481         if (obj->base.size < mode->vdisplay * fb->pitches[0])
9482                 return NULL;
9483
9484         drm_framebuffer_reference(fb);
9485         return fb;
9486 #else
9487         return NULL;
9488 #endif
9489 }
9490
9491 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9492                                            struct drm_crtc *crtc,
9493                                            struct drm_display_mode *mode,
9494                                            struct drm_framebuffer *fb,
9495                                            int x, int y)
9496 {
9497         struct drm_plane_state *plane_state;
9498         int hdisplay, vdisplay;
9499         int ret;
9500
9501         plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9502         if (IS_ERR(plane_state))
9503                 return PTR_ERR(plane_state);
9504
9505         if (mode)
9506                 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
9507         else
9508                 hdisplay = vdisplay = 0;
9509
9510         ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9511         if (ret)
9512                 return ret;
9513         drm_atomic_set_fb_for_plane(plane_state, fb);
9514         plane_state->crtc_x = 0;
9515         plane_state->crtc_y = 0;
9516         plane_state->crtc_w = hdisplay;
9517         plane_state->crtc_h = vdisplay;
9518         plane_state->src_x = x << 16;
9519         plane_state->src_y = y << 16;
9520         plane_state->src_w = hdisplay << 16;
9521         plane_state->src_h = vdisplay << 16;
9522
9523         return 0;
9524 }
9525
9526 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9527                                 struct drm_display_mode *mode,
9528                                 struct intel_load_detect_pipe *old,
9529                                 struct drm_modeset_acquire_ctx *ctx)
9530 {
9531         struct intel_crtc *intel_crtc;
9532         struct intel_encoder *intel_encoder =
9533                 intel_attached_encoder(connector);
9534         struct drm_crtc *possible_crtc;
9535         struct drm_encoder *encoder = &intel_encoder->base;
9536         struct drm_crtc *crtc = NULL;
9537         struct drm_device *dev = encoder->dev;
9538         struct drm_i915_private *dev_priv = to_i915(dev);
9539         struct drm_framebuffer *fb;
9540         struct drm_mode_config *config = &dev->mode_config;
9541         struct drm_atomic_state *state = NULL, *restore_state = NULL;
9542         struct drm_connector_state *connector_state;
9543         struct intel_crtc_state *crtc_state;
9544         int ret, i = -1;
9545
9546         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9547                       connector->base.id, connector->name,
9548                       encoder->base.id, encoder->name);
9549
9550         old->restore_state = NULL;
9551
9552 retry:
9553         ret = drm_modeset_lock(&config->connection_mutex, ctx);
9554         if (ret)
9555                 goto fail;
9556
9557         /*
9558          * Algorithm gets a little messy:
9559          *
9560          *   - if the connector already has an assigned crtc, use it (but make
9561          *     sure it's on first)
9562          *
9563          *   - try to find the first unused crtc that can drive this connector,
9564          *     and use that if we find one
9565          */
9566
9567         /* See if we already have a CRTC for this connector */
9568         if (connector->state->crtc) {
9569                 crtc = connector->state->crtc;
9570
9571                 ret = drm_modeset_lock(&crtc->mutex, ctx);
9572                 if (ret)
9573                         goto fail;
9574
9575                 /* Make sure the crtc and connector are running */
9576                 goto found;
9577         }
9578
9579         /* Find an unused one (if possible) */
9580         for_each_crtc(dev, possible_crtc) {
9581                 i++;
9582                 if (!(encoder->possible_crtcs & (1 << i)))
9583                         continue;
9584
9585                 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9586                 if (ret)
9587                         goto fail;
9588
9589                 if (possible_crtc->state->enable) {
9590                         drm_modeset_unlock(&possible_crtc->mutex);
9591                         continue;
9592                 }
9593
9594                 crtc = possible_crtc;
9595                 break;
9596         }
9597
9598         /*
9599          * If we didn't find an unused CRTC, don't use any.
9600          */
9601         if (!crtc) {
9602                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9603                 goto fail;
9604         }
9605
9606 found:
9607         intel_crtc = to_intel_crtc(crtc);
9608
9609         ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9610         if (ret)
9611                 goto fail;
9612
9613         state = drm_atomic_state_alloc(dev);
9614         restore_state = drm_atomic_state_alloc(dev);
9615         if (!state || !restore_state) {
9616                 ret = -ENOMEM;
9617                 goto fail;
9618         }
9619
9620         state->acquire_ctx = ctx;
9621         restore_state->acquire_ctx = ctx;
9622
9623         connector_state = drm_atomic_get_connector_state(state, connector);
9624         if (IS_ERR(connector_state)) {
9625                 ret = PTR_ERR(connector_state);
9626                 goto fail;
9627         }
9628
9629         ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9630         if (ret)
9631                 goto fail;
9632
9633         crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9634         if (IS_ERR(crtc_state)) {
9635                 ret = PTR_ERR(crtc_state);
9636                 goto fail;
9637         }
9638
9639         crtc_state->base.active = crtc_state->base.enable = true;
9640
9641         if (!mode)
9642                 mode = &load_detect_mode;
9643
9644         /* We need a framebuffer large enough to accommodate all accesses
9645          * that the plane may generate whilst we perform load detection.
9646          * We can not rely on the fbcon either being present (we get called
9647          * during its initialisation to detect all boot displays, or it may
9648          * not even exist) or that it is large enough to satisfy the
9649          * requested mode.
9650          */
9651         fb = mode_fits_in_fbdev(dev, mode);
9652         if (fb == NULL) {
9653                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9654                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9655         } else
9656                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9657         if (IS_ERR(fb)) {
9658                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9659                 goto fail;
9660         }
9661
9662         ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9663         if (ret)
9664                 goto fail;
9665
9666         drm_framebuffer_unreference(fb);
9667
9668         ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9669         if (ret)
9670                 goto fail;
9671
9672         ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9673         if (!ret)
9674                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9675         if (!ret)
9676                 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9677         if (ret) {
9678                 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9679                 goto fail;
9680         }
9681
9682         ret = drm_atomic_commit(state);
9683         if (ret) {
9684                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9685                 goto fail;
9686         }
9687
9688         old->restore_state = restore_state;
9689         drm_atomic_state_put(state);
9690
9691         /* let the connector get through one full cycle before testing */
9692         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
9693         return true;
9694
9695 fail:
9696         if (state) {
9697                 drm_atomic_state_put(state);
9698                 state = NULL;
9699         }
9700         if (restore_state) {
9701                 drm_atomic_state_put(restore_state);
9702                 restore_state = NULL;
9703         }
9704
9705         if (ret == -EDEADLK) {
9706                 drm_modeset_backoff(ctx);
9707                 goto retry;
9708         }
9709
9710         return false;
9711 }
9712
9713 void intel_release_load_detect_pipe(struct drm_connector *connector,
9714                                     struct intel_load_detect_pipe *old,
9715                                     struct drm_modeset_acquire_ctx *ctx)
9716 {
9717         struct intel_encoder *intel_encoder =
9718                 intel_attached_encoder(connector);
9719         struct drm_encoder *encoder = &intel_encoder->base;
9720         struct drm_atomic_state *state = old->restore_state;
9721         int ret;
9722
9723         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9724                       connector->base.id, connector->name,
9725                       encoder->base.id, encoder->name);
9726
9727         if (!state)
9728                 return;
9729
9730         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
9731         if (ret)
9732                 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
9733         drm_atomic_state_put(state);
9734 }
9735
9736 static int i9xx_pll_refclk(struct drm_device *dev,
9737                            const struct intel_crtc_state *pipe_config)
9738 {
9739         struct drm_i915_private *dev_priv = to_i915(dev);
9740         u32 dpll = pipe_config->dpll_hw_state.dpll;
9741
9742         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9743                 return dev_priv->vbt.lvds_ssc_freq;
9744         else if (HAS_PCH_SPLIT(dev_priv))
9745                 return 120000;
9746         else if (!IS_GEN2(dev_priv))
9747                 return 96000;
9748         else
9749                 return 48000;
9750 }
9751
9752 /* Returns the clock of the currently programmed mode of the given pipe. */
9753 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9754                                 struct intel_crtc_state *pipe_config)
9755 {
9756         struct drm_device *dev = crtc->base.dev;
9757         struct drm_i915_private *dev_priv = to_i915(dev);
9758         int pipe = pipe_config->cpu_transcoder;
9759         u32 dpll = pipe_config->dpll_hw_state.dpll;
9760         u32 fp;
9761         struct dpll clock;
9762         int port_clock;
9763         int refclk = i9xx_pll_refclk(dev, pipe_config);
9764
9765         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9766                 fp = pipe_config->dpll_hw_state.fp0;
9767         else
9768                 fp = pipe_config->dpll_hw_state.fp1;
9769
9770         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9771         if (IS_PINEVIEW(dev_priv)) {
9772                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9773                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9774         } else {
9775                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9776                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9777         }
9778
9779         if (!IS_GEN2(dev_priv)) {
9780                 if (IS_PINEVIEW(dev_priv))
9781                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9782                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9783                 else
9784                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9785                                DPLL_FPA01_P1_POST_DIV_SHIFT);
9786
9787                 switch (dpll & DPLL_MODE_MASK) {
9788                 case DPLLB_MODE_DAC_SERIAL:
9789                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9790                                 5 : 10;
9791                         break;
9792                 case DPLLB_MODE_LVDS:
9793                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9794                                 7 : 14;
9795                         break;
9796                 default:
9797                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9798                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
9799                         return;
9800                 }
9801
9802                 if (IS_PINEVIEW(dev_priv))
9803                         port_clock = pnv_calc_dpll_params(refclk, &clock);
9804                 else
9805                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
9806         } else {
9807                 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
9808                 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9809
9810                 if (is_lvds) {
9811                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9812                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
9813
9814                         if (lvds & LVDS_CLKB_POWER_UP)
9815                                 clock.p2 = 7;
9816                         else
9817                                 clock.p2 = 14;
9818                 } else {
9819                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
9820                                 clock.p1 = 2;
9821                         else {
9822                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9823                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9824                         }
9825                         if (dpll & PLL_P2_DIVIDE_BY_4)
9826                                 clock.p2 = 4;
9827                         else
9828                                 clock.p2 = 2;
9829                 }
9830
9831                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
9832         }
9833
9834         /*
9835          * This value includes pixel_multiplier. We will use
9836          * port_clock to compute adjusted_mode.crtc_clock in the
9837          * encoder's get_config() function.
9838          */
9839         pipe_config->port_clock = port_clock;
9840 }
9841
9842 int intel_dotclock_calculate(int link_freq,
9843                              const struct intel_link_m_n *m_n)
9844 {
9845         /*
9846          * The calculation for the data clock is:
9847          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9848          * But we want to avoid losing precison if possible, so:
9849          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9850          *
9851          * and the link clock is simpler:
9852          * link_clock = (m * link_clock) / n
9853          */
9854
9855         if (!m_n->link_n)
9856                 return 0;
9857
9858         return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9859 }
9860
9861 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9862                                    struct intel_crtc_state *pipe_config)
9863 {
9864         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
9865
9866         /* read out port_clock from the DPLL */
9867         i9xx_crtc_clock_get(crtc, pipe_config);
9868
9869         /*
9870          * In case there is an active pipe without active ports,
9871          * we may need some idea for the dotclock anyway.
9872          * Calculate one based on the FDI configuration.
9873          */
9874         pipe_config->base.adjusted_mode.crtc_clock =
9875                 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
9876                                          &pipe_config->fdi_m_n);
9877 }
9878
9879 /** Returns the currently programmed mode of the given pipe. */
9880 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9881                                              struct drm_crtc *crtc)
9882 {
9883         struct drm_i915_private *dev_priv = to_i915(dev);
9884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9885         enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9886         struct drm_display_mode *mode;
9887         struct intel_crtc_state *pipe_config;
9888         int htot = I915_READ(HTOTAL(cpu_transcoder));
9889         int hsync = I915_READ(HSYNC(cpu_transcoder));
9890         int vtot = I915_READ(VTOTAL(cpu_transcoder));
9891         int vsync = I915_READ(VSYNC(cpu_transcoder));
9892         enum pipe pipe = intel_crtc->pipe;
9893
9894         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9895         if (!mode)
9896                 return NULL;
9897
9898         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9899         if (!pipe_config) {
9900                 kfree(mode);
9901                 return NULL;
9902         }
9903
9904         /*
9905          * Construct a pipe_config sufficient for getting the clock info
9906          * back out of crtc_clock_get.
9907          *
9908          * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9909          * to use a real value here instead.
9910          */
9911         pipe_config->cpu_transcoder = (enum transcoder) pipe;
9912         pipe_config->pixel_multiplier = 1;
9913         pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9914         pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9915         pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9916         i9xx_crtc_clock_get(intel_crtc, pipe_config);
9917
9918         mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
9919         mode->hdisplay = (htot & 0xffff) + 1;
9920         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9921         mode->hsync_start = (hsync & 0xffff) + 1;
9922         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9923         mode->vdisplay = (vtot & 0xffff) + 1;
9924         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9925         mode->vsync_start = (vsync & 0xffff) + 1;
9926         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9927
9928         drm_mode_set_name(mode);
9929
9930         kfree(pipe_config);
9931
9932         return mode;
9933 }
9934
9935 static void intel_crtc_destroy(struct drm_crtc *crtc)
9936 {
9937         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9938         struct drm_device *dev = crtc->dev;
9939         struct intel_flip_work *work;
9940
9941         spin_lock_irq(&dev->event_lock);
9942         work = intel_crtc->flip_work;
9943         intel_crtc->flip_work = NULL;
9944         spin_unlock_irq(&dev->event_lock);
9945
9946         if (work) {
9947                 cancel_work_sync(&work->mmio_work);
9948                 cancel_work_sync(&work->unpin_work);
9949                 kfree(work);
9950         }
9951
9952         drm_crtc_cleanup(crtc);
9953
9954         kfree(intel_crtc);
9955 }
9956
9957 static void intel_unpin_work_fn(struct work_struct *__work)
9958 {
9959         struct intel_flip_work *work =
9960                 container_of(__work, struct intel_flip_work, unpin_work);
9961         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
9962         struct drm_device *dev = crtc->base.dev;
9963         struct drm_plane *primary = crtc->base.primary;
9964
9965         if (is_mmio_work(work))
9966                 flush_work(&work->mmio_work);
9967
9968         mutex_lock(&dev->struct_mutex);
9969         intel_unpin_fb_vma(work->old_vma);
9970         i915_gem_object_put(work->pending_flip_obj);
9971         mutex_unlock(&dev->struct_mutex);
9972
9973         i915_gem_request_put(work->flip_queued_req);
9974
9975         intel_frontbuffer_flip_complete(to_i915(dev),
9976                                         to_intel_plane(primary)->frontbuffer_bit);
9977         intel_fbc_post_update(crtc);
9978         drm_framebuffer_unreference(work->old_fb);
9979
9980         BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
9981         atomic_dec(&crtc->unpin_work_count);
9982
9983         kfree(work);
9984 }
9985
9986 /* Is 'a' after or equal to 'b'? */
9987 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9988 {
9989         return !((a - b) & 0x80000000);
9990 }
9991
9992 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
9993                                    struct intel_flip_work *work)
9994 {
9995         struct drm_device *dev = crtc->base.dev;
9996         struct drm_i915_private *dev_priv = to_i915(dev);
9997
9998         if (abort_flip_on_reset(crtc))
9999                 return true;
10000
10001         /*
10002          * The relevant registers doen't exist on pre-ctg.
10003          * As the flip done interrupt doesn't trigger for mmio
10004          * flips on gmch platforms, a flip count check isn't
10005          * really needed there. But since ctg has the registers,
10006          * include it in the check anyway.
10007          */
10008         if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
10009                 return true;
10010
10011         /*
10012          * BDW signals flip done immediately if the plane
10013          * is disabled, even if the plane enable is already
10014          * armed to occur at the next vblank :(
10015          */
10016
10017         /*
10018          * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10019          * used the same base address. In that case the mmio flip might
10020          * have completed, but the CS hasn't even executed the flip yet.
10021          *
10022          * A flip count check isn't enough as the CS might have updated
10023          * the base address just after start of vblank, but before we
10024          * managed to process the interrupt. This means we'd complete the
10025          * CS flip too soon.
10026          *
10027          * Combining both checks should get us a good enough result. It may
10028          * still happen that the CS flip has been executed, but has not
10029          * yet actually completed. But in case the base address is the same
10030          * anyway, we don't really care.
10031          */
10032         return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10033                 crtc->flip_work->gtt_offset &&
10034                 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10035                                     crtc->flip_work->flip_count);
10036 }
10037
10038 static bool
10039 __pageflip_finished_mmio(struct intel_crtc *crtc,
10040                                struct intel_flip_work *work)
10041 {
10042         /*
10043          * MMIO work completes when vblank is different from
10044          * flip_queued_vblank.
10045          *
10046          * Reset counter value doesn't matter, this is handled by
10047          * i915_wait_request finishing early, so no need to handle
10048          * reset here.
10049          */
10050         return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
10051 }
10052
10053
10054 static bool pageflip_finished(struct intel_crtc *crtc,
10055                               struct intel_flip_work *work)
10056 {
10057         if (!atomic_read(&work->pending))
10058                 return false;
10059
10060         smp_rmb();
10061
10062         if (is_mmio_work(work))
10063                 return __pageflip_finished_mmio(crtc, work);
10064         else
10065                 return __pageflip_finished_cs(crtc, work);
10066 }
10067
10068 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10069 {
10070         struct drm_device *dev = &dev_priv->drm;
10071         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10072         struct intel_flip_work *work;
10073         unsigned long flags;
10074
10075         /* Ignore early vblank irqs */
10076         if (!crtc)
10077                 return;
10078
10079         /*
10080          * This is called both by irq handlers and the reset code (to complete
10081          * lost pageflips) so needs the full irqsave spinlocks.
10082          */
10083         spin_lock_irqsave(&dev->event_lock, flags);
10084         work = crtc->flip_work;
10085
10086         if (work != NULL &&
10087             !is_mmio_work(work) &&
10088             pageflip_finished(crtc, work))
10089                 page_flip_completed(crtc);
10090
10091         spin_unlock_irqrestore(&dev->event_lock, flags);
10092 }
10093
10094 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
10095 {
10096         struct drm_device *dev = &dev_priv->drm;
10097         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10098         struct intel_flip_work *work;
10099         unsigned long flags;
10100
10101         /* Ignore early vblank irqs */
10102         if (!crtc)
10103                 return;
10104
10105         /*
10106          * This is called both by irq handlers and the reset code (to complete
10107          * lost pageflips) so needs the full irqsave spinlocks.
10108          */
10109         spin_lock_irqsave(&dev->event_lock, flags);
10110         work = crtc->flip_work;
10111
10112         if (work != NULL &&
10113             is_mmio_work(work) &&
10114             pageflip_finished(crtc, work))
10115                 page_flip_completed(crtc);
10116
10117         spin_unlock_irqrestore(&dev->event_lock, flags);
10118 }
10119
10120 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10121                                                struct intel_flip_work *work)
10122 {
10123         work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
10124
10125         /* Ensure that the work item is consistent when activating it ... */
10126         smp_mb__before_atomic();
10127         atomic_set(&work->pending, 1);
10128 }
10129
10130 static int intel_gen2_queue_flip(struct drm_device *dev,
10131                                  struct drm_crtc *crtc,
10132                                  struct drm_framebuffer *fb,
10133                                  struct drm_i915_gem_object *obj,
10134                                  struct drm_i915_gem_request *req,
10135                                  uint32_t flags)
10136 {
10137         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10138         u32 flip_mask, *cs;
10139
10140         cs = intel_ring_begin(req, 6);
10141         if (IS_ERR(cs))
10142                 return PTR_ERR(cs);
10143
10144         /* Can't queue multiple flips, so wait for the previous
10145          * one to finish before executing the next.
10146          */
10147         if (intel_crtc->plane)
10148                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10149         else
10150                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10151         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10152         *cs++ = MI_NOOP;
10153         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10154         *cs++ = fb->pitches[0];
10155         *cs++ = intel_crtc->flip_work->gtt_offset;
10156         *cs++ = 0; /* aux display base address, unused */
10157
10158         return 0;
10159 }
10160
10161 static int intel_gen3_queue_flip(struct drm_device *dev,
10162                                  struct drm_crtc *crtc,
10163                                  struct drm_framebuffer *fb,
10164                                  struct drm_i915_gem_object *obj,
10165                                  struct drm_i915_gem_request *req,
10166                                  uint32_t flags)
10167 {
10168         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10169         u32 flip_mask, *cs;
10170
10171         cs = intel_ring_begin(req, 6);
10172         if (IS_ERR(cs))
10173                 return PTR_ERR(cs);
10174
10175         if (intel_crtc->plane)
10176                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10177         else
10178                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10179         *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10180         *cs++ = MI_NOOP;
10181         *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10182         *cs++ = fb->pitches[0];
10183         *cs++ = intel_crtc->flip_work->gtt_offset;
10184         *cs++ = MI_NOOP;
10185
10186         return 0;
10187 }
10188
10189 static int intel_gen4_queue_flip(struct drm_device *dev,
10190                                  struct drm_crtc *crtc,
10191                                  struct drm_framebuffer *fb,
10192                                  struct drm_i915_gem_object *obj,
10193                                  struct drm_i915_gem_request *req,
10194                                  uint32_t flags)
10195 {
10196         struct drm_i915_private *dev_priv = to_i915(dev);
10197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10198         u32 pf, pipesrc, *cs;
10199
10200         cs = intel_ring_begin(req, 4);
10201         if (IS_ERR(cs))
10202                 return PTR_ERR(cs);
10203
10204         /* i965+ uses the linear or tiled offsets from the
10205          * Display Registers (which do not change across a page-flip)
10206          * so we need only reprogram the base address.
10207          */
10208         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10209         *cs++ = fb->pitches[0];
10210         *cs++ = intel_crtc->flip_work->gtt_offset |
10211                 intel_fb_modifier_to_tiling(fb->modifier);
10212
10213         /* XXX Enabling the panel-fitter across page-flip is so far
10214          * untested on non-native modes, so ignore it for now.
10215          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10216          */
10217         pf = 0;
10218         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10219         *cs++ = pf | pipesrc;
10220
10221         return 0;
10222 }
10223
10224 static int intel_gen6_queue_flip(struct drm_device *dev,
10225                                  struct drm_crtc *crtc,
10226                                  struct drm_framebuffer *fb,
10227                                  struct drm_i915_gem_object *obj,
10228                                  struct drm_i915_gem_request *req,
10229                                  uint32_t flags)
10230 {
10231         struct drm_i915_private *dev_priv = to_i915(dev);
10232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10233         u32 pf, pipesrc, *cs;
10234
10235         cs = intel_ring_begin(req, 4);
10236         if (IS_ERR(cs))
10237                 return PTR_ERR(cs);
10238
10239         *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10240         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10241         *cs++ = intel_crtc->flip_work->gtt_offset;
10242
10243         /* Contrary to the suggestions in the documentation,
10244          * "Enable Panel Fitter" does not seem to be required when page
10245          * flipping with a non-native mode, and worse causes a normal
10246          * modeset to fail.
10247          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10248          */
10249         pf = 0;
10250         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10251         *cs++ = pf | pipesrc;
10252
10253         return 0;
10254 }
10255
10256 static int intel_gen7_queue_flip(struct drm_device *dev,
10257                                  struct drm_crtc *crtc,
10258                                  struct drm_framebuffer *fb,
10259                                  struct drm_i915_gem_object *obj,
10260                                  struct drm_i915_gem_request *req,
10261                                  uint32_t flags)
10262 {
10263         struct drm_i915_private *dev_priv = to_i915(dev);
10264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10265         u32 *cs, plane_bit = 0;
10266         int len, ret;
10267
10268         switch (intel_crtc->plane) {
10269         case PLANE_A:
10270                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10271                 break;
10272         case PLANE_B:
10273                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10274                 break;
10275         case PLANE_C:
10276                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10277                 break;
10278         default:
10279                 WARN_ONCE(1, "unknown plane in flip command\n");
10280                 return -ENODEV;
10281         }
10282
10283         len = 4;
10284         if (req->engine->id == RCS) {
10285                 len += 6;
10286                 /*
10287                  * On Gen 8, SRM is now taking an extra dword to accommodate
10288                  * 48bits addresses, and we need a NOOP for the batch size to
10289                  * stay even.
10290                  */
10291                 if (IS_GEN8(dev_priv))
10292                         len += 2;
10293         }
10294
10295         /*
10296          * BSpec MI_DISPLAY_FLIP for IVB:
10297          * "The full packet must be contained within the same cache line."
10298          *
10299          * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10300          * cacheline, if we ever start emitting more commands before
10301          * the MI_DISPLAY_FLIP we may need to first emit everything else,
10302          * then do the cacheline alignment, and finally emit the
10303          * MI_DISPLAY_FLIP.
10304          */
10305         ret = intel_ring_cacheline_align(req);
10306         if (ret)
10307                 return ret;
10308
10309         cs = intel_ring_begin(req, len);
10310         if (IS_ERR(cs))
10311                 return PTR_ERR(cs);
10312
10313         /* Unmask the flip-done completion message. Note that the bspec says that
10314          * we should do this for both the BCS and RCS, and that we must not unmask
10315          * more than one flip event at any time (or ensure that one flip message
10316          * can be sent by waiting for flip-done prior to queueing new flips).
10317          * Experimentation says that BCS works despite DERRMR masking all
10318          * flip-done completion events and that unmasking all planes at once
10319          * for the RCS also doesn't appear to drop events. Setting the DERRMR
10320          * to zero does lead to lockups within MI_DISPLAY_FLIP.
10321          */
10322         if (req->engine->id == RCS) {
10323                 *cs++ = MI_LOAD_REGISTER_IMM(1);
10324                 *cs++ = i915_mmio_reg_offset(DERRMR);
10325                 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10326                           DERRMR_PIPEB_PRI_FLIP_DONE |
10327                           DERRMR_PIPEC_PRI_FLIP_DONE);
10328                 if (IS_GEN8(dev_priv))
10329                         *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10330                                 MI_SRM_LRM_GLOBAL_GTT;
10331                 else
10332                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10333                 *cs++ = i915_mmio_reg_offset(DERRMR);
10334                 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
10335                 if (IS_GEN8(dev_priv)) {
10336                         *cs++ = 0;
10337                         *cs++ = MI_NOOP;
10338                 }
10339         }
10340
10341         *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10342         *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10343         *cs++ = intel_crtc->flip_work->gtt_offset;
10344         *cs++ = MI_NOOP;
10345
10346         return 0;
10347 }
10348
10349 static bool use_mmio_flip(struct intel_engine_cs *engine,
10350                           struct drm_i915_gem_object *obj)
10351 {
10352         /*
10353          * This is not being used for older platforms, because
10354          * non-availability of flip done interrupt forces us to use
10355          * CS flips. Older platforms derive flip done using some clever
10356          * tricks involving the flip_pending status bits and vblank irqs.
10357          * So using MMIO flips there would disrupt this mechanism.
10358          */
10359
10360         if (engine == NULL)
10361                 return true;
10362
10363         if (INTEL_GEN(engine->i915) < 5)
10364                 return false;
10365
10366         if (i915.use_mmio_flip < 0)
10367                 return false;
10368         else if (i915.use_mmio_flip > 0)
10369                 return true;
10370         else if (i915.enable_execlists)
10371                 return true;
10372
10373         return engine != i915_gem_object_last_write_engine(obj);
10374 }
10375
10376 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10377                              unsigned int rotation,
10378                              struct intel_flip_work *work)
10379 {
10380         struct drm_device *dev = intel_crtc->base.dev;
10381         struct drm_i915_private *dev_priv = to_i915(dev);
10382         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10383         const enum pipe pipe = intel_crtc->pipe;
10384         u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
10385
10386         ctl = I915_READ(PLANE_CTL(pipe, 0));
10387         ctl &= ~PLANE_CTL_TILED_MASK;
10388         switch (fb->modifier) {
10389         case DRM_FORMAT_MOD_NONE:
10390                 break;
10391         case I915_FORMAT_MOD_X_TILED:
10392                 ctl |= PLANE_CTL_TILED_X;
10393                 break;
10394         case I915_FORMAT_MOD_Y_TILED:
10395                 ctl |= PLANE_CTL_TILED_Y;
10396                 break;
10397         case I915_FORMAT_MOD_Yf_TILED:
10398                 ctl |= PLANE_CTL_TILED_YF;
10399                 break;
10400         default:
10401                 MISSING_CASE(fb->modifier);
10402         }
10403
10404         /*
10405          * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10406          * PLANE_SURF updates, the update is then guaranteed to be atomic.
10407          */
10408         I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10409         I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10410
10411         I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10412         POSTING_READ(PLANE_SURF(pipe, 0));
10413 }
10414
10415 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10416                              struct intel_flip_work *work)
10417 {
10418         struct drm_device *dev = intel_crtc->base.dev;
10419         struct drm_i915_private *dev_priv = to_i915(dev);
10420         struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10421         i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10422         u32 dspcntr;
10423
10424         dspcntr = I915_READ(reg);
10425
10426         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
10427                 dspcntr |= DISPPLANE_TILED;
10428         else
10429                 dspcntr &= ~DISPPLANE_TILED;
10430
10431         I915_WRITE(reg, dspcntr);
10432
10433         I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10434         POSTING_READ(DSPSURF(intel_crtc->plane));
10435 }
10436
10437 static void intel_mmio_flip_work_func(struct work_struct *w)
10438 {
10439         struct intel_flip_work *work =
10440                 container_of(w, struct intel_flip_work, mmio_work);
10441         struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10442         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10443         struct intel_framebuffer *intel_fb =
10444                 to_intel_framebuffer(crtc->base.primary->fb);
10445         struct drm_i915_gem_object *obj = intel_fb->obj;
10446
10447         WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
10448
10449         intel_pipe_update_start(crtc);
10450
10451         if (INTEL_GEN(dev_priv) >= 9)
10452                 skl_do_mmio_flip(crtc, work->rotation, work);
10453         else
10454                 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10455                 ilk_do_mmio_flip(crtc, work);
10456
10457         intel_pipe_update_end(crtc, work);
10458 }
10459
10460 static int intel_default_queue_flip(struct drm_device *dev,
10461                                     struct drm_crtc *crtc,
10462                                     struct drm_framebuffer *fb,
10463                                     struct drm_i915_gem_object *obj,
10464                                     struct drm_i915_gem_request *req,
10465                                     uint32_t flags)
10466 {
10467         return -ENODEV;
10468 }
10469
10470 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10471                                       struct intel_crtc *intel_crtc,
10472                                       struct intel_flip_work *work)
10473 {
10474         u32 addr, vblank;
10475
10476         if (!atomic_read(&work->pending))
10477                 return false;
10478
10479         smp_rmb();
10480
10481         vblank = intel_crtc_get_vblank_counter(intel_crtc);
10482         if (work->flip_ready_vblank == 0) {
10483                 if (work->flip_queued_req &&
10484                     !i915_gem_request_completed(work->flip_queued_req))
10485                         return false;
10486
10487                 work->flip_ready_vblank = vblank;
10488         }
10489
10490         if (vblank - work->flip_ready_vblank < 3)
10491                 return false;
10492
10493         /* Potential stall - if we see that the flip has happened,
10494          * assume a missed interrupt. */
10495         if (INTEL_GEN(dev_priv) >= 4)
10496                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10497         else
10498                 addr = I915_READ(DSPADDR(intel_crtc->plane));
10499
10500         /* There is a potential issue here with a false positive after a flip
10501          * to the same address. We could address this by checking for a
10502          * non-incrementing frame counter.
10503          */
10504         return addr == work->gtt_offset;
10505 }
10506
10507 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10508 {
10509         struct drm_device *dev = &dev_priv->drm;
10510         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
10511         struct intel_flip_work *work;
10512
10513         WARN_ON(!in_interrupt());
10514
10515         if (crtc == NULL)
10516                 return;
10517
10518         spin_lock(&dev->event_lock);
10519         work = crtc->flip_work;
10520
10521         if (work != NULL && !is_mmio_work(work) &&
10522             __pageflip_stall_check_cs(dev_priv, crtc, work)) {
10523                 WARN_ONCE(1,
10524                           "Kicking stuck page flip: queued at %d, now %d\n",
10525                         work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10526                 page_flip_completed(crtc);
10527                 work = NULL;
10528         }
10529
10530         if (work != NULL && !is_mmio_work(work) &&
10531             intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
10532                 intel_queue_rps_boost_for_request(work->flip_queued_req);
10533         spin_unlock(&dev->event_lock);
10534 }
10535
10536 __maybe_unused
10537 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10538                                 struct drm_framebuffer *fb,
10539                                 struct drm_pending_vblank_event *event,
10540                                 uint32_t page_flip_flags)
10541 {
10542         struct drm_device *dev = crtc->dev;
10543         struct drm_i915_private *dev_priv = to_i915(dev);
10544         struct drm_framebuffer *old_fb = crtc->primary->fb;
10545         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10546         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10547         struct drm_plane *primary = crtc->primary;
10548         enum pipe pipe = intel_crtc->pipe;
10549         struct intel_flip_work *work;
10550         struct intel_engine_cs *engine;
10551         bool mmio_flip;
10552         struct drm_i915_gem_request *request;
10553         struct i915_vma *vma;
10554         int ret;
10555
10556         /*
10557          * drm_mode_page_flip_ioctl() should already catch this, but double
10558          * check to be safe.  In the future we may enable pageflipping from
10559          * a disabled primary plane.
10560          */
10561         if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10562                 return -EBUSY;
10563
10564         /* Can't change pixel format via MI display flips. */
10565         if (fb->format != crtc->primary->fb->format)
10566                 return -EINVAL;
10567
10568         /*
10569          * TILEOFF/LINOFF registers can't be changed via MI display flips.
10570          * Note that pitch changes could also affect these register.
10571          */
10572         if (INTEL_GEN(dev_priv) > 3 &&
10573             (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10574              fb->pitches[0] != crtc->primary->fb->pitches[0]))
10575                 return -EINVAL;
10576
10577         if (i915_terminally_wedged(&dev_priv->gpu_error))
10578                 goto out_hang;
10579
10580         work = kzalloc(sizeof(*work), GFP_KERNEL);
10581         if (work == NULL)
10582                 return -ENOMEM;
10583
10584         work->event = event;
10585         work->crtc = crtc;
10586         work->old_fb = old_fb;
10587         INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10588
10589         ret = drm_crtc_vblank_get(crtc);
10590         if (ret)
10591                 goto free_work;
10592
10593         /* We borrow the event spin lock for protecting flip_work */
10594         spin_lock_irq(&dev->event_lock);
10595         if (intel_crtc->flip_work) {
10596                 /* Before declaring the flip queue wedged, check if
10597                  * the hardware completed the operation behind our backs.
10598                  */
10599                 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10600                         DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10601                         page_flip_completed(intel_crtc);
10602                 } else {
10603                         DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10604                         spin_unlock_irq(&dev->event_lock);
10605
10606                         drm_crtc_vblank_put(crtc);
10607                         kfree(work);
10608                         return -EBUSY;
10609                 }
10610         }
10611         intel_crtc->flip_work = work;
10612         spin_unlock_irq(&dev->event_lock);
10613
10614         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10615                 flush_workqueue(dev_priv->wq);
10616
10617         /* Reference the objects for the scheduled work. */
10618         drm_framebuffer_reference(work->old_fb);
10619
10620         crtc->primary->fb = fb;
10621         update_state_fb(crtc->primary);
10622
10623         work->pending_flip_obj = i915_gem_object_get(obj);
10624
10625         ret = i915_mutex_lock_interruptible(dev);
10626         if (ret)
10627                 goto cleanup;
10628
10629         intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
10630         if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) {
10631                 ret = -EIO;
10632                 goto unlock;
10633         }
10634
10635         atomic_inc(&intel_crtc->unpin_work_count);
10636
10637         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
10638                 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10639
10640         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
10641                 engine = dev_priv->engine[BCS];
10642                 if (fb->modifier != old_fb->modifier)
10643                         /* vlv: DISPLAY_FLIP fails to change tiling */
10644                         engine = NULL;
10645         } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
10646                 engine = dev_priv->engine[BCS];
10647         } else if (INTEL_GEN(dev_priv) >= 7) {
10648                 engine = i915_gem_object_last_write_engine(obj);
10649                 if (engine == NULL || engine->id != RCS)
10650                         engine = dev_priv->engine[BCS];
10651         } else {
10652                 engine = dev_priv->engine[RCS];
10653         }
10654
10655         mmio_flip = use_mmio_flip(engine, obj);
10656
10657         vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10658         if (IS_ERR(vma)) {
10659                 ret = PTR_ERR(vma);
10660                 goto cleanup_pending;
10661         }
10662
10663         work->old_vma = to_intel_plane_state(primary->state)->vma;
10664         to_intel_plane_state(primary->state)->vma = vma;
10665
10666         work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
10667         work->rotation = crtc->primary->state->rotation;
10668
10669         /*
10670          * There's the potential that the next frame will not be compatible with
10671          * FBC, so we want to call pre_update() before the actual page flip.
10672          * The problem is that pre_update() caches some information about the fb
10673          * object, so we want to do this only after the object is pinned. Let's
10674          * be on the safe side and do this immediately before scheduling the
10675          * flip.
10676          */
10677         intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10678                              to_intel_plane_state(primary->state));
10679
10680         if (mmio_flip) {
10681                 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
10682                 queue_work(system_unbound_wq, &work->mmio_work);
10683         } else {
10684                 request = i915_gem_request_alloc(engine,
10685                                                  dev_priv->kernel_context);
10686                 if (IS_ERR(request)) {
10687                         ret = PTR_ERR(request);
10688                         goto cleanup_unpin;
10689                 }
10690
10691                 ret = i915_gem_request_await_object(request, obj, false);
10692                 if (ret)
10693                         goto cleanup_request;
10694
10695                 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10696                                                    page_flip_flags);
10697                 if (ret)
10698                         goto cleanup_request;
10699
10700                 intel_mark_page_flip_active(intel_crtc, work);
10701
10702                 work->flip_queued_req = i915_gem_request_get(request);
10703                 i915_add_request(request);
10704         }
10705
10706         i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
10707         i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10708                           to_intel_plane(primary)->frontbuffer_bit);
10709         mutex_unlock(&dev->struct_mutex);
10710
10711         intel_frontbuffer_flip_prepare(to_i915(dev),
10712                                        to_intel_plane(primary)->frontbuffer_bit);
10713
10714         trace_i915_flip_request(intel_crtc->plane, obj);
10715
10716         return 0;
10717
10718 cleanup_request:
10719         i915_add_request(request);
10720 cleanup_unpin:
10721         to_intel_plane_state(primary->state)->vma = work->old_vma;
10722         intel_unpin_fb_vma(vma);
10723 cleanup_pending:
10724         atomic_dec(&intel_crtc->unpin_work_count);
10725 unlock:
10726         mutex_unlock(&dev->struct_mutex);
10727 cleanup:
10728         crtc->primary->fb = old_fb;
10729         update_state_fb(crtc->primary);
10730
10731         i915_gem_object_put(obj);
10732         drm_framebuffer_unreference(work->old_fb);
10733
10734         spin_lock_irq(&dev->event_lock);
10735         intel_crtc->flip_work = NULL;
10736         spin_unlock_irq(&dev->event_lock);
10737
10738         drm_crtc_vblank_put(crtc);
10739 free_work:
10740         kfree(work);
10741
10742         if (ret == -EIO) {
10743                 struct drm_atomic_state *state;
10744                 struct drm_plane_state *plane_state;
10745
10746 out_hang:
10747                 state = drm_atomic_state_alloc(dev);
10748                 if (!state)
10749                         return -ENOMEM;
10750                 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
10751
10752 retry:
10753                 plane_state = drm_atomic_get_plane_state(state, primary);
10754                 ret = PTR_ERR_OR_ZERO(plane_state);
10755                 if (!ret) {
10756                         drm_atomic_set_fb_for_plane(plane_state, fb);
10757
10758                         ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10759                         if (!ret)
10760                                 ret = drm_atomic_commit(state);
10761                 }
10762
10763                 if (ret == -EDEADLK) {
10764                         drm_modeset_backoff(state->acquire_ctx);
10765                         drm_atomic_state_clear(state);
10766                         goto retry;
10767                 }
10768
10769                 drm_atomic_state_put(state);
10770
10771                 if (ret == 0 && event) {
10772                         spin_lock_irq(&dev->event_lock);
10773                         drm_crtc_send_vblank_event(crtc, event);
10774                         spin_unlock_irq(&dev->event_lock);
10775                 }
10776         }
10777         return ret;
10778 }
10779
10780
10781 /**
10782  * intel_wm_need_update - Check whether watermarks need updating
10783  * @plane: drm plane
10784  * @state: new plane state
10785  *
10786  * Check current plane state versus the new one to determine whether
10787  * watermarks need to be recalculated.
10788  *
10789  * Returns true or false.
10790  */
10791 static bool intel_wm_need_update(struct drm_plane *plane,
10792                                  struct drm_plane_state *state)
10793 {
10794         struct intel_plane_state *new = to_intel_plane_state(state);
10795         struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10796
10797         /* Update watermarks on tiling or size changes. */
10798         if (new->base.visible != cur->base.visible)
10799                 return true;
10800
10801         if (!cur->base.fb || !new->base.fb)
10802                 return false;
10803
10804         if (cur->base.fb->modifier != new->base.fb->modifier ||
10805             cur->base.rotation != new->base.rotation ||
10806             drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10807             drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10808             drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10809             drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
10810                 return true;
10811
10812         return false;
10813 }
10814
10815 static bool needs_scaling(struct intel_plane_state *state)
10816 {
10817         int src_w = drm_rect_width(&state->base.src) >> 16;
10818         int src_h = drm_rect_height(&state->base.src) >> 16;
10819         int dst_w = drm_rect_width(&state->base.dst);
10820         int dst_h = drm_rect_height(&state->base.dst);
10821
10822         return (src_w != dst_w || src_h != dst_h);
10823 }
10824
10825 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10826                                     struct drm_plane_state *plane_state)
10827 {
10828         struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
10829         struct drm_crtc *crtc = crtc_state->crtc;
10830         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10831         struct intel_plane *plane = to_intel_plane(plane_state->plane);
10832         struct drm_device *dev = crtc->dev;
10833         struct drm_i915_private *dev_priv = to_i915(dev);
10834         struct intel_plane_state *old_plane_state =
10835                 to_intel_plane_state(plane->base.state);
10836         bool mode_changed = needs_modeset(crtc_state);
10837         bool was_crtc_enabled = crtc->state->active;
10838         bool is_crtc_enabled = crtc_state->active;
10839         bool turn_off, turn_on, visible, was_visible;
10840         struct drm_framebuffer *fb = plane_state->fb;
10841         int ret;
10842
10843         if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
10844                 ret = skl_update_scaler_plane(
10845                         to_intel_crtc_state(crtc_state),
10846                         to_intel_plane_state(plane_state));
10847                 if (ret)
10848                         return ret;
10849         }
10850
10851         was_visible = old_plane_state->base.visible;
10852         visible = plane_state->visible;
10853
10854         if (!was_crtc_enabled && WARN_ON(was_visible))
10855                 was_visible = false;
10856
10857         /*
10858          * Visibility is calculated as if the crtc was on, but
10859          * after scaler setup everything depends on it being off
10860          * when the crtc isn't active.
10861          *
10862          * FIXME this is wrong for watermarks. Watermarks should also
10863          * be computed as if the pipe would be active. Perhaps move
10864          * per-plane wm computation to the .check_plane() hook, and
10865          * only combine the results from all planes in the current place?
10866          */
10867         if (!is_crtc_enabled) {
10868                 plane_state->visible = visible = false;
10869                 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10870         }
10871
10872         if (!was_visible && !visible)
10873                 return 0;
10874
10875         if (fb != old_plane_state->base.fb)
10876                 pipe_config->fb_changed = true;
10877
10878         turn_off = was_visible && (!visible || mode_changed);
10879         turn_on = visible && (!was_visible || mode_changed);
10880
10881         DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
10882                          intel_crtc->base.base.id, intel_crtc->base.name,
10883                          plane->base.base.id, plane->base.name,
10884                          fb ? fb->base.id : -1);
10885
10886         DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
10887                          plane->base.base.id, plane->base.name,
10888                          was_visible, visible,
10889                          turn_off, turn_on, mode_changed);
10890
10891         if (turn_on) {
10892                 if (INTEL_GEN(dev_priv) < 5)
10893                         pipe_config->update_wm_pre = true;
10894
10895                 /* must disable cxsr around plane enable/disable */
10896                 if (plane->id != PLANE_CURSOR)
10897                         pipe_config->disable_cxsr = true;
10898         } else if (turn_off) {
10899                 if (INTEL_GEN(dev_priv) < 5)
10900                         pipe_config->update_wm_post = true;
10901
10902                 /* must disable cxsr around plane enable/disable */
10903                 if (plane->id != PLANE_CURSOR)
10904                         pipe_config->disable_cxsr = true;
10905         } else if (intel_wm_need_update(&plane->base, plane_state)) {
10906                 if (INTEL_GEN(dev_priv) < 5) {
10907                         /* FIXME bollocks */
10908                         pipe_config->update_wm_pre = true;
10909                         pipe_config->update_wm_post = true;
10910                 }
10911         }
10912
10913         if (visible || was_visible)
10914                 pipe_config->fb_bits |= plane->frontbuffer_bit;
10915
10916         /*
10917          * WaCxSRDisabledForSpriteScaling:ivb
10918          *
10919          * cstate->update_wm was already set above, so this flag will
10920          * take effect when we commit and program watermarks.
10921          */
10922         if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
10923             needs_scaling(to_intel_plane_state(plane_state)) &&
10924             !needs_scaling(old_plane_state))
10925                 pipe_config->disable_lp_wm = true;
10926
10927         return 0;
10928 }
10929
10930 static bool encoders_cloneable(const struct intel_encoder *a,
10931                                const struct intel_encoder *b)
10932 {
10933         /* masks could be asymmetric, so check both ways */
10934         return a == b || (a->cloneable & (1 << b->type) &&
10935                           b->cloneable & (1 << a->type));
10936 }
10937
10938 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10939                                          struct intel_crtc *crtc,
10940                                          struct intel_encoder *encoder)
10941 {
10942         struct intel_encoder *source_encoder;
10943         struct drm_connector *connector;
10944         struct drm_connector_state *connector_state;
10945         int i;
10946
10947         for_each_new_connector_in_state(state, connector, connector_state, i) {
10948                 if (connector_state->crtc != &crtc->base)
10949                         continue;
10950
10951                 source_encoder =
10952                         to_intel_encoder(connector_state->best_encoder);
10953                 if (!encoders_cloneable(encoder, source_encoder))
10954                         return false;
10955         }
10956
10957         return true;
10958 }
10959
10960 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10961                                    struct drm_crtc_state *crtc_state)
10962 {
10963         struct drm_device *dev = crtc->dev;
10964         struct drm_i915_private *dev_priv = to_i915(dev);
10965         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10966         struct intel_crtc_state *pipe_config =
10967                 to_intel_crtc_state(crtc_state);
10968         struct drm_atomic_state *state = crtc_state->state;
10969         int ret;
10970         bool mode_changed = needs_modeset(crtc_state);
10971
10972         if (mode_changed && !crtc_state->active)
10973                 pipe_config->update_wm_post = true;
10974
10975         if (mode_changed && crtc_state->enable &&
10976             dev_priv->display.crtc_compute_clock &&
10977             !WARN_ON(pipe_config->shared_dpll)) {
10978                 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10979                                                            pipe_config);
10980                 if (ret)
10981                         return ret;
10982         }
10983
10984         if (crtc_state->color_mgmt_changed) {
10985                 ret = intel_color_check(crtc, crtc_state);
10986                 if (ret)
10987                         return ret;
10988
10989                 /*
10990                  * Changing color management on Intel hardware is
10991                  * handled as part of planes update.
10992                  */
10993                 crtc_state->planes_changed = true;
10994         }
10995
10996         ret = 0;
10997         if (dev_priv->display.compute_pipe_wm) {
10998                 ret = dev_priv->display.compute_pipe_wm(pipe_config);
10999                 if (ret) {
11000                         DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11001                         return ret;
11002                 }
11003         }
11004
11005         if (dev_priv->display.compute_intermediate_wm &&
11006             !to_intel_atomic_state(state)->skip_intermediate_wm) {
11007                 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11008                         return 0;
11009
11010                 /*
11011                  * Calculate 'intermediate' watermarks that satisfy both the
11012                  * old state and the new state.  We can program these
11013                  * immediately.
11014                  */
11015                 ret = dev_priv->display.compute_intermediate_wm(dev,
11016                                                                 intel_crtc,
11017                                                                 pipe_config);
11018                 if (ret) {
11019                         DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11020                         return ret;
11021                 }
11022         } else if (dev_priv->display.compute_intermediate_wm) {
11023                 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
11024                         pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
11025         }
11026
11027         if (INTEL_GEN(dev_priv) >= 9) {
11028                 if (mode_changed)
11029                         ret = skl_update_scaler_crtc(pipe_config);
11030
11031                 if (!ret)
11032                         ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
11033                                                          pipe_config);
11034         }
11035
11036         return ret;
11037 }
11038
11039 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11040         .mode_set_base_atomic = intel_pipe_set_base_atomic,
11041         .atomic_begin = intel_begin_crtc_commit,
11042         .atomic_flush = intel_finish_crtc_commit,
11043         .atomic_check = intel_crtc_atomic_check,
11044 };
11045
11046 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11047 {
11048         struct intel_connector *connector;
11049         struct drm_connector_list_iter conn_iter;
11050
11051         drm_connector_list_iter_begin(dev, &conn_iter);
11052         for_each_intel_connector_iter(connector, &conn_iter) {
11053                 if (connector->base.state->crtc)
11054                         drm_connector_unreference(&connector->base);
11055
11056                 if (connector->base.encoder) {
11057                         connector->base.state->best_encoder =
11058                                 connector->base.encoder;
11059                         connector->base.state->crtc =
11060                                 connector->base.encoder->crtc;
11061
11062                         drm_connector_reference(&connector->base);
11063                 } else {
11064                         connector->base.state->best_encoder = NULL;
11065                         connector->base.state->crtc = NULL;
11066                 }
11067         }
11068         drm_connector_list_iter_end(&conn_iter);
11069 }
11070
11071 static void
11072 connected_sink_compute_bpp(struct intel_connector *connector,
11073                            struct intel_crtc_state *pipe_config)
11074 {
11075         const struct drm_display_info *info = &connector->base.display_info;
11076         int bpp = pipe_config->pipe_bpp;
11077
11078         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11079                       connector->base.base.id,
11080                       connector->base.name);
11081
11082         /* Don't use an invalid EDID bpc value */
11083         if (info->bpc != 0 && info->bpc * 3 < bpp) {
11084                 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11085                               bpp, info->bpc * 3);
11086                 pipe_config->pipe_bpp = info->bpc * 3;
11087         }
11088
11089         /* Clamp bpp to 8 on screens without EDID 1.4 */
11090         if (info->bpc == 0 && bpp > 24) {
11091                 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11092                               bpp);
11093                 pipe_config->pipe_bpp = 24;
11094         }
11095 }
11096
11097 static int
11098 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11099                           struct intel_crtc_state *pipe_config)
11100 {
11101         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11102         struct drm_atomic_state *state;
11103         struct drm_connector *connector;
11104         struct drm_connector_state *connector_state;
11105         int bpp, i;
11106
11107         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11108             IS_CHERRYVIEW(dev_priv)))
11109                 bpp = 10*3;
11110         else if (INTEL_GEN(dev_priv) >= 5)
11111                 bpp = 12*3;
11112         else
11113                 bpp = 8*3;
11114
11115
11116         pipe_config->pipe_bpp = bpp;
11117
11118         state = pipe_config->base.state;
11119
11120         /* Clamp display bpp to EDID value */
11121         for_each_new_connector_in_state(state, connector, connector_state, i) {
11122                 if (connector_state->crtc != &crtc->base)
11123                         continue;
11124
11125                 connected_sink_compute_bpp(to_intel_connector(connector),
11126                                            pipe_config);
11127         }
11128
11129         return bpp;
11130 }
11131
11132 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11133 {
11134         DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11135                         "type: 0x%x flags: 0x%x\n",
11136                 mode->crtc_clock,
11137                 mode->crtc_hdisplay, mode->crtc_hsync_start,
11138                 mode->crtc_hsync_end, mode->crtc_htotal,
11139                 mode->crtc_vdisplay, mode->crtc_vsync_start,
11140                 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11141 }
11142
11143 static inline void
11144 intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
11145                       unsigned int lane_count, struct intel_link_m_n *m_n)
11146 {
11147         DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11148                       id, lane_count,
11149                       m_n->gmch_m, m_n->gmch_n,
11150                       m_n->link_m, m_n->link_n, m_n->tu);
11151 }
11152
11153 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11154                                    struct intel_crtc_state *pipe_config,
11155                                    const char *context)
11156 {
11157         struct drm_device *dev = crtc->base.dev;
11158         struct drm_i915_private *dev_priv = to_i915(dev);
11159         struct drm_plane *plane;
11160         struct intel_plane *intel_plane;
11161         struct intel_plane_state *state;
11162         struct drm_framebuffer *fb;
11163
11164         DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11165                       crtc->base.base.id, crtc->base.name, context);
11166
11167         DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11168                       transcoder_name(pipe_config->cpu_transcoder),
11169                       pipe_config->pipe_bpp, pipe_config->dither);
11170
11171         if (pipe_config->has_pch_encoder)
11172                 intel_dump_m_n_config(pipe_config, "fdi",
11173                                       pipe_config->fdi_lanes,
11174                                       &pipe_config->fdi_m_n);
11175
11176         if (intel_crtc_has_dp_encoder(pipe_config)) {
11177                 intel_dump_m_n_config(pipe_config, "dp m_n",
11178                                 pipe_config->lane_count, &pipe_config->dp_m_n);
11179                 if (pipe_config->has_drrs)
11180                         intel_dump_m_n_config(pipe_config, "dp m2_n2",
11181                                               pipe_config->lane_count,
11182                                               &pipe_config->dp_m2_n2);
11183         }
11184
11185         DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11186                       pipe_config->has_audio, pipe_config->has_infoframe);
11187
11188         DRM_DEBUG_KMS("requested mode:\n");
11189         drm_mode_debug_printmodeline(&pipe_config->base.mode);
11190         DRM_DEBUG_KMS("adjusted mode:\n");
11191         drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11192         intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11193         DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
11194                       pipe_config->port_clock,
11195                       pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11196                       pipe_config->pixel_rate);
11197
11198         if (INTEL_GEN(dev_priv) >= 9)
11199                 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11200                               crtc->num_scalers,
11201                               pipe_config->scaler_state.scaler_users,
11202                               pipe_config->scaler_state.scaler_id);
11203
11204         if (HAS_GMCH_DISPLAY(dev_priv))
11205                 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11206                               pipe_config->gmch_pfit.control,
11207                               pipe_config->gmch_pfit.pgm_ratios,
11208                               pipe_config->gmch_pfit.lvds_border_bits);
11209         else
11210                 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11211                               pipe_config->pch_pfit.pos,
11212                               pipe_config->pch_pfit.size,
11213                               enableddisabled(pipe_config->pch_pfit.enabled));
11214
11215         DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11216                       pipe_config->ips_enabled, pipe_config->double_wide);
11217
11218         intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
11219
11220         DRM_DEBUG_KMS("planes on this crtc\n");
11221         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11222                 struct drm_format_name_buf format_name;
11223                 intel_plane = to_intel_plane(plane);
11224                 if (intel_plane->pipe != crtc->pipe)
11225                         continue;
11226
11227                 state = to_intel_plane_state(plane->state);
11228                 fb = state->base.fb;
11229                 if (!fb) {
11230                         DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11231                                       plane->base.id, plane->name, state->scaler_id);
11232                         continue;
11233                 }
11234
11235                 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11236                               plane->base.id, plane->name,
11237                               fb->base.id, fb->width, fb->height,
11238                               drm_get_format_name(fb->format->format, &format_name));
11239                 if (INTEL_GEN(dev_priv) >= 9)
11240                         DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11241                                       state->scaler_id,
11242                                       state->base.src.x1 >> 16,
11243                                       state->base.src.y1 >> 16,
11244                                       drm_rect_width(&state->base.src) >> 16,
11245                                       drm_rect_height(&state->base.src) >> 16,
11246                                       state->base.dst.x1, state->base.dst.y1,
11247                                       drm_rect_width(&state->base.dst),
11248                                       drm_rect_height(&state->base.dst));
11249         }
11250 }
11251
11252 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11253 {
11254         struct drm_device *dev = state->dev;
11255         struct drm_connector *connector;
11256         unsigned int used_ports = 0;
11257         unsigned int used_mst_ports = 0;
11258
11259         /*
11260          * Walk the connector list instead of the encoder
11261          * list to detect the problem on ddi platforms
11262          * where there's just one encoder per digital port.
11263          */
11264         drm_for_each_connector(connector, dev) {
11265                 struct drm_connector_state *connector_state;
11266                 struct intel_encoder *encoder;
11267
11268                 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11269                 if (!connector_state)
11270                         connector_state = connector->state;
11271
11272                 if (!connector_state->best_encoder)
11273                         continue;
11274
11275                 encoder = to_intel_encoder(connector_state->best_encoder);
11276
11277                 WARN_ON(!connector_state->crtc);
11278
11279                 switch (encoder->type) {
11280                         unsigned int port_mask;
11281                 case INTEL_OUTPUT_UNKNOWN:
11282                         if (WARN_ON(!HAS_DDI(to_i915(dev))))
11283                                 break;
11284                 case INTEL_OUTPUT_DP:
11285                 case INTEL_OUTPUT_HDMI:
11286                 case INTEL_OUTPUT_EDP:
11287                         port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11288
11289                         /* the same port mustn't appear more than once */
11290                         if (used_ports & port_mask)
11291                                 return false;
11292
11293                         used_ports |= port_mask;
11294                         break;
11295                 case INTEL_OUTPUT_DP_MST:
11296                         used_mst_ports |=
11297                                 1 << enc_to_mst(&encoder->base)->primary->port;
11298                         break;
11299                 default:
11300                         break;
11301                 }
11302         }
11303
11304         /* can't mix MST and SST/HDMI on the same port */
11305         if (used_ports & used_mst_ports)
11306                 return false;
11307
11308         return true;
11309 }
11310
11311 static void
11312 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11313 {
11314         struct drm_i915_private *dev_priv =
11315                 to_i915(crtc_state->base.crtc->dev);
11316         struct intel_crtc_scaler_state scaler_state;
11317         struct intel_dpll_hw_state dpll_hw_state;
11318         struct intel_shared_dpll *shared_dpll;
11319         struct intel_crtc_wm_state wm_state;
11320         bool force_thru;
11321
11322         /* FIXME: before the switch to atomic started, a new pipe_config was
11323          * kzalloc'd. Code that depends on any field being zero should be
11324          * fixed, so that the crtc_state can be safely duplicated. For now,
11325          * only fields that are know to not cause problems are preserved. */
11326
11327         scaler_state = crtc_state->scaler_state;
11328         shared_dpll = crtc_state->shared_dpll;
11329         dpll_hw_state = crtc_state->dpll_hw_state;
11330         force_thru = crtc_state->pch_pfit.force_thru;
11331         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11332                 wm_state = crtc_state->wm;
11333
11334         /* Keep base drm_crtc_state intact, only clear our extended struct */
11335         BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11336         memset(&crtc_state->base + 1, 0,
11337                sizeof(*crtc_state) - sizeof(crtc_state->base));
11338
11339         crtc_state->scaler_state = scaler_state;
11340         crtc_state->shared_dpll = shared_dpll;
11341         crtc_state->dpll_hw_state = dpll_hw_state;
11342         crtc_state->pch_pfit.force_thru = force_thru;
11343         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11344                 crtc_state->wm = wm_state;
11345 }
11346
11347 static int
11348 intel_modeset_pipe_config(struct drm_crtc *crtc,
11349                           struct intel_crtc_state *pipe_config)
11350 {
11351         struct drm_atomic_state *state = pipe_config->base.state;
11352         struct intel_encoder *encoder;
11353         struct drm_connector *connector;
11354         struct drm_connector_state *connector_state;
11355         int base_bpp, ret = -EINVAL;
11356         int i;
11357         bool retry = true;
11358
11359         clear_intel_crtc_state(pipe_config);
11360
11361         pipe_config->cpu_transcoder =
11362                 (enum transcoder) to_intel_crtc(crtc)->pipe;
11363
11364         /*
11365          * Sanitize sync polarity flags based on requested ones. If neither
11366          * positive or negative polarity is requested, treat this as meaning
11367          * negative polarity.
11368          */
11369         if (!(pipe_config->base.adjusted_mode.flags &
11370               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11371                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11372
11373         if (!(pipe_config->base.adjusted_mode.flags &
11374               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11375                 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11376
11377         base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11378                                              pipe_config);
11379         if (base_bpp < 0)
11380                 goto fail;
11381
11382         /*
11383          * Determine the real pipe dimensions. Note that stereo modes can
11384          * increase the actual pipe size due to the frame doubling and
11385          * insertion of additional space for blanks between the frame. This
11386          * is stored in the crtc timings. We use the requested mode to do this
11387          * computation to clearly distinguish it from the adjusted mode, which
11388          * can be changed by the connectors in the below retry loop.
11389          */
11390         drm_mode_get_hv_timing(&pipe_config->base.mode,
11391                                &pipe_config->pipe_src_w,
11392                                &pipe_config->pipe_src_h);
11393
11394         for_each_new_connector_in_state(state, connector, connector_state, i) {
11395                 if (connector_state->crtc != crtc)
11396                         continue;
11397
11398                 encoder = to_intel_encoder(connector_state->best_encoder);
11399
11400                 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11401                         DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11402                         goto fail;
11403                 }
11404
11405                 /*
11406                  * Determine output_types before calling the .compute_config()
11407                  * hooks so that the hooks can use this information safely.
11408                  */
11409                 pipe_config->output_types |= 1 << encoder->type;
11410         }
11411
11412 encoder_retry:
11413         /* Ensure the port clock defaults are reset when retrying. */
11414         pipe_config->port_clock = 0;
11415         pipe_config->pixel_multiplier = 1;
11416
11417         /* Fill in default crtc timings, allow encoders to overwrite them. */
11418         drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11419                               CRTC_STEREO_DOUBLE);
11420
11421         /* Pass our mode to the connectors and the CRTC to give them a chance to
11422          * adjust it according to limitations or connector properties, and also
11423          * a chance to reject the mode entirely.
11424          */
11425         for_each_new_connector_in_state(state, connector, connector_state, i) {
11426                 if (connector_state->crtc != crtc)
11427                         continue;
11428
11429                 encoder = to_intel_encoder(connector_state->best_encoder);
11430
11431                 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
11432                         DRM_DEBUG_KMS("Encoder config failure\n");
11433                         goto fail;
11434                 }
11435         }
11436
11437         /* Set default port clock if not overwritten by the encoder. Needs to be
11438          * done afterwards in case the encoder adjusts the mode. */
11439         if (!pipe_config->port_clock)
11440                 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11441                         * pipe_config->pixel_multiplier;
11442
11443         ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11444         if (ret < 0) {
11445                 DRM_DEBUG_KMS("CRTC fixup failed\n");
11446                 goto fail;
11447         }
11448
11449         if (ret == RETRY) {
11450                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11451                         ret = -EINVAL;
11452                         goto fail;
11453                 }
11454
11455                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11456                 retry = false;
11457                 goto encoder_retry;
11458         }
11459
11460         /* Dithering seems to not pass-through bits correctly when it should, so
11461          * only enable it on 6bpc panels and when its not a compliance
11462          * test requesting 6bpc video pattern.
11463          */
11464         pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11465                 !pipe_config->dither_force_disable;
11466         DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
11467                       base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11468
11469 fail:
11470         return ret;
11471 }
11472
11473 static void
11474 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
11475 {
11476         struct drm_crtc *crtc;
11477         struct drm_crtc_state *new_crtc_state;
11478         int i;
11479
11480         /* Double check state. */
11481         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11482                 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
11483
11484                 /* Update hwmode for vblank functions */
11485                 if (new_crtc_state->active)
11486                         crtc->hwmode = new_crtc_state->adjusted_mode;
11487                 else
11488                         crtc->hwmode.crtc_clock = 0;
11489
11490                 /*
11491                  * Update legacy state to satisfy fbc code. This can
11492                  * be removed when fbc uses the atomic state.
11493                  */
11494                 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11495                         struct drm_plane_state *plane_state = crtc->primary->state;
11496
11497                         crtc->primary->fb = plane_state->fb;
11498                         crtc->x = plane_state->src_x >> 16;
11499                         crtc->y = plane_state->src_y >> 16;
11500                 }
11501         }
11502 }
11503
11504 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11505 {
11506         int diff;
11507
11508         if (clock1 == clock2)
11509                 return true;
11510
11511         if (!clock1 || !clock2)
11512                 return false;
11513
11514         diff = abs(clock1 - clock2);
11515
11516         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11517                 return true;
11518
11519         return false;
11520 }
11521
11522 static bool
11523 intel_compare_m_n(unsigned int m, unsigned int n,
11524                   unsigned int m2, unsigned int n2,
11525                   bool exact)
11526 {
11527         if (m == m2 && n == n2)
11528                 return true;
11529
11530         if (exact || !m || !n || !m2 || !n2)
11531                 return false;
11532
11533         BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11534
11535         if (n > n2) {
11536                 while (n > n2) {
11537                         m2 <<= 1;
11538                         n2 <<= 1;
11539                 }
11540         } else if (n < n2) {
11541                 while (n < n2) {
11542                         m <<= 1;
11543                         n <<= 1;
11544                 }
11545         }
11546
11547         if (n != n2)
11548                 return false;
11549
11550         return intel_fuzzy_clock_check(m, m2);
11551 }
11552
11553 static bool
11554 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11555                        struct intel_link_m_n *m2_n2,
11556                        bool adjust)
11557 {
11558         if (m_n->tu == m2_n2->tu &&
11559             intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11560                               m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11561             intel_compare_m_n(m_n->link_m, m_n->link_n,
11562                               m2_n2->link_m, m2_n2->link_n, !adjust)) {
11563                 if (adjust)
11564                         *m2_n2 = *m_n;
11565
11566                 return true;
11567         }
11568
11569         return false;
11570 }
11571
11572 static void __printf(3, 4)
11573 pipe_config_err(bool adjust, const char *name, const char *format, ...)
11574 {
11575         char *level;
11576         unsigned int category;
11577         struct va_format vaf;
11578         va_list args;
11579
11580         if (adjust) {
11581                 level = KERN_DEBUG;
11582                 category = DRM_UT_KMS;
11583         } else {
11584                 level = KERN_ERR;
11585                 category = DRM_UT_NONE;
11586         }
11587
11588         va_start(args, format);
11589         vaf.fmt = format;
11590         vaf.va = &args;
11591
11592         drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11593
11594         va_end(args);
11595 }
11596
11597 static bool
11598 intel_pipe_config_compare(struct drm_i915_private *dev_priv,
11599                           struct intel_crtc_state *current_config,
11600                           struct intel_crtc_state *pipe_config,
11601                           bool adjust)
11602 {
11603         bool ret = true;
11604
11605 #define PIPE_CONF_CHECK_X(name) \
11606         if (current_config->name != pipe_config->name) { \
11607                 pipe_config_err(adjust, __stringify(name), \
11608                           "(expected 0x%08x, found 0x%08x)\n", \
11609                           current_config->name, \
11610                           pipe_config->name); \
11611                 ret = false; \
11612         }
11613
11614 #define PIPE_CONF_CHECK_I(name) \
11615         if (current_config->name != pipe_config->name) { \
11616                 pipe_config_err(adjust, __stringify(name), \
11617                           "(expected %i, found %i)\n", \
11618                           current_config->name, \
11619                           pipe_config->name); \
11620                 ret = false; \
11621         }
11622
11623 #define PIPE_CONF_CHECK_P(name) \
11624         if (current_config->name != pipe_config->name) { \
11625                 pipe_config_err(adjust, __stringify(name), \
11626                           "(expected %p, found %p)\n", \
11627                           current_config->name, \
11628                           pipe_config->name); \
11629                 ret = false; \
11630         }
11631
11632 #define PIPE_CONF_CHECK_M_N(name) \
11633         if (!intel_compare_link_m_n(&current_config->name, \
11634                                     &pipe_config->name,\
11635                                     adjust)) { \
11636                 pipe_config_err(adjust, __stringify(name), \
11637                           "(expected tu %i gmch %i/%i link %i/%i, " \
11638                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11639                           current_config->name.tu, \
11640                           current_config->name.gmch_m, \
11641                           current_config->name.gmch_n, \
11642                           current_config->name.link_m, \
11643                           current_config->name.link_n, \
11644                           pipe_config->name.tu, \
11645                           pipe_config->name.gmch_m, \
11646                           pipe_config->name.gmch_n, \
11647                           pipe_config->name.link_m, \
11648                           pipe_config->name.link_n); \
11649                 ret = false; \
11650         }
11651
11652 /* This is required for BDW+ where there is only one set of registers for
11653  * switching between high and low RR.
11654  * This macro can be used whenever a comparison has to be made between one
11655  * hw state and multiple sw state variables.
11656  */
11657 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11658         if (!intel_compare_link_m_n(&current_config->name, \
11659                                     &pipe_config->name, adjust) && \
11660             !intel_compare_link_m_n(&current_config->alt_name, \
11661                                     &pipe_config->name, adjust)) { \
11662                 pipe_config_err(adjust, __stringify(name), \
11663                           "(expected tu %i gmch %i/%i link %i/%i, " \
11664                           "or tu %i gmch %i/%i link %i/%i, " \
11665                           "found tu %i, gmch %i/%i link %i/%i)\n", \
11666                           current_config->name.tu, \
11667                           current_config->name.gmch_m, \
11668                           current_config->name.gmch_n, \
11669                           current_config->name.link_m, \
11670                           current_config->name.link_n, \
11671                           current_config->alt_name.tu, \
11672                           current_config->alt_name.gmch_m, \
11673                           current_config->alt_name.gmch_n, \
11674                           current_config->alt_name.link_m, \
11675                           current_config->alt_name.link_n, \
11676                           pipe_config->name.tu, \
11677                           pipe_config->name.gmch_m, \
11678                           pipe_config->name.gmch_n, \
11679                           pipe_config->name.link_m, \
11680                           pipe_config->name.link_n); \
11681                 ret = false; \
11682         }
11683
11684 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
11685         if ((current_config->name ^ pipe_config->name) & (mask)) { \
11686                 pipe_config_err(adjust, __stringify(name), \
11687                           "(%x) (expected %i, found %i)\n", \
11688                           (mask), \
11689                           current_config->name & (mask), \
11690                           pipe_config->name & (mask)); \
11691                 ret = false; \
11692         }
11693
11694 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11695         if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11696                 pipe_config_err(adjust, __stringify(name), \
11697                           "(expected %i, found %i)\n", \
11698                           current_config->name, \
11699                           pipe_config->name); \
11700                 ret = false; \
11701         }
11702
11703 #define PIPE_CONF_QUIRK(quirk)  \
11704         ((current_config->quirks | pipe_config->quirks) & (quirk))
11705
11706         PIPE_CONF_CHECK_I(cpu_transcoder);
11707
11708         PIPE_CONF_CHECK_I(has_pch_encoder);
11709         PIPE_CONF_CHECK_I(fdi_lanes);
11710         PIPE_CONF_CHECK_M_N(fdi_m_n);
11711
11712         PIPE_CONF_CHECK_I(lane_count);
11713         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
11714
11715         if (INTEL_GEN(dev_priv) < 8) {
11716                 PIPE_CONF_CHECK_M_N(dp_m_n);
11717
11718                 if (current_config->has_drrs)
11719                         PIPE_CONF_CHECK_M_N(dp_m2_n2);
11720         } else
11721                 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
11722
11723         PIPE_CONF_CHECK_X(output_types);
11724
11725         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11726         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11727         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11728         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11729         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11730         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11731
11732         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11733         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11734         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11735         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11736         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11737         PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11738
11739         PIPE_CONF_CHECK_I(pixel_multiplier);
11740         PIPE_CONF_CHECK_I(has_hdmi_sink);
11741         if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
11742             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11743                 PIPE_CONF_CHECK_I(limited_color_range);
11744         PIPE_CONF_CHECK_I(has_infoframe);
11745
11746         PIPE_CONF_CHECK_I(has_audio);
11747
11748         PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11749                               DRM_MODE_FLAG_INTERLACE);
11750
11751         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11752                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11753                                       DRM_MODE_FLAG_PHSYNC);
11754                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11755                                       DRM_MODE_FLAG_NHSYNC);
11756                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11757                                       DRM_MODE_FLAG_PVSYNC);
11758                 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11759                                       DRM_MODE_FLAG_NVSYNC);
11760         }
11761
11762         PIPE_CONF_CHECK_X(gmch_pfit.control);
11763         /* pfit ratios are autocomputed by the hw on gen4+ */
11764         if (INTEL_GEN(dev_priv) < 4)
11765                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
11766         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
11767
11768         if (!adjust) {
11769                 PIPE_CONF_CHECK_I(pipe_src_w);
11770                 PIPE_CONF_CHECK_I(pipe_src_h);
11771
11772                 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11773                 if (current_config->pch_pfit.enabled) {
11774                         PIPE_CONF_CHECK_X(pch_pfit.pos);
11775                         PIPE_CONF_CHECK_X(pch_pfit.size);
11776                 }
11777
11778                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11779                 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
11780         }
11781
11782         /* BDW+ don't expose a synchronous way to read the state */
11783         if (IS_HASWELL(dev_priv))
11784                 PIPE_CONF_CHECK_I(ips_enabled);
11785
11786         PIPE_CONF_CHECK_I(double_wide);
11787
11788         PIPE_CONF_CHECK_P(shared_dpll);
11789         PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11790         PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11791         PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11792         PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11793         PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11794         PIPE_CONF_CHECK_X(dpll_hw_state.spll);
11795         PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11796         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11797         PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11798
11799         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11800         PIPE_CONF_CHECK_X(dsi_pll.div);
11801
11802         if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
11803                 PIPE_CONF_CHECK_I(pipe_bpp);
11804
11805         PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11806         PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11807
11808 #undef PIPE_CONF_CHECK_X
11809 #undef PIPE_CONF_CHECK_I
11810 #undef PIPE_CONF_CHECK_P
11811 #undef PIPE_CONF_CHECK_FLAGS
11812 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11813 #undef PIPE_CONF_QUIRK
11814
11815         return ret;
11816 }
11817
11818 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11819                                            const struct intel_crtc_state *pipe_config)
11820 {
11821         if (pipe_config->has_pch_encoder) {
11822                 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11823                                                             &pipe_config->fdi_m_n);
11824                 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11825
11826                 /*
11827                  * FDI already provided one idea for the dotclock.
11828                  * Yell if the encoder disagrees.
11829                  */
11830                 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11831                      "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11832                      fdi_dotclock, dotclock);
11833         }
11834 }
11835
11836 static void verify_wm_state(struct drm_crtc *crtc,
11837                             struct drm_crtc_state *new_state)
11838 {
11839         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
11840         struct skl_ddb_allocation hw_ddb, *sw_ddb;
11841         struct skl_pipe_wm hw_wm, *sw_wm;
11842         struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11843         struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
11844         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11845         const enum pipe pipe = intel_crtc->pipe;
11846         int plane, level, max_level = ilk_wm_max_level(dev_priv);
11847
11848         if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
11849                 return;
11850
11851         skl_pipe_wm_get_hw_state(crtc, &hw_wm);
11852         sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
11853
11854         skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11855         sw_ddb = &dev_priv->wm.skl_hw.ddb;
11856
11857         /* planes */
11858         for_each_universal_plane(dev_priv, pipe, plane) {
11859                 hw_plane_wm = &hw_wm.planes[plane];
11860                 sw_plane_wm = &sw_wm->planes[plane];
11861
11862                 /* Watermarks */
11863                 for (level = 0; level <= max_level; level++) {
11864                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11865                                                 &sw_plane_wm->wm[level]))
11866                                 continue;
11867
11868                         DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11869                                   pipe_name(pipe), plane + 1, level,
11870                                   sw_plane_wm->wm[level].plane_en,
11871                                   sw_plane_wm->wm[level].plane_res_b,
11872                                   sw_plane_wm->wm[level].plane_res_l,
11873                                   hw_plane_wm->wm[level].plane_en,
11874                                   hw_plane_wm->wm[level].plane_res_b,
11875                                   hw_plane_wm->wm[level].plane_res_l);
11876                 }
11877
11878                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11879                                          &sw_plane_wm->trans_wm)) {
11880                         DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11881                                   pipe_name(pipe), plane + 1,
11882                                   sw_plane_wm->trans_wm.plane_en,
11883                                   sw_plane_wm->trans_wm.plane_res_b,
11884                                   sw_plane_wm->trans_wm.plane_res_l,
11885                                   hw_plane_wm->trans_wm.plane_en,
11886                                   hw_plane_wm->trans_wm.plane_res_b,
11887                                   hw_plane_wm->trans_wm.plane_res_l);
11888                 }
11889
11890                 /* DDB */
11891                 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11892                 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11893
11894                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11895                         DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
11896                                   pipe_name(pipe), plane + 1,
11897                                   sw_ddb_entry->start, sw_ddb_entry->end,
11898                                   hw_ddb_entry->start, hw_ddb_entry->end);
11899                 }
11900         }
11901
11902         /*
11903          * cursor
11904          * If the cursor plane isn't active, we may not have updated it's ddb
11905          * allocation. In that case since the ddb allocation will be updated
11906          * once the plane becomes visible, we can skip this check
11907          */
11908         if (intel_crtc->cursor_addr) {
11909                 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11910                 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11911
11912                 /* Watermarks */
11913                 for (level = 0; level <= max_level; level++) {
11914                         if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11915                                                 &sw_plane_wm->wm[level]))
11916                                 continue;
11917
11918                         DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11919                                   pipe_name(pipe), level,
11920                                   sw_plane_wm->wm[level].plane_en,
11921                                   sw_plane_wm->wm[level].plane_res_b,
11922                                   sw_plane_wm->wm[level].plane_res_l,
11923                                   hw_plane_wm->wm[level].plane_en,
11924                                   hw_plane_wm->wm[level].plane_res_b,
11925                                   hw_plane_wm->wm[level].plane_res_l);
11926                 }
11927
11928                 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11929                                          &sw_plane_wm->trans_wm)) {
11930                         DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11931                                   pipe_name(pipe),
11932                                   sw_plane_wm->trans_wm.plane_en,
11933                                   sw_plane_wm->trans_wm.plane_res_b,
11934                                   sw_plane_wm->trans_wm.plane_res_l,
11935                                   hw_plane_wm->trans_wm.plane_en,
11936                                   hw_plane_wm->trans_wm.plane_res_b,
11937                                   hw_plane_wm->trans_wm.plane_res_l);
11938                 }
11939
11940                 /* DDB */
11941                 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11942                 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
11943
11944                 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
11945                         DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
11946                                   pipe_name(pipe),
11947                                   sw_ddb_entry->start, sw_ddb_entry->end,
11948                                   hw_ddb_entry->start, hw_ddb_entry->end);
11949                 }
11950         }
11951 }
11952
11953 static void
11954 verify_connector_state(struct drm_device *dev,
11955                        struct drm_atomic_state *state,
11956                        struct drm_crtc *crtc)
11957 {
11958         struct drm_connector *connector;
11959         struct drm_connector_state *new_conn_state;
11960         int i;
11961
11962         for_each_new_connector_in_state(state, connector, new_conn_state, i) {
11963                 struct drm_encoder *encoder = connector->encoder;
11964
11965                 if (new_conn_state->crtc != crtc)
11966                         continue;
11967
11968                 intel_connector_verify_state(to_intel_connector(connector));
11969
11970                 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
11971                      "connector's atomic encoder doesn't match legacy encoder\n");
11972         }
11973 }
11974
11975 static void
11976 verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
11977 {
11978         struct intel_encoder *encoder;
11979         struct drm_connector *connector;
11980         struct drm_connector_state *old_conn_state, *new_conn_state;
11981         int i;
11982
11983         for_each_intel_encoder(dev, encoder) {
11984                 bool enabled = false, found = false;
11985                 enum pipe pipe;
11986
11987                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11988                               encoder->base.base.id,
11989                               encoder->base.name);
11990
11991                 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11992                                                    new_conn_state, i) {
11993                         if (old_conn_state->best_encoder == &encoder->base)
11994                                 found = true;
11995
11996                         if (new_conn_state->best_encoder != &encoder->base)
11997                                 continue;
11998                         found = enabled = true;
11999
12000                         I915_STATE_WARN(new_conn_state->crtc !=
12001                                         encoder->base.crtc,
12002                              "connector's crtc doesn't match encoder crtc\n");
12003                 }
12004
12005                 if (!found)
12006                         continue;
12007
12008                 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12009                      "encoder's enabled state mismatch "
12010                      "(expected %i, found %i)\n",
12011                      !!encoder->base.crtc, enabled);
12012
12013                 if (!encoder->base.crtc) {
12014                         bool active;
12015
12016                         active = encoder->get_hw_state(encoder, &pipe);
12017                         I915_STATE_WARN(active,
12018                              "encoder detached but still enabled on pipe %c.\n",
12019                              pipe_name(pipe));
12020                 }
12021         }
12022 }
12023
12024 static void
12025 verify_crtc_state(struct drm_crtc *crtc,
12026                   struct drm_crtc_state *old_crtc_state,
12027                   struct drm_crtc_state *new_crtc_state)
12028 {
12029         struct drm_device *dev = crtc->dev;
12030         struct drm_i915_private *dev_priv = to_i915(dev);
12031         struct intel_encoder *encoder;
12032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12033         struct intel_crtc_state *pipe_config, *sw_config;
12034         struct drm_atomic_state *old_state;
12035         bool active;
12036
12037         old_state = old_crtc_state->state;
12038         __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
12039         pipe_config = to_intel_crtc_state(old_crtc_state);
12040         memset(pipe_config, 0, sizeof(*pipe_config));
12041         pipe_config->base.crtc = crtc;
12042         pipe_config->base.state = old_state;
12043
12044         DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
12045
12046         active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
12047
12048         /* hw state is inconsistent with the pipe quirk */
12049         if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12050             (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12051                 active = new_crtc_state->active;
12052
12053         I915_STATE_WARN(new_crtc_state->active != active,
12054              "crtc active state doesn't match with hw state "
12055              "(expected %i, found %i)\n", new_crtc_state->active, active);
12056
12057         I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12058              "transitional active state does not match atomic hw state "
12059              "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
12060
12061         for_each_encoder_on_crtc(dev, crtc, encoder) {
12062                 enum pipe pipe;
12063
12064                 active = encoder->get_hw_state(encoder, &pipe);
12065                 I915_STATE_WARN(active != new_crtc_state->active,
12066                         "[ENCODER:%i] active %i with crtc active %i\n",
12067                         encoder->base.base.id, active, new_crtc_state->active);
12068
12069                 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12070                                 "Encoder connected to wrong pipe %c\n",
12071                                 pipe_name(pipe));
12072
12073                 if (active) {
12074                         pipe_config->output_types |= 1 << encoder->type;
12075                         encoder->get_config(encoder, pipe_config);
12076                 }
12077         }
12078
12079         intel_crtc_compute_pixel_rate(pipe_config);
12080
12081         if (!new_crtc_state->active)
12082                 return;
12083
12084         intel_pipe_config_sanity_check(dev_priv, pipe_config);
12085
12086         sw_config = to_intel_crtc_state(crtc->state);
12087         if (!intel_pipe_config_compare(dev_priv, sw_config,
12088                                        pipe_config, false)) {
12089                 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12090                 intel_dump_pipe_config(intel_crtc, pipe_config,
12091                                        "[hw state]");
12092                 intel_dump_pipe_config(intel_crtc, sw_config,
12093                                        "[sw state]");
12094         }
12095 }
12096
12097 static void
12098 verify_single_dpll_state(struct drm_i915_private *dev_priv,
12099                          struct intel_shared_dpll *pll,
12100                          struct drm_crtc *crtc,
12101                          struct drm_crtc_state *new_state)
12102 {
12103         struct intel_dpll_hw_state dpll_hw_state;
12104         unsigned crtc_mask;
12105         bool active;
12106
12107         memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12108
12109         DRM_DEBUG_KMS("%s\n", pll->name);
12110
12111         active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12112
12113         if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12114                 I915_STATE_WARN(!pll->on && pll->active_mask,
12115                      "pll in active use but not on in sw tracking\n");
12116                 I915_STATE_WARN(pll->on && !pll->active_mask,
12117                      "pll is on but not used by any active crtc\n");
12118                 I915_STATE_WARN(pll->on != active,
12119                      "pll on state mismatch (expected %i, found %i)\n",
12120                      pll->on, active);
12121         }
12122
12123         if (!crtc) {
12124                 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
12125                                 "more active pll users than references: %x vs %x\n",
12126                                 pll->active_mask, pll->state.crtc_mask);
12127
12128                 return;
12129         }
12130
12131         crtc_mask = 1 << drm_crtc_index(crtc);
12132
12133         if (new_state->active)
12134                 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12135                                 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12136                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12137         else
12138                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12139                                 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12140                                 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12141
12142         I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
12143                         "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
12144                         crtc_mask, pll->state.crtc_mask);
12145
12146         I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
12147                                           &dpll_hw_state,
12148                                           sizeof(dpll_hw_state)),
12149                         "pll hw state mismatch\n");
12150 }
12151
12152 static void
12153 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12154                          struct drm_crtc_state *old_crtc_state,
12155                          struct drm_crtc_state *new_crtc_state)
12156 {
12157         struct drm_i915_private *dev_priv = to_i915(dev);
12158         struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12159         struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12160
12161         if (new_state->shared_dpll)
12162                 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
12163
12164         if (old_state->shared_dpll &&
12165             old_state->shared_dpll != new_state->shared_dpll) {
12166                 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12167                 struct intel_shared_dpll *pll = old_state->shared_dpll;
12168
12169                 I915_STATE_WARN(pll->active_mask & crtc_mask,
12170                                 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12171                                 pipe_name(drm_crtc_index(crtc)));
12172                 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
12173                                 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12174                                 pipe_name(drm_crtc_index(crtc)));
12175         }
12176 }
12177
12178 static void
12179 intel_modeset_verify_crtc(struct drm_crtc *crtc,
12180                           struct drm_atomic_state *state,
12181                           struct drm_crtc_state *old_state,
12182                           struct drm_crtc_state *new_state)
12183 {
12184         if (!needs_modeset(new_state) &&
12185             !to_intel_crtc_state(new_state)->update_pipe)
12186                 return;
12187
12188         verify_wm_state(crtc, new_state);
12189         verify_connector_state(crtc->dev, state, crtc);
12190         verify_crtc_state(crtc, old_state, new_state);
12191         verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
12192 }
12193
12194 static void
12195 verify_disabled_dpll_state(struct drm_device *dev)
12196 {
12197         struct drm_i915_private *dev_priv = to_i915(dev);
12198         int i;
12199
12200         for (i = 0; i < dev_priv->num_shared_dpll; i++)
12201                 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
12202 }
12203
12204 static void
12205 intel_modeset_verify_disabled(struct drm_device *dev,
12206                               struct drm_atomic_state *state)
12207 {
12208         verify_encoder_state(dev, state);
12209         verify_connector_state(dev, state, NULL);
12210         verify_disabled_dpll_state(dev);
12211 }
12212
12213 static void update_scanline_offset(struct intel_crtc *crtc)
12214 {
12215         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12216
12217         /*
12218          * The scanline counter increments at the leading edge of hsync.
12219          *
12220          * On most platforms it starts counting from vtotal-1 on the
12221          * first active line. That means the scanline counter value is
12222          * always one less than what we would expect. Ie. just after
12223          * start of vblank, which also occurs at start of hsync (on the
12224          * last active line), the scanline counter will read vblank_start-1.
12225          *
12226          * On gen2 the scanline counter starts counting from 1 instead
12227          * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12228          * to keep the value positive), instead of adding one.
12229          *
12230          * On HSW+ the behaviour of the scanline counter depends on the output
12231          * type. For DP ports it behaves like most other platforms, but on HDMI
12232          * there's an extra 1 line difference. So we need to add two instead of
12233          * one to the value.
12234          */
12235         if (IS_GEN2(dev_priv)) {
12236                 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12237                 int vtotal;
12238
12239                 vtotal = adjusted_mode->crtc_vtotal;
12240                 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12241                         vtotal /= 2;
12242
12243                 crtc->scanline_offset = vtotal - 1;
12244         } else if (HAS_DDI(dev_priv) &&
12245                    intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
12246                 crtc->scanline_offset = 2;
12247         } else
12248                 crtc->scanline_offset = 1;
12249 }
12250
12251 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12252 {
12253         struct drm_device *dev = state->dev;
12254         struct drm_i915_private *dev_priv = to_i915(dev);
12255         struct drm_crtc *crtc;
12256         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12257         int i;
12258
12259         if (!dev_priv->display.crtc_compute_clock)
12260                 return;
12261
12262         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12263                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12264                 struct intel_shared_dpll *old_dpll =
12265                         to_intel_crtc_state(old_crtc_state)->shared_dpll;
12266
12267                 if (!needs_modeset(new_crtc_state))
12268                         continue;
12269
12270                 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
12271
12272                 if (!old_dpll)
12273                         continue;
12274
12275                 intel_release_shared_dpll(old_dpll, intel_crtc, state);
12276         }
12277 }
12278
12279 /*
12280  * This implements the workaround described in the "notes" section of the mode
12281  * set sequence documentation. When going from no pipes or single pipe to
12282  * multiple pipes, and planes are enabled after the pipe, we need to wait at
12283  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12284  */
12285 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12286 {
12287         struct drm_crtc_state *crtc_state;
12288         struct intel_crtc *intel_crtc;
12289         struct drm_crtc *crtc;
12290         struct intel_crtc_state *first_crtc_state = NULL;
12291         struct intel_crtc_state *other_crtc_state = NULL;
12292         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12293         int i;
12294
12295         /* look at all crtc's that are going to be enabled in during modeset */
12296         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12297                 intel_crtc = to_intel_crtc(crtc);
12298
12299                 if (!crtc_state->active || !needs_modeset(crtc_state))
12300                         continue;
12301
12302                 if (first_crtc_state) {
12303                         other_crtc_state = to_intel_crtc_state(crtc_state);
12304                         break;
12305                 } else {
12306                         first_crtc_state = to_intel_crtc_state(crtc_state);
12307                         first_pipe = intel_crtc->pipe;
12308                 }
12309         }
12310
12311         /* No workaround needed? */
12312         if (!first_crtc_state)
12313                 return 0;
12314
12315         /* w/a possibly needed, check how many crtc's are already enabled. */
12316         for_each_intel_crtc(state->dev, intel_crtc) {
12317                 struct intel_crtc_state *pipe_config;
12318
12319                 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12320                 if (IS_ERR(pipe_config))
12321                         return PTR_ERR(pipe_config);
12322
12323                 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12324
12325                 if (!pipe_config->base.active ||
12326                     needs_modeset(&pipe_config->base))
12327                         continue;
12328
12329                 /* 2 or more enabled crtcs means no need for w/a */
12330                 if (enabled_pipe != INVALID_PIPE)
12331                         return 0;
12332
12333                 enabled_pipe = intel_crtc->pipe;
12334         }
12335
12336         if (enabled_pipe != INVALID_PIPE)
12337                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12338         else if (other_crtc_state)
12339                 other_crtc_state->hsw_workaround_pipe = first_pipe;
12340
12341         return 0;
12342 }
12343
12344 static int intel_lock_all_pipes(struct drm_atomic_state *state)
12345 {
12346         struct drm_crtc *crtc;
12347
12348         /* Add all pipes to the state */
12349         for_each_crtc(state->dev, crtc) {
12350                 struct drm_crtc_state *crtc_state;
12351
12352                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12353                 if (IS_ERR(crtc_state))
12354                         return PTR_ERR(crtc_state);
12355         }
12356
12357         return 0;
12358 }
12359
12360 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12361 {
12362         struct drm_crtc *crtc;
12363
12364         /*
12365          * Add all pipes to the state, and force
12366          * a modeset on all the active ones.
12367          */
12368         for_each_crtc(state->dev, crtc) {
12369                 struct drm_crtc_state *crtc_state;
12370                 int ret;
12371
12372                 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12373                 if (IS_ERR(crtc_state))
12374                         return PTR_ERR(crtc_state);
12375
12376                 if (!crtc_state->active || needs_modeset(crtc_state))
12377                         continue;
12378
12379                 crtc_state->mode_changed = true;
12380
12381                 ret = drm_atomic_add_affected_connectors(state, crtc);
12382                 if (ret)
12383                         return ret;
12384
12385                 ret = drm_atomic_add_affected_planes(state, crtc);
12386                 if (ret)
12387                         return ret;
12388         }
12389
12390         return 0;
12391 }
12392
12393 static int intel_modeset_checks(struct drm_atomic_state *state)
12394 {
12395         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12396         struct drm_i915_private *dev_priv = to_i915(state->dev);
12397         struct drm_crtc *crtc;
12398         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12399         int ret = 0, i;
12400
12401         if (!check_digital_port_conflicts(state)) {
12402                 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12403                 return -EINVAL;
12404         }
12405
12406         intel_state->modeset = true;
12407         intel_state->active_crtcs = dev_priv->active_crtcs;
12408         intel_state->cdclk.logical = dev_priv->cdclk.logical;
12409         intel_state->cdclk.actual = dev_priv->cdclk.actual;
12410
12411         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12412                 if (new_crtc_state->active)
12413                         intel_state->active_crtcs |= 1 << i;
12414                 else
12415                         intel_state->active_crtcs &= ~(1 << i);
12416
12417                 if (old_crtc_state->active != new_crtc_state->active)
12418                         intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
12419         }
12420
12421         /*
12422          * See if the config requires any additional preparation, e.g.
12423          * to adjust global state with pipes off.  We need to do this
12424          * here so we can get the modeset_pipe updated config for the new
12425          * mode set on this crtc.  For other crtcs we need to use the
12426          * adjusted_mode bits in the crtc directly.
12427          */
12428         if (dev_priv->display.modeset_calc_cdclk) {
12429                 ret = dev_priv->display.modeset_calc_cdclk(state);
12430                 if (ret < 0)
12431                         return ret;
12432
12433                 /*
12434                  * Writes to dev_priv->cdclk.logical must protected by
12435                  * holding all the crtc locks, even if we don't end up
12436                  * touching the hardware
12437                  */
12438                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12439                                                &intel_state->cdclk.logical)) {
12440                         ret = intel_lock_all_pipes(state);
12441                         if (ret < 0)
12442                                 return ret;
12443                 }
12444
12445                 /* All pipes must be switched off while we change the cdclk. */
12446                 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12447                                                &intel_state->cdclk.actual)) {
12448                         ret = intel_modeset_all_pipes(state);
12449                         if (ret < 0)
12450                                 return ret;
12451                 }
12452
12453                 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12454                               intel_state->cdclk.logical.cdclk,
12455                               intel_state->cdclk.actual.cdclk);
12456         } else {
12457                 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
12458         }
12459
12460         intel_modeset_clear_plls(state);
12461
12462         if (IS_HASWELL(dev_priv))
12463                 return haswell_mode_set_planes_workaround(state);
12464
12465         return 0;
12466 }
12467
12468 /*
12469  * Handle calculation of various watermark data at the end of the atomic check
12470  * phase.  The code here should be run after the per-crtc and per-plane 'check'
12471  * handlers to ensure that all derived state has been updated.
12472  */
12473 static int calc_watermark_data(struct drm_atomic_state *state)
12474 {
12475         struct drm_device *dev = state->dev;
12476         struct drm_i915_private *dev_priv = to_i915(dev);
12477
12478         /* Is there platform-specific watermark information to calculate? */
12479         if (dev_priv->display.compute_global_watermarks)
12480                 return dev_priv->display.compute_global_watermarks(state);
12481
12482         return 0;
12483 }
12484
12485 /**
12486  * intel_atomic_check - validate state object
12487  * @dev: drm device
12488  * @state: state to validate
12489  */
12490 static int intel_atomic_check(struct drm_device *dev,
12491                               struct drm_atomic_state *state)
12492 {
12493         struct drm_i915_private *dev_priv = to_i915(dev);
12494         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12495         struct drm_crtc *crtc;
12496         struct drm_crtc_state *old_crtc_state, *crtc_state;
12497         int ret, i;
12498         bool any_ms = false;
12499
12500         ret = drm_atomic_helper_check_modeset(dev, state);
12501         if (ret)
12502                 return ret;
12503
12504         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
12505                 struct intel_crtc_state *pipe_config =
12506                         to_intel_crtc_state(crtc_state);
12507
12508                 /* Catch I915_MODE_FLAG_INHERITED */
12509                 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
12510                         crtc_state->mode_changed = true;
12511
12512                 if (!needs_modeset(crtc_state))
12513                         continue;
12514
12515                 if (!crtc_state->enable) {
12516                         any_ms = true;
12517                         continue;
12518                 }
12519
12520                 /* FIXME: For only active_changed we shouldn't need to do any
12521                  * state recomputation at all. */
12522
12523                 ret = drm_atomic_add_affected_connectors(state, crtc);
12524                 if (ret)
12525                         return ret;
12526
12527                 ret = intel_modeset_pipe_config(crtc, pipe_config);
12528                 if (ret) {
12529                         intel_dump_pipe_config(to_intel_crtc(crtc),
12530                                                pipe_config, "[failed]");
12531                         return ret;
12532                 }
12533
12534                 if (i915.fastboot &&
12535                     intel_pipe_config_compare(dev_priv,
12536                                         to_intel_crtc_state(old_crtc_state),
12537                                         pipe_config, true)) {
12538                         crtc_state->mode_changed = false;
12539                         pipe_config->update_pipe = true;
12540                 }
12541
12542                 if (needs_modeset(crtc_state))
12543                         any_ms = true;
12544
12545                 ret = drm_atomic_add_affected_planes(state, crtc);
12546                 if (ret)
12547                         return ret;
12548
12549                 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12550                                        needs_modeset(crtc_state) ?
12551                                        "[modeset]" : "[fastset]");
12552         }
12553
12554         if (any_ms) {
12555                 ret = intel_modeset_checks(state);
12556
12557                 if (ret)
12558                         return ret;
12559         } else {
12560                 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12561         }
12562
12563         ret = drm_atomic_helper_check_planes(dev, state);
12564         if (ret)
12565                 return ret;
12566
12567         intel_fbc_choose_crtc(dev_priv, state);
12568         return calc_watermark_data(state);
12569 }
12570
12571 static int intel_atomic_prepare_commit(struct drm_device *dev,
12572                                        struct drm_atomic_state *state)
12573 {
12574         struct drm_i915_private *dev_priv = to_i915(dev);
12575         struct drm_crtc_state *crtc_state;
12576         struct drm_crtc *crtc;
12577         int i, ret;
12578
12579         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
12580                 if (state->legacy_cursor_update)
12581                         continue;
12582
12583                 ret = intel_crtc_wait_for_pending_flips(crtc);
12584                 if (ret)
12585                         return ret;
12586
12587                 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12588                         flush_workqueue(dev_priv->wq);
12589         }
12590
12591         ret = mutex_lock_interruptible(&dev->struct_mutex);
12592         if (ret)
12593                 return ret;
12594
12595         ret = drm_atomic_helper_prepare_planes(dev, state);
12596         mutex_unlock(&dev->struct_mutex);
12597
12598         return ret;
12599 }
12600
12601 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12602 {
12603         struct drm_device *dev = crtc->base.dev;
12604
12605         if (!dev->max_vblank_count)
12606                 return drm_accurate_vblank_count(&crtc->base);
12607
12608         return dev->driver->get_vblank_counter(dev, crtc->pipe);
12609 }
12610
12611 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12612                                           struct drm_i915_private *dev_priv,
12613                                           unsigned crtc_mask)
12614 {
12615         unsigned last_vblank_count[I915_MAX_PIPES];
12616         enum pipe pipe;
12617         int ret;
12618
12619         if (!crtc_mask)
12620                 return;
12621
12622         for_each_pipe(dev_priv, pipe) {
12623                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12624                                                                   pipe);
12625
12626                 if (!((1 << pipe) & crtc_mask))
12627                         continue;
12628
12629                 ret = drm_crtc_vblank_get(&crtc->base);
12630                 if (WARN_ON(ret != 0)) {
12631                         crtc_mask &= ~(1 << pipe);
12632                         continue;
12633                 }
12634
12635                 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
12636         }
12637
12638         for_each_pipe(dev_priv, pipe) {
12639                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12640                                                                   pipe);
12641                 long lret;
12642
12643                 if (!((1 << pipe) & crtc_mask))
12644                         continue;
12645
12646                 lret = wait_event_timeout(dev->vblank[pipe].queue,
12647                                 last_vblank_count[pipe] !=
12648                                         drm_crtc_vblank_count(&crtc->base),
12649                                 msecs_to_jiffies(50));
12650
12651                 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
12652
12653                 drm_crtc_vblank_put(&crtc->base);
12654         }
12655 }
12656
12657 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
12658 {
12659         /* fb updated, need to unpin old fb */
12660         if (crtc_state->fb_changed)
12661                 return true;
12662
12663         /* wm changes, need vblank before final wm's */
12664         if (crtc_state->update_wm_post)
12665                 return true;
12666
12667         if (crtc_state->wm.need_postvbl_update)
12668                 return true;
12669
12670         return false;
12671 }
12672
12673 static void intel_update_crtc(struct drm_crtc *crtc,
12674                               struct drm_atomic_state *state,
12675                               struct drm_crtc_state *old_crtc_state,
12676                               struct drm_crtc_state *new_crtc_state,
12677                               unsigned int *crtc_vblank_mask)
12678 {
12679         struct drm_device *dev = crtc->dev;
12680         struct drm_i915_private *dev_priv = to_i915(dev);
12681         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12682         struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12683         bool modeset = needs_modeset(new_crtc_state);
12684
12685         if (modeset) {
12686                 update_scanline_offset(intel_crtc);
12687                 dev_priv->display.crtc_enable(pipe_config, state);
12688         } else {
12689                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12690                                        pipe_config);
12691         }
12692
12693         if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12694                 intel_fbc_enable(
12695                     intel_crtc, pipe_config,
12696                     to_intel_plane_state(crtc->primary->state));
12697         }
12698
12699         drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12700
12701         if (needs_vblank_wait(pipe_config))
12702                 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12703 }
12704
12705 static void intel_update_crtcs(struct drm_atomic_state *state,
12706                                unsigned int *crtc_vblank_mask)
12707 {
12708         struct drm_crtc *crtc;
12709         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12710         int i;
12711
12712         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12713                 if (!new_crtc_state->active)
12714                         continue;
12715
12716                 intel_update_crtc(crtc, state, old_crtc_state,
12717                                   new_crtc_state, crtc_vblank_mask);
12718         }
12719 }
12720
12721 static void skl_update_crtcs(struct drm_atomic_state *state,
12722                              unsigned int *crtc_vblank_mask)
12723 {
12724         struct drm_i915_private *dev_priv = to_i915(state->dev);
12725         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12726         struct drm_crtc *crtc;
12727         struct intel_crtc *intel_crtc;
12728         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12729         struct intel_crtc_state *cstate;
12730         unsigned int updated = 0;
12731         bool progress;
12732         enum pipe pipe;
12733         int i;
12734
12735         const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12736
12737         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
12738                 /* ignore allocations for crtc's that have been turned off. */
12739                 if (new_crtc_state->active)
12740                         entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
12741
12742         /*
12743          * Whenever the number of active pipes changes, we need to make sure we
12744          * update the pipes in the right order so that their ddb allocations
12745          * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12746          * cause pipe underruns and other bad stuff.
12747          */
12748         do {
12749                 progress = false;
12750
12751                 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12752                         bool vbl_wait = false;
12753                         unsigned int cmask = drm_crtc_mask(crtc);
12754
12755                         intel_crtc = to_intel_crtc(crtc);
12756                         cstate = to_intel_crtc_state(crtc->state);
12757                         pipe = intel_crtc->pipe;
12758
12759                         if (updated & cmask || !cstate->base.active)
12760                                 continue;
12761
12762                         if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
12763                                 continue;
12764
12765                         updated |= cmask;
12766                         entries[i] = &cstate->wm.skl.ddb;
12767
12768                         /*
12769                          * If this is an already active pipe, it's DDB changed,
12770                          * and this isn't the last pipe that needs updating
12771                          * then we need to wait for a vblank to pass for the
12772                          * new ddb allocation to take effect.
12773                          */
12774                         if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
12775                                                  &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
12776                             !new_crtc_state->active_changed &&
12777                             intel_state->wm_results.dirty_pipes != updated)
12778                                 vbl_wait = true;
12779
12780                         intel_update_crtc(crtc, state, old_crtc_state,
12781                                           new_crtc_state, crtc_vblank_mask);
12782
12783                         if (vbl_wait)
12784                                 intel_wait_for_vblank(dev_priv, pipe);
12785
12786                         progress = true;
12787                 }
12788         } while (progress);
12789 }
12790
12791 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12792 {
12793         struct intel_atomic_state *state, *next;
12794         struct llist_node *freed;
12795
12796         freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12797         llist_for_each_entry_safe(state, next, freed, freed)
12798                 drm_atomic_state_put(&state->base);
12799 }
12800
12801 static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12802 {
12803         struct drm_i915_private *dev_priv =
12804                 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12805
12806         intel_atomic_helper_free_state(dev_priv);
12807 }
12808
12809 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
12810 {
12811         struct drm_device *dev = state->dev;
12812         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12813         struct drm_i915_private *dev_priv = to_i915(dev);
12814         struct drm_crtc_state *old_crtc_state, *new_crtc_state;
12815         struct drm_crtc *crtc;
12816         struct intel_crtc_state *intel_cstate;
12817         bool hw_check = intel_state->modeset;
12818         u64 put_domains[I915_MAX_PIPES] = {};
12819         unsigned crtc_vblank_mask = 0;
12820         int i;
12821
12822         drm_atomic_helper_wait_for_dependencies(state);
12823
12824         if (intel_state->modeset)
12825                 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
12826
12827         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12828                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12829
12830                 if (needs_modeset(new_crtc_state) ||
12831                     to_intel_crtc_state(new_crtc_state)->update_pipe) {
12832                         hw_check = true;
12833
12834                         put_domains[to_intel_crtc(crtc)->pipe] =
12835                                 modeset_get_crtc_power_domains(crtc,
12836                                         to_intel_crtc_state(new_crtc_state));
12837                 }
12838
12839                 if (!needs_modeset(new_crtc_state))
12840                         continue;
12841
12842                 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12843                                        to_intel_crtc_state(new_crtc_state));
12844
12845                 if (old_crtc_state->active) {
12846                         intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
12847                         dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
12848                         intel_crtc->active = false;
12849                         intel_fbc_disable(intel_crtc);
12850                         intel_disable_shared_dpll(intel_crtc);
12851
12852                         /*
12853                          * Underruns don't always raise
12854                          * interrupts, so check manually.
12855                          */
12856                         intel_check_cpu_fifo_underruns(dev_priv);
12857                         intel_check_pch_fifo_underruns(dev_priv);
12858
12859                         if (!crtc->state->active) {
12860                                 /*
12861                                  * Make sure we don't call initial_watermarks
12862                                  * for ILK-style watermark updates.
12863                                  *
12864                                  * No clue what this is supposed to achieve.
12865                                  */
12866                                 if (INTEL_GEN(dev_priv) >= 9)
12867                                         dev_priv->display.initial_watermarks(intel_state,
12868                                                                              to_intel_crtc_state(crtc->state));
12869                         }
12870                 }
12871         }
12872
12873         /* Only after disabling all output pipelines that will be changed can we
12874          * update the the output configuration. */
12875         intel_modeset_update_crtc_state(state);
12876
12877         if (intel_state->modeset) {
12878                 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
12879
12880                 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
12881
12882                 /*
12883                  * SKL workaround: bspec recommends we disable the SAGV when we
12884                  * have more then one pipe enabled
12885                  */
12886                 if (!intel_can_enable_sagv(state))
12887                         intel_disable_sagv(dev_priv);
12888
12889                 intel_modeset_verify_disabled(dev, state);
12890         }
12891
12892         /* Complete the events for pipes that have now been disabled */
12893         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12894                 bool modeset = needs_modeset(new_crtc_state);
12895
12896                 /* Complete events for now disable pipes here. */
12897                 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
12898                         spin_lock_irq(&dev->event_lock);
12899                         drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
12900                         spin_unlock_irq(&dev->event_lock);
12901
12902                         new_crtc_state->event = NULL;
12903                 }
12904         }
12905
12906         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12907         dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12908
12909         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12910          * already, but still need the state for the delayed optimization. To
12911          * fix this:
12912          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12913          * - schedule that vblank worker _before_ calling hw_done
12914          * - at the start of commit_tail, cancel it _synchrously
12915          * - switch over to the vblank wait helper in the core after that since
12916          *   we don't need out special handling any more.
12917          */
12918         if (!state->legacy_cursor_update)
12919                 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12920
12921         /*
12922          * Now that the vblank has passed, we can go ahead and program the
12923          * optimal watermarks on platforms that need two-step watermark
12924          * programming.
12925          *
12926          * TODO: Move this (and other cleanup) to an async worker eventually.
12927          */
12928         for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12929                 intel_cstate = to_intel_crtc_state(new_crtc_state);
12930
12931                 if (dev_priv->display.optimize_watermarks)
12932                         dev_priv->display.optimize_watermarks(intel_state,
12933                                                               intel_cstate);
12934         }
12935
12936         for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12937                 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12938
12939                 if (put_domains[i])
12940                         modeset_put_power_domains(dev_priv, put_domains[i]);
12941
12942                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
12943         }
12944
12945         if (intel_state->modeset && intel_can_enable_sagv(state))
12946                 intel_enable_sagv(dev_priv);
12947
12948         drm_atomic_helper_commit_hw_done(state);
12949
12950         if (intel_state->modeset)
12951                 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12952
12953         mutex_lock(&dev->struct_mutex);
12954         drm_atomic_helper_cleanup_planes(dev, state);
12955         mutex_unlock(&dev->struct_mutex);
12956
12957         drm_atomic_helper_commit_cleanup_done(state);
12958
12959         drm_atomic_state_put(state);
12960
12961         /* As one of the primary mmio accessors, KMS has a high likelihood
12962          * of triggering bugs in unclaimed access. After we finish
12963          * modesetting, see if an error has been flagged, and if so
12964          * enable debugging for the next modeset - and hope we catch
12965          * the culprit.
12966          *
12967          * XXX note that we assume display power is on at this point.
12968          * This might hold true now but we need to add pm helper to check
12969          * unclaimed only when the hardware is on, as atomic commits
12970          * can happen also when the device is completely off.
12971          */
12972         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
12973
12974         intel_atomic_helper_free_state(dev_priv);
12975 }
12976
12977 static void intel_atomic_commit_work(struct work_struct *work)
12978 {
12979         struct drm_atomic_state *state =
12980                 container_of(work, struct drm_atomic_state, commit_work);
12981
12982         intel_atomic_commit_tail(state);
12983 }
12984
12985 static int __i915_sw_fence_call
12986 intel_atomic_commit_ready(struct i915_sw_fence *fence,
12987                           enum i915_sw_fence_notify notify)
12988 {
12989         struct intel_atomic_state *state =
12990                 container_of(fence, struct intel_atomic_state, commit_ready);
12991
12992         switch (notify) {
12993         case FENCE_COMPLETE:
12994                 if (state->base.commit_work.func)
12995                         queue_work(system_unbound_wq, &state->base.commit_work);
12996                 break;
12997
12998         case FENCE_FREE:
12999                 {
13000                         struct intel_atomic_helper *helper =
13001                                 &to_i915(state->base.dev)->atomic_helper;
13002
13003                         if (llist_add(&state->freed, &helper->free_list))
13004                                 schedule_work(&helper->free_work);
13005                         break;
13006                 }
13007         }
13008
13009         return NOTIFY_DONE;
13010 }
13011
13012 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
13013 {
13014         struct drm_plane_state *old_plane_state, *new_plane_state;
13015         struct drm_plane *plane;
13016         int i;
13017
13018         for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
13019                 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
13020                                   intel_fb_obj(new_plane_state->fb),
13021                                   to_intel_plane(plane)->frontbuffer_bit);
13022 }
13023
13024 /**
13025  * intel_atomic_commit - commit validated state object
13026  * @dev: DRM device
13027  * @state: the top-level driver state object
13028  * @nonblock: nonblocking commit
13029  *
13030  * This function commits a top-level state object that has been validated
13031  * with drm_atomic_helper_check().
13032  *
13033  * RETURNS
13034  * Zero for success or -errno.
13035  */
13036 static int intel_atomic_commit(struct drm_device *dev,
13037                                struct drm_atomic_state *state,
13038                                bool nonblock)
13039 {
13040         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13041         struct drm_i915_private *dev_priv = to_i915(dev);
13042         int ret = 0;
13043
13044         /*
13045          * The intel_legacy_cursor_update() fast path takes care
13046          * of avoiding the vblank waits for simple cursor
13047          * movement and flips. For cursor on/off and size changes,
13048          * we want to perform the vblank waits so that watermark
13049          * updates happen during the correct frames. Gen9+ have
13050          * double buffered watermarks and so shouldn't need this.
13051          */
13052         if (INTEL_GEN(dev_priv) < 9)
13053                 state->legacy_cursor_update = false;
13054
13055         ret = drm_atomic_helper_setup_commit(state, nonblock);
13056         if (ret)
13057                 return ret;
13058
13059         drm_atomic_state_get(state);
13060         i915_sw_fence_init(&intel_state->commit_ready,
13061                            intel_atomic_commit_ready);
13062
13063         ret = intel_atomic_prepare_commit(dev, state);
13064         if (ret) {
13065                 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13066                 i915_sw_fence_commit(&intel_state->commit_ready);
13067                 return ret;
13068         }
13069
13070         drm_atomic_helper_swap_state(state, true);
13071         dev_priv->wm.distrust_bios_wm = false;
13072         intel_shared_dpll_swap_state(state);
13073         intel_atomic_track_fbs(state);
13074
13075         if (intel_state->modeset) {
13076                 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13077                        sizeof(intel_state->min_pixclk));
13078                 dev_priv->active_crtcs = intel_state->active_crtcs;
13079                 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13080                 dev_priv->cdclk.actual = intel_state->cdclk.actual;
13081         }
13082
13083         drm_atomic_state_get(state);
13084         INIT_WORK(&state->commit_work,
13085                   nonblock ? intel_atomic_commit_work : NULL);
13086
13087         i915_sw_fence_commit(&intel_state->commit_ready);
13088         if (!nonblock) {
13089                 i915_sw_fence_wait(&intel_state->commit_ready);
13090                 intel_atomic_commit_tail(state);
13091         }
13092
13093         return 0;
13094 }
13095
13096 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13097 {
13098         struct drm_device *dev = crtc->dev;
13099         struct drm_atomic_state *state;
13100         struct drm_crtc_state *crtc_state;
13101         int ret;
13102
13103         state = drm_atomic_state_alloc(dev);
13104         if (!state) {
13105                 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13106                               crtc->base.id, crtc->name);
13107                 return;
13108         }
13109
13110         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13111
13112 retry:
13113         crtc_state = drm_atomic_get_crtc_state(state, crtc);
13114         ret = PTR_ERR_OR_ZERO(crtc_state);
13115         if (!ret) {
13116                 if (!crtc_state->active)
13117                         goto out;
13118
13119                 crtc_state->mode_changed = true;
13120                 ret = drm_atomic_commit(state);
13121         }
13122
13123         if (ret == -EDEADLK) {
13124                 drm_atomic_state_clear(state);
13125                 drm_modeset_backoff(state->acquire_ctx);
13126                 goto retry;
13127         }
13128
13129 out:
13130         drm_atomic_state_put(state);
13131 }
13132
13133 /*
13134  * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
13135  *        drm_atomic_helper_legacy_gamma_set() directly.
13136  */
13137 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
13138                                          u16 *red, u16 *green, u16 *blue,
13139                                          uint32_t size)
13140 {
13141         struct drm_device *dev = crtc->dev;
13142         struct drm_mode_config *config = &dev->mode_config;
13143         struct drm_crtc_state *state;
13144         int ret;
13145
13146         ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
13147         if (ret)
13148                 return ret;
13149
13150         /*
13151          * Make sure we update the legacy properties so this works when
13152          * atomic is not enabled.
13153          */
13154
13155         state = crtc->state;
13156
13157         drm_object_property_set_value(&crtc->base,
13158                                       config->degamma_lut_property,
13159                                       (state->degamma_lut) ?
13160                                       state->degamma_lut->base.id : 0);
13161
13162         drm_object_property_set_value(&crtc->base,
13163                                       config->ctm_property,
13164                                       (state->ctm) ?
13165                                       state->ctm->base.id : 0);
13166
13167         drm_object_property_set_value(&crtc->base,
13168                                       config->gamma_lut_property,
13169                                       (state->gamma_lut) ?
13170                                       state->gamma_lut->base.id : 0);
13171
13172         return 0;
13173 }
13174
13175 static const struct drm_crtc_funcs intel_crtc_funcs = {
13176         .gamma_set = intel_atomic_legacy_gamma_set,
13177         .set_config = drm_atomic_helper_set_config,
13178         .set_property = drm_atomic_helper_crtc_set_property,
13179         .destroy = intel_crtc_destroy,
13180         .page_flip = drm_atomic_helper_page_flip,
13181         .atomic_duplicate_state = intel_crtc_duplicate_state,
13182         .atomic_destroy_state = intel_crtc_destroy_state,
13183         .set_crc_source = intel_crtc_set_crc_source,
13184 };
13185
13186 /**
13187  * intel_prepare_plane_fb - Prepare fb for usage on plane
13188  * @plane: drm plane to prepare for
13189  * @fb: framebuffer to prepare for presentation
13190  *
13191  * Prepares a framebuffer for usage on a display plane.  Generally this
13192  * involves pinning the underlying object and updating the frontbuffer tracking
13193  * bits.  Some older platforms need special physical address handling for
13194  * cursor planes.
13195  *
13196  * Must be called with struct_mutex held.
13197  *
13198  * Returns 0 on success, negative error code on failure.
13199  */
13200 int
13201 intel_prepare_plane_fb(struct drm_plane *plane,
13202                        struct drm_plane_state *new_state)
13203 {
13204         struct intel_atomic_state *intel_state =
13205                 to_intel_atomic_state(new_state->state);
13206         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13207         struct drm_framebuffer *fb = new_state->fb;
13208         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13209         struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13210         int ret;
13211
13212         if (obj) {
13213                 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13214                     INTEL_INFO(dev_priv)->cursor_needs_physical) {
13215                         const int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13216
13217                         ret = i915_gem_object_attach_phys(obj, align);
13218                         if (ret) {
13219                                 DRM_DEBUG_KMS("failed to attach phys object\n");
13220                                 return ret;
13221                         }
13222                 } else {
13223                         struct i915_vma *vma;
13224
13225                         vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13226                         if (IS_ERR(vma)) {
13227                                 DRM_DEBUG_KMS("failed to pin object\n");
13228                                 return PTR_ERR(vma);
13229                         }
13230
13231                         to_intel_plane_state(new_state)->vma = vma;
13232                 }
13233         }
13234
13235         if (!obj && !old_obj)
13236                 return 0;
13237
13238         if (old_obj) {
13239                 struct drm_crtc_state *crtc_state =
13240                         drm_atomic_get_existing_crtc_state(new_state->state,
13241                                                            plane->state->crtc);
13242
13243                 /* Big Hammer, we also need to ensure that any pending
13244                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13245                  * current scanout is retired before unpinning the old
13246                  * framebuffer. Note that we rely on userspace rendering
13247                  * into the buffer attached to the pipe they are waiting
13248                  * on. If not, userspace generates a GPU hang with IPEHR
13249                  * point to the MI_WAIT_FOR_EVENT.
13250                  *
13251                  * This should only fail upon a hung GPU, in which case we
13252                  * can safely continue.
13253                  */
13254                 if (needs_modeset(crtc_state)) {
13255                         ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13256                                                               old_obj->resv, NULL,
13257                                                               false, 0,
13258                                                               GFP_KERNEL);
13259                         if (ret < 0)
13260                                 return ret;
13261                 }
13262         }
13263
13264         if (new_state->fence) { /* explicit fencing */
13265                 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13266                                                     new_state->fence,
13267                                                     I915_FENCE_TIMEOUT,
13268                                                     GFP_KERNEL);
13269                 if (ret < 0)
13270                         return ret;
13271         }
13272
13273         if (!obj)
13274                 return 0;
13275
13276         if (!new_state->fence) { /* implicit fencing */
13277                 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13278                                                       obj->resv, NULL,
13279                                                       false, I915_FENCE_TIMEOUT,
13280                                                       GFP_KERNEL);
13281                 if (ret < 0)
13282                         return ret;
13283
13284                 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
13285         }
13286
13287         return 0;
13288 }
13289
13290 /**
13291  * intel_cleanup_plane_fb - Cleans up an fb after plane use
13292  * @plane: drm plane to clean up for
13293  * @fb: old framebuffer that was on plane
13294  *
13295  * Cleans up a framebuffer that has just been removed from a plane.
13296  *
13297  * Must be called with struct_mutex held.
13298  */
13299 void
13300 intel_cleanup_plane_fb(struct drm_plane *plane,
13301                        struct drm_plane_state *old_state)
13302 {
13303         struct i915_vma *vma;
13304
13305         /* Should only be called after a successful intel_prepare_plane_fb()! */
13306         vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13307         if (vma)
13308                 intel_unpin_fb_vma(vma);
13309 }
13310
13311 int
13312 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13313 {
13314         struct drm_i915_private *dev_priv;
13315         int max_scale;
13316         int crtc_clock, max_dotclk;
13317
13318         if (!intel_crtc || !crtc_state->base.enable)
13319                 return DRM_PLANE_HELPER_NO_SCALING;
13320
13321         dev_priv = to_i915(intel_crtc->base.dev);
13322
13323         crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13324         max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13325
13326         if (IS_GEMINILAKE(dev_priv))
13327                 max_dotclk *= 2;
13328
13329         if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
13330                 return DRM_PLANE_HELPER_NO_SCALING;
13331
13332         /*
13333          * skl max scale is lower of:
13334          *    close to 3 but not 3, -1 is for that purpose
13335          *            or
13336          *    cdclk/crtc_clock
13337          */
13338         max_scale = min((1 << 16) * 3 - 1,
13339                         (1 << 8) * ((max_dotclk << 8) / crtc_clock));
13340
13341         return max_scale;
13342 }
13343
13344 static int
13345 intel_check_primary_plane(struct drm_plane *plane,
13346                           struct intel_crtc_state *crtc_state,
13347                           struct intel_plane_state *state)
13348 {
13349         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13350         struct drm_crtc *crtc = state->base.crtc;
13351         int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13352         int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13353         bool can_position = false;
13354         int ret;
13355
13356         if (INTEL_GEN(dev_priv) >= 9) {
13357                 /* use scaler when colorkey is not required */
13358                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13359                         min_scale = 1;
13360                         max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13361                 }
13362                 can_position = true;
13363         }
13364
13365         ret = drm_plane_helper_check_state(&state->base,
13366                                            &state->clip,
13367                                            min_scale, max_scale,
13368                                            can_position, true);
13369         if (ret)
13370                 return ret;
13371
13372         if (!state->base.fb)
13373                 return 0;
13374
13375         if (INTEL_GEN(dev_priv) >= 9) {
13376                 ret = skl_check_plane_surface(state);
13377                 if (ret)
13378                         return ret;
13379
13380                 state->ctl = skl_plane_ctl(crtc_state, state);
13381         } else {
13382                 ret = i9xx_check_plane_surface(state);
13383                 if (ret)
13384                         return ret;
13385
13386                 state->ctl = i9xx_plane_ctl(crtc_state, state);
13387         }
13388
13389         return 0;
13390 }
13391
13392 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13393                                     struct drm_crtc_state *old_crtc_state)
13394 {
13395         struct drm_device *dev = crtc->dev;
13396         struct drm_i915_private *dev_priv = to_i915(dev);
13397         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13398         struct intel_crtc_state *intel_cstate =
13399                 to_intel_crtc_state(crtc->state);
13400         struct intel_crtc_state *old_intel_cstate =
13401                 to_intel_crtc_state(old_crtc_state);
13402         struct intel_atomic_state *old_intel_state =
13403                 to_intel_atomic_state(old_crtc_state->state);
13404         bool modeset = needs_modeset(crtc->state);
13405
13406         if (!modeset &&
13407             (intel_cstate->base.color_mgmt_changed ||
13408              intel_cstate->update_pipe)) {
13409                 intel_color_set_csc(crtc->state);
13410                 intel_color_load_luts(crtc->state);
13411         }
13412
13413         /* Perform vblank evasion around commit operation */
13414         intel_pipe_update_start(intel_crtc);
13415
13416         if (modeset)
13417                 goto out;
13418
13419         if (intel_cstate->update_pipe)
13420                 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13421         else if (INTEL_GEN(dev_priv) >= 9)
13422                 skl_detach_scalers(intel_crtc);
13423
13424 out:
13425         if (dev_priv->display.atomic_update_watermarks)
13426                 dev_priv->display.atomic_update_watermarks(old_intel_state,
13427                                                            intel_cstate);
13428 }
13429
13430 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13431                                      struct drm_crtc_state *old_crtc_state)
13432 {
13433         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13434
13435         intel_pipe_update_end(intel_crtc, NULL);
13436 }
13437
13438 /**
13439  * intel_plane_destroy - destroy a plane
13440  * @plane: plane to destroy
13441  *
13442  * Common destruction function for all types of planes (primary, cursor,
13443  * sprite).
13444  */
13445 void intel_plane_destroy(struct drm_plane *plane)
13446 {
13447         drm_plane_cleanup(plane);
13448         kfree(to_intel_plane(plane));
13449 }
13450
13451 const struct drm_plane_funcs intel_plane_funcs = {
13452         .update_plane = drm_atomic_helper_update_plane,
13453         .disable_plane = drm_atomic_helper_disable_plane,
13454         .destroy = intel_plane_destroy,
13455         .set_property = drm_atomic_helper_plane_set_property,
13456         .atomic_get_property = intel_plane_atomic_get_property,
13457         .atomic_set_property = intel_plane_atomic_set_property,
13458         .atomic_duplicate_state = intel_plane_duplicate_state,
13459         .atomic_destroy_state = intel_plane_destroy_state,
13460 };
13461
13462 static int
13463 intel_legacy_cursor_update(struct drm_plane *plane,
13464                            struct drm_crtc *crtc,
13465                            struct drm_framebuffer *fb,
13466                            int crtc_x, int crtc_y,
13467                            unsigned int crtc_w, unsigned int crtc_h,
13468                            uint32_t src_x, uint32_t src_y,
13469                            uint32_t src_w, uint32_t src_h)
13470 {
13471         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13472         int ret;
13473         struct drm_plane_state *old_plane_state, *new_plane_state;
13474         struct intel_plane *intel_plane = to_intel_plane(plane);
13475         struct drm_framebuffer *old_fb;
13476         struct drm_crtc_state *crtc_state = crtc->state;
13477         struct i915_vma *old_vma;
13478
13479         /*
13480          * When crtc is inactive or there is a modeset pending,
13481          * wait for it to complete in the slowpath
13482          */
13483         if (!crtc_state->active || needs_modeset(crtc_state) ||
13484             to_intel_crtc_state(crtc_state)->update_pipe)
13485                 goto slow;
13486
13487         old_plane_state = plane->state;
13488
13489         /*
13490          * If any parameters change that may affect watermarks,
13491          * take the slowpath. Only changing fb or position should be
13492          * in the fastpath.
13493          */
13494         if (old_plane_state->crtc != crtc ||
13495             old_plane_state->src_w != src_w ||
13496             old_plane_state->src_h != src_h ||
13497             old_plane_state->crtc_w != crtc_w ||
13498             old_plane_state->crtc_h != crtc_h ||
13499             !old_plane_state->fb != !fb)
13500                 goto slow;
13501
13502         new_plane_state = intel_plane_duplicate_state(plane);
13503         if (!new_plane_state)
13504                 return -ENOMEM;
13505
13506         drm_atomic_set_fb_for_plane(new_plane_state, fb);
13507
13508         new_plane_state->src_x = src_x;
13509         new_plane_state->src_y = src_y;
13510         new_plane_state->src_w = src_w;
13511         new_plane_state->src_h = src_h;
13512         new_plane_state->crtc_x = crtc_x;
13513         new_plane_state->crtc_y = crtc_y;
13514         new_plane_state->crtc_w = crtc_w;
13515         new_plane_state->crtc_h = crtc_h;
13516
13517         ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13518                                                   to_intel_plane_state(new_plane_state));
13519         if (ret)
13520                 goto out_free;
13521
13522         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13523         if (ret)
13524                 goto out_free;
13525
13526         if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13527                 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13528
13529                 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13530                 if (ret) {
13531                         DRM_DEBUG_KMS("failed to attach phys object\n");
13532                         goto out_unlock;
13533                 }
13534         } else {
13535                 struct i915_vma *vma;
13536
13537                 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13538                 if (IS_ERR(vma)) {
13539                         DRM_DEBUG_KMS("failed to pin object\n");
13540
13541                         ret = PTR_ERR(vma);
13542                         goto out_unlock;
13543                 }
13544
13545                 to_intel_plane_state(new_plane_state)->vma = vma;
13546         }
13547
13548         old_fb = old_plane_state->fb;
13549         old_vma = to_intel_plane_state(old_plane_state)->vma;
13550
13551         i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13552                           intel_plane->frontbuffer_bit);
13553
13554         /* Swap plane state */
13555         new_plane_state->fence = old_plane_state->fence;
13556         *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13557         new_plane_state->fence = NULL;
13558         new_plane_state->fb = old_fb;
13559         to_intel_plane_state(new_plane_state)->vma = old_vma;
13560
13561         if (plane->state->visible) {
13562                 trace_intel_update_plane(plane, to_intel_crtc(crtc));
13563                 intel_plane->update_plane(plane,
13564                                           to_intel_crtc_state(crtc->state),
13565                                           to_intel_plane_state(plane->state));
13566         } else {
13567                 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
13568                 intel_plane->disable_plane(plane, crtc);
13569         }
13570
13571         intel_cleanup_plane_fb(plane, new_plane_state);
13572
13573 out_unlock:
13574         mutex_unlock(&dev_priv->drm.struct_mutex);
13575 out_free:
13576         intel_plane_destroy_state(plane, new_plane_state);
13577         return ret;
13578
13579 slow:
13580         return drm_atomic_helper_update_plane(plane, crtc, fb,
13581                                               crtc_x, crtc_y, crtc_w, crtc_h,
13582                                               src_x, src_y, src_w, src_h);
13583 }
13584
13585 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13586         .update_plane = intel_legacy_cursor_update,
13587         .disable_plane = drm_atomic_helper_disable_plane,
13588         .destroy = intel_plane_destroy,
13589         .set_property = drm_atomic_helper_plane_set_property,
13590         .atomic_get_property = intel_plane_atomic_get_property,
13591         .atomic_set_property = intel_plane_atomic_set_property,
13592         .atomic_duplicate_state = intel_plane_duplicate_state,
13593         .atomic_destroy_state = intel_plane_destroy_state,
13594 };
13595
13596 static struct intel_plane *
13597 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13598 {
13599         struct intel_plane *primary = NULL;
13600         struct intel_plane_state *state = NULL;
13601         const uint32_t *intel_primary_formats;
13602         unsigned int supported_rotations;
13603         unsigned int num_formats;
13604         int ret;
13605
13606         primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13607         if (!primary) {
13608                 ret = -ENOMEM;
13609                 goto fail;
13610         }
13611
13612         state = intel_create_plane_state(&primary->base);
13613         if (!state) {
13614                 ret = -ENOMEM;
13615                 goto fail;
13616         }
13617
13618         primary->base.state = &state->base;
13619
13620         primary->can_scale = false;
13621         primary->max_downscale = 1;
13622         if (INTEL_GEN(dev_priv) >= 9) {
13623                 primary->can_scale = true;
13624                 state->scaler_id = -1;
13625         }
13626         primary->pipe = pipe;
13627         /*
13628          * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13629          * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13630          */
13631         if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13632                 primary->plane = (enum plane) !pipe;
13633         else
13634                 primary->plane = (enum plane) pipe;
13635         primary->id = PLANE_PRIMARY;
13636         primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13637         primary->check_plane = intel_check_primary_plane;
13638
13639         if (INTEL_GEN(dev_priv) >= 9) {
13640                 intel_primary_formats = skl_primary_formats;
13641                 num_formats = ARRAY_SIZE(skl_primary_formats);
13642
13643                 primary->update_plane = skylake_update_primary_plane;
13644                 primary->disable_plane = skylake_disable_primary_plane;
13645         } else if (HAS_PCH_SPLIT(dev_priv)) {
13646                 intel_primary_formats = i965_primary_formats;
13647                 num_formats = ARRAY_SIZE(i965_primary_formats);
13648
13649                 primary->update_plane = ironlake_update_primary_plane;
13650                 primary->disable_plane = i9xx_disable_primary_plane;
13651         } else if (INTEL_GEN(dev_priv) >= 4) {
13652                 intel_primary_formats = i965_primary_formats;
13653                 num_formats = ARRAY_SIZE(i965_primary_formats);
13654
13655                 primary->update_plane = i9xx_update_primary_plane;
13656                 primary->disable_plane = i9xx_disable_primary_plane;
13657         } else {
13658                 intel_primary_formats = i8xx_primary_formats;
13659                 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13660
13661                 primary->update_plane = i9xx_update_primary_plane;
13662                 primary->disable_plane = i9xx_disable_primary_plane;
13663         }
13664
13665         if (INTEL_GEN(dev_priv) >= 9)
13666                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13667                                                0, &intel_plane_funcs,
13668                                                intel_primary_formats, num_formats,
13669                                                DRM_PLANE_TYPE_PRIMARY,
13670                                                "plane 1%c", pipe_name(pipe));
13671         else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
13672                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13673                                                0, &intel_plane_funcs,
13674                                                intel_primary_formats, num_formats,
13675                                                DRM_PLANE_TYPE_PRIMARY,
13676                                                "primary %c", pipe_name(pipe));
13677         else
13678                 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13679                                                0, &intel_plane_funcs,
13680                                                intel_primary_formats, num_formats,
13681                                                DRM_PLANE_TYPE_PRIMARY,
13682                                                "plane %c", plane_name(primary->plane));
13683         if (ret)
13684                 goto fail;
13685
13686         if (INTEL_GEN(dev_priv) >= 9) {
13687                 supported_rotations =
13688                         DRM_ROTATE_0 | DRM_ROTATE_90 |
13689                         DRM_ROTATE_180 | DRM_ROTATE_270;
13690         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13691                 supported_rotations =
13692                         DRM_ROTATE_0 | DRM_ROTATE_180 |
13693                         DRM_REFLECT_X;
13694         } else if (INTEL_GEN(dev_priv) >= 4) {
13695                 supported_rotations =
13696                         DRM_ROTATE_0 | DRM_ROTATE_180;
13697         } else {
13698                 supported_rotations = DRM_ROTATE_0;
13699         }
13700
13701         if (INTEL_GEN(dev_priv) >= 4)
13702                 drm_plane_create_rotation_property(&primary->base,
13703                                                    DRM_ROTATE_0,
13704                                                    supported_rotations);
13705
13706         drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13707
13708         return primary;
13709
13710 fail:
13711         kfree(state);
13712         kfree(primary);
13713
13714         return ERR_PTR(ret);
13715 }
13716
13717 static int
13718 intel_check_cursor_plane(struct drm_plane *plane,
13719                          struct intel_crtc_state *crtc_state,
13720                          struct intel_plane_state *state)
13721 {
13722         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13723         struct drm_framebuffer *fb = state->base.fb;
13724         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13725         enum pipe pipe = to_intel_plane(plane)->pipe;
13726         unsigned stride;
13727         int ret;
13728
13729         ret = drm_plane_helper_check_state(&state->base,
13730                                            &state->clip,
13731                                            DRM_PLANE_HELPER_NO_SCALING,
13732                                            DRM_PLANE_HELPER_NO_SCALING,
13733                                            true, true);
13734         if (ret)
13735                 return ret;
13736
13737         /* if we want to turn off the cursor ignore width and height */
13738         if (!obj)
13739                 return 0;
13740
13741         /* Check for which cursor types we support */
13742         if (!cursor_size_ok(dev_priv, state->base.crtc_w,
13743                             state->base.crtc_h)) {
13744                 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13745                           state->base.crtc_w, state->base.crtc_h);
13746                 return -EINVAL;
13747         }
13748
13749         stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13750         if (obj->base.size < stride * state->base.crtc_h) {
13751                 DRM_DEBUG_KMS("buffer is too small\n");
13752                 return -ENOMEM;
13753         }
13754
13755         if (fb->modifier != DRM_FORMAT_MOD_NONE) {
13756                 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13757                 return -EINVAL;
13758         }
13759
13760         /*
13761          * There's something wrong with the cursor on CHV pipe C.
13762          * If it straddles the left edge of the screen then
13763          * moving it away from the edge or disabling it often
13764          * results in a pipe underrun, and often that can lead to
13765          * dead pipe (constant underrun reported, and it scans
13766          * out just a solid color). To recover from that, the
13767          * display power well must be turned off and on again.
13768          * Refuse the put the cursor into that compromised position.
13769          */
13770         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
13771             state->base.visible && state->base.crtc_x < 0) {
13772                 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13773                 return -EINVAL;
13774         }
13775
13776         if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
13777                 state->ctl = i845_cursor_ctl(crtc_state, state);
13778         else
13779                 state->ctl = i9xx_cursor_ctl(crtc_state, state);
13780
13781         return 0;
13782 }
13783
13784 static void
13785 intel_disable_cursor_plane(struct drm_plane *plane,
13786                            struct drm_crtc *crtc)
13787 {
13788         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13789
13790         intel_crtc->cursor_addr = 0;
13791         intel_crtc_update_cursor(crtc, NULL);
13792 }
13793
13794 static void
13795 intel_update_cursor_plane(struct drm_plane *plane,
13796                           const struct intel_crtc_state *crtc_state,
13797                           const struct intel_plane_state *state)
13798 {
13799         struct drm_crtc *crtc = crtc_state->base.crtc;
13800         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13801         struct drm_i915_private *dev_priv = to_i915(plane->dev);
13802         struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13803         uint32_t addr;
13804
13805         if (!obj)
13806                 addr = 0;
13807         else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
13808                 addr = intel_plane_ggtt_offset(state);
13809         else
13810                 addr = obj->phys_handle->busaddr;
13811
13812         intel_crtc->cursor_addr = addr;
13813         intel_crtc_update_cursor(crtc, state);
13814 }
13815
13816 static struct intel_plane *
13817 intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
13818 {
13819         struct intel_plane *cursor = NULL;
13820         struct intel_plane_state *state = NULL;
13821         int ret;
13822
13823         cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13824         if (!cursor) {
13825                 ret = -ENOMEM;
13826                 goto fail;
13827         }
13828
13829         state = intel_create_plane_state(&cursor->base);
13830         if (!state) {
13831                 ret = -ENOMEM;
13832                 goto fail;
13833         }
13834
13835         cursor->base.state = &state->base;
13836
13837         cursor->can_scale = false;
13838         cursor->max_downscale = 1;
13839         cursor->pipe = pipe;
13840         cursor->plane = pipe;
13841         cursor->id = PLANE_CURSOR;
13842         cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
13843         cursor->check_plane = intel_check_cursor_plane;
13844         cursor->update_plane = intel_update_cursor_plane;
13845         cursor->disable_plane = intel_disable_cursor_plane;
13846
13847         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
13848                                        0, &intel_cursor_plane_funcs,
13849                                        intel_cursor_formats,
13850                                        ARRAY_SIZE(intel_cursor_formats),
13851                                        DRM_PLANE_TYPE_CURSOR,
13852                                        "cursor %c", pipe_name(pipe));
13853         if (ret)
13854                 goto fail;
13855
13856         if (INTEL_GEN(dev_priv) >= 4)
13857                 drm_plane_create_rotation_property(&cursor->base,
13858                                                    DRM_ROTATE_0,
13859                                                    DRM_ROTATE_0 |
13860                                                    DRM_ROTATE_180);
13861
13862         if (INTEL_GEN(dev_priv) >= 9)
13863                 state->scaler_id = -1;
13864
13865         drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13866
13867         return cursor;
13868
13869 fail:
13870         kfree(state);
13871         kfree(cursor);
13872
13873         return ERR_PTR(ret);
13874 }
13875
13876 static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13877                                     struct intel_crtc_state *crtc_state)
13878 {
13879         struct intel_crtc_scaler_state *scaler_state =
13880                 &crtc_state->scaler_state;
13881         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
13882         int i;
13883
13884         crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13885         if (!crtc->num_scalers)
13886                 return;
13887
13888         for (i = 0; i < crtc->num_scalers; i++) {
13889                 struct intel_scaler *scaler = &scaler_state->scalers[i];
13890
13891                 scaler->in_use = 0;
13892                 scaler->mode = PS_SCALER_MODE_DYN;
13893         }
13894
13895         scaler_state->scaler_id = -1;
13896 }
13897
13898 static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
13899 {
13900         struct intel_crtc *intel_crtc;
13901         struct intel_crtc_state *crtc_state = NULL;
13902         struct intel_plane *primary = NULL;
13903         struct intel_plane *cursor = NULL;
13904         int sprite, ret;
13905
13906         intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13907         if (!intel_crtc)
13908                 return -ENOMEM;
13909
13910         crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13911         if (!crtc_state) {
13912                 ret = -ENOMEM;
13913                 goto fail;
13914         }
13915         intel_crtc->config = crtc_state;
13916         intel_crtc->base.state = &crtc_state->base;
13917         crtc_state->base.crtc = &intel_crtc->base;
13918
13919         primary = intel_primary_plane_create(dev_priv, pipe);
13920         if (IS_ERR(primary)) {
13921                 ret = PTR_ERR(primary);
13922                 goto fail;
13923         }
13924         intel_crtc->plane_ids_mask |= BIT(primary->id);
13925
13926         for_each_sprite(dev_priv, pipe, sprite) {
13927                 struct intel_plane *plane;
13928
13929                 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
13930                 if (IS_ERR(plane)) {
13931                         ret = PTR_ERR(plane);
13932                         goto fail;
13933                 }
13934                 intel_crtc->plane_ids_mask |= BIT(plane->id);
13935         }
13936
13937         cursor = intel_cursor_plane_create(dev_priv, pipe);
13938         if (IS_ERR(cursor)) {
13939                 ret = PTR_ERR(cursor);
13940                 goto fail;
13941         }
13942         intel_crtc->plane_ids_mask |= BIT(cursor->id);
13943
13944         ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
13945                                         &primary->base, &cursor->base,
13946                                         &intel_crtc_funcs,
13947                                         "pipe %c", pipe_name(pipe));
13948         if (ret)
13949                 goto fail;
13950
13951         intel_crtc->pipe = pipe;
13952         intel_crtc->plane = primary->plane;
13953
13954         intel_crtc->cursor_base = ~0;
13955         intel_crtc->cursor_cntl = ~0;
13956         intel_crtc->cursor_size = ~0;
13957
13958         /* initialize shared scalers */
13959         intel_crtc_init_scalers(intel_crtc, crtc_state);
13960
13961         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13962                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13963         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13964         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
13965
13966         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13967
13968         intel_color_init(&intel_crtc->base);
13969
13970         WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13971
13972         return 0;
13973
13974 fail:
13975         /*
13976          * drm_mode_config_cleanup() will free up any
13977          * crtcs/planes already initialized.
13978          */
13979         kfree(crtc_state);
13980         kfree(intel_crtc);
13981
13982         return ret;
13983 }
13984
13985 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13986 {
13987         struct drm_device *dev = connector->base.dev;
13988
13989         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13990
13991         if (!connector->base.state->crtc)
13992                 return INVALID_PIPE;
13993
13994         return to_intel_crtc(connector->base.state->crtc)->pipe;
13995 }
13996
13997 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13998                                 struct drm_file *file)
13999 {
14000         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14001         struct drm_crtc *drmmode_crtc;
14002         struct intel_crtc *crtc;
14003
14004         drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14005         if (!drmmode_crtc)
14006                 return -ENOENT;
14007
14008         crtc = to_intel_crtc(drmmode_crtc);
14009         pipe_from_crtc_id->pipe = crtc->pipe;
14010
14011         return 0;
14012 }
14013
14014 static int intel_encoder_clones(struct intel_encoder *encoder)
14015 {
14016         struct drm_device *dev = encoder->base.dev;
14017         struct intel_encoder *source_encoder;
14018         int index_mask = 0;
14019         int entry = 0;
14020
14021         for_each_intel_encoder(dev, source_encoder) {
14022                 if (encoders_cloneable(encoder, source_encoder))
14023                         index_mask |= (1 << entry);
14024
14025                 entry++;
14026         }
14027
14028         return index_mask;
14029 }
14030
14031 static bool has_edp_a(struct drm_i915_private *dev_priv)
14032 {
14033         if (!IS_MOBILE(dev_priv))
14034                 return false;
14035
14036         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14037                 return false;
14038
14039         if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14040                 return false;
14041
14042         return true;
14043 }
14044
14045 static bool intel_crt_present(struct drm_i915_private *dev_priv)
14046 {
14047         if (INTEL_GEN(dev_priv) >= 9)
14048                 return false;
14049
14050         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
14051                 return false;
14052
14053         if (IS_CHERRYVIEW(dev_priv))
14054                 return false;
14055
14056         if (HAS_PCH_LPT_H(dev_priv) &&
14057             I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14058                 return false;
14059
14060         /* DDI E can't be used if DDI A requires 4 lanes */
14061         if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14062                 return false;
14063
14064         if (!dev_priv->vbt.int_crt_support)
14065                 return false;
14066
14067         return true;
14068 }
14069
14070 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
14071 {
14072         int pps_num;
14073         int pps_idx;
14074
14075         if (HAS_DDI(dev_priv))
14076                 return;
14077         /*
14078          * This w/a is needed at least on CPT/PPT, but to be sure apply it
14079          * everywhere where registers can be write protected.
14080          */
14081         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14082                 pps_num = 2;
14083         else
14084                 pps_num = 1;
14085
14086         for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14087                 u32 val = I915_READ(PP_CONTROL(pps_idx));
14088
14089                 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14090                 I915_WRITE(PP_CONTROL(pps_idx), val);
14091         }
14092 }
14093
14094 static void intel_pps_init(struct drm_i915_private *dev_priv)
14095 {
14096         if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
14097                 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14098         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14099                 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14100         else
14101                 dev_priv->pps_mmio_base = PPS_BASE;
14102
14103         intel_pps_unlock_regs_wa(dev_priv);
14104 }
14105
14106 static void intel_setup_outputs(struct drm_i915_private *dev_priv)
14107 {
14108         struct intel_encoder *encoder;
14109         bool dpd_is_edp = false;
14110
14111         intel_pps_init(dev_priv);
14112
14113         /*
14114          * intel_edp_init_connector() depends on this completing first, to
14115          * prevent the registeration of both eDP and LVDS and the incorrect
14116          * sharing of the PPS.
14117          */
14118         intel_lvds_init(dev_priv);
14119
14120         if (intel_crt_present(dev_priv))
14121                 intel_crt_init(dev_priv);
14122
14123         if (IS_GEN9_LP(dev_priv)) {
14124                 /*
14125                  * FIXME: Broxton doesn't support port detection via the
14126                  * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14127                  * detect the ports.
14128                  */
14129                 intel_ddi_init(dev_priv, PORT_A);
14130                 intel_ddi_init(dev_priv, PORT_B);
14131                 intel_ddi_init(dev_priv, PORT_C);
14132
14133                 intel_dsi_init(dev_priv);
14134         } else if (HAS_DDI(dev_priv)) {
14135                 int found;
14136
14137                 /*
14138                  * Haswell uses DDI functions to detect digital outputs.
14139                  * On SKL pre-D0 the strap isn't connected, so we assume
14140                  * it's there.
14141                  */
14142                 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14143                 /* WaIgnoreDDIAStrap: skl */
14144                 if (found || IS_GEN9_BC(dev_priv))
14145                         intel_ddi_init(dev_priv, PORT_A);
14146
14147                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14148                  * register */
14149                 found = I915_READ(SFUSE_STRAP);
14150
14151                 if (found & SFUSE_STRAP_DDIB_DETECTED)
14152                         intel_ddi_init(dev_priv, PORT_B);
14153                 if (found & SFUSE_STRAP_DDIC_DETECTED)
14154                         intel_ddi_init(dev_priv, PORT_C);
14155                 if (found & SFUSE_STRAP_DDID_DETECTED)
14156                         intel_ddi_init(dev_priv, PORT_D);
14157                 /*
14158                  * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14159                  */
14160                 if (IS_GEN9_BC(dev_priv) &&
14161                     (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14162                      dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14163                      dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14164                         intel_ddi_init(dev_priv, PORT_E);
14165
14166         } else if (HAS_PCH_SPLIT(dev_priv)) {
14167                 int found;
14168                 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
14169
14170                 if (has_edp_a(dev_priv))
14171                         intel_dp_init(dev_priv, DP_A, PORT_A);
14172
14173                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14174                         /* PCH SDVOB multiplex with HDMIB */
14175                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
14176                         if (!found)
14177                                 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
14178                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14179                                 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
14180                 }
14181
14182                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14183                         intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
14184
14185                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14186                         intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
14187
14188                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14189                         intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
14190
14191                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14192                         intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
14193         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14194                 bool has_edp, has_port;
14195
14196                 /*
14197                  * The DP_DETECTED bit is the latched state of the DDC
14198                  * SDA pin at boot. However since eDP doesn't require DDC
14199                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
14200                  * eDP ports may have been muxed to an alternate function.
14201                  * Thus we can't rely on the DP_DETECTED bit alone to detect
14202                  * eDP ports. Consult the VBT as well as DP_DETECTED to
14203                  * detect eDP ports.
14204                  *
14205                  * Sadly the straps seem to be missing sometimes even for HDMI
14206                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14207                  * and VBT for the presence of the port. Additionally we can't
14208                  * trust the port type the VBT declares as we've seen at least
14209                  * HDMI ports that the VBT claim are DP or eDP.
14210                  */
14211                 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
14212                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14213                 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
14214                         has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
14215                 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
14216                         intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
14217
14218                 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
14219                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14220                 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
14221                         has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
14222                 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
14223                         intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
14224
14225                 if (IS_CHERRYVIEW(dev_priv)) {
14226                         /*
14227                          * eDP not supported on port D,
14228                          * so no need to worry about it
14229                          */
14230                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14231                         if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
14232                                 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
14233                         if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
14234                                 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
14235                 }
14236
14237                 intel_dsi_init(dev_priv);
14238         } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
14239                 bool found = false;
14240
14241                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14242                         DRM_DEBUG_KMS("probing SDVOB\n");
14243                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
14244                         if (!found && IS_G4X(dev_priv)) {
14245                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14246                                 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
14247                         }
14248
14249                         if (!found && IS_G4X(dev_priv))
14250                                 intel_dp_init(dev_priv, DP_B, PORT_B);
14251                 }
14252
14253                 /* Before G4X SDVOC doesn't have its own detect register */
14254
14255                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14256                         DRM_DEBUG_KMS("probing SDVOC\n");
14257                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
14258                 }
14259
14260                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14261
14262                         if (IS_G4X(dev_priv)) {
14263                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14264                                 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
14265                         }
14266                         if (IS_G4X(dev_priv))
14267                                 intel_dp_init(dev_priv, DP_C, PORT_C);
14268                 }
14269
14270                 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
14271                         intel_dp_init(dev_priv, DP_D, PORT_D);
14272         } else if (IS_GEN2(dev_priv))
14273                 intel_dvo_init(dev_priv);
14274
14275         if (SUPPORTS_TV(dev_priv))
14276                 intel_tv_init(dev_priv);
14277
14278         intel_psr_init(dev_priv);
14279
14280         for_each_intel_encoder(&dev_priv->drm, encoder) {
14281                 encoder->base.possible_crtcs = encoder->crtc_mask;
14282                 encoder->base.possible_clones =
14283                         intel_encoder_clones(encoder);
14284         }
14285
14286         intel_init_pch_refclk(dev_priv);
14287
14288         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
14289 }
14290
14291 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14292 {
14293         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14294
14295         drm_framebuffer_cleanup(fb);
14296
14297         i915_gem_object_lock(intel_fb->obj);
14298         WARN_ON(!intel_fb->obj->framebuffer_references--);
14299         i915_gem_object_unlock(intel_fb->obj);
14300
14301         i915_gem_object_put(intel_fb->obj);
14302
14303         kfree(intel_fb);
14304 }
14305
14306 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14307                                                 struct drm_file *file,
14308                                                 unsigned int *handle)
14309 {
14310         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14311         struct drm_i915_gem_object *obj = intel_fb->obj;
14312
14313         if (obj->userptr.mm) {
14314                 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14315                 return -EINVAL;
14316         }
14317
14318         return drm_gem_handle_create(file, &obj->base, handle);
14319 }
14320
14321 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14322                                         struct drm_file *file,
14323                                         unsigned flags, unsigned color,
14324                                         struct drm_clip_rect *clips,
14325                                         unsigned num_clips)
14326 {
14327         struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14328
14329         i915_gem_object_flush_if_display(obj);
14330         intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
14331
14332         return 0;
14333 }
14334
14335 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14336         .destroy = intel_user_framebuffer_destroy,
14337         .create_handle = intel_user_framebuffer_create_handle,
14338         .dirty = intel_user_framebuffer_dirty,
14339 };
14340
14341 static
14342 u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14343                          uint64_t fb_modifier, uint32_t pixel_format)
14344 {
14345         u32 gen = INTEL_GEN(dev_priv);
14346
14347         if (gen >= 9) {
14348                 int cpp = drm_format_plane_cpp(pixel_format, 0);
14349
14350                 /* "The stride in bytes must not exceed the of the size of 8K
14351                  *  pixels and 32K bytes."
14352                  */
14353                 return min(8192 * cpp, 32768);
14354         } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
14355                 return 32*1024;
14356         } else if (gen >= 4) {
14357                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14358                         return 16*1024;
14359                 else
14360                         return 32*1024;
14361         } else if (gen >= 3) {
14362                 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14363                         return 8*1024;
14364                 else
14365                         return 16*1024;
14366         } else {
14367                 /* XXX DSPC is limited to 4k tiled */
14368                 return 8*1024;
14369         }
14370 }
14371
14372 static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14373                                   struct drm_i915_gem_object *obj,
14374                                   struct drm_mode_fb_cmd2 *mode_cmd)
14375 {
14376         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14377         struct drm_format_name_buf format_name;
14378         u32 pitch_limit, stride_alignment;
14379         unsigned int tiling, stride;
14380         int ret = -EINVAL;
14381
14382         i915_gem_object_lock(obj);
14383         obj->framebuffer_references++;
14384         tiling = i915_gem_object_get_tiling(obj);
14385         stride = i915_gem_object_get_stride(obj);
14386         i915_gem_object_unlock(obj);
14387
14388         if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14389                 /*
14390                  * If there's a fence, enforce that
14391                  * the fb modifier and tiling mode match.
14392                  */
14393                 if (tiling != I915_TILING_NONE &&
14394                     tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14395                         DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
14396                         goto err;
14397                 }
14398         } else {
14399                 if (tiling == I915_TILING_X) {
14400                         mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14401                 } else if (tiling == I915_TILING_Y) {
14402                         DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
14403                         goto err;
14404                 }
14405         }
14406
14407         /* Passed in modifier sanity checking. */
14408         switch (mode_cmd->modifier[0]) {
14409         case I915_FORMAT_MOD_Y_TILED:
14410         case I915_FORMAT_MOD_Yf_TILED:
14411                 if (INTEL_GEN(dev_priv) < 9) {
14412                         DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14413                                       mode_cmd->modifier[0]);
14414                         goto err;
14415                 }
14416         case DRM_FORMAT_MOD_NONE:
14417         case I915_FORMAT_MOD_X_TILED:
14418                 break;
14419         default:
14420                 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14421                               mode_cmd->modifier[0]);
14422                 goto err;
14423         }
14424
14425         /*
14426          * gen2/3 display engine uses the fence if present,
14427          * so the tiling mode must match the fb modifier exactly.
14428          */
14429         if (INTEL_INFO(dev_priv)->gen < 4 &&
14430             tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
14431                 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
14432                 goto err;
14433         }
14434
14435         pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
14436                                            mode_cmd->pixel_format);
14437         if (mode_cmd->pitches[0] > pitch_limit) {
14438                 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
14439                               mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14440                               "tiled" : "linear",
14441                               mode_cmd->pitches[0], pitch_limit);
14442                 goto err;
14443         }
14444
14445         /*
14446          * If there's a fence, enforce that
14447          * the fb pitch and fence stride match.
14448          */
14449         if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14450                 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14451                               mode_cmd->pitches[0], stride);
14452                 goto err;
14453         }
14454
14455         /* Reject formats not supported by any plane early. */
14456         switch (mode_cmd->pixel_format) {
14457         case DRM_FORMAT_C8:
14458         case DRM_FORMAT_RGB565:
14459         case DRM_FORMAT_XRGB8888:
14460         case DRM_FORMAT_ARGB8888:
14461                 break;
14462         case DRM_FORMAT_XRGB1555:
14463                 if (INTEL_GEN(dev_priv) > 3) {
14464                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14465                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14466                         goto err;
14467                 }
14468                 break;
14469         case DRM_FORMAT_ABGR8888:
14470                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
14471                     INTEL_GEN(dev_priv) < 9) {
14472                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14473                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14474                         goto err;
14475                 }
14476                 break;
14477         case DRM_FORMAT_XBGR8888:
14478         case DRM_FORMAT_XRGB2101010:
14479         case DRM_FORMAT_XBGR2101010:
14480                 if (INTEL_GEN(dev_priv) < 4) {
14481                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14482                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14483                         goto err;
14484                 }
14485                 break;
14486         case DRM_FORMAT_ABGR2101010:
14487                 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
14488                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14489                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14490                         goto err;
14491                 }
14492                 break;
14493         case DRM_FORMAT_YUYV:
14494         case DRM_FORMAT_UYVY:
14495         case DRM_FORMAT_YVYU:
14496         case DRM_FORMAT_VYUY:
14497                 if (INTEL_GEN(dev_priv) < 5) {
14498                         DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14499                                       drm_get_format_name(mode_cmd->pixel_format, &format_name));
14500                         goto err;
14501                 }
14502                 break;
14503         default:
14504                 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14505                               drm_get_format_name(mode_cmd->pixel_format, &format_name));
14506                 goto err;
14507         }
14508
14509         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14510         if (mode_cmd->offsets[0] != 0)
14511                 goto err;
14512
14513         drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14514                                        &intel_fb->base, mode_cmd);
14515
14516         stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
14517         if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14518                 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
14519                               mode_cmd->pitches[0], stride_alignment);
14520                 goto err;
14521         }
14522
14523         intel_fb->obj = obj;
14524
14525         ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14526         if (ret)
14527                 goto err;
14528
14529         ret = drm_framebuffer_init(obj->base.dev,
14530                                    &intel_fb->base,
14531                                    &intel_fb_funcs);
14532         if (ret) {
14533                 DRM_ERROR("framebuffer init failed %d\n", ret);
14534                 goto err;
14535         }
14536
14537         return 0;
14538
14539 err:
14540         i915_gem_object_lock(obj);
14541         obj->framebuffer_references--;
14542         i915_gem_object_unlock(obj);
14543         return ret;
14544 }
14545
14546 static struct drm_framebuffer *
14547 intel_user_framebuffer_create(struct drm_device *dev,
14548                               struct drm_file *filp,
14549                               const struct drm_mode_fb_cmd2 *user_mode_cmd)
14550 {
14551         struct drm_framebuffer *fb;
14552         struct drm_i915_gem_object *obj;
14553         struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14554
14555         obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14556         if (!obj)
14557                 return ERR_PTR(-ENOENT);
14558
14559         fb = intel_framebuffer_create(obj, &mode_cmd);
14560         if (IS_ERR(fb))
14561                 i915_gem_object_put(obj);
14562
14563         return fb;
14564 }
14565
14566 static void intel_atomic_state_free(struct drm_atomic_state *state)
14567 {
14568         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14569
14570         drm_atomic_state_default_release(state);
14571
14572         i915_sw_fence_fini(&intel_state->commit_ready);
14573
14574         kfree(state);
14575 }
14576
14577 static const struct drm_mode_config_funcs intel_mode_funcs = {
14578         .fb_create = intel_user_framebuffer_create,
14579         .output_poll_changed = intel_fbdev_output_poll_changed,
14580         .atomic_check = intel_atomic_check,
14581         .atomic_commit = intel_atomic_commit,
14582         .atomic_state_alloc = intel_atomic_state_alloc,
14583         .atomic_state_clear = intel_atomic_state_clear,
14584         .atomic_state_free = intel_atomic_state_free,
14585 };
14586
14587 /**
14588  * intel_init_display_hooks - initialize the display modesetting hooks
14589  * @dev_priv: device private
14590  */
14591 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14592 {
14593         intel_init_cdclk_hooks(dev_priv);
14594
14595         if (INTEL_INFO(dev_priv)->gen >= 9) {
14596                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14597                 dev_priv->display.get_initial_plane_config =
14598                         skylake_get_initial_plane_config;
14599                 dev_priv->display.crtc_compute_clock =
14600                         haswell_crtc_compute_clock;
14601                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14602                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14603         } else if (HAS_DDI(dev_priv)) {
14604                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14605                 dev_priv->display.get_initial_plane_config =
14606                         ironlake_get_initial_plane_config;
14607                 dev_priv->display.crtc_compute_clock =
14608                         haswell_crtc_compute_clock;
14609                 dev_priv->display.crtc_enable = haswell_crtc_enable;
14610                 dev_priv->display.crtc_disable = haswell_crtc_disable;
14611         } else if (HAS_PCH_SPLIT(dev_priv)) {
14612                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14613                 dev_priv->display.get_initial_plane_config =
14614                         ironlake_get_initial_plane_config;
14615                 dev_priv->display.crtc_compute_clock =
14616                         ironlake_crtc_compute_clock;
14617                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14618                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14619         } else if (IS_CHERRYVIEW(dev_priv)) {
14620                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14621                 dev_priv->display.get_initial_plane_config =
14622                         i9xx_get_initial_plane_config;
14623                 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14624                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14625                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14626         } else if (IS_VALLEYVIEW(dev_priv)) {
14627                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14628                 dev_priv->display.get_initial_plane_config =
14629                         i9xx_get_initial_plane_config;
14630                 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14631                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14632                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14633         } else if (IS_G4X(dev_priv)) {
14634                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14635                 dev_priv->display.get_initial_plane_config =
14636                         i9xx_get_initial_plane_config;
14637                 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14638                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14639                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14640         } else if (IS_PINEVIEW(dev_priv)) {
14641                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14642                 dev_priv->display.get_initial_plane_config =
14643                         i9xx_get_initial_plane_config;
14644                 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14645                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14646                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14647         } else if (!IS_GEN2(dev_priv)) {
14648                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14649                 dev_priv->display.get_initial_plane_config =
14650                         i9xx_get_initial_plane_config;
14651                 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14652                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14653                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14654         } else {
14655                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14656                 dev_priv->display.get_initial_plane_config =
14657                         i9xx_get_initial_plane_config;
14658                 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14659                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14660                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14661         }
14662
14663         if (IS_GEN5(dev_priv)) {
14664                 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14665         } else if (IS_GEN6(dev_priv)) {
14666                 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14667         } else if (IS_IVYBRIDGE(dev_priv)) {
14668                 /* FIXME: detect B0+ stepping and use auto training */
14669                 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14670         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14671                 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14672         }
14673
14674         if (dev_priv->info.gen >= 9)
14675                 dev_priv->display.update_crtcs = skl_update_crtcs;
14676         else
14677                 dev_priv->display.update_crtcs = intel_update_crtcs;
14678
14679         switch (INTEL_INFO(dev_priv)->gen) {
14680         case 2:
14681                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14682                 break;
14683
14684         case 3:
14685                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14686                 break;
14687
14688         case 4:
14689         case 5:
14690                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14691                 break;
14692
14693         case 6:
14694                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14695                 break;
14696         case 7:
14697         case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14698                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14699                 break;
14700         case 9:
14701                 /* Drop through - unsupported since execlist only. */
14702         default:
14703                 /* Default just returns -ENODEV to indicate unsupported */
14704                 dev_priv->display.queue_flip = intel_default_queue_flip;
14705         }
14706 }
14707
14708 /*
14709  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14710  * resume, or other times.  This quirk makes sure that's the case for
14711  * affected systems.
14712  */
14713 static void quirk_pipea_force(struct drm_device *dev)
14714 {
14715         struct drm_i915_private *dev_priv = to_i915(dev);
14716
14717         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14718         DRM_INFO("applying pipe a force quirk\n");
14719 }
14720
14721 static void quirk_pipeb_force(struct drm_device *dev)
14722 {
14723         struct drm_i915_private *dev_priv = to_i915(dev);
14724
14725         dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14726         DRM_INFO("applying pipe b force quirk\n");
14727 }
14728
14729 /*
14730  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14731  */
14732 static void quirk_ssc_force_disable(struct drm_device *dev)
14733 {
14734         struct drm_i915_private *dev_priv = to_i915(dev);
14735         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14736         DRM_INFO("applying lvds SSC disable quirk\n");
14737 }
14738
14739 /*
14740  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14741  * brightness value
14742  */
14743 static void quirk_invert_brightness(struct drm_device *dev)
14744 {
14745         struct drm_i915_private *dev_priv = to_i915(dev);
14746         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14747         DRM_INFO("applying inverted panel brightness quirk\n");
14748 }
14749
14750 /* Some VBT's incorrectly indicate no backlight is present */
14751 static void quirk_backlight_present(struct drm_device *dev)
14752 {
14753         struct drm_i915_private *dev_priv = to_i915(dev);
14754         dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14755         DRM_INFO("applying backlight present quirk\n");
14756 }
14757
14758 struct intel_quirk {
14759         int device;
14760         int subsystem_vendor;
14761         int subsystem_device;
14762         void (*hook)(struct drm_device *dev);
14763 };
14764
14765 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14766 struct intel_dmi_quirk {
14767         void (*hook)(struct drm_device *dev);
14768         const struct dmi_system_id (*dmi_id_list)[];
14769 };
14770
14771 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14772 {
14773         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14774         return 1;
14775 }
14776
14777 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14778         {
14779                 .dmi_id_list = &(const struct dmi_system_id[]) {
14780                         {
14781                                 .callback = intel_dmi_reverse_brightness,
14782                                 .ident = "NCR Corporation",
14783                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14784                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
14785                                 },
14786                         },
14787                         { }  /* terminating entry */
14788                 },
14789                 .hook = quirk_invert_brightness,
14790         },
14791 };
14792
14793 static struct intel_quirk intel_quirks[] = {
14794         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14795         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14796
14797         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14798         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14799
14800         /* 830 needs to leave pipe A & dpll A up */
14801         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14802
14803         /* 830 needs to leave pipe B & dpll B up */
14804         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14805
14806         /* Lenovo U160 cannot use SSC on LVDS */
14807         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14808
14809         /* Sony Vaio Y cannot use SSC on LVDS */
14810         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14811
14812         /* Acer Aspire 5734Z must invert backlight brightness */
14813         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14814
14815         /* Acer/eMachines G725 */
14816         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14817
14818         /* Acer/eMachines e725 */
14819         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14820
14821         /* Acer/Packard Bell NCL20 */
14822         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14823
14824         /* Acer Aspire 4736Z */
14825         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14826
14827         /* Acer Aspire 5336 */
14828         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14829
14830         /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14831         { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14832
14833         /* Acer C720 Chromebook (Core i3 4005U) */
14834         { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14835
14836         /* Apple Macbook 2,1 (Core 2 T7400) */
14837         { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14838
14839         /* Apple Macbook 4,1 */
14840         { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14841
14842         /* Toshiba CB35 Chromebook (Celeron 2955U) */
14843         { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14844
14845         /* HP Chromebook 14 (Celeron 2955U) */
14846         { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14847
14848         /* Dell Chromebook 11 */
14849         { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14850
14851         /* Dell Chromebook 11 (2015 version) */
14852         { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
14853 };
14854
14855 static void intel_init_quirks(struct drm_device *dev)
14856 {
14857         struct pci_dev *d = dev->pdev;
14858         int i;
14859
14860         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14861                 struct intel_quirk *q = &intel_quirks[i];
14862
14863                 if (d->device == q->device &&
14864                     (d->subsystem_vendor == q->subsystem_vendor ||
14865                      q->subsystem_vendor == PCI_ANY_ID) &&
14866                     (d->subsystem_device == q->subsystem_device ||
14867                      q->subsystem_device == PCI_ANY_ID))
14868                         q->hook(dev);
14869         }
14870         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14871                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14872                         intel_dmi_quirks[i].hook(dev);
14873         }
14874 }
14875
14876 /* Disable the VGA plane that we never use */
14877 static void i915_disable_vga(struct drm_i915_private *dev_priv)
14878 {
14879         struct pci_dev *pdev = dev_priv->drm.pdev;
14880         u8 sr1;
14881         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
14882
14883         /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14884         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
14885         outb(SR01, VGA_SR_INDEX);
14886         sr1 = inb(VGA_SR_DATA);
14887         outb(sr1 | 1<<5, VGA_SR_DATA);
14888         vga_put(pdev, VGA_RSRC_LEGACY_IO);
14889         udelay(300);
14890
14891         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14892         POSTING_READ(vga_reg);
14893 }
14894
14895 void intel_modeset_init_hw(struct drm_device *dev)
14896 {
14897         struct drm_i915_private *dev_priv = to_i915(dev);
14898
14899         intel_update_cdclk(dev_priv);
14900         dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
14901
14902         intel_init_clock_gating(dev_priv);
14903 }
14904
14905 /*
14906  * Calculate what we think the watermarks should be for the state we've read
14907  * out of the hardware and then immediately program those watermarks so that
14908  * we ensure the hardware settings match our internal state.
14909  *
14910  * We can calculate what we think WM's should be by creating a duplicate of the
14911  * current state (which was constructed during hardware readout) and running it
14912  * through the atomic check code to calculate new watermark values in the
14913  * state object.
14914  */
14915 static void sanitize_watermarks(struct drm_device *dev)
14916 {
14917         struct drm_i915_private *dev_priv = to_i915(dev);
14918         struct drm_atomic_state *state;
14919         struct intel_atomic_state *intel_state;
14920         struct drm_crtc *crtc;
14921         struct drm_crtc_state *cstate;
14922         struct drm_modeset_acquire_ctx ctx;
14923         int ret;
14924         int i;
14925
14926         /* Only supported on platforms that use atomic watermark design */
14927         if (!dev_priv->display.optimize_watermarks)
14928                 return;
14929
14930         /*
14931          * We need to hold connection_mutex before calling duplicate_state so
14932          * that the connector loop is protected.
14933          */
14934         drm_modeset_acquire_init(&ctx, 0);
14935 retry:
14936         ret = drm_modeset_lock_all_ctx(dev, &ctx);
14937         if (ret == -EDEADLK) {
14938                 drm_modeset_backoff(&ctx);
14939                 goto retry;
14940         } else if (WARN_ON(ret)) {
14941                 goto fail;
14942         }
14943
14944         state = drm_atomic_helper_duplicate_state(dev, &ctx);
14945         if (WARN_ON(IS_ERR(state)))
14946                 goto fail;
14947
14948         intel_state = to_intel_atomic_state(state);
14949
14950         /*
14951          * Hardware readout is the only time we don't want to calculate
14952          * intermediate watermarks (since we don't trust the current
14953          * watermarks).
14954          */
14955         if (!HAS_GMCH_DISPLAY(dev_priv))
14956                 intel_state->skip_intermediate_wm = true;
14957
14958         ret = intel_atomic_check(dev, state);
14959         if (ret) {
14960                 /*
14961                  * If we fail here, it means that the hardware appears to be
14962                  * programmed in a way that shouldn't be possible, given our
14963                  * understanding of watermark requirements.  This might mean a
14964                  * mistake in the hardware readout code or a mistake in the
14965                  * watermark calculations for a given platform.  Raise a WARN
14966                  * so that this is noticeable.
14967                  *
14968                  * If this actually happens, we'll have to just leave the
14969                  * BIOS-programmed watermarks untouched and hope for the best.
14970                  */
14971                 WARN(true, "Could not determine valid watermarks for inherited state\n");
14972                 goto put_state;
14973         }
14974
14975         /* Write calculated watermark values back */
14976         for_each_new_crtc_in_state(state, crtc, cstate, i) {
14977                 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14978
14979                 cs->wm.need_postvbl_update = true;
14980                 dev_priv->display.optimize_watermarks(intel_state, cs);
14981         }
14982
14983 put_state:
14984         drm_atomic_state_put(state);
14985 fail:
14986         drm_modeset_drop_locks(&ctx);
14987         drm_modeset_acquire_fini(&ctx);
14988 }
14989
14990 int intel_modeset_init(struct drm_device *dev)
14991 {
14992         struct drm_i915_private *dev_priv = to_i915(dev);
14993         struct i915_ggtt *ggtt = &dev_priv->ggtt;
14994         enum pipe pipe;
14995         struct intel_crtc *crtc;
14996
14997         drm_mode_config_init(dev);
14998
14999         dev->mode_config.min_width = 0;
15000         dev->mode_config.min_height = 0;
15001
15002         dev->mode_config.preferred_depth = 24;
15003         dev->mode_config.prefer_shadow = 1;
15004
15005         dev->mode_config.allow_fb_modifiers = true;
15006
15007         dev->mode_config.funcs = &intel_mode_funcs;
15008
15009         INIT_WORK(&dev_priv->atomic_helper.free_work,
15010                   intel_atomic_helper_free_state_worker);
15011
15012         intel_init_quirks(dev);
15013
15014         intel_init_pm(dev_priv);
15015
15016         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15017                 return 0;
15018
15019         /*
15020          * There may be no VBT; and if the BIOS enabled SSC we can
15021          * just keep using it to avoid unnecessary flicker.  Whereas if the
15022          * BIOS isn't using it, don't assume it will work even if the VBT
15023          * indicates as much.
15024          */
15025         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
15026                 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15027                                             DREF_SSC1_ENABLE);
15028
15029                 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15030                         DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15031                                      bios_lvds_use_ssc ? "en" : "dis",
15032                                      dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15033                         dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15034                 }
15035         }
15036
15037         if (IS_GEN2(dev_priv)) {
15038                 dev->mode_config.max_width = 2048;
15039                 dev->mode_config.max_height = 2048;
15040         } else if (IS_GEN3(dev_priv)) {
15041                 dev->mode_config.max_width = 4096;
15042                 dev->mode_config.max_height = 4096;
15043         } else {
15044                 dev->mode_config.max_width = 8192;
15045                 dev->mode_config.max_height = 8192;
15046         }
15047
15048         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
15049                 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
15050                 dev->mode_config.cursor_height = 1023;
15051         } else if (IS_GEN2(dev_priv)) {
15052                 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15053                 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15054         } else {
15055                 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15056                 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15057         }
15058
15059         dev->mode_config.fb_base = ggtt->mappable_base;
15060
15061         DRM_DEBUG_KMS("%d display pipe%s available.\n",
15062                       INTEL_INFO(dev_priv)->num_pipes,
15063                       INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
15064
15065         for_each_pipe(dev_priv, pipe) {
15066                 int ret;
15067
15068                 ret = intel_crtc_init(dev_priv, pipe);
15069                 if (ret) {
15070                         drm_mode_config_cleanup(dev);
15071                         return ret;
15072                 }
15073         }
15074
15075         intel_shared_dpll_init(dev);
15076
15077         intel_update_czclk(dev_priv);
15078         intel_modeset_init_hw(dev);
15079
15080         if (dev_priv->max_cdclk_freq == 0)
15081                 intel_update_max_cdclk(dev_priv);
15082
15083         /* Just disable it once at startup */
15084         i915_disable_vga(dev_priv);
15085         intel_setup_outputs(dev_priv);
15086
15087         drm_modeset_lock_all(dev);
15088         intel_modeset_setup_hw_state(dev);
15089         drm_modeset_unlock_all(dev);
15090
15091         for_each_intel_crtc(dev, crtc) {
15092                 struct intel_initial_plane_config plane_config = {};
15093
15094                 if (!crtc->active)
15095                         continue;
15096
15097                 /*
15098                  * Note that reserving the BIOS fb up front prevents us
15099                  * from stuffing other stolen allocations like the ring
15100                  * on top.  This prevents some ugliness at boot time, and
15101                  * can even allow for smooth boot transitions if the BIOS
15102                  * fb is large enough for the active pipe configuration.
15103                  */
15104                 dev_priv->display.get_initial_plane_config(crtc,
15105                                                            &plane_config);
15106
15107                 /*
15108                  * If the fb is shared between multiple heads, we'll
15109                  * just get the first one.
15110                  */
15111                 intel_find_initial_plane_obj(crtc, &plane_config);
15112         }
15113
15114         /*
15115          * Make sure hardware watermarks really match the state we read out.
15116          * Note that we need to do this after reconstructing the BIOS fb's
15117          * since the watermark calculation done here will use pstate->fb.
15118          */
15119         if (!HAS_GMCH_DISPLAY(dev_priv))
15120                 sanitize_watermarks(dev);
15121
15122         return 0;
15123 }
15124
15125 static void intel_enable_pipe_a(struct drm_device *dev)
15126 {
15127         struct intel_connector *connector;
15128         struct drm_connector_list_iter conn_iter;
15129         struct drm_connector *crt = NULL;
15130         struct intel_load_detect_pipe load_detect_temp;
15131         struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15132
15133         /* We can't just switch on the pipe A, we need to set things up with a
15134          * proper mode and output configuration. As a gross hack, enable pipe A
15135          * by enabling the load detect pipe once. */
15136         drm_connector_list_iter_begin(dev, &conn_iter);
15137         for_each_intel_connector_iter(connector, &conn_iter) {
15138                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15139                         crt = &connector->base;
15140                         break;
15141                 }
15142         }
15143         drm_connector_list_iter_end(&conn_iter);
15144
15145         if (!crt)
15146                 return;
15147
15148         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15149                 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15150 }
15151
15152 static bool
15153 intel_check_plane_mapping(struct intel_crtc *crtc)
15154 {
15155         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
15156         u32 val;
15157
15158         if (INTEL_INFO(dev_priv)->num_pipes == 1)
15159                 return true;
15160
15161         val = I915_READ(DSPCNTR(!crtc->plane));
15162
15163         if ((val & DISPLAY_PLANE_ENABLE) &&
15164             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15165                 return false;
15166
15167         return true;
15168 }
15169
15170 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15171 {
15172         struct drm_device *dev = crtc->base.dev;
15173         struct intel_encoder *encoder;
15174
15175         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15176                 return true;
15177
15178         return false;
15179 }
15180
15181 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15182 {
15183         struct drm_device *dev = encoder->base.dev;
15184         struct intel_connector *connector;
15185
15186         for_each_connector_on_encoder(dev, &encoder->base, connector)
15187                 return connector;
15188
15189         return NULL;
15190 }
15191
15192 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15193                               enum transcoder pch_transcoder)
15194 {
15195         return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15196                 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15197 }
15198
15199 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15200 {
15201         struct drm_device *dev = crtc->base.dev;
15202         struct drm_i915_private *dev_priv = to_i915(dev);
15203         enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15204
15205         /* Clear any frame start delays used for debugging left by the BIOS */
15206         if (!transcoder_is_dsi(cpu_transcoder)) {
15207                 i915_reg_t reg = PIPECONF(cpu_transcoder);
15208
15209                 I915_WRITE(reg,
15210                            I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15211         }
15212
15213         /* restore vblank interrupts to correct state */
15214         drm_crtc_vblank_reset(&crtc->base);
15215         if (crtc->active) {
15216                 struct intel_plane *plane;
15217
15218                 drm_crtc_vblank_on(&crtc->base);
15219
15220                 /* Disable everything but the primary plane */
15221                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15222                         if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15223                                 continue;
15224
15225                         trace_intel_disable_plane(&plane->base, crtc);
15226                         plane->disable_plane(&plane->base, &crtc->base);
15227                 }
15228         }
15229
15230         /* We need to sanitize the plane -> pipe mapping first because this will
15231          * disable the crtc (and hence change the state) if it is wrong. Note
15232          * that gen4+ has a fixed plane -> pipe mapping.  */
15233         if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
15234                 bool plane;
15235
15236                 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15237                               crtc->base.base.id, crtc->base.name);
15238
15239                 /* Pipe has the wrong plane attached and the plane is active.
15240                  * Temporarily change the plane mapping and disable everything
15241                  * ...  */
15242                 plane = crtc->plane;
15243                 crtc->base.primary->state->visible = true;
15244                 crtc->plane = !plane;
15245                 intel_crtc_disable_noatomic(&crtc->base);
15246                 crtc->plane = plane;
15247         }
15248
15249         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15250             crtc->pipe == PIPE_A && !crtc->active) {
15251                 /* BIOS forgot to enable pipe A, this mostly happens after
15252                  * resume. Force-enable the pipe to fix this, the update_dpms
15253                  * call below we restore the pipe to the right state, but leave
15254                  * the required bits on. */
15255                 intel_enable_pipe_a(dev);
15256         }
15257
15258         /* Adjust the state of the output pipe according to whether we
15259          * have active connectors/encoders. */
15260         if (crtc->active && !intel_crtc_has_encoders(crtc))
15261                 intel_crtc_disable_noatomic(&crtc->base);
15262
15263         if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
15264                 /*
15265                  * We start out with underrun reporting disabled to avoid races.
15266                  * For correct bookkeeping mark this on active crtcs.
15267                  *
15268                  * Also on gmch platforms we dont have any hardware bits to
15269                  * disable the underrun reporting. Which means we need to start
15270                  * out with underrun reporting disabled also on inactive pipes,
15271                  * since otherwise we'll complain about the garbage we read when
15272                  * e.g. coming up after runtime pm.
15273                  *
15274                  * No protection against concurrent access is required - at
15275                  * worst a fifo underrun happens which also sets this to false.
15276                  */
15277                 crtc->cpu_fifo_underrun_disabled = true;
15278                 /*
15279                  * We track the PCH trancoder underrun reporting state
15280                  * within the crtc. With crtc for pipe A housing the underrun
15281                  * reporting state for PCH transcoder A, crtc for pipe B housing
15282                  * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15283                  * and marking underrun reporting as disabled for the non-existing
15284                  * PCH transcoders B and C would prevent enabling the south
15285                  * error interrupt (see cpt_can_enable_serr_int()).
15286                  */
15287                 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15288                         crtc->pch_fifo_underrun_disabled = true;
15289         }
15290 }
15291
15292 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15293 {
15294         struct intel_connector *connector;
15295
15296         /* We need to check both for a crtc link (meaning that the
15297          * encoder is active and trying to read from a pipe) and the
15298          * pipe itself being active. */
15299         bool has_active_crtc = encoder->base.crtc &&
15300                 to_intel_crtc(encoder->base.crtc)->active;
15301
15302         connector = intel_encoder_find_connector(encoder);
15303         if (connector && !has_active_crtc) {
15304                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15305                               encoder->base.base.id,
15306                               encoder->base.name);
15307
15308                 /* Connector is active, but has no active pipe. This is
15309                  * fallout from our resume register restoring. Disable
15310                  * the encoder manually again. */
15311                 if (encoder->base.crtc) {
15312                         struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15313
15314                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15315                                       encoder->base.base.id,
15316                                       encoder->base.name);
15317                         encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15318                         if (encoder->post_disable)
15319                                 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
15320                 }
15321                 encoder->base.crtc = NULL;
15322
15323                 /* Inconsistent output/port/pipe state happens presumably due to
15324                  * a bug in one of the get_hw_state functions. Or someplace else
15325                  * in our code, like the register restore mess on resume. Clamp
15326                  * things to off as a safer default. */
15327
15328                 connector->base.dpms = DRM_MODE_DPMS_OFF;
15329                 connector->base.encoder = NULL;
15330         }
15331         /* Enabled encoders without active connectors will be fixed in
15332          * the crtc fixup. */
15333 }
15334
15335 void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
15336 {
15337         i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
15338
15339         if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15340                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15341                 i915_disable_vga(dev_priv);
15342         }
15343 }
15344
15345 void i915_redisable_vga(struct drm_i915_private *dev_priv)
15346 {
15347         /* This function can be called both from intel_modeset_setup_hw_state or
15348          * at a very early point in our resume sequence, where the power well
15349          * structures are not yet restored. Since this function is at a very
15350          * paranoid "someone might have enabled VGA while we were not looking"
15351          * level, just check if the power well is enabled instead of trying to
15352          * follow the "don't touch the power well if we don't need it" policy
15353          * the rest of the driver uses. */
15354         if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15355                 return;
15356
15357         i915_redisable_vga_power_on(dev_priv);
15358
15359         intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15360 }
15361
15362 static bool primary_get_hw_state(struct intel_plane *plane)
15363 {
15364         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15365
15366         return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15367 }
15368
15369 /* FIXME read out full plane state for all planes */
15370 static void readout_plane_state(struct intel_crtc *crtc)
15371 {
15372         struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15373         bool visible;
15374
15375         visible = crtc->active && primary_get_hw_state(primary);
15376
15377         intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15378                                 to_intel_plane_state(primary->base.state),
15379                                 visible);
15380 }
15381
15382 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15383 {
15384         struct drm_i915_private *dev_priv = to_i915(dev);
15385         enum pipe pipe;
15386         struct intel_crtc *crtc;
15387         struct intel_encoder *encoder;
15388         struct intel_connector *connector;
15389         struct drm_connector_list_iter conn_iter;
15390         int i;
15391
15392         dev_priv->active_crtcs = 0;
15393
15394         for_each_intel_crtc(dev, crtc) {
15395                 struct intel_crtc_state *crtc_state =
15396                         to_intel_crtc_state(crtc->base.state);
15397
15398                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
15399                 memset(crtc_state, 0, sizeof(*crtc_state));
15400                 crtc_state->base.crtc = &crtc->base;
15401
15402                 crtc_state->base.active = crtc_state->base.enable =
15403                         dev_priv->display.get_pipe_config(crtc, crtc_state);
15404
15405                 crtc->base.enabled = crtc_state->base.enable;
15406                 crtc->active = crtc_state->base.active;
15407
15408                 if (crtc_state->base.active)
15409                         dev_priv->active_crtcs |= 1 << crtc->pipe;
15410
15411                 readout_plane_state(crtc);
15412
15413                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15414                               crtc->base.base.id, crtc->base.name,
15415                               enableddisabled(crtc_state->base.active));
15416         }
15417
15418         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15419                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15420
15421                 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15422                                                   &pll->state.hw_state);
15423                 pll->state.crtc_mask = 0;
15424                 for_each_intel_crtc(dev, crtc) {
15425                         struct intel_crtc_state *crtc_state =
15426                                 to_intel_crtc_state(crtc->base.state);
15427
15428                         if (crtc_state->base.active &&
15429                             crtc_state->shared_dpll == pll)
15430                                 pll->state.crtc_mask |= 1 << crtc->pipe;
15431                 }
15432                 pll->active_mask = pll->state.crtc_mask;
15433
15434                 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15435                               pll->name, pll->state.crtc_mask, pll->on);
15436         }
15437
15438         for_each_intel_encoder(dev, encoder) {
15439                 pipe = 0;
15440
15441                 if (encoder->get_hw_state(encoder, &pipe)) {
15442                         struct intel_crtc_state *crtc_state;
15443
15444                         crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15445                         crtc_state = to_intel_crtc_state(crtc->base.state);
15446
15447                         encoder->base.crtc = &crtc->base;
15448                         crtc_state->output_types |= 1 << encoder->type;
15449                         encoder->get_config(encoder, crtc_state);
15450                 } else {
15451                         encoder->base.crtc = NULL;
15452                 }
15453
15454                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15455                               encoder->base.base.id, encoder->base.name,
15456                               enableddisabled(encoder->base.crtc),
15457                               pipe_name(pipe));
15458         }
15459
15460         drm_connector_list_iter_begin(dev, &conn_iter);
15461         for_each_intel_connector_iter(connector, &conn_iter) {
15462                 if (connector->get_hw_state(connector)) {
15463                         connector->base.dpms = DRM_MODE_DPMS_ON;
15464
15465                         encoder = connector->encoder;
15466                         connector->base.encoder = &encoder->base;
15467
15468                         if (encoder->base.crtc &&
15469                             encoder->base.crtc->state->active) {
15470                                 /*
15471                                  * This has to be done during hardware readout
15472                                  * because anything calling .crtc_disable may
15473                                  * rely on the connector_mask being accurate.
15474                                  */
15475                                 encoder->base.crtc->state->connector_mask |=
15476                                         1 << drm_connector_index(&connector->base);
15477                                 encoder->base.crtc->state->encoder_mask |=
15478                                         1 << drm_encoder_index(&encoder->base);
15479                         }
15480
15481                 } else {
15482                         connector->base.dpms = DRM_MODE_DPMS_OFF;
15483                         connector->base.encoder = NULL;
15484                 }
15485                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15486                               connector->base.base.id, connector->base.name,
15487                               enableddisabled(connector->base.encoder));
15488         }
15489         drm_connector_list_iter_end(&conn_iter);
15490
15491         for_each_intel_crtc(dev, crtc) {
15492                 struct intel_crtc_state *crtc_state =
15493                         to_intel_crtc_state(crtc->base.state);
15494                 int pixclk = 0;
15495
15496                 crtc->base.hwmode = crtc_state->base.adjusted_mode;
15497
15498                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15499                 if (crtc_state->base.active) {
15500                         intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15501                         intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
15502                         WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15503
15504                         /*
15505                          * The initial mode needs to be set in order to keep
15506                          * the atomic core happy. It wants a valid mode if the
15507                          * crtc's enabled, so we do the above call.
15508                          *
15509                          * But we don't set all the derived state fully, hence
15510                          * set a flag to indicate that a full recalculation is
15511                          * needed on the next commit.
15512                          */
15513                         crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
15514
15515                         intel_crtc_compute_pixel_rate(crtc_state);
15516
15517                         if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15518                             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15519                                 pixclk = crtc_state->pixel_rate;
15520                         else
15521                                 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15522
15523                         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15524                         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
15525                                 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15526
15527                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15528                         update_scanline_offset(crtc);
15529                 }
15530
15531                 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15532
15533                 intel_pipe_config_sanity_check(dev_priv, crtc_state);
15534         }
15535 }
15536
15537 static void
15538 get_encoder_power_domains(struct drm_i915_private *dev_priv)
15539 {
15540         struct intel_encoder *encoder;
15541
15542         for_each_intel_encoder(&dev_priv->drm, encoder) {
15543                 u64 get_domains;
15544                 enum intel_display_power_domain domain;
15545
15546                 if (!encoder->get_power_domains)
15547                         continue;
15548
15549                 get_domains = encoder->get_power_domains(encoder);
15550                 for_each_power_domain(domain, get_domains)
15551                         intel_display_power_get(dev_priv, domain);
15552         }
15553 }
15554
15555 /* Scan out the current hw modeset state,
15556  * and sanitizes it to the current state
15557  */
15558 static void
15559 intel_modeset_setup_hw_state(struct drm_device *dev)
15560 {
15561         struct drm_i915_private *dev_priv = to_i915(dev);
15562         enum pipe pipe;
15563         struct intel_crtc *crtc;
15564         struct intel_encoder *encoder;
15565         int i;
15566
15567         intel_modeset_readout_hw_state(dev);
15568
15569         /* HW state is read out, now we need to sanitize this mess. */
15570         get_encoder_power_domains(dev_priv);
15571
15572         for_each_intel_encoder(dev, encoder) {
15573                 intel_sanitize_encoder(encoder);
15574         }
15575
15576         for_each_pipe(dev_priv, pipe) {
15577                 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
15578
15579                 intel_sanitize_crtc(crtc);
15580                 intel_dump_pipe_config(crtc, crtc->config,
15581                                        "[setup_hw_state]");
15582         }
15583
15584         intel_modeset_update_connector_atomic_state(dev);
15585
15586         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15587                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15588
15589                 if (!pll->on || pll->active_mask)
15590                         continue;
15591
15592                 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15593
15594                 pll->funcs.disable(dev_priv, pll);
15595                 pll->on = false;
15596         }
15597
15598         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
15599                 vlv_wm_get_hw_state(dev);
15600                 vlv_wm_sanitize(dev_priv);
15601         } else if (IS_GEN9(dev_priv)) {
15602                 skl_wm_get_hw_state(dev);
15603         } else if (HAS_PCH_SPLIT(dev_priv)) {
15604                 ilk_wm_get_hw_state(dev);
15605         }
15606
15607         for_each_intel_crtc(dev, crtc) {
15608                 u64 put_domains;
15609
15610                 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15611                 if (WARN_ON(put_domains))
15612                         modeset_put_power_domains(dev_priv, put_domains);
15613         }
15614         intel_display_set_init_power(dev_priv, false);
15615
15616         intel_power_domains_verify_state(dev_priv);
15617
15618         intel_fbc_init_pipe_state(dev_priv);
15619 }
15620
15621 void intel_display_resume(struct drm_device *dev)
15622 {
15623         struct drm_i915_private *dev_priv = to_i915(dev);
15624         struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15625         struct drm_modeset_acquire_ctx ctx;
15626         int ret;
15627
15628         dev_priv->modeset_restore_state = NULL;
15629         if (state)
15630                 state->acquire_ctx = &ctx;
15631
15632         /*
15633          * This is a cludge because with real atomic modeset mode_config.mutex
15634          * won't be taken. Unfortunately some probed state like
15635          * audio_codec_enable is still protected by mode_config.mutex, so lock
15636          * it here for now.
15637          */
15638         mutex_lock(&dev->mode_config.mutex);
15639         drm_modeset_acquire_init(&ctx, 0);
15640
15641         while (1) {
15642                 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15643                 if (ret != -EDEADLK)
15644                         break;
15645
15646                 drm_modeset_backoff(&ctx);
15647         }
15648
15649         if (!ret)
15650                 ret = __intel_display_resume(dev, state, &ctx);
15651
15652         drm_modeset_drop_locks(&ctx);
15653         drm_modeset_acquire_fini(&ctx);
15654         mutex_unlock(&dev->mode_config.mutex);
15655
15656         if (ret)
15657                 DRM_ERROR("Restoring old state failed with %i\n", ret);
15658         if (state)
15659                 drm_atomic_state_put(state);
15660 }
15661
15662 void intel_modeset_gem_init(struct drm_device *dev)
15663 {
15664         struct drm_i915_private *dev_priv = to_i915(dev);
15665
15666         intel_init_gt_powersave(dev_priv);
15667
15668         intel_setup_overlay(dev_priv);
15669 }
15670
15671 int intel_connector_register(struct drm_connector *connector)
15672 {
15673         struct intel_connector *intel_connector = to_intel_connector(connector);
15674         int ret;
15675
15676         ret = intel_backlight_device_register(intel_connector);
15677         if (ret)
15678                 goto err;
15679
15680         return 0;
15681
15682 err:
15683         return ret;
15684 }
15685
15686 void intel_connector_unregister(struct drm_connector *connector)
15687 {
15688         struct intel_connector *intel_connector = to_intel_connector(connector);
15689
15690         intel_backlight_device_unregister(intel_connector);
15691         intel_panel_destroy_backlight(connector);
15692 }
15693
15694 void intel_modeset_cleanup(struct drm_device *dev)
15695 {
15696         struct drm_i915_private *dev_priv = to_i915(dev);
15697
15698         flush_work(&dev_priv->atomic_helper.free_work);
15699         WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15700
15701         intel_disable_gt_powersave(dev_priv);
15702
15703         /*
15704          * Interrupts and polling as the first thing to avoid creating havoc.
15705          * Too much stuff here (turning of connectors, ...) would
15706          * experience fancy races otherwise.
15707          */
15708         intel_irq_uninstall(dev_priv);
15709
15710         /*
15711          * Due to the hpd irq storm handling the hotplug work can re-arm the
15712          * poll handlers. Hence disable polling after hpd handling is shut down.
15713          */
15714         drm_kms_helper_poll_fini(dev);
15715
15716         intel_unregister_dsm_handler();
15717
15718         intel_fbc_global_disable(dev_priv);
15719
15720         /* flush any delayed tasks or pending work */
15721         flush_scheduled_work();
15722
15723         drm_mode_config_cleanup(dev);
15724
15725         intel_cleanup_overlay(dev_priv);
15726
15727         intel_cleanup_gt_powersave(dev_priv);
15728
15729         intel_teardown_gmbus(dev_priv);
15730 }
15731
15732 void intel_connector_attach_encoder(struct intel_connector *connector,
15733                                     struct intel_encoder *encoder)
15734 {
15735         connector->encoder = encoder;
15736         drm_mode_connector_attach_encoder(&connector->base,
15737                                           &encoder->base);
15738 }
15739
15740 /*
15741  * set vga decode state - true == enable VGA decode
15742  */
15743 int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
15744 {
15745         unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15746         u16 gmch_ctrl;
15747
15748         if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15749                 DRM_ERROR("failed to read control word\n");
15750                 return -EIO;
15751         }
15752
15753         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15754                 return 0;
15755
15756         if (state)
15757                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15758         else
15759                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15760
15761         if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15762                 DRM_ERROR("failed to write control word\n");
15763                 return -EIO;
15764         }
15765
15766         return 0;
15767 }
15768
15769 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15770
15771 struct intel_display_error_state {
15772
15773         u32 power_well_driver;
15774
15775         int num_transcoders;
15776
15777         struct intel_cursor_error_state {
15778                 u32 control;
15779                 u32 position;
15780                 u32 base;
15781                 u32 size;
15782         } cursor[I915_MAX_PIPES];
15783
15784         struct intel_pipe_error_state {
15785                 bool power_domain_on;
15786                 u32 source;
15787                 u32 stat;
15788         } pipe[I915_MAX_PIPES];
15789
15790         struct intel_plane_error_state {
15791                 u32 control;
15792                 u32 stride;
15793                 u32 size;
15794                 u32 pos;
15795                 u32 addr;
15796                 u32 surface;
15797                 u32 tile_offset;
15798         } plane[I915_MAX_PIPES];
15799
15800         struct intel_transcoder_error_state {
15801                 bool power_domain_on;
15802                 enum transcoder cpu_transcoder;
15803
15804                 u32 conf;
15805
15806                 u32 htotal;
15807                 u32 hblank;
15808                 u32 hsync;
15809                 u32 vtotal;
15810                 u32 vblank;
15811                 u32 vsync;
15812         } transcoder[4];
15813 };
15814
15815 struct intel_display_error_state *
15816 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
15817 {
15818         struct intel_display_error_state *error;
15819         int transcoders[] = {
15820                 TRANSCODER_A,
15821                 TRANSCODER_B,
15822                 TRANSCODER_C,
15823                 TRANSCODER_EDP,
15824         };
15825         int i;
15826
15827         if (INTEL_INFO(dev_priv)->num_pipes == 0)
15828                 return NULL;
15829
15830         error = kzalloc(sizeof(*error), GFP_ATOMIC);
15831         if (error == NULL)
15832                 return NULL;
15833
15834         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15835                 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15836
15837         for_each_pipe(dev_priv, i) {
15838                 error->pipe[i].power_domain_on =
15839                         __intel_display_power_is_enabled(dev_priv,
15840                                                          POWER_DOMAIN_PIPE(i));
15841                 if (!error->pipe[i].power_domain_on)
15842                         continue;
15843
15844                 error->cursor[i].control = I915_READ(CURCNTR(i));
15845                 error->cursor[i].position = I915_READ(CURPOS(i));
15846                 error->cursor[i].base = I915_READ(CURBASE(i));
15847
15848                 error->plane[i].control = I915_READ(DSPCNTR(i));
15849                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15850                 if (INTEL_GEN(dev_priv) <= 3) {
15851                         error->plane[i].size = I915_READ(DSPSIZE(i));
15852                         error->plane[i].pos = I915_READ(DSPPOS(i));
15853                 }
15854                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15855                         error->plane[i].addr = I915_READ(DSPADDR(i));
15856                 if (INTEL_GEN(dev_priv) >= 4) {
15857                         error->plane[i].surface = I915_READ(DSPSURF(i));
15858                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15859                 }
15860
15861                 error->pipe[i].source = I915_READ(PIPESRC(i));
15862
15863                 if (HAS_GMCH_DISPLAY(dev_priv))
15864                         error->pipe[i].stat = I915_READ(PIPESTAT(i));
15865         }
15866
15867         /* Note: this does not include DSI transcoders. */
15868         error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
15869         if (HAS_DDI(dev_priv))
15870                 error->num_transcoders++; /* Account for eDP. */
15871
15872         for (i = 0; i < error->num_transcoders; i++) {
15873                 enum transcoder cpu_transcoder = transcoders[i];
15874
15875                 error->transcoder[i].power_domain_on =
15876                         __intel_display_power_is_enabled(dev_priv,
15877                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15878                 if (!error->transcoder[i].power_domain_on)
15879                         continue;
15880
15881                 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15882
15883                 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15884                 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15885                 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15886                 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15887                 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15888                 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15889                 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15890         }
15891
15892         return error;
15893 }
15894
15895 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15896
15897 void
15898 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15899                                 struct intel_display_error_state *error)
15900 {
15901         struct drm_i915_private *dev_priv = m->i915;
15902         int i;
15903
15904         if (!error)
15905                 return;
15906
15907         err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
15908         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
15909                 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15910                            error->power_well_driver);
15911         for_each_pipe(dev_priv, i) {
15912                 err_printf(m, "Pipe [%d]:\n", i);
15913                 err_printf(m, "  Power: %s\n",
15914                            onoff(error->pipe[i].power_domain_on));
15915                 err_printf(m, "  SRC: %08x\n", error->pipe[i].source);
15916                 err_printf(m, "  STAT: %08x\n", error->pipe[i].stat);
15917
15918                 err_printf(m, "Plane [%d]:\n", i);
15919                 err_printf(m, "  CNTR: %08x\n", error->plane[i].control);
15920                 err_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
15921                 if (INTEL_GEN(dev_priv) <= 3) {
15922                         err_printf(m, "  SIZE: %08x\n", error->plane[i].size);
15923                         err_printf(m, "  POS: %08x\n", error->plane[i].pos);
15924                 }
15925                 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
15926                         err_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
15927                 if (INTEL_GEN(dev_priv) >= 4) {
15928                         err_printf(m, "  SURF: %08x\n", error->plane[i].surface);
15929                         err_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
15930                 }
15931
15932                 err_printf(m, "Cursor [%d]:\n", i);
15933                 err_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
15934                 err_printf(m, "  POS: %08x\n", error->cursor[i].position);
15935                 err_printf(m, "  BASE: %08x\n", error->cursor[i].base);
15936         }
15937
15938         for (i = 0; i < error->num_transcoders; i++) {
15939                 err_printf(m, "CPU transcoder: %s\n",
15940                            transcoder_name(error->transcoder[i].cpu_transcoder));
15941                 err_printf(m, "  Power: %s\n",
15942                            onoff(error->transcoder[i].power_domain_on));
15943                 err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);
15944                 err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);
15945                 err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);
15946                 err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);
15947                 err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);
15948                 err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);
15949                 err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);
15950         }
15951 }
15952
15953 #endif