drivers/gpu/drm/i915/intel_fbc.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: Frame Buffer Compression (FBC)
  26  *
  27  * FBC tries to save memory bandwidth (and so power consumption) by
  28  * compressing the amount of memory used by the display. It is total
  29  * transparent to user space and completely handled in the kernel.
  30  *
  31  * The benefits of FBC are mostly visible with solid backgrounds and
  32  * variation-less patterns. It comes from keeping the memory footprint small
  33  * and having fewer memory pages opened and accessed for refreshing the display.
  34  *
  35  * i915 is responsible to reserve stolen memory for FBC and configure its
  36  * offset on proper registers. The hardware takes care of all
  37  * compress/decompress. However there are many known cases where we have to
  38  * forcibly disable it to allow proper screen updates.
  39  */
  40
  41 #include "intel_drv.h"
  42 #include "i915_drv.h"
  43
  44 static inline bool fbc_supported(struct drm_i915_private *dev_priv)
  45 {
  46         return HAS_FBC(dev_priv);
  47 }
  48
  49 static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
  50 {
  51         return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
  52 }
  53
  54 static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
  55 {
  56         return INTEL_GEN(dev_priv) < 4;
  57 }
  58
  59 static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
  60 {
  61         return INTEL_GEN(dev_priv) <= 3;
  62 }
  63
  64 /*
  65  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
  66  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
  67  * origin so the x and y offsets can actually fit the registers. As a
  68  * consequence, the fence doesn't really start exactly at the display plane
  69  * address we program because it starts at the real start of the buffer, so we
  70  * have to take this into consideration here.
  71  */
  72 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
  73 {
  74         return crtc->base.y - crtc->adjusted_y;
  75 }
  76
  77 /*
  78  * For SKL+, the plane source size used by the hardware is based on the value we
  79  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
  80  * we wrote to PIPESRC.
  81  */
  82 static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
  83                                             int *width, int *height)
  84 {
  85         int w, h;
  86
  87         if (drm_rotation_90_or_270(cache->plane.rotation)) {
  88                 w = cache->plane.src_h;
  89                 h = cache->plane.src_w;
  90         } else {
  91                 w = cache->plane.src_w;
  92                 h = cache->plane.src_h;
  93         }
  94
  95         if (width)
  96                 *width = w;
  97         if (height)
  98                 *height = h;
  99 }
 100
 101 static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
 102                                         struct intel_fbc_state_cache *cache)
 103 {
 104         int lines;
 105
 106         intel_fbc_get_plane_source_size(cache, NULL, &lines);
 107         if (INTEL_GEN(dev_priv) == 7)
 108                 lines = min(lines, 2048);
 109         else if (INTEL_GEN(dev_priv) >= 8)
 110                 lines = min(lines, 2560);
 111
 112         /* Hardware needs the full buffer stride, not just the active area. */
 113         return lines * cache->fb.stride;
 114 }
 115
 116 static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
 117 {
 118         u32 fbc_ctl;
 119
 120         /* Disable compression */
 121         fbc_ctl = I915_READ(FBC_CONTROL);
 122         if ((fbc_ctl & FBC_CTL_EN) == 0)
 123                 return;
 124
 125         fbc_ctl &= ~FBC_CTL_EN;
 126         I915_WRITE(FBC_CONTROL, fbc_ctl);
 127
 128         /* Wait for compressing bit to clear */
 129         if (intel_wait_for_register(dev_priv,
 130                                     FBC_STATUS, FBC_STAT_COMPRESSING, 0,
 131                                     10)) {
 132                 DRM_DEBUG_KMS("FBC idle timed out\n");
 133                 return;
 134         }
 135 }
 136
 137 static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
 138 {
 139         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 140         int cfb_pitch;
 141         int i;
 142         u32 fbc_ctl;
 143
 144         /* Note: fbc.threshold == 1 for i8xx */
 145         cfb_pitch = params->cfb_size / FBC_LL_SIZE;
 146         if (params->fb.stride < cfb_pitch)
 147                 cfb_pitch = params->fb.stride;
 148
 149         /* FBC_CTL wants 32B or 64B units */
 150         if (IS_GEN2(dev_priv))
 151                 cfb_pitch = (cfb_pitch / 32) - 1;
 152         else
 153                 cfb_pitch = (cfb_pitch / 64) - 1;
 154
 155         /* Clear old tags */
 156         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 157                 I915_WRITE(FBC_TAG(i), 0);
 158
 159         if (IS_GEN4(dev_priv)) {
 160                 u32 fbc_ctl2;
 161
 162                 /* Set it up... */
 163                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 164                 fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);
 165                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 166                 I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
 167         }
 168
 169         /* enable it... */
 170         fbc_ctl = I915_READ(FBC_CONTROL);
 171         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 172         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 173         if (IS_I945GM(dev_priv))
 174                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 175         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 176         fbc_ctl |= params->vma->fence->id;
 177         I915_WRITE(FBC_CONTROL, fbc_ctl);
 178 }
 179
 180 static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
 181 {
 182         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 183 }
 184
 185 static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
 186 {
 187         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 188         u32 dpfc_ctl;
 189
 190         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;
 191         if (params->fb.format->cpp[0] == 2)
 192                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 193         else
 194                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 195
 196         if (params->vma->fence) {
 197                 dpfc_ctl |= DPFC_CTL_FENCE_EN | params->vma->fence->id;
 198                 I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 199         } else {
 200                 I915_WRITE(DPFC_FENCE_YOFF, 0);
 201         }
 202
 203         /* enable it... */
 204         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 205 }
 206
 207 static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
 208 {
 209         u32 dpfc_ctl;
 210
 211         /* Disable compression */
 212         dpfc_ctl = I915_READ(DPFC_CONTROL);
 213         if (dpfc_ctl & DPFC_CTL_EN) {
 214                 dpfc_ctl &= ~DPFC_CTL_EN;
 215                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 216         }
 217 }
 218
 219 static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
 220 {
 221         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 222 }
 223
 224 /* This function forces a CFB recompression through the nuke operation. */
 225 static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
 226 {
 227         I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
 228         POSTING_READ(MSG_FBC_REND_STATE);
 229 }
 230
 231 static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
 232 {
 233         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 234         u32 dpfc_ctl;
 235         int threshold = dev_priv->fbc.threshold;
 236
 237         dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);
 238         if (params->fb.format->cpp[0] == 2)
 239                 threshold++;
 240
 241         switch (threshold) {
 242         case 4:
 243         case 3:
 244                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 245                 break;
 246         case 2:
 247                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 248                 break;
 249         case 1:
 250                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 251                 break;
 252         }
 253
 254         if (params->vma->fence) {
 255                 dpfc_ctl |= DPFC_CTL_FENCE_EN;
 256                 if (IS_GEN5(dev_priv))
 257                         dpfc_ctl |= params->vma->fence->id;
 258                 if (IS_GEN6(dev_priv)) {
 259                         I915_WRITE(SNB_DPFC_CTL_SA,
 260                                    SNB_CPU_FENCE_ENABLE |
 261                                    params->vma->fence->id);
 262                         I915_WRITE(DPFC_CPU_FENCE_OFFSET,
 263                                    params->crtc.fence_y_offset);
 264                 }
 265         } else {
 266                 if (IS_GEN6(dev_priv)) {
 267                         I915_WRITE(SNB_DPFC_CTL_SA, 0);
 268                         I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 269                 }
 270         }
 271
 272         I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
 273         I915_WRITE(ILK_FBC_RT_BASE,
 274                    i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID);
 275         /* enable it... */
 276         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 277
 278         intel_fbc_recompress(dev_priv);
 279 }
 280
 281 static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
 282 {
 283         u32 dpfc_ctl;
 284
 285         /* Disable compression */
 286         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 287         if (dpfc_ctl & DPFC_CTL_EN) {
 288                 dpfc_ctl &= ~DPFC_CTL_EN;
 289                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 290         }
 291 }
 292
 293 static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
 294 {
 295         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 296 }
 297
 298 static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
 299 {
 300         struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
 301         u32 dpfc_ctl;
 302         int threshold = dev_priv->fbc.threshold;
 303
 304         dpfc_ctl = 0;
 305         if (IS_IVYBRIDGE(dev_priv))
 306                 dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
 307
 308         if (params->fb.format->cpp[0] == 2)
 309                 threshold++;
 310
 311         switch (threshold) {
 312         case 4:
 313         case 3:
 314                 dpfc_ctl |= DPFC_CTL_LIMIT_4X;
 315                 break;
 316         case 2:
 317                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 318                 break;
 319         case 1:
 320                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 321                 break;
 322         }
 323
 324         if (params->vma->fence) {
 325                 dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 326                 I915_WRITE(SNB_DPFC_CTL_SA,
 327                            SNB_CPU_FENCE_ENABLE |
 328                            params->vma->fence->id);
 329                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
 330         } else {
 331                 I915_WRITE(SNB_DPFC_CTL_SA,0);
 332                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
 333         }
 334
 335         if (dev_priv->fbc.false_color)
 336                 dpfc_ctl |= FBC_CTL_FALSE_COLOR;
 337
 338         if (IS_IVYBRIDGE(dev_priv)) {
 339                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 340                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 341                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 342                            ILK_FBCQ_DIS);
 343         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 344                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 345                 I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
 346                            I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
 347                            HSW_FBCQ_DIS);
 348         }
 349
 350         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 351
 352         intel_fbc_recompress(dev_priv);
 353 }
 354
 355 static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
 356 {
 357         if (INTEL_GEN(dev_priv) >= 5)
 358                 return ilk_fbc_is_active(dev_priv);
 359         else if (IS_GM45(dev_priv))
 360                 return g4x_fbc_is_active(dev_priv);
 361         else
 362                 return i8xx_fbc_is_active(dev_priv);
 363 }
 364
 365 static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
 366 {
 367         struct intel_fbc *fbc = &dev_priv->fbc;
 368
 369         fbc->active = true;
 370
 371         if (INTEL_GEN(dev_priv) >= 7)
 372                 gen7_fbc_activate(dev_priv);
 373         else if (INTEL_GEN(dev_priv) >= 5)
 374                 ilk_fbc_activate(dev_priv);
 375         else if (IS_GM45(dev_priv))
 376                 g4x_fbc_activate(dev_priv);
 377         else
 378                 i8xx_fbc_activate(dev_priv);
 379 }
 380
 381 static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
 382 {
 383         struct intel_fbc *fbc = &dev_priv->fbc;
 384
 385         fbc->active = false;
 386
 387         if (INTEL_GEN(dev_priv) >= 5)
 388                 ilk_fbc_deactivate(dev_priv);
 389         else if (IS_GM45(dev_priv))
 390                 g4x_fbc_deactivate(dev_priv);
 391         else
 392                 i8xx_fbc_deactivate(dev_priv);
 393 }
 394
 395 /**
 396  * intel_fbc_is_active - Is FBC active?
 397  * @dev_priv: i915 device instance
 398  *
 399  * This function is used to verify the current state of FBC.
 400  *
 401  * FIXME: This should be tracked in the plane config eventually
 402  * instead of queried at runtime for most callers.
 403  */
 404 bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
 405 {
 406         return dev_priv->fbc.active;
 407 }
 408
 409 static void intel_fbc_work_fn(struct work_struct *__work)
 410 {
 411         struct drm_i915_private *dev_priv =
 412                 container_of(__work, struct drm_i915_private, fbc.work.work);
 413         struct intel_fbc *fbc = &dev_priv->fbc;
 414         struct intel_fbc_work *work = &fbc->work;
 415         struct intel_crtc *crtc = fbc->crtc;
 416         struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe];
 417
 418         if (drm_crtc_vblank_get(&crtc->base)) {
 419                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 420                           pipe_name(crtc->pipe));
 421
 422                 mutex_lock(&fbc->lock);
 423                 work->scheduled = false;
 424                 mutex_unlock(&fbc->lock);
 425                 return;
 426         }
 427
 428 retry:
 429         /* Delay the actual enabling to let pageflipping cease and the
 430          * display to settle before starting the compression. Note that
 431          * this delay also serves a second purpose: it allows for a
 432          * vblank to pass after disabling the FBC before we attempt
 433          * to modify the control registers.
 434          *
 435          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 436          *
 437          * It is also worth mentioning that since work->scheduled_vblank can be
 438          * updated multiple times by the other threads, hitting the timeout is
 439          * not an error condition. We'll just end up hitting the "goto retry"
 440          * case below.
 441          */
 442         wait_event_timeout(vblank->queue,
 443                 drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
 444                 msecs_to_jiffies(50));
 445
 446         mutex_lock(&fbc->lock);
 447
 448         /* Were we cancelled? */
 449         if (!work->scheduled)
 450                 goto out;
 451
 452         /* Were we delayed again while this function was sleeping? */
 453         if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
 454                 mutex_unlock(&fbc->lock);
 455                 goto retry;
 456         }
 457
 458         intel_fbc_hw_activate(dev_priv);
 459
 460         work->scheduled = false;
 461
 462 out:
 463         mutex_unlock(&fbc->lock);
 464         drm_crtc_vblank_put(&crtc->base);
 465 }
 466
 467 static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
 468 {
 469         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 470         struct intel_fbc *fbc = &dev_priv->fbc;
 471         struct intel_fbc_work *work = &fbc->work;
 472
 473         WARN_ON(!mutex_is_locked(&fbc->lock));
 474
 475         if (drm_crtc_vblank_get(&crtc->base)) {
 476                 DRM_ERROR("vblank not available for FBC on pipe %c\n",
 477                           pipe_name(crtc->pipe));
 478                 return;
 479         }
 480
 481         /* It is useless to call intel_fbc_cancel_work() or cancel_work() in
 482          * this function since we're not releasing fbc.lock, so it won't have an
 483          * opportunity to grab it to discover that it was cancelled. So we just
 484          * update the expected jiffy count. */
 485         work->scheduled = true;
 486         work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
 487         drm_crtc_vblank_put(&crtc->base);
 488
 489         schedule_work(&work->work);
 490 }
 491
 492 static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
 493 {
 494         struct intel_fbc *fbc = &dev_priv->fbc;
 495
 496         WARN_ON(!mutex_is_locked(&fbc->lock));
 497
 498         /* Calling cancel_work() here won't help due to the fact that the work
 499          * function grabs fbc->lock. Just set scheduled to false so the work
 500          * function can know it was cancelled. */
 501         fbc->work.scheduled = false;
 502
 503         if (fbc->active)
 504                 intel_fbc_hw_deactivate(dev_priv);
 505 }
 506
 507 static bool multiple_pipes_ok(struct intel_crtc *crtc,
 508                               struct intel_plane_state *plane_state)
 509 {
 510         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 511         struct intel_fbc *fbc = &dev_priv->fbc;
 512         enum pipe pipe = crtc->pipe;
 513
 514         /* Don't even bother tracking anything we don't need. */
 515         if (!no_fbc_on_multiple_pipes(dev_priv))
 516                 return true;
 517
 518         if (plane_state->base.visible)
 519                 fbc->visible_pipes_mask |= (1 << pipe);
 520         else
 521                 fbc->visible_pipes_mask &= ~(1 << pipe);
 522
 523         return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
 524 }
 525
 526 static int find_compression_threshold(struct drm_i915_private *dev_priv,
 527                                       struct drm_mm_node *node,
 528                                       int size,
 529                                       int fb_cpp)
 530 {
 531         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 532         int compression_threshold = 1;
 533         int ret;
 534         u64 end;
 535
 536         /* The FBC hardware for BDW/SKL doesn't have access to the stolen
 537          * reserved range size, so it always assumes the maximum (8mb) is used.
 538          * If we enable FBC using a CFB on that memory range we'll get FIFO
 539          * underruns, even if that range is not reserved by the BIOS. */
 540         if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
 541                 end = ggtt->stolen_size - 8 * 1024 * 1024;
 542         else
 543                 end = U64_MAX;
 544
 545         /* HACK: This code depends on what we will do in *_enable_fbc. If that
 546          * code changes, this code needs to change as well.
 547          *
 548          * The enable_fbc code will attempt to use one of our 2 compression
 549          * thresholds, therefore, in that case, we only have 1 resort.
 550          */
 551
 552         /* Try to over-allocate to reduce reallocations and fragmentation. */
 553         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
 554                                                    4096, 0, end);
 555         if (ret == 0)
 556                 return compression_threshold;
 557
 558 again:
 559         /* HW's ability to limit the CFB is 1:4 */
 560         if (compression_threshold > 4 ||
 561             (fb_cpp == 2 && compression_threshold == 2))
 562                 return 0;
 563
 564         ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
 565                                                    4096, 0, end);
 566         if (ret && INTEL_GEN(dev_priv) <= 4) {
 567                 return 0;
 568         } else if (ret) {
 569                 compression_threshold <<= 1;
 570                 goto again;
 571         } else {
 572                 return compression_threshold;
 573         }
 574 }
 575
 576 static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
 577 {
 578         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 579         struct intel_fbc *fbc = &dev_priv->fbc;
 580         struct drm_mm_node *uninitialized_var(compressed_llb);
 581         int size, fb_cpp, ret;
 582
 583         WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
 584
 585         size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
 586         fb_cpp = fbc->state_cache.fb.format->cpp[0];
 587
 588         ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
 589                                          size, fb_cpp);
 590         if (!ret)
 591                 goto err_llb;
 592         else if (ret > 1) {
 593                 DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
 594
 595         }
 596
 597         fbc->threshold = ret;
 598
 599         if (INTEL_GEN(dev_priv) >= 5)
 600                 I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
 601         else if (IS_GM45(dev_priv)) {
 602                 I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
 603         } else {
 604                 compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
 605                 if (!compressed_llb)
 606                         goto err_fb;
 607
 608                 ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
 609                                                   4096, 4096);
 610                 if (ret)
 611                         goto err_fb;
 612
 613                 fbc->compressed_llb = compressed_llb;
 614
 615                 I915_WRITE(FBC_CFB_BASE,
 616                            dev_priv->mm.stolen_base + fbc->compressed_fb.start);
 617                 I915_WRITE(FBC_LL_BASE,
 618                            dev_priv->mm.stolen_base + compressed_llb->start);
 619         }
 620
 621         DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
 622                       fbc->compressed_fb.size, fbc->threshold);
 623
 624         return 0;
 625
 626 err_fb:
 627         kfree(compressed_llb);
 628         i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 629 err_llb:
 630         if (drm_mm_initialized(&dev_priv->mm.stolen))
 631                 pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
 632         return -ENOSPC;
 633 }
 634
 635 static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 636 {
 637         struct intel_fbc *fbc = &dev_priv->fbc;
 638
 639         if (drm_mm_node_allocated(&fbc->compressed_fb))
 640                 i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
 641
 642         if (fbc->compressed_llb) {
 643                 i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
 644                 kfree(fbc->compressed_llb);
 645         }
 646 }
 647
 648 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
 649 {
 650         struct intel_fbc *fbc = &dev_priv->fbc;
 651
 652         if (!fbc_supported(dev_priv))
 653                 return;
 654
 655         mutex_lock(&fbc->lock);
 656         __intel_fbc_cleanup_cfb(dev_priv);
 657         mutex_unlock(&fbc->lock);
 658 }
 659
 660 static bool stride_is_valid(struct drm_i915_private *dev_priv,
 661                             unsigned int stride)
 662 {
 663         /* These should have been caught earlier. */
 664         WARN_ON(stride < 512);
 665         WARN_ON((stride & (64 - 1)) != 0);
 666
 667         /* Below are the additional FBC restrictions. */
 668
 669         if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
 670                 return stride == 4096 || stride == 8192;
 671
 672         if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
 673                 return false;
 674
 675         if (stride > 16384)
 676                 return false;
 677
 678         return true;
 679 }
 680
 681 static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
 682                                   uint32_t pixel_format)
 683 {
 684         switch (pixel_format) {
 685         case DRM_FORMAT_XRGB8888:
 686         case DRM_FORMAT_XBGR8888:
 687                 return true;
 688         case DRM_FORMAT_XRGB1555:
 689         case DRM_FORMAT_RGB565:
 690                 /* 16bpp not supported on gen2 */
 691                 if (IS_GEN2(dev_priv))
 692                         return false;
 693                 /* WaFbcOnly1to1Ratio:ctg */
 694                 if (IS_G4X(dev_priv))
 695                         return false;
 696                 return true;
 697         default:
 698                 return false;
 699         }
 700 }
 701
 702 /*
 703  * For some reason, the hardware tracking starts looking at whatever we
 704  * programmed as the display plane base address register. It does not look at
 705  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 706  * variables instead of just looking at the pipe/plane size.
 707  */
 708 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
 709 {
 710         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 711         struct intel_fbc *fbc = &dev_priv->fbc;
 712         unsigned int effective_w, effective_h, max_w, max_h;
 713
 714         if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
 715                 max_w = 4096;
 716                 max_h = 4096;
 717         } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 718                 max_w = 4096;
 719                 max_h = 2048;
 720         } else {
 721                 max_w = 2048;
 722                 max_h = 1536;
 723         }
 724
 725         intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
 726                                         &effective_h);
 727         effective_w += crtc->adjusted_x;
 728         effective_h += crtc->adjusted_y;
 729
 730         return effective_w <= max_w && effective_h <= max_h;
 731 }
 732
 733 static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
 734                                          struct intel_crtc_state *crtc_state,
 735                                          struct intel_plane_state *plane_state)
 736 {
 737         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 738         struct intel_fbc *fbc = &dev_priv->fbc;
 739         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 740         struct drm_framebuffer *fb = plane_state->base.fb;
 741
 742         cache->vma = NULL;
 743
 744         cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
 745         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 746                 cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
 747
 748         cache->plane.rotation = plane_state->base.rotation;
 749         cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
 750         cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
 751         cache->plane.visible = plane_state->base.visible;
 752
 753         if (!cache->plane.visible)
 754                 return;
 755
 756         cache->fb.format = fb->format;
 757         cache->fb.stride = fb->pitches[0];
 758
 759         cache->vma = plane_state->vma;
 760 }
 761
 762 static bool intel_fbc_can_activate(struct intel_crtc *crtc)
 763 {
 764         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 765         struct intel_fbc *fbc = &dev_priv->fbc;
 766         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 767
 768         /* We don't need to use a state cache here since this information is
 769          * global for all CRTC.
 770          */
 771         if (fbc->underrun_detected) {
 772                 fbc->no_fbc_reason = "underrun detected";
 773                 return false;
 774         }
 775
 776         if (!cache->vma) {
 777                 fbc->no_fbc_reason = "primary plane not visible";
 778                 return false;
 779         }
 780
 781         if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) ||
 782             (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) {
 783                 fbc->no_fbc_reason = "incompatible mode";
 784                 return false;
 785         }
 786
 787         if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
 788                 fbc->no_fbc_reason = "mode too large for compression";
 789                 return false;
 790         }
 791
 792         /* The use of a CPU fence is mandatory in order to detect writes
 793          * by the CPU to the scanout and trigger updates to the FBC.
 794          *
 795          * Note that is possible for a tiled surface to be unmappable (and
 796          * so have no fence associated with it) due to aperture constaints
 797          * at the time of pinning.
 798          */
 799         if (!cache->vma->fence) {
 800                 fbc->no_fbc_reason = "framebuffer not tiled or fenced";
 801                 return false;
 802         }
 803         if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
 804             cache->plane.rotation != DRM_MODE_ROTATE_0) {
 805                 fbc->no_fbc_reason = "rotation unsupported";
 806                 return false;
 807         }
 808
 809         if (!stride_is_valid(dev_priv, cache->fb.stride)) {
 810                 fbc->no_fbc_reason = "framebuffer stride not supported";
 811                 return false;
 812         }
 813
 814         if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
 815                 fbc->no_fbc_reason = "pixel format is invalid";
 816                 return false;
 817         }
 818
 819         /* WaFbcExceedCdClockThreshold:hsw,bdw */
 820         if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
 821             cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
 822                 fbc->no_fbc_reason = "pixel rate is too big";
 823                 return false;
 824         }
 825
 826         /* It is possible for the required CFB size change without a
 827          * crtc->disable + crtc->enable since it is possible to change the
 828          * stride without triggering a full modeset. Since we try to
 829          * over-allocate the CFB, there's a chance we may keep FBC enabled even
 830          * if this happens, but if we exceed the current CFB size we'll have to
 831          * disable FBC. Notice that it would be possible to disable FBC, wait
 832          * for a frame, free the stolen node, then try to reenable FBC in case
 833          * we didn't get any invalidate/deactivate calls, but this would require
 834          * a lot of tracking just for a specific case. If we conclude it's an
 835          * important case, we can implement it later. */
 836         if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
 837             fbc->compressed_fb.size * fbc->threshold) {
 838                 fbc->no_fbc_reason = "CFB requirements changed";
 839                 return false;
 840         }
 841
 842         return true;
 843 }
 844
 845 static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
 846 {
 847         struct intel_fbc *fbc = &dev_priv->fbc;
 848
 849         if (intel_vgpu_active(dev_priv)) {
 850                 fbc->no_fbc_reason = "VGPU is active";
 851                 return false;
 852         }
 853
 854         if (!i915.enable_fbc) {
 855                 fbc->no_fbc_reason = "disabled per module param or by default";
 856                 return false;
 857         }
 858
 859         if (fbc->underrun_detected) {
 860                 fbc->no_fbc_reason = "underrun detected";
 861                 return false;
 862         }
 863
 864         return true;
 865 }
 866
 867 static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
 868                                      struct intel_fbc_reg_params *params)
 869 {
 870         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 871         struct intel_fbc *fbc = &dev_priv->fbc;
 872         struct intel_fbc_state_cache *cache = &fbc->state_cache;
 873
 874         /* Since all our fields are integer types, use memset here so the
 875          * comparison function can rely on memcmp because the padding will be
 876          * zero. */
 877         memset(params, 0, sizeof(*params));
 878
 879         params->vma = cache->vma;
 880
 881         params->crtc.pipe = crtc->pipe;
 882         params->crtc.plane = crtc->plane;
 883         params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);
 884
 885         params->fb.format = cache->fb.format;
 886         params->fb.stride = cache->fb.stride;
 887
 888         params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
 889 }
 890
 891 static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
 892                                        struct intel_fbc_reg_params *params2)
 893 {
 894         /* We can use this since intel_fbc_get_reg_params() does a memset. */
 895         return memcmp(params1, params2, sizeof(*params1)) == 0;
 896 }
 897
 898 void intel_fbc_pre_update(struct intel_crtc *crtc,
 899                           struct intel_crtc_state *crtc_state,
 900                           struct intel_plane_state *plane_state)
 901 {
 902         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 903         struct intel_fbc *fbc = &dev_priv->fbc;
 904
 905         if (!fbc_supported(dev_priv))
 906                 return;
 907
 908         mutex_lock(&fbc->lock);
 909
 910         if (!multiple_pipes_ok(crtc, plane_state)) {
 911                 fbc->no_fbc_reason = "more than one pipe active";
 912                 goto deactivate;
 913         }
 914
 915         if (!fbc->enabled || fbc->crtc != crtc)
 916                 goto unlock;
 917
 918         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
 919
 920 deactivate:
 921         intel_fbc_deactivate(dev_priv);
 922 unlock:
 923         mutex_unlock(&fbc->lock);
 924 }
 925
 926 static void __intel_fbc_post_update(struct intel_crtc *crtc)
 927 {
 928         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 929         struct intel_fbc *fbc = &dev_priv->fbc;
 930         struct intel_fbc_reg_params old_params;
 931
 932         WARN_ON(!mutex_is_locked(&fbc->lock));
 933
 934         if (!fbc->enabled || fbc->crtc != crtc)
 935                 return;
 936
 937         if (!intel_fbc_can_activate(crtc)) {
 938                 WARN_ON(fbc->active);
 939                 return;
 940         }
 941
 942         old_params = fbc->params;
 943         intel_fbc_get_reg_params(crtc, &fbc->params);
 944
 945         /* If the scanout has not changed, don't modify the FBC settings.
 946          * Note that we make the fundamental assumption that the fb->obj
 947          * cannot be unpinned (and have its GTT offset and fence revoked)
 948          * without first being decoupled from the scanout and FBC disabled.
 949          */
 950         if (fbc->active &&
 951             intel_fbc_reg_params_equal(&old_params, &fbc->params))
 952                 return;
 953
 954         intel_fbc_deactivate(dev_priv);
 955         intel_fbc_schedule_activation(crtc);
 956         fbc->no_fbc_reason = "FBC enabled (active or scheduled)";
 957 }
 958
 959 void intel_fbc_post_update(struct intel_crtc *crtc)
 960 {
 961         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 962         struct intel_fbc *fbc = &dev_priv->fbc;
 963
 964         if (!fbc_supported(dev_priv))
 965                 return;
 966
 967         mutex_lock(&fbc->lock);
 968         __intel_fbc_post_update(crtc);
 969         mutex_unlock(&fbc->lock);
 970 }
 971
 972 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
 973 {
 974         if (fbc->enabled)
 975                 return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
 976         else
 977                 return fbc->possible_framebuffer_bits;
 978 }
 979
 980 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
 981                           unsigned int frontbuffer_bits,
 982                           enum fb_op_origin origin)
 983 {
 984         struct intel_fbc *fbc = &dev_priv->fbc;
 985
 986         if (!fbc_supported(dev_priv))
 987                 return;
 988
 989         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
 990                 return;
 991
 992         mutex_lock(&fbc->lock);
 993
 994         fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
 995
 996         if (fbc->enabled && fbc->busy_bits)
 997                 intel_fbc_deactivate(dev_priv);
 998
 999         mutex_unlock(&fbc->lock);
1000 }
1001
1002 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1003                      unsigned int frontbuffer_bits, enum fb_op_origin origin)
1004 {
1005         struct intel_fbc *fbc = &dev_priv->fbc;
1006
1007         if (!fbc_supported(dev_priv))
1008                 return;
1009
1010         mutex_lock(&fbc->lock);
1011
1012         fbc->busy_bits &= ~frontbuffer_bits;
1013
1014         if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1015                 goto out;
1016
1017         if (!fbc->busy_bits && fbc->enabled &&
1018             (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1019                 if (fbc->active)
1020                         intel_fbc_recompress(dev_priv);
1021                 else
1022                         __intel_fbc_post_update(fbc->crtc);
1023         }
1024
1025 out:
1026         mutex_unlock(&fbc->lock);
1027 }
1028
1029 /**
1030  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
1031  * @dev_priv: i915 device instance
1032  * @state: the atomic state structure
1033  *
1034  * This function looks at the proposed state for CRTCs and planes, then chooses
1035  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
1036  * true.
1037  *
1038  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
1039  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
1040  */
1041 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1042                            struct drm_atomic_state *state)
1043 {
1044         struct intel_fbc *fbc = &dev_priv->fbc;
1045         struct drm_plane *plane;
1046         struct drm_plane_state *plane_state;
1047         bool crtc_chosen = false;
1048         int i;
1049
1050         mutex_lock(&fbc->lock);
1051
1052         /* Does this atomic commit involve the CRTC currently tied to FBC? */
1053         if (fbc->crtc &&
1054             !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base))
1055                 goto out;
1056
1057         if (!intel_fbc_can_enable(dev_priv))
1058                 goto out;
1059
1060         /* Simply choose the first CRTC that is compatible and has a visible
1061          * plane. We could go for fancier schemes such as checking the plane
1062          * size, but this would just affect the few platforms that don't tie FBC
1063          * to pipe or plane A. */
1064         for_each_new_plane_in_state(state, plane, plane_state, i) {
1065                 struct intel_plane_state *intel_plane_state =
1066                         to_intel_plane_state(plane_state);
1067                 struct intel_crtc_state *intel_crtc_state;
1068                 struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc);
1069
1070                 if (!intel_plane_state->base.visible)
1071                         continue;
1072
1073                 if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
1074                         continue;
1075
1076                 if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
1077                         continue;
1078
1079                 intel_crtc_state = to_intel_crtc_state(
1080                         drm_atomic_get_existing_crtc_state(state, &crtc->base));
1081
1082                 intel_crtc_state->enable_fbc = true;
1083                 crtc_chosen = true;
1084                 break;
1085         }
1086
1087         if (!crtc_chosen)
1088                 fbc->no_fbc_reason = "no suitable CRTC for FBC";
1089
1090 out:
1091         mutex_unlock(&fbc->lock);
1092 }
1093
1094 /**
1095  * intel_fbc_enable: tries to enable FBC on the CRTC
1096  * @crtc: the CRTC
1097  * @crtc_state: corresponding &drm_crtc_state for @crtc
1098  * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1099  *
1100  * This function checks if the given CRTC was chosen for FBC, then enables it if
1101  * possible. Notice that it doesn't activate FBC. It is valid to call
1102  * intel_fbc_enable multiple times for the same pipe without an
1103  * intel_fbc_disable in the middle, as long as it is deactivated.
1104  */
1105 void intel_fbc_enable(struct intel_crtc *crtc,
1106                       struct intel_crtc_state *crtc_state,
1107                       struct intel_plane_state *plane_state)
1108 {
1109         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1110         struct intel_fbc *fbc = &dev_priv->fbc;
1111
1112         if (!fbc_supported(dev_priv))
1113                 return;
1114
1115         mutex_lock(&fbc->lock);
1116
1117         if (fbc->enabled) {
1118                 WARN_ON(fbc->crtc == NULL);
1119                 if (fbc->crtc == crtc) {
1120                         WARN_ON(!crtc_state->enable_fbc);
1121                         WARN_ON(fbc->active);
1122                 }
1123                 goto out;
1124         }
1125
1126         if (!crtc_state->enable_fbc)
1127                 goto out;
1128
1129         WARN_ON(fbc->active);
1130         WARN_ON(fbc->crtc != NULL);
1131
1132         intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1133         if (intel_fbc_alloc_cfb(crtc)) {
1134                 fbc->no_fbc_reason = "not enough stolen memory";
1135                 goto out;
1136         }
1137
1138         DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1139         fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1140
1141         fbc->enabled = true;
1142         fbc->crtc = crtc;
1143 out:
1144         mutex_unlock(&fbc->lock);
1145 }
1146
1147 /**
1148  * __intel_fbc_disable - disable FBC
1149  * @dev_priv: i915 device instance
1150  *
1151  * This is the low level function that actually disables FBC. Callers should
1152  * grab the FBC lock.
1153  */
1154 static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
1155 {
1156         struct intel_fbc *fbc = &dev_priv->fbc;
1157         struct intel_crtc *crtc = fbc->crtc;
1158
1159         WARN_ON(!mutex_is_locked(&fbc->lock));
1160         WARN_ON(!fbc->enabled);
1161         WARN_ON(fbc->active);
1162         WARN_ON(crtc->active);
1163
1164         DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1165
1166         __intel_fbc_cleanup_cfb(dev_priv);
1167
1168         fbc->enabled = false;
1169         fbc->crtc = NULL;
1170 }
1171
1172 /**
1173  * intel_fbc_disable - disable FBC if it's associated with crtc
1174  * @crtc: the CRTC
1175  *
1176  * This function disables FBC if it's associated with the provided CRTC.
1177  */
1178 void intel_fbc_disable(struct intel_crtc *crtc)
1179 {
1180         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1181         struct intel_fbc *fbc = &dev_priv->fbc;
1182
1183         if (!fbc_supported(dev_priv))
1184                 return;
1185
1186         mutex_lock(&fbc->lock);
1187         if (fbc->crtc == crtc)
1188                 __intel_fbc_disable(dev_priv);
1189         mutex_unlock(&fbc->lock);
1190
1191         cancel_work_sync(&fbc->work.work);
1192 }
1193
1194 /**
1195  * intel_fbc_global_disable - globally disable FBC
1196  * @dev_priv: i915 device instance
1197  *
1198  * This function disables FBC regardless of which CRTC is associated with it.
1199  */
1200 void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1201 {
1202         struct intel_fbc *fbc = &dev_priv->fbc;
1203
1204         if (!fbc_supported(dev_priv))
1205                 return;
1206
1207         mutex_lock(&fbc->lock);
1208         if (fbc->enabled)
1209                 __intel_fbc_disable(dev_priv);
1210         mutex_unlock(&fbc->lock);
1211
1212         cancel_work_sync(&fbc->work.work);
1213 }
1214
1215 static void intel_fbc_underrun_work_fn(struct work_struct *work)
1216 {
1217         struct drm_i915_private *dev_priv =
1218                 container_of(work, struct drm_i915_private, fbc.underrun_work);
1219         struct intel_fbc *fbc = &dev_priv->fbc;
1220
1221         mutex_lock(&fbc->lock);
1222
1223         /* Maybe we were scheduled twice. */
1224         if (fbc->underrun_detected)
1225                 goto out;
1226
1227         DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
1228         fbc->underrun_detected = true;
1229
1230         intel_fbc_deactivate(dev_priv);
1231 out:
1232         mutex_unlock(&fbc->lock);
1233 }
1234
1235 /**
1236  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
1237  * @dev_priv: i915 device instance
1238  *
1239  * Without FBC, most underruns are harmless and don't really cause too many
1240  * problems, except for an annoying message on dmesg. With FBC, underruns can
1241  * become black screens or even worse, especially when paired with bad
1242  * watermarks. So in order for us to be on the safe side, completely disable FBC
1243  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
1244  * already suggests that watermarks may be bad, so try to be as safe as
1245  * possible.
1246  *
1247  * This function is called from the IRQ handler.
1248  */
1249 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
1250 {
1251         struct intel_fbc *fbc = &dev_priv->fbc;
1252
1253         if (!fbc_supported(dev_priv))
1254                 return;
1255
1256         /* There's no guarantee that underrun_detected won't be set to true
1257          * right after this check and before the work is scheduled, but that's
1258          * not a problem since we'll check it again under the work function
1259          * while FBC is locked. This check here is just to prevent us from
1260          * unnecessarily scheduling the work, and it relies on the fact that we
1261          * never switch underrun_detect back to false after it's true. */
1262         if (READ_ONCE(fbc->underrun_detected))
1263                 return;
1264
1265         schedule_work(&fbc->underrun_work);
1266 }
1267
1268 /**
1269  * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
1270  * @dev_priv: i915 device instance
1271  *
1272  * The FBC code needs to track CRTC visibility since the older platforms can't
1273  * have FBC enabled while multiple pipes are used. This function does the
1274  * initial setup at driver load to make sure FBC is matching the real hardware.
1275  */
1276 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
1277 {
1278         struct intel_crtc *crtc;
1279
1280         /* Don't even bother tracking anything if we don't need. */
1281         if (!no_fbc_on_multiple_pipes(dev_priv))
1282                 return;
1283
1284         for_each_intel_crtc(&dev_priv->drm, crtc)
1285                 if (intel_crtc_active(crtc) &&
1286                     crtc->base.primary->state->visible)
1287                         dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
1288 }
1289
1290 /*
1291  * The DDX driver changes its behavior depending on the value it reads from
1292  * i915.enable_fbc, so sanitize it by translating the default value into either
1293  * 0 or 1 in order to allow it to know what's going on.
1294  *
1295  * Notice that this is done at driver initialization and we still allow user
1296  * space to change the value during runtime without sanitizing it again. IGT
1297  * relies on being able to change i915.enable_fbc at runtime.
1298  */
1299 static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
1300 {
1301         if (i915.enable_fbc >= 0)
1302                 return !!i915.enable_fbc;
1303
1304         if (!HAS_FBC(dev_priv))
1305                 return 0;
1306
1307         if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1308                 return 1;
1309
1310         return 0;
1311 }
1312
1313 static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
1314 {
1315         /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
1316         if (intel_vtd_active() &&
1317             (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
1318                 DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
1319                 return true;
1320         }
1321
1322         return false;
1323 }
1324
1325 /**
1326  * intel_fbc_init - Initialize FBC
1327  * @dev_priv: the i915 device
1328  *
1329  * This function might be called during PM init process.
1330  */
1331 void intel_fbc_init(struct drm_i915_private *dev_priv)
1332 {
1333         struct intel_fbc *fbc = &dev_priv->fbc;
1334         enum pipe pipe;
1335
1336         INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
1337         INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1338         mutex_init(&fbc->lock);
1339         fbc->enabled = false;
1340         fbc->active = false;
1341         fbc->work.scheduled = false;
1342
1343         if (need_fbc_vtd_wa(dev_priv))
1344                 mkwrite_device_info(dev_priv)->has_fbc = false;
1345
1346         i915.enable_fbc = intel_sanitize_fbc_option(dev_priv);
1347         DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc);
1348
1349         if (!HAS_FBC(dev_priv)) {
1350                 fbc->no_fbc_reason = "unsupported by this chipset";
1351                 return;
1352         }
1353
1354         for_each_pipe(dev_priv, pipe) {
1355                 fbc->possible_framebuffer_bits |=
1356                                 INTEL_FRONTBUFFER_PRIMARY(pipe);
1357
1358                 if (fbc_on_pipe_a_only(dev_priv))
1359                         break;
1360         }
1361
1362         /* This value was pulled out of someone's hat */
1363         if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
1364                 I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
1365
1366         /* We still don't have any sort of hardware state readout for FBC, so
1367          * deactivate it in case the BIOS activated it to make sure software
1368          * matches the hardware state. */
1369         if (intel_fbc_hw_is_active(dev_priv))
1370                 intel_fbc_hw_deactivate(dev_priv);
1371 }