2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
142 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
143 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define CTX_LRI_HEADER_0 0x01
160 #define CTX_CONTEXT_CONTROL 0x02
161 #define CTX_RING_HEAD 0x04
162 #define CTX_RING_TAIL 0x06
163 #define CTX_RING_BUFFER_START 0x08
164 #define CTX_RING_BUFFER_CONTROL 0x0a
165 #define CTX_BB_HEAD_U 0x0c
166 #define CTX_BB_HEAD_L 0x0e
167 #define CTX_BB_STATE 0x10
168 #define CTX_SECOND_BB_HEAD_U 0x12
169 #define CTX_SECOND_BB_HEAD_L 0x14
170 #define CTX_SECOND_BB_STATE 0x16
171 #define CTX_BB_PER_CTX_PTR 0x18
172 #define CTX_RCS_INDIRECT_CTX 0x1a
173 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
174 #define CTX_LRI_HEADER_1 0x21
175 #define CTX_CTX_TIMESTAMP 0x22
176 #define CTX_PDP3_UDW 0x24
177 #define CTX_PDP3_LDW 0x26
178 #define CTX_PDP2_UDW 0x28
179 #define CTX_PDP2_LDW 0x2a
180 #define CTX_PDP1_UDW 0x2c
181 #define CTX_PDP1_LDW 0x2e
182 #define CTX_PDP0_UDW 0x30
183 #define CTX_PDP0_LDW 0x32
184 #define CTX_LRI_HEADER_2 0x41
185 #define CTX_R_PWR_CLK_STATE 0x42
186 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
188 #define GEN8_CTX_VALID (1<<0)
189 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
190 #define GEN8_CTX_FORCE_RESTORE (1<<2)
191 #define GEN8_CTX_L3LLC_COHERENT (1<<5)
192 #define GEN8_CTX_PRIVILEGE (1<<8)
194 #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
195 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
196 (reg_state)[(pos)+1] = (val); \
199 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
200 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
201 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
202 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
205 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
206 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
207 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
212 FAULT_AND_HALT, /* Debug only */
214 FAULT_AND_CONTINUE /* Unsupported */
216 #define GEN8_CTX_ID_SHIFT 32
217 #define GEN8_CTX_ID_WIDTH 21
218 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
219 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
221 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
222 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
224 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
225 struct intel_engine_cs *engine);
226 static int intel_lr_context_pin(struct i915_gem_context *ctx,
227 struct intel_engine_cs *engine);
230 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
231 * @dev_priv: i915 device private
232 * @enable_execlists: value of i915.enable_execlists module parameter.
234 * Only certain platforms support Execlists (the prerequisites being
235 * support for Logical Ring Contexts and Aliasing PPGTT or better).
237 * Return: 1 if Execlists is supported and has to be enabled.
239 int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
241 /* On platforms with execlist available, vGPU will only
242 * support execlist mode, no ring buffer mode.
244 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
247 if (INTEL_GEN(dev_priv) >= 9)
250 if (enable_execlists == 0)
253 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
254 USES_PPGTT(dev_priv) &&
255 i915.use_mmio_flip >= 0)
262 logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
264 struct drm_i915_private *dev_priv = engine->i915;
266 if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
267 engine->idle_lite_restore_wa = ~0;
269 engine->disable_lite_restore_wa = (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
270 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
271 (engine->id == VCS || engine->id == VCS2);
273 engine->ctx_desc_template = GEN8_CTX_VALID;
274 if (IS_GEN8(dev_priv))
275 engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
276 engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
278 /* TODO: WaDisableLiteRestore when we start using semaphore
279 * signalling between Command Streamers */
280 /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */
282 /* WaEnableForceRestoreInCtxtDescForVCS:skl */
283 /* WaEnableForceRestoreInCtxtDescForVCS:bxt */
284 if (engine->disable_lite_restore_wa)
285 engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
289 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
290 * descriptor for a pinned context
291 * @ctx: Context to work on
292 * @engine: Engine the descriptor will be used with
294 * The context descriptor encodes various attributes of a context,
295 * including its GTT address and some flags. Because it's fairly
296 * expensive to calculate, we'll just do it once and cache the result,
297 * which remains valid until the context is unpinned.
299 * This is what a descriptor looks like, from LSB to MSB::
301 * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
302 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
303 * bits 32-52: ctx ID, a globally unique tag
304 * bits 53-54: mbz, reserved for use by hardware
305 * bits 55-63: group ID, currently unused and set to 0
308 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
309 struct intel_engine_cs *engine)
311 struct intel_context *ce = &ctx->engine[engine->id];
314 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
316 desc = ctx->desc_template; /* bits 3-4 */
317 desc |= engine->ctx_desc_template; /* bits 0-11 */
318 desc |= ce->lrc_vma->node.start + LRC_PPHWSP_PN * PAGE_SIZE;
320 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
325 uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
326 struct intel_engine_cs *engine)
328 return ctx->engine[engine->id].lrc_desc;
331 static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
332 struct drm_i915_gem_request *rq1)
335 struct intel_engine_cs *engine = rq0->engine;
336 struct drm_i915_private *dev_priv = rq0->i915;
340 desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine);
341 rq1->elsp_submitted++;
346 desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine);
347 rq0->elsp_submitted++;
349 /* You must always write both descriptors in the order below. */
350 I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1]));
351 I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1]));
353 I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0]));
354 /* The context is automatically loaded after the following */
355 I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0]));
357 /* ELSP is a wo register, use another nearby reg for posting */
358 POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine));
362 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
364 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
365 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
366 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
367 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
370 static void execlists_update_context(struct drm_i915_gem_request *rq)
372 struct intel_engine_cs *engine = rq->engine;
373 struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
374 uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state;
376 reg_state[CTX_RING_TAIL+1] = intel_ring_offset(rq->ring, rq->tail);
378 /* True 32b PPGTT with dynamic page allocation: update PDP
379 * registers and point the unallocated PDPs to scratch page.
380 * PML4 is allocated during ppgtt init, so this is not needed
383 if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
384 execlists_update_context_pdps(ppgtt, reg_state);
387 static void execlists_elsp_submit_contexts(struct drm_i915_gem_request *rq0,
388 struct drm_i915_gem_request *rq1)
390 struct drm_i915_private *dev_priv = rq0->i915;
391 unsigned int fw_domains = rq0->engine->fw_domains;
393 execlists_update_context(rq0);
396 execlists_update_context(rq1);
398 spin_lock_irq(&dev_priv->uncore.lock);
399 intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
401 execlists_elsp_write(rq0, rq1);
403 intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
404 spin_unlock_irq(&dev_priv->uncore.lock);
407 static inline void execlists_context_status_change(
408 struct drm_i915_gem_request *rq,
409 unsigned long status)
412 * Only used when GVT-g is enabled now. When GVT-g is disabled,
413 * The compiler should eliminate this function as dead-code.
415 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
418 atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);
421 static void execlists_unqueue(struct intel_engine_cs *engine)
423 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
424 struct drm_i915_gem_request *cursor, *tmp;
426 assert_spin_locked(&engine->execlist_lock);
429 * If irqs are not active generate a warning as batches that finish
430 * without the irqs may get lost and a GPU Hang may occur.
432 WARN_ON(!intel_irqs_enabled(engine->i915));
434 /* Try to read in pairs */
435 list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
439 } else if (req0->ctx == cursor->ctx) {
440 /* Same ctx: ignore first request, as second request
441 * will update tail past first request's workload */
442 cursor->elsp_submitted = req0->elsp_submitted;
443 list_del(&req0->execlist_link);
444 i915_gem_request_put(req0);
447 if (IS_ENABLED(CONFIG_DRM_I915_GVT)) {
449 * req0 (after merged) ctx requires single
450 * submission, stop picking
452 if (req0->ctx->execlists_force_single_submission)
455 * req0 ctx doesn't require single submission,
456 * but next req ctx requires, stop picking
458 if (cursor->ctx->execlists_force_single_submission)
462 WARN_ON(req1->elsp_submitted);
470 execlists_context_status_change(req0, INTEL_CONTEXT_SCHEDULE_IN);
473 execlists_context_status_change(req1,
474 INTEL_CONTEXT_SCHEDULE_IN);
476 if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
478 * WaIdleLiteRestore: make sure we never cause a lite restore
481 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
482 * resubmit the request. See gen8_emit_request() for where we
483 * prepare the padding after the end of the request.
486 req0->tail &= req0->ring->size - 1;
489 execlists_elsp_submit_contexts(req0, req1);
493 execlists_check_remove_request(struct intel_engine_cs *engine, u32 ctx_id)
495 struct drm_i915_gem_request *head_req;
497 assert_spin_locked(&engine->execlist_lock);
499 head_req = list_first_entry_or_null(&engine->execlist_queue,
500 struct drm_i915_gem_request,
503 if (WARN_ON(!head_req || (head_req->ctx_hw_id != ctx_id)))
506 WARN(head_req->elsp_submitted == 0, "Never submitted head request\n");
508 if (--head_req->elsp_submitted > 0)
511 execlists_context_status_change(head_req, INTEL_CONTEXT_SCHEDULE_OUT);
513 list_del(&head_req->execlist_link);
514 i915_gem_request_put(head_req);
520 get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
523 struct drm_i915_private *dev_priv = engine->i915;
526 read_pointer %= GEN8_CSB_ENTRIES;
528 status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer));
530 if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
533 *context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine,
540 * Check the unread Context Status Buffers and manage the submission of new
541 * contexts to the ELSP accordingly.
543 static void intel_lrc_irq_handler(unsigned long data)
545 struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
546 struct drm_i915_private *dev_priv = engine->i915;
548 unsigned int read_pointer, write_pointer;
549 u32 csb[GEN8_CSB_ENTRIES][2];
550 unsigned int csb_read = 0, i;
551 unsigned int submit_contexts = 0;
553 intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
555 status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine));
557 read_pointer = engine->next_context_status_buffer;
558 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
559 if (read_pointer > write_pointer)
560 write_pointer += GEN8_CSB_ENTRIES;
562 while (read_pointer < write_pointer) {
563 if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES))
565 csb[csb_read][0] = get_context_status(engine, ++read_pointer,
570 engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;
572 /* Update the read pointer to the old write pointer. Manual ringbuffer
573 * management ftw </sarcasm> */
574 I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine),
575 _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
576 engine->next_context_status_buffer << 8));
578 intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
580 spin_lock(&engine->execlist_lock);
582 for (i = 0; i < csb_read; i++) {
583 if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) {
584 if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) {
585 if (execlists_check_remove_request(engine, csb[i][1]))
586 WARN(1, "Lite Restored request removed from queue\n");
588 WARN(1, "Preemption without Lite Restore\n");
591 if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE |
592 GEN8_CTX_STATUS_ELEMENT_SWITCH))
594 execlists_check_remove_request(engine, csb[i][1]);
597 if (submit_contexts) {
598 if (!engine->disable_lite_restore_wa ||
599 (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE))
600 execlists_unqueue(engine);
603 spin_unlock(&engine->execlist_lock);
605 if (unlikely(submit_contexts > 2))
606 DRM_ERROR("More than two context complete events?\n");
609 static void execlists_submit_request(struct drm_i915_gem_request *request)
611 struct intel_engine_cs *engine = request->engine;
612 struct drm_i915_gem_request *cursor;
613 int num_elements = 0;
615 spin_lock_bh(&engine->execlist_lock);
617 list_for_each_entry(cursor, &engine->execlist_queue, execlist_link)
618 if (++num_elements > 2)
621 if (num_elements > 2) {
622 struct drm_i915_gem_request *tail_req;
624 tail_req = list_last_entry(&engine->execlist_queue,
625 struct drm_i915_gem_request,
628 if (request->ctx == tail_req->ctx) {
629 WARN(tail_req->elsp_submitted != 0,
630 "More than 2 already-submitted reqs queued\n");
631 list_del(&tail_req->execlist_link);
632 i915_gem_request_put(tail_req);
636 i915_gem_request_get(request);
637 list_add_tail(&request->execlist_link, &engine->execlist_queue);
638 request->ctx_hw_id = request->ctx->hw_id;
639 if (num_elements == 0)
640 execlists_unqueue(engine);
642 spin_unlock_bh(&engine->execlist_lock);
645 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
647 struct intel_engine_cs *engine = request->engine;
648 struct intel_context *ce = &request->ctx->engine[engine->id];
651 /* Flush enough space to reduce the likelihood of waiting after
652 * we start building the request - in which case we will just
653 * have to repeat work.
655 request->reserved_space += EXECLISTS_REQUEST_SIZE;
658 ret = execlists_context_deferred_alloc(request->ctx, engine);
663 request->ring = ce->ring;
665 if (i915.enable_guc_submission) {
667 * Check that the GuC has space for the request before
668 * going any further, as the i915_add_request() call
669 * later on mustn't fail ...
671 ret = i915_guc_wq_check_space(request);
676 ret = intel_lr_context_pin(request->ctx, engine);
680 ret = intel_ring_begin(request, 0);
684 if (!ce->initialised) {
685 ret = engine->init_context(request);
689 ce->initialised = true;
692 /* Note that after this point, we have committed to using
693 * this request as it is being used to both track the
694 * state of engine initialisation and liveness of the
695 * golden renderstate above. Think twice before you try
696 * to cancel/unwind this request now.
699 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
703 intel_lr_context_unpin(request->ctx, engine);
708 * intel_logical_ring_advance() - advance the tail and prepare for submission
709 * @request: Request to advance the logical ringbuffer of.
711 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
712 * really happens during submission is that the context and current tail will be placed
713 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
714 * point, the tail *inside* the context is updated and the ELSP written to.
717 intel_logical_ring_advance(struct drm_i915_gem_request *request)
719 struct intel_ring *ring = request->ring;
720 struct intel_engine_cs *engine = request->engine;
722 intel_ring_advance(ring);
723 request->tail = ring->tail;
726 * Here we add two extra NOOPs as padding to avoid
727 * lite restore of a context with HEAD==TAIL.
729 * Caller must reserve WA_TAIL_DWORDS for us!
731 intel_ring_emit(ring, MI_NOOP);
732 intel_ring_emit(ring, MI_NOOP);
733 intel_ring_advance(ring);
735 /* We keep the previous context alive until we retire the following
736 * request. This ensures that any the context object is still pinned
737 * for any residual writes the HW makes into it on the context switch
738 * into the next object following the breadcrumb. Otherwise, we may
739 * retire the context too early.
741 request->previous_context = engine->last_context;
742 engine->last_context = request->ctx;
746 void intel_execlists_cancel_requests(struct intel_engine_cs *engine)
748 struct drm_i915_gem_request *req, *tmp;
749 LIST_HEAD(cancel_list);
751 WARN_ON(!mutex_is_locked(&engine->i915->drm.struct_mutex));
753 spin_lock_bh(&engine->execlist_lock);
754 list_replace_init(&engine->execlist_queue, &cancel_list);
755 spin_unlock_bh(&engine->execlist_lock);
757 list_for_each_entry_safe(req, tmp, &cancel_list, execlist_link) {
758 list_del(&req->execlist_link);
759 i915_gem_request_put(req);
763 static int intel_lr_context_pin(struct i915_gem_context *ctx,
764 struct intel_engine_cs *engine)
766 struct drm_i915_private *dev_priv = ctx->i915;
767 struct intel_context *ce = &ctx->engine[engine->id];
772 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
777 ret = i915_gem_object_ggtt_pin(ce->state, NULL,
778 0, GEN8_LR_CONTEXT_ALIGN,
779 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
783 vaddr = i915_gem_object_pin_map(ce->state);
785 ret = PTR_ERR(vaddr);
789 lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
791 ret = intel_ring_pin(ce->ring);
795 ce->lrc_vma = i915_gem_obj_to_ggtt(ce->state);
796 intel_lr_context_descriptor_update(ctx, engine);
798 lrc_reg_state[CTX_RING_BUFFER_START+1] = ce->ring->vma->node.start;
799 ce->lrc_reg_state = lrc_reg_state;
800 ce->state->dirty = true;
802 /* Invalidate GuC TLB. */
803 if (i915.enable_guc_submission)
804 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
806 i915_gem_context_get(ctx);
810 i915_gem_object_unpin_map(ce->state);
812 i915_gem_object_ggtt_unpin(ce->state);
818 void intel_lr_context_unpin(struct i915_gem_context *ctx,
819 struct intel_engine_cs *engine)
821 struct intel_context *ce = &ctx->engine[engine->id];
823 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
824 GEM_BUG_ON(ce->pin_count == 0);
829 intel_ring_unpin(ce->ring);
831 i915_gem_object_unpin_map(ce->state);
832 i915_gem_object_ggtt_unpin(ce->state);
836 ce->lrc_reg_state = NULL;
838 i915_gem_context_put(ctx);
841 static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
844 struct intel_ring *ring = req->ring;
845 struct i915_workarounds *w = &req->i915->workarounds;
850 ret = req->engine->emit_flush(req, EMIT_BARRIER);
854 ret = intel_ring_begin(req, w->count * 2 + 2);
858 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
859 for (i = 0; i < w->count; i++) {
860 intel_ring_emit_reg(ring, w->reg[i].addr);
861 intel_ring_emit(ring, w->reg[i].value);
863 intel_ring_emit(ring, MI_NOOP);
865 intel_ring_advance(ring);
867 ret = req->engine->emit_flush(req, EMIT_BARRIER);
874 #define wa_ctx_emit(batch, index, cmd) \
876 int __index = (index)++; \
877 if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
880 batch[__index] = (cmd); \
883 #define wa_ctx_emit_reg(batch, index, reg) \
884 wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
887 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
888 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
889 * but there is a slight complication as this is applied in WA batch where the
890 * values are only initialized once so we cannot take register value at the
891 * beginning and reuse it further; hence we save its value to memory, upload a
892 * constant value with bit21 set and then we restore it back with the saved value.
893 * To simplify the WA, a constant value is formed by using the default value
894 * of this register. This shouldn't be a problem because we are only modifying
895 * it for a short period and this batch in non-premptible. We can ofcourse
896 * use additional instructions that read the actual value of the register
897 * at that time and set our bit of interest but it makes the WA complicated.
899 * This WA is also required for Gen9 so extracting as a function avoids
902 static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
906 struct drm_i915_private *dev_priv = engine->i915;
907 uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
910 * WaDisableLSQCROPERFforOCL:skl,kbl
911 * This WA is implemented in skl_init_clock_gating() but since
912 * this batch updates GEN8_L3SQCREG4 with default value we need to
913 * set this bit here to retain the WA during flush.
915 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0) ||
916 IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
917 l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
919 wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
920 MI_SRM_LRM_GLOBAL_GTT));
921 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
922 wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
923 wa_ctx_emit(batch, index, 0);
925 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
926 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
927 wa_ctx_emit(batch, index, l3sqc4_flush);
929 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
930 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
931 PIPE_CONTROL_DC_FLUSH_ENABLE));
932 wa_ctx_emit(batch, index, 0);
933 wa_ctx_emit(batch, index, 0);
934 wa_ctx_emit(batch, index, 0);
935 wa_ctx_emit(batch, index, 0);
937 wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
938 MI_SRM_LRM_GLOBAL_GTT));
939 wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
940 wa_ctx_emit(batch, index, engine->scratch.gtt_offset + 256);
941 wa_ctx_emit(batch, index, 0);
946 static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
948 uint32_t start_alignment)
950 return wa_ctx->offset = ALIGN(offset, start_alignment);
953 static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
955 uint32_t size_alignment)
957 wa_ctx->size = offset - wa_ctx->offset;
959 WARN(wa_ctx->size % size_alignment,
960 "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
961 wa_ctx->size, size_alignment);
966 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
967 * initialized at the beginning and shared across all contexts but this field
968 * helps us to have multiple batches at different offsets and select them based
969 * on a criteria. At the moment this batch always start at the beginning of the page
970 * and at this point we don't have multiple wa_ctx batch buffers.
972 * The number of WA applied are not known at the beginning; we use this field
973 * to return the no of DWORDS written.
975 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
976 * so it adds NOOPs as padding to make it cacheline aligned.
977 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
978 * makes a complete batch buffer.
980 static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
981 struct i915_wa_ctx_bb *wa_ctx,
985 uint32_t scratch_addr;
986 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
988 /* WaDisableCtxRestoreArbitration:bdw,chv */
989 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
991 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
992 if (IS_BROADWELL(engine->i915)) {
993 int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
999 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1000 /* Actual scratch location is at 128 bytes offset */
1001 scratch_addr = engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
1003 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1004 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1005 PIPE_CONTROL_GLOBAL_GTT_IVB |
1006 PIPE_CONTROL_CS_STALL |
1007 PIPE_CONTROL_QW_WRITE));
1008 wa_ctx_emit(batch, index, scratch_addr);
1009 wa_ctx_emit(batch, index, 0);
1010 wa_ctx_emit(batch, index, 0);
1011 wa_ctx_emit(batch, index, 0);
1013 /* Pad to end of cacheline */
1014 while (index % CACHELINE_DWORDS)
1015 wa_ctx_emit(batch, index, MI_NOOP);
1018 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1019 * execution depends on the length specified in terms of cache lines
1020 * in the register CTX_RCS_INDIRECT_CTX
1023 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1027 * This batch is started immediately after indirect_ctx batch. Since we ensure
1028 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1030 * The number of DWORDS written are returned using this field.
1032 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1033 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1035 static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
1036 struct i915_wa_ctx_bb *wa_ctx,
1040 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1042 /* WaDisableCtxRestoreArbitration:bdw,chv */
1043 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1045 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1047 return wa_ctx_end(wa_ctx, *offset = index, 1);
1050 static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
1051 struct i915_wa_ctx_bb *wa_ctx,
1056 struct drm_i915_private *dev_priv = engine->i915;
1057 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1059 /* WaDisableCtxRestoreArbitration:skl,bxt */
1060 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
1061 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1062 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1064 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1065 ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1070 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */
1071 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1072 wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2);
1073 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(
1074 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE));
1075 wa_ctx_emit(batch, index, MI_NOOP);
1077 /* WaClearSlmSpaceAtContextSwitch:kbl */
1078 /* Actual scratch location is at 128 bytes offset */
1079 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) {
1080 uint32_t scratch_addr
1081 = engine->scratch.gtt_offset + 2*CACHELINE_BYTES;
1083 wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
1084 wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
1085 PIPE_CONTROL_GLOBAL_GTT_IVB |
1086 PIPE_CONTROL_CS_STALL |
1087 PIPE_CONTROL_QW_WRITE));
1088 wa_ctx_emit(batch, index, scratch_addr);
1089 wa_ctx_emit(batch, index, 0);
1090 wa_ctx_emit(batch, index, 0);
1091 wa_ctx_emit(batch, index, 0);
1094 /* WaMediaPoolStateCmdInWABB:bxt */
1095 if (HAS_POOLED_EU(engine->i915)) {
1097 * EU pool configuration is setup along with golden context
1098 * during context initialization. This value depends on
1099 * device type (2x6 or 3x6) and needs to be updated based
1100 * on which subslice is disabled especially for 2x6
1101 * devices, however it is safe to load default
1102 * configuration of 3x6 device instead of masking off
1103 * corresponding bits because HW ignores bits of a disabled
1104 * subslice and drops down to appropriate config. Please
1105 * see render_state_setup() in i915_gem_render_state.c for
1106 * possible configurations, to avoid duplication they are
1107 * not shown here again.
1109 u32 eu_pool_config = 0x00777000;
1110 wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE);
1111 wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE);
1112 wa_ctx_emit(batch, index, eu_pool_config);
1113 wa_ctx_emit(batch, index, 0);
1114 wa_ctx_emit(batch, index, 0);
1115 wa_ctx_emit(batch, index, 0);
1118 /* Pad to end of cacheline */
1119 while (index % CACHELINE_DWORDS)
1120 wa_ctx_emit(batch, index, MI_NOOP);
1122 return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
1125 static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
1126 struct i915_wa_ctx_bb *wa_ctx,
1130 uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
1132 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1133 if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
1134 IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
1135 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1136 wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1137 wa_ctx_emit(batch, index,
1138 _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
1139 wa_ctx_emit(batch, index, MI_NOOP);
1142 /* WaClearTdlStateAckDirtyBits:bxt */
1143 if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) {
1144 wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
1146 wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
1147 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1149 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1);
1150 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1152 wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2);
1153 wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));
1155 wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2);
1156 /* dummy write to CS, mask bits are 0 to ensure the register is not modified */
1157 wa_ctx_emit(batch, index, 0x0);
1158 wa_ctx_emit(batch, index, MI_NOOP);
1161 /* WaDisableCtxRestoreArbitration:skl,bxt */
1162 if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) ||
1163 IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
1164 wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1166 wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1168 return wa_ctx_end(wa_ctx, *offset = index, 1);
1171 static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
1175 engine->wa_ctx.obj = i915_gem_object_create(&engine->i915->drm,
1177 if (IS_ERR(engine->wa_ctx.obj)) {
1178 DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n");
1179 ret = PTR_ERR(engine->wa_ctx.obj);
1180 engine->wa_ctx.obj = NULL;
1184 ret = i915_gem_object_ggtt_pin(engine->wa_ctx.obj, NULL,
1187 DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n",
1189 i915_gem_object_put(engine->wa_ctx.obj);
1196 static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine)
1198 if (engine->wa_ctx.obj) {
1199 i915_gem_object_ggtt_unpin(engine->wa_ctx.obj);
1200 i915_gem_object_put(engine->wa_ctx.obj);
1201 engine->wa_ctx.obj = NULL;
1205 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1211 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1213 WARN_ON(engine->id != RCS);
1215 /* update this when WA for higher Gen are added */
1216 if (INTEL_GEN(engine->i915) > 9) {
1217 DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1218 INTEL_GEN(engine->i915));
1222 /* some WA perform writes to scratch page, ensure it is valid */
1223 if (engine->scratch.obj == NULL) {
1224 DRM_ERROR("scratch page not allocated for %s\n", engine->name);
1228 ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE);
1230 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1234 page = i915_gem_object_get_dirty_page(wa_ctx->obj, 0);
1235 batch = kmap_atomic(page);
1238 if (IS_GEN8(engine->i915)) {
1239 ret = gen8_init_indirectctx_bb(engine,
1240 &wa_ctx->indirect_ctx,
1246 ret = gen8_init_perctx_bb(engine,
1252 } else if (IS_GEN9(engine->i915)) {
1253 ret = gen9_init_indirectctx_bb(engine,
1254 &wa_ctx->indirect_ctx,
1260 ret = gen9_init_perctx_bb(engine,
1269 kunmap_atomic(batch);
1271 lrc_destroy_wa_ctx_obj(engine);
1276 static void lrc_init_hws(struct intel_engine_cs *engine)
1278 struct drm_i915_private *dev_priv = engine->i915;
1280 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1281 (u32)engine->status_page.gfx_addr);
1282 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1285 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1287 struct drm_i915_private *dev_priv = engine->i915;
1288 unsigned int next_context_status_buffer_hw;
1290 lrc_init_hws(engine);
1292 I915_WRITE_IMR(engine,
1293 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1294 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1296 I915_WRITE(RING_MODE_GEN7(engine),
1297 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
1298 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1299 POSTING_READ(RING_MODE_GEN7(engine));
1302 * Instead of resetting the Context Status Buffer (CSB) read pointer to
1303 * zero, we need to read the write pointer from hardware and use its
1304 * value because "this register is power context save restored".
1305 * Effectively, these states have been observed:
1307 * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
1308 * BDW | CSB regs not reset | CSB regs reset |
1309 * CHT | CSB regs not reset | CSB regs not reset |
1313 next_context_status_buffer_hw =
1314 GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine)));
1317 * When the CSB registers are reset (also after power-up / gpu reset),
1318 * CSB write pointer is set to all 1's, which is not valid, use '5' in
1319 * this special case, so the first element read is CSB[0].
1321 if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK)
1322 next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1);
1324 engine->next_context_status_buffer = next_context_status_buffer_hw;
1325 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1327 intel_engine_init_hangcheck(engine);
1329 return intel_mocs_init_engine(engine);
1332 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1334 struct drm_i915_private *dev_priv = engine->i915;
1337 ret = gen8_init_common_ring(engine);
1341 /* We need to disable the AsyncFlip performance optimisations in order
1342 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1343 * programmed to '1' on all products.
1345 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1347 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1349 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1351 return init_workarounds_ring(engine);
1354 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1358 ret = gen8_init_common_ring(engine);
1362 return init_workarounds_ring(engine);
1365 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1367 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1368 struct intel_ring *ring = req->ring;
1369 struct intel_engine_cs *engine = req->engine;
1370 const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1373 ret = intel_ring_begin(req, num_lri_cmds * 2 + 2);
1377 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1378 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
1379 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1381 intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, i));
1382 intel_ring_emit(ring, upper_32_bits(pd_daddr));
1383 intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, i));
1384 intel_ring_emit(ring, lower_32_bits(pd_daddr));
1387 intel_ring_emit(ring, MI_NOOP);
1388 intel_ring_advance(ring);
1393 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1394 u64 offset, u32 len,
1395 unsigned int dispatch_flags)
1397 struct intel_ring *ring = req->ring;
1398 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1401 /* Don't rely in hw updating PDPs, specially in lite-restore.
1402 * Ideally, we should set Force PD Restore in ctx descriptor,
1403 * but we can't. Force Restore would be a second option, but
1404 * it is unsafe in case of lite-restore (because the ctx is
1405 * not idle). PML4 is allocated during ppgtt init so this is
1406 * not needed in 48-bit.*/
1407 if (req->ctx->ppgtt &&
1408 (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
1409 if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1410 !intel_vgpu_active(req->i915)) {
1411 ret = intel_logical_ring_emit_pdps(req);
1416 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1419 ret = intel_ring_begin(req, 4);
1423 /* FIXME(BDW): Address space and security selectors. */
1424 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 |
1426 (dispatch_flags & I915_DISPATCH_RS ?
1427 MI_BATCH_RESOURCE_STREAMER : 0));
1428 intel_ring_emit(ring, lower_32_bits(offset));
1429 intel_ring_emit(ring, upper_32_bits(offset));
1430 intel_ring_emit(ring, MI_NOOP);
1431 intel_ring_advance(ring);
1436 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1438 struct drm_i915_private *dev_priv = engine->i915;
1439 I915_WRITE_IMR(engine,
1440 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1441 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1444 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1446 struct drm_i915_private *dev_priv = engine->i915;
1447 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1450 static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode)
1452 struct intel_ring *ring = request->ring;
1456 ret = intel_ring_begin(request, 4);
1460 cmd = MI_FLUSH_DW + 1;
1462 /* We always require a command barrier so that subsequent
1463 * commands, such as breadcrumb interrupts, are strictly ordered
1464 * wrt the contents of the write cache being flushed to memory
1465 * (and thus being coherent from the CPU).
1467 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1469 if (mode & EMIT_INVALIDATE) {
1470 cmd |= MI_INVALIDATE_TLB;
1471 if (request->engine->id == VCS)
1472 cmd |= MI_INVALIDATE_BSD;
1475 intel_ring_emit(ring, cmd);
1476 intel_ring_emit(ring,
1477 I915_GEM_HWS_SCRATCH_ADDR |
1478 MI_FLUSH_DW_USE_GTT);
1479 intel_ring_emit(ring, 0); /* upper addr */
1480 intel_ring_emit(ring, 0); /* value */
1481 intel_ring_advance(ring);
1486 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1489 struct intel_ring *ring = request->ring;
1490 struct intel_engine_cs *engine = request->engine;
1491 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
1492 bool vf_flush_wa = false, dc_flush_wa = false;
1497 flags |= PIPE_CONTROL_CS_STALL;
1499 if (mode & EMIT_FLUSH) {
1500 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1501 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1502 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1503 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1506 if (mode & EMIT_INVALIDATE) {
1507 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1508 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1509 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1510 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1511 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1512 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1513 flags |= PIPE_CONTROL_QW_WRITE;
1514 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1517 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1520 if (IS_GEN9(request->i915))
1523 /* WaForGAMHang:kbl */
1524 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
1536 ret = intel_ring_begin(request, len);
1541 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1542 intel_ring_emit(ring, 0);
1543 intel_ring_emit(ring, 0);
1544 intel_ring_emit(ring, 0);
1545 intel_ring_emit(ring, 0);
1546 intel_ring_emit(ring, 0);
1550 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1551 intel_ring_emit(ring, PIPE_CONTROL_DC_FLUSH_ENABLE);
1552 intel_ring_emit(ring, 0);
1553 intel_ring_emit(ring, 0);
1554 intel_ring_emit(ring, 0);
1555 intel_ring_emit(ring, 0);
1558 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1559 intel_ring_emit(ring, flags);
1560 intel_ring_emit(ring, scratch_addr);
1561 intel_ring_emit(ring, 0);
1562 intel_ring_emit(ring, 0);
1563 intel_ring_emit(ring, 0);
1566 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1567 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL);
1568 intel_ring_emit(ring, 0);
1569 intel_ring_emit(ring, 0);
1570 intel_ring_emit(ring, 0);
1571 intel_ring_emit(ring, 0);
1574 intel_ring_advance(ring);
1579 static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
1582 * On BXT A steppings there is a HW coherency issue whereby the
1583 * MI_STORE_DATA_IMM storing the completed request's seqno
1584 * occasionally doesn't invalidate the CPU cache. Work around this by
1585 * clflushing the corresponding cacheline whenever the caller wants
1586 * the coherency to be guaranteed. Note that this cacheline is known
1587 * to be clean at this point, since we only write it in
1588 * bxt_a_set_seqno(), where we also do a clflush after the write. So
1589 * this clflush in practice becomes an invalidate operation.
1591 intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1595 * Reserve space for 2 NOOPs at the end of each request to be
1596 * used as a workaround for not being allowed to do lite
1597 * restore with HEAD==TAIL (WaIdleLiteRestore).
1599 #define WA_TAIL_DWORDS 2
1601 static int gen8_emit_request(struct drm_i915_gem_request *request)
1603 struct intel_ring *ring = request->ring;
1606 ret = intel_ring_begin(request, 6 + WA_TAIL_DWORDS);
1610 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1611 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1613 intel_ring_emit(ring, (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
1614 intel_ring_emit(ring,
1615 intel_hws_seqno_address(request->engine) |
1616 MI_FLUSH_DW_USE_GTT);
1617 intel_ring_emit(ring, 0);
1618 intel_ring_emit(ring, request->fence.seqno);
1619 intel_ring_emit(ring, MI_USER_INTERRUPT);
1620 intel_ring_emit(ring, MI_NOOP);
1621 return intel_logical_ring_advance(request);
1624 static int gen8_emit_request_render(struct drm_i915_gem_request *request)
1626 struct intel_ring *ring = request->ring;
1629 ret = intel_ring_begin(request, 8 + WA_TAIL_DWORDS);
1633 /* We're using qword write, seqno should be aligned to 8 bytes. */
1634 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
1636 /* w/a for post sync ops following a GPGPU operation we
1637 * need a prior CS_STALL, which is emitted by the flush
1638 * following the batch.
1640 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
1641 intel_ring_emit(ring,
1642 (PIPE_CONTROL_GLOBAL_GTT_IVB |
1643 PIPE_CONTROL_CS_STALL |
1644 PIPE_CONTROL_QW_WRITE));
1645 intel_ring_emit(ring, intel_hws_seqno_address(request->engine));
1646 intel_ring_emit(ring, 0);
1647 intel_ring_emit(ring, i915_gem_request_get_seqno(request));
1648 /* We're thrashing one dword of HWS. */
1649 intel_ring_emit(ring, 0);
1650 intel_ring_emit(ring, MI_USER_INTERRUPT);
1651 intel_ring_emit(ring, MI_NOOP);
1652 return intel_logical_ring_advance(request);
1655 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1659 ret = intel_logical_ring_workarounds_emit(req);
1663 ret = intel_rcs_context_init_mocs(req);
1665 * Failing to program the MOCS is non-fatal.The system will not
1666 * run at peak performance. So generate an error and carry on.
1669 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1671 return i915_gem_render_state_init(req);
1675 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1676 * @engine: Engine Command Streamer.
1678 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
1680 struct drm_i915_private *dev_priv;
1682 if (!intel_engine_initialized(engine))
1686 * Tasklet cannot be active at this point due intel_mark_active/idle
1687 * so this is just for documentation.
1689 if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
1690 tasklet_kill(&engine->irq_tasklet);
1692 dev_priv = engine->i915;
1694 if (engine->buffer) {
1695 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
1698 if (engine->cleanup)
1699 engine->cleanup(engine);
1701 intel_engine_cleanup_common(engine);
1703 if (engine->status_page.obj) {
1704 i915_gem_object_unpin_map(engine->status_page.obj);
1705 engine->status_page.obj = NULL;
1707 intel_lr_context_unpin(dev_priv->kernel_context, engine);
1709 engine->idle_lite_restore_wa = 0;
1710 engine->disable_lite_restore_wa = false;
1711 engine->ctx_desc_template = 0;
1713 lrc_destroy_wa_ctx_obj(engine);
1714 engine->i915 = NULL;
1717 void intel_execlists_enable_submission(struct drm_i915_private *dev_priv)
1719 struct intel_engine_cs *engine;
1721 for_each_engine(engine, dev_priv)
1722 engine->submit_request = execlists_submit_request;
1726 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
1728 /* Default vfuncs which can be overriden by each engine. */
1729 engine->init_hw = gen8_init_common_ring;
1730 engine->emit_flush = gen8_emit_flush;
1731 engine->emit_request = gen8_emit_request;
1732 engine->submit_request = execlists_submit_request;
1734 engine->irq_enable = gen8_logical_ring_enable_irq;
1735 engine->irq_disable = gen8_logical_ring_disable_irq;
1736 engine->emit_bb_start = gen8_emit_bb_start;
1737 if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
1738 engine->irq_seqno_barrier = bxt_a_seqno_barrier;
1742 logical_ring_default_irqs(struct intel_engine_cs *engine)
1744 unsigned shift = engine->irq_shift;
1745 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
1746 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
1750 lrc_setup_hws(struct intel_engine_cs *engine,
1751 struct drm_i915_gem_object *dctx_obj)
1755 /* The HWSP is part of the default context object in LRC mode. */
1756 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(dctx_obj) +
1757 LRC_PPHWSP_PN * PAGE_SIZE;
1758 hws = i915_gem_object_pin_map(dctx_obj);
1760 return PTR_ERR(hws);
1761 engine->status_page.page_addr = hws + LRC_PPHWSP_PN * PAGE_SIZE;
1762 engine->status_page.obj = dctx_obj;
1768 logical_ring_setup(struct intel_engine_cs *engine)
1770 struct drm_i915_private *dev_priv = engine->i915;
1771 enum forcewake_domains fw_domains;
1773 intel_engine_setup_common(engine);
1775 /* Intentionally left blank. */
1776 engine->buffer = NULL;
1778 fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
1782 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1783 RING_CONTEXT_STATUS_PTR(engine),
1784 FW_REG_READ | FW_REG_WRITE);
1786 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1787 RING_CONTEXT_STATUS_BUF_BASE(engine),
1790 engine->fw_domains = fw_domains;
1792 tasklet_init(&engine->irq_tasklet,
1793 intel_lrc_irq_handler, (unsigned long)engine);
1795 logical_ring_init_platform_invariants(engine);
1796 logical_ring_default_vfuncs(engine);
1797 logical_ring_default_irqs(engine);
1801 logical_ring_init(struct intel_engine_cs *engine)
1803 struct i915_gem_context *dctx = engine->i915->kernel_context;
1806 ret = intel_engine_init_common(engine);
1810 ret = execlists_context_deferred_alloc(dctx, engine);
1814 /* As this is the default context, always pin it */
1815 ret = intel_lr_context_pin(dctx, engine);
1817 DRM_ERROR("Failed to pin context for %s: %d\n",
1822 /* And setup the hardware status page. */
1823 ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
1825 DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
1832 intel_logical_ring_cleanup(engine);
1836 int logical_render_ring_init(struct intel_engine_cs *engine)
1838 struct drm_i915_private *dev_priv = engine->i915;
1841 logical_ring_setup(engine);
1843 if (HAS_L3_DPF(dev_priv))
1844 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1846 /* Override some for render ring. */
1847 if (INTEL_GEN(dev_priv) >= 9)
1848 engine->init_hw = gen9_init_render_ring;
1850 engine->init_hw = gen8_init_render_ring;
1851 engine->init_context = gen8_init_rcs_context;
1852 engine->cleanup = intel_fini_pipe_control;
1853 engine->emit_flush = gen8_emit_flush_render;
1854 engine->emit_request = gen8_emit_request_render;
1856 ret = intel_init_pipe_control(engine, 4096);
1860 ret = intel_init_workaround_bb(engine);
1863 * We continue even if we fail to initialize WA batch
1864 * because we only expect rare glitches but nothing
1865 * critical to prevent us from using GPU
1867 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1871 ret = logical_ring_init(engine);
1873 lrc_destroy_wa_ctx_obj(engine);
1879 int logical_xcs_ring_init(struct intel_engine_cs *engine)
1881 logical_ring_setup(engine);
1883 return logical_ring_init(engine);
1887 make_rpcs(struct drm_i915_private *dev_priv)
1892 * No explicit RPCS request is needed to ensure full
1893 * slice/subslice/EU enablement prior to Gen9.
1895 if (INTEL_GEN(dev_priv) < 9)
1899 * Starting in Gen9, render power gating can leave
1900 * slice/subslice/EU in a partially enabled state. We
1901 * must make an explicit request through RPCS for full
1904 if (INTEL_INFO(dev_priv)->has_slice_pg) {
1905 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1906 rpcs |= INTEL_INFO(dev_priv)->slice_total <<
1907 GEN8_RPCS_S_CNT_SHIFT;
1908 rpcs |= GEN8_RPCS_ENABLE;
1911 if (INTEL_INFO(dev_priv)->has_subslice_pg) {
1912 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1913 rpcs |= INTEL_INFO(dev_priv)->subslice_per_slice <<
1914 GEN8_RPCS_SS_CNT_SHIFT;
1915 rpcs |= GEN8_RPCS_ENABLE;
1918 if (INTEL_INFO(dev_priv)->has_eu_pg) {
1919 rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
1920 GEN8_RPCS_EU_MIN_SHIFT;
1921 rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
1922 GEN8_RPCS_EU_MAX_SHIFT;
1923 rpcs |= GEN8_RPCS_ENABLE;
1929 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
1931 u32 indirect_ctx_offset;
1933 switch (INTEL_GEN(engine->i915)) {
1935 MISSING_CASE(INTEL_GEN(engine->i915));
1938 indirect_ctx_offset =
1939 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
1942 indirect_ctx_offset =
1943 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
1947 return indirect_ctx_offset;
1951 populate_lr_context(struct i915_gem_context *ctx,
1952 struct drm_i915_gem_object *ctx_obj,
1953 struct intel_engine_cs *engine,
1954 struct intel_ring *ring)
1956 struct drm_i915_private *dev_priv = ctx->i915;
1957 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1963 ppgtt = dev_priv->mm.aliasing_ppgtt;
1965 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1967 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1971 vaddr = i915_gem_object_pin_map(ctx_obj);
1972 if (IS_ERR(vaddr)) {
1973 ret = PTR_ERR(vaddr);
1974 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
1977 ctx_obj->dirty = true;
1979 /* The second page of the context object contains some fields which must
1980 * be set up prior to the first execution. */
1981 reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1983 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
1984 * commands followed by (reg, value) pairs. The values we are setting here are
1985 * only for the first context restore: on a subsequent save, the GPU will
1986 * recreate this batchbuffer with new values (including all the missing
1987 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1988 reg_state[CTX_LRI_HEADER_0] =
1989 MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
1990 ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
1991 RING_CONTEXT_CONTROL(engine),
1992 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
1993 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
1994 (HAS_RESOURCE_STREAMER(dev_priv) ?
1995 CTX_CTRL_RS_CTX_ENABLE : 0)));
1996 ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
1998 ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
2000 /* Ring buffer start address is not known until the buffer is pinned.
2001 * It is written to the context image in execlists_update_context()
2003 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
2004 RING_START(engine->mmio_base), 0);
2005 ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
2006 RING_CTL(engine->mmio_base),
2007 ((ring->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
2008 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
2009 RING_BBADDR_UDW(engine->mmio_base), 0);
2010 ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
2011 RING_BBADDR(engine->mmio_base), 0);
2012 ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
2013 RING_BBSTATE(engine->mmio_base),
2015 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
2016 RING_SBBADDR_UDW(engine->mmio_base), 0);
2017 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
2018 RING_SBBADDR(engine->mmio_base), 0);
2019 ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
2020 RING_SBBSTATE(engine->mmio_base), 0);
2021 if (engine->id == RCS) {
2022 ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
2023 RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
2024 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
2025 RING_INDIRECT_CTX(engine->mmio_base), 0);
2026 ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
2027 RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
2028 if (engine->wa_ctx.obj) {
2029 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2030 uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj);
2032 reg_state[CTX_RCS_INDIRECT_CTX+1] =
2033 (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
2034 (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);
2036 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2037 intel_lr_indirect_ctx_offset(engine) << 6;
2039 reg_state[CTX_BB_PER_CTX_PTR+1] =
2040 (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
2044 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2045 ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
2046 RING_CTX_TIMESTAMP(engine->mmio_base), 0);
2047 /* PDP values well be assigned later if needed */
2048 ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
2050 ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
2052 ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
2054 ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
2056 ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
2058 ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
2060 ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
2062 ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
2065 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
2066 /* 64b PPGTT (48bit canonical)
2067 * PDP0_DESCRIPTOR contains the base address to PML4 and
2068 * other PDP Descriptors are ignored.
2070 ASSIGN_CTX_PML4(ppgtt, reg_state);
2073 * PDP*_DESCRIPTOR contains the base address of space supported.
2074 * With dynamic page allocation, PDPs may not be allocated at
2075 * this point. Point the unallocated PDPs to the scratch page
2077 execlists_update_context_pdps(ppgtt, reg_state);
2080 if (engine->id == RCS) {
2081 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2082 ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2083 make_rpcs(dev_priv));
2086 i915_gem_object_unpin_map(ctx_obj);
2092 * intel_lr_context_size() - return the size of the context for an engine
2093 * @engine: which engine to find the context size for
2095 * Each engine may require a different amount of space for a context image,
2096 * so when allocating (or copying) an image, this function can be used to
2097 * find the right size for the specific engine.
2099 * Return: size (in bytes) of an engine-specific context image
2101 * Note: this size includes the HWSP, which is part of the context image
2102 * in LRC mode, but does not include the "shared data page" used with
2103 * GuC submission. The caller should account for this if using the GuC.
2105 uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
2109 WARN_ON(INTEL_GEN(engine->i915) < 8);
2111 switch (engine->id) {
2113 if (INTEL_GEN(engine->i915) >= 9)
2114 ret = GEN9_LR_CONTEXT_RENDER_SIZE;
2116 ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2122 ret = GEN8_LR_CONTEXT_OTHER_SIZE;
2129 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2130 struct intel_engine_cs *engine)
2132 struct drm_i915_gem_object *ctx_obj;
2133 struct intel_context *ce = &ctx->engine[engine->id];
2134 uint32_t context_size;
2135 struct intel_ring *ring;
2140 context_size = round_up(intel_lr_context_size(engine), 4096);
2142 /* One extra page as the sharing data between driver and GuC */
2143 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2145 ctx_obj = i915_gem_object_create(&ctx->i915->drm, context_size);
2146 if (IS_ERR(ctx_obj)) {
2147 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2148 return PTR_ERR(ctx_obj);
2151 ring = intel_engine_create_ring(engine, ctx->ring_size);
2153 ret = PTR_ERR(ring);
2154 goto error_deref_obj;
2157 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2159 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2160 goto error_ring_free;
2164 ce->state = ctx_obj;
2165 ce->initialised = engine->init_context == NULL;
2170 intel_ring_free(ring);
2172 i915_gem_object_put(ctx_obj);
2178 void intel_lr_context_reset(struct drm_i915_private *dev_priv,
2179 struct i915_gem_context *ctx)
2181 struct intel_engine_cs *engine;
2183 for_each_engine(engine, dev_priv) {
2184 struct intel_context *ce = &ctx->engine[engine->id];
2185 struct drm_i915_gem_object *ctx_obj = ce->state;
2187 uint32_t *reg_state;
2192 vaddr = i915_gem_object_pin_map(ctx_obj);
2193 if (WARN_ON(IS_ERR(vaddr)))
2196 reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
2197 ctx_obj->dirty = true;
2199 reg_state[CTX_RING_HEAD+1] = 0;
2200 reg_state[CTX_RING_TAIL+1] = 0;
2202 i915_gem_object_unpin_map(ctx_obj);