2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "intel_mocs.h"
141 #define RING_EXECLIST_QFULL (1 << 0x2)
142 #define RING_EXECLIST1_VALID (1 << 0x3)
143 #define RING_EXECLIST0_VALID (1 << 0x4)
144 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
145 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
146 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
148 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
149 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
150 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
151 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
152 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
153 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
155 #define GEN8_CTX_STATUS_COMPLETED_MASK \
156 (GEN8_CTX_STATUS_ACTIVE_IDLE | \
157 GEN8_CTX_STATUS_PREEMPTED | \
158 GEN8_CTX_STATUS_ELEMENT_SWITCH)
160 #define CTX_LRI_HEADER_0 0x01
161 #define CTX_CONTEXT_CONTROL 0x02
162 #define CTX_RING_HEAD 0x04
163 #define CTX_RING_TAIL 0x06
164 #define CTX_RING_BUFFER_START 0x08
165 #define CTX_RING_BUFFER_CONTROL 0x0a
166 #define CTX_BB_HEAD_U 0x0c
167 #define CTX_BB_HEAD_L 0x0e
168 #define CTX_BB_STATE 0x10
169 #define CTX_SECOND_BB_HEAD_U 0x12
170 #define CTX_SECOND_BB_HEAD_L 0x14
171 #define CTX_SECOND_BB_STATE 0x16
172 #define CTX_BB_PER_CTX_PTR 0x18
173 #define CTX_RCS_INDIRECT_CTX 0x1a
174 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
175 #define CTX_LRI_HEADER_1 0x21
176 #define CTX_CTX_TIMESTAMP 0x22
177 #define CTX_PDP3_UDW 0x24
178 #define CTX_PDP3_LDW 0x26
179 #define CTX_PDP2_UDW 0x28
180 #define CTX_PDP2_LDW 0x2a
181 #define CTX_PDP1_UDW 0x2c
182 #define CTX_PDP1_LDW 0x2e
183 #define CTX_PDP0_UDW 0x30
184 #define CTX_PDP0_LDW 0x32
185 #define CTX_LRI_HEADER_2 0x41
186 #define CTX_R_PWR_CLK_STATE 0x42
187 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
189 #define CTX_REG(reg_state, pos, reg, val) do { \
190 (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
191 (reg_state)[(pos)+1] = (val); \
194 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \
195 const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \
196 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
197 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
200 #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
201 reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
202 reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
205 #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17
206 #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26
208 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
209 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
211 #define WA_TAIL_DWORDS 2
213 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
214 struct intel_engine_cs *engine);
215 static void execlists_init_reg_state(u32 *reg_state,
216 struct i915_gem_context *ctx,
217 struct intel_engine_cs *engine,
218 struct intel_ring *ring);
221 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
222 * @dev_priv: i915 device private
223 * @enable_execlists: value of i915.enable_execlists module parameter.
225 * Only certain platforms support Execlists (the prerequisites being
226 * support for Logical Ring Contexts and Aliasing PPGTT or better).
228 * Return: 1 if Execlists is supported and has to be enabled.
230 int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
232 /* On platforms with execlist available, vGPU will only
233 * support execlist mode, no ring buffer mode.
235 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
238 if (INTEL_GEN(dev_priv) >= 9)
241 if (enable_execlists == 0)
244 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
245 USES_PPGTT(dev_priv) &&
246 i915.use_mmio_flip >= 0)
253 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
254 * descriptor for a pinned context
255 * @ctx: Context to work on
256 * @engine: Engine the descriptor will be used with
258 * The context descriptor encodes various attributes of a context,
259 * including its GTT address and some flags. Because it's fairly
260 * expensive to calculate, we'll just do it once and cache the result,
261 * which remains valid until the context is unpinned.
263 * This is what a descriptor looks like, from LSB to MSB::
265 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
266 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
267 * bits 32-52: ctx ID, a globally unique tag
268 * bits 53-54: mbz, reserved for use by hardware
269 * bits 55-63: group ID, currently unused and set to 0
272 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
273 struct intel_engine_cs *engine)
275 struct intel_context *ce = &ctx->engine[engine->id];
278 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
280 desc = ctx->desc_template; /* bits 0-11 */
281 desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE;
283 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
288 uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
289 struct intel_engine_cs *engine)
291 return ctx->engine[engine->id].lrc_desc;
295 execlists_context_status_change(struct drm_i915_gem_request *rq,
296 unsigned long status)
299 * Only used when GVT-g is enabled now. When GVT-g is disabled,
300 * The compiler should eliminate this function as dead-code.
302 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
305 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
310 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
312 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
313 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
314 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
315 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
318 static u64 execlists_update_context(struct drm_i915_gem_request *rq)
320 struct intel_context *ce = &rq->ctx->engine[rq->engine->id];
321 struct i915_hw_ppgtt *ppgtt =
322 rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
323 u32 *reg_state = ce->lrc_reg_state;
325 reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
327 /* True 32b PPGTT with dynamic page allocation: update PDP
328 * registers and point the unallocated PDPs to scratch page.
329 * PML4 is allocated during ppgtt init, so this is not needed
332 if (ppgtt && !i915_vm_is_48bit(&ppgtt->base))
333 execlists_update_context_pdps(ppgtt, reg_state);
338 static void execlists_submit_ports(struct intel_engine_cs *engine)
340 struct execlist_port *port = engine->execlist_port;
342 engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine));
345 for (n = ARRAY_SIZE(engine->execlist_port); n--; ) {
346 struct drm_i915_gem_request *rq;
350 rq = port_unpack(&port[n], &count);
352 GEM_BUG_ON(count > !n);
354 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
355 port_set(&port[n], port_pack(rq, count));
356 desc = execlists_update_context(rq);
357 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
363 writel(upper_32_bits(desc), elsp);
364 writel(lower_32_bits(desc), elsp);
368 static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
370 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
371 i915_gem_context_force_single_submission(ctx));
374 static bool can_merge_ctx(const struct i915_gem_context *prev,
375 const struct i915_gem_context *next)
380 if (ctx_single_port_submission(prev))
386 static void port_assign(struct execlist_port *port,
387 struct drm_i915_gem_request *rq)
389 GEM_BUG_ON(rq == port_request(port));
391 if (port_isset(port))
392 i915_gem_request_put(port_request(port));
394 port_set(port, port_pack(i915_gem_request_get(rq), port_count(port)));
397 static void execlists_dequeue(struct intel_engine_cs *engine)
399 struct drm_i915_gem_request *last;
400 struct execlist_port *port = engine->execlist_port;
404 last = port_request(port);
406 /* WaIdleLiteRestore:bdw,skl
407 * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL
408 * as we resubmit the request. See gen8_emit_breadcrumb()
409 * for where we prepare the padding after the end of the
412 last->tail = last->wa_tail;
414 GEM_BUG_ON(port_isset(&port[1]));
416 /* Hardware submission is through 2 ports. Conceptually each port
417 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
418 * static for a context, and unique to each, so we only execute
419 * requests belonging to a single context from each ring. RING_HEAD
420 * is maintained by the CS in the context image, it marks the place
421 * where it got up to last time, and through RING_TAIL we tell the CS
422 * where we want to execute up to this time.
424 * In this list the requests are in order of execution. Consecutive
425 * requests from the same context are adjacent in the ringbuffer. We
426 * can combine these requests into a single RING_TAIL update:
428 * RING_HEAD...req1...req2
430 * since to execute req2 the CS must first execute req1.
432 * Our goal then is to point each port to the end of a consecutive
433 * sequence of requests as being the most optimal (fewest wake ups
434 * and context switches) submission.
437 spin_lock_irq(&engine->timeline->lock);
438 rb = engine->execlist_first;
439 GEM_BUG_ON(rb_first(&engine->execlist_queue) != rb);
441 struct i915_priolist *p = rb_entry(rb, typeof(*p), node);
442 struct drm_i915_gem_request *rq, *rn;
444 list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) {
446 * Can we combine this request with the current port?
447 * It has to be the same context/ringbuffer and not
448 * have any exceptions (e.g. GVT saying never to
451 * If we can combine the requests, we can execute both
452 * by updating the RING_TAIL to point to the end of the
453 * second request, and so we never need to tell the
454 * hardware about the first.
456 if (last && !can_merge_ctx(rq->ctx, last->ctx)) {
458 * If we are on the second port and cannot
459 * combine this request with the last, then we
462 if (port != engine->execlist_port) {
463 __list_del_many(&p->requests,
469 * If GVT overrides us we only ever submit
470 * port[0], leaving port[1] empty. Note that we
471 * also have to be careful that we don't queue
472 * the same context (even though a different
473 * request) to the second port.
475 if (ctx_single_port_submission(last->ctx) ||
476 ctx_single_port_submission(rq->ctx)) {
477 __list_del_many(&p->requests,
482 GEM_BUG_ON(last->ctx == rq->ctx);
485 port_assign(port, last);
489 INIT_LIST_HEAD(&rq->priotree.link);
490 rq->priotree.priority = INT_MAX;
492 __i915_gem_request_submit(rq);
493 trace_i915_gem_request_in(rq, port_index(port, engine));
499 rb_erase(&p->node, &engine->execlist_queue);
500 INIT_LIST_HEAD(&p->requests);
501 if (p->priority != I915_PRIORITY_NORMAL)
505 engine->execlist_first = rb;
507 port_assign(port, last);
508 spin_unlock_irq(&engine->timeline->lock);
511 execlists_submit_ports(engine);
514 static bool execlists_elsp_ready(const struct intel_engine_cs *engine)
516 const struct execlist_port *port = engine->execlist_port;
518 return port_count(&port[0]) + port_count(&port[1]) < 2;
522 * Check the unread Context Status Buffers and manage the submission of new
523 * contexts to the ELSP accordingly.
525 static void intel_lrc_irq_handler(unsigned long data)
527 struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
528 struct execlist_port *port = engine->execlist_port;
529 struct drm_i915_private *dev_priv = engine->i915;
531 /* We can skip acquiring intel_runtime_pm_get() here as it was taken
532 * on our behalf by the request (see i915_gem_mark_busy()) and it will
533 * not be relinquished until the device is idle (see
534 * i915_gem_idle_work_handler()). As a precaution, we make sure
535 * that all ELSP are drained i.e. we have processed the CSB,
536 * before allowing ourselves to idle and calling intel_runtime_pm_put().
538 GEM_BUG_ON(!dev_priv->gt.awake);
540 intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
542 /* Prefer doing test_and_clear_bit() as a two stage operation to avoid
543 * imposing the cost of a locked atomic transaction when submitting a
544 * new request (outside of the context-switch interrupt).
546 while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
547 u32 __iomem *csb_mmio =
548 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
550 dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));
551 unsigned int head, tail;
553 /* The write will be ordered by the uncached read (itself
554 * a memory barrier), so we do not need another in the form
555 * of a locked instruction. The race between the interrupt
556 * handler and the split test/clear is harmless as we order
557 * our clear before the CSB read. If the interrupt arrived
558 * first between the test and the clear, we read the updated
559 * CSB and clear the bit. If the interrupt arrives as we read
560 * the CSB or later (i.e. after we had cleared the bit) the bit
561 * is set and we do a new loop.
563 __clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
564 head = readl(csb_mmio);
565 tail = GEN8_CSB_WRITE_PTR(head);
566 head = GEN8_CSB_READ_PTR(head);
567 while (head != tail) {
568 struct drm_i915_gem_request *rq;
572 if (++head == GEN8_CSB_ENTRIES)
575 /* We are flying near dragons again.
577 * We hold a reference to the request in execlist_port[]
578 * but no more than that. We are operating in softirq
579 * context and so cannot hold any mutex or sleep. That
580 * prevents us stopping the requests we are processing
581 * in port[] from being retired simultaneously (the
582 * breadcrumb will be complete before we see the
583 * context-switch). As we only hold the reference to the
584 * request, any pointer chasing underneath the request
585 * is subject to a potential use-after-free. Thus we
586 * store all of the bookkeeping within port[] as
587 * required, and avoid using unguarded pointers beneath
588 * request itself. The same applies to the atomic
592 status = readl(buf + 2 * head);
593 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
596 /* Check the context/desc id for this event matches */
597 GEM_DEBUG_BUG_ON(readl(buf + 2 * head + 1) !=
600 rq = port_unpack(port, &count);
601 GEM_BUG_ON(count == 0);
603 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
604 GEM_BUG_ON(!i915_gem_request_completed(rq));
605 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT);
607 trace_i915_gem_request_out(rq);
608 i915_gem_request_put(rq);
611 memset(&port[1], 0, sizeof(port[1]));
613 port_set(port, port_pack(rq, count));
616 /* After the final element, the hw should be idle */
617 GEM_BUG_ON(port_count(port) == 0 &&
618 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
621 writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8),
625 if (execlists_elsp_ready(engine))
626 execlists_dequeue(engine);
628 intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
632 insert_request(struct intel_engine_cs *engine,
633 struct i915_priotree *pt,
636 struct i915_priolist *p;
637 struct rb_node **parent, *rb;
640 if (unlikely(engine->no_priolist))
641 prio = I915_PRIORITY_NORMAL;
644 /* most positive priority is scheduled first, equal priorities fifo */
646 parent = &engine->execlist_queue.rb_node;
649 p = rb_entry(rb, typeof(*p), node);
650 if (prio > p->priority) {
651 parent = &rb->rb_left;
652 } else if (prio < p->priority) {
653 parent = &rb->rb_right;
656 list_add_tail(&pt->link, &p->requests);
661 if (prio == I915_PRIORITY_NORMAL) {
662 p = &engine->default_priolist;
664 p = kmalloc(sizeof(*p), GFP_ATOMIC);
665 /* Convert an allocation failure to a priority bump */
667 prio = I915_PRIORITY_NORMAL; /* recurses just once */
669 /* To maintain ordering with all rendering, after an
670 * allocation failure we have to disable all scheduling.
671 * Requests will then be executed in fifo, and schedule
672 * will ensure that dependencies are emitted in fifo.
673 * There will be still some reordering with existing
674 * requests, so if userspace lied about their
675 * dependencies that reordering may be visible.
677 engine->no_priolist = true;
683 rb_link_node(&p->node, rb, parent);
684 rb_insert_color(&p->node, &engine->execlist_queue);
686 INIT_LIST_HEAD(&p->requests);
687 list_add_tail(&pt->link, &p->requests);
690 engine->execlist_first = &p->node;
695 static void execlists_submit_request(struct drm_i915_gem_request *request)
697 struct intel_engine_cs *engine = request->engine;
700 /* Will be called from irq-context when using foreign fences. */
701 spin_lock_irqsave(&engine->timeline->lock, flags);
703 if (insert_request(engine,
705 request->priotree.priority)) {
706 if (execlists_elsp_ready(engine))
707 tasklet_hi_schedule(&engine->irq_tasklet);
710 GEM_BUG_ON(!engine->execlist_first);
711 GEM_BUG_ON(list_empty(&request->priotree.link));
713 spin_unlock_irqrestore(&engine->timeline->lock, flags);
716 static struct intel_engine_cs *
717 pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
719 struct intel_engine_cs *engine =
720 container_of(pt, struct drm_i915_gem_request, priotree)->engine;
724 if (engine != locked) {
725 spin_unlock(&locked->timeline->lock);
726 spin_lock(&engine->timeline->lock);
732 static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
734 struct intel_engine_cs *engine;
735 struct i915_dependency *dep, *p;
736 struct i915_dependency stack;
739 if (prio <= READ_ONCE(request->priotree.priority))
742 /* Need BKL in order to use the temporary link inside i915_dependency */
743 lockdep_assert_held(&request->i915->drm.struct_mutex);
745 stack.signaler = &request->priotree;
746 list_add(&stack.dfs_link, &dfs);
748 /* Recursively bump all dependent priorities to match the new request.
750 * A naive approach would be to use recursion:
751 * static void update_priorities(struct i915_priotree *pt, prio) {
752 * list_for_each_entry(dep, &pt->signalers_list, signal_link)
753 * update_priorities(dep->signal, prio)
754 * insert_request(pt);
756 * but that may have unlimited recursion depth and so runs a very
757 * real risk of overunning the kernel stack. Instead, we build
758 * a flat list of all dependencies starting with the current request.
759 * As we walk the list of dependencies, we add all of its dependencies
760 * to the end of the list (this may include an already visited
761 * request) and continue to walk onwards onto the new dependencies. The
762 * end result is a topological list of requests in reverse order, the
763 * last element in the list is the request we must execute first.
765 list_for_each_entry_safe(dep, p, &dfs, dfs_link) {
766 struct i915_priotree *pt = dep->signaler;
768 /* Within an engine, there can be no cycle, but we may
769 * refer to the same dependency chain multiple times
770 * (redundant dependencies are not eliminated) and across
773 list_for_each_entry(p, &pt->signalers_list, signal_link) {
774 GEM_BUG_ON(p->signaler->priority < pt->priority);
775 if (prio > READ_ONCE(p->signaler->priority))
776 list_move_tail(&p->dfs_link, &dfs);
779 list_safe_reset_next(dep, p, dfs_link);
782 engine = request->engine;
783 spin_lock_irq(&engine->timeline->lock);
785 /* Fifo and depth-first replacement ensure our deps execute before us */
786 list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
787 struct i915_priotree *pt = dep->signaler;
789 INIT_LIST_HEAD(&dep->dfs_link);
791 engine = pt_lock_engine(pt, engine);
793 if (prio <= pt->priority)
797 if (!list_empty(&pt->link)) {
798 __list_del_entry(&pt->link);
799 insert_request(engine, pt, prio);
803 spin_unlock_irq(&engine->timeline->lock);
805 /* XXX Do we need to preempt to make room for us and our deps? */
808 static struct intel_ring *
809 execlists_context_pin(struct intel_engine_cs *engine,
810 struct i915_gem_context *ctx)
812 struct intel_context *ce = &ctx->engine[engine->id];
817 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
819 if (likely(ce->pin_count++))
821 GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
824 ret = execlists_context_deferred_alloc(ctx, engine);
828 GEM_BUG_ON(!ce->state);
830 flags = PIN_GLOBAL | PIN_HIGH;
831 if (ctx->ggtt_offset_bias)
832 flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
834 ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags);
838 vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
840 ret = PTR_ERR(vaddr);
844 ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias);
848 intel_lr_context_descriptor_update(ctx, engine);
850 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
851 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
852 i915_ggtt_offset(ce->ring->vma);
854 ce->state->obj->mm.dirty = true;
856 i915_gem_context_get(ctx);
861 i915_gem_object_unpin_map(ce->state->obj);
863 __i915_vma_unpin(ce->state);
869 static void execlists_context_unpin(struct intel_engine_cs *engine,
870 struct i915_gem_context *ctx)
872 struct intel_context *ce = &ctx->engine[engine->id];
874 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
875 GEM_BUG_ON(ce->pin_count == 0);
880 intel_ring_unpin(ce->ring);
882 i915_gem_object_unpin_map(ce->state->obj);
883 i915_vma_unpin(ce->state);
885 i915_gem_context_put(ctx);
888 static int execlists_request_alloc(struct drm_i915_gem_request *request)
890 struct intel_engine_cs *engine = request->engine;
891 struct intel_context *ce = &request->ctx->engine[engine->id];
895 GEM_BUG_ON(!ce->pin_count);
897 /* Flush enough space to reduce the likelihood of waiting after
898 * we start building the request - in which case we will just
899 * have to repeat work.
901 request->reserved_space += EXECLISTS_REQUEST_SIZE;
903 if (i915.enable_guc_submission) {
905 * Check that the GuC has space for the request before
906 * going any further, as the i915_add_request() call
907 * later on mustn't fail ...
909 ret = i915_guc_wq_reserve(request);
914 cs = intel_ring_begin(request, 0);
920 if (!ce->initialised) {
921 ret = engine->init_context(request);
925 ce->initialised = true;
928 /* Note that after this point, we have committed to using
929 * this request as it is being used to both track the
930 * state of engine initialisation and liveness of the
931 * golden renderstate above. Think twice before you try
932 * to cancel/unwind this request now.
935 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
939 if (i915.enable_guc_submission)
940 i915_guc_wq_unreserve(request);
946 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
947 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
948 * but there is a slight complication as this is applied in WA batch where the
949 * values are only initialized once so we cannot take register value at the
950 * beginning and reuse it further; hence we save its value to memory, upload a
951 * constant value with bit21 set and then we restore it back with the saved value.
952 * To simplify the WA, a constant value is formed by using the default value
953 * of this register. This shouldn't be a problem because we are only modifying
954 * it for a short period and this batch in non-premptible. We can ofcourse
955 * use additional instructions that read the actual value of the register
956 * at that time and set our bit of interest but it makes the WA complicated.
958 * This WA is also required for Gen9 so extracting as a function avoids
962 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
964 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
965 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
966 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
969 *batch++ = MI_LOAD_REGISTER_IMM(1);
970 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
971 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
973 batch = gen8_emit_pipe_control(batch,
974 PIPE_CONTROL_CS_STALL |
975 PIPE_CONTROL_DC_FLUSH_ENABLE,
978 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
979 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
980 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
987 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
988 * initialized at the beginning and shared across all contexts but this field
989 * helps us to have multiple batches at different offsets and select them based
990 * on a criteria. At the moment this batch always start at the beginning of the page
991 * and at this point we don't have multiple wa_ctx batch buffers.
993 * The number of WA applied are not known at the beginning; we use this field
994 * to return the no of DWORDS written.
996 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
997 * so it adds NOOPs as padding to make it cacheline aligned.
998 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
999 * makes a complete batch buffer.
1001 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1003 /* WaDisableCtxRestoreArbitration:bdw,chv */
1004 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1006 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1007 if (IS_BROADWELL(engine->i915))
1008 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1010 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1011 /* Actual scratch location is at 128 bytes offset */
1012 batch = gen8_emit_pipe_control(batch,
1013 PIPE_CONTROL_FLUSH_L3 |
1014 PIPE_CONTROL_GLOBAL_GTT_IVB |
1015 PIPE_CONTROL_CS_STALL |
1016 PIPE_CONTROL_QW_WRITE,
1017 i915_ggtt_offset(engine->scratch) +
1018 2 * CACHELINE_BYTES);
1020 /* Pad to end of cacheline */
1021 while ((unsigned long)batch % CACHELINE_BYTES)
1025 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1026 * execution depends on the length specified in terms of cache lines
1027 * in the register CTX_RCS_INDIRECT_CTX
1034 * This batch is started immediately after indirect_ctx batch. Since we ensure
1035 * that indirect_ctx ends on a cacheline this batch is aligned automatically.
1037 * The number of DWORDS written are returned using this field.
1039 * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
1040 * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
1042 static u32 *gen8_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
1044 /* WaDisableCtxRestoreArbitration:bdw,chv */
1045 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1046 *batch++ = MI_BATCH_BUFFER_END;
1051 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1053 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1054 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1056 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1057 *batch++ = MI_LOAD_REGISTER_IMM(1);
1058 *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2);
1059 *batch++ = _MASKED_BIT_DISABLE(
1060 GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
1063 /* WaClearSlmSpaceAtContextSwitch:kbl */
1064 /* Actual scratch location is at 128 bytes offset */
1065 if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
1066 batch = gen8_emit_pipe_control(batch,
1067 PIPE_CONTROL_FLUSH_L3 |
1068 PIPE_CONTROL_GLOBAL_GTT_IVB |
1069 PIPE_CONTROL_CS_STALL |
1070 PIPE_CONTROL_QW_WRITE,
1071 i915_ggtt_offset(engine->scratch)
1072 + 2 * CACHELINE_BYTES);
1075 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1076 if (HAS_POOLED_EU(engine->i915)) {
1078 * EU pool configuration is setup along with golden context
1079 * during context initialization. This value depends on
1080 * device type (2x6 or 3x6) and needs to be updated based
1081 * on which subslice is disabled especially for 2x6
1082 * devices, however it is safe to load default
1083 * configuration of 3x6 device instead of masking off
1084 * corresponding bits because HW ignores bits of a disabled
1085 * subslice and drops down to appropriate config. Please
1086 * see render_state_setup() in i915_gem_render_state.c for
1087 * possible configurations, to avoid duplication they are
1088 * not shown here again.
1090 *batch++ = GEN9_MEDIA_POOL_STATE;
1091 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1092 *batch++ = 0x00777000;
1098 /* Pad to end of cacheline */
1099 while ((unsigned long)batch % CACHELINE_BYTES)
1105 static u32 *gen9_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch)
1107 *batch++ = MI_BATCH_BUFFER_END;
1112 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1114 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
1116 struct drm_i915_gem_object *obj;
1117 struct i915_vma *vma;
1120 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE);
1122 return PTR_ERR(obj);
1124 vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
1130 err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
1134 engine->wa_ctx.vma = vma;
1138 i915_gem_object_put(obj);
1142 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
1144 i915_vma_unpin_and_release(&engine->wa_ctx.vma);
1147 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1149 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1151 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1152 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
1154 wa_bb_func_t wa_bb_fn[2];
1156 void *batch, *batch_ptr;
1160 if (WARN_ON(engine->id != RCS || !engine->scratch))
1163 switch (INTEL_GEN(engine->i915)) {
1165 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1166 wa_bb_fn[1] = gen9_init_perctx_bb;
1169 wa_bb_fn[0] = gen8_init_indirectctx_bb;
1170 wa_bb_fn[1] = gen8_init_perctx_bb;
1173 MISSING_CASE(INTEL_GEN(engine->i915));
1177 ret = lrc_setup_wa_ctx(engine);
1179 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1183 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1184 batch = batch_ptr = kmap_atomic(page);
1187 * Emit the two workaround batch buffers, recording the offset from the
1188 * start of the workaround batch buffer object for each and their
1191 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1192 wa_bb[i]->offset = batch_ptr - batch;
1193 if (WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, CACHELINE_BYTES))) {
1197 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
1198 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
1201 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
1203 kunmap_atomic(batch);
1205 lrc_destroy_wa_ctx(engine);
1210 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1212 struct drm_i915_private *dev_priv = engine->i915;
1213 struct execlist_port *port = engine->execlist_port;
1218 ret = intel_mocs_init_engine(engine);
1222 intel_engine_reset_breadcrumbs(engine);
1223 intel_engine_init_hangcheck(engine);
1225 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1226 I915_WRITE(RING_MODE_GEN7(engine),
1227 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1228 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1229 engine->status_page.ggtt_offset);
1230 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1232 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1234 /* After a GPU reset, we may have requests to replay */
1235 clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1238 for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) {
1239 if (!port_isset(&port[n]))
1242 DRM_DEBUG_DRIVER("Restarting %s:%d from 0x%x\n",
1244 port_request(&port[n])->global_seqno);
1246 /* Discard the current inflight count */
1247 port_set(&port[n], port_request(&port[n]));
1251 if (submit && !i915.enable_guc_submission)
1252 execlists_submit_ports(engine);
1257 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1259 struct drm_i915_private *dev_priv = engine->i915;
1262 ret = gen8_init_common_ring(engine);
1266 /* We need to disable the AsyncFlip performance optimisations in order
1267 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1268 * programmed to '1' on all products.
1270 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1272 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1274 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1276 return init_workarounds_ring(engine);
1279 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1283 ret = gen8_init_common_ring(engine);
1287 return init_workarounds_ring(engine);
1290 static void reset_common_ring(struct intel_engine_cs *engine,
1291 struct drm_i915_gem_request *request)
1293 struct execlist_port *port = engine->execlist_port;
1294 struct intel_context *ce;
1296 /* If the request was innocent, we leave the request in the ELSP
1297 * and will try to replay it on restarting. The context image may
1298 * have been corrupted by the reset, in which case we may have
1299 * to service a new GPU hang, but more likely we can continue on
1302 * If the request was guilty, we presume the context is corrupt
1303 * and have to at least restore the RING register in the context
1304 * image back to the expected values to skip over the guilty request.
1306 if (!request || request->fence.error != -EIO)
1309 /* We want a simple context + ring to execute the breadcrumb update.
1310 * We cannot rely on the context being intact across the GPU hang,
1311 * so clear it and rebuild just what we need for the breadcrumb.
1312 * All pending requests for this context will be zapped, and any
1313 * future request will be after userspace has had the opportunity
1314 * to recreate its own state.
1316 ce = &request->ctx->engine[engine->id];
1317 execlists_init_reg_state(ce->lrc_reg_state,
1318 request->ctx, engine, ce->ring);
1320 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1321 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1322 i915_ggtt_offset(ce->ring->vma);
1323 ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix;
1325 request->ring->head = request->postfix;
1326 intel_ring_update_space(request->ring);
1328 /* Catch up with any missed context-switch interrupts */
1329 if (request->ctx != port_request(port)->ctx) {
1330 i915_gem_request_put(port_request(port));
1332 memset(&port[1], 0, sizeof(port[1]));
1335 GEM_BUG_ON(request->ctx != port_request(port)->ctx);
1337 /* Reset WaIdleLiteRestore:bdw,skl as well */
1339 intel_ring_wrap(request->ring,
1340 request->wa_tail - WA_TAIL_DWORDS*sizeof(u32));
1341 assert_ring_tail_valid(request->ring, request->tail);
1344 static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
1346 struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1347 struct intel_engine_cs *engine = req->engine;
1348 const int num_lri_cmds = GEN8_3LVL_PDPES * 2;
1352 cs = intel_ring_begin(req, num_lri_cmds * 2 + 2);
1356 *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
1357 for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {
1358 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
1360 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
1361 *cs++ = upper_32_bits(pd_daddr);
1362 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
1363 *cs++ = lower_32_bits(pd_daddr);
1367 intel_ring_advance(req, cs);
1372 static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1373 u64 offset, u32 len,
1374 const unsigned int flags)
1379 /* Don't rely in hw updating PDPs, specially in lite-restore.
1380 * Ideally, we should set Force PD Restore in ctx descriptor,
1381 * but we can't. Force Restore would be a second option, but
1382 * it is unsafe in case of lite-restore (because the ctx is
1383 * not idle). PML4 is allocated during ppgtt init so this is
1384 * not needed in 48-bit.*/
1385 if (req->ctx->ppgtt &&
1386 (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) &&
1387 !i915_vm_is_48bit(&req->ctx->ppgtt->base) &&
1388 !intel_vgpu_active(req->i915)) {
1389 ret = intel_logical_ring_emit_pdps(req);
1393 req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1396 cs = intel_ring_begin(req, 4);
1400 /* FIXME(BDW): Address space and security selectors. */
1401 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
1402 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
1403 (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
1404 *cs++ = lower_32_bits(offset);
1405 *cs++ = upper_32_bits(offset);
1407 intel_ring_advance(req, cs);
1412 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1414 struct drm_i915_private *dev_priv = engine->i915;
1415 I915_WRITE_IMR(engine,
1416 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1417 POSTING_READ_FW(RING_IMR(engine->mmio_base));
1420 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1422 struct drm_i915_private *dev_priv = engine->i915;
1423 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1426 static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode)
1430 cs = intel_ring_begin(request, 4);
1434 cmd = MI_FLUSH_DW + 1;
1436 /* We always require a command barrier so that subsequent
1437 * commands, such as breadcrumb interrupts, are strictly ordered
1438 * wrt the contents of the write cache being flushed to memory
1439 * (and thus being coherent from the CPU).
1441 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1443 if (mode & EMIT_INVALIDATE) {
1444 cmd |= MI_INVALIDATE_TLB;
1445 if (request->engine->id == VCS)
1446 cmd |= MI_INVALIDATE_BSD;
1450 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1451 *cs++ = 0; /* upper addr */
1452 *cs++ = 0; /* value */
1453 intel_ring_advance(request, cs);
1458 static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1461 struct intel_engine_cs *engine = request->engine;
1463 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1464 bool vf_flush_wa = false, dc_flush_wa = false;
1468 flags |= PIPE_CONTROL_CS_STALL;
1470 if (mode & EMIT_FLUSH) {
1471 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
1472 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1473 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1474 flags |= PIPE_CONTROL_FLUSH_ENABLE;
1477 if (mode & EMIT_INVALIDATE) {
1478 flags |= PIPE_CONTROL_TLB_INVALIDATE;
1479 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
1480 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
1481 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
1482 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
1483 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
1484 flags |= PIPE_CONTROL_QW_WRITE;
1485 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
1488 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
1491 if (IS_GEN9(request->i915))
1494 /* WaForGAMHang:kbl */
1495 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
1507 cs = intel_ring_begin(request, len);
1512 cs = gen8_emit_pipe_control(cs, 0, 0);
1515 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
1518 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
1521 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
1523 intel_ring_advance(request, cs);
1529 * Reserve space for 2 NOOPs at the end of each request to be
1530 * used as a workaround for not being allowed to do lite
1531 * restore with HEAD==TAIL (WaIdleLiteRestore).
1533 static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *cs)
1537 request->wa_tail = intel_ring_offset(request, cs);
1540 static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs)
1542 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
1543 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1545 *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;
1546 *cs++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT;
1548 *cs++ = request->global_seqno;
1549 *cs++ = MI_USER_INTERRUPT;
1551 request->tail = intel_ring_offset(request, cs);
1552 assert_ring_tail_valid(request->ring, request->tail);
1554 gen8_emit_wa_tail(request, cs);
1557 static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
1559 static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request,
1562 /* We're using qword write, seqno should be aligned to 8 bytes. */
1563 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
1565 /* w/a for post sync ops following a GPGPU operation we
1566 * need a prior CS_STALL, which is emitted by the flush
1567 * following the batch.
1569 *cs++ = GFX_OP_PIPE_CONTROL(6);
1570 *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL |
1571 PIPE_CONTROL_QW_WRITE;
1572 *cs++ = intel_hws_seqno_address(request->engine);
1574 *cs++ = request->global_seqno;
1575 /* We're thrashing one dword of HWS. */
1577 *cs++ = MI_USER_INTERRUPT;
1579 request->tail = intel_ring_offset(request, cs);
1580 assert_ring_tail_valid(request->ring, request->tail);
1582 gen8_emit_wa_tail(request, cs);
1585 static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS;
1587 static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1591 ret = intel_ring_workarounds_emit(req);
1595 ret = intel_rcs_context_init_mocs(req);
1597 * Failing to program the MOCS is non-fatal.The system will not
1598 * run at peak performance. So generate an error and carry on.
1601 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
1603 return i915_gem_render_state_emit(req);
1607 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1608 * @engine: Engine Command Streamer.
1610 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
1612 struct drm_i915_private *dev_priv;
1615 * Tasklet cannot be active at this point due intel_mark_active/idle
1616 * so this is just for documentation.
1618 if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
1619 tasklet_kill(&engine->irq_tasklet);
1621 dev_priv = engine->i915;
1623 if (engine->buffer) {
1624 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
1627 if (engine->cleanup)
1628 engine->cleanup(engine);
1630 if (engine->status_page.vma) {
1631 i915_gem_object_unpin_map(engine->status_page.vma->obj);
1632 engine->status_page.vma = NULL;
1635 intel_engine_cleanup_common(engine);
1637 lrc_destroy_wa_ctx(engine);
1638 engine->i915 = NULL;
1639 dev_priv->engine[engine->id] = NULL;
1643 static void execlists_set_default_submission(struct intel_engine_cs *engine)
1645 engine->submit_request = execlists_submit_request;
1646 engine->schedule = execlists_schedule;
1647 engine->irq_tasklet.func = intel_lrc_irq_handler;
1651 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
1653 /* Default vfuncs which can be overriden by each engine. */
1654 engine->init_hw = gen8_init_common_ring;
1655 engine->reset_hw = reset_common_ring;
1657 engine->context_pin = execlists_context_pin;
1658 engine->context_unpin = execlists_context_unpin;
1660 engine->request_alloc = execlists_request_alloc;
1662 engine->emit_flush = gen8_emit_flush;
1663 engine->emit_breadcrumb = gen8_emit_breadcrumb;
1664 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
1666 engine->set_default_submission = execlists_set_default_submission;
1668 engine->irq_enable = gen8_logical_ring_enable_irq;
1669 engine->irq_disable = gen8_logical_ring_disable_irq;
1670 engine->emit_bb_start = gen8_emit_bb_start;
1674 logical_ring_default_irqs(struct intel_engine_cs *engine)
1676 unsigned shift = engine->irq_shift;
1677 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
1678 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
1682 lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma)
1684 const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE;
1687 /* The HWSP is part of the default context object in LRC mode. */
1688 hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
1690 return PTR_ERR(hws);
1692 engine->status_page.page_addr = hws + hws_offset;
1693 engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset;
1694 engine->status_page.vma = vma;
1700 logical_ring_setup(struct intel_engine_cs *engine)
1702 struct drm_i915_private *dev_priv = engine->i915;
1703 enum forcewake_domains fw_domains;
1705 intel_engine_setup_common(engine);
1707 /* Intentionally left blank. */
1708 engine->buffer = NULL;
1710 fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
1714 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1715 RING_CONTEXT_STATUS_PTR(engine),
1716 FW_REG_READ | FW_REG_WRITE);
1718 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
1719 RING_CONTEXT_STATUS_BUF_BASE(engine),
1722 engine->fw_domains = fw_domains;
1724 tasklet_init(&engine->irq_tasklet,
1725 intel_lrc_irq_handler, (unsigned long)engine);
1727 logical_ring_default_vfuncs(engine);
1728 logical_ring_default_irqs(engine);
1732 logical_ring_init(struct intel_engine_cs *engine)
1734 struct i915_gem_context *dctx = engine->i915->kernel_context;
1737 ret = intel_engine_init_common(engine);
1741 /* And setup the hardware status page. */
1742 ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
1744 DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
1751 intel_logical_ring_cleanup(engine);
1755 int logical_render_ring_init(struct intel_engine_cs *engine)
1757 struct drm_i915_private *dev_priv = engine->i915;
1760 logical_ring_setup(engine);
1762 if (HAS_L3_DPF(dev_priv))
1763 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1765 /* Override some for render ring. */
1766 if (INTEL_GEN(dev_priv) >= 9)
1767 engine->init_hw = gen9_init_render_ring;
1769 engine->init_hw = gen8_init_render_ring;
1770 engine->init_context = gen8_init_rcs_context;
1771 engine->emit_flush = gen8_emit_flush_render;
1772 engine->emit_breadcrumb = gen8_emit_breadcrumb_render;
1773 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz;
1775 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
1779 ret = intel_init_workaround_bb(engine);
1782 * We continue even if we fail to initialize WA batch
1783 * because we only expect rare glitches but nothing
1784 * critical to prevent us from using GPU
1786 DRM_ERROR("WA batch buffer initialization failed: %d\n",
1790 return logical_ring_init(engine);
1793 int logical_xcs_ring_init(struct intel_engine_cs *engine)
1795 logical_ring_setup(engine);
1797 return logical_ring_init(engine);
1801 make_rpcs(struct drm_i915_private *dev_priv)
1806 * No explicit RPCS request is needed to ensure full
1807 * slice/subslice/EU enablement prior to Gen9.
1809 if (INTEL_GEN(dev_priv) < 9)
1813 * Starting in Gen9, render power gating can leave
1814 * slice/subslice/EU in a partially enabled state. We
1815 * must make an explicit request through RPCS for full
1818 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
1819 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1820 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
1821 GEN8_RPCS_S_CNT_SHIFT;
1822 rpcs |= GEN8_RPCS_ENABLE;
1825 if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
1826 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1827 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) <<
1828 GEN8_RPCS_SS_CNT_SHIFT;
1829 rpcs |= GEN8_RPCS_ENABLE;
1832 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
1833 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
1834 GEN8_RPCS_EU_MIN_SHIFT;
1835 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
1836 GEN8_RPCS_EU_MAX_SHIFT;
1837 rpcs |= GEN8_RPCS_ENABLE;
1843 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
1845 u32 indirect_ctx_offset;
1847 switch (INTEL_GEN(engine->i915)) {
1849 MISSING_CASE(INTEL_GEN(engine->i915));
1852 indirect_ctx_offset =
1853 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
1856 indirect_ctx_offset =
1857 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
1861 return indirect_ctx_offset;
1864 static void execlists_init_reg_state(u32 *regs,
1865 struct i915_gem_context *ctx,
1866 struct intel_engine_cs *engine,
1867 struct intel_ring *ring)
1869 struct drm_i915_private *dev_priv = engine->i915;
1870 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
1871 u32 base = engine->mmio_base;
1872 bool rcs = engine->id == RCS;
1874 /* A context is actually a big batch buffer with several
1875 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
1876 * values we are setting here are only for the first context restore:
1877 * on a subsequent save, the GPU will recreate this batchbuffer with new
1878 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
1879 * we are not initializing here).
1881 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
1882 MI_LRI_FORCE_POSTED;
1884 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
1885 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
1886 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
1887 (HAS_RESOURCE_STREAMER(dev_priv) ?
1888 CTX_CTRL_RS_CTX_ENABLE : 0)));
1889 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
1890 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
1891 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
1892 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
1893 RING_CTL_SIZE(ring->size) | RING_VALID);
1894 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
1895 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
1896 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
1897 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
1898 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
1899 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
1901 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
1902 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
1903 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
1904 RING_INDIRECT_CTX_OFFSET(base), 0);
1906 if (engine->wa_ctx.vma) {
1907 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1908 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
1910 regs[CTX_RCS_INDIRECT_CTX + 1] =
1911 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
1912 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
1914 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
1915 intel_lr_indirect_ctx_offset(engine) << 6;
1917 regs[CTX_BB_PER_CTX_PTR + 1] =
1918 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
1922 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
1924 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
1925 /* PDP values well be assigned later if needed */
1926 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
1927 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
1928 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
1929 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
1930 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
1931 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
1932 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
1933 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
1935 if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) {
1936 /* 64b PPGTT (48bit canonical)
1937 * PDP0_DESCRIPTOR contains the base address to PML4 and
1938 * other PDP Descriptors are ignored.
1940 ASSIGN_CTX_PML4(ppgtt, regs);
1944 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
1945 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
1946 make_rpcs(dev_priv));
1951 populate_lr_context(struct i915_gem_context *ctx,
1952 struct drm_i915_gem_object *ctx_obj,
1953 struct intel_engine_cs *engine,
1954 struct intel_ring *ring)
1959 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
1961 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
1965 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
1966 if (IS_ERR(vaddr)) {
1967 ret = PTR_ERR(vaddr);
1968 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
1971 ctx_obj->mm.dirty = true;
1973 /* The second page of the context object contains some fields which must
1974 * be set up prior to the first execution. */
1976 execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE,
1979 i915_gem_object_unpin_map(ctx_obj);
1984 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
1985 struct intel_engine_cs *engine)
1987 struct drm_i915_gem_object *ctx_obj;
1988 struct intel_context *ce = &ctx->engine[engine->id];
1989 struct i915_vma *vma;
1990 uint32_t context_size;
1991 struct intel_ring *ring;
1996 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
1998 /* One extra page as the sharing data between driver and GuC */
1999 context_size += PAGE_SIZE * LRC_PPHWSP_PN;
2001 ctx_obj = i915_gem_object_create(ctx->i915, context_size);
2002 if (IS_ERR(ctx_obj)) {
2003 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2004 return PTR_ERR(ctx_obj);
2007 vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL);
2010 goto error_deref_obj;
2013 ring = intel_engine_create_ring(engine, ctx->ring_size);
2015 ret = PTR_ERR(ring);
2016 goto error_deref_obj;
2019 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2021 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2022 goto error_ring_free;
2027 ce->initialised |= engine->init_context == NULL;
2032 intel_ring_free(ring);
2034 i915_gem_object_put(ctx_obj);
2038 void intel_lr_context_resume(struct drm_i915_private *dev_priv)
2040 struct intel_engine_cs *engine;
2041 struct i915_gem_context *ctx;
2042 enum intel_engine_id id;
2044 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2045 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2046 * that stored in context. As we only write new commands from
2047 * ce->ring->tail onwards, everything before that is junk. If the GPU
2048 * starts reading from its RING_HEAD from the context, it may try to
2049 * execute that junk and die.
2051 * So to avoid that we reset the context images upon resume. For
2052 * simplicity, we just zero everything out.
2054 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2055 for_each_engine(engine, dev_priv, id) {
2056 struct intel_context *ce = &ctx->engine[engine->id];
2062 reg = i915_gem_object_pin_map(ce->state->obj,
2064 if (WARN_ON(IS_ERR(reg)))
2067 reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
2068 reg[CTX_RING_HEAD+1] = 0;
2069 reg[CTX_RING_TAIL+1] = 0;
2071 ce->state->obj->mm.dirty = true;
2072 i915_gem_object_unpin_map(ce->state->obj);
2074 intel_ring_reset(ce->ring, 0);