drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * DOC: RC6
  36  *
  37  * RC6 is a special power stage which allows the GPU to enter an very
  38  * low-voltage mode when idle, using down to 0V while at this stage.  This
  39  * stage is entered automatically when the GPU is idle when RC6 support is
  40  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  41  *
  42  * There are different RC6 modes available in Intel GPU, which differentiate
  43  * among each other with the latency required to enter and leave RC6 and
  44  * voltage consumed by the GPU in different states.
  45  *
  46  * The combination of the following flags define which states GPU is allowed
  47  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  48  * RC6pp is deepest RC6. Their support by hardware varies according to the
  49  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  50  * which brings the most power savings; deeper states save more power, but
  51  * require higher latency to switch to and wake up.
  52  */
  53 #define INTEL_RC6_ENABLE                        (1<<0)
  54 #define INTEL_RC6p_ENABLE                       (1<<1)
  55 #define INTEL_RC6pp_ENABLE                      (1<<2)
  56
  57 static void bxt_init_clock_gating(struct drm_device *dev)
  58 {
  59         struct drm_i915_private *dev_priv = dev->dev_private;
  60
  61         /* WaDisableSDEUnitClockGating:bxt */
  62         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  63                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  64
  65         /*
  66          * FIXME:
  67          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  68          */
  69         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  70                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  71
  72         /*
  73          * Wa: Backlight PWM may stop in the asserted state, causing backlight
  74          * to stay fully on.
  75          */
  76         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
  77                 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
  78                            PWM1_GATING_DIS | PWM2_GATING_DIS);
  79 }
  80
  81 static void i915_pineview_get_mem_freq(struct drm_device *dev)
  82 {
  83         struct drm_i915_private *dev_priv = dev->dev_private;
  84         u32 tmp;
  85
  86         tmp = I915_READ(CLKCFG);
  87
  88         switch (tmp & CLKCFG_FSB_MASK) {
  89         case CLKCFG_FSB_533:
  90                 dev_priv->fsb_freq = 533; /* 133*4 */
  91                 break;
  92         case CLKCFG_FSB_800:
  93                 dev_priv->fsb_freq = 800; /* 200*4 */
  94                 break;
  95         case CLKCFG_FSB_667:
  96                 dev_priv->fsb_freq =  667; /* 167*4 */
  97                 break;
  98         case CLKCFG_FSB_400:
  99                 dev_priv->fsb_freq = 400; /* 100*4 */
 100                 break;
 101         }
 102
 103         switch (tmp & CLKCFG_MEM_MASK) {
 104         case CLKCFG_MEM_533:
 105                 dev_priv->mem_freq = 533;
 106                 break;
 107         case CLKCFG_MEM_667:
 108                 dev_priv->mem_freq = 667;
 109                 break;
 110         case CLKCFG_MEM_800:
 111                 dev_priv->mem_freq = 800;
 112                 break;
 113         }
 114
 115         /* detect pineview DDR3 setting */
 116         tmp = I915_READ(CSHRDDR3CTL);
 117         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 118 }
 119
 120 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123         u16 ddrpll, csipll;
 124
 125         ddrpll = I915_READ16(DDRMPLL1);
 126         csipll = I915_READ16(CSIPLL0);
 127
 128         switch (ddrpll & 0xff) {
 129         case 0xc:
 130                 dev_priv->mem_freq = 800;
 131                 break;
 132         case 0x10:
 133                 dev_priv->mem_freq = 1066;
 134                 break;
 135         case 0x14:
 136                 dev_priv->mem_freq = 1333;
 137                 break;
 138         case 0x18:
 139                 dev_priv->mem_freq = 1600;
 140                 break;
 141         default:
 142                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 143                                  ddrpll & 0xff);
 144                 dev_priv->mem_freq = 0;
 145                 break;
 146         }
 147
 148         dev_priv->ips.r_t = dev_priv->mem_freq;
 149
 150         switch (csipll & 0x3ff) {
 151         case 0x00c:
 152                 dev_priv->fsb_freq = 3200;
 153                 break;
 154         case 0x00e:
 155                 dev_priv->fsb_freq = 3733;
 156                 break;
 157         case 0x010:
 158                 dev_priv->fsb_freq = 4266;
 159                 break;
 160         case 0x012:
 161                 dev_priv->fsb_freq = 4800;
 162                 break;
 163         case 0x014:
 164                 dev_priv->fsb_freq = 5333;
 165                 break;
 166         case 0x016:
 167                 dev_priv->fsb_freq = 5866;
 168                 break;
 169         case 0x018:
 170                 dev_priv->fsb_freq = 6400;
 171                 break;
 172         default:
 173                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 174                                  csipll & 0x3ff);
 175                 dev_priv->fsb_freq = 0;
 176                 break;
 177         }
 178
 179         if (dev_priv->fsb_freq == 3200) {
 180                 dev_priv->ips.c_m = 0;
 181         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 182                 dev_priv->ips.c_m = 1;
 183         } else {
 184                 dev_priv->ips.c_m = 2;
 185         }
 186 }
 187
 188 static const struct cxsr_latency cxsr_latency_table[] = {
 189         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 190         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 191         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 192         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 193         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 194
 195         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 196         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 197         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 198         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 199         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 200
 201         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 202         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 203         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 204         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 205         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 206
 207         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 208         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 209         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 210         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 211         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 212
 213         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 214         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 215         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 216         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 217         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 218
 219         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 220         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 221         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 222         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 223         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 224 };
 225
 226 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 227                                                          int is_ddr3,
 228                                                          int fsb,
 229                                                          int mem)
 230 {
 231         const struct cxsr_latency *latency;
 232         int i;
 233
 234         if (fsb == 0 || mem == 0)
 235                 return NULL;
 236
 237         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 238                 latency = &cxsr_latency_table[i];
 239                 if (is_desktop == latency->is_desktop &&
 240                     is_ddr3 == latency->is_ddr3 &&
 241                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 242                         return latency;
 243         }
 244
 245         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 246
 247         return NULL;
 248 }
 249
 250 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 251 {
 252         u32 val;
 253
 254         mutex_lock(&dev_priv->rps.hw_lock);
 255
 256         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 257         if (enable)
 258                 val &= ~FORCE_DDR_HIGH_FREQ;
 259         else
 260                 val |= FORCE_DDR_HIGH_FREQ;
 261         val &= ~FORCE_DDR_LOW_FREQ;
 262         val |= FORCE_DDR_FREQ_REQ_ACK;
 263         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 264
 265         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 266                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 267                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 268
 269         mutex_unlock(&dev_priv->rps.hw_lock);
 270 }
 271
 272 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 273 {
 274         u32 val;
 275
 276         mutex_lock(&dev_priv->rps.hw_lock);
 277
 278         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 279         if (enable)
 280                 val |= DSP_MAXFIFO_PM5_ENABLE;
 281         else
 282                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 283         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 284
 285         mutex_unlock(&dev_priv->rps.hw_lock);
 286 }
 287
 288 #define FW_WM(value, plane) \
 289         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 290
 291 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 292 {
 293         struct drm_device *dev = dev_priv->dev;
 294         u32 val;
 295
 296         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 297                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 298                 POSTING_READ(FW_BLC_SELF_VLV);
 299                 dev_priv->wm.vlv.cxsr = enable;
 300         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 301                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 302                 POSTING_READ(FW_BLC_SELF);
 303         } else if (IS_PINEVIEW(dev)) {
 304                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 305                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 306                 I915_WRITE(DSPFW3, val);
 307                 POSTING_READ(DSPFW3);
 308         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 309                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 310                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 311                 I915_WRITE(FW_BLC_SELF, val);
 312                 POSTING_READ(FW_BLC_SELF);
 313         } else if (IS_I915GM(dev)) {
 314                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 315                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 316                 I915_WRITE(INSTPM, val);
 317                 POSTING_READ(INSTPM);
 318         } else {
 319                 return;
 320         }
 321
 322         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 323                       enable ? "enabled" : "disabled");
 324 }
 325
 326
 327 /*
 328  * Latency for FIFO fetches is dependent on several factors:
 329  *   - memory configuration (speed, channels)
 330  *   - chipset
 331  *   - current MCH state
 332  * It can be fairly high in some situations, so here we assume a fairly
 333  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 334  * set this value too high, the FIFO will fetch frequently to stay full)
 335  * and power consumption (set it too low to save power and we might see
 336  * FIFO underruns and display "flicker").
 337  *
 338  * A value of 5us seems to be a good balance; safe for very low end
 339  * platforms but not overly aggressive on lower latency configs.
 340  */
 341 static const int pessimal_latency_ns = 5000;
 342
 343 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 344         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 345
 346 static int vlv_get_fifo_size(struct drm_device *dev,
 347                               enum pipe pipe, int plane)
 348 {
 349         struct drm_i915_private *dev_priv = dev->dev_private;
 350         int sprite0_start, sprite1_start, size;
 351
 352         switch (pipe) {
 353                 uint32_t dsparb, dsparb2, dsparb3;
 354         case PIPE_A:
 355                 dsparb = I915_READ(DSPARB);
 356                 dsparb2 = I915_READ(DSPARB2);
 357                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 358                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 359                 break;
 360         case PIPE_B:
 361                 dsparb = I915_READ(DSPARB);
 362                 dsparb2 = I915_READ(DSPARB2);
 363                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 364                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 365                 break;
 366         case PIPE_C:
 367                 dsparb2 = I915_READ(DSPARB2);
 368                 dsparb3 = I915_READ(DSPARB3);
 369                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 370                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 371                 break;
 372         default:
 373                 return 0;
 374         }
 375
 376         switch (plane) {
 377         case 0:
 378                 size = sprite0_start;
 379                 break;
 380         case 1:
 381                 size = sprite1_start - sprite0_start;
 382                 break;
 383         case 2:
 384                 size = 512 - 1 - sprite1_start;
 385                 break;
 386         default:
 387                 return 0;
 388         }
 389
 390         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 391                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 392                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 393                       size);
 394
 395         return size;
 396 }
 397
 398 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 399 {
 400         struct drm_i915_private *dev_priv = dev->dev_private;
 401         uint32_t dsparb = I915_READ(DSPARB);
 402         int size;
 403
 404         size = dsparb & 0x7f;
 405         if (plane)
 406                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 407
 408         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 409                       plane ? "B" : "A", size);
 410
 411         return size;
 412 }
 413
 414 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 415 {
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417         uint32_t dsparb = I915_READ(DSPARB);
 418         int size;
 419
 420         size = dsparb & 0x1ff;
 421         if (plane)
 422                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 423         size >>= 1; /* Convert to cachelines */
 424
 425         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 426                       plane ? "B" : "A", size);
 427
 428         return size;
 429 }
 430
 431 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 432 {
 433         struct drm_i915_private *dev_priv = dev->dev_private;
 434         uint32_t dsparb = I915_READ(DSPARB);
 435         int size;
 436
 437         size = dsparb & 0x7f;
 438         size >>= 2; /* Convert to cachelines */
 439
 440         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 441                       plane ? "B" : "A",
 442                       size);
 443
 444         return size;
 445 }
 446
 447 /* Pineview has different values for various configs */
 448 static const struct intel_watermark_params pineview_display_wm = {
 449         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 450         .max_wm = PINEVIEW_MAX_WM,
 451         .default_wm = PINEVIEW_DFT_WM,
 452         .guard_size = PINEVIEW_GUARD_WM,
 453         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 454 };
 455 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 456         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 457         .max_wm = PINEVIEW_MAX_WM,
 458         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 459         .guard_size = PINEVIEW_GUARD_WM,
 460         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 461 };
 462 static const struct intel_watermark_params pineview_cursor_wm = {
 463         .fifo_size = PINEVIEW_CURSOR_FIFO,
 464         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 465         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 466         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 467         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 468 };
 469 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 470         .fifo_size = PINEVIEW_CURSOR_FIFO,
 471         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 472         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 473         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 474         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 475 };
 476 static const struct intel_watermark_params g4x_wm_info = {
 477         .fifo_size = G4X_FIFO_SIZE,
 478         .max_wm = G4X_MAX_WM,
 479         .default_wm = G4X_MAX_WM,
 480         .guard_size = 2,
 481         .cacheline_size = G4X_FIFO_LINE_SIZE,
 482 };
 483 static const struct intel_watermark_params g4x_cursor_wm_info = {
 484         .fifo_size = I965_CURSOR_FIFO,
 485         .max_wm = I965_CURSOR_MAX_WM,
 486         .default_wm = I965_CURSOR_DFT_WM,
 487         .guard_size = 2,
 488         .cacheline_size = G4X_FIFO_LINE_SIZE,
 489 };
 490 static const struct intel_watermark_params valleyview_wm_info = {
 491         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 492         .max_wm = VALLEYVIEW_MAX_WM,
 493         .default_wm = VALLEYVIEW_MAX_WM,
 494         .guard_size = 2,
 495         .cacheline_size = G4X_FIFO_LINE_SIZE,
 496 };
 497 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 498         .fifo_size = I965_CURSOR_FIFO,
 499         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 500         .default_wm = I965_CURSOR_DFT_WM,
 501         .guard_size = 2,
 502         .cacheline_size = G4X_FIFO_LINE_SIZE,
 503 };
 504 static const struct intel_watermark_params i965_cursor_wm_info = {
 505         .fifo_size = I965_CURSOR_FIFO,
 506         .max_wm = I965_CURSOR_MAX_WM,
 507         .default_wm = I965_CURSOR_DFT_WM,
 508         .guard_size = 2,
 509         .cacheline_size = I915_FIFO_LINE_SIZE,
 510 };
 511 static const struct intel_watermark_params i945_wm_info = {
 512         .fifo_size = I945_FIFO_SIZE,
 513         .max_wm = I915_MAX_WM,
 514         .default_wm = 1,
 515         .guard_size = 2,
 516         .cacheline_size = I915_FIFO_LINE_SIZE,
 517 };
 518 static const struct intel_watermark_params i915_wm_info = {
 519         .fifo_size = I915_FIFO_SIZE,
 520         .max_wm = I915_MAX_WM,
 521         .default_wm = 1,
 522         .guard_size = 2,
 523         .cacheline_size = I915_FIFO_LINE_SIZE,
 524 };
 525 static const struct intel_watermark_params i830_a_wm_info = {
 526         .fifo_size = I855GM_FIFO_SIZE,
 527         .max_wm = I915_MAX_WM,
 528         .default_wm = 1,
 529         .guard_size = 2,
 530         .cacheline_size = I830_FIFO_LINE_SIZE,
 531 };
 532 static const struct intel_watermark_params i830_bc_wm_info = {
 533         .fifo_size = I855GM_FIFO_SIZE,
 534         .max_wm = I915_MAX_WM/2,
 535         .default_wm = 1,
 536         .guard_size = 2,
 537         .cacheline_size = I830_FIFO_LINE_SIZE,
 538 };
 539 static const struct intel_watermark_params i845_wm_info = {
 540         .fifo_size = I830_FIFO_SIZE,
 541         .max_wm = I915_MAX_WM,
 542         .default_wm = 1,
 543         .guard_size = 2,
 544         .cacheline_size = I830_FIFO_LINE_SIZE,
 545 };
 546
 547 /**
 548  * intel_calculate_wm - calculate watermark level
 549  * @clock_in_khz: pixel clock
 550  * @wm: chip FIFO params
 551  * @pixel_size: display pixel size
 552  * @latency_ns: memory latency for the platform
 553  *
 554  * Calculate the watermark level (the level at which the display plane will
 555  * start fetching from memory again).  Each chip has a different display
 556  * FIFO size and allocation, so the caller needs to figure that out and pass
 557  * in the correct intel_watermark_params structure.
 558  *
 559  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 560  * on the pixel size.  When it reaches the watermark level, it'll start
 561  * fetching FIFO line sized based chunks from memory until the FIFO fills
 562  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 563  * will occur, and a display engine hang could result.
 564  */
 565 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 566                                         const struct intel_watermark_params *wm,
 567                                         int fifo_size,
 568                                         int pixel_size,
 569                                         unsigned long latency_ns)
 570 {
 571         long entries_required, wm_size;
 572
 573         /*
 574          * Note: we need to make sure we don't overflow for various clock &
 575          * latency values.
 576          * clocks go from a few thousand to several hundred thousand.
 577          * latency is usually a few thousand
 578          */
 579         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 580                 1000;
 581         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 582
 583         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 584
 585         wm_size = fifo_size - (entries_required + wm->guard_size);
 586
 587         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 588
 589         /* Don't promote wm_size to unsigned... */
 590         if (wm_size > (long)wm->max_wm)
 591                 wm_size = wm->max_wm;
 592         if (wm_size <= 0)
 593                 wm_size = wm->default_wm;
 594
 595         /*
 596          * Bspec seems to indicate that the value shouldn't be lower than
 597          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 598          * Lets go for 8 which is the burst size since certain platforms
 599          * already use a hardcoded 8 (which is what the spec says should be
 600          * done).
 601          */
 602         if (wm_size <= 8)
 603                 wm_size = 8;
 604
 605         return wm_size;
 606 }
 607
 608 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 609 {
 610         struct drm_crtc *crtc, *enabled = NULL;
 611
 612         for_each_crtc(dev, crtc) {
 613                 if (intel_crtc_active(crtc)) {
 614                         if (enabled)
 615                                 return NULL;
 616                         enabled = crtc;
 617                 }
 618         }
 619
 620         return enabled;
 621 }
 622
 623 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 624 {
 625         struct drm_device *dev = unused_crtc->dev;
 626         struct drm_i915_private *dev_priv = dev->dev_private;
 627         struct drm_crtc *crtc;
 628         const struct cxsr_latency *latency;
 629         u32 reg;
 630         unsigned long wm;
 631
 632         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 633                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 634         if (!latency) {
 635                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 636                 intel_set_memory_cxsr(dev_priv, false);
 637                 return;
 638         }
 639
 640         crtc = single_enabled_crtc(dev);
 641         if (crtc) {
 642                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 643                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 644                 int clock = adjusted_mode->crtc_clock;
 645
 646                 /* Display SR */
 647                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 648                                         pineview_display_wm.fifo_size,
 649                                         pixel_size, latency->display_sr);
 650                 reg = I915_READ(DSPFW1);
 651                 reg &= ~DSPFW_SR_MASK;
 652                 reg |= FW_WM(wm, SR);
 653                 I915_WRITE(DSPFW1, reg);
 654                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 655
 656                 /* cursor SR */
 657                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 658                                         pineview_display_wm.fifo_size,
 659                                         pixel_size, latency->cursor_sr);
 660                 reg = I915_READ(DSPFW3);
 661                 reg &= ~DSPFW_CURSOR_SR_MASK;
 662                 reg |= FW_WM(wm, CURSOR_SR);
 663                 I915_WRITE(DSPFW3, reg);
 664
 665                 /* Display HPLL off SR */
 666                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 667                                         pineview_display_hplloff_wm.fifo_size,
 668                                         pixel_size, latency->display_hpll_disable);
 669                 reg = I915_READ(DSPFW3);
 670                 reg &= ~DSPFW_HPLL_SR_MASK;
 671                 reg |= FW_WM(wm, HPLL_SR);
 672                 I915_WRITE(DSPFW3, reg);
 673
 674                 /* cursor HPLL off SR */
 675                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 676                                         pineview_display_hplloff_wm.fifo_size,
 677                                         pixel_size, latency->cursor_hpll_disable);
 678                 reg = I915_READ(DSPFW3);
 679                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 680                 reg |= FW_WM(wm, HPLL_CURSOR);
 681                 I915_WRITE(DSPFW3, reg);
 682                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 683
 684                 intel_set_memory_cxsr(dev_priv, true);
 685         } else {
 686                 intel_set_memory_cxsr(dev_priv, false);
 687         }
 688 }
 689
 690 static bool g4x_compute_wm0(struct drm_device *dev,
 691                             int plane,
 692                             const struct intel_watermark_params *display,
 693                             int display_latency_ns,
 694                             const struct intel_watermark_params *cursor,
 695                             int cursor_latency_ns,
 696                             int *plane_wm,
 697                             int *cursor_wm)
 698 {
 699         struct drm_crtc *crtc;
 700         const struct drm_display_mode *adjusted_mode;
 701         int htotal, hdisplay, clock, pixel_size;
 702         int line_time_us, line_count;
 703         int entries, tlb_miss;
 704
 705         crtc = intel_get_crtc_for_plane(dev, plane);
 706         if (!intel_crtc_active(crtc)) {
 707                 *cursor_wm = cursor->guard_size;
 708                 *plane_wm = display->guard_size;
 709                 return false;
 710         }
 711
 712         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 713         clock = adjusted_mode->crtc_clock;
 714         htotal = adjusted_mode->crtc_htotal;
 715         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 716         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 717
 718         /* Use the small buffer method to calculate plane watermark */
 719         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
 720         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 721         if (tlb_miss > 0)
 722                 entries += tlb_miss;
 723         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 724         *plane_wm = entries + display->guard_size;
 725         if (*plane_wm > (int)display->max_wm)
 726                 *plane_wm = display->max_wm;
 727
 728         /* Use the large buffer method to calculate cursor watermark */
 729         line_time_us = max(htotal * 1000 / clock, 1);
 730         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 731         entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
 732         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 733         if (tlb_miss > 0)
 734                 entries += tlb_miss;
 735         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 736         *cursor_wm = entries + cursor->guard_size;
 737         if (*cursor_wm > (int)cursor->max_wm)
 738                 *cursor_wm = (int)cursor->max_wm;
 739
 740         return true;
 741 }
 742
 743 /*
 744  * Check the wm result.
 745  *
 746  * If any calculated watermark values is larger than the maximum value that
 747  * can be programmed into the associated watermark register, that watermark
 748  * must be disabled.
 749  */
 750 static bool g4x_check_srwm(struct drm_device *dev,
 751                            int display_wm, int cursor_wm,
 752                            const struct intel_watermark_params *display,
 753                            const struct intel_watermark_params *cursor)
 754 {
 755         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 756                       display_wm, cursor_wm);
 757
 758         if (display_wm > display->max_wm) {
 759                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 760                               display_wm, display->max_wm);
 761                 return false;
 762         }
 763
 764         if (cursor_wm > cursor->max_wm) {
 765                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 766                               cursor_wm, cursor->max_wm);
 767                 return false;
 768         }
 769
 770         if (!(display_wm || cursor_wm)) {
 771                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 772                 return false;
 773         }
 774
 775         return true;
 776 }
 777
 778 static bool g4x_compute_srwm(struct drm_device *dev,
 779                              int plane,
 780                              int latency_ns,
 781                              const struct intel_watermark_params *display,
 782                              const struct intel_watermark_params *cursor,
 783                              int *display_wm, int *cursor_wm)
 784 {
 785         struct drm_crtc *crtc;
 786         const struct drm_display_mode *adjusted_mode;
 787         int hdisplay, htotal, pixel_size, clock;
 788         unsigned long line_time_us;
 789         int line_count, line_size;
 790         int small, large;
 791         int entries;
 792
 793         if (!latency_ns) {
 794                 *display_wm = *cursor_wm = 0;
 795                 return false;
 796         }
 797
 798         crtc = intel_get_crtc_for_plane(dev, plane);
 799         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 800         clock = adjusted_mode->crtc_clock;
 801         htotal = adjusted_mode->crtc_htotal;
 802         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 803         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 804
 805         line_time_us = max(htotal * 1000 / clock, 1);
 806         line_count = (latency_ns / line_time_us + 1000) / 1000;
 807         line_size = hdisplay * pixel_size;
 808
 809         /* Use the minimum of the small and large buffer method for primary */
 810         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 811         large = line_count * line_size;
 812
 813         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 814         *display_wm = entries + display->guard_size;
 815
 816         /* calculate the self-refresh watermark for display cursor */
 817         entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
 818         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 819         *cursor_wm = entries + cursor->guard_size;
 820
 821         return g4x_check_srwm(dev,
 822                               *display_wm, *cursor_wm,
 823                               display, cursor);
 824 }
 825
 826 #define FW_WM_VLV(value, plane) \
 827         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 828
 829 static void vlv_write_wm_values(struct intel_crtc *crtc,
 830                                 const struct vlv_wm_values *wm)
 831 {
 832         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 833         enum pipe pipe = crtc->pipe;
 834
 835         I915_WRITE(VLV_DDL(pipe),
 836                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 837                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 838                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 839                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 840
 841         I915_WRITE(DSPFW1,
 842                    FW_WM(wm->sr.plane, SR) |
 843                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 844                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 845                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 846         I915_WRITE(DSPFW2,
 847                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 848                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 849                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 850         I915_WRITE(DSPFW3,
 851                    FW_WM(wm->sr.cursor, CURSOR_SR));
 852
 853         if (IS_CHERRYVIEW(dev_priv)) {
 854                 I915_WRITE(DSPFW7_CHV,
 855                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 856                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 857                 I915_WRITE(DSPFW8_CHV,
 858                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 859                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 860                 I915_WRITE(DSPFW9_CHV,
 861                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 862                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 863                 I915_WRITE(DSPHOWM,
 864                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 865                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 866                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 867                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 868                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 869                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 870                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 871                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 872                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 873                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 874         } else {
 875                 I915_WRITE(DSPFW7,
 876                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 877                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 878                 I915_WRITE(DSPHOWM,
 879                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 880                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 881                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 882                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 883                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 884                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 885                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 886         }
 887
 888         /* zero (unused) WM1 watermarks */
 889         I915_WRITE(DSPFW4, 0);
 890         I915_WRITE(DSPFW5, 0);
 891         I915_WRITE(DSPFW6, 0);
 892         I915_WRITE(DSPHOWM1, 0);
 893
 894         POSTING_READ(DSPFW1);
 895 }
 896
 897 #undef FW_WM_VLV
 898
 899 enum vlv_wm_level {
 900         VLV_WM_LEVEL_PM2,
 901         VLV_WM_LEVEL_PM5,
 902         VLV_WM_LEVEL_DDR_DVFS,
 903 };
 904
 905 /* latency must be in 0.1us units. */
 906 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 907                                    unsigned int pipe_htotal,
 908                                    unsigned int horiz_pixels,
 909                                    unsigned int bytes_per_pixel,
 910                                    unsigned int latency)
 911 {
 912         unsigned int ret;
 913
 914         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 915         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
 916         ret = DIV_ROUND_UP(ret, 64);
 917
 918         return ret;
 919 }
 920
 921 static void vlv_setup_wm_latency(struct drm_device *dev)
 922 {
 923         struct drm_i915_private *dev_priv = dev->dev_private;
 924
 925         /* all latencies in usec */
 926         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 927
 928         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 929
 930         if (IS_CHERRYVIEW(dev_priv)) {
 931                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 932                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 933
 934                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 935         }
 936 }
 937
 938 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 939                                      struct intel_crtc *crtc,
 940                                      const struct intel_plane_state *state,
 941                                      int level)
 942 {
 943         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 944         int clock, htotal, pixel_size, width, wm;
 945
 946         if (dev_priv->wm.pri_latency[level] == 0)
 947                 return USHRT_MAX;
 948
 949         if (!state->visible)
 950                 return 0;
 951
 952         pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 953         clock = crtc->config->base.adjusted_mode.crtc_clock;
 954         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 955         width = crtc->config->pipe_src_w;
 956         if (WARN_ON(htotal == 0))
 957                 htotal = 1;
 958
 959         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 960                 /*
 961                  * FIXME the formula gives values that are
 962                  * too big for the cursor FIFO, and hence we
 963                  * would never be able to use cursors. For
 964                  * now just hardcode the watermark.
 965                  */
 966                 wm = 63;
 967         } else {
 968                 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
 969                                     dev_priv->wm.pri_latency[level] * 10);
 970         }
 971
 972         return min_t(int, wm, USHRT_MAX);
 973 }
 974
 975 static void vlv_compute_fifo(struct intel_crtc *crtc)
 976 {
 977         struct drm_device *dev = crtc->base.dev;
 978         struct vlv_wm_state *wm_state = &crtc->wm_state;
 979         struct intel_plane *plane;
 980         unsigned int total_rate = 0;
 981         const int fifo_size = 512 - 1;
 982         int fifo_extra, fifo_left = fifo_size;
 983
 984         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 985                 struct intel_plane_state *state =
 986                         to_intel_plane_state(plane->base.state);
 987
 988                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 989                         continue;
 990
 991                 if (state->visible) {
 992                         wm_state->num_active_planes++;
 993                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 994                 }
 995         }
 996
 997         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 998                 struct intel_plane_state *state =
 999                         to_intel_plane_state(plane->base.state);
1000                 unsigned int rate;
1001
1002                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1003                         plane->wm.fifo_size = 63;
1004                         continue;
1005                 }
1006
1007                 if (!state->visible) {
1008                         plane->wm.fifo_size = 0;
1009                         continue;
1010                 }
1011
1012                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1014                 fifo_left -= plane->wm.fifo_size;
1015         }
1016
1017         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1018
1019         /* spread the remainder evenly */
1020         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1021                 int plane_extra;
1022
1023                 if (fifo_left == 0)
1024                         break;
1025
1026                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1027                         continue;
1028
1029                 /* give it all to the first plane if none are active */
1030                 if (plane->wm.fifo_size == 0 &&
1031                     wm_state->num_active_planes)
1032                         continue;
1033
1034                 plane_extra = min(fifo_extra, fifo_left);
1035                 plane->wm.fifo_size += plane_extra;
1036                 fifo_left -= plane_extra;
1037         }
1038
1039         WARN_ON(fifo_left != 0);
1040 }
1041
1042 static void vlv_invert_wms(struct intel_crtc *crtc)
1043 {
1044         struct vlv_wm_state *wm_state = &crtc->wm_state;
1045         int level;
1046
1047         for (level = 0; level < wm_state->num_levels; level++) {
1048                 struct drm_device *dev = crtc->base.dev;
1049                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1050                 struct intel_plane *plane;
1051
1052                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1053                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1054
1055                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1056                         switch (plane->base.type) {
1057                                 int sprite;
1058                         case DRM_PLANE_TYPE_CURSOR:
1059                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1060                                         wm_state->wm[level].cursor;
1061                                 break;
1062                         case DRM_PLANE_TYPE_PRIMARY:
1063                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1064                                         wm_state->wm[level].primary;
1065                                 break;
1066                         case DRM_PLANE_TYPE_OVERLAY:
1067                                 sprite = plane->plane;
1068                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1069                                         wm_state->wm[level].sprite[sprite];
1070                                 break;
1071                         }
1072                 }
1073         }
1074 }
1075
1076 static void vlv_compute_wm(struct intel_crtc *crtc)
1077 {
1078         struct drm_device *dev = crtc->base.dev;
1079         struct vlv_wm_state *wm_state = &crtc->wm_state;
1080         struct intel_plane *plane;
1081         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1082         int level;
1083
1084         memset(wm_state, 0, sizeof(*wm_state));
1085
1086         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1087         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1088
1089         wm_state->num_active_planes = 0;
1090
1091         vlv_compute_fifo(crtc);
1092
1093         if (wm_state->num_active_planes != 1)
1094                 wm_state->cxsr = false;
1095
1096         if (wm_state->cxsr) {
1097                 for (level = 0; level < wm_state->num_levels; level++) {
1098                         wm_state->sr[level].plane = sr_fifo_size;
1099                         wm_state->sr[level].cursor = 63;
1100                 }
1101         }
1102
1103         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1104                 struct intel_plane_state *state =
1105                         to_intel_plane_state(plane->base.state);
1106
1107                 if (!state->visible)
1108                         continue;
1109
1110                 /* normal watermarks */
1111                 for (level = 0; level < wm_state->num_levels; level++) {
1112                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1113                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1114
1115                         /* hack */
1116                         if (WARN_ON(level == 0 && wm > max_wm))
1117                                 wm = max_wm;
1118
1119                         if (wm > plane->wm.fifo_size)
1120                                 break;
1121
1122                         switch (plane->base.type) {
1123                                 int sprite;
1124                         case DRM_PLANE_TYPE_CURSOR:
1125                                 wm_state->wm[level].cursor = wm;
1126                                 break;
1127                         case DRM_PLANE_TYPE_PRIMARY:
1128                                 wm_state->wm[level].primary = wm;
1129                                 break;
1130                         case DRM_PLANE_TYPE_OVERLAY:
1131                                 sprite = plane->plane;
1132                                 wm_state->wm[level].sprite[sprite] = wm;
1133                                 break;
1134                         }
1135                 }
1136
1137                 wm_state->num_levels = level;
1138
1139                 if (!wm_state->cxsr)
1140                         continue;
1141
1142                 /* maxfifo watermarks */
1143                 switch (plane->base.type) {
1144                         int sprite, level;
1145                 case DRM_PLANE_TYPE_CURSOR:
1146                         for (level = 0; level < wm_state->num_levels; level++)
1147                                 wm_state->sr[level].cursor =
1148                                         wm_state->wm[level].cursor;
1149                         break;
1150                 case DRM_PLANE_TYPE_PRIMARY:
1151                         for (level = 0; level < wm_state->num_levels; level++)
1152                                 wm_state->sr[level].plane =
1153                                         min(wm_state->sr[level].plane,
1154                                             wm_state->wm[level].primary);
1155                         break;
1156                 case DRM_PLANE_TYPE_OVERLAY:
1157                         sprite = plane->plane;
1158                         for (level = 0; level < wm_state->num_levels; level++)
1159                                 wm_state->sr[level].plane =
1160                                         min(wm_state->sr[level].plane,
1161                                             wm_state->wm[level].sprite[sprite]);
1162                         break;
1163                 }
1164         }
1165
1166         /* clear any (partially) filled invalid levels */
1167         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1168                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1169                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1170         }
1171
1172         vlv_invert_wms(crtc);
1173 }
1174
1175 #define VLV_FIFO(plane, value) \
1176         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1177
1178 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1179 {
1180         struct drm_device *dev = crtc->base.dev;
1181         struct drm_i915_private *dev_priv = to_i915(dev);
1182         struct intel_plane *plane;
1183         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1184
1185         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1186                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1187                         WARN_ON(plane->wm.fifo_size != 63);
1188                         continue;
1189                 }
1190
1191                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1192                         sprite0_start = plane->wm.fifo_size;
1193                 else if (plane->plane == 0)
1194                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1195                 else
1196                         fifo_size = sprite1_start + plane->wm.fifo_size;
1197         }
1198
1199         WARN_ON(fifo_size != 512 - 1);
1200
1201         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1202                       pipe_name(crtc->pipe), sprite0_start,
1203                       sprite1_start, fifo_size);
1204
1205         switch (crtc->pipe) {
1206                 uint32_t dsparb, dsparb2, dsparb3;
1207         case PIPE_A:
1208                 dsparb = I915_READ(DSPARB);
1209                 dsparb2 = I915_READ(DSPARB2);
1210
1211                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1212                             VLV_FIFO(SPRITEB, 0xff));
1213                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1214                            VLV_FIFO(SPRITEB, sprite1_start));
1215
1216                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1217                              VLV_FIFO(SPRITEB_HI, 0x1));
1218                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1219                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1220
1221                 I915_WRITE(DSPARB, dsparb);
1222                 I915_WRITE(DSPARB2, dsparb2);
1223                 break;
1224         case PIPE_B:
1225                 dsparb = I915_READ(DSPARB);
1226                 dsparb2 = I915_READ(DSPARB2);
1227
1228                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1229                             VLV_FIFO(SPRITED, 0xff));
1230                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1231                            VLV_FIFO(SPRITED, sprite1_start));
1232
1233                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1234                              VLV_FIFO(SPRITED_HI, 0xff));
1235                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1236                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1237
1238                 I915_WRITE(DSPARB, dsparb);
1239                 I915_WRITE(DSPARB2, dsparb2);
1240                 break;
1241         case PIPE_C:
1242                 dsparb3 = I915_READ(DSPARB3);
1243                 dsparb2 = I915_READ(DSPARB2);
1244
1245                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1246                              VLV_FIFO(SPRITEF, 0xff));
1247                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1248                             VLV_FIFO(SPRITEF, sprite1_start));
1249
1250                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1251                              VLV_FIFO(SPRITEF_HI, 0xff));
1252                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1253                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1254
1255                 I915_WRITE(DSPARB3, dsparb3);
1256                 I915_WRITE(DSPARB2, dsparb2);
1257                 break;
1258         default:
1259                 break;
1260         }
1261 }
1262
1263 #undef VLV_FIFO
1264
1265 static void vlv_merge_wm(struct drm_device *dev,
1266                          struct vlv_wm_values *wm)
1267 {
1268         struct intel_crtc *crtc;
1269         int num_active_crtcs = 0;
1270
1271         wm->level = to_i915(dev)->wm.max_level;
1272         wm->cxsr = true;
1273
1274         for_each_intel_crtc(dev, crtc) {
1275                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1276
1277                 if (!crtc->active)
1278                         continue;
1279
1280                 if (!wm_state->cxsr)
1281                         wm->cxsr = false;
1282
1283                 num_active_crtcs++;
1284                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1285         }
1286
1287         if (num_active_crtcs != 1)
1288                 wm->cxsr = false;
1289
1290         if (num_active_crtcs > 1)
1291                 wm->level = VLV_WM_LEVEL_PM2;
1292
1293         for_each_intel_crtc(dev, crtc) {
1294                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1295                 enum pipe pipe = crtc->pipe;
1296
1297                 if (!crtc->active)
1298                         continue;
1299
1300                 wm->pipe[pipe] = wm_state->wm[wm->level];
1301                 if (wm->cxsr)
1302                         wm->sr = wm_state->sr[wm->level];
1303
1304                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1305                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1306                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1307                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1308         }
1309 }
1310
1311 static void vlv_update_wm(struct drm_crtc *crtc)
1312 {
1313         struct drm_device *dev = crtc->dev;
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1316         enum pipe pipe = intel_crtc->pipe;
1317         struct vlv_wm_values wm = {};
1318
1319         vlv_compute_wm(intel_crtc);
1320         vlv_merge_wm(dev, &wm);
1321
1322         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1323                 /* FIXME should be part of crtc atomic commit */
1324                 vlv_pipe_set_fifo_size(intel_crtc);
1325                 return;
1326         }
1327
1328         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1329             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1330                 chv_set_memory_dvfs(dev_priv, false);
1331
1332         if (wm.level < VLV_WM_LEVEL_PM5 &&
1333             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1334                 chv_set_memory_pm5(dev_priv, false);
1335
1336         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1337                 intel_set_memory_cxsr(dev_priv, false);
1338
1339         /* FIXME should be part of crtc atomic commit */
1340         vlv_pipe_set_fifo_size(intel_crtc);
1341
1342         vlv_write_wm_values(intel_crtc, &wm);
1343
1344         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1345                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1346                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1347                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1348                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1349
1350         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1351                 intel_set_memory_cxsr(dev_priv, true);
1352
1353         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1354             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1355                 chv_set_memory_pm5(dev_priv, true);
1356
1357         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1358             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1359                 chv_set_memory_dvfs(dev_priv, true);
1360
1361         dev_priv->wm.vlv = wm;
1362 }
1363
1364 #define single_plane_enabled(mask) is_power_of_2(mask)
1365
1366 static void g4x_update_wm(struct drm_crtc *crtc)
1367 {
1368         struct drm_device *dev = crtc->dev;
1369         static const int sr_latency_ns = 12000;
1370         struct drm_i915_private *dev_priv = dev->dev_private;
1371         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1372         int plane_sr, cursor_sr;
1373         unsigned int enabled = 0;
1374         bool cxsr_enabled;
1375
1376         if (g4x_compute_wm0(dev, PIPE_A,
1377                             &g4x_wm_info, pessimal_latency_ns,
1378                             &g4x_cursor_wm_info, pessimal_latency_ns,
1379                             &planea_wm, &cursora_wm))
1380                 enabled |= 1 << PIPE_A;
1381
1382         if (g4x_compute_wm0(dev, PIPE_B,
1383                             &g4x_wm_info, pessimal_latency_ns,
1384                             &g4x_cursor_wm_info, pessimal_latency_ns,
1385                             &planeb_wm, &cursorb_wm))
1386                 enabled |= 1 << PIPE_B;
1387
1388         if (single_plane_enabled(enabled) &&
1389             g4x_compute_srwm(dev, ffs(enabled) - 1,
1390                              sr_latency_ns,
1391                              &g4x_wm_info,
1392                              &g4x_cursor_wm_info,
1393                              &plane_sr, &cursor_sr)) {
1394                 cxsr_enabled = true;
1395         } else {
1396                 cxsr_enabled = false;
1397                 intel_set_memory_cxsr(dev_priv, false);
1398                 plane_sr = cursor_sr = 0;
1399         }
1400
1401         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1402                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1403                       planea_wm, cursora_wm,
1404                       planeb_wm, cursorb_wm,
1405                       plane_sr, cursor_sr);
1406
1407         I915_WRITE(DSPFW1,
1408                    FW_WM(plane_sr, SR) |
1409                    FW_WM(cursorb_wm, CURSORB) |
1410                    FW_WM(planeb_wm, PLANEB) |
1411                    FW_WM(planea_wm, PLANEA));
1412         I915_WRITE(DSPFW2,
1413                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1414                    FW_WM(cursora_wm, CURSORA));
1415         /* HPLL off in SR has some issues on G4x... disable it */
1416         I915_WRITE(DSPFW3,
1417                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1418                    FW_WM(cursor_sr, CURSOR_SR));
1419
1420         if (cxsr_enabled)
1421                 intel_set_memory_cxsr(dev_priv, true);
1422 }
1423
1424 static void i965_update_wm(struct drm_crtc *unused_crtc)
1425 {
1426         struct drm_device *dev = unused_crtc->dev;
1427         struct drm_i915_private *dev_priv = dev->dev_private;
1428         struct drm_crtc *crtc;
1429         int srwm = 1;
1430         int cursor_sr = 16;
1431         bool cxsr_enabled;
1432
1433         /* Calc sr entries for one plane configs */
1434         crtc = single_enabled_crtc(dev);
1435         if (crtc) {
1436                 /* self-refresh has much higher latency */
1437                 static const int sr_latency_ns = 12000;
1438                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1439                 int clock = adjusted_mode->crtc_clock;
1440                 int htotal = adjusted_mode->crtc_htotal;
1441                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1442                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1443                 unsigned long line_time_us;
1444                 int entries;
1445
1446                 line_time_us = max(htotal * 1000 / clock, 1);
1447
1448                 /* Use ns/us then divide to preserve precision */
1449                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450                         pixel_size * hdisplay;
1451                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1452                 srwm = I965_FIFO_SIZE - entries;
1453                 if (srwm < 0)
1454                         srwm = 1;
1455                 srwm &= 0x1ff;
1456                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1457                               entries, srwm);
1458
1459                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1460                         pixel_size * crtc->cursor->state->crtc_w;
1461                 entries = DIV_ROUND_UP(entries,
1462                                           i965_cursor_wm_info.cacheline_size);
1463                 cursor_sr = i965_cursor_wm_info.fifo_size -
1464                         (entries + i965_cursor_wm_info.guard_size);
1465
1466                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1467                         cursor_sr = i965_cursor_wm_info.max_wm;
1468
1469                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470                               "cursor %d\n", srwm, cursor_sr);
1471
1472                 cxsr_enabled = true;
1473         } else {
1474                 cxsr_enabled = false;
1475                 /* Turn off self refresh if both pipes are enabled */
1476                 intel_set_memory_cxsr(dev_priv, false);
1477         }
1478
1479         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1480                       srwm);
1481
1482         /* 965 has limitations... */
1483         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1484                    FW_WM(8, CURSORB) |
1485                    FW_WM(8, PLANEB) |
1486                    FW_WM(8, PLANEA));
1487         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1488                    FW_WM(8, PLANEC_OLD));
1489         /* update cursor SR watermark */
1490         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1491
1492         if (cxsr_enabled)
1493                 intel_set_memory_cxsr(dev_priv, true);
1494 }
1495
1496 #undef FW_WM
1497
1498 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1499 {
1500         struct drm_device *dev = unused_crtc->dev;
1501         struct drm_i915_private *dev_priv = dev->dev_private;
1502         const struct intel_watermark_params *wm_info;
1503         uint32_t fwater_lo;
1504         uint32_t fwater_hi;
1505         int cwm, srwm = 1;
1506         int fifo_size;
1507         int planea_wm, planeb_wm;
1508         struct drm_crtc *crtc, *enabled = NULL;
1509
1510         if (IS_I945GM(dev))
1511                 wm_info = &i945_wm_info;
1512         else if (!IS_GEN2(dev))
1513                 wm_info = &i915_wm_info;
1514         else
1515                 wm_info = &i830_a_wm_info;
1516
1517         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1518         crtc = intel_get_crtc_for_plane(dev, 0);
1519         if (intel_crtc_active(crtc)) {
1520                 const struct drm_display_mode *adjusted_mode;
1521                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1522                 if (IS_GEN2(dev))
1523                         cpp = 4;
1524
1525                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1526                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1527                                                wm_info, fifo_size, cpp,
1528                                                pessimal_latency_ns);
1529                 enabled = crtc;
1530         } else {
1531                 planea_wm = fifo_size - wm_info->guard_size;
1532                 if (planea_wm > (long)wm_info->max_wm)
1533                         planea_wm = wm_info->max_wm;
1534         }
1535
1536         if (IS_GEN2(dev))
1537                 wm_info = &i830_bc_wm_info;
1538
1539         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1540         crtc = intel_get_crtc_for_plane(dev, 1);
1541         if (intel_crtc_active(crtc)) {
1542                 const struct drm_display_mode *adjusted_mode;
1543                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1544                 if (IS_GEN2(dev))
1545                         cpp = 4;
1546
1547                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1548                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1549                                                wm_info, fifo_size, cpp,
1550                                                pessimal_latency_ns);
1551                 if (enabled == NULL)
1552                         enabled = crtc;
1553                 else
1554                         enabled = NULL;
1555         } else {
1556                 planeb_wm = fifo_size - wm_info->guard_size;
1557                 if (planeb_wm > (long)wm_info->max_wm)
1558                         planeb_wm = wm_info->max_wm;
1559         }
1560
1561         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1562
1563         if (IS_I915GM(dev) && enabled) {
1564                 struct drm_i915_gem_object *obj;
1565
1566                 obj = intel_fb_obj(enabled->primary->state->fb);
1567
1568                 /* self-refresh seems busted with untiled */
1569                 if (obj->tiling_mode == I915_TILING_NONE)
1570                         enabled = NULL;
1571         }
1572
1573         /*
1574          * Overlay gets an aggressive default since video jitter is bad.
1575          */
1576         cwm = 2;
1577
1578         /* Play safe and disable self-refresh before adjusting watermarks. */
1579         intel_set_memory_cxsr(dev_priv, false);
1580
1581         /* Calc sr entries for one plane configs */
1582         if (HAS_FW_BLC(dev) && enabled) {
1583                 /* self-refresh has much higher latency */
1584                 static const int sr_latency_ns = 6000;
1585                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1586                 int clock = adjusted_mode->crtc_clock;
1587                 int htotal = adjusted_mode->crtc_htotal;
1588                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1589                 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1590                 unsigned long line_time_us;
1591                 int entries;
1592
1593                 line_time_us = max(htotal * 1000 / clock, 1);
1594
1595                 /* Use ns/us then divide to preserve precision */
1596                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1597                         pixel_size * hdisplay;
1598                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1599                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1600                 srwm = wm_info->fifo_size - entries;
1601                 if (srwm < 0)
1602                         srwm = 1;
1603
1604                 if (IS_I945G(dev) || IS_I945GM(dev))
1605                         I915_WRITE(FW_BLC_SELF,
1606                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1607                 else if (IS_I915GM(dev))
1608                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1609         }
1610
1611         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1612                       planea_wm, planeb_wm, cwm, srwm);
1613
1614         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1615         fwater_hi = (cwm & 0x1f);
1616
1617         /* Set request length to 8 cachelines per fetch */
1618         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1619         fwater_hi = fwater_hi | (1 << 8);
1620
1621         I915_WRITE(FW_BLC, fwater_lo);
1622         I915_WRITE(FW_BLC2, fwater_hi);
1623
1624         if (enabled)
1625                 intel_set_memory_cxsr(dev_priv, true);
1626 }
1627
1628 static void i845_update_wm(struct drm_crtc *unused_crtc)
1629 {
1630         struct drm_device *dev = unused_crtc->dev;
1631         struct drm_i915_private *dev_priv = dev->dev_private;
1632         struct drm_crtc *crtc;
1633         const struct drm_display_mode *adjusted_mode;
1634         uint32_t fwater_lo;
1635         int planea_wm;
1636
1637         crtc = single_enabled_crtc(dev);
1638         if (crtc == NULL)
1639                 return;
1640
1641         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1642         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1643                                        &i845_wm_info,
1644                                        dev_priv->display.get_fifo_size(dev, 0),
1645                                        4, pessimal_latency_ns);
1646         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1647         fwater_lo |= (3<<8) | planea_wm;
1648
1649         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1650
1651         I915_WRITE(FW_BLC, fwater_lo);
1652 }
1653
1654 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1655 {
1656         uint32_t pixel_rate;
1657
1658         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1659
1660         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661          * adjust the pixel_rate here. */
1662
1663         if (pipe_config->pch_pfit.enabled) {
1664                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1665                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1666
1667                 pipe_w = pipe_config->pipe_src_w;
1668                 pipe_h = pipe_config->pipe_src_h;
1669
1670                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1671                 pfit_h = pfit_size & 0xFFFF;
1672                 if (pipe_w < pfit_w)
1673                         pipe_w = pfit_w;
1674                 if (pipe_h < pfit_h)
1675                         pipe_h = pfit_h;
1676
1677                 if (WARN_ON(!pfit_w || !pfit_h))
1678                         return pixel_rate;
1679
1680                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1681                                      pfit_w * pfit_h);
1682         }
1683
1684         return pixel_rate;
1685 }
1686
1687 /* latency must be in 0.1us units. */
1688 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1689                                uint32_t latency)
1690 {
1691         uint64_t ret;
1692
1693         if (WARN(latency == 0, "Latency value missing\n"))
1694                 return UINT_MAX;
1695
1696         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1697         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1698
1699         return ret;
1700 }
1701
1702 /* latency must be in 0.1us units. */
1703 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1704                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1705                                uint32_t latency)
1706 {
1707         uint32_t ret;
1708
1709         if (WARN(latency == 0, "Latency value missing\n"))
1710                 return UINT_MAX;
1711         if (WARN_ON(!pipe_htotal))
1712                 return UINT_MAX;
1713
1714         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1715         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1716         ret = DIV_ROUND_UP(ret, 64) + 2;
1717         return ret;
1718 }
1719
1720 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1721                            uint8_t bytes_per_pixel)
1722 {
1723         /*
1724          * Neither of these should be possible since this function shouldn't be
1725          * called if the CRTC is off or the plane is invisible.  But let's be
1726          * extra paranoid to avoid a potential divide-by-zero if we screw up
1727          * elsewhere in the driver.
1728          */
1729         if (WARN_ON(!bytes_per_pixel))
1730                 return 0;
1731         if (WARN_ON(!horiz_pixels))
1732                 return 0;
1733
1734         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1735 }
1736
1737 struct ilk_wm_maximums {
1738         uint16_t pri;
1739         uint16_t spr;
1740         uint16_t cur;
1741         uint16_t fbc;
1742 };
1743
1744 /*
1745  * For both WM_PIPE and WM_LP.
1746  * mem_value must be in 0.1us units.
1747  */
1748 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1749                                    const struct intel_plane_state *pstate,
1750                                    uint32_t mem_value,
1751                                    bool is_lp)
1752 {
1753         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1754         uint32_t method1, method2;
1755
1756         if (!cstate->base.active || !pstate->visible)
1757                 return 0;
1758
1759         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1760
1761         if (!is_lp)
1762                 return method1;
1763
1764         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1765                                  cstate->base.adjusted_mode.crtc_htotal,
1766                                  drm_rect_width(&pstate->dst),
1767                                  bpp,
1768                                  mem_value);
1769
1770         return min(method1, method2);
1771 }
1772
1773 /*
1774  * For both WM_PIPE and WM_LP.
1775  * mem_value must be in 0.1us units.
1776  */
1777 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1778                                    const struct intel_plane_state *pstate,
1779                                    uint32_t mem_value)
1780 {
1781         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1782         uint32_t method1, method2;
1783
1784         if (!cstate->base.active || !pstate->visible)
1785                 return 0;
1786
1787         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1788         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1789                                  cstate->base.adjusted_mode.crtc_htotal,
1790                                  drm_rect_width(&pstate->dst),
1791                                  bpp,
1792                                  mem_value);
1793         return min(method1, method2);
1794 }
1795
1796 /*
1797  * For both WM_PIPE and WM_LP.
1798  * mem_value must be in 0.1us units.
1799  */
1800 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1801                                    const struct intel_plane_state *pstate,
1802                                    uint32_t mem_value)
1803 {
1804         /*
1805          * We treat the cursor plane as always-on for the purposes of watermark
1806          * calculation.  Until we have two-stage watermark programming merged,
1807          * this is necessary to avoid flickering.
1808          */
1809         int cpp = 4;
1810         int width = pstate->visible ? pstate->base.crtc_w : 64;
1811
1812         if (!cstate->base.active)
1813                 return 0;
1814
1815         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1816                               cstate->base.adjusted_mode.crtc_htotal,
1817                               width, cpp, mem_value);
1818 }
1819
1820 /* Only for WM_LP. */
1821 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1822                                    const struct intel_plane_state *pstate,
1823                                    uint32_t pri_val)
1824 {
1825         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1826
1827         if (!cstate->base.active || !pstate->visible)
1828                 return 0;
1829
1830         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
1831 }
1832
1833 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1834 {
1835         if (INTEL_INFO(dev)->gen >= 8)
1836                 return 3072;
1837         else if (INTEL_INFO(dev)->gen >= 7)
1838                 return 768;
1839         else
1840                 return 512;
1841 }
1842
1843 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1844                                          int level, bool is_sprite)
1845 {
1846         if (INTEL_INFO(dev)->gen >= 8)
1847                 /* BDW primary/sprite plane watermarks */
1848                 return level == 0 ? 255 : 2047;
1849         else if (INTEL_INFO(dev)->gen >= 7)
1850                 /* IVB/HSW primary/sprite plane watermarks */
1851                 return level == 0 ? 127 : 1023;
1852         else if (!is_sprite)
1853                 /* ILK/SNB primary plane watermarks */
1854                 return level == 0 ? 127 : 511;
1855         else
1856                 /* ILK/SNB sprite plane watermarks */
1857                 return level == 0 ? 63 : 255;
1858 }
1859
1860 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1861                                           int level)
1862 {
1863         if (INTEL_INFO(dev)->gen >= 7)
1864                 return level == 0 ? 63 : 255;
1865         else
1866                 return level == 0 ? 31 : 63;
1867 }
1868
1869 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1870 {
1871         if (INTEL_INFO(dev)->gen >= 8)
1872                 return 31;
1873         else
1874                 return 15;
1875 }
1876
1877 /* Calculate the maximum primary/sprite plane watermark */
1878 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1879                                      int level,
1880                                      const struct intel_wm_config *config,
1881                                      enum intel_ddb_partitioning ddb_partitioning,
1882                                      bool is_sprite)
1883 {
1884         unsigned int fifo_size = ilk_display_fifo_size(dev);
1885
1886         /* if sprites aren't enabled, sprites get nothing */
1887         if (is_sprite && !config->sprites_enabled)
1888                 return 0;
1889
1890         /* HSW allows LP1+ watermarks even with multiple pipes */
1891         if (level == 0 || config->num_pipes_active > 1) {
1892                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1893
1894                 /*
1895                  * For some reason the non self refresh
1896                  * FIFO size is only half of the self
1897                  * refresh FIFO size on ILK/SNB.
1898                  */
1899                 if (INTEL_INFO(dev)->gen <= 6)
1900                         fifo_size /= 2;
1901         }
1902
1903         if (config->sprites_enabled) {
1904                 /* level 0 is always calculated with 1:1 split */
1905                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1906                         if (is_sprite)
1907                                 fifo_size *= 5;
1908                         fifo_size /= 6;
1909                 } else {
1910                         fifo_size /= 2;
1911                 }
1912         }
1913
1914         /* clamp to max that the registers can hold */
1915         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1916 }
1917
1918 /* Calculate the maximum cursor plane watermark */
1919 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1920                                       int level,
1921                                       const struct intel_wm_config *config)
1922 {
1923         /* HSW LP1+ watermarks w/ multiple pipes */
1924         if (level > 0 && config->num_pipes_active > 1)
1925                 return 64;
1926
1927         /* otherwise just report max that registers can hold */
1928         return ilk_cursor_wm_reg_max(dev, level);
1929 }
1930
1931 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1932                                     int level,
1933                                     const struct intel_wm_config *config,
1934                                     enum intel_ddb_partitioning ddb_partitioning,
1935                                     struct ilk_wm_maximums *max)
1936 {
1937         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1938         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1939         max->cur = ilk_cursor_wm_max(dev, level, config);
1940         max->fbc = ilk_fbc_wm_reg_max(dev);
1941 }
1942
1943 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1944                                         int level,
1945                                         struct ilk_wm_maximums *max)
1946 {
1947         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1948         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1949         max->cur = ilk_cursor_wm_reg_max(dev, level);
1950         max->fbc = ilk_fbc_wm_reg_max(dev);
1951 }
1952
1953 static bool ilk_validate_wm_level(int level,
1954                                   const struct ilk_wm_maximums *max,
1955                                   struct intel_wm_level *result)
1956 {
1957         bool ret;
1958
1959         /* already determined to be invalid? */
1960         if (!result->enable)
1961                 return false;
1962
1963         result->enable = result->pri_val <= max->pri &&
1964                          result->spr_val <= max->spr &&
1965                          result->cur_val <= max->cur;
1966
1967         ret = result->enable;
1968
1969         /*
1970          * HACK until we can pre-compute everything,
1971          * and thus fail gracefully if LP0 watermarks
1972          * are exceeded...
1973          */
1974         if (level == 0 && !result->enable) {
1975                 if (result->pri_val > max->pri)
1976                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1977                                       level, result->pri_val, max->pri);
1978                 if (result->spr_val > max->spr)
1979                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1980                                       level, result->spr_val, max->spr);
1981                 if (result->cur_val > max->cur)
1982                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1983                                       level, result->cur_val, max->cur);
1984
1985                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1986                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1987                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1988                 result->enable = true;
1989         }
1990
1991         return ret;
1992 }
1993
1994 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1995                                  const struct intel_crtc *intel_crtc,
1996                                  int level,
1997                                  struct intel_crtc_state *cstate,
1998                                  struct intel_plane_state *pristate,
1999                                  struct intel_plane_state *sprstate,
2000                                  struct intel_plane_state *curstate,
2001                                  struct intel_wm_level *result)
2002 {
2003         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2004         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2005         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2006
2007         /* WM1+ latency values stored in 0.5us units */
2008         if (level > 0) {
2009                 pri_latency *= 5;
2010                 spr_latency *= 5;
2011                 cur_latency *= 5;
2012         }
2013
2014         result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2015                                              pri_latency, level);
2016         result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2017         result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2018         result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2019         result->enable = true;
2020 }
2021
2022 static uint32_t
2023 hsw_compute_linetime_wm(struct drm_device *dev,
2024                         struct intel_crtc_state *cstate)
2025 {
2026         struct drm_i915_private *dev_priv = dev->dev_private;
2027         const struct drm_display_mode *adjusted_mode =
2028                 &cstate->base.adjusted_mode;
2029         u32 linetime, ips_linetime;
2030
2031         if (!cstate->base.active)
2032                 return 0;
2033         if (WARN_ON(adjusted_mode->crtc_clock == 0))
2034                 return 0;
2035         if (WARN_ON(dev_priv->cdclk_freq == 0))
2036                 return 0;
2037
2038         /* The WM are computed with base on how long it takes to fill a single
2039          * row at the given clock rate, multiplied by 8.
2040          * */
2041         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2042                                      adjusted_mode->crtc_clock);
2043         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2044                                          dev_priv->cdclk_freq);
2045
2046         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2047                PIPE_WM_LINETIME_TIME(linetime);
2048 }
2049
2050 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2051 {
2052         struct drm_i915_private *dev_priv = dev->dev_private;
2053
2054         if (IS_GEN9(dev)) {
2055                 uint32_t val;
2056                 int ret, i;
2057                 int level, max_level = ilk_wm_max_level(dev);
2058
2059                 /* read the first set of memory latencies[0:3] */
2060                 val = 0; /* data0 to be programmed to 0 for first set */
2061                 mutex_lock(&dev_priv->rps.hw_lock);
2062                 ret = sandybridge_pcode_read(dev_priv,
2063                                              GEN9_PCODE_READ_MEM_LATENCY,
2064                                              &val);
2065                 mutex_unlock(&dev_priv->rps.hw_lock);
2066
2067                 if (ret) {
2068                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2069                         return;
2070                 }
2071
2072                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2073                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2074                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2075                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2076                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2077                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2078                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2079
2080                 /* read the second set of memory latencies[4:7] */
2081                 val = 1; /* data0 to be programmed to 1 for second set */
2082                 mutex_lock(&dev_priv->rps.hw_lock);
2083                 ret = sandybridge_pcode_read(dev_priv,
2084                                              GEN9_PCODE_READ_MEM_LATENCY,
2085                                              &val);
2086                 mutex_unlock(&dev_priv->rps.hw_lock);
2087                 if (ret) {
2088                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2089                         return;
2090                 }
2091
2092                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2093                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2094                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2095                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2096                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2097                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2098                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2099
2100                 /*
2101                  * WaWmMemoryReadLatency:skl
2102                  *
2103                  * punit doesn't take into account the read latency so we need
2104                  * to add 2us to the various latency levels we retrieve from
2105                  * the punit.
2106                  *   - W0 is a bit special in that it's the only level that
2107                  *   can't be disabled if we want to have display working, so
2108                  *   we always add 2us there.
2109                  *   - For levels >=1, punit returns 0us latency when they are
2110                  *   disabled, so we respect that and don't add 2us then
2111                  *
2112                  * Additionally, if a level n (n > 1) has a 0us latency, all
2113                  * levels m (m >= n) need to be disabled. We make sure to
2114                  * sanitize the values out of the punit to satisfy this
2115                  * requirement.
2116                  */
2117                 wm[0] += 2;
2118                 for (level = 1; level <= max_level; level++)
2119                         if (wm[level] != 0)
2120                                 wm[level] += 2;
2121                         else {
2122                                 for (i = level + 1; i <= max_level; i++)
2123                                         wm[i] = 0;
2124
2125                                 break;
2126                         }
2127         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2128                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2129
2130                 wm[0] = (sskpd >> 56) & 0xFF;
2131                 if (wm[0] == 0)
2132                         wm[0] = sskpd & 0xF;
2133                 wm[1] = (sskpd >> 4) & 0xFF;
2134                 wm[2] = (sskpd >> 12) & 0xFF;
2135                 wm[3] = (sskpd >> 20) & 0x1FF;
2136                 wm[4] = (sskpd >> 32) & 0x1FF;
2137         } else if (INTEL_INFO(dev)->gen >= 6) {
2138                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2139
2140                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2141                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2142                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2143                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2144         } else if (INTEL_INFO(dev)->gen >= 5) {
2145                 uint32_t mltr = I915_READ(MLTR_ILK);
2146
2147                 /* ILK primary LP0 latency is 700 ns */
2148                 wm[0] = 7;
2149                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2150                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2151         }
2152 }
2153
2154 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2155 {
2156         /* ILK sprite LP0 latency is 1300 ns */
2157         if (INTEL_INFO(dev)->gen == 5)
2158                 wm[0] = 13;
2159 }
2160
2161 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2162 {
2163         /* ILK cursor LP0 latency is 1300 ns */
2164         if (INTEL_INFO(dev)->gen == 5)
2165                 wm[0] = 13;
2166
2167         /* WaDoubleCursorLP3Latency:ivb */
2168         if (IS_IVYBRIDGE(dev))
2169                 wm[3] *= 2;
2170 }
2171
2172 int ilk_wm_max_level(const struct drm_device *dev)
2173 {
2174         /* how many WM levels are we expecting */
2175         if (INTEL_INFO(dev)->gen >= 9)
2176                 return 7;
2177         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2178                 return 4;
2179         else if (INTEL_INFO(dev)->gen >= 6)
2180                 return 3;
2181         else
2182                 return 2;
2183 }
2184
2185 static void intel_print_wm_latency(struct drm_device *dev,
2186                                    const char *name,
2187                                    const uint16_t wm[8])
2188 {
2189         int level, max_level = ilk_wm_max_level(dev);
2190
2191         for (level = 0; level <= max_level; level++) {
2192                 unsigned int latency = wm[level];
2193
2194                 if (latency == 0) {
2195                         DRM_ERROR("%s WM%d latency not provided\n",
2196                                   name, level);
2197                         continue;
2198                 }
2199
2200                 /*
2201                  * - latencies are in us on gen9.
2202                  * - before then, WM1+ latency values are in 0.5us units
2203                  */
2204                 if (IS_GEN9(dev))
2205                         latency *= 10;
2206                 else if (level > 0)
2207                         latency *= 5;
2208
2209                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2210                               name, level, wm[level],
2211                               latency / 10, latency % 10);
2212         }
2213 }
2214
2215 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2216                                     uint16_t wm[5], uint16_t min)
2217 {
2218         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2219
2220         if (wm[0] >= min)
2221                 return false;
2222
2223         wm[0] = max(wm[0], min);
2224         for (level = 1; level <= max_level; level++)
2225                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2226
2227         return true;
2228 }
2229
2230 static void snb_wm_latency_quirk(struct drm_device *dev)
2231 {
2232         struct drm_i915_private *dev_priv = dev->dev_private;
2233         bool changed;
2234
2235         /*
2236          * The BIOS provided WM memory latency values are often
2237          * inadequate for high resolution displays. Adjust them.
2238          */
2239         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2240                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2241                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2242
2243         if (!changed)
2244                 return;
2245
2246         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2247         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2248         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2249         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2250 }
2251
2252 static void ilk_setup_wm_latency(struct drm_device *dev)
2253 {
2254         struct drm_i915_private *dev_priv = dev->dev_private;
2255
2256         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2257
2258         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2259                sizeof(dev_priv->wm.pri_latency));
2260         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2261                sizeof(dev_priv->wm.pri_latency));
2262
2263         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2264         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2265
2266         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2267         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2268         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2269
2270         if (IS_GEN6(dev))
2271                 snb_wm_latency_quirk(dev);
2272 }
2273
2274 static void skl_setup_wm_latency(struct drm_device *dev)
2275 {
2276         struct drm_i915_private *dev_priv = dev->dev_private;
2277
2278         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2279         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2280 }
2281
2282 /* Compute new watermarks for the pipe */
2283 static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2284                                struct drm_atomic_state *state)
2285 {
2286         struct intel_pipe_wm *pipe_wm;
2287         struct drm_device *dev = intel_crtc->base.dev;
2288         const struct drm_i915_private *dev_priv = dev->dev_private;
2289         struct intel_crtc_state *cstate = NULL;
2290         struct intel_plane *intel_plane;
2291         struct drm_plane_state *ps;
2292         struct intel_plane_state *pristate = NULL;
2293         struct intel_plane_state *sprstate = NULL;
2294         struct intel_plane_state *curstate = NULL;
2295         int level, max_level = ilk_wm_max_level(dev);
2296         /* LP0 watermark maximums depend on this pipe alone */
2297         struct intel_wm_config config = {
2298                 .num_pipes_active = 1,
2299         };
2300         struct ilk_wm_maximums max;
2301
2302         cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2303         if (IS_ERR(cstate))
2304                 return PTR_ERR(cstate);
2305
2306         pipe_wm = &cstate->wm.optimal.ilk;
2307         memset(pipe_wm, 0, sizeof(*pipe_wm));
2308
2309         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2310                 ps = drm_atomic_get_plane_state(state,
2311                                                 &intel_plane->base);
2312                 if (IS_ERR(ps))
2313                         return PTR_ERR(ps);
2314
2315                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2316                         pristate = to_intel_plane_state(ps);
2317                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2318                         sprstate = to_intel_plane_state(ps);
2319                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2320                         curstate = to_intel_plane_state(ps);
2321         }
2322
2323         config.sprites_enabled = sprstate->visible;
2324         config.sprites_scaled = sprstate->visible &&
2325                 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2326                 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2327
2328         pipe_wm->pipe_enabled = cstate->base.active;
2329         pipe_wm->sprites_enabled = config.sprites_enabled;
2330         pipe_wm->sprites_scaled = config.sprites_scaled;
2331
2332         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2333         if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2334                 max_level = 1;
2335
2336         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2337         if (config.sprites_scaled)
2338                 max_level = 0;
2339
2340         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2341                              pristate, sprstate, curstate, &pipe_wm->wm[0]);
2342
2343         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2344                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
2345
2346         /* LP0 watermarks always use 1/2 DDB partitioning */
2347         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2348
2349         /* At least LP0 must be valid */
2350         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2351                 return -EINVAL;
2352
2353         ilk_compute_wm_reg_maximums(dev, 1, &max);
2354
2355         for (level = 1; level <= max_level; level++) {
2356                 struct intel_wm_level wm = {};
2357
2358                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2359                                      pristate, sprstate, curstate, &wm);
2360
2361                 /*
2362                  * Disable any watermark level that exceeds the
2363                  * register maximums since such watermarks are
2364                  * always invalid.
2365                  */
2366                 if (!ilk_validate_wm_level(level, &max, &wm))
2367                         break;
2368
2369                 pipe_wm->wm[level] = wm;
2370         }
2371
2372         return 0;
2373 }
2374
2375 /*
2376  * Merge the watermarks from all active pipes for a specific level.
2377  */
2378 static void ilk_merge_wm_level(struct drm_device *dev,
2379                                int level,
2380                                struct intel_wm_level *ret_wm)
2381 {
2382         const struct intel_crtc *intel_crtc;
2383
2384         ret_wm->enable = true;
2385
2386         for_each_intel_crtc(dev, intel_crtc) {
2387                 const struct intel_crtc_state *cstate =
2388                         to_intel_crtc_state(intel_crtc->base.state);
2389                 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
2390                 const struct intel_wm_level *wm = &active->wm[level];
2391
2392                 if (!active->pipe_enabled)
2393                         continue;
2394
2395                 /*
2396                  * The watermark values may have been used in the past,
2397                  * so we must maintain them in the registers for some
2398                  * time even if the level is now disabled.
2399                  */
2400                 if (!wm->enable)
2401                         ret_wm->enable = false;
2402
2403                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2404                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2405                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2406                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2407         }
2408 }
2409
2410 /*
2411  * Merge all low power watermarks for all active pipes.
2412  */
2413 static void ilk_wm_merge(struct drm_device *dev,
2414                          const struct intel_wm_config *config,
2415                          const struct ilk_wm_maximums *max,
2416                          struct intel_pipe_wm *merged)
2417 {
2418         struct drm_i915_private *dev_priv = dev->dev_private;
2419         int level, max_level = ilk_wm_max_level(dev);
2420         int last_enabled_level = max_level;
2421
2422         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2423         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2424             config->num_pipes_active > 1)
2425                 return;
2426
2427         /* ILK: FBC WM must be disabled always */
2428         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2429
2430         /* merge each WM1+ level */
2431         for (level = 1; level <= max_level; level++) {
2432                 struct intel_wm_level *wm = &merged->wm[level];
2433
2434                 ilk_merge_wm_level(dev, level, wm);
2435
2436                 if (level > last_enabled_level)
2437                         wm->enable = false;
2438                 else if (!ilk_validate_wm_level(level, max, wm))
2439                         /* make sure all following levels get disabled */
2440                         last_enabled_level = level - 1;
2441
2442                 /*
2443                  * The spec says it is preferred to disable
2444                  * FBC WMs instead of disabling a WM level.
2445                  */
2446                 if (wm->fbc_val > max->fbc) {
2447                         if (wm->enable)
2448                                 merged->fbc_wm_enabled = false;
2449                         wm->fbc_val = 0;
2450                 }
2451         }
2452
2453         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2454         /*
2455          * FIXME this is racy. FBC might get enabled later.
2456          * What we should check here is whether FBC can be
2457          * enabled sometime later.
2458          */
2459         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2460             intel_fbc_is_active(dev_priv)) {
2461                 for (level = 2; level <= max_level; level++) {
2462                         struct intel_wm_level *wm = &merged->wm[level];
2463
2464                         wm->enable = false;
2465                 }
2466         }
2467 }
2468
2469 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2470 {
2471         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2472         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2473 }
2474
2475 /* The value we need to program into the WM_LPx latency field */
2476 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2477 {
2478         struct drm_i915_private *dev_priv = dev->dev_private;
2479
2480         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2481                 return 2 * level;
2482         else
2483                 return dev_priv->wm.pri_latency[level];
2484 }
2485
2486 static void ilk_compute_wm_results(struct drm_device *dev,
2487                                    const struct intel_pipe_wm *merged,
2488                                    enum intel_ddb_partitioning partitioning,
2489                                    struct ilk_wm_values *results)
2490 {
2491         struct intel_crtc *intel_crtc;
2492         int level, wm_lp;
2493
2494         results->enable_fbc_wm = merged->fbc_wm_enabled;
2495         results->partitioning = partitioning;
2496
2497         /* LP1+ register values */
2498         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2499                 const struct intel_wm_level *r;
2500
2501                 level = ilk_wm_lp_to_level(wm_lp, merged);
2502
2503                 r = &merged->wm[level];
2504
2505                 /*
2506                  * Maintain the watermark values even if the level is
2507                  * disabled. Doing otherwise could cause underruns.
2508                  */
2509                 results->wm_lp[wm_lp - 1] =
2510                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2511                         (r->pri_val << WM1_LP_SR_SHIFT) |
2512                         r->cur_val;
2513
2514                 if (r->enable)
2515                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2516
2517                 if (INTEL_INFO(dev)->gen >= 8)
2518                         results->wm_lp[wm_lp - 1] |=
2519                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2520                 else
2521                         results->wm_lp[wm_lp - 1] |=
2522                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2523
2524                 /*
2525                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2526                  * level is disabled. Doing otherwise could cause underruns.
2527                  */
2528                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2529                         WARN_ON(wm_lp != 1);
2530                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2531                 } else
2532                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2533         }
2534
2535         /* LP0 register values */
2536         for_each_intel_crtc(dev, intel_crtc) {
2537                 const struct intel_crtc_state *cstate =
2538                         to_intel_crtc_state(intel_crtc->base.state);
2539                 enum pipe pipe = intel_crtc->pipe;
2540                 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
2541
2542                 if (WARN_ON(!r->enable))
2543                         continue;
2544
2545                 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
2546
2547                 results->wm_pipe[pipe] =
2548                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2549                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2550                         r->cur_val;
2551         }
2552 }
2553
2554 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2555  * case both are at the same level. Prefer r1 in case they're the same. */
2556 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2557                                                   struct intel_pipe_wm *r1,
2558                                                   struct intel_pipe_wm *r2)
2559 {
2560         int level, max_level = ilk_wm_max_level(dev);
2561         int level1 = 0, level2 = 0;
2562
2563         for (level = 1; level <= max_level; level++) {
2564                 if (r1->wm[level].enable)
2565                         level1 = level;
2566                 if (r2->wm[level].enable)
2567                         level2 = level;
2568         }
2569
2570         if (level1 == level2) {
2571                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2572                         return r2;
2573                 else
2574                         return r1;
2575         } else if (level1 > level2) {
2576                 return r1;
2577         } else {
2578                 return r2;
2579         }
2580 }
2581
2582 /* dirty bits used to track which watermarks need changes */
2583 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2584 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2585 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2586 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2587 #define WM_DIRTY_FBC (1 << 24)
2588 #define WM_DIRTY_DDB (1 << 25)
2589
2590 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2591                                          const struct ilk_wm_values *old,
2592                                          const struct ilk_wm_values *new)
2593 {
2594         unsigned int dirty = 0;
2595         enum pipe pipe;
2596         int wm_lp;
2597
2598         for_each_pipe(dev_priv, pipe) {
2599                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2600                         dirty |= WM_DIRTY_LINETIME(pipe);
2601                         /* Must disable LP1+ watermarks too */
2602                         dirty |= WM_DIRTY_LP_ALL;
2603                 }
2604
2605                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2606                         dirty |= WM_DIRTY_PIPE(pipe);
2607                         /* Must disable LP1+ watermarks too */
2608                         dirty |= WM_DIRTY_LP_ALL;
2609                 }
2610         }
2611
2612         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2613                 dirty |= WM_DIRTY_FBC;
2614                 /* Must disable LP1+ watermarks too */
2615                 dirty |= WM_DIRTY_LP_ALL;
2616         }
2617
2618         if (old->partitioning != new->partitioning) {
2619                 dirty |= WM_DIRTY_DDB;
2620                 /* Must disable LP1+ watermarks too */
2621                 dirty |= WM_DIRTY_LP_ALL;
2622         }
2623
2624         /* LP1+ watermarks already deemed dirty, no need to continue */
2625         if (dirty & WM_DIRTY_LP_ALL)
2626                 return dirty;
2627
2628         /* Find the lowest numbered LP1+ watermark in need of an update... */
2629         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2630                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2631                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2632                         break;
2633         }
2634
2635         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2636         for (; wm_lp <= 3; wm_lp++)
2637                 dirty |= WM_DIRTY_LP(wm_lp);
2638
2639         return dirty;
2640 }
2641
2642 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2643                                unsigned int dirty)
2644 {
2645         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2646         bool changed = false;
2647
2648         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2649                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2650                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2651                 changed = true;
2652         }
2653         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2654                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2655                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2656                 changed = true;
2657         }
2658         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2659                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2660                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2661                 changed = true;
2662         }
2663
2664         /*
2665          * Don't touch WM1S_LP_EN here.
2666          * Doing so could cause underruns.
2667          */
2668
2669         return changed;
2670 }
2671
2672 /*
2673  * The spec says we shouldn't write when we don't need, because every write
2674  * causes WMs to be re-evaluated, expending some power.
2675  */
2676 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2677                                 struct ilk_wm_values *results)
2678 {
2679         struct drm_device *dev = dev_priv->dev;
2680         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2681         unsigned int dirty;
2682         uint32_t val;
2683
2684         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2685         if (!dirty)
2686                 return;
2687
2688         _ilk_disable_lp_wm(dev_priv, dirty);
2689
2690         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2691                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2692         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2693                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2694         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2695                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2696
2697         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2698                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2699         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2700                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2701         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2702                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2703
2704         if (dirty & WM_DIRTY_DDB) {
2705                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2706                         val = I915_READ(WM_MISC);
2707                         if (results->partitioning == INTEL_DDB_PART_1_2)
2708                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2709                         else
2710                                 val |= WM_MISC_DATA_PARTITION_5_6;
2711                         I915_WRITE(WM_MISC, val);
2712                 } else {
2713                         val = I915_READ(DISP_ARB_CTL2);
2714                         if (results->partitioning == INTEL_DDB_PART_1_2)
2715                                 val &= ~DISP_DATA_PARTITION_5_6;
2716                         else
2717                                 val |= DISP_DATA_PARTITION_5_6;
2718                         I915_WRITE(DISP_ARB_CTL2, val);
2719                 }
2720         }
2721
2722         if (dirty & WM_DIRTY_FBC) {
2723                 val = I915_READ(DISP_ARB_CTL);
2724                 if (results->enable_fbc_wm)
2725                         val &= ~DISP_FBC_WM_DIS;
2726                 else
2727                         val |= DISP_FBC_WM_DIS;
2728                 I915_WRITE(DISP_ARB_CTL, val);
2729         }
2730
2731         if (dirty & WM_DIRTY_LP(1) &&
2732             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2733                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2734
2735         if (INTEL_INFO(dev)->gen >= 7) {
2736                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2737                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2738                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2739                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2740         }
2741
2742         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2743                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2744         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2745                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2746         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2747                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2748
2749         dev_priv->wm.hw = *results;
2750 }
2751
2752 static bool ilk_disable_lp_wm(struct drm_device *dev)
2753 {
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755
2756         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2757 }
2758
2759 /*
2760  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2761  * different active planes.
2762  */
2763
2764 #define SKL_DDB_SIZE            896     /* in blocks */
2765 #define BXT_DDB_SIZE            512
2766
2767 /*
2768  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2769  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2770  * other universal planes are in indices 1..n.  Note that this may leave unused
2771  * indices between the top "sprite" plane and the cursor.
2772  */
2773 static int
2774 skl_wm_plane_id(const struct intel_plane *plane)
2775 {
2776         switch (plane->base.type) {
2777         case DRM_PLANE_TYPE_PRIMARY:
2778                 return 0;
2779         case DRM_PLANE_TYPE_CURSOR:
2780                 return PLANE_CURSOR;
2781         case DRM_PLANE_TYPE_OVERLAY:
2782                 return plane->plane + 1;
2783         default:
2784                 MISSING_CASE(plane->base.type);
2785                 return plane->plane;
2786         }
2787 }
2788
2789 static void
2790 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2791                                    const struct intel_crtc_state *cstate,
2792                                    const struct intel_wm_config *config,
2793                                    struct skl_ddb_entry *alloc /* out */)
2794 {
2795         struct drm_crtc *for_crtc = cstate->base.crtc;
2796         struct drm_crtc *crtc;
2797         unsigned int pipe_size, ddb_size;
2798         int nth_active_pipe;
2799
2800         if (!cstate->base.active) {
2801                 alloc->start = 0;
2802                 alloc->end = 0;
2803                 return;
2804         }
2805
2806         if (IS_BROXTON(dev))
2807                 ddb_size = BXT_DDB_SIZE;
2808         else
2809                 ddb_size = SKL_DDB_SIZE;
2810
2811         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2812
2813         nth_active_pipe = 0;
2814         for_each_crtc(dev, crtc) {
2815                 if (!to_intel_crtc(crtc)->active)
2816                         continue;
2817
2818                 if (crtc == for_crtc)
2819                         break;
2820
2821                 nth_active_pipe++;
2822         }
2823
2824         pipe_size = ddb_size / config->num_pipes_active;
2825         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2826         alloc->end = alloc->start + pipe_size;
2827 }
2828
2829 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2830 {
2831         if (config->num_pipes_active == 1)
2832                 return 32;
2833
2834         return 8;
2835 }
2836
2837 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2838 {
2839         entry->start = reg & 0x3ff;
2840         entry->end = (reg >> 16) & 0x3ff;
2841         if (entry->end)
2842                 entry->end += 1;
2843 }
2844
2845 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2846                           struct skl_ddb_allocation *ddb /* out */)
2847 {
2848         enum pipe pipe;
2849         int plane;
2850         u32 val;
2851
2852         memset(ddb, 0, sizeof(*ddb));
2853
2854         for_each_pipe(dev_priv, pipe) {
2855                 enum intel_display_power_domain power_domain;
2856
2857                 power_domain = POWER_DOMAIN_PIPE(pipe);
2858                 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
2859                         continue;
2860
2861                 for_each_plane(dev_priv, pipe, plane) {
2862                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2863                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2864                                                    val);
2865                 }
2866
2867                 val = I915_READ(CUR_BUF_CFG(pipe));
2868                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2869                                            val);
2870
2871                 intel_display_power_put(dev_priv, power_domain);
2872         }
2873 }
2874
2875 static unsigned int
2876 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2877                              const struct drm_plane_state *pstate,
2878                              int y)
2879 {
2880         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2881         struct drm_framebuffer *fb = pstate->fb;
2882
2883         /* for planar format */
2884         if (fb->pixel_format == DRM_FORMAT_NV12) {
2885                 if (y)  /* y-plane data rate */
2886                         return intel_crtc->config->pipe_src_w *
2887                                 intel_crtc->config->pipe_src_h *
2888                                 drm_format_plane_cpp(fb->pixel_format, 0);
2889                 else    /* uv-plane data rate */
2890                         return (intel_crtc->config->pipe_src_w/2) *
2891                                 (intel_crtc->config->pipe_src_h/2) *
2892                                 drm_format_plane_cpp(fb->pixel_format, 1);
2893         }
2894
2895         /* for packed formats */
2896         return intel_crtc->config->pipe_src_w *
2897                 intel_crtc->config->pipe_src_h *
2898                 drm_format_plane_cpp(fb->pixel_format, 0);
2899 }
2900
2901 /*
2902  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2903  * a 8192x4096@32bpp framebuffer:
2904  *   3 * 4096 * 8192  * 4 < 2^32
2905  */
2906 static unsigned int
2907 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2908 {
2909         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2910         struct drm_device *dev = intel_crtc->base.dev;
2911         const struct intel_plane *intel_plane;
2912         unsigned int total_data_rate = 0;
2913
2914         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2915                 const struct drm_plane_state *pstate = intel_plane->base.state;
2916
2917                 if (pstate->fb == NULL)
2918                         continue;
2919
2920                 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2921                         continue;
2922
2923                 /* packed/uv */
2924                 total_data_rate += skl_plane_relative_data_rate(cstate,
2925                                                                 pstate,
2926                                                                 0);
2927
2928                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2929                         /* y-plane */
2930                         total_data_rate += skl_plane_relative_data_rate(cstate,
2931                                                                         pstate,
2932                                                                         1);
2933         }
2934
2935         return total_data_rate;
2936 }
2937
2938 static void
2939 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
2940                       struct skl_ddb_allocation *ddb /* out */)
2941 {
2942         struct drm_crtc *crtc = cstate->base.crtc;
2943         struct drm_device *dev = crtc->dev;
2944         struct drm_i915_private *dev_priv = to_i915(dev);
2945         struct intel_wm_config *config = &dev_priv->wm.config;
2946         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2947         struct intel_plane *intel_plane;
2948         enum pipe pipe = intel_crtc->pipe;
2949         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2950         uint16_t alloc_size, start, cursor_blocks;
2951         uint16_t minimum[I915_MAX_PLANES];
2952         uint16_t y_minimum[I915_MAX_PLANES];
2953         unsigned int total_data_rate;
2954
2955         skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
2956         alloc_size = skl_ddb_entry_size(alloc);
2957         if (alloc_size == 0) {
2958                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2959                 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2960                        sizeof(ddb->plane[pipe][PLANE_CURSOR]));
2961                 return;
2962         }
2963
2964         cursor_blocks = skl_cursor_allocation(config);
2965         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2966         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
2967
2968         alloc_size -= cursor_blocks;
2969         alloc->end -= cursor_blocks;
2970
2971         /* 1. Allocate the mininum required blocks for each active plane */
2972         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2973                 struct drm_plane *plane = &intel_plane->base;
2974                 struct drm_framebuffer *fb = plane->state->fb;
2975                 int id = skl_wm_plane_id(intel_plane);
2976
2977                 if (fb == NULL)
2978                         continue;
2979                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
2980                         continue;
2981
2982                 minimum[id] = 8;
2983                 alloc_size -= minimum[id];
2984                 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2985                 alloc_size -= y_minimum[id];
2986         }
2987
2988         /*
2989          * 2. Distribute the remaining space in proportion to the amount of
2990          * data each plane needs to fetch from memory.
2991          *
2992          * FIXME: we may not allocate every single block here.
2993          */
2994         total_data_rate = skl_get_total_relative_data_rate(cstate);
2995
2996         start = alloc->start;
2997         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2998                 struct drm_plane *plane = &intel_plane->base;
2999                 struct drm_plane_state *pstate = intel_plane->base.state;
3000                 unsigned int data_rate, y_data_rate;
3001                 uint16_t plane_blocks, y_plane_blocks = 0;
3002                 int id = skl_wm_plane_id(intel_plane);
3003
3004                 if (pstate->fb == NULL)
3005                         continue;
3006                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
3007                         continue;
3008
3009                 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
3010
3011                 /*
3012                  * allocation for (packed formats) or (uv-plane part of planar format):
3013                  * promote the expression to 64 bits to avoid overflowing, the
3014                  * result is < available as data_rate / total_data_rate < 1
3015                  */
3016                 plane_blocks = minimum[id];
3017                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3018                                         total_data_rate);
3019
3020                 ddb->plane[pipe][id].start = start;
3021                 ddb->plane[pipe][id].end = start + plane_blocks;
3022
3023                 start += plane_blocks;
3024
3025                 /*
3026                  * allocation for y_plane part of planar format:
3027                  */
3028                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3029                         y_data_rate = skl_plane_relative_data_rate(cstate,
3030                                                                    pstate,
3031                                                                    1);
3032                         y_plane_blocks = y_minimum[id];
3033                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3034                                                 total_data_rate);
3035
3036                         ddb->y_plane[pipe][id].start = start;
3037                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3038
3039                         start += y_plane_blocks;
3040                 }
3041
3042         }
3043
3044 }
3045
3046 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3047 {
3048         /* TODO: Take into account the scalers once we support them */
3049         return config->base.adjusted_mode.crtc_clock;
3050 }
3051
3052 /*
3053  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3054  * for the read latency) and bytes_per_pixel should always be <= 8, so that
3055  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3056  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3057 */
3058 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3059                                uint32_t latency)
3060 {
3061         uint32_t wm_intermediate_val, ret;
3062
3063         if (latency == 0)
3064                 return UINT_MAX;
3065
3066         wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3067         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3068
3069         return ret;
3070 }
3071
3072 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3073                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3074                                uint64_t tiling, uint32_t latency)
3075 {
3076         uint32_t ret;
3077         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3078         uint32_t wm_intermediate_val;
3079
3080         if (latency == 0)
3081                 return UINT_MAX;
3082
3083         plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3084
3085         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3086             tiling == I915_FORMAT_MOD_Yf_TILED) {
3087                 plane_bytes_per_line *= 4;
3088                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3089                 plane_blocks_per_line /= 4;
3090         } else {
3091                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3092         }
3093
3094         wm_intermediate_val = latency * pixel_rate;
3095         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3096                                 plane_blocks_per_line;
3097
3098         return ret;
3099 }
3100
3101 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3102                                        const struct intel_crtc *intel_crtc)
3103 {
3104         struct drm_device *dev = intel_crtc->base.dev;
3105         struct drm_i915_private *dev_priv = dev->dev_private;
3106         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3107
3108         /*
3109          * If ddb allocation of pipes changed, it may require recalculation of
3110          * watermarks
3111          */
3112         if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3113                 return true;
3114
3115         return false;
3116 }
3117
3118 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3119                                  struct intel_crtc_state *cstate,
3120                                  struct intel_plane *intel_plane,
3121                                  uint16_t ddb_allocation,
3122                                  int level,
3123                                  uint16_t *out_blocks, /* out */
3124                                  uint8_t *out_lines /* out */)
3125 {
3126         struct drm_plane *plane = &intel_plane->base;
3127         struct drm_framebuffer *fb = plane->state->fb;
3128         uint32_t latency = dev_priv->wm.skl_latency[level];
3129         uint32_t method1, method2;
3130         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3131         uint32_t res_blocks, res_lines;
3132         uint32_t selected_result;
3133         uint8_t bytes_per_pixel;
3134
3135         if (latency == 0 || !cstate->base.active || !fb)
3136                 return false;
3137
3138         bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);
3139         method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3140                                  bytes_per_pixel,
3141                                  latency);
3142         method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3143                                  cstate->base.adjusted_mode.crtc_htotal,
3144                                  cstate->pipe_src_w,
3145                                  bytes_per_pixel,
3146                                  fb->modifier[0],
3147                                  latency);
3148
3149         plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
3150         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3151
3152         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3153             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3154                 uint32_t min_scanlines = 4;
3155                 uint32_t y_tile_minimum;
3156                 if (intel_rotation_90_or_270(plane->state->rotation)) {
3157                         int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3158                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3159                                 drm_format_plane_cpp(fb->pixel_format, 0);
3160
3161                         switch (bpp) {
3162                         case 1:
3163                                 min_scanlines = 16;
3164                                 break;
3165                         case 2:
3166                                 min_scanlines = 8;
3167                                 break;
3168                         case 8:
3169                                 WARN(1, "Unsupported pixel depth for rotation");
3170                         }
3171                 }
3172                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3173                 selected_result = max(method2, y_tile_minimum);
3174         } else {
3175                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3176                         selected_result = min(method1, method2);
3177                 else
3178                         selected_result = method1;
3179         }
3180
3181         res_blocks = selected_result + 1;
3182         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3183
3184         if (level >= 1 && level <= 7) {
3185                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3186                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3187                         res_lines += 4;
3188                 else
3189                         res_blocks++;
3190         }
3191
3192         if (res_blocks >= ddb_allocation || res_lines > 31)
3193                 return false;
3194
3195         *out_blocks = res_blocks;
3196         *out_lines = res_lines;
3197
3198         return true;
3199 }
3200
3201 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3202                                  struct skl_ddb_allocation *ddb,
3203                                  struct intel_crtc_state *cstate,
3204                                  int level,
3205                                  struct skl_wm_level *result)
3206 {
3207         struct drm_device *dev = dev_priv->dev;
3208         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3209         struct intel_plane *intel_plane;
3210         uint16_t ddb_blocks;
3211         enum pipe pipe = intel_crtc->pipe;
3212
3213         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3214                 int i = skl_wm_plane_id(intel_plane);
3215
3216                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3217
3218                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3219                                                 cstate,
3220                                                 intel_plane,
3221                                                 ddb_blocks,
3222                                                 level,
3223                                                 &result->plane_res_b[i],
3224                                                 &result->plane_res_l[i]);
3225         }
3226 }
3227
3228 static uint32_t
3229 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3230 {
3231         if (!cstate->base.active)
3232                 return 0;
3233
3234         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3235                 return 0;
3236
3237         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3238                             skl_pipe_pixel_rate(cstate));
3239 }
3240
3241 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3242                                       struct skl_wm_level *trans_wm /* out */)
3243 {
3244         struct drm_crtc *crtc = cstate->base.crtc;
3245         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3246         struct intel_plane *intel_plane;
3247
3248         if (!cstate->base.active)
3249                 return;
3250
3251         /* Until we know more, just disable transition WMs */
3252         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3253                 int i = skl_wm_plane_id(intel_plane);
3254
3255                 trans_wm->plane_en[i] = false;
3256         }
3257 }
3258
3259 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3260                                 struct skl_ddb_allocation *ddb,
3261                                 struct skl_pipe_wm *pipe_wm)
3262 {
3263         struct drm_device *dev = cstate->base.crtc->dev;
3264         const struct drm_i915_private *dev_priv = dev->dev_private;
3265         int level, max_level = ilk_wm_max_level(dev);
3266
3267         for (level = 0; level <= max_level; level++) {
3268                 skl_compute_wm_level(dev_priv, ddb, cstate,
3269                                      level, &pipe_wm->wm[level]);
3270         }
3271         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3272
3273         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3274 }
3275
3276 static void skl_compute_wm_results(struct drm_device *dev,
3277                                    struct skl_pipe_wm *p_wm,
3278                                    struct skl_wm_values *r,
3279                                    struct intel_crtc *intel_crtc)
3280 {
3281         int level, max_level = ilk_wm_max_level(dev);
3282         enum pipe pipe = intel_crtc->pipe;
3283         uint32_t temp;
3284         int i;
3285
3286         for (level = 0; level <= max_level; level++) {
3287                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3288                         temp = 0;
3289
3290                         temp |= p_wm->wm[level].plane_res_l[i] <<
3291                                         PLANE_WM_LINES_SHIFT;
3292                         temp |= p_wm->wm[level].plane_res_b[i];
3293                         if (p_wm->wm[level].plane_en[i])
3294                                 temp |= PLANE_WM_EN;
3295
3296                         r->plane[pipe][i][level] = temp;
3297                 }
3298
3299                 temp = 0;
3300
3301                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3302                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3303
3304                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3305                         temp |= PLANE_WM_EN;
3306
3307                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3308
3309         }
3310
3311         /* transition WMs */
3312         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3313                 temp = 0;
3314                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3315                 temp |= p_wm->trans_wm.plane_res_b[i];
3316                 if (p_wm->trans_wm.plane_en[i])
3317                         temp |= PLANE_WM_EN;
3318
3319                 r->plane_trans[pipe][i] = temp;
3320         }
3321
3322         temp = 0;
3323         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3324         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3325         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3326                 temp |= PLANE_WM_EN;
3327
3328         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3329
3330         r->wm_linetime[pipe] = p_wm->linetime;
3331 }
3332
3333 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3334                                 i915_reg_t reg,
3335                                 const struct skl_ddb_entry *entry)
3336 {
3337         if (entry->end)
3338                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3339         else
3340                 I915_WRITE(reg, 0);
3341 }
3342
3343 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3344                                 const struct skl_wm_values *new)
3345 {
3346         struct drm_device *dev = dev_priv->dev;
3347         struct intel_crtc *crtc;
3348
3349         for_each_intel_crtc(dev, crtc) {
3350                 int i, level, max_level = ilk_wm_max_level(dev);
3351                 enum pipe pipe = crtc->pipe;
3352
3353                 if (!new->dirty[pipe])
3354                         continue;
3355
3356                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3357
3358                 for (level = 0; level <= max_level; level++) {
3359                         for (i = 0; i < intel_num_planes(crtc); i++)
3360                                 I915_WRITE(PLANE_WM(pipe, i, level),
3361                                            new->plane[pipe][i][level]);
3362                         I915_WRITE(CUR_WM(pipe, level),
3363                                    new->plane[pipe][PLANE_CURSOR][level]);
3364                 }
3365                 for (i = 0; i < intel_num_planes(crtc); i++)
3366                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3367                                    new->plane_trans[pipe][i]);
3368                 I915_WRITE(CUR_WM_TRANS(pipe),
3369                            new->plane_trans[pipe][PLANE_CURSOR]);
3370
3371                 for (i = 0; i < intel_num_planes(crtc); i++) {
3372                         skl_ddb_entry_write(dev_priv,
3373                                             PLANE_BUF_CFG(pipe, i),
3374                                             &new->ddb.plane[pipe][i]);
3375                         skl_ddb_entry_write(dev_priv,
3376                                             PLANE_NV12_BUF_CFG(pipe, i),
3377                                             &new->ddb.y_plane[pipe][i]);
3378                 }
3379
3380                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3381                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3382         }
3383 }
3384
3385 /*
3386  * When setting up a new DDB allocation arrangement, we need to correctly
3387  * sequence the times at which the new allocations for the pipes are taken into
3388  * account or we'll have pipes fetching from space previously allocated to
3389  * another pipe.
3390  *
3391  * Roughly the sequence looks like:
3392  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3393  *     overlapping with a previous light-up pipe (another way to put it is:
3394  *     pipes with their new allocation strickly included into their old ones).
3395  *  2. re-allocate the other pipes that get their allocation reduced
3396  *  3. allocate the pipes having their allocation increased
3397  *
3398  * Steps 1. and 2. are here to take care of the following case:
3399  * - Initially DDB looks like this:
3400  *     |   B    |   C    |
3401  * - enable pipe A.
3402  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3403  *   allocation
3404  *     |  A  |  B  |  C  |
3405  *
3406  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3407  */
3408
3409 static void
3410 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3411 {
3412         int plane;
3413
3414         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3415
3416         for_each_plane(dev_priv, pipe, plane) {
3417                 I915_WRITE(PLANE_SURF(pipe, plane),
3418                            I915_READ(PLANE_SURF(pipe, plane)));
3419         }
3420         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3421 }
3422
3423 static bool
3424 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3425                             const struct skl_ddb_allocation *new,
3426                             enum pipe pipe)
3427 {
3428         uint16_t old_size, new_size;
3429
3430         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3431         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3432
3433         return old_size != new_size &&
3434                new->pipe[pipe].start >= old->pipe[pipe].start &&
3435                new->pipe[pipe].end <= old->pipe[pipe].end;
3436 }
3437
3438 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3439                                 struct skl_wm_values *new_values)
3440 {
3441         struct drm_device *dev = dev_priv->dev;
3442         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3443         bool reallocated[I915_MAX_PIPES] = {};
3444         struct intel_crtc *crtc;
3445         enum pipe pipe;
3446
3447         new_ddb = &new_values->ddb;
3448         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3449
3450         /*
3451          * First pass: flush the pipes with the new allocation contained into
3452          * the old space.
3453          *
3454          * We'll wait for the vblank on those pipes to ensure we can safely
3455          * re-allocate the freed space without this pipe fetching from it.
3456          */
3457         for_each_intel_crtc(dev, crtc) {
3458                 if (!crtc->active)
3459                         continue;
3460
3461                 pipe = crtc->pipe;
3462
3463                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3464                         continue;
3465
3466                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3467                 intel_wait_for_vblank(dev, pipe);
3468
3469                 reallocated[pipe] = true;
3470         }
3471
3472
3473         /*
3474          * Second pass: flush the pipes that are having their allocation
3475          * reduced, but overlapping with a previous allocation.
3476          *
3477          * Here as well we need to wait for the vblank to make sure the freed
3478          * space is not used anymore.
3479          */
3480         for_each_intel_crtc(dev, crtc) {
3481                 if (!crtc->active)
3482                         continue;
3483
3484                 pipe = crtc->pipe;
3485
3486                 if (reallocated[pipe])
3487                         continue;
3488
3489                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3490                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3491                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3492                         intel_wait_for_vblank(dev, pipe);
3493                         reallocated[pipe] = true;
3494                 }
3495         }
3496
3497         /*
3498          * Third pass: flush the pipes that got more space allocated.
3499          *
3500          * We don't need to actively wait for the update here, next vblank
3501          * will just get more DDB space with the correct WM values.
3502          */
3503         for_each_intel_crtc(dev, crtc) {
3504                 if (!crtc->active)
3505                         continue;
3506
3507                 pipe = crtc->pipe;
3508
3509                 /*
3510                  * At this point, only the pipes more space than before are
3511                  * left to re-allocate.
3512                  */
3513                 if (reallocated[pipe])
3514                         continue;
3515
3516                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3517         }
3518 }
3519
3520 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3521                                struct skl_ddb_allocation *ddb, /* out */
3522                                struct skl_pipe_wm *pipe_wm /* out */)
3523 {
3524         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3525         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3526
3527         skl_allocate_pipe_ddb(cstate, ddb);
3528         skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3529
3530         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3531                 return false;
3532
3533         intel_crtc->wm.active.skl = *pipe_wm;
3534
3535         return true;
3536 }
3537
3538 static void skl_update_other_pipe_wm(struct drm_device *dev,
3539                                      struct drm_crtc *crtc,
3540                                      struct skl_wm_values *r)
3541 {
3542         struct intel_crtc *intel_crtc;
3543         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3544
3545         /*
3546          * If the WM update hasn't changed the allocation for this_crtc (the
3547          * crtc we are currently computing the new WM values for), other
3548          * enabled crtcs will keep the same allocation and we don't need to
3549          * recompute anything for them.
3550          */
3551         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3552                 return;
3553
3554         /*
3555          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3556          * other active pipes need new DDB allocation and WM values.
3557          */
3558         for_each_intel_crtc(dev, intel_crtc) {
3559                 struct skl_pipe_wm pipe_wm = {};
3560                 bool wm_changed;
3561
3562                 if (this_crtc->pipe == intel_crtc->pipe)
3563                         continue;
3564
3565                 if (!intel_crtc->active)
3566                         continue;
3567
3568                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3569                                                 &r->ddb, &pipe_wm);
3570
3571                 /*
3572                  * If we end up re-computing the other pipe WM values, it's
3573                  * because it was really needed, so we expect the WM values to
3574                  * be different.
3575                  */
3576                 WARN_ON(!wm_changed);
3577
3578                 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3579                 r->dirty[intel_crtc->pipe] = true;
3580         }
3581 }
3582
3583 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3584 {
3585         watermarks->wm_linetime[pipe] = 0;
3586         memset(watermarks->plane[pipe], 0,
3587                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3588         memset(watermarks->plane_trans[pipe],
3589                0, sizeof(uint32_t) * I915_MAX_PLANES);
3590         watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3591
3592         /* Clear ddb entries for pipe */
3593         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3594         memset(&watermarks->ddb.plane[pipe], 0,
3595                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3596         memset(&watermarks->ddb.y_plane[pipe], 0,
3597                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3598         memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3599                sizeof(struct skl_ddb_entry));
3600
3601 }
3602
3603 static void skl_update_wm(struct drm_crtc *crtc)
3604 {
3605         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3606         struct drm_device *dev = crtc->dev;
3607         struct drm_i915_private *dev_priv = dev->dev_private;
3608         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3609         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3610         struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3611
3612
3613         /* Clear all dirty flags */
3614         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3615
3616         skl_clear_wm(results, intel_crtc->pipe);
3617
3618         if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3619                 return;
3620
3621         skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3622         results->dirty[intel_crtc->pipe] = true;
3623
3624         skl_update_other_pipe_wm(dev, crtc, results);
3625         skl_write_wm_values(dev_priv, results);
3626         skl_flush_wm_values(dev_priv, results);
3627
3628         /* store the new configuration */
3629         dev_priv->wm.skl_hw = *results;
3630 }
3631
3632 static void ilk_compute_wm_config(struct drm_device *dev,
3633                                   struct intel_wm_config *config)
3634 {
3635         struct intel_crtc *crtc;
3636
3637         /* Compute the currently _active_ config */
3638         for_each_intel_crtc(dev, crtc) {
3639                 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3640
3641                 if (!wm->pipe_enabled)
3642                         continue;
3643
3644                 config->sprites_enabled |= wm->sprites_enabled;
3645                 config->sprites_scaled |= wm->sprites_scaled;
3646                 config->num_pipes_active++;
3647         }
3648 }
3649
3650 static void ilk_program_watermarks(struct intel_crtc_state *cstate)
3651 {
3652         struct drm_crtc *crtc = cstate->base.crtc;
3653         struct drm_device *dev = crtc->dev;
3654         struct drm_i915_private *dev_priv = to_i915(dev);
3655         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3656         struct ilk_wm_maximums max;
3657         struct intel_wm_config config = {};
3658         struct ilk_wm_values results = {};
3659         enum intel_ddb_partitioning partitioning;
3660
3661         ilk_compute_wm_config(dev, &config);
3662
3663         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3664         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
3665
3666         /* 5/6 split only in single pipe config on IVB+ */
3667         if (INTEL_INFO(dev)->gen >= 7 &&
3668             config.num_pipes_active == 1 && config.sprites_enabled) {
3669                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3670                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
3671
3672                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3673         } else {
3674                 best_lp_wm = &lp_wm_1_2;
3675         }
3676
3677         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3678                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3679
3680         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3681
3682         ilk_write_wm_values(dev_priv, &results);
3683 }
3684
3685 static void ilk_update_wm(struct drm_crtc *crtc)
3686 {
3687         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3688         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3689
3690         WARN_ON(cstate->base.active != intel_crtc->active);
3691
3692         /*
3693          * IVB workaround: must disable low power watermarks for at least
3694          * one frame before enabling scaling.  LP watermarks can be re-enabled
3695          * when scaling is disabled.
3696          *
3697          * WaCxSRDisabledForSpriteScaling:ivb
3698          */
3699         if (cstate->disable_lp_wm) {
3700                 ilk_disable_lp_wm(crtc->dev);
3701                 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
3702         }
3703
3704         intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3705
3706         ilk_program_watermarks(cstate);
3707 }
3708
3709 static void skl_pipe_wm_active_state(uint32_t val,
3710                                      struct skl_pipe_wm *active,
3711                                      bool is_transwm,
3712                                      bool is_cursor,
3713                                      int i,
3714                                      int level)
3715 {
3716         bool is_enabled = (val & PLANE_WM_EN) != 0;
3717
3718         if (!is_transwm) {
3719                 if (!is_cursor) {
3720                         active->wm[level].plane_en[i] = is_enabled;
3721                         active->wm[level].plane_res_b[i] =
3722                                         val & PLANE_WM_BLOCKS_MASK;
3723                         active->wm[level].plane_res_l[i] =
3724                                         (val >> PLANE_WM_LINES_SHIFT) &
3725                                                 PLANE_WM_LINES_MASK;
3726                 } else {
3727                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3728                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3729                                         val & PLANE_WM_BLOCKS_MASK;
3730                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3731                                         (val >> PLANE_WM_LINES_SHIFT) &
3732                                                 PLANE_WM_LINES_MASK;
3733                 }
3734         } else {
3735                 if (!is_cursor) {
3736                         active->trans_wm.plane_en[i] = is_enabled;
3737                         active->trans_wm.plane_res_b[i] =
3738                                         val & PLANE_WM_BLOCKS_MASK;
3739                         active->trans_wm.plane_res_l[i] =
3740                                         (val >> PLANE_WM_LINES_SHIFT) &
3741                                                 PLANE_WM_LINES_MASK;
3742                 } else {
3743                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3744                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3745                                         val & PLANE_WM_BLOCKS_MASK;
3746                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3747                                         (val >> PLANE_WM_LINES_SHIFT) &
3748                                                 PLANE_WM_LINES_MASK;
3749                 }
3750         }
3751 }
3752
3753 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3754 {
3755         struct drm_device *dev = crtc->dev;
3756         struct drm_i915_private *dev_priv = dev->dev_private;
3757         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3758         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3759         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3760         struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3761         enum pipe pipe = intel_crtc->pipe;
3762         int level, i, max_level;
3763         uint32_t temp;
3764
3765         max_level = ilk_wm_max_level(dev);
3766
3767         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3768
3769         for (level = 0; level <= max_level; level++) {
3770                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3771                         hw->plane[pipe][i][level] =
3772                                         I915_READ(PLANE_WM(pipe, i, level));
3773                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3774         }
3775
3776         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3777                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3778         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3779
3780         if (!intel_crtc->active)
3781                 return;
3782
3783         hw->dirty[pipe] = true;
3784
3785         active->linetime = hw->wm_linetime[pipe];
3786
3787         for (level = 0; level <= max_level; level++) {
3788                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3789                         temp = hw->plane[pipe][i][level];
3790                         skl_pipe_wm_active_state(temp, active, false,
3791                                                 false, i, level);
3792                 }
3793                 temp = hw->plane[pipe][PLANE_CURSOR][level];
3794                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3795         }
3796
3797         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3798                 temp = hw->plane_trans[pipe][i];
3799                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3800         }
3801
3802         temp = hw->plane_trans[pipe][PLANE_CURSOR];
3803         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3804
3805         intel_crtc->wm.active.skl = *active;
3806 }
3807
3808 void skl_wm_get_hw_state(struct drm_device *dev)
3809 {
3810         struct drm_i915_private *dev_priv = dev->dev_private;
3811         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3812         struct drm_crtc *crtc;
3813
3814         skl_ddb_get_hw_state(dev_priv, ddb);
3815         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3816                 skl_pipe_wm_get_hw_state(crtc);
3817 }
3818
3819 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3820 {
3821         struct drm_device *dev = crtc->dev;
3822         struct drm_i915_private *dev_priv = dev->dev_private;
3823         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3825         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3826         struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3827         enum pipe pipe = intel_crtc->pipe;
3828         static const i915_reg_t wm0_pipe_reg[] = {
3829                 [PIPE_A] = WM0_PIPEA_ILK,
3830                 [PIPE_B] = WM0_PIPEB_ILK,
3831                 [PIPE_C] = WM0_PIPEC_IVB,
3832         };
3833
3834         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3835         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3836                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3837
3838         active->pipe_enabled = intel_crtc->active;
3839
3840         if (active->pipe_enabled) {
3841                 u32 tmp = hw->wm_pipe[pipe];
3842
3843                 /*
3844                  * For active pipes LP0 watermark is marked as
3845                  * enabled, and LP1+ watermaks as disabled since
3846                  * we can't really reverse compute them in case
3847                  * multiple pipes are active.
3848                  */
3849                 active->wm[0].enable = true;
3850                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3851                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3852                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3853                 active->linetime = hw->wm_linetime[pipe];
3854         } else {
3855                 int level, max_level = ilk_wm_max_level(dev);
3856
3857                 /*
3858                  * For inactive pipes, all watermark levels
3859                  * should be marked as enabled but zeroed,
3860                  * which is what we'd compute them to.
3861                  */
3862                 for (level = 0; level <= max_level; level++)
3863                         active->wm[level].enable = true;
3864         }
3865
3866         intel_crtc->wm.active.ilk = *active;
3867 }
3868
3869 #define _FW_WM(value, plane) \
3870         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3871 #define _FW_WM_VLV(value, plane) \
3872         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3873
3874 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3875                                struct vlv_wm_values *wm)
3876 {
3877         enum pipe pipe;
3878         uint32_t tmp;
3879
3880         for_each_pipe(dev_priv, pipe) {
3881                 tmp = I915_READ(VLV_DDL(pipe));
3882
3883                 wm->ddl[pipe].primary =
3884                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3885                 wm->ddl[pipe].cursor =
3886                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3887                 wm->ddl[pipe].sprite[0] =
3888                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3889                 wm->ddl[pipe].sprite[1] =
3890                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3891         }
3892
3893         tmp = I915_READ(DSPFW1);
3894         wm->sr.plane = _FW_WM(tmp, SR);
3895         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3896         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3897         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3898
3899         tmp = I915_READ(DSPFW2);
3900         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3901         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3902         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3903
3904         tmp = I915_READ(DSPFW3);
3905         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3906
3907         if (IS_CHERRYVIEW(dev_priv)) {
3908                 tmp = I915_READ(DSPFW7_CHV);
3909                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3910                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3911
3912                 tmp = I915_READ(DSPFW8_CHV);
3913                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3914                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3915
3916                 tmp = I915_READ(DSPFW9_CHV);
3917                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3918                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3919
3920                 tmp = I915_READ(DSPHOWM);
3921                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3922                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3923                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3924                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3925                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3926                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3927                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3928                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3929                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3930                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3931         } else {
3932                 tmp = I915_READ(DSPFW7);
3933                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3934                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3935
3936                 tmp = I915_READ(DSPHOWM);
3937                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3938                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3939                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3940                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3941                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3942                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3943                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3944         }
3945 }
3946
3947 #undef _FW_WM
3948 #undef _FW_WM_VLV
3949
3950 void vlv_wm_get_hw_state(struct drm_device *dev)
3951 {
3952         struct drm_i915_private *dev_priv = to_i915(dev);
3953         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3954         struct intel_plane *plane;
3955         enum pipe pipe;
3956         u32 val;
3957
3958         vlv_read_wm_values(dev_priv, wm);
3959
3960         for_each_intel_plane(dev, plane) {
3961                 switch (plane->base.type) {
3962                         int sprite;
3963                 case DRM_PLANE_TYPE_CURSOR:
3964                         plane->wm.fifo_size = 63;
3965                         break;
3966                 case DRM_PLANE_TYPE_PRIMARY:
3967                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3968                         break;
3969                 case DRM_PLANE_TYPE_OVERLAY:
3970                         sprite = plane->plane;
3971                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3972                         break;
3973                 }
3974         }
3975
3976         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3977         wm->level = VLV_WM_LEVEL_PM2;
3978
3979         if (IS_CHERRYVIEW(dev_priv)) {
3980                 mutex_lock(&dev_priv->rps.hw_lock);
3981
3982                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3983                 if (val & DSP_MAXFIFO_PM5_ENABLE)
3984                         wm->level = VLV_WM_LEVEL_PM5;
3985
3986                 /*
3987                  * If DDR DVFS is disabled in the BIOS, Punit
3988                  * will never ack the request. So if that happens
3989                  * assume we don't have to enable/disable DDR DVFS
3990                  * dynamically. To test that just set the REQ_ACK
3991                  * bit to poke the Punit, but don't change the
3992                  * HIGH/LOW bits so that we don't actually change
3993                  * the current state.
3994                  */
3995                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3996                 val |= FORCE_DDR_FREQ_REQ_ACK;
3997                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
3998
3999                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4000                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4001                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4002                                       "assuming DDR DVFS is disabled\n");
4003                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4004                 } else {
4005                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4006                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4007                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4008                 }
4009
4010                 mutex_unlock(&dev_priv->rps.hw_lock);
4011         }
4012
4013         for_each_pipe(dev_priv, pipe)
4014                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4015                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4016                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4017
4018         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4019                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4020 }
4021
4022 void ilk_wm_get_hw_state(struct drm_device *dev)
4023 {
4024         struct drm_i915_private *dev_priv = dev->dev_private;
4025         struct ilk_wm_values *hw = &dev_priv->wm.hw;
4026         struct drm_crtc *crtc;
4027
4028         for_each_crtc(dev, crtc)
4029                 ilk_pipe_wm_get_hw_state(crtc);
4030
4031         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4032         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4033         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4034
4035         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
4036         if (INTEL_INFO(dev)->gen >= 7) {
4037                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4038                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4039         }
4040
4041         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4042                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4043                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4044         else if (IS_IVYBRIDGE(dev))
4045                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4046                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4047
4048         hw->enable_fbc_wm =
4049                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4050 }
4051
4052 /**
4053  * intel_update_watermarks - update FIFO watermark values based on current modes
4054  *
4055  * Calculate watermark values for the various WM regs based on current mode
4056  * and plane configuration.
4057  *
4058  * There are several cases to deal with here:
4059  *   - normal (i.e. non-self-refresh)
4060  *   - self-refresh (SR) mode
4061  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4062  *   - lines are small relative to FIFO size (buffer can hold more than 2
4063  *     lines), so need to account for TLB latency
4064  *
4065  *   The normal calculation is:
4066  *     watermark = dotclock * bytes per pixel * latency
4067  *   where latency is platform & configuration dependent (we assume pessimal
4068  *   values here).
4069  *
4070  *   The SR calculation is:
4071  *     watermark = (trunc(latency/line time)+1) * surface width *
4072  *       bytes per pixel
4073  *   where
4074  *     line time = htotal / dotclock
4075  *     surface width = hdisplay for normal plane and 64 for cursor
4076  *   and latency is assumed to be high, as above.
4077  *
4078  * The final value programmed to the register should always be rounded up,
4079  * and include an extra 2 entries to account for clock crossings.
4080  *
4081  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4082  * to set the non-SR watermarks to 8.
4083  */
4084 void intel_update_watermarks(struct drm_crtc *crtc)
4085 {
4086         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4087
4088         if (dev_priv->display.update_wm)
4089                 dev_priv->display.update_wm(crtc);
4090 }
4091
4092 /*
4093  * Lock protecting IPS related data structures
4094  */
4095 DEFINE_SPINLOCK(mchdev_lock);
4096
4097 /* Global for IPS driver to get at the current i915 device. Protected by
4098  * mchdev_lock. */
4099 static struct drm_i915_private *i915_mch_dev;
4100
4101 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4102 {
4103         struct drm_i915_private *dev_priv = dev->dev_private;
4104         u16 rgvswctl;
4105
4106         assert_spin_locked(&mchdev_lock);
4107
4108         rgvswctl = I915_READ16(MEMSWCTL);
4109         if (rgvswctl & MEMCTL_CMD_STS) {
4110                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4111                 return false; /* still busy with another command */
4112         }
4113
4114         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4115                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4116         I915_WRITE16(MEMSWCTL, rgvswctl);
4117         POSTING_READ16(MEMSWCTL);
4118
4119         rgvswctl |= MEMCTL_CMD_STS;
4120         I915_WRITE16(MEMSWCTL, rgvswctl);
4121
4122         return true;
4123 }
4124
4125 static void ironlake_enable_drps(struct drm_device *dev)
4126 {
4127         struct drm_i915_private *dev_priv = dev->dev_private;
4128         u32 rgvmodectl = I915_READ(MEMMODECTL);
4129         u8 fmax, fmin, fstart, vstart;
4130
4131         spin_lock_irq(&mchdev_lock);
4132
4133         /* Enable temp reporting */
4134         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4135         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4136
4137         /* 100ms RC evaluation intervals */
4138         I915_WRITE(RCUPEI, 100000);
4139         I915_WRITE(RCDNEI, 100000);
4140
4141         /* Set max/min thresholds to 90ms and 80ms respectively */
4142         I915_WRITE(RCBMAXAVG, 90000);
4143         I915_WRITE(RCBMINAVG, 80000);
4144
4145         I915_WRITE(MEMIHYST, 1);
4146
4147         /* Set up min, max, and cur for interrupt handling */
4148         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4149         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4150         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4151                 MEMMODE_FSTART_SHIFT;
4152
4153         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4154                 PXVFREQ_PX_SHIFT;
4155
4156         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4157         dev_priv->ips.fstart = fstart;
4158
4159         dev_priv->ips.max_delay = fstart;
4160         dev_priv->ips.min_delay = fmin;
4161         dev_priv->ips.cur_delay = fstart;
4162
4163         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4164                          fmax, fmin, fstart);
4165
4166         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4167
4168         /*
4169          * Interrupts will be enabled in ironlake_irq_postinstall
4170          */
4171
4172         I915_WRITE(VIDSTART, vstart);
4173         POSTING_READ(VIDSTART);
4174
4175         rgvmodectl |= MEMMODE_SWMODE_EN;
4176         I915_WRITE(MEMMODECTL, rgvmodectl);
4177
4178         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4179                 DRM_ERROR("stuck trying to change perf mode\n");
4180         mdelay(1);
4181
4182         ironlake_set_drps(dev, fstart);
4183
4184         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4185                 I915_READ(DDREC) + I915_READ(CSIEC);
4186         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4187         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4188         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4189
4190         spin_unlock_irq(&mchdev_lock);
4191 }
4192
4193 static void ironlake_disable_drps(struct drm_device *dev)
4194 {
4195         struct drm_i915_private *dev_priv = dev->dev_private;
4196         u16 rgvswctl;
4197
4198         spin_lock_irq(&mchdev_lock);
4199
4200         rgvswctl = I915_READ16(MEMSWCTL);
4201
4202         /* Ack interrupts, disable EFC interrupt */
4203         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4204         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4205         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4206         I915_WRITE(DEIIR, DE_PCU_EVENT);
4207         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4208
4209         /* Go back to the starting frequency */
4210         ironlake_set_drps(dev, dev_priv->ips.fstart);
4211         mdelay(1);
4212         rgvswctl |= MEMCTL_CMD_STS;
4213         I915_WRITE(MEMSWCTL, rgvswctl);
4214         mdelay(1);
4215
4216         spin_unlock_irq(&mchdev_lock);
4217 }
4218
4219 /* There's a funny hw issue where the hw returns all 0 when reading from
4220  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4221  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4222  * all limits and the gpu stuck at whatever frequency it is at atm).
4223  */
4224 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4225 {
4226         u32 limits;
4227
4228         /* Only set the down limit when we've reached the lowest level to avoid
4229          * getting more interrupts, otherwise leave this clear. This prevents a
4230          * race in the hw when coming out of rc6: There's a tiny window where
4231          * the hw runs at the minimal clock before selecting the desired
4232          * frequency, if the down threshold expires in that window we will not
4233          * receive a down interrupt. */
4234         if (IS_GEN9(dev_priv->dev)) {
4235                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4236                 if (val <= dev_priv->rps.min_freq_softlimit)
4237                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4238         } else {
4239                 limits = dev_priv->rps.max_freq_softlimit << 24;
4240                 if (val <= dev_priv->rps.min_freq_softlimit)
4241                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4242         }
4243
4244         return limits;
4245 }
4246
4247 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4248 {
4249         int new_power;
4250         u32 threshold_up = 0, threshold_down = 0; /* in % */
4251         u32 ei_up = 0, ei_down = 0;
4252
4253         new_power = dev_priv->rps.power;
4254         switch (dev_priv->rps.power) {
4255         case LOW_POWER:
4256                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4257                         new_power = BETWEEN;
4258                 break;
4259
4260         case BETWEEN:
4261                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4262                         new_power = LOW_POWER;
4263                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4264                         new_power = HIGH_POWER;
4265                 break;
4266
4267         case HIGH_POWER:
4268                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4269                         new_power = BETWEEN;
4270                 break;
4271         }
4272         /* Max/min bins are special */
4273         if (val <= dev_priv->rps.min_freq_softlimit)
4274                 new_power = LOW_POWER;
4275         if (val >= dev_priv->rps.max_freq_softlimit)
4276                 new_power = HIGH_POWER;
4277         if (new_power == dev_priv->rps.power)
4278                 return;
4279
4280         /* Note the units here are not exactly 1us, but 1280ns. */
4281         switch (new_power) {
4282         case LOW_POWER:
4283                 /* Upclock if more than 95% busy over 16ms */
4284                 ei_up = 16000;
4285                 threshold_up = 95;
4286
4287                 /* Downclock if less than 85% busy over 32ms */
4288                 ei_down = 32000;
4289                 threshold_down = 85;
4290                 break;
4291
4292         case BETWEEN:
4293                 /* Upclock if more than 90% busy over 13ms */
4294                 ei_up = 13000;
4295                 threshold_up = 90;
4296
4297                 /* Downclock if less than 75% busy over 32ms */
4298                 ei_down = 32000;
4299                 threshold_down = 75;
4300                 break;
4301
4302         case HIGH_POWER:
4303                 /* Upclock if more than 85% busy over 10ms */
4304                 ei_up = 10000;
4305                 threshold_up = 85;
4306
4307                 /* Downclock if less than 60% busy over 32ms */
4308                 ei_down = 32000;
4309                 threshold_down = 60;
4310                 break;
4311         }
4312
4313         I915_WRITE(GEN6_RP_UP_EI,
4314                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4315         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4316                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4317
4318         I915_WRITE(GEN6_RP_DOWN_EI,
4319                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4320         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4321                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4322
4323          I915_WRITE(GEN6_RP_CONTROL,
4324                     GEN6_RP_MEDIA_TURBO |
4325                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4326                     GEN6_RP_MEDIA_IS_GFX |
4327                     GEN6_RP_ENABLE |
4328                     GEN6_RP_UP_BUSY_AVG |
4329                     GEN6_RP_DOWN_IDLE_AVG);
4330
4331         dev_priv->rps.power = new_power;
4332         dev_priv->rps.up_threshold = threshold_up;
4333         dev_priv->rps.down_threshold = threshold_down;
4334         dev_priv->rps.last_adj = 0;
4335 }
4336
4337 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4338 {
4339         u32 mask = 0;
4340
4341         if (val > dev_priv->rps.min_freq_softlimit)
4342                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4343         if (val < dev_priv->rps.max_freq_softlimit)
4344                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4345
4346         mask &= dev_priv->pm_rps_events;
4347
4348         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4349 }
4350
4351 /* gen6_set_rps is called to update the frequency request, but should also be
4352  * called when the range (min_delay and max_delay) is modified so that we can
4353  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4354 static void gen6_set_rps(struct drm_device *dev, u8 val)
4355 {
4356         struct drm_i915_private *dev_priv = dev->dev_private;
4357
4358         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4359         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
4360                 return;
4361
4362         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4363         WARN_ON(val > dev_priv->rps.max_freq);
4364         WARN_ON(val < dev_priv->rps.min_freq);
4365
4366         /* min/max delay may still have been modified so be sure to
4367          * write the limits value.
4368          */
4369         if (val != dev_priv->rps.cur_freq) {
4370                 gen6_set_rps_thresholds(dev_priv, val);
4371
4372                 if (IS_GEN9(dev))
4373                         I915_WRITE(GEN6_RPNSWREQ,
4374                                    GEN9_FREQUENCY(val));
4375                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4376                         I915_WRITE(GEN6_RPNSWREQ,
4377                                    HSW_FREQUENCY(val));
4378                 else
4379                         I915_WRITE(GEN6_RPNSWREQ,
4380                                    GEN6_FREQUENCY(val) |
4381                                    GEN6_OFFSET(0) |
4382                                    GEN6_AGGRESSIVE_TURBO);
4383         }
4384
4385         /* Make sure we continue to get interrupts
4386          * until we hit the minimum or maximum frequencies.
4387          */
4388         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4389         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4390
4391         POSTING_READ(GEN6_RPNSWREQ);
4392
4393         dev_priv->rps.cur_freq = val;
4394         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4395 }
4396
4397 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4398 {
4399         struct drm_i915_private *dev_priv = dev->dev_private;
4400
4401         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4402         WARN_ON(val > dev_priv->rps.max_freq);
4403         WARN_ON(val < dev_priv->rps.min_freq);
4404
4405         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4406                       "Odd GPU freq value\n"))
4407                 val &= ~1;
4408
4409         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4410
4411         if (val != dev_priv->rps.cur_freq) {
4412                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4413                 if (!IS_CHERRYVIEW(dev_priv))
4414                         gen6_set_rps_thresholds(dev_priv, val);
4415         }
4416
4417         dev_priv->rps.cur_freq = val;
4418         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4419 }
4420
4421 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4422  *
4423  * * If Gfx is Idle, then
4424  * 1. Forcewake Media well.
4425  * 2. Request idle freq.
4426  * 3. Release Forcewake of Media well.
4427 */
4428 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4429 {
4430         u32 val = dev_priv->rps.idle_freq;
4431
4432         if (dev_priv->rps.cur_freq <= val)
4433                 return;
4434
4435         /* Wake up the media well, as that takes a lot less
4436          * power than the Render well. */
4437         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4438         valleyview_set_rps(dev_priv->dev, val);
4439         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4440 }
4441
4442 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4443 {
4444         mutex_lock(&dev_priv->rps.hw_lock);
4445         if (dev_priv->rps.enabled) {
4446                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4447                         gen6_rps_reset_ei(dev_priv);
4448                 I915_WRITE(GEN6_PMINTRMSK,
4449                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4450         }
4451         mutex_unlock(&dev_priv->rps.hw_lock);
4452 }
4453
4454 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4455 {
4456         struct drm_device *dev = dev_priv->dev;
4457
4458         mutex_lock(&dev_priv->rps.hw_lock);
4459         if (dev_priv->rps.enabled) {
4460                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4461                         vlv_set_rps_idle(dev_priv);
4462                 else
4463                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4464                 dev_priv->rps.last_adj = 0;
4465                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4466         }
4467         mutex_unlock(&dev_priv->rps.hw_lock);
4468
4469         spin_lock(&dev_priv->rps.client_lock);
4470         while (!list_empty(&dev_priv->rps.clients))
4471                 list_del_init(dev_priv->rps.clients.next);
4472         spin_unlock(&dev_priv->rps.client_lock);
4473 }
4474
4475 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4476                     struct intel_rps_client *rps,
4477                     unsigned long submitted)
4478 {
4479         /* This is intentionally racy! We peek at the state here, then
4480          * validate inside the RPS worker.
4481          */
4482         if (!(dev_priv->mm.busy &&
4483               dev_priv->rps.enabled &&
4484               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4485                 return;
4486
4487         /* Force a RPS boost (and don't count it against the client) if
4488          * the GPU is severely congested.
4489          */
4490         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4491                 rps = NULL;
4492
4493         spin_lock(&dev_priv->rps.client_lock);
4494         if (rps == NULL || list_empty(&rps->link)) {
4495                 spin_lock_irq(&dev_priv->irq_lock);
4496                 if (dev_priv->rps.interrupts_enabled) {
4497                         dev_priv->rps.client_boost = true;
4498                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4499                 }
4500                 spin_unlock_irq(&dev_priv->irq_lock);
4501
4502                 if (rps != NULL) {
4503                         list_add(&rps->link, &dev_priv->rps.clients);
4504                         rps->boosts++;
4505                 } else
4506                         dev_priv->rps.boosts++;
4507         }
4508         spin_unlock(&dev_priv->rps.client_lock);
4509 }
4510
4511 void intel_set_rps(struct drm_device *dev, u8 val)
4512 {
4513         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4514                 valleyview_set_rps(dev, val);
4515         else
4516                 gen6_set_rps(dev, val);
4517 }
4518
4519 static void gen9_disable_rps(struct drm_device *dev)
4520 {
4521         struct drm_i915_private *dev_priv = dev->dev_private;
4522
4523         I915_WRITE(GEN6_RC_CONTROL, 0);
4524         I915_WRITE(GEN9_PG_ENABLE, 0);
4525 }
4526
4527 static void gen6_disable_rps(struct drm_device *dev)
4528 {
4529         struct drm_i915_private *dev_priv = dev->dev_private;
4530
4531         I915_WRITE(GEN6_RC_CONTROL, 0);
4532         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4533 }
4534
4535 static void cherryview_disable_rps(struct drm_device *dev)
4536 {
4537         struct drm_i915_private *dev_priv = dev->dev_private;
4538
4539         I915_WRITE(GEN6_RC_CONTROL, 0);
4540 }
4541
4542 static void valleyview_disable_rps(struct drm_device *dev)
4543 {
4544         struct drm_i915_private *dev_priv = dev->dev_private;
4545
4546         /* we're doing forcewake before Disabling RC6,
4547          * This what the BIOS expects when going into suspend */
4548         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4549
4550         I915_WRITE(GEN6_RC_CONTROL, 0);
4551
4552         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4553 }
4554
4555 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4556 {
4557         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
4558                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4559                         mode = GEN6_RC_CTL_RC6_ENABLE;
4560                 else
4561                         mode = 0;
4562         }
4563         if (HAS_RC6p(dev))
4564                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4565                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4566                               onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4567                               onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
4568
4569         else
4570                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4571                               onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
4572 }
4573
4574 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4575 {
4576         /* No RC6 before Ironlake and code is gone for ilk. */
4577         if (INTEL_INFO(dev)->gen < 6)
4578                 return 0;
4579
4580         /* Respect the kernel parameter if it is set */
4581         if (enable_rc6 >= 0) {
4582                 int mask;
4583
4584                 if (HAS_RC6p(dev))
4585                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4586                                INTEL_RC6pp_ENABLE;
4587                 else
4588                         mask = INTEL_RC6_ENABLE;
4589
4590                 if ((enable_rc6 & mask) != enable_rc6)
4591                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4592                                       enable_rc6 & mask, enable_rc6, mask);
4593
4594                 return enable_rc6 & mask;
4595         }
4596
4597         if (IS_IVYBRIDGE(dev))
4598                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4599
4600         return INTEL_RC6_ENABLE;
4601 }
4602
4603 int intel_enable_rc6(const struct drm_device *dev)
4604 {
4605         return i915.enable_rc6;
4606 }
4607
4608 static void gen6_init_rps_frequencies(struct drm_device *dev)
4609 {
4610         struct drm_i915_private *dev_priv = dev->dev_private;
4611         uint32_t rp_state_cap;
4612         u32 ddcc_status = 0;
4613         int ret;
4614
4615         /* All of these values are in units of 50MHz */
4616         dev_priv->rps.cur_freq          = 0;
4617         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4618         if (IS_BROXTON(dev)) {
4619                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4620                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4621                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4622                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4623         } else {
4624                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4625                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4626                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4627                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4628         }
4629
4630         /* hw_max = RP0 until we check for overclocking */
4631         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4632
4633         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4634         if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4635             IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4636                 ret = sandybridge_pcode_read(dev_priv,
4637                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4638                                         &ddcc_status);
4639                 if (0 == ret)
4640                         dev_priv->rps.efficient_freq =
4641                                 clamp_t(u8,
4642                                         ((ddcc_status >> 8) & 0xff),
4643                                         dev_priv->rps.min_freq,
4644                                         dev_priv->rps.max_freq);
4645         }
4646
4647         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4648                 /* Store the frequency values in 16.66 MHZ units, which is
4649                    the natural hardware unit for SKL */
4650                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4651                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4652                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4653                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4654                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4655         }
4656
4657         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4658
4659         /* Preserve min/max settings in case of re-init */
4660         if (dev_priv->rps.max_freq_softlimit == 0)
4661                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4662
4663         if (dev_priv->rps.min_freq_softlimit == 0) {
4664                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4665                         dev_priv->rps.min_freq_softlimit =
4666                                 max_t(int, dev_priv->rps.efficient_freq,
4667                                       intel_freq_opcode(dev_priv, 450));
4668                 else
4669                         dev_priv->rps.min_freq_softlimit =
4670                                 dev_priv->rps.min_freq;
4671         }
4672 }
4673
4674 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4675 static void gen9_enable_rps(struct drm_device *dev)
4676 {
4677         struct drm_i915_private *dev_priv = dev->dev_private;
4678
4679         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4680
4681         gen6_init_rps_frequencies(dev);
4682
4683         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4684         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4685                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4686                 return;
4687         }
4688
4689         /* Program defaults and thresholds for RPS*/
4690         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4691                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4692
4693         /* 1 second timeout*/
4694         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4695                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4696
4697         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4698
4699         /* Leaning on the below call to gen6_set_rps to program/setup the
4700          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4701          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4702         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4703         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4704
4705         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4706 }
4707
4708 static void gen9_enable_rc6(struct drm_device *dev)
4709 {
4710         struct drm_i915_private *dev_priv = dev->dev_private;
4711         struct intel_engine_cs *ring;
4712         uint32_t rc6_mask = 0;
4713         int unused;
4714
4715         /* 1a: Software RC state - RC0 */
4716         I915_WRITE(GEN6_RC_STATE, 0);
4717
4718         /* 1b: Get forcewake during program sequence. Although the driver
4719          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4720         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4721
4722         /* 2a: Disable RC states. */
4723         I915_WRITE(GEN6_RC_CONTROL, 0);
4724
4725         /* 2b: Program RC6 thresholds.*/
4726
4727         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4728         if (IS_SKYLAKE(dev))
4729                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4730         else
4731                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4732         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4733         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4734         for_each_ring(ring, dev_priv, unused)
4735                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4736
4737         if (HAS_GUC_UCODE(dev))
4738                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4739
4740         I915_WRITE(GEN6_RC_SLEEP, 0);
4741
4742         /* 2c: Program Coarse Power Gating Policies. */
4743         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4744         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4745
4746         /* 3a: Enable RC6 */
4747         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4748                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4749         DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4750         /* WaRsUseTimeoutMode */
4751         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
4752             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4753                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4754                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4755                            GEN7_RC_CTL_TO_MODE |
4756                            rc6_mask);
4757         } else {
4758                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4759                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4760                            GEN6_RC_CTL_EI_MODE(1) |
4761                            rc6_mask);
4762         }
4763
4764         /*
4765          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4766          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4767          */
4768         if (NEEDS_WaRsDisableCoarsePowerGating(dev))
4769                 I915_WRITE(GEN9_PG_ENABLE, 0);
4770         else
4771                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4772                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4773
4774         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4775
4776 }
4777
4778 static void gen8_enable_rps(struct drm_device *dev)
4779 {
4780         struct drm_i915_private *dev_priv = dev->dev_private;
4781         struct intel_engine_cs *ring;
4782         uint32_t rc6_mask = 0;
4783         int unused;
4784
4785         /* 1a: Software RC state - RC0 */
4786         I915_WRITE(GEN6_RC_STATE, 0);
4787
4788         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4789          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4790         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4791
4792         /* 2a: Disable RC states. */
4793         I915_WRITE(GEN6_RC_CONTROL, 0);
4794
4795         /* Initialize rps frequencies */
4796         gen6_init_rps_frequencies(dev);
4797
4798         /* 2b: Program RC6 thresholds.*/
4799         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4800         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4801         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4802         for_each_ring(ring, dev_priv, unused)
4803                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4804         I915_WRITE(GEN6_RC_SLEEP, 0);
4805         if (IS_BROADWELL(dev))
4806                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4807         else
4808                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4809
4810         /* 3: Enable RC6 */
4811         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4812                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4813         intel_print_rc6_info(dev, rc6_mask);
4814         if (IS_BROADWELL(dev))
4815                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4816                                 GEN7_RC_CTL_TO_MODE |
4817                                 rc6_mask);
4818         else
4819                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4820                                 GEN6_RC_CTL_EI_MODE(1) |
4821                                 rc6_mask);
4822
4823         /* 4 Program defaults and thresholds for RPS*/
4824         I915_WRITE(GEN6_RPNSWREQ,
4825                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4826         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4827                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4828         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4829         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4830
4831         /* Docs recommend 900MHz, and 300 MHz respectively */
4832         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4833                    dev_priv->rps.max_freq_softlimit << 24 |
4834                    dev_priv->rps.min_freq_softlimit << 16);
4835
4836         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4837         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4838         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4839         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4840
4841         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4842
4843         /* 5: Enable RPS */
4844         I915_WRITE(GEN6_RP_CONTROL,
4845                    GEN6_RP_MEDIA_TURBO |
4846                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4847                    GEN6_RP_MEDIA_IS_GFX |
4848                    GEN6_RP_ENABLE |
4849                    GEN6_RP_UP_BUSY_AVG |
4850                    GEN6_RP_DOWN_IDLE_AVG);
4851
4852         /* 6: Ring frequency + overclocking (our driver does this later */
4853
4854         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4855         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4856
4857         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4858 }
4859
4860 static void gen6_enable_rps(struct drm_device *dev)
4861 {
4862         struct drm_i915_private *dev_priv = dev->dev_private;
4863         struct intel_engine_cs *ring;
4864         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4865         u32 gtfifodbg;
4866         int rc6_mode;
4867         int i, ret;
4868
4869         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4870
4871         /* Here begins a magic sequence of register writes to enable
4872          * auto-downclocking.
4873          *
4874          * Perhaps there might be some value in exposing these to
4875          * userspace...
4876          */
4877         I915_WRITE(GEN6_RC_STATE, 0);
4878
4879         /* Clear the DBG now so we don't confuse earlier errors */
4880         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4881                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4882                 I915_WRITE(GTFIFODBG, gtfifodbg);
4883         }
4884
4885         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4886
4887         /* Initialize rps frequencies */
4888         gen6_init_rps_frequencies(dev);
4889
4890         /* disable the counters and set deterministic thresholds */
4891         I915_WRITE(GEN6_RC_CONTROL, 0);
4892
4893         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4894         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4895         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4896         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4897         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4898
4899         for_each_ring(ring, dev_priv, i)
4900                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4901
4902         I915_WRITE(GEN6_RC_SLEEP, 0);
4903         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4904         if (IS_IVYBRIDGE(dev))
4905                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4906         else
4907                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4908         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4909         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4910
4911         /* Check if we are enabling RC6 */
4912         rc6_mode = intel_enable_rc6(dev_priv->dev);
4913         if (rc6_mode & INTEL_RC6_ENABLE)
4914                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4915
4916         /* We don't use those on Haswell */
4917         if (!IS_HASWELL(dev)) {
4918                 if (rc6_mode & INTEL_RC6p_ENABLE)
4919                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4920
4921                 if (rc6_mode & INTEL_RC6pp_ENABLE)
4922                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4923         }
4924
4925         intel_print_rc6_info(dev, rc6_mask);
4926
4927         I915_WRITE(GEN6_RC_CONTROL,
4928                    rc6_mask |
4929                    GEN6_RC_CTL_EI_MODE(1) |
4930                    GEN6_RC_CTL_HW_ENABLE);
4931
4932         /* Power down if completely idle for over 50ms */
4933         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4934         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4935
4936         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4937         if (ret)
4938                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4939
4940         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4941         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4942                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4943                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4944                                  (pcu_mbox & 0xff) * 50);
4945                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4946         }
4947
4948         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4949         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4950
4951         rc6vids = 0;
4952         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4953         if (IS_GEN6(dev) && ret) {
4954                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4955         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4956                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4957                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4958                 rc6vids &= 0xffff00;
4959                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4960                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4961                 if (ret)
4962                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4963         }
4964
4965         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4966 }
4967
4968 static void __gen6_update_ring_freq(struct drm_device *dev)
4969 {
4970         struct drm_i915_private *dev_priv = dev->dev_private;
4971         int min_freq = 15;
4972         unsigned int gpu_freq;
4973         unsigned int max_ia_freq, min_ring_freq;
4974         unsigned int max_gpu_freq, min_gpu_freq;
4975         int scaling_factor = 180;
4976         struct cpufreq_policy *policy;
4977
4978         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4979
4980         policy = cpufreq_cpu_get(0);
4981         if (policy) {
4982                 max_ia_freq = policy->cpuinfo.max_freq;
4983                 cpufreq_cpu_put(policy);
4984         } else {
4985                 /*
4986                  * Default to measured freq if none found, PCU will ensure we
4987                  * don't go over
4988                  */
4989                 max_ia_freq = tsc_khz;
4990         }
4991
4992         /* Convert from kHz to MHz */
4993         max_ia_freq /= 1000;
4994
4995         min_ring_freq = I915_READ(DCLK) & 0xf;
4996         /* convert DDR frequency from units of 266.6MHz to bandwidth */
4997         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4998
4999         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5000                 /* Convert GT frequency to 50 HZ units */
5001                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5002                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5003         } else {
5004                 min_gpu_freq = dev_priv->rps.min_freq;
5005                 max_gpu_freq = dev_priv->rps.max_freq;
5006         }
5007
5008         /*
5009          * For each potential GPU frequency, load a ring frequency we'd like
5010          * to use for memory access.  We do this by specifying the IA frequency
5011          * the PCU should use as a reference to determine the ring frequency.
5012          */
5013         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5014                 int diff = max_gpu_freq - gpu_freq;
5015                 unsigned int ia_freq = 0, ring_freq = 0;
5016
5017                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5018                         /*
5019                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
5020                          * No floor required for ring frequency on SKL.
5021                          */
5022                         ring_freq = gpu_freq;
5023                 } else if (INTEL_INFO(dev)->gen >= 8) {
5024                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
5025                         ring_freq = max(min_ring_freq, gpu_freq);
5026                 } else if (IS_HASWELL(dev)) {
5027                         ring_freq = mult_frac(gpu_freq, 5, 4);
5028                         ring_freq = max(min_ring_freq, ring_freq);
5029                         /* leave ia_freq as the default, chosen by cpufreq */
5030                 } else {
5031                         /* On older processors, there is no separate ring
5032                          * clock domain, so in order to boost the bandwidth
5033                          * of the ring, we need to upclock the CPU (ia_freq).
5034                          *
5035                          * For GPU frequencies less than 750MHz,
5036                          * just use the lowest ring freq.
5037                          */
5038                         if (gpu_freq < min_freq)
5039                                 ia_freq = 800;
5040                         else
5041                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5042                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5043                 }
5044
5045                 sandybridge_pcode_write(dev_priv,
5046                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
5047                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5048                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5049                                         gpu_freq);
5050         }
5051 }
5052
5053 void gen6_update_ring_freq(struct drm_device *dev)
5054 {
5055         struct drm_i915_private *dev_priv = dev->dev_private;
5056
5057         if (!HAS_CORE_RING_FREQ(dev))
5058                 return;
5059
5060         mutex_lock(&dev_priv->rps.hw_lock);
5061         __gen6_update_ring_freq(dev);
5062         mutex_unlock(&dev_priv->rps.hw_lock);
5063 }
5064
5065 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5066 {
5067         struct drm_device *dev = dev_priv->dev;
5068         u32 val, rp0;
5069
5070         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5071
5072         switch (INTEL_INFO(dev)->eu_total) {
5073         case 8:
5074                 /* (2 * 4) config */
5075                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5076                 break;
5077         case 12:
5078                 /* (2 * 6) config */
5079                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5080                 break;
5081         case 16:
5082                 /* (2 * 8) config */
5083         default:
5084                 /* Setting (2 * 8) Min RP0 for any other combination */
5085                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5086                 break;
5087         }
5088
5089         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5090
5091         return rp0;
5092 }
5093
5094 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5095 {
5096         u32 val, rpe;
5097
5098         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5099         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5100
5101         return rpe;
5102 }
5103
5104 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5105 {
5106         u32 val, rp1;
5107
5108         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5109         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5110
5111         return rp1;
5112 }
5113
5114 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5115 {
5116         u32 val, rp1;
5117
5118         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5119
5120         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5121
5122         return rp1;
5123 }
5124
5125 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5126 {
5127         u32 val, rp0;
5128
5129         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5130
5131         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5132         /* Clamp to max */
5133         rp0 = min_t(u32, rp0, 0xea);
5134
5135         return rp0;
5136 }
5137
5138 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5139 {
5140         u32 val, rpe;
5141
5142         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5143         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5144         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5145         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5146
5147         return rpe;
5148 }
5149
5150 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5151 {
5152         u32 val;
5153
5154         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5155         /*
5156          * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5157          * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5158          * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5159          * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5160          * to make sure it matches what Punit accepts.
5161          */
5162         return max_t(u32, val, 0xc0);
5163 }
5164
5165 /* Check that the pctx buffer wasn't move under us. */
5166 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5167 {
5168         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5169
5170         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5171                              dev_priv->vlv_pctx->stolen->start);
5172 }
5173
5174
5175 /* Check that the pcbr address is not empty. */
5176 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5177 {
5178         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5179
5180         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5181 }
5182
5183 static void cherryview_setup_pctx(struct drm_device *dev)
5184 {
5185         struct drm_i915_private *dev_priv = dev->dev_private;
5186         unsigned long pctx_paddr, paddr;
5187         struct i915_gtt *gtt = &dev_priv->gtt;
5188         u32 pcbr;
5189         int pctx_size = 32*1024;
5190
5191         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5192
5193         pcbr = I915_READ(VLV_PCBR);
5194         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5195                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5196                 paddr = (dev_priv->mm.stolen_base +
5197                          (gtt->stolen_size - pctx_size));
5198
5199                 pctx_paddr = (paddr & (~4095));
5200                 I915_WRITE(VLV_PCBR, pctx_paddr);
5201         }
5202
5203         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5204 }
5205
5206 static void valleyview_setup_pctx(struct drm_device *dev)
5207 {
5208         struct drm_i915_private *dev_priv = dev->dev_private;
5209         struct drm_i915_gem_object *pctx;
5210         unsigned long pctx_paddr;
5211         u32 pcbr;
5212         int pctx_size = 24*1024;
5213
5214         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5215
5216         pcbr = I915_READ(VLV_PCBR);
5217         if (pcbr) {
5218                 /* BIOS set it up already, grab the pre-alloc'd space */
5219                 int pcbr_offset;
5220
5221                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5222                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5223                                                                       pcbr_offset,
5224                                                                       I915_GTT_OFFSET_NONE,
5225                                                                       pctx_size);
5226                 goto out;
5227         }
5228
5229         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5230
5231         /*
5232          * From the Gunit register HAS:
5233          * The Gfx driver is expected to program this register and ensure
5234          * proper allocation within Gfx stolen memory.  For example, this
5235          * register should be programmed such than the PCBR range does not
5236          * overlap with other ranges, such as the frame buffer, protected
5237          * memory, or any other relevant ranges.
5238          */
5239         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5240         if (!pctx) {
5241                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5242                 return;
5243         }
5244
5245         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5246         I915_WRITE(VLV_PCBR, pctx_paddr);
5247
5248 out:
5249         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5250         dev_priv->vlv_pctx = pctx;
5251 }
5252
5253 static void valleyview_cleanup_pctx(struct drm_device *dev)
5254 {
5255         struct drm_i915_private *dev_priv = dev->dev_private;
5256
5257         if (WARN_ON(!dev_priv->vlv_pctx))
5258                 return;
5259
5260         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5261         dev_priv->vlv_pctx = NULL;
5262 }
5263
5264 static void valleyview_init_gt_powersave(struct drm_device *dev)
5265 {
5266         struct drm_i915_private *dev_priv = dev->dev_private;
5267         u32 val;
5268
5269         valleyview_setup_pctx(dev);
5270
5271         mutex_lock(&dev_priv->rps.hw_lock);
5272
5273         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5274         switch ((val >> 6) & 3) {
5275         case 0:
5276         case 1:
5277                 dev_priv->mem_freq = 800;
5278                 break;
5279         case 2:
5280                 dev_priv->mem_freq = 1066;
5281                 break;
5282         case 3:
5283                 dev_priv->mem_freq = 1333;
5284                 break;
5285         }
5286         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5287
5288         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5289         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5290         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5291                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5292                          dev_priv->rps.max_freq);
5293
5294         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5295         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5296                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5297                          dev_priv->rps.efficient_freq);
5298
5299         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5300         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5301                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5302                          dev_priv->rps.rp1_freq);
5303
5304         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5305         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5306                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5307                          dev_priv->rps.min_freq);
5308
5309         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5310
5311         /* Preserve min/max settings in case of re-init */
5312         if (dev_priv->rps.max_freq_softlimit == 0)
5313                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5314
5315         if (dev_priv->rps.min_freq_softlimit == 0)
5316                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5317
5318         mutex_unlock(&dev_priv->rps.hw_lock);
5319 }
5320
5321 static void cherryview_init_gt_powersave(struct drm_device *dev)
5322 {
5323         struct drm_i915_private *dev_priv = dev->dev_private;
5324         u32 val;
5325
5326         cherryview_setup_pctx(dev);
5327
5328         mutex_lock(&dev_priv->rps.hw_lock);
5329
5330         mutex_lock(&dev_priv->sb_lock);
5331         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5332         mutex_unlock(&dev_priv->sb_lock);
5333
5334         switch ((val >> 2) & 0x7) {
5335         case 3:
5336                 dev_priv->mem_freq = 2000;
5337                 break;
5338         default:
5339                 dev_priv->mem_freq = 1600;
5340                 break;
5341         }
5342         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5343
5344         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5345         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5346         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5347                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5348                          dev_priv->rps.max_freq);
5349
5350         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5351         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5352                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5353                          dev_priv->rps.efficient_freq);
5354
5355         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5356         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5357                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5358                          dev_priv->rps.rp1_freq);
5359
5360         /* PUnit validated range is only [RPe, RP0] */
5361         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5362         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5363                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5364                          dev_priv->rps.min_freq);
5365
5366         WARN_ONCE((dev_priv->rps.max_freq |
5367                    dev_priv->rps.efficient_freq |
5368                    dev_priv->rps.rp1_freq |
5369                    dev_priv->rps.min_freq) & 1,
5370                   "Odd GPU freq values\n");
5371
5372         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5373
5374         /* Preserve min/max settings in case of re-init */
5375         if (dev_priv->rps.max_freq_softlimit == 0)
5376                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5377
5378         if (dev_priv->rps.min_freq_softlimit == 0)
5379                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5380
5381         mutex_unlock(&dev_priv->rps.hw_lock);
5382 }
5383
5384 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5385 {
5386         valleyview_cleanup_pctx(dev);
5387 }
5388
5389 static void cherryview_enable_rps(struct drm_device *dev)
5390 {
5391         struct drm_i915_private *dev_priv = dev->dev_private;
5392         struct intel_engine_cs *ring;
5393         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5394         int i;
5395
5396         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5397
5398         gtfifodbg = I915_READ(GTFIFODBG);
5399         if (gtfifodbg) {
5400                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5401                                  gtfifodbg);
5402                 I915_WRITE(GTFIFODBG, gtfifodbg);
5403         }
5404
5405         cherryview_check_pctx(dev_priv);
5406
5407         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5408          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5409         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5410
5411         /*  Disable RC states. */
5412         I915_WRITE(GEN6_RC_CONTROL, 0);
5413
5414         /* 2a: Program RC6 thresholds.*/
5415         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5416         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5417         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5418
5419         for_each_ring(ring, dev_priv, i)
5420                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5421         I915_WRITE(GEN6_RC_SLEEP, 0);
5422
5423         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5424         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5425
5426         /* allows RC6 residency counter to work */
5427         I915_WRITE(VLV_COUNTER_CONTROL,
5428                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5429                                       VLV_MEDIA_RC6_COUNT_EN |
5430                                       VLV_RENDER_RC6_COUNT_EN));
5431
5432         /* For now we assume BIOS is allocating and populating the PCBR  */
5433         pcbr = I915_READ(VLV_PCBR);
5434
5435         /* 3: Enable RC6 */
5436         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5437                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5438                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5439
5440         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5441
5442         /* 4 Program defaults and thresholds for RPS*/
5443         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5444         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5445         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5446         I915_WRITE(GEN6_RP_UP_EI, 66000);
5447         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5448
5449         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5450
5451         /* 5: Enable RPS */
5452         I915_WRITE(GEN6_RP_CONTROL,
5453                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5454                    GEN6_RP_MEDIA_IS_GFX |
5455                    GEN6_RP_ENABLE |
5456                    GEN6_RP_UP_BUSY_AVG |
5457                    GEN6_RP_DOWN_IDLE_AVG);
5458
5459         /* Setting Fixed Bias */
5460         val = VLV_OVERRIDE_EN |
5461                   VLV_SOC_TDP_EN |
5462                   CHV_BIAS_CPU_50_SOC_50;
5463         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5464
5465         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5466
5467         /* RPS code assumes GPLL is used */
5468         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5469
5470         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5471         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5472
5473         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5474         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5475                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5476                          dev_priv->rps.cur_freq);
5477
5478         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5479                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5480                          dev_priv->rps.efficient_freq);
5481
5482         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5483
5484         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5485 }
5486
5487 static void valleyview_enable_rps(struct drm_device *dev)
5488 {
5489         struct drm_i915_private *dev_priv = dev->dev_private;
5490         struct intel_engine_cs *ring;
5491         u32 gtfifodbg, val, rc6_mode = 0;
5492         int i;
5493
5494         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5495
5496         valleyview_check_pctx(dev_priv);
5497
5498         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5499                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5500                                  gtfifodbg);
5501                 I915_WRITE(GTFIFODBG, gtfifodbg);
5502         }
5503
5504         /* If VLV, Forcewake all wells, else re-direct to regular path */
5505         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5506
5507         /*  Disable RC states. */
5508         I915_WRITE(GEN6_RC_CONTROL, 0);
5509
5510         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5511         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5512         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5513         I915_WRITE(GEN6_RP_UP_EI, 66000);
5514         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5515
5516         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5517
5518         I915_WRITE(GEN6_RP_CONTROL,
5519                    GEN6_RP_MEDIA_TURBO |
5520                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5521                    GEN6_RP_MEDIA_IS_GFX |
5522                    GEN6_RP_ENABLE |
5523                    GEN6_RP_UP_BUSY_AVG |
5524                    GEN6_RP_DOWN_IDLE_CONT);
5525
5526         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5527         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5528         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5529
5530         for_each_ring(ring, dev_priv, i)
5531                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5532
5533         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5534
5535         /* allows RC6 residency counter to work */
5536         I915_WRITE(VLV_COUNTER_CONTROL,
5537                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5538                                       VLV_RENDER_RC0_COUNT_EN |
5539                                       VLV_MEDIA_RC6_COUNT_EN |
5540                                       VLV_RENDER_RC6_COUNT_EN));
5541
5542         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5543                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5544
5545         intel_print_rc6_info(dev, rc6_mode);
5546
5547         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5548
5549         /* Setting Fixed Bias */
5550         val = VLV_OVERRIDE_EN |
5551                   VLV_SOC_TDP_EN |
5552                   VLV_BIAS_CPU_125_SOC_875;
5553         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5554
5555         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5556
5557         /* RPS code assumes GPLL is used */
5558         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5559
5560         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5561         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5562
5563         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5564         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5565                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5566                          dev_priv->rps.cur_freq);
5567
5568         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5569                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5570                          dev_priv->rps.efficient_freq);
5571
5572         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5573
5574         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5575 }
5576
5577 static unsigned long intel_pxfreq(u32 vidfreq)
5578 {
5579         unsigned long freq;
5580         int div = (vidfreq & 0x3f0000) >> 16;
5581         int post = (vidfreq & 0x3000) >> 12;
5582         int pre = (vidfreq & 0x7);
5583
5584         if (!pre)
5585                 return 0;
5586
5587         freq = ((div * 133333) / ((1<<post) * pre));
5588
5589         return freq;
5590 }
5591
5592 static const struct cparams {
5593         u16 i;
5594         u16 t;
5595         u16 m;
5596         u16 c;
5597 } cparams[] = {
5598         { 1, 1333, 301, 28664 },
5599         { 1, 1066, 294, 24460 },
5600         { 1, 800, 294, 25192 },
5601         { 0, 1333, 276, 27605 },
5602         { 0, 1066, 276, 27605 },
5603         { 0, 800, 231, 23784 },
5604 };
5605
5606 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5607 {
5608         u64 total_count, diff, ret;
5609         u32 count1, count2, count3, m = 0, c = 0;
5610         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5611         int i;
5612
5613         assert_spin_locked(&mchdev_lock);
5614
5615         diff1 = now - dev_priv->ips.last_time1;
5616
5617         /* Prevent division-by-zero if we are asking too fast.
5618          * Also, we don't get interesting results if we are polling
5619          * faster than once in 10ms, so just return the saved value
5620          * in such cases.
5621          */
5622         if (diff1 <= 10)
5623                 return dev_priv->ips.chipset_power;
5624
5625         count1 = I915_READ(DMIEC);
5626         count2 = I915_READ(DDREC);
5627         count3 = I915_READ(CSIEC);
5628
5629         total_count = count1 + count2 + count3;
5630
5631         /* FIXME: handle per-counter overflow */
5632         if (total_count < dev_priv->ips.last_count1) {
5633                 diff = ~0UL - dev_priv->ips.last_count1;
5634                 diff += total_count;
5635         } else {
5636                 diff = total_count - dev_priv->ips.last_count1;
5637         }
5638
5639         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5640                 if (cparams[i].i == dev_priv->ips.c_m &&
5641                     cparams[i].t == dev_priv->ips.r_t) {
5642                         m = cparams[i].m;
5643                         c = cparams[i].c;
5644                         break;
5645                 }
5646         }
5647
5648         diff = div_u64(diff, diff1);
5649         ret = ((m * diff) + c);
5650         ret = div_u64(ret, 10);
5651
5652         dev_priv->ips.last_count1 = total_count;
5653         dev_priv->ips.last_time1 = now;
5654
5655         dev_priv->ips.chipset_power = ret;
5656
5657         return ret;
5658 }
5659
5660 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5661 {
5662         struct drm_device *dev = dev_priv->dev;
5663         unsigned long val;
5664
5665         if (INTEL_INFO(dev)->gen != 5)
5666                 return 0;
5667
5668         spin_lock_irq(&mchdev_lock);
5669
5670         val = __i915_chipset_val(dev_priv);
5671
5672         spin_unlock_irq(&mchdev_lock);
5673
5674         return val;
5675 }
5676
5677 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5678 {
5679         unsigned long m, x, b;
5680         u32 tsfs;
5681
5682         tsfs = I915_READ(TSFS);
5683
5684         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5685         x = I915_READ8(TR1);
5686
5687         b = tsfs & TSFS_INTR_MASK;
5688
5689         return ((m * x) / 127) - b;
5690 }
5691
5692 static int _pxvid_to_vd(u8 pxvid)
5693 {
5694         if (pxvid == 0)
5695                 return 0;
5696
5697         if (pxvid >= 8 && pxvid < 31)
5698                 pxvid = 31;
5699
5700         return (pxvid + 2) * 125;
5701 }
5702
5703 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5704 {
5705         struct drm_device *dev = dev_priv->dev;
5706         const int vd = _pxvid_to_vd(pxvid);
5707         const int vm = vd - 1125;
5708
5709         if (INTEL_INFO(dev)->is_mobile)
5710                 return vm > 0 ? vm : 0;
5711
5712         return vd;
5713 }
5714
5715 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5716 {
5717         u64 now, diff, diffms;
5718         u32 count;
5719
5720         assert_spin_locked(&mchdev_lock);
5721
5722         now = ktime_get_raw_ns();
5723         diffms = now - dev_priv->ips.last_time2;
5724         do_div(diffms, NSEC_PER_MSEC);
5725
5726         /* Don't divide by 0 */
5727         if (!diffms)
5728                 return;
5729
5730         count = I915_READ(GFXEC);
5731
5732         if (count < dev_priv->ips.last_count2) {
5733                 diff = ~0UL - dev_priv->ips.last_count2;
5734                 diff += count;
5735         } else {
5736                 diff = count - dev_priv->ips.last_count2;
5737         }
5738
5739         dev_priv->ips.last_count2 = count;
5740         dev_priv->ips.last_time2 = now;
5741
5742         /* More magic constants... */
5743         diff = diff * 1181;
5744         diff = div_u64(diff, diffms * 10);
5745         dev_priv->ips.gfx_power = diff;
5746 }
5747
5748 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5749 {
5750         struct drm_device *dev = dev_priv->dev;
5751
5752         if (INTEL_INFO(dev)->gen != 5)
5753                 return;
5754
5755         spin_lock_irq(&mchdev_lock);
5756
5757         __i915_update_gfx_val(dev_priv);
5758
5759         spin_unlock_irq(&mchdev_lock);
5760 }
5761
5762 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5763 {
5764         unsigned long t, corr, state1, corr2, state2;
5765         u32 pxvid, ext_v;
5766
5767         assert_spin_locked(&mchdev_lock);
5768
5769         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5770         pxvid = (pxvid >> 24) & 0x7f;
5771         ext_v = pvid_to_extvid(dev_priv, pxvid);
5772
5773         state1 = ext_v;
5774
5775         t = i915_mch_val(dev_priv);
5776
5777         /* Revel in the empirically derived constants */
5778
5779         /* Correction factor in 1/100000 units */
5780         if (t > 80)
5781                 corr = ((t * 2349) + 135940);
5782         else if (t >= 50)
5783                 corr = ((t * 964) + 29317);
5784         else /* < 50 */
5785                 corr = ((t * 301) + 1004);
5786
5787         corr = corr * ((150142 * state1) / 10000 - 78642);
5788         corr /= 100000;
5789         corr2 = (corr * dev_priv->ips.corr);
5790
5791         state2 = (corr2 * state1) / 10000;
5792         state2 /= 100; /* convert to mW */
5793
5794         __i915_update_gfx_val(dev_priv);
5795
5796         return dev_priv->ips.gfx_power + state2;
5797 }
5798
5799 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5800 {
5801         struct drm_device *dev = dev_priv->dev;
5802         unsigned long val;
5803
5804         if (INTEL_INFO(dev)->gen != 5)
5805                 return 0;
5806
5807         spin_lock_irq(&mchdev_lock);
5808
5809         val = __i915_gfx_val(dev_priv);
5810
5811         spin_unlock_irq(&mchdev_lock);
5812
5813         return val;
5814 }
5815
5816 /**
5817  * i915_read_mch_val - return value for IPS use
5818  *
5819  * Calculate and return a value for the IPS driver to use when deciding whether
5820  * we have thermal and power headroom to increase CPU or GPU power budget.
5821  */
5822 unsigned long i915_read_mch_val(void)
5823 {
5824         struct drm_i915_private *dev_priv;
5825         unsigned long chipset_val, graphics_val, ret = 0;
5826
5827         spin_lock_irq(&mchdev_lock);
5828         if (!i915_mch_dev)
5829                 goto out_unlock;
5830         dev_priv = i915_mch_dev;
5831
5832         chipset_val = __i915_chipset_val(dev_priv);
5833         graphics_val = __i915_gfx_val(dev_priv);
5834
5835         ret = chipset_val + graphics_val;
5836
5837 out_unlock:
5838         spin_unlock_irq(&mchdev_lock);
5839
5840         return ret;
5841 }
5842 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5843
5844 /**
5845  * i915_gpu_raise - raise GPU frequency limit
5846  *
5847  * Raise the limit; IPS indicates we have thermal headroom.
5848  */
5849 bool i915_gpu_raise(void)
5850 {
5851         struct drm_i915_private *dev_priv;
5852         bool ret = true;
5853
5854         spin_lock_irq(&mchdev_lock);
5855         if (!i915_mch_dev) {
5856                 ret = false;
5857                 goto out_unlock;
5858         }
5859         dev_priv = i915_mch_dev;
5860
5861         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5862                 dev_priv->ips.max_delay--;
5863
5864 out_unlock:
5865         spin_unlock_irq(&mchdev_lock);
5866
5867         return ret;
5868 }
5869 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5870
5871 /**
5872  * i915_gpu_lower - lower GPU frequency limit
5873  *
5874  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5875  * frequency maximum.
5876  */
5877 bool i915_gpu_lower(void)
5878 {
5879         struct drm_i915_private *dev_priv;
5880         bool ret = true;
5881
5882         spin_lock_irq(&mchdev_lock);
5883         if (!i915_mch_dev) {
5884                 ret = false;
5885                 goto out_unlock;
5886         }
5887         dev_priv = i915_mch_dev;
5888
5889         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5890                 dev_priv->ips.max_delay++;
5891
5892 out_unlock:
5893         spin_unlock_irq(&mchdev_lock);
5894
5895         return ret;
5896 }
5897 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5898
5899 /**
5900  * i915_gpu_busy - indicate GPU business to IPS
5901  *
5902  * Tell the IPS driver whether or not the GPU is busy.
5903  */
5904 bool i915_gpu_busy(void)
5905 {
5906         struct drm_i915_private *dev_priv;
5907         struct intel_engine_cs *ring;
5908         bool ret = false;
5909         int i;
5910
5911         spin_lock_irq(&mchdev_lock);
5912         if (!i915_mch_dev)
5913                 goto out_unlock;
5914         dev_priv = i915_mch_dev;
5915
5916         for_each_ring(ring, dev_priv, i)
5917                 ret |= !list_empty(&ring->request_list);
5918
5919 out_unlock:
5920         spin_unlock_irq(&mchdev_lock);
5921
5922         return ret;
5923 }
5924 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5925
5926 /**
5927  * i915_gpu_turbo_disable - disable graphics turbo
5928  *
5929  * Disable graphics turbo by resetting the max frequency and setting the
5930  * current frequency to the default.
5931  */
5932 bool i915_gpu_turbo_disable(void)
5933 {
5934         struct drm_i915_private *dev_priv;
5935         bool ret = true;
5936
5937         spin_lock_irq(&mchdev_lock);
5938         if (!i915_mch_dev) {
5939                 ret = false;
5940                 goto out_unlock;
5941         }
5942         dev_priv = i915_mch_dev;
5943
5944         dev_priv->ips.max_delay = dev_priv->ips.fstart;
5945
5946         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5947                 ret = false;
5948
5949 out_unlock:
5950         spin_unlock_irq(&mchdev_lock);
5951
5952         return ret;
5953 }
5954 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5955
5956 /**
5957  * Tells the intel_ips driver that the i915 driver is now loaded, if
5958  * IPS got loaded first.
5959  *
5960  * This awkward dance is so that neither module has to depend on the
5961  * other in order for IPS to do the appropriate communication of
5962  * GPU turbo limits to i915.
5963  */
5964 static void
5965 ips_ping_for_i915_load(void)
5966 {
5967         void (*link)(void);
5968
5969         link = symbol_get(ips_link_to_i915_driver);
5970         if (link) {
5971                 link();
5972                 symbol_put(ips_link_to_i915_driver);
5973         }
5974 }
5975
5976 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5977 {
5978         /* We only register the i915 ips part with intel-ips once everything is
5979          * set up, to avoid intel-ips sneaking in and reading bogus values. */
5980         spin_lock_irq(&mchdev_lock);
5981         i915_mch_dev = dev_priv;
5982         spin_unlock_irq(&mchdev_lock);
5983
5984         ips_ping_for_i915_load();
5985 }
5986
5987 void intel_gpu_ips_teardown(void)
5988 {
5989         spin_lock_irq(&mchdev_lock);
5990         i915_mch_dev = NULL;
5991         spin_unlock_irq(&mchdev_lock);
5992 }
5993
5994 static void intel_init_emon(struct drm_device *dev)
5995 {
5996         struct drm_i915_private *dev_priv = dev->dev_private;
5997         u32 lcfuse;
5998         u8 pxw[16];
5999         int i;
6000
6001         /* Disable to program */
6002         I915_WRITE(ECR, 0);
6003         POSTING_READ(ECR);
6004
6005         /* Program energy weights for various events */
6006         I915_WRITE(SDEW, 0x15040d00);
6007         I915_WRITE(CSIEW0, 0x007f0000);
6008         I915_WRITE(CSIEW1, 0x1e220004);
6009         I915_WRITE(CSIEW2, 0x04000004);
6010
6011         for (i = 0; i < 5; i++)
6012                 I915_WRITE(PEW(i), 0);
6013         for (i = 0; i < 3; i++)
6014                 I915_WRITE(DEW(i), 0);
6015
6016         /* Program P-state weights to account for frequency power adjustment */
6017         for (i = 0; i < 16; i++) {
6018                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
6019                 unsigned long freq = intel_pxfreq(pxvidfreq);
6020                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6021                         PXVFREQ_PX_SHIFT;
6022                 unsigned long val;
6023
6024                 val = vid * vid;
6025                 val *= (freq / 1000);
6026                 val *= 255;
6027                 val /= (127*127*900);
6028                 if (val > 0xff)
6029                         DRM_ERROR("bad pxval: %ld\n", val);
6030                 pxw[i] = val;
6031         }
6032         /* Render standby states get 0 weight */
6033         pxw[14] = 0;
6034         pxw[15] = 0;
6035
6036         for (i = 0; i < 4; i++) {
6037                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6038                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6039                 I915_WRITE(PXW(i), val);
6040         }
6041
6042         /* Adjust magic regs to magic values (more experimental results) */
6043         I915_WRITE(OGW0, 0);
6044         I915_WRITE(OGW1, 0);
6045         I915_WRITE(EG0, 0x00007f00);
6046         I915_WRITE(EG1, 0x0000000e);
6047         I915_WRITE(EG2, 0x000e0000);
6048         I915_WRITE(EG3, 0x68000300);
6049         I915_WRITE(EG4, 0x42000000);
6050         I915_WRITE(EG5, 0x00140031);
6051         I915_WRITE(EG6, 0);
6052         I915_WRITE(EG7, 0);
6053
6054         for (i = 0; i < 8; i++)
6055                 I915_WRITE(PXWL(i), 0);
6056
6057         /* Enable PMON + select events */
6058         I915_WRITE(ECR, 0x80000019);
6059
6060         lcfuse = I915_READ(LCFUSE02);
6061
6062         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
6063 }
6064
6065 void intel_init_gt_powersave(struct drm_device *dev)
6066 {
6067         struct drm_i915_private *dev_priv = dev->dev_private;
6068
6069         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6070         /*
6071          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6072          * requirement.
6073          */
6074         if (!i915.enable_rc6) {
6075                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6076                 intel_runtime_pm_get(dev_priv);
6077         }
6078
6079         if (IS_CHERRYVIEW(dev))
6080                 cherryview_init_gt_powersave(dev);
6081         else if (IS_VALLEYVIEW(dev))
6082                 valleyview_init_gt_powersave(dev);
6083 }
6084
6085 void intel_cleanup_gt_powersave(struct drm_device *dev)
6086 {
6087         struct drm_i915_private *dev_priv = dev->dev_private;
6088
6089         if (IS_CHERRYVIEW(dev))
6090                 return;
6091         else if (IS_VALLEYVIEW(dev))
6092                 valleyview_cleanup_gt_powersave(dev);
6093
6094         if (!i915.enable_rc6)
6095                 intel_runtime_pm_put(dev_priv);
6096 }
6097
6098 static void gen6_suspend_rps(struct drm_device *dev)
6099 {
6100         struct drm_i915_private *dev_priv = dev->dev_private;
6101
6102         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6103
6104         gen6_disable_rps_interrupts(dev);
6105 }
6106
6107 /**
6108  * intel_suspend_gt_powersave - suspend PM work and helper threads
6109  * @dev: drm device
6110  *
6111  * We don't want to disable RC6 or other features here, we just want
6112  * to make sure any work we've queued has finished and won't bother
6113  * us while we're suspended.
6114  */
6115 void intel_suspend_gt_powersave(struct drm_device *dev)
6116 {
6117         struct drm_i915_private *dev_priv = dev->dev_private;
6118
6119         if (INTEL_INFO(dev)->gen < 6)
6120                 return;
6121
6122         gen6_suspend_rps(dev);
6123
6124         /* Force GPU to min freq during suspend */
6125         gen6_rps_idle(dev_priv);
6126 }
6127
6128 void intel_disable_gt_powersave(struct drm_device *dev)
6129 {
6130         struct drm_i915_private *dev_priv = dev->dev_private;
6131
6132         if (IS_IRONLAKE_M(dev)) {
6133                 ironlake_disable_drps(dev);
6134         } else if (INTEL_INFO(dev)->gen >= 6) {
6135                 intel_suspend_gt_powersave(dev);
6136
6137                 mutex_lock(&dev_priv->rps.hw_lock);
6138                 if (INTEL_INFO(dev)->gen >= 9)
6139                         gen9_disable_rps(dev);
6140                 else if (IS_CHERRYVIEW(dev))
6141                         cherryview_disable_rps(dev);
6142                 else if (IS_VALLEYVIEW(dev))
6143                         valleyview_disable_rps(dev);
6144                 else
6145                         gen6_disable_rps(dev);
6146
6147                 dev_priv->rps.enabled = false;
6148                 mutex_unlock(&dev_priv->rps.hw_lock);
6149         }
6150 }
6151
6152 static void intel_gen6_powersave_work(struct work_struct *work)
6153 {
6154         struct drm_i915_private *dev_priv =
6155                 container_of(work, struct drm_i915_private,
6156                              rps.delayed_resume_work.work);
6157         struct drm_device *dev = dev_priv->dev;
6158
6159         mutex_lock(&dev_priv->rps.hw_lock);
6160
6161         gen6_reset_rps_interrupts(dev);
6162
6163         if (IS_CHERRYVIEW(dev)) {
6164                 cherryview_enable_rps(dev);
6165         } else if (IS_VALLEYVIEW(dev)) {
6166                 valleyview_enable_rps(dev);
6167         } else if (INTEL_INFO(dev)->gen >= 9) {
6168                 gen9_enable_rc6(dev);
6169                 gen9_enable_rps(dev);
6170                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
6171                         __gen6_update_ring_freq(dev);
6172         } else if (IS_BROADWELL(dev)) {
6173                 gen8_enable_rps(dev);
6174                 __gen6_update_ring_freq(dev);
6175         } else {
6176                 gen6_enable_rps(dev);
6177                 __gen6_update_ring_freq(dev);
6178         }
6179
6180         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6181         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6182
6183         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6184         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6185
6186         dev_priv->rps.enabled = true;
6187
6188         gen6_enable_rps_interrupts(dev);
6189
6190         mutex_unlock(&dev_priv->rps.hw_lock);
6191
6192         intel_runtime_pm_put(dev_priv);
6193 }
6194
6195 void intel_enable_gt_powersave(struct drm_device *dev)
6196 {
6197         struct drm_i915_private *dev_priv = dev->dev_private;
6198
6199         /* Powersaving is controlled by the host when inside a VM */
6200         if (intel_vgpu_active(dev))
6201                 return;
6202
6203         if (IS_IRONLAKE_M(dev)) {
6204                 mutex_lock(&dev->struct_mutex);
6205                 ironlake_enable_drps(dev);
6206                 intel_init_emon(dev);
6207                 mutex_unlock(&dev->struct_mutex);
6208         } else if (INTEL_INFO(dev)->gen >= 6) {
6209                 /*
6210                  * PCU communication is slow and this doesn't need to be
6211                  * done at any specific time, so do this out of our fast path
6212                  * to make resume and init faster.
6213                  *
6214                  * We depend on the HW RC6 power context save/restore
6215                  * mechanism when entering D3 through runtime PM suspend. So
6216                  * disable RPM until RPS/RC6 is properly setup. We can only
6217                  * get here via the driver load/system resume/runtime resume
6218                  * paths, so the _noresume version is enough (and in case of
6219                  * runtime resume it's necessary).
6220                  */
6221                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6222                                            round_jiffies_up_relative(HZ)))
6223                         intel_runtime_pm_get_noresume(dev_priv);
6224         }
6225 }
6226
6227 void intel_reset_gt_powersave(struct drm_device *dev)
6228 {
6229         struct drm_i915_private *dev_priv = dev->dev_private;
6230
6231         if (INTEL_INFO(dev)->gen < 6)
6232                 return;
6233
6234         gen6_suspend_rps(dev);
6235         dev_priv->rps.enabled = false;
6236 }
6237
6238 static void ibx_init_clock_gating(struct drm_device *dev)
6239 {
6240         struct drm_i915_private *dev_priv = dev->dev_private;
6241
6242         /*
6243          * On Ibex Peak and Cougar Point, we need to disable clock
6244          * gating for the panel power sequencer or it will fail to
6245          * start up when no ports are active.
6246          */
6247         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6248 }
6249
6250 static void g4x_disable_trickle_feed(struct drm_device *dev)
6251 {
6252         struct drm_i915_private *dev_priv = dev->dev_private;
6253         enum pipe pipe;
6254
6255         for_each_pipe(dev_priv, pipe) {
6256                 I915_WRITE(DSPCNTR(pipe),
6257                            I915_READ(DSPCNTR(pipe)) |
6258                            DISPPLANE_TRICKLE_FEED_DISABLE);
6259
6260                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6261                 POSTING_READ(DSPSURF(pipe));
6262         }
6263 }
6264
6265 static void ilk_init_lp_watermarks(struct drm_device *dev)
6266 {
6267         struct drm_i915_private *dev_priv = dev->dev_private;
6268
6269         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6270         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6271         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6272
6273         /*
6274          * Don't touch WM1S_LP_EN here.
6275          * Doing so could cause underruns.
6276          */
6277 }
6278
6279 static void ironlake_init_clock_gating(struct drm_device *dev)
6280 {
6281         struct drm_i915_private *dev_priv = dev->dev_private;
6282         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6283
6284         /*
6285          * Required for FBC
6286          * WaFbcDisableDpfcClockGating:ilk
6287          */
6288         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6289                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6290                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6291
6292         I915_WRITE(PCH_3DCGDIS0,
6293                    MARIUNIT_CLOCK_GATE_DISABLE |
6294                    SVSMUNIT_CLOCK_GATE_DISABLE);
6295         I915_WRITE(PCH_3DCGDIS1,
6296                    VFMUNIT_CLOCK_GATE_DISABLE);
6297
6298         /*
6299          * According to the spec the following bits should be set in
6300          * order to enable memory self-refresh
6301          * The bit 22/21 of 0x42004
6302          * The bit 5 of 0x42020
6303          * The bit 15 of 0x45000
6304          */
6305         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6306                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6307                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6308         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6309         I915_WRITE(DISP_ARB_CTL,
6310                    (I915_READ(DISP_ARB_CTL) |
6311                     DISP_FBC_WM_DIS));
6312
6313         ilk_init_lp_watermarks(dev);
6314
6315         /*
6316          * Based on the document from hardware guys the following bits
6317          * should be set unconditionally in order to enable FBC.
6318          * The bit 22 of 0x42000
6319          * The bit 22 of 0x42004
6320          * The bit 7,8,9 of 0x42020.
6321          */
6322         if (IS_IRONLAKE_M(dev)) {
6323                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6324                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6325                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6326                            ILK_FBCQ_DIS);
6327                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6328                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6329                            ILK_DPARB_GATE);
6330         }
6331
6332         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6333
6334         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6335                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6336                    ILK_ELPIN_409_SELECT);
6337         I915_WRITE(_3D_CHICKEN2,
6338                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6339                    _3D_CHICKEN2_WM_READ_PIPELINED);
6340
6341         /* WaDisableRenderCachePipelinedFlush:ilk */
6342         I915_WRITE(CACHE_MODE_0,
6343                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6344
6345         /* WaDisable_RenderCache_OperationalFlush:ilk */
6346         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6347
6348         g4x_disable_trickle_feed(dev);
6349
6350         ibx_init_clock_gating(dev);
6351 }
6352
6353 static void cpt_init_clock_gating(struct drm_device *dev)
6354 {
6355         struct drm_i915_private *dev_priv = dev->dev_private;
6356         int pipe;
6357         uint32_t val;
6358
6359         /*
6360          * On Ibex Peak and Cougar Point, we need to disable clock
6361          * gating for the panel power sequencer or it will fail to
6362          * start up when no ports are active.
6363          */
6364         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6365                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6366                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6367         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6368                    DPLS_EDP_PPS_FIX_DIS);
6369         /* The below fixes the weird display corruption, a few pixels shifted
6370          * downward, on (only) LVDS of some HP laptops with IVY.
6371          */
6372         for_each_pipe(dev_priv, pipe) {
6373                 val = I915_READ(TRANS_CHICKEN2(pipe));
6374                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6375                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6376                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6377                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6378                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6379                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6380                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6381                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6382         }
6383         /* WADP0ClockGatingDisable */
6384         for_each_pipe(dev_priv, pipe) {
6385                 I915_WRITE(TRANS_CHICKEN1(pipe),
6386                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6387         }
6388 }
6389
6390 static void gen6_check_mch_setup(struct drm_device *dev)
6391 {
6392         struct drm_i915_private *dev_priv = dev->dev_private;
6393         uint32_t tmp;
6394
6395         tmp = I915_READ(MCH_SSKPD);
6396         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6397                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6398                               tmp);
6399 }
6400
6401 static void gen6_init_clock_gating(struct drm_device *dev)
6402 {
6403         struct drm_i915_private *dev_priv = dev->dev_private;
6404         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6405
6406         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6407
6408         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6409                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6410                    ILK_ELPIN_409_SELECT);
6411
6412         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6413         I915_WRITE(_3D_CHICKEN,
6414                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6415
6416         /* WaDisable_RenderCache_OperationalFlush:snb */
6417         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6418
6419         /*
6420          * BSpec recoomends 8x4 when MSAA is used,
6421          * however in practice 16x4 seems fastest.
6422          *
6423          * Note that PS/WM thread counts depend on the WIZ hashing
6424          * disable bit, which we don't touch here, but it's good
6425          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6426          */
6427         I915_WRITE(GEN6_GT_MODE,
6428                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6429
6430         ilk_init_lp_watermarks(dev);
6431
6432         I915_WRITE(CACHE_MODE_0,
6433                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6434
6435         I915_WRITE(GEN6_UCGCTL1,
6436                    I915_READ(GEN6_UCGCTL1) |
6437                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6438                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6439
6440         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6441          * gating disable must be set.  Failure to set it results in
6442          * flickering pixels due to Z write ordering failures after
6443          * some amount of runtime in the Mesa "fire" demo, and Unigine
6444          * Sanctuary and Tropics, and apparently anything else with
6445          * alpha test or pixel discard.
6446          *
6447          * According to the spec, bit 11 (RCCUNIT) must also be set,
6448          * but we didn't debug actual testcases to find it out.
6449          *
6450          * WaDisableRCCUnitClockGating:snb
6451          * WaDisableRCPBUnitClockGating:snb
6452          */
6453         I915_WRITE(GEN6_UCGCTL2,
6454                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6455                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6456
6457         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6458         I915_WRITE(_3D_CHICKEN3,
6459                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6460
6461         /*
6462          * Bspec says:
6463          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6464          * 3DSTATE_SF number of SF output attributes is more than 16."
6465          */
6466         I915_WRITE(_3D_CHICKEN3,
6467                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6468
6469         /*
6470          * According to the spec the following bits should be
6471          * set in order to enable memory self-refresh and fbc:
6472          * The bit21 and bit22 of 0x42000
6473          * The bit21 and bit22 of 0x42004
6474          * The bit5 and bit7 of 0x42020
6475          * The bit14 of 0x70180
6476          * The bit14 of 0x71180
6477          *
6478          * WaFbcAsynchFlipDisableFbcQueue:snb
6479          */
6480         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6481                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6482                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6483         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6484                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6485                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6486         I915_WRITE(ILK_DSPCLK_GATE_D,
6487                    I915_READ(ILK_DSPCLK_GATE_D) |
6488                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6489                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6490
6491         g4x_disable_trickle_feed(dev);
6492
6493         cpt_init_clock_gating(dev);
6494
6495         gen6_check_mch_setup(dev);
6496 }
6497
6498 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6499 {
6500         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6501
6502         /*
6503          * WaVSThreadDispatchOverride:ivb,vlv
6504          *
6505          * This actually overrides the dispatch
6506          * mode for all thread types.
6507          */
6508         reg &= ~GEN7_FF_SCHED_MASK;
6509         reg |= GEN7_FF_TS_SCHED_HW;
6510         reg |= GEN7_FF_VS_SCHED_HW;
6511         reg |= GEN7_FF_DS_SCHED_HW;
6512
6513         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6514 }
6515
6516 static void lpt_init_clock_gating(struct drm_device *dev)
6517 {
6518         struct drm_i915_private *dev_priv = dev->dev_private;
6519
6520         /*
6521          * TODO: this bit should only be enabled when really needed, then
6522          * disabled when not needed anymore in order to save power.
6523          */
6524         if (HAS_PCH_LPT_LP(dev))
6525                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6526                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6527                            PCH_LP_PARTITION_LEVEL_DISABLE);
6528
6529         /* WADPOClockGatingDisable:hsw */
6530         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6531                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6532                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6533 }
6534
6535 static void lpt_suspend_hw(struct drm_device *dev)
6536 {
6537         struct drm_i915_private *dev_priv = dev->dev_private;
6538
6539         if (HAS_PCH_LPT_LP(dev)) {
6540                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6541
6542                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6543                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6544         }
6545 }
6546
6547 static void broadwell_init_clock_gating(struct drm_device *dev)
6548 {
6549         struct drm_i915_private *dev_priv = dev->dev_private;
6550         enum pipe pipe;
6551         uint32_t misccpctl;
6552
6553         ilk_init_lp_watermarks(dev);
6554
6555         /* WaSwitchSolVfFArbitrationPriority:bdw */
6556         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6557
6558         /* WaPsrDPAMaskVBlankInSRD:bdw */
6559         I915_WRITE(CHICKEN_PAR1_1,
6560                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6561
6562         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6563         for_each_pipe(dev_priv, pipe) {
6564                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6565                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6566                            BDW_DPRS_MASK_VBLANK_SRD);
6567         }
6568
6569         /* WaVSRefCountFullforceMissDisable:bdw */
6570         /* WaDSRefCountFullforceMissDisable:bdw */
6571         I915_WRITE(GEN7_FF_THREAD_MODE,
6572                    I915_READ(GEN7_FF_THREAD_MODE) &
6573                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6574
6575         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6576                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6577
6578         /* WaDisableSDEUnitClockGating:bdw */
6579         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6580                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6581
6582         /*
6583          * WaProgramL3SqcReg1Default:bdw
6584          * WaTempDisableDOPClkGating:bdw
6585          */
6586         misccpctl = I915_READ(GEN7_MISCCPCTL);
6587         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6588         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6589         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6590
6591         /*
6592          * WaGttCachingOffByDefault:bdw
6593          * GTT cache may not work with big pages, so if those
6594          * are ever enabled GTT cache may need to be disabled.
6595          */
6596         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6597
6598         lpt_init_clock_gating(dev);
6599 }
6600
6601 static void haswell_init_clock_gating(struct drm_device *dev)
6602 {
6603         struct drm_i915_private *dev_priv = dev->dev_private;
6604
6605         ilk_init_lp_watermarks(dev);
6606
6607         /* L3 caching of data atomics doesn't work -- disable it. */
6608         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6609         I915_WRITE(HSW_ROW_CHICKEN3,
6610                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6611
6612         /* This is required by WaCatErrorRejectionIssue:hsw */
6613         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6614                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6615                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6616
6617         /* WaVSRefCountFullforceMissDisable:hsw */
6618         I915_WRITE(GEN7_FF_THREAD_MODE,
6619                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6620
6621         /* WaDisable_RenderCache_OperationalFlush:hsw */
6622         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6623
6624         /* enable HiZ Raw Stall Optimization */
6625         I915_WRITE(CACHE_MODE_0_GEN7,
6626                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6627
6628         /* WaDisable4x2SubspanOptimization:hsw */
6629         I915_WRITE(CACHE_MODE_1,
6630                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6631
6632         /*
6633          * BSpec recommends 8x4 when MSAA is used,
6634          * however in practice 16x4 seems fastest.
6635          *
6636          * Note that PS/WM thread counts depend on the WIZ hashing
6637          * disable bit, which we don't touch here, but it's good
6638          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6639          */
6640         I915_WRITE(GEN7_GT_MODE,
6641                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6642
6643         /* WaSampleCChickenBitEnable:hsw */
6644         I915_WRITE(HALF_SLICE_CHICKEN3,
6645                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6646
6647         /* WaSwitchSolVfFArbitrationPriority:hsw */
6648         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6649
6650         /* WaRsPkgCStateDisplayPMReq:hsw */
6651         I915_WRITE(CHICKEN_PAR1_1,
6652                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6653
6654         lpt_init_clock_gating(dev);
6655 }
6656
6657 static void ivybridge_init_clock_gating(struct drm_device *dev)
6658 {
6659         struct drm_i915_private *dev_priv = dev->dev_private;
6660         uint32_t snpcr;
6661
6662         ilk_init_lp_watermarks(dev);
6663
6664         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6665
6666         /* WaDisableEarlyCull:ivb */
6667         I915_WRITE(_3D_CHICKEN3,
6668                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6669
6670         /* WaDisableBackToBackFlipFix:ivb */
6671         I915_WRITE(IVB_CHICKEN3,
6672                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6673                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6674
6675         /* WaDisablePSDDualDispatchEnable:ivb */
6676         if (IS_IVB_GT1(dev))
6677                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6678                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6679
6680         /* WaDisable_RenderCache_OperationalFlush:ivb */
6681         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6682
6683         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6684         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6685                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6686
6687         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6688         I915_WRITE(GEN7_L3CNTLREG1,
6689                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6690         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6691                    GEN7_WA_L3_CHICKEN_MODE);
6692         if (IS_IVB_GT1(dev))
6693                 I915_WRITE(GEN7_ROW_CHICKEN2,
6694                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6695         else {
6696                 /* must write both registers */
6697                 I915_WRITE(GEN7_ROW_CHICKEN2,
6698                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6699                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6700                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6701         }
6702
6703         /* WaForceL3Serialization:ivb */
6704         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6705                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6706
6707         /*
6708          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6709          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6710          */
6711         I915_WRITE(GEN6_UCGCTL2,
6712                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6713
6714         /* This is required by WaCatErrorRejectionIssue:ivb */
6715         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6716                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6717                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6718
6719         g4x_disable_trickle_feed(dev);
6720
6721         gen7_setup_fixed_func_scheduler(dev_priv);
6722
6723         if (0) { /* causes HiZ corruption on ivb:gt1 */
6724                 /* enable HiZ Raw Stall Optimization */
6725                 I915_WRITE(CACHE_MODE_0_GEN7,
6726                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6727         }
6728
6729         /* WaDisable4x2SubspanOptimization:ivb */
6730         I915_WRITE(CACHE_MODE_1,
6731                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6732
6733         /*
6734          * BSpec recommends 8x4 when MSAA is used,
6735          * however in practice 16x4 seems fastest.
6736          *
6737          * Note that PS/WM thread counts depend on the WIZ hashing
6738          * disable bit, which we don't touch here, but it's good
6739          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6740          */
6741         I915_WRITE(GEN7_GT_MODE,
6742                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6743
6744         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6745         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6746         snpcr |= GEN6_MBC_SNPCR_MED;
6747         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6748
6749         if (!HAS_PCH_NOP(dev))
6750                 cpt_init_clock_gating(dev);
6751
6752         gen6_check_mch_setup(dev);
6753 }
6754
6755 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6756 {
6757         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6758
6759         /*
6760          * Disable trickle feed and enable pnd deadline calculation
6761          */
6762         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6763         I915_WRITE(CBR1_VLV, 0);
6764 }
6765
6766 static void valleyview_init_clock_gating(struct drm_device *dev)
6767 {
6768         struct drm_i915_private *dev_priv = dev->dev_private;
6769
6770         vlv_init_display_clock_gating(dev_priv);
6771
6772         /* WaDisableEarlyCull:vlv */
6773         I915_WRITE(_3D_CHICKEN3,
6774                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6775
6776         /* WaDisableBackToBackFlipFix:vlv */
6777         I915_WRITE(IVB_CHICKEN3,
6778                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6779                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6780
6781         /* WaPsdDispatchEnable:vlv */
6782         /* WaDisablePSDDualDispatchEnable:vlv */
6783         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6784                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6785                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6786
6787         /* WaDisable_RenderCache_OperationalFlush:vlv */
6788         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6789
6790         /* WaForceL3Serialization:vlv */
6791         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6792                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6793
6794         /* WaDisableDopClockGating:vlv */
6795         I915_WRITE(GEN7_ROW_CHICKEN2,
6796                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6797
6798         /* This is required by WaCatErrorRejectionIssue:vlv */
6799         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6800                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6801                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6802
6803         gen7_setup_fixed_func_scheduler(dev_priv);
6804
6805         /*
6806          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6807          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6808          */
6809         I915_WRITE(GEN6_UCGCTL2,
6810                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6811
6812         /* WaDisableL3Bank2xClockGate:vlv
6813          * Disabling L3 clock gating- MMIO 940c[25] = 1
6814          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6815         I915_WRITE(GEN7_UCGCTL4,
6816                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6817
6818         /*
6819          * BSpec says this must be set, even though
6820          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6821          */
6822         I915_WRITE(CACHE_MODE_1,
6823                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6824
6825         /*
6826          * BSpec recommends 8x4 when MSAA is used,
6827          * however in practice 16x4 seems fastest.
6828          *
6829          * Note that PS/WM thread counts depend on the WIZ hashing
6830          * disable bit, which we don't touch here, but it's good
6831          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6832          */
6833         I915_WRITE(GEN7_GT_MODE,
6834                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6835
6836         /*
6837          * WaIncreaseL3CreditsForVLVB0:vlv
6838          * This is the hardware default actually.
6839          */
6840         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6841
6842         /*
6843          * WaDisableVLVClockGating_VBIIssue:vlv
6844          * Disable clock gating on th GCFG unit to prevent a delay
6845          * in the reporting of vblank events.
6846          */
6847         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6848 }
6849
6850 static void cherryview_init_clock_gating(struct drm_device *dev)
6851 {
6852         struct drm_i915_private *dev_priv = dev->dev_private;
6853
6854         vlv_init_display_clock_gating(dev_priv);
6855
6856         /* WaVSRefCountFullforceMissDisable:chv */
6857         /* WaDSRefCountFullforceMissDisable:chv */
6858         I915_WRITE(GEN7_FF_THREAD_MODE,
6859                    I915_READ(GEN7_FF_THREAD_MODE) &
6860                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6861
6862         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6863         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6864                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6865
6866         /* WaDisableCSUnitClockGating:chv */
6867         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6868                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6869
6870         /* WaDisableSDEUnitClockGating:chv */
6871         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6872                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6873
6874         /*
6875          * GTT cache may not work with big pages, so if those
6876          * are ever enabled GTT cache may need to be disabled.
6877          */
6878         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6879 }
6880
6881 static void g4x_init_clock_gating(struct drm_device *dev)
6882 {
6883         struct drm_i915_private *dev_priv = dev->dev_private;
6884         uint32_t dspclk_gate;
6885
6886         I915_WRITE(RENCLK_GATE_D1, 0);
6887         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6888                    GS_UNIT_CLOCK_GATE_DISABLE |
6889                    CL_UNIT_CLOCK_GATE_DISABLE);
6890         I915_WRITE(RAMCLK_GATE_D, 0);
6891         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6892                 OVRUNIT_CLOCK_GATE_DISABLE |
6893                 OVCUNIT_CLOCK_GATE_DISABLE;
6894         if (IS_GM45(dev))
6895                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6896         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6897
6898         /* WaDisableRenderCachePipelinedFlush */
6899         I915_WRITE(CACHE_MODE_0,
6900                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6901
6902         /* WaDisable_RenderCache_OperationalFlush:g4x */
6903         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6904
6905         g4x_disable_trickle_feed(dev);
6906 }
6907
6908 static void crestline_init_clock_gating(struct drm_device *dev)
6909 {
6910         struct drm_i915_private *dev_priv = dev->dev_private;
6911
6912         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6913         I915_WRITE(RENCLK_GATE_D2, 0);
6914         I915_WRITE(DSPCLK_GATE_D, 0);
6915         I915_WRITE(RAMCLK_GATE_D, 0);
6916         I915_WRITE16(DEUC, 0);
6917         I915_WRITE(MI_ARB_STATE,
6918                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6919
6920         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6921         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6922 }
6923
6924 static void broadwater_init_clock_gating(struct drm_device *dev)
6925 {
6926         struct drm_i915_private *dev_priv = dev->dev_private;
6927
6928         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6929                    I965_RCC_CLOCK_GATE_DISABLE |
6930                    I965_RCPB_CLOCK_GATE_DISABLE |
6931                    I965_ISC_CLOCK_GATE_DISABLE |
6932                    I965_FBC_CLOCK_GATE_DISABLE);
6933         I915_WRITE(RENCLK_GATE_D2, 0);
6934         I915_WRITE(MI_ARB_STATE,
6935                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6936
6937         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6938         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6939 }
6940
6941 static void gen3_init_clock_gating(struct drm_device *dev)
6942 {
6943         struct drm_i915_private *dev_priv = dev->dev_private;
6944         u32 dstate = I915_READ(D_STATE);
6945
6946         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6947                 DSTATE_DOT_CLOCK_GATING;
6948         I915_WRITE(D_STATE, dstate);
6949
6950         if (IS_PINEVIEW(dev))
6951                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6952
6953         /* IIR "flip pending" means done if this bit is set */
6954         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6955
6956         /* interrupts should cause a wake up from C3 */
6957         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6958
6959         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6960         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6961
6962         I915_WRITE(MI_ARB_STATE,
6963                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6964 }
6965
6966 static void i85x_init_clock_gating(struct drm_device *dev)
6967 {
6968         struct drm_i915_private *dev_priv = dev->dev_private;
6969
6970         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6971
6972         /* interrupts should cause a wake up from C3 */
6973         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6974                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6975
6976         I915_WRITE(MEM_MODE,
6977                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6978 }
6979
6980 static void i830_init_clock_gating(struct drm_device *dev)
6981 {
6982         struct drm_i915_private *dev_priv = dev->dev_private;
6983
6984         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6985
6986         I915_WRITE(MEM_MODE,
6987                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6988                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6989 }
6990
6991 void intel_init_clock_gating(struct drm_device *dev)
6992 {
6993         struct drm_i915_private *dev_priv = dev->dev_private;
6994
6995         if (dev_priv->display.init_clock_gating)
6996                 dev_priv->display.init_clock_gating(dev);
6997 }
6998
6999 void intel_suspend_hw(struct drm_device *dev)
7000 {
7001         if (HAS_PCH_LPT(dev))
7002                 lpt_suspend_hw(dev);
7003 }
7004
7005 /* Set up chip specific power management-related functions */
7006 void intel_init_pm(struct drm_device *dev)
7007 {
7008         struct drm_i915_private *dev_priv = dev->dev_private;
7009
7010         intel_fbc_init(dev_priv);
7011
7012         /* For cxsr */
7013         if (IS_PINEVIEW(dev))
7014                 i915_pineview_get_mem_freq(dev);
7015         else if (IS_GEN5(dev))
7016                 i915_ironlake_get_mem_freq(dev);
7017
7018         /* For FIFO watermark updates */
7019         if (INTEL_INFO(dev)->gen >= 9) {
7020                 skl_setup_wm_latency(dev);
7021
7022                 if (IS_BROXTON(dev))
7023                         dev_priv->display.init_clock_gating =
7024                                 bxt_init_clock_gating;
7025                 dev_priv->display.update_wm = skl_update_wm;
7026         } else if (HAS_PCH_SPLIT(dev)) {
7027                 ilk_setup_wm_latency(dev);
7028
7029                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7030                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7031                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7032                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7033                         dev_priv->display.update_wm = ilk_update_wm;
7034                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
7035                         dev_priv->display.program_watermarks = ilk_program_watermarks;
7036                 } else {
7037                         DRM_DEBUG_KMS("Failed to read display plane latency. "
7038                                       "Disable CxSR\n");
7039                 }
7040
7041                 if (IS_GEN5(dev))
7042                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7043                 else if (IS_GEN6(dev))
7044                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7045                 else if (IS_IVYBRIDGE(dev))
7046                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7047                 else if (IS_HASWELL(dev))
7048                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7049                 else if (INTEL_INFO(dev)->gen == 8)
7050                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7051         } else if (IS_CHERRYVIEW(dev)) {
7052                 vlv_setup_wm_latency(dev);
7053
7054                 dev_priv->display.update_wm = vlv_update_wm;
7055                 dev_priv->display.init_clock_gating =
7056                         cherryview_init_clock_gating;
7057         } else if (IS_VALLEYVIEW(dev)) {
7058                 vlv_setup_wm_latency(dev);
7059
7060                 dev_priv->display.update_wm = vlv_update_wm;
7061                 dev_priv->display.init_clock_gating =
7062                         valleyview_init_clock_gating;
7063         } else if (IS_PINEVIEW(dev)) {
7064                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7065                                             dev_priv->is_ddr3,
7066                                             dev_priv->fsb_freq,
7067                                             dev_priv->mem_freq)) {
7068                         DRM_INFO("failed to find known CxSR latency "
7069                                  "(found ddr%s fsb freq %d, mem freq %d), "
7070                                  "disabling CxSR\n",
7071                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
7072                                  dev_priv->fsb_freq, dev_priv->mem_freq);
7073                         /* Disable CxSR and never update its watermark again */
7074                         intel_set_memory_cxsr(dev_priv, false);
7075                         dev_priv->display.update_wm = NULL;
7076                 } else
7077                         dev_priv->display.update_wm = pineview_update_wm;
7078                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7079         } else if (IS_G4X(dev)) {
7080                 dev_priv->display.update_wm = g4x_update_wm;
7081                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7082         } else if (IS_GEN4(dev)) {
7083                 dev_priv->display.update_wm = i965_update_wm;
7084                 if (IS_CRESTLINE(dev))
7085                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7086                 else if (IS_BROADWATER(dev))
7087                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7088         } else if (IS_GEN3(dev)) {
7089                 dev_priv->display.update_wm = i9xx_update_wm;
7090                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7091                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7092         } else if (IS_GEN2(dev)) {
7093                 if (INTEL_INFO(dev)->num_pipes == 1) {
7094                         dev_priv->display.update_wm = i845_update_wm;
7095                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7096                 } else {
7097                         dev_priv->display.update_wm = i9xx_update_wm;
7098                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7099                 }
7100
7101                 if (IS_I85X(dev) || IS_I865G(dev))
7102                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7103                 else
7104                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7105         } else {
7106                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7107         }
7108 }
7109
7110 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7111 {
7112         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7113
7114         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7115                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7116                 return -EAGAIN;
7117         }
7118
7119         I915_WRITE(GEN6_PCODE_DATA, *val);
7120         I915_WRITE(GEN6_PCODE_DATA1, 0);
7121         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7122
7123         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7124                      500)) {
7125                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7126                 return -ETIMEDOUT;
7127         }
7128
7129         *val = I915_READ(GEN6_PCODE_DATA);
7130         I915_WRITE(GEN6_PCODE_DATA, 0);
7131
7132         return 0;
7133 }
7134
7135 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7136 {
7137         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7138
7139         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7140                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7141                 return -EAGAIN;
7142         }
7143
7144         I915_WRITE(GEN6_PCODE_DATA, val);
7145         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7146
7147         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7148                      500)) {
7149                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7150                 return -ETIMEDOUT;
7151         }
7152
7153         I915_WRITE(GEN6_PCODE_DATA, 0);
7154
7155         return 0;
7156 }
7157
7158 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7159 {
7160         switch (czclk_freq) {
7161         case 200:
7162                 return 10;
7163         case 267:
7164                 return 12;
7165         case 320:
7166         case 333:
7167                 return 16;
7168         case 400:
7169                 return 20;
7170         default:
7171                 return -1;
7172         }
7173 }
7174
7175 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7176 {
7177         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7178
7179         div = vlv_gpu_freq_div(czclk_freq);
7180         if (div < 0)
7181                 return div;
7182
7183         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7184 }
7185
7186 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7187 {
7188         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7189
7190         mul = vlv_gpu_freq_div(czclk_freq);
7191         if (mul < 0)
7192                 return mul;
7193
7194         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7195 }
7196
7197 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7198 {
7199         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7200
7201         div = vlv_gpu_freq_div(czclk_freq) / 2;
7202         if (div < 0)
7203                 return div;
7204
7205         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7206 }
7207
7208 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7209 {
7210         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7211
7212         mul = vlv_gpu_freq_div(czclk_freq) / 2;
7213         if (mul < 0)
7214                 return mul;
7215
7216         /* CHV needs even values */
7217         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7218 }
7219
7220 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7221 {
7222         if (IS_GEN9(dev_priv->dev))
7223                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7224                                          GEN9_FREQ_SCALER);
7225         else if (IS_CHERRYVIEW(dev_priv->dev))
7226                 return chv_gpu_freq(dev_priv, val);
7227         else if (IS_VALLEYVIEW(dev_priv->dev))
7228                 return byt_gpu_freq(dev_priv, val);
7229         else
7230                 return val * GT_FREQUENCY_MULTIPLIER;
7231 }
7232
7233 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7234 {
7235         if (IS_GEN9(dev_priv->dev))
7236                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7237                                          GT_FREQUENCY_MULTIPLIER);
7238         else if (IS_CHERRYVIEW(dev_priv->dev))
7239                 return chv_freq_opcode(dev_priv, val);
7240         else if (IS_VALLEYVIEW(dev_priv->dev))
7241                 return byt_freq_opcode(dev_priv, val);
7242         else
7243                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7244 }
7245
7246 struct request_boost {
7247         struct work_struct work;
7248         struct drm_i915_gem_request *req;
7249 };
7250
7251 static void __intel_rps_boost_work(struct work_struct *work)
7252 {
7253         struct request_boost *boost = container_of(work, struct request_boost, work);
7254         struct drm_i915_gem_request *req = boost->req;
7255
7256         if (!i915_gem_request_completed(req, true))
7257                 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7258                                req->emitted_jiffies);
7259
7260         i915_gem_request_unreference__unlocked(req);
7261         kfree(boost);
7262 }
7263
7264 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7265                                        struct drm_i915_gem_request *req)
7266 {
7267         struct request_boost *boost;
7268
7269         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7270                 return;
7271
7272         if (i915_gem_request_completed(req, true))
7273                 return;
7274
7275         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7276         if (boost == NULL)
7277                 return;
7278
7279         i915_gem_request_reference(req);
7280         boost->req = req;
7281
7282         INIT_WORK(&boost->work, __intel_rps_boost_work);
7283         queue_work(to_i915(dev)->wq, &boost->work);
7284 }
7285
7286 void intel_pm_setup(struct drm_device *dev)
7287 {
7288         struct drm_i915_private *dev_priv = dev->dev_private;
7289
7290         mutex_init(&dev_priv->rps.hw_lock);
7291         spin_lock_init(&dev_priv->rps.client_lock);
7292
7293         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7294                           intel_gen6_powersave_work);
7295         INIT_LIST_HEAD(&dev_priv->rps.clients);
7296         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7297         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7298
7299         dev_priv->pm.suspended = false;
7300         atomic_set(&dev_priv->pm.wakeref_count, 0);
7301         atomic_set(&dev_priv->pm.atomic_seq, 0);
7302 }