drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31 #include <drm/drmP.h>
  32 #include "i915_drv.h"
  33 #include <drm/i915_drm.h>
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 /* Rough estimate of the typical request size, performing a flush,
  38  * set-context and then emitting the batch.
  39  */
  40 #define LEGACY_REQUEST_SIZE 200
  41
  42 int __intel_ring_space(int head, int tail, int size)
  43 {
  44         int space = head - tail;
  45         if (space <= 0)
  46                 space += size;
  47         return space - I915_RING_FREE_SPACE;
  48 }
  49
  50 void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
  51 {
  52         if (ringbuf->last_retired_head != -1) {
  53                 ringbuf->head = ringbuf->last_retired_head;
  54                 ringbuf->last_retired_head = -1;
  55         }
  56
  57         ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
  58                                             ringbuf->tail, ringbuf->size);
  59 }
  60
  61 static void __intel_ring_advance(struct intel_engine_cs *engine)
  62 {
  63         struct intel_ringbuffer *ringbuf = engine->buffer;
  64         ringbuf->tail &= ringbuf->size - 1;
  65         engine->write_tail(engine, ringbuf->tail);
  66 }
  67
  68 static int
  69 gen2_render_ring_flush(struct drm_i915_gem_request *req,
  70                        u32      invalidate_domains,
  71                        u32      flush_domains)
  72 {
  73         struct intel_engine_cs *engine = req->engine;
  74         u32 cmd;
  75         int ret;
  76
  77         cmd = MI_FLUSH;
  78         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  79                 cmd |= MI_NO_WRITE_FLUSH;
  80
  81         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  82                 cmd |= MI_READ_FLUSH;
  83
  84         ret = intel_ring_begin(req, 2);
  85         if (ret)
  86                 return ret;
  87
  88         intel_ring_emit(engine, cmd);
  89         intel_ring_emit(engine, MI_NOOP);
  90         intel_ring_advance(engine);
  91
  92         return 0;
  93 }
  94
  95 static int
  96 gen4_render_ring_flush(struct drm_i915_gem_request *req,
  97                        u32      invalidate_domains,
  98                        u32      flush_domains)
  99 {
 100         struct intel_engine_cs *engine = req->engine;
 101         u32 cmd;
 102         int ret;
 103
 104         /*
 105          * read/write caches:
 106          *
 107          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 108          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 109          * also flushed at 2d versus 3d pipeline switches.
 110          *
 111          * read-only caches:
 112          *
 113          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 114          * MI_READ_FLUSH is set, and is always flushed on 965.
 115          *
 116          * I915_GEM_DOMAIN_COMMAND may not exist?
 117          *
 118          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 119          * invalidated when MI_EXE_FLUSH is set.
 120          *
 121          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 122          * invalidated with every MI_FLUSH.
 123          *
 124          * TLBs:
 125          *
 126          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 127          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 128          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 129          * are flushed at any MI_FLUSH.
 130          */
 131
 132         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 133         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 134                 cmd &= ~MI_NO_WRITE_FLUSH;
 135         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 136                 cmd |= MI_EXE_FLUSH;
 137
 138         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 139             (IS_G4X(req->i915) || IS_GEN5(req->i915)))
 140                 cmd |= MI_INVALIDATE_ISP;
 141
 142         ret = intel_ring_begin(req, 2);
 143         if (ret)
 144                 return ret;
 145
 146         intel_ring_emit(engine, cmd);
 147         intel_ring_emit(engine, MI_NOOP);
 148         intel_ring_advance(engine);
 149
 150         return 0;
 151 }
 152
 153 /**
 154  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 155  * implementing two workarounds on gen6.  From section 1.4.7.1
 156  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 157  *
 158  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 159  * produced by non-pipelined state commands), software needs to first
 160  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 161  * 0.
 162  *
 163  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 164  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 165  *
 166  * And the workaround for these two requires this workaround first:
 167  *
 168  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 169  * BEFORE the pipe-control with a post-sync op and no write-cache
 170  * flushes.
 171  *
 172  * And this last workaround is tricky because of the requirements on
 173  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 174  * volume 2 part 1:
 175  *
 176  *     "1 of the following must also be set:
 177  *      - Render Target Cache Flush Enable ([12] of DW1)
 178  *      - Depth Cache Flush Enable ([0] of DW1)
 179  *      - Stall at Pixel Scoreboard ([1] of DW1)
 180  *      - Depth Stall ([13] of DW1)
 181  *      - Post-Sync Operation ([13] of DW1)
 182  *      - Notify Enable ([8] of DW1)"
 183  *
 184  * The cache flushes require the workaround flush that triggered this
 185  * one, so we can't use it.  Depth stall would trigger the same.
 186  * Post-sync nonzero is what triggered this second workaround, so we
 187  * can't use that one either.  Notify enable is IRQs, which aren't
 188  * really our business.  That leaves only stall at scoreboard.
 189  */
 190 static int
 191 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
 192 {
 193         struct intel_engine_cs *engine = req->engine;
 194         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 195         int ret;
 196
 197         ret = intel_ring_begin(req, 6);
 198         if (ret)
 199                 return ret;
 200
 201         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 202         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 203                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 204         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 205         intel_ring_emit(engine, 0); /* low dword */
 206         intel_ring_emit(engine, 0); /* high dword */
 207         intel_ring_emit(engine, MI_NOOP);
 208         intel_ring_advance(engine);
 209
 210         ret = intel_ring_begin(req, 6);
 211         if (ret)
 212                 return ret;
 213
 214         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
 215         intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
 216         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 217         intel_ring_emit(engine, 0);
 218         intel_ring_emit(engine, 0);
 219         intel_ring_emit(engine, MI_NOOP);
 220         intel_ring_advance(engine);
 221
 222         return 0;
 223 }
 224
 225 static int
 226 gen6_render_ring_flush(struct drm_i915_gem_request *req,
 227                        u32 invalidate_domains, u32 flush_domains)
 228 {
 229         struct intel_engine_cs *engine = req->engine;
 230         u32 flags = 0;
 231         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 232         int ret;
 233
 234         /* Force SNB workarounds for PIPE_CONTROL flushes */
 235         ret = intel_emit_post_sync_nonzero_flush(req);
 236         if (ret)
 237                 return ret;
 238
 239         /* Just flush everything.  Experiments have shown that reducing the
 240          * number of bits based on the write domains has little performance
 241          * impact.
 242          */
 243         if (flush_domains) {
 244                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 245                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 246                 /*
 247                  * Ensure that any following seqno writes only happen
 248                  * when the render cache is indeed flushed.
 249                  */
 250                 flags |= PIPE_CONTROL_CS_STALL;
 251         }
 252         if (invalidate_domains) {
 253                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 254                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 255                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 256                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 257                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 258                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 259                 /*
 260                  * TLB invalidate requires a post-sync write.
 261                  */
 262                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 263         }
 264
 265         ret = intel_ring_begin(req, 4);
 266         if (ret)
 267                 return ret;
 268
 269         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 270         intel_ring_emit(engine, flags);
 271         intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 272         intel_ring_emit(engine, 0);
 273         intel_ring_advance(engine);
 274
 275         return 0;
 276 }
 277
 278 static int
 279 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
 280 {
 281         struct intel_engine_cs *engine = req->engine;
 282         int ret;
 283
 284         ret = intel_ring_begin(req, 4);
 285         if (ret)
 286                 return ret;
 287
 288         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 289         intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
 290                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 291         intel_ring_emit(engine, 0);
 292         intel_ring_emit(engine, 0);
 293         intel_ring_advance(engine);
 294
 295         return 0;
 296 }
 297
 298 static int
 299 gen7_render_ring_flush(struct drm_i915_gem_request *req,
 300                        u32 invalidate_domains, u32 flush_domains)
 301 {
 302         struct intel_engine_cs *engine = req->engine;
 303         u32 flags = 0;
 304         u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 305         int ret;
 306
 307         /*
 308          * Ensure that any following seqno writes only happen when the render
 309          * cache is indeed flushed.
 310          *
 311          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 312          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 313          * don't try to be clever and just set it unconditionally.
 314          */
 315         flags |= PIPE_CONTROL_CS_STALL;
 316
 317         /* Just flush everything.  Experiments have shown that reducing the
 318          * number of bits based on the write domains has little performance
 319          * impact.
 320          */
 321         if (flush_domains) {
 322                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 323                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 324                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 325                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 326         }
 327         if (invalidate_domains) {
 328                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 329                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 330                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 331                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 332                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 333                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 335                 /*
 336                  * TLB invalidate requires a post-sync write.
 337                  */
 338                 flags |= PIPE_CONTROL_QW_WRITE;
 339                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 340
 341                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 342
 343                 /* Workaround: we must issue a pipe_control with CS-stall bit
 344                  * set before a pipe_control command that has the state cache
 345                  * invalidate bit set. */
 346                 gen7_render_ring_cs_stall_wa(req);
 347         }
 348
 349         ret = intel_ring_begin(req, 4);
 350         if (ret)
 351                 return ret;
 352
 353         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
 354         intel_ring_emit(engine, flags);
 355         intel_ring_emit(engine, scratch_addr);
 356         intel_ring_emit(engine, 0);
 357         intel_ring_advance(engine);
 358
 359         return 0;
 360 }
 361
 362 static int
 363 gen8_emit_pipe_control(struct drm_i915_gem_request *req,
 364                        u32 flags, u32 scratch_addr)
 365 {
 366         struct intel_engine_cs *engine = req->engine;
 367         int ret;
 368
 369         ret = intel_ring_begin(req, 6);
 370         if (ret)
 371                 return ret;
 372
 373         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
 374         intel_ring_emit(engine, flags);
 375         intel_ring_emit(engine, scratch_addr);
 376         intel_ring_emit(engine, 0);
 377         intel_ring_emit(engine, 0);
 378         intel_ring_emit(engine, 0);
 379         intel_ring_advance(engine);
 380
 381         return 0;
 382 }
 383
 384 static int
 385 gen8_render_ring_flush(struct drm_i915_gem_request *req,
 386                        u32 invalidate_domains, u32 flush_domains)
 387 {
 388         u32 flags = 0;
 389         u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
 390         int ret;
 391
 392         flags |= PIPE_CONTROL_CS_STALL;
 393
 394         if (flush_domains) {
 395                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 396                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 397                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 398                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 399         }
 400         if (invalidate_domains) {
 401                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 402                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 403                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 404                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 405                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 406                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 407                 flags |= PIPE_CONTROL_QW_WRITE;
 408                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 409
 410                 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
 411                 ret = gen8_emit_pipe_control(req,
 412                                              PIPE_CONTROL_CS_STALL |
 413                                              PIPE_CONTROL_STALL_AT_SCOREBOARD,
 414                                              0);
 415                 if (ret)
 416                         return ret;
 417         }
 418
 419         return gen8_emit_pipe_control(req, flags, scratch_addr);
 420 }
 421
 422 static void ring_write_tail(struct intel_engine_cs *engine,
 423                             u32 value)
 424 {
 425         struct drm_i915_private *dev_priv = engine->i915;
 426         I915_WRITE_TAIL(engine, value);
 427 }
 428
 429 u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
 430 {
 431         struct drm_i915_private *dev_priv = engine->i915;
 432         u64 acthd;
 433
 434         if (INTEL_GEN(dev_priv) >= 8)
 435                 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
 436                                          RING_ACTHD_UDW(engine->mmio_base));
 437         else if (INTEL_GEN(dev_priv) >= 4)
 438                 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
 439         else
 440                 acthd = I915_READ(ACTHD);
 441
 442         return acthd;
 443 }
 444
 445 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 446 {
 447         struct drm_i915_private *dev_priv = engine->i915;
 448         u32 addr;
 449
 450         addr = dev_priv->status_page_dmah->busaddr;
 451         if (INTEL_GEN(dev_priv) >= 4)
 452                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 453         I915_WRITE(HWS_PGA, addr);
 454 }
 455
 456 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 457 {
 458         struct drm_i915_private *dev_priv = engine->i915;
 459         i915_reg_t mmio;
 460
 461         /* The ring status page addresses are no longer next to the rest of
 462          * the ring registers as of gen7.
 463          */
 464         if (IS_GEN7(dev_priv)) {
 465                 switch (engine->id) {
 466                 case RCS:
 467                         mmio = RENDER_HWS_PGA_GEN7;
 468                         break;
 469                 case BCS:
 470                         mmio = BLT_HWS_PGA_GEN7;
 471                         break;
 472                 /*
 473                  * VCS2 actually doesn't exist on Gen7. Only shut up
 474                  * gcc switch check warning
 475                  */
 476                 case VCS2:
 477                 case VCS:
 478                         mmio = BSD_HWS_PGA_GEN7;
 479                         break;
 480                 case VECS:
 481                         mmio = VEBOX_HWS_PGA_GEN7;
 482                         break;
 483                 }
 484         } else if (IS_GEN6(dev_priv)) {
 485                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 486         } else {
 487                 /* XXX: gen8 returns to sanity */
 488                 mmio = RING_HWS_PGA(engine->mmio_base);
 489         }
 490
 491         I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
 492         POSTING_READ(mmio);
 493
 494         /*
 495          * Flush the TLB for this page
 496          *
 497          * FIXME: These two bits have disappeared on gen8, so a question
 498          * arises: do we still need this and if so how should we go about
 499          * invalidating the TLB?
 500          */
 501         if (IS_GEN(dev_priv, 6, 7)) {
 502                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 503
 504                 /* ring should be idle before issuing a sync flush*/
 505                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 506
 507                 I915_WRITE(reg,
 508                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 509                                               INSTPM_SYNC_FLUSH));
 510                 if (intel_wait_for_register(dev_priv,
 511                                             reg, INSTPM_SYNC_FLUSH, 0,
 512                                             1000))
 513                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 514                                   engine->name);
 515         }
 516 }
 517
 518 static bool stop_ring(struct intel_engine_cs *engine)
 519 {
 520         struct drm_i915_private *dev_priv = engine->i915;
 521
 522         if (!IS_GEN2(dev_priv)) {
 523                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 524                 if (intel_wait_for_register(dev_priv,
 525                                             RING_MI_MODE(engine->mmio_base),
 526                                             MODE_IDLE,
 527                                             MODE_IDLE,
 528                                             1000)) {
 529                         DRM_ERROR("%s : timed out trying to stop ring\n",
 530                                   engine->name);
 531                         /* Sometimes we observe that the idle flag is not
 532                          * set even though the ring is empty. So double
 533                          * check before giving up.
 534                          */
 535                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 536                                 return false;
 537                 }
 538         }
 539
 540         I915_WRITE_CTL(engine, 0);
 541         I915_WRITE_HEAD(engine, 0);
 542         engine->write_tail(engine, 0);
 543
 544         if (!IS_GEN2(dev_priv)) {
 545                 (void)I915_READ_CTL(engine);
 546                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 547         }
 548
 549         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 550 }
 551
 552 void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
 553 {
 554         memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
 555 }
 556
 557 static int init_ring_common(struct intel_engine_cs *engine)
 558 {
 559         struct drm_i915_private *dev_priv = engine->i915;
 560         struct intel_ringbuffer *ringbuf = engine->buffer;
 561         struct drm_i915_gem_object *obj = ringbuf->obj;
 562         int ret = 0;
 563
 564         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 565
 566         if (!stop_ring(engine)) {
 567                 /* G45 ring initialization often fails to reset head to zero */
 568                 DRM_DEBUG_KMS("%s head not reset to zero "
 569                               "ctl %08x head %08x tail %08x start %08x\n",
 570                               engine->name,
 571                               I915_READ_CTL(engine),
 572                               I915_READ_HEAD(engine),
 573                               I915_READ_TAIL(engine),
 574                               I915_READ_START(engine));
 575
 576                 if (!stop_ring(engine)) {
 577                         DRM_ERROR("failed to set %s head to zero "
 578                                   "ctl %08x head %08x tail %08x start %08x\n",
 579                                   engine->name,
 580                                   I915_READ_CTL(engine),
 581                                   I915_READ_HEAD(engine),
 582                                   I915_READ_TAIL(engine),
 583                                   I915_READ_START(engine));
 584                         ret = -EIO;
 585                         goto out;
 586                 }
 587         }
 588
 589         if (I915_NEED_GFX_HWS(dev_priv))
 590                 intel_ring_setup_status_page(engine);
 591         else
 592                 ring_setup_phys_status_page(engine);
 593
 594         /* Enforce ordering by reading HEAD register back */
 595         I915_READ_HEAD(engine);
 596
 597         /* Initialize the ring. This must happen _after_ we've cleared the ring
 598          * registers with the above sequence (the readback of the HEAD registers
 599          * also enforces ordering), otherwise the hw might lose the new ring
 600          * register values. */
 601         I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
 602
 603         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 604         if (I915_READ_HEAD(engine))
 605                 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
 606                           engine->name, I915_READ_HEAD(engine));
 607         I915_WRITE_HEAD(engine, 0);
 608         (void)I915_READ_HEAD(engine);
 609
 610         I915_WRITE_CTL(engine,
 611                         ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
 612                         | RING_VALID);
 613
 614         /* If the head is still not zero, the ring is dead */
 615         if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
 616                      I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
 617                      (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
 618                 DRM_ERROR("%s initialization failed "
 619                           "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
 620                           engine->name,
 621                           I915_READ_CTL(engine),
 622                           I915_READ_CTL(engine) & RING_VALID,
 623                           I915_READ_HEAD(engine), I915_READ_TAIL(engine),
 624                           I915_READ_START(engine),
 625                           (unsigned long)i915_gem_obj_ggtt_offset(obj));
 626                 ret = -EIO;
 627                 goto out;
 628         }
 629
 630         ringbuf->last_retired_head = -1;
 631         ringbuf->head = I915_READ_HEAD(engine);
 632         ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
 633         intel_ring_update_space(ringbuf);
 634
 635         intel_engine_init_hangcheck(engine);
 636
 637 out:
 638         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 639
 640         return ret;
 641 }
 642
 643 void intel_fini_pipe_control(struct intel_engine_cs *engine)
 644 {
 645         if (engine->scratch.obj == NULL)
 646                 return;
 647
 648         i915_gem_object_ggtt_unpin(engine->scratch.obj);
 649         drm_gem_object_unreference(&engine->scratch.obj->base);
 650         engine->scratch.obj = NULL;
 651 }
 652
 653 int intel_init_pipe_control(struct intel_engine_cs *engine, int size)
 654 {
 655         struct drm_i915_gem_object *obj;
 656         int ret;
 657
 658         WARN_ON(engine->scratch.obj);
 659
 660         obj = i915_gem_object_create_stolen(&engine->i915->drm, size);
 661         if (!obj)
 662                 obj = i915_gem_object_create(&engine->i915->drm, size);
 663         if (IS_ERR(obj)) {
 664                 DRM_ERROR("Failed to allocate scratch page\n");
 665                 ret = PTR_ERR(obj);
 666                 goto err;
 667         }
 668
 669         ret = i915_gem_obj_ggtt_pin(obj, 4096, PIN_HIGH);
 670         if (ret)
 671                 goto err_unref;
 672
 673         engine->scratch.obj = obj;
 674         engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
 675         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 676                          engine->name, engine->scratch.gtt_offset);
 677         return 0;
 678
 679 err_unref:
 680         drm_gem_object_unreference(&engine->scratch.obj->base);
 681 err:
 682         return ret;
 683 }
 684
 685 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
 686 {
 687         struct intel_engine_cs *engine = req->engine;
 688         struct i915_workarounds *w = &req->i915->workarounds;
 689         int ret, i;
 690
 691         if (w->count == 0)
 692                 return 0;
 693
 694         engine->gpu_caches_dirty = true;
 695         ret = intel_ring_flush_all_caches(req);
 696         if (ret)
 697                 return ret;
 698
 699         ret = intel_ring_begin(req, (w->count * 2 + 2));
 700         if (ret)
 701                 return ret;
 702
 703         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
 704         for (i = 0; i < w->count; i++) {
 705                 intel_ring_emit_reg(engine, w->reg[i].addr);
 706                 intel_ring_emit(engine, w->reg[i].value);
 707         }
 708         intel_ring_emit(engine, MI_NOOP);
 709
 710         intel_ring_advance(engine);
 711
 712         engine->gpu_caches_dirty = true;
 713         ret = intel_ring_flush_all_caches(req);
 714         if (ret)
 715                 return ret;
 716
 717         DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
 718
 719         return 0;
 720 }
 721
 722 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
 723 {
 724         int ret;
 725
 726         ret = intel_ring_workarounds_emit(req);
 727         if (ret != 0)
 728                 return ret;
 729
 730         ret = i915_gem_render_state_init(req);
 731         if (ret)
 732                 return ret;
 733
 734         return 0;
 735 }
 736
 737 static int wa_add(struct drm_i915_private *dev_priv,
 738                   i915_reg_t addr,
 739                   const u32 mask, const u32 val)
 740 {
 741         const u32 idx = dev_priv->workarounds.count;
 742
 743         if (WARN_ON(idx >= I915_MAX_WA_REGS))
 744                 return -ENOSPC;
 745
 746         dev_priv->workarounds.reg[idx].addr = addr;
 747         dev_priv->workarounds.reg[idx].value = val;
 748         dev_priv->workarounds.reg[idx].mask = mask;
 749
 750         dev_priv->workarounds.count++;
 751
 752         return 0;
 753 }
 754
 755 #define WA_REG(addr, mask, val) do { \
 756                 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
 757                 if (r) \
 758                         return r; \
 759         } while (0)
 760
 761 #define WA_SET_BIT_MASKED(addr, mask) \
 762         WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
 763
 764 #define WA_CLR_BIT_MASKED(addr, mask) \
 765         WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
 766
 767 #define WA_SET_FIELD_MASKED(addr, mask, value) \
 768         WA_REG(addr, mask, _MASKED_FIELD(mask, value))
 769
 770 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
 771 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
 772
 773 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
 774
 775 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
 776                                  i915_reg_t reg)
 777 {
 778         struct drm_i915_private *dev_priv = engine->i915;
 779         struct i915_workarounds *wa = &dev_priv->workarounds;
 780         const uint32_t index = wa->hw_whitelist_count[engine->id];
 781
 782         if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
 783                 return -EINVAL;
 784
 785         WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
 786                  i915_mmio_reg_offset(reg));
 787         wa->hw_whitelist_count[engine->id]++;
 788
 789         return 0;
 790 }
 791
 792 static int gen8_init_workarounds(struct intel_engine_cs *engine)
 793 {
 794         struct drm_i915_private *dev_priv = engine->i915;
 795
 796         WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
 797
 798         /* WaDisableAsyncFlipPerfMode:bdw,chv */
 799         WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
 800
 801         /* WaDisablePartialInstShootdown:bdw,chv */
 802         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 803                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 804
 805         /* Use Force Non-Coherent whenever executing a 3D context. This is a
 806          * workaround for for a possible hang in the unlikely event a TLB
 807          * invalidation occurs during a PSD flush.
 808          */
 809         /* WaForceEnableNonCoherent:bdw,chv */
 810         /* WaHdcDisableFetchWhenMasked:bdw,chv */
 811         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 812                           HDC_DONOT_FETCH_MEM_WHEN_MASKED |
 813                           HDC_FORCE_NON_COHERENT);
 814
 815         /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
 816          * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
 817          *  polygons in the same 8x4 pixel/sample area to be processed without
 818          *  stalling waiting for the earlier ones to write to Hierarchical Z
 819          *  buffer."
 820          *
 821          * This optimization is off by default for BDW and CHV; turn it on.
 822          */
 823         WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
 824
 825         /* Wa4x4STCOptimizationDisable:bdw,chv */
 826         WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
 827
 828         /*
 829          * BSpec recommends 8x4 when MSAA is used,
 830          * however in practice 16x4 seems fastest.
 831          *
 832          * Note that PS/WM thread counts depend on the WIZ hashing
 833          * disable bit, which we don't touch here, but it's good
 834          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
 835          */
 836         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
 837                             GEN6_WIZ_HASHING_MASK,
 838                             GEN6_WIZ_HASHING_16x4);
 839
 840         return 0;
 841 }
 842
 843 static int bdw_init_workarounds(struct intel_engine_cs *engine)
 844 {
 845         struct drm_i915_private *dev_priv = engine->i915;
 846         int ret;
 847
 848         ret = gen8_init_workarounds(engine);
 849         if (ret)
 850                 return ret;
 851
 852         /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
 853         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 854
 855         /* WaDisableDopClockGating:bdw */
 856         WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
 857                           DOP_CLOCK_GATING_DISABLE);
 858
 859         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 860                           GEN8_SAMPLER_POWER_BYPASS_DIS);
 861
 862         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 863                           /* WaForceContextSaveRestoreNonCoherent:bdw */
 864                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 865                           /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
 866                           (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
 867
 868         return 0;
 869 }
 870
 871 static int chv_init_workarounds(struct intel_engine_cs *engine)
 872 {
 873         struct drm_i915_private *dev_priv = engine->i915;
 874         int ret;
 875
 876         ret = gen8_init_workarounds(engine);
 877         if (ret)
 878                 return ret;
 879
 880         /* WaDisableThreadStallDopClockGating:chv */
 881         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
 882
 883         /* Improve HiZ throughput on CHV. */
 884         WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
 885
 886         return 0;
 887 }
 888
 889 static int gen9_init_workarounds(struct intel_engine_cs *engine)
 890 {
 891         struct drm_i915_private *dev_priv = engine->i915;
 892         int ret;
 893
 894         /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */
 895         I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE));
 896
 897         /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
 898         I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
 899                    GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
 900
 901         /* WaDisableKillLogic:bxt,skl,kbl */
 902         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 903                    ECOCHK_DIS_TLB);
 904
 905         /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
 906         /* WaDisablePartialInstShootdown:skl,bxt,kbl */
 907         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
 908                           FLOW_CONTROL_ENABLE |
 909                           PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
 910
 911         /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
 912         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 913                           GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
 914
 915         /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
 916         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
 917             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
 918                 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 919                                   GEN9_DG_MIRROR_FIX_ENABLE);
 920
 921         /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
 922         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
 923             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
 924                 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
 925                                   GEN9_RHWO_OPTIMIZATION_DISABLE);
 926                 /*
 927                  * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
 928                  * but we do that in per ctx batchbuffer as there is an issue
 929                  * with this register not getting restored on ctx restore
 930                  */
 931         }
 932
 933         /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
 934         /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
 935         WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
 936                           GEN9_ENABLE_YV12_BUGFIX |
 937                           GEN9_ENABLE_GPGPU_PREEMPTION);
 938
 939         /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
 940         /* WaDisablePartialResolveInVc:skl,bxt,kbl */
 941         WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
 942                                          GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
 943
 944         /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
 945         WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
 946                           GEN9_CCS_TLB_PREFETCH_ENABLE);
 947
 948         /* WaDisableMaskBasedCammingInRCC:skl,bxt */
 949         if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) ||
 950             IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
 951                 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
 952                                   PIXEL_MASK_CAMMING_DISABLE);
 953
 954         /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
 955         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 956                           HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
 957                           HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
 958
 959         /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
 960          * both tied to WaForceContextSaveRestoreNonCoherent
 961          * in some hsds for skl. We keep the tie for all gen9. The
 962          * documentation is a bit hazy and so we want to get common behaviour,
 963          * even though there is no clear evidence we would need both on kbl/bxt.
 964          * This area has been source of system hangs so we play it safe
 965          * and mimic the skl regardless of what bspec says.
 966          *
 967          * Use Force Non-Coherent whenever executing a 3D context. This
 968          * is a workaround for a possible hang in the unlikely event
 969          * a TLB invalidation occurs during a PSD flush.
 970          */
 971
 972         /* WaForceEnableNonCoherent:skl,bxt,kbl */
 973         WA_SET_BIT_MASKED(HDC_CHICKEN0,
 974                           HDC_FORCE_NON_COHERENT);
 975
 976         /* WaDisableHDCInvalidation:skl,bxt,kbl */
 977         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
 978                    BDW_DISABLE_HDC_INVALIDATION);
 979
 980         /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
 981         if (IS_SKYLAKE(dev_priv) ||
 982             IS_KABYLAKE(dev_priv) ||
 983             IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
 984                 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
 985                                   GEN8_SAMPLER_POWER_BYPASS_DIS);
 986
 987         /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
 988         WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
 989
 990         /* WaOCLCoherentLineFlush:skl,bxt,kbl */
 991         I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
 992                                     GEN8_LQSC_FLUSH_COHERENT_LINES));
 993
 994         /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
 995         ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
 996         if (ret)
 997                 return ret;
 998
 999         /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
1000         ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
1001         if (ret)
1002                 return ret;
1003
1004         /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
1005         ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
1006         if (ret)
1007                 return ret;
1008
1009         return 0;
1010 }
1011
1012 static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
1013 {
1014         struct drm_i915_private *dev_priv = engine->i915;
1015         u8 vals[3] = { 0, 0, 0 };
1016         unsigned int i;
1017
1018         for (i = 0; i < 3; i++) {
1019                 u8 ss;
1020
1021                 /*
1022                  * Only consider slices where one, and only one, subslice has 7
1023                  * EUs
1024                  */
1025                 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
1026                         continue;
1027
1028                 /*
1029                  * subslice_7eu[i] != 0 (because of the check above) and
1030                  * ss_max == 4 (maximum number of subslices possible per slice)
1031                  *
1032                  * ->    0 <= ss <= 3;
1033                  */
1034                 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1035                 vals[i] = 3 - ss;
1036         }
1037
1038         if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1039                 return 0;
1040
1041         /* Tune IZ hashing. See intel_device_info_runtime_init() */
1042         WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1043                             GEN9_IZ_HASHING_MASK(2) |
1044                             GEN9_IZ_HASHING_MASK(1) |
1045                             GEN9_IZ_HASHING_MASK(0),
1046                             GEN9_IZ_HASHING(2, vals[2]) |
1047                             GEN9_IZ_HASHING(1, vals[1]) |
1048                             GEN9_IZ_HASHING(0, vals[0]));
1049
1050         return 0;
1051 }
1052
1053 static int skl_init_workarounds(struct intel_engine_cs *engine)
1054 {
1055         struct drm_i915_private *dev_priv = engine->i915;
1056         int ret;
1057
1058         ret = gen9_init_workarounds(engine);
1059         if (ret)
1060                 return ret;
1061
1062         /*
1063          * Actual WA is to disable percontext preemption granularity control
1064          * until D0 which is the default case so this is equivalent to
1065          * !WaDisablePerCtxtPreemptionGranularityControl:skl
1066          */
1067         if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) {
1068                 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1069                            _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1070         }
1071
1072         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) {
1073                 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1074                 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1075                            _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1076         }
1077
1078         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1079          * involving this register should also be added to WA batch as required.
1080          */
1081         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0))
1082                 /* WaDisableLSQCROPERFforOCL:skl */
1083                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1084                            GEN8_LQSC_RO_PERF_DIS);
1085
1086         /* WaEnableGapsTsvCreditFix:skl */
1087         if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
1088                 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1089                                            GEN9_GAPS_TSV_CREDIT_DISABLE));
1090         }
1091
1092         /* WaDisablePowerCompilerClockGating:skl */
1093         if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
1094                 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1095                                   BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1096
1097         /* WaBarrierPerformanceFixDisable:skl */
1098         if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
1099                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1100                                   HDC_FENCE_DEST_SLM_DISABLE |
1101                                   HDC_BARRIER_PERFORMANCE_DISABLE);
1102
1103         /* WaDisableSbeCacheDispatchPortSharing:skl */
1104         if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0))
1105                 WA_SET_BIT_MASKED(
1106                         GEN7_HALF_SLICE_CHICKEN1,
1107                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1108
1109         /* WaDisableGafsUnitClkGating:skl */
1110         WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1111
1112         /* WaDisableLSQCROPERFforOCL:skl */
1113         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1114         if (ret)
1115                 return ret;
1116
1117         return skl_tune_iz_hashing(engine);
1118 }
1119
1120 static int bxt_init_workarounds(struct intel_engine_cs *engine)
1121 {
1122         struct drm_i915_private *dev_priv = engine->i915;
1123         int ret;
1124
1125         ret = gen9_init_workarounds(engine);
1126         if (ret)
1127                 return ret;
1128
1129         /* WaStoreMultiplePTEenable:bxt */
1130         /* This is a requirement according to Hardware specification */
1131         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1132                 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1133
1134         /* WaSetClckGatingDisableMedia:bxt */
1135         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1136                 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1137                                             ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1138         }
1139
1140         /* WaDisableThreadStallDopClockGating:bxt */
1141         WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1142                           STALL_DOP_GATING_DISABLE);
1143
1144         /* WaDisablePooledEuLoadBalancingFix:bxt */
1145         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
1146                 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2,
1147                                   GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE);
1148         }
1149
1150         /* WaDisableSbeCacheDispatchPortSharing:bxt */
1151         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
1152                 WA_SET_BIT_MASKED(
1153                         GEN7_HALF_SLICE_CHICKEN1,
1154                         GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1155         }
1156
1157         /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1158         /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1159         /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
1160         /* WaDisableLSQCROPERFforOCL:bxt */
1161         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
1162                 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
1163                 if (ret)
1164                         return ret;
1165
1166                 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1167                 if (ret)
1168                         return ret;
1169         }
1170
1171         /* WaProgramL3SqcReg1DefaultForPerf:bxt */
1172         if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
1173                 I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
1174                                            L3_HIGH_PRIO_CREDITS(2));
1175
1176         /* WaInsertDummyPushConstPs:bxt */
1177         if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
1178                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1179                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1180
1181         return 0;
1182 }
1183
1184 static int kbl_init_workarounds(struct intel_engine_cs *engine)
1185 {
1186         struct drm_i915_private *dev_priv = engine->i915;
1187         int ret;
1188
1189         ret = gen9_init_workarounds(engine);
1190         if (ret)
1191                 return ret;
1192
1193         /* WaEnableGapsTsvCreditFix:kbl */
1194         I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1195                                    GEN9_GAPS_TSV_CREDIT_DISABLE));
1196
1197         /* WaDisableDynamicCreditSharing:kbl */
1198         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1199                 WA_SET_BIT(GAMT_CHKN_BIT_REG,
1200                            GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING);
1201
1202         /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
1203         if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
1204                 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1205                                   HDC_FENCE_DEST_SLM_DISABLE);
1206
1207         /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1208          * involving this register should also be added to WA batch as required.
1209          */
1210         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
1211                 /* WaDisableLSQCROPERFforOCL:kbl */
1212                 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1213                            GEN8_LQSC_RO_PERF_DIS);
1214
1215         /* WaInsertDummyPushConstPs:kbl */
1216         if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
1217                 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
1218                                   GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
1219
1220         /* WaDisableGafsUnitClkGating:kbl */
1221         WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1222
1223         /* WaDisableSbeCacheDispatchPortSharing:kbl */
1224         WA_SET_BIT_MASKED(
1225                 GEN7_HALF_SLICE_CHICKEN1,
1226                 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1227
1228         /* WaDisableLSQCROPERFforOCL:kbl */
1229         ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
1230         if (ret)
1231                 return ret;
1232
1233         return 0;
1234 }
1235
1236 int init_workarounds_ring(struct intel_engine_cs *engine)
1237 {
1238         struct drm_i915_private *dev_priv = engine->i915;
1239
1240         WARN_ON(engine->id != RCS);
1241
1242         dev_priv->workarounds.count = 0;
1243         dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
1244
1245         if (IS_BROADWELL(dev_priv))
1246                 return bdw_init_workarounds(engine);
1247
1248         if (IS_CHERRYVIEW(dev_priv))
1249                 return chv_init_workarounds(engine);
1250
1251         if (IS_SKYLAKE(dev_priv))
1252                 return skl_init_workarounds(engine);
1253
1254         if (IS_BROXTON(dev_priv))
1255                 return bxt_init_workarounds(engine);
1256
1257         if (IS_KABYLAKE(dev_priv))
1258                 return kbl_init_workarounds(engine);
1259
1260         return 0;
1261 }
1262
1263 static int init_render_ring(struct intel_engine_cs *engine)
1264 {
1265         struct drm_i915_private *dev_priv = engine->i915;
1266         int ret = init_ring_common(engine);
1267         if (ret)
1268                 return ret;
1269
1270         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1271         if (IS_GEN(dev_priv, 4, 6))
1272                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1273
1274         /* We need to disable the AsyncFlip performance optimisations in order
1275          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1276          * programmed to '1' on all products.
1277          *
1278          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1279          */
1280         if (IS_GEN(dev_priv, 6, 7))
1281                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1282
1283         /* Required for the hardware to program scanline values for waiting */
1284         /* WaEnableFlushTlbInvalidationMode:snb */
1285         if (IS_GEN6(dev_priv))
1286                 I915_WRITE(GFX_MODE,
1287                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
1288
1289         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1290         if (IS_GEN7(dev_priv))
1291                 I915_WRITE(GFX_MODE_GEN7,
1292                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1293                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
1294
1295         if (IS_GEN6(dev_priv)) {
1296                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1297                  * "If this bit is set, STCunit will have LRA as replacement
1298                  *  policy. [...] This bit must be reset.  LRA replacement
1299                  *  policy is not supported."
1300                  */
1301                 I915_WRITE(CACHE_MODE_0,
1302                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
1303         }
1304
1305         if (IS_GEN(dev_priv, 6, 7))
1306                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1307
1308         I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1309
1310         return init_workarounds_ring(engine);
1311 }
1312
1313 static void render_ring_cleanup(struct intel_engine_cs *engine)
1314 {
1315         struct drm_i915_private *dev_priv = engine->i915;
1316
1317         if (dev_priv->semaphore_obj) {
1318                 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1319                 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1320                 dev_priv->semaphore_obj = NULL;
1321         }
1322
1323         intel_fini_pipe_control(engine);
1324 }
1325
1326 static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
1327                            unsigned int num_dwords)
1328 {
1329 #define MBOX_UPDATE_DWORDS 8
1330         struct intel_engine_cs *signaller = signaller_req->engine;
1331         struct drm_i915_private *dev_priv = signaller_req->i915;
1332         struct intel_engine_cs *waiter;
1333         enum intel_engine_id id;
1334         int ret, num_rings;
1335
1336         num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1337         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1338 #undef MBOX_UPDATE_DWORDS
1339
1340         ret = intel_ring_begin(signaller_req, num_dwords);
1341         if (ret)
1342                 return ret;
1343
1344         for_each_engine_id(waiter, dev_priv, id) {
1345                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1346                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1347                         continue;
1348
1349                 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1350                 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1351                                            PIPE_CONTROL_QW_WRITE |
1352                                            PIPE_CONTROL_CS_STALL);
1353                 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1354                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1355                 intel_ring_emit(signaller, signaller_req->seqno);
1356                 intel_ring_emit(signaller, 0);
1357                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1358                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1359                 intel_ring_emit(signaller, 0);
1360         }
1361
1362         return 0;
1363 }
1364
1365 static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
1366                            unsigned int num_dwords)
1367 {
1368 #define MBOX_UPDATE_DWORDS 6
1369         struct intel_engine_cs *signaller = signaller_req->engine;
1370         struct drm_i915_private *dev_priv = signaller_req->i915;
1371         struct intel_engine_cs *waiter;
1372         enum intel_engine_id id;
1373         int ret, num_rings;
1374
1375         num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1376         num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1377 #undef MBOX_UPDATE_DWORDS
1378
1379         ret = intel_ring_begin(signaller_req, num_dwords);
1380         if (ret)
1381                 return ret;
1382
1383         for_each_engine_id(waiter, dev_priv, id) {
1384                 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
1385                 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1386                         continue;
1387
1388                 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1389                                            MI_FLUSH_DW_OP_STOREDW);
1390                 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1391                                            MI_FLUSH_DW_USE_GTT);
1392                 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
1393                 intel_ring_emit(signaller, signaller_req->seqno);
1394                 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1395                                            MI_SEMAPHORE_TARGET(waiter->hw_id));
1396                 intel_ring_emit(signaller, 0);
1397         }
1398
1399         return 0;
1400 }
1401
1402 static int gen6_signal(struct drm_i915_gem_request *signaller_req,
1403                        unsigned int num_dwords)
1404 {
1405         struct intel_engine_cs *signaller = signaller_req->engine;
1406         struct drm_i915_private *dev_priv = signaller_req->i915;
1407         struct intel_engine_cs *useless;
1408         enum intel_engine_id id;
1409         int ret, num_rings;
1410
1411 #define MBOX_UPDATE_DWORDS 3
1412         num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
1413         num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1414 #undef MBOX_UPDATE_DWORDS
1415
1416         ret = intel_ring_begin(signaller_req, num_dwords);
1417         if (ret)
1418                 return ret;
1419
1420         for_each_engine_id(useless, dev_priv, id) {
1421                 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
1422
1423                 if (i915_mmio_reg_valid(mbox_reg)) {
1424                         intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
1425                         intel_ring_emit_reg(signaller, mbox_reg);
1426                         intel_ring_emit(signaller, signaller_req->seqno);
1427                 }
1428         }
1429
1430         /* If num_dwords was rounded, make sure the tail pointer is correct */
1431         if (num_rings % 2 == 0)
1432                 intel_ring_emit(signaller, MI_NOOP);
1433
1434         return 0;
1435 }
1436
1437 /**
1438  * gen6_add_request - Update the semaphore mailbox registers
1439  *
1440  * @request - request to write to the ring
1441  *
1442  * Update the mailbox registers in the *other* rings with the current seqno.
1443  * This acts like a signal in the canonical semaphore.
1444  */
1445 static int
1446 gen6_add_request(struct drm_i915_gem_request *req)
1447 {
1448         struct intel_engine_cs *engine = req->engine;
1449         int ret;
1450
1451         if (engine->semaphore.signal)
1452                 ret = engine->semaphore.signal(req, 4);
1453         else
1454                 ret = intel_ring_begin(req, 4);
1455
1456         if (ret)
1457                 return ret;
1458
1459         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1460         intel_ring_emit(engine,
1461                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1462         intel_ring_emit(engine, req->seqno);
1463         intel_ring_emit(engine, MI_USER_INTERRUPT);
1464         __intel_ring_advance(engine);
1465
1466         return 0;
1467 }
1468
1469 static int
1470 gen8_render_add_request(struct drm_i915_gem_request *req)
1471 {
1472         struct intel_engine_cs *engine = req->engine;
1473         int ret;
1474
1475         if (engine->semaphore.signal)
1476                 ret = engine->semaphore.signal(req, 8);
1477         else
1478                 ret = intel_ring_begin(req, 8);
1479         if (ret)
1480                 return ret;
1481
1482         intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
1483         intel_ring_emit(engine, (PIPE_CONTROL_GLOBAL_GTT_IVB |
1484                                  PIPE_CONTROL_CS_STALL |
1485                                  PIPE_CONTROL_QW_WRITE));
1486         intel_ring_emit(engine, intel_hws_seqno_address(req->engine));
1487         intel_ring_emit(engine, 0);
1488         intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1489         /* We're thrashing one dword of HWS. */
1490         intel_ring_emit(engine, 0);
1491         intel_ring_emit(engine, MI_USER_INTERRUPT);
1492         intel_ring_emit(engine, MI_NOOP);
1493         __intel_ring_advance(engine);
1494
1495         return 0;
1496 }
1497
1498 static inline bool i915_gem_has_seqno_wrapped(struct drm_i915_private *dev_priv,
1499                                               u32 seqno)
1500 {
1501         return dev_priv->last_seqno < seqno;
1502 }
1503
1504 /**
1505  * intel_ring_sync - sync the waiter to the signaller on seqno
1506  *
1507  * @waiter - ring that is waiting
1508  * @signaller - ring which has, or will signal
1509  * @seqno - seqno which the waiter will block on
1510  */
1511
1512 static int
1513 gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
1514                struct intel_engine_cs *signaller,
1515                u32 seqno)
1516 {
1517         struct intel_engine_cs *waiter = waiter_req->engine;
1518         struct drm_i915_private *dev_priv = waiter_req->i915;
1519         u64 offset = GEN8_WAIT_OFFSET(waiter, signaller->id);
1520         struct i915_hw_ppgtt *ppgtt;
1521         int ret;
1522
1523         ret = intel_ring_begin(waiter_req, 4);
1524         if (ret)
1525                 return ret;
1526
1527         intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1528                                 MI_SEMAPHORE_GLOBAL_GTT |
1529                                 MI_SEMAPHORE_SAD_GTE_SDD);
1530         intel_ring_emit(waiter, seqno);
1531         intel_ring_emit(waiter, lower_32_bits(offset));
1532         intel_ring_emit(waiter, upper_32_bits(offset));
1533         intel_ring_advance(waiter);
1534
1535         /* When the !RCS engines idle waiting upon a semaphore, they lose their
1536          * pagetables and we must reload them before executing the batch.
1537          * We do this on the i915_switch_context() following the wait and
1538          * before the dispatch.
1539          */
1540         ppgtt = waiter_req->ctx->ppgtt;
1541         if (ppgtt && waiter_req->engine->id != RCS)
1542                 ppgtt->pd_dirty_rings |= intel_engine_flag(waiter_req->engine);
1543         return 0;
1544 }
1545
1546 static int
1547 gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
1548                struct intel_engine_cs *signaller,
1549                u32 seqno)
1550 {
1551         struct intel_engine_cs *waiter = waiter_req->engine;
1552         u32 dw1 = MI_SEMAPHORE_MBOX |
1553                   MI_SEMAPHORE_COMPARE |
1554                   MI_SEMAPHORE_REGISTER;
1555         u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1556         int ret;
1557
1558         /* Throughout all of the GEM code, seqno passed implies our current
1559          * seqno is >= the last seqno executed. However for hardware the
1560          * comparison is strictly greater than.
1561          */
1562         seqno -= 1;
1563
1564         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
1565
1566         ret = intel_ring_begin(waiter_req, 4);
1567         if (ret)
1568                 return ret;
1569
1570         /* If seqno wrap happened, omit the wait with no-ops */
1571         if (likely(!i915_gem_has_seqno_wrapped(waiter_req->i915, seqno))) {
1572                 intel_ring_emit(waiter, dw1 | wait_mbox);
1573                 intel_ring_emit(waiter, seqno);
1574                 intel_ring_emit(waiter, 0);
1575                 intel_ring_emit(waiter, MI_NOOP);
1576         } else {
1577                 intel_ring_emit(waiter, MI_NOOP);
1578                 intel_ring_emit(waiter, MI_NOOP);
1579                 intel_ring_emit(waiter, MI_NOOP);
1580                 intel_ring_emit(waiter, MI_NOOP);
1581         }
1582         intel_ring_advance(waiter);
1583
1584         return 0;
1585 }
1586
1587 static void
1588 gen5_seqno_barrier(struct intel_engine_cs *ring)
1589 {
1590         /* MI_STORE are internally buffered by the GPU and not flushed
1591          * either by MI_FLUSH or SyncFlush or any other combination of
1592          * MI commands.
1593          *
1594          * "Only the submission of the store operation is guaranteed.
1595          * The write result will be complete (coherent) some time later
1596          * (this is practically a finite period but there is no guaranteed
1597          * latency)."
1598          *
1599          * Empirically, we observe that we need a delay of at least 75us to
1600          * be sure that the seqno write is visible by the CPU.
1601          */
1602         usleep_range(125, 250);
1603 }
1604
1605 static void
1606 gen6_seqno_barrier(struct intel_engine_cs *engine)
1607 {
1608         struct drm_i915_private *dev_priv = engine->i915;
1609
1610         /* Workaround to force correct ordering between irq and seqno writes on
1611          * ivb (and maybe also on snb) by reading from a CS register (like
1612          * ACTHD) before reading the status page.
1613          *
1614          * Note that this effectively stalls the read by the time it takes to
1615          * do a memory transaction, which more or less ensures that the write
1616          * from the GPU has sufficient time to invalidate the CPU cacheline.
1617          * Alternatively we could delay the interrupt from the CS ring to give
1618          * the write time to land, but that would incur a delay after every
1619          * batch i.e. much more frequent than a delay when waiting for the
1620          * interrupt (with the same net latency).
1621          *
1622          * Also note that to prevent whole machine hangs on gen7, we have to
1623          * take the spinlock to guard against concurrent cacheline access.
1624          */
1625         spin_lock_irq(&dev_priv->uncore.lock);
1626         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
1627         spin_unlock_irq(&dev_priv->uncore.lock);
1628 }
1629
1630 static void
1631 gen5_irq_enable(struct intel_engine_cs *engine)
1632 {
1633         gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
1634 }
1635
1636 static void
1637 gen5_irq_disable(struct intel_engine_cs *engine)
1638 {
1639         gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
1640 }
1641
1642 static void
1643 i9xx_irq_enable(struct intel_engine_cs *engine)
1644 {
1645         struct drm_i915_private *dev_priv = engine->i915;
1646
1647         dev_priv->irq_mask &= ~engine->irq_enable_mask;
1648         I915_WRITE(IMR, dev_priv->irq_mask);
1649         POSTING_READ_FW(RING_IMR(engine->mmio_base));
1650 }
1651
1652 static void
1653 i9xx_irq_disable(struct intel_engine_cs *engine)
1654 {
1655         struct drm_i915_private *dev_priv = engine->i915;
1656
1657         dev_priv->irq_mask |= engine->irq_enable_mask;
1658         I915_WRITE(IMR, dev_priv->irq_mask);
1659 }
1660
1661 static void
1662 i8xx_irq_enable(struct intel_engine_cs *engine)
1663 {
1664         struct drm_i915_private *dev_priv = engine->i915;
1665
1666         dev_priv->irq_mask &= ~engine->irq_enable_mask;
1667         I915_WRITE16(IMR, dev_priv->irq_mask);
1668         POSTING_READ16(RING_IMR(engine->mmio_base));
1669 }
1670
1671 static void
1672 i8xx_irq_disable(struct intel_engine_cs *engine)
1673 {
1674         struct drm_i915_private *dev_priv = engine->i915;
1675
1676         dev_priv->irq_mask |= engine->irq_enable_mask;
1677         I915_WRITE16(IMR, dev_priv->irq_mask);
1678 }
1679
1680 static int
1681 bsd_ring_flush(struct drm_i915_gem_request *req,
1682                u32     invalidate_domains,
1683                u32     flush_domains)
1684 {
1685         struct intel_engine_cs *engine = req->engine;
1686         int ret;
1687
1688         ret = intel_ring_begin(req, 2);
1689         if (ret)
1690                 return ret;
1691
1692         intel_ring_emit(engine, MI_FLUSH);
1693         intel_ring_emit(engine, MI_NOOP);
1694         intel_ring_advance(engine);
1695         return 0;
1696 }
1697
1698 static int
1699 i9xx_add_request(struct drm_i915_gem_request *req)
1700 {
1701         struct intel_engine_cs *engine = req->engine;
1702         int ret;
1703
1704         ret = intel_ring_begin(req, 4);
1705         if (ret)
1706                 return ret;
1707
1708         intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1709         intel_ring_emit(engine,
1710                         I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1711         intel_ring_emit(engine, req->seqno);
1712         intel_ring_emit(engine, MI_USER_INTERRUPT);
1713         __intel_ring_advance(engine);
1714
1715         return 0;
1716 }
1717
1718 static void
1719 gen6_irq_enable(struct intel_engine_cs *engine)
1720 {
1721         struct drm_i915_private *dev_priv = engine->i915;
1722
1723         I915_WRITE_IMR(engine,
1724                        ~(engine->irq_enable_mask |
1725                          engine->irq_keep_mask));
1726         gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
1727 }
1728
1729 static void
1730 gen6_irq_disable(struct intel_engine_cs *engine)
1731 {
1732         struct drm_i915_private *dev_priv = engine->i915;
1733
1734         I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1735         gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1736 }
1737
1738 static void
1739 hsw_vebox_irq_enable(struct intel_engine_cs *engine)
1740 {
1741         struct drm_i915_private *dev_priv = engine->i915;
1742
1743         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1744         gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
1745 }
1746
1747 static void
1748 hsw_vebox_irq_disable(struct intel_engine_cs *engine)
1749 {
1750         struct drm_i915_private *dev_priv = engine->i915;
1751
1752         I915_WRITE_IMR(engine, ~0);
1753         gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
1754 }
1755
1756 static void
1757 gen8_irq_enable(struct intel_engine_cs *engine)
1758 {
1759         struct drm_i915_private *dev_priv = engine->i915;
1760
1761         I915_WRITE_IMR(engine,
1762                        ~(engine->irq_enable_mask |
1763                          engine->irq_keep_mask));
1764         POSTING_READ_FW(RING_IMR(engine->mmio_base));
1765 }
1766
1767 static void
1768 gen8_irq_disable(struct intel_engine_cs *engine)
1769 {
1770         struct drm_i915_private *dev_priv = engine->i915;
1771
1772         I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1773 }
1774
1775 static int
1776 i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
1777                          u64 offset, u32 length,
1778                          unsigned dispatch_flags)
1779 {
1780         struct intel_engine_cs *engine = req->engine;
1781         int ret;
1782
1783         ret = intel_ring_begin(req, 2);
1784         if (ret)
1785                 return ret;
1786
1787         intel_ring_emit(engine,
1788                         MI_BATCH_BUFFER_START |
1789                         MI_BATCH_GTT |
1790                         (dispatch_flags & I915_DISPATCH_SECURE ?
1791                          0 : MI_BATCH_NON_SECURE_I965));
1792         intel_ring_emit(engine, offset);
1793         intel_ring_advance(engine);
1794
1795         return 0;
1796 }
1797
1798 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1799 #define I830_BATCH_LIMIT (256*1024)
1800 #define I830_TLB_ENTRIES (2)
1801 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1802 static int
1803 i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
1804                          u64 offset, u32 len,
1805                          unsigned dispatch_flags)
1806 {
1807         struct intel_engine_cs *engine = req->engine;
1808         u32 cs_offset = engine->scratch.gtt_offset;
1809         int ret;
1810
1811         ret = intel_ring_begin(req, 6);
1812         if (ret)
1813                 return ret;
1814
1815         /* Evict the invalid PTE TLBs */
1816         intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1817         intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1818         intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1819         intel_ring_emit(engine, cs_offset);
1820         intel_ring_emit(engine, 0xdeadbeef);
1821         intel_ring_emit(engine, MI_NOOP);
1822         intel_ring_advance(engine);
1823
1824         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1825                 if (len > I830_BATCH_LIMIT)
1826                         return -ENOSPC;
1827
1828                 ret = intel_ring_begin(req, 6 + 2);
1829                 if (ret)
1830                         return ret;
1831
1832                 /* Blit the batch (which has now all relocs applied) to the
1833                  * stable batch scratch bo area (so that the CS never
1834                  * stumbles over its tlb invalidation bug) ...
1835                  */
1836                 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1837                 intel_ring_emit(engine,
1838                                 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1839                 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1840                 intel_ring_emit(engine, cs_offset);
1841                 intel_ring_emit(engine, 4096);
1842                 intel_ring_emit(engine, offset);
1843
1844                 intel_ring_emit(engine, MI_FLUSH);
1845                 intel_ring_emit(engine, MI_NOOP);
1846                 intel_ring_advance(engine);
1847
1848                 /* ... and execute it. */
1849                 offset = cs_offset;
1850         }
1851
1852         ret = intel_ring_begin(req, 2);
1853         if (ret)
1854                 return ret;
1855
1856         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1857         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1858                                           0 : MI_BATCH_NON_SECURE));
1859         intel_ring_advance(engine);
1860
1861         return 0;
1862 }
1863
1864 static int
1865 i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
1866                          u64 offset, u32 len,
1867                          unsigned dispatch_flags)
1868 {
1869         struct intel_engine_cs *engine = req->engine;
1870         int ret;
1871
1872         ret = intel_ring_begin(req, 2);
1873         if (ret)
1874                 return ret;
1875
1876         intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1877         intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1878                                           0 : MI_BATCH_NON_SECURE));
1879         intel_ring_advance(engine);
1880
1881         return 0;
1882 }
1883
1884 static void cleanup_phys_status_page(struct intel_engine_cs *engine)
1885 {
1886         struct drm_i915_private *dev_priv = engine->i915;
1887
1888         if (!dev_priv->status_page_dmah)
1889                 return;
1890
1891         drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah);
1892         engine->status_page.page_addr = NULL;
1893 }
1894
1895 static void cleanup_status_page(struct intel_engine_cs *engine)
1896 {
1897         struct drm_i915_gem_object *obj;
1898
1899         obj = engine->status_page.obj;
1900         if (obj == NULL)
1901                 return;
1902
1903         kunmap(sg_page(obj->pages->sgl));
1904         i915_gem_object_ggtt_unpin(obj);
1905         drm_gem_object_unreference(&obj->base);
1906         engine->status_page.obj = NULL;
1907 }
1908
1909 static int init_status_page(struct intel_engine_cs *engine)
1910 {
1911         struct drm_i915_gem_object *obj = engine->status_page.obj;
1912
1913         if (obj == NULL) {
1914                 unsigned flags;
1915                 int ret;
1916
1917                 obj = i915_gem_object_create(&engine->i915->drm, 4096);
1918                 if (IS_ERR(obj)) {
1919                         DRM_ERROR("Failed to allocate status page\n");
1920                         return PTR_ERR(obj);
1921                 }
1922
1923                 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1924                 if (ret)
1925                         goto err_unref;
1926
1927                 flags = 0;
1928                 if (!HAS_LLC(engine->i915))
1929                         /* On g33, we cannot place HWS above 256MiB, so
1930                          * restrict its pinning to the low mappable arena.
1931                          * Though this restriction is not documented for
1932                          * gen4, gen5, or byt, they also behave similarly
1933                          * and hang if the HWS is placed at the top of the
1934                          * GTT. To generalise, it appears that all !llc
1935                          * platforms have issues with us placing the HWS
1936                          * above the mappable region (even though we never
1937                          * actualy map it).
1938                          */
1939                         flags |= PIN_MAPPABLE;
1940                 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
1941                 if (ret) {
1942 err_unref:
1943                         drm_gem_object_unreference(&obj->base);
1944                         return ret;
1945                 }
1946
1947                 engine->status_page.obj = obj;
1948         }
1949
1950         engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1951         engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1952         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
1953
1954         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1955                         engine->name, engine->status_page.gfx_addr);
1956
1957         return 0;
1958 }
1959
1960 static int init_phys_status_page(struct intel_engine_cs *engine)
1961 {
1962         struct drm_i915_private *dev_priv = engine->i915;
1963
1964         if (!dev_priv->status_page_dmah) {
1965                 dev_priv->status_page_dmah =
1966                         drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE);
1967                 if (!dev_priv->status_page_dmah)
1968                         return -ENOMEM;
1969         }
1970
1971         engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1972         memset(engine->status_page.page_addr, 0, PAGE_SIZE);
1973
1974         return 0;
1975 }
1976
1977 void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
1978 {
1979         GEM_BUG_ON(ringbuf->vma == NULL);
1980         GEM_BUG_ON(ringbuf->virtual_start == NULL);
1981
1982         if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
1983                 i915_gem_object_unpin_map(ringbuf->obj);
1984         else
1985                 i915_vma_unpin_iomap(ringbuf->vma);
1986         ringbuf->virtual_start = NULL;
1987
1988         i915_gem_object_ggtt_unpin(ringbuf->obj);
1989         ringbuf->vma = NULL;
1990 }
1991
1992 int intel_pin_and_map_ringbuffer_obj(struct drm_i915_private *dev_priv,
1993                                      struct intel_ringbuffer *ringbuf)
1994 {
1995         struct drm_i915_gem_object *obj = ringbuf->obj;
1996         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1997         unsigned flags = PIN_OFFSET_BIAS | 4096;
1998         void *addr;
1999         int ret;
2000
2001         if (HAS_LLC(dev_priv) && !obj->stolen) {
2002                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
2003                 if (ret)
2004                         return ret;
2005
2006                 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2007                 if (ret)
2008                         goto err_unpin;
2009
2010                 addr = i915_gem_object_pin_map(obj);
2011                 if (IS_ERR(addr)) {
2012                         ret = PTR_ERR(addr);
2013                         goto err_unpin;
2014                 }
2015         } else {
2016                 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2017                                             flags | PIN_MAPPABLE);
2018                 if (ret)
2019                         return ret;
2020
2021                 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2022                 if (ret)
2023                         goto err_unpin;
2024
2025                 /* Access through the GTT requires the device to be awake. */
2026                 assert_rpm_wakelock_held(dev_priv);
2027
2028                 addr = i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj));
2029                 if (IS_ERR(addr)) {
2030                         ret = PTR_ERR(addr);
2031                         goto err_unpin;
2032                 }
2033         }
2034
2035         ringbuf->virtual_start = addr;
2036         ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2037         return 0;
2038
2039 err_unpin:
2040         i915_gem_object_ggtt_unpin(obj);
2041         return ret;
2042 }
2043
2044 static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2045 {
2046         drm_gem_object_unreference(&ringbuf->obj->base);
2047         ringbuf->obj = NULL;
2048 }
2049
2050 static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2051                                       struct intel_ringbuffer *ringbuf)
2052 {
2053         struct drm_i915_gem_object *obj;
2054
2055         obj = NULL;
2056         if (!HAS_LLC(dev))
2057                 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
2058         if (obj == NULL)
2059                 obj = i915_gem_object_create(dev, ringbuf->size);
2060         if (IS_ERR(obj))
2061                 return PTR_ERR(obj);
2062
2063         /* mark ring buffers as read-only from GPU side by default */
2064         obj->gt_ro = 1;
2065
2066         ringbuf->obj = obj;
2067
2068         return 0;
2069 }
2070
2071 struct intel_ringbuffer *
2072 intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2073 {
2074         struct intel_ringbuffer *ring;
2075         int ret;
2076
2077         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
2078         if (ring == NULL) {
2079                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2080                                  engine->name);
2081                 return ERR_PTR(-ENOMEM);
2082         }
2083
2084         ring->engine = engine;
2085         list_add(&ring->link, &engine->buffers);
2086
2087         ring->size = size;
2088         /* Workaround an erratum on the i830 which causes a hang if
2089          * the TAIL pointer points to within the last 2 cachelines
2090          * of the buffer.
2091          */
2092         ring->effective_size = size;
2093         if (IS_I830(engine->i915) || IS_845G(engine->i915))
2094                 ring->effective_size -= 2 * CACHELINE_BYTES;
2095
2096         ring->last_retired_head = -1;
2097         intel_ring_update_space(ring);
2098
2099         ret = intel_alloc_ringbuffer_obj(&engine->i915->drm, ring);
2100         if (ret) {
2101                 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2102                                  engine->name, ret);
2103                 list_del(&ring->link);
2104                 kfree(ring);
2105                 return ERR_PTR(ret);
2106         }
2107
2108         return ring;
2109 }
2110
2111 void
2112 intel_ringbuffer_free(struct intel_ringbuffer *ring)
2113 {
2114         intel_destroy_ringbuffer_obj(ring);
2115         list_del(&ring->link);
2116         kfree(ring);
2117 }
2118
2119 static int intel_ring_context_pin(struct i915_gem_context *ctx,
2120                                   struct intel_engine_cs *engine)
2121 {
2122         struct intel_context *ce = &ctx->engine[engine->id];
2123         int ret;
2124
2125         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
2126
2127         if (ce->pin_count++)
2128                 return 0;
2129
2130         if (ce->state) {
2131                 ret = i915_gem_obj_ggtt_pin(ce->state, ctx->ggtt_alignment, 0);
2132                 if (ret)
2133                         goto error;
2134         }
2135
2136         /* The kernel context is only used as a placeholder for flushing the
2137          * active context. It is never used for submitting user rendering and
2138          * as such never requires the golden render context, and so we can skip
2139          * emitting it when we switch to the kernel context. This is required
2140          * as during eviction we cannot allocate and pin the renderstate in
2141          * order to initialise the context.
2142          */
2143         if (ctx == ctx->i915->kernel_context)
2144                 ce->initialised = true;
2145
2146         i915_gem_context_reference(ctx);
2147         return 0;
2148
2149 error:
2150         ce->pin_count = 0;
2151         return ret;
2152 }
2153
2154 static void intel_ring_context_unpin(struct i915_gem_context *ctx,
2155                                      struct intel_engine_cs *engine)
2156 {
2157         struct intel_context *ce = &ctx->engine[engine->id];
2158
2159         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
2160
2161         if (--ce->pin_count)
2162                 return;
2163
2164         if (ce->state)
2165                 i915_gem_object_ggtt_unpin(ce->state);
2166
2167         i915_gem_context_unreference(ctx);
2168 }
2169
2170 static int intel_init_ring_buffer(struct drm_device *dev,
2171                                   struct intel_engine_cs *engine)
2172 {
2173         struct drm_i915_private *dev_priv = to_i915(dev);
2174         struct intel_ringbuffer *ringbuf;
2175         int ret;
2176
2177         WARN_ON(engine->buffer);
2178
2179         engine->i915 = dev_priv;
2180         INIT_LIST_HEAD(&engine->active_list);
2181         INIT_LIST_HEAD(&engine->request_list);
2182         INIT_LIST_HEAD(&engine->execlist_queue);
2183         INIT_LIST_HEAD(&engine->buffers);
2184         i915_gem_batch_pool_init(dev, &engine->batch_pool);
2185         memset(engine->semaphore.sync_seqno, 0,
2186                sizeof(engine->semaphore.sync_seqno));
2187
2188         ret = intel_engine_init_breadcrumbs(engine);
2189         if (ret)
2190                 goto error;
2191
2192         /* We may need to do things with the shrinker which
2193          * require us to immediately switch back to the default
2194          * context. This can cause a problem as pinning the
2195          * default context also requires GTT space which may not
2196          * be available. To avoid this we always pin the default
2197          * context.
2198          */
2199         ret = intel_ring_context_pin(dev_priv->kernel_context, engine);
2200         if (ret)
2201                 goto error;
2202
2203         ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
2204         if (IS_ERR(ringbuf)) {
2205                 ret = PTR_ERR(ringbuf);
2206                 goto error;
2207         }
2208         engine->buffer = ringbuf;
2209
2210         if (I915_NEED_GFX_HWS(dev_priv)) {
2211                 ret = init_status_page(engine);
2212                 if (ret)
2213                         goto error;
2214         } else {
2215                 WARN_ON(engine->id != RCS);
2216                 ret = init_phys_status_page(engine);
2217                 if (ret)
2218                         goto error;
2219         }
2220
2221         ret = intel_pin_and_map_ringbuffer_obj(dev_priv, ringbuf);
2222         if (ret) {
2223                 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
2224                                 engine->name, ret);
2225                 intel_destroy_ringbuffer_obj(ringbuf);
2226                 goto error;
2227         }
2228
2229         ret = i915_cmd_parser_init_ring(engine);
2230         if (ret)
2231                 goto error;
2232
2233         return 0;
2234
2235 error:
2236         intel_cleanup_engine(engine);
2237         return ret;
2238 }
2239
2240 void intel_cleanup_engine(struct intel_engine_cs *engine)
2241 {
2242         struct drm_i915_private *dev_priv;
2243
2244         if (!intel_engine_initialized(engine))
2245                 return;
2246
2247         dev_priv = engine->i915;
2248
2249         if (engine->buffer) {
2250                 intel_stop_engine(engine);
2251                 WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
2252
2253                 intel_unpin_ringbuffer_obj(engine->buffer);
2254                 intel_ringbuffer_free(engine->buffer);
2255                 engine->buffer = NULL;
2256         }
2257
2258         if (engine->cleanup)
2259                 engine->cleanup(engine);
2260
2261         if (I915_NEED_GFX_HWS(dev_priv)) {
2262                 cleanup_status_page(engine);
2263         } else {
2264                 WARN_ON(engine->id != RCS);
2265                 cleanup_phys_status_page(engine);
2266         }
2267
2268         i915_cmd_parser_fini_ring(engine);
2269         i915_gem_batch_pool_fini(&engine->batch_pool);
2270         intel_engine_fini_breadcrumbs(engine);
2271
2272         intel_ring_context_unpin(dev_priv->kernel_context, engine);
2273
2274         engine->i915 = NULL;
2275 }
2276
2277 int intel_engine_idle(struct intel_engine_cs *engine)
2278 {
2279         struct drm_i915_gem_request *req;
2280
2281         /* Wait upon the last request to be completed */
2282         if (list_empty(&engine->request_list))
2283                 return 0;
2284
2285         req = list_entry(engine->request_list.prev,
2286                          struct drm_i915_gem_request,
2287                          list);
2288
2289         /* Make sure we do not trigger any retires */
2290         return __i915_wait_request(req,
2291                                    req->i915->mm.interruptible,
2292                                    NULL, NULL);
2293 }
2294
2295 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
2296 {
2297         int ret;
2298
2299         /* Flush enough space to reduce the likelihood of waiting after
2300          * we start building the request - in which case we will just
2301          * have to repeat work.
2302          */
2303         request->reserved_space += LEGACY_REQUEST_SIZE;
2304
2305         request->ringbuf = request->engine->buffer;
2306
2307         ret = intel_ring_begin(request, 0);
2308         if (ret)
2309                 return ret;
2310
2311         request->reserved_space -= LEGACY_REQUEST_SIZE;
2312         return 0;
2313 }
2314
2315 static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2316 {
2317         struct intel_ringbuffer *ringbuf = req->ringbuf;
2318         struct intel_engine_cs *engine = req->engine;
2319         struct drm_i915_gem_request *target;
2320
2321         intel_ring_update_space(ringbuf);
2322         if (ringbuf->space >= bytes)
2323                 return 0;
2324
2325         /*
2326          * Space is reserved in the ringbuffer for finalising the request,
2327          * as that cannot be allowed to fail. During request finalisation,
2328          * reserved_space is set to 0 to stop the overallocation and the
2329          * assumption is that then we never need to wait (which has the
2330          * risk of failing with EINTR).
2331          *
2332          * See also i915_gem_request_alloc() and i915_add_request().
2333          */
2334         GEM_BUG_ON(!req->reserved_space);
2335
2336         list_for_each_entry(target, &engine->request_list, list) {
2337                 unsigned space;
2338
2339                 /*
2340                  * The request queue is per-engine, so can contain requests
2341                  * from multiple ringbuffers. Here, we must ignore any that
2342                  * aren't from the ringbuffer we're considering.
2343                  */
2344                 if (target->ringbuf != ringbuf)
2345                         continue;
2346
2347                 /* Would completion of this request free enough space? */
2348                 space = __intel_ring_space(target->postfix, ringbuf->tail,
2349                                            ringbuf->size);
2350                 if (space >= bytes)
2351                         break;
2352         }
2353
2354         if (WARN_ON(&target->list == &engine->request_list))
2355                 return -ENOSPC;
2356
2357         return i915_wait_request(target);
2358 }
2359
2360 int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
2361 {
2362         struct intel_ringbuffer *ringbuf = req->ringbuf;
2363         int remain_actual = ringbuf->size - ringbuf->tail;
2364         int remain_usable = ringbuf->effective_size - ringbuf->tail;
2365         int bytes = num_dwords * sizeof(u32);
2366         int total_bytes, wait_bytes;
2367         bool need_wrap = false;
2368
2369         total_bytes = bytes + req->reserved_space;
2370
2371         if (unlikely(bytes > remain_usable)) {
2372                 /*
2373                  * Not enough space for the basic request. So need to flush
2374                  * out the remainder and then wait for base + reserved.
2375                  */
2376                 wait_bytes = remain_actual + total_bytes;
2377                 need_wrap = true;
2378         } else if (unlikely(total_bytes > remain_usable)) {
2379                 /*
2380                  * The base request will fit but the reserved space
2381                  * falls off the end. So we don't need an immediate wrap
2382                  * and only need to effectively wait for the reserved
2383                  * size space from the start of ringbuffer.
2384                  */
2385                 wait_bytes = remain_actual + req->reserved_space;
2386         } else {
2387                 /* No wrapping required, just waiting. */
2388                 wait_bytes = total_bytes;
2389         }
2390
2391         if (wait_bytes > ringbuf->space) {
2392                 int ret = wait_for_space(req, wait_bytes);
2393                 if (unlikely(ret))
2394                         return ret;
2395
2396                 intel_ring_update_space(ringbuf);
2397                 if (unlikely(ringbuf->space < wait_bytes))
2398                         return -EAGAIN;
2399         }
2400
2401         if (unlikely(need_wrap)) {
2402                 GEM_BUG_ON(remain_actual > ringbuf->space);
2403                 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
2404
2405                 /* Fill the tail with MI_NOOP */
2406                 memset(ringbuf->virtual_start + ringbuf->tail,
2407                        0, remain_actual);
2408                 ringbuf->tail = 0;
2409                 ringbuf->space -= remain_actual;
2410         }
2411
2412         ringbuf->space -= bytes;
2413         GEM_BUG_ON(ringbuf->space < 0);
2414         return 0;
2415 }
2416
2417 /* Align the ring tail to a cacheline boundary */
2418 int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
2419 {
2420         struct intel_engine_cs *engine = req->engine;
2421         int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
2422         int ret;
2423
2424         if (num_dwords == 0)
2425                 return 0;
2426
2427         num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
2428         ret = intel_ring_begin(req, num_dwords);
2429         if (ret)
2430                 return ret;
2431
2432         while (num_dwords--)
2433                 intel_ring_emit(engine, MI_NOOP);
2434
2435         intel_ring_advance(engine);
2436
2437         return 0;
2438 }
2439
2440 void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
2441 {
2442         struct drm_i915_private *dev_priv = engine->i915;
2443
2444         /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2445          * so long as the semaphore value in the register/page is greater
2446          * than the sync value), so whenever we reset the seqno,
2447          * so long as we reset the tracking semaphore value to 0, it will
2448          * always be before the next request's seqno. If we don't reset
2449          * the semaphore value, then when the seqno moves backwards all
2450          * future waits will complete instantly (causing rendering corruption).
2451          */
2452         if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
2453                 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2454                 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
2455                 if (HAS_VEBOX(dev_priv))
2456                         I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
2457         }
2458         if (dev_priv->semaphore_obj) {
2459                 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2460                 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2461                 void *semaphores = kmap(page);
2462                 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2463                        0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2464                 kunmap(page);
2465         }
2466         memset(engine->semaphore.sync_seqno, 0,
2467                sizeof(engine->semaphore.sync_seqno));
2468
2469         intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
2470         if (engine->irq_seqno_barrier)
2471                 engine->irq_seqno_barrier(engine);
2472         engine->last_submitted_seqno = seqno;
2473
2474         engine->hangcheck.seqno = seqno;
2475
2476         /* After manually advancing the seqno, fake the interrupt in case
2477          * there are any waiters for that seqno.
2478          */
2479         rcu_read_lock();
2480         intel_engine_wakeup(engine);
2481         rcu_read_unlock();
2482 }
2483
2484 static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
2485                                      u32 value)
2486 {
2487         struct drm_i915_private *dev_priv = engine->i915;
2488
2489         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2490
2491        /* Every tail move must follow the sequence below */
2492
2493         /* Disable notification that the ring is IDLE. The GT
2494          * will then assume that it is busy and bring it out of rc6.
2495          */
2496         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
2497                       _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2498
2499         /* Clear the context id. Here be magic! */
2500         I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
2501
2502         /* Wait for the ring not to be idle, i.e. for it to wake up. */
2503         if (intel_wait_for_register_fw(dev_priv,
2504                                        GEN6_BSD_SLEEP_PSMI_CONTROL,
2505                                        GEN6_BSD_SLEEP_INDICATOR,
2506                                        0,
2507                                        50))
2508                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2509
2510         /* Now that the ring is fully powered up, update the tail */
2511         I915_WRITE_FW(RING_TAIL(engine->mmio_base), value);
2512         POSTING_READ_FW(RING_TAIL(engine->mmio_base));
2513
2514         /* Let the ring send IDLE messages to the GT again,
2515          * and so let it sleep to conserve power when idle.
2516          */
2517         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
2518                       _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2519
2520         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2521 }
2522
2523 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
2524                                u32 invalidate, u32 flush)
2525 {
2526         struct intel_engine_cs *engine = req->engine;
2527         uint32_t cmd;
2528         int ret;
2529
2530         ret = intel_ring_begin(req, 4);
2531         if (ret)
2532                 return ret;
2533
2534         cmd = MI_FLUSH_DW;
2535         if (INTEL_GEN(req->i915) >= 8)
2536                 cmd += 1;
2537
2538         /* We always require a command barrier so that subsequent
2539          * commands, such as breadcrumb interrupts, are strictly ordered
2540          * wrt the contents of the write cache being flushed to memory
2541          * (and thus being coherent from the CPU).
2542          */
2543         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2544
2545         /*
2546          * Bspec vol 1c.5 - video engine command streamer:
2547          * "If ENABLED, all TLBs will be invalidated once the flush
2548          * operation is complete. This bit is only valid when the
2549          * Post-Sync Operation field is a value of 1h or 3h."
2550          */
2551         if (invalidate & I915_GEM_GPU_DOMAINS)
2552                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2553
2554         intel_ring_emit(engine, cmd);
2555         intel_ring_emit(engine,
2556                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2557         if (INTEL_GEN(req->i915) >= 8) {
2558                 intel_ring_emit(engine, 0); /* upper addr */
2559                 intel_ring_emit(engine, 0); /* value */
2560         } else  {
2561                 intel_ring_emit(engine, 0);
2562                 intel_ring_emit(engine, MI_NOOP);
2563         }
2564         intel_ring_advance(engine);
2565         return 0;
2566 }
2567
2568 static int
2569 gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2570                               u64 offset, u32 len,
2571                               unsigned dispatch_flags)
2572 {
2573         struct intel_engine_cs *engine = req->engine;
2574         bool ppgtt = USES_PPGTT(engine->dev) &&
2575                         !(dispatch_flags & I915_DISPATCH_SECURE);
2576         int ret;
2577
2578         ret = intel_ring_begin(req, 4);
2579         if (ret)
2580                 return ret;
2581
2582         /* FIXME(BDW): Address space and security selectors. */
2583         intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
2584                         (dispatch_flags & I915_DISPATCH_RS ?
2585                          MI_BATCH_RESOURCE_STREAMER : 0));
2586         intel_ring_emit(engine, lower_32_bits(offset));
2587         intel_ring_emit(engine, upper_32_bits(offset));
2588         intel_ring_emit(engine, MI_NOOP);
2589         intel_ring_advance(engine);
2590
2591         return 0;
2592 }
2593
2594 static int
2595 hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2596                              u64 offset, u32 len,
2597                              unsigned dispatch_flags)
2598 {
2599         struct intel_engine_cs *engine = req->engine;
2600         int ret;
2601
2602         ret = intel_ring_begin(req, 2);
2603         if (ret)
2604                 return ret;
2605
2606         intel_ring_emit(engine,
2607                         MI_BATCH_BUFFER_START |
2608                         (dispatch_flags & I915_DISPATCH_SECURE ?
2609                          0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2610                         (dispatch_flags & I915_DISPATCH_RS ?
2611                          MI_BATCH_RESOURCE_STREAMER : 0));
2612         /* bit0-7 is the length on GEN6+ */
2613         intel_ring_emit(engine, offset);
2614         intel_ring_advance(engine);
2615
2616         return 0;
2617 }
2618
2619 static int
2620 gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
2621                               u64 offset, u32 len,
2622                               unsigned dispatch_flags)
2623 {
2624         struct intel_engine_cs *engine = req->engine;
2625         int ret;
2626
2627         ret = intel_ring_begin(req, 2);
2628         if (ret)
2629                 return ret;
2630
2631         intel_ring_emit(engine,
2632                         MI_BATCH_BUFFER_START |
2633                         (dispatch_flags & I915_DISPATCH_SECURE ?
2634                          0 : MI_BATCH_NON_SECURE_I965));
2635         /* bit0-7 is the length on GEN6+ */
2636         intel_ring_emit(engine, offset);
2637         intel_ring_advance(engine);
2638
2639         return 0;
2640 }
2641
2642 /* Blitter support (SandyBridge+) */
2643
2644 static int gen6_ring_flush(struct drm_i915_gem_request *req,
2645                            u32 invalidate, u32 flush)
2646 {
2647         struct intel_engine_cs *engine = req->engine;
2648         uint32_t cmd;
2649         int ret;
2650
2651         ret = intel_ring_begin(req, 4);
2652         if (ret)
2653                 return ret;
2654
2655         cmd = MI_FLUSH_DW;
2656         if (INTEL_GEN(req->i915) >= 8)
2657                 cmd += 1;
2658
2659         /* We always require a command barrier so that subsequent
2660          * commands, such as breadcrumb interrupts, are strictly ordered
2661          * wrt the contents of the write cache being flushed to memory
2662          * (and thus being coherent from the CPU).
2663          */
2664         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2665
2666         /*
2667          * Bspec vol 1c.3 - blitter engine command streamer:
2668          * "If ENABLED, all TLBs will be invalidated once the flush
2669          * operation is complete. This bit is only valid when the
2670          * Post-Sync Operation field is a value of 1h or 3h."
2671          */
2672         if (invalidate & I915_GEM_DOMAIN_RENDER)
2673                 cmd |= MI_INVALIDATE_TLB;
2674         intel_ring_emit(engine, cmd);
2675         intel_ring_emit(engine,
2676                         I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2677         if (INTEL_GEN(req->i915) >= 8) {
2678                 intel_ring_emit(engine, 0); /* upper addr */
2679                 intel_ring_emit(engine, 0); /* value */
2680         } else  {
2681                 intel_ring_emit(engine, 0);
2682                 intel_ring_emit(engine, MI_NOOP);
2683         }
2684         intel_ring_advance(engine);
2685
2686         return 0;
2687 }
2688
2689 static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
2690                                        struct intel_engine_cs *engine)
2691 {
2692         struct drm_i915_gem_object *obj;
2693         int ret, i;
2694
2695         if (!i915_semaphore_is_enabled(dev_priv))
2696                 return;
2697
2698         if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore_obj) {
2699                 obj = i915_gem_object_create(&dev_priv->drm, 4096);
2700                 if (IS_ERR(obj)) {
2701                         DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2702                         i915.semaphores = 0;
2703                 } else {
2704                         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2705                         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2706                         if (ret != 0) {
2707                                 drm_gem_object_unreference(&obj->base);
2708                                 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2709                                 i915.semaphores = 0;
2710                         } else {
2711                                 dev_priv->semaphore_obj = obj;
2712                         }
2713                 }
2714         }
2715
2716         if (!i915_semaphore_is_enabled(dev_priv))
2717                 return;
2718
2719         if (INTEL_GEN(dev_priv) >= 8) {
2720                 u64 offset = i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj);
2721
2722                 engine->semaphore.sync_to = gen8_ring_sync;
2723                 engine->semaphore.signal = gen8_xcs_signal;
2724
2725                 for (i = 0; i < I915_NUM_ENGINES; i++) {
2726                         u64 ring_offset;
2727
2728                         if (i != engine->id)
2729                                 ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i);
2730                         else
2731                                 ring_offset = MI_SEMAPHORE_SYNC_INVALID;
2732
2733                         engine->semaphore.signal_ggtt[i] = ring_offset;
2734                 }
2735         } else if (INTEL_GEN(dev_priv) >= 6) {
2736                 engine->semaphore.sync_to = gen6_ring_sync;
2737                 engine->semaphore.signal = gen6_signal;
2738
2739                 /*
2740                  * The current semaphore is only applied on pre-gen8
2741                  * platform.  And there is no VCS2 ring on the pre-gen8
2742                  * platform. So the semaphore between RCS and VCS2 is
2743                  * initialized as INVALID.  Gen8 will initialize the
2744                  * sema between VCS2 and RCS later.
2745                  */
2746                 for (i = 0; i < I915_NUM_ENGINES; i++) {
2747                         static const struct {
2748                                 u32 wait_mbox;
2749                                 i915_reg_t mbox_reg;
2750                         } sem_data[I915_NUM_ENGINES][I915_NUM_ENGINES] = {
2751                                 [RCS] = {
2752                                         [VCS] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RV,  .mbox_reg = GEN6_VRSYNC },
2753                                         [BCS] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RB,  .mbox_reg = GEN6_BRSYNC },
2754                                         [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
2755                                 },
2756                                 [VCS] = {
2757                                         [RCS] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VR,  .mbox_reg = GEN6_RVSYNC },
2758                                         [BCS] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VB,  .mbox_reg = GEN6_BVSYNC },
2759                                         [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
2760                                 },
2761                                 [BCS] = {
2762                                         [RCS] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BR,  .mbox_reg = GEN6_RBSYNC },
2763                                         [VCS] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BV,  .mbox_reg = GEN6_VBSYNC },
2764                                         [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
2765                                 },
2766                                 [VECS] = {
2767                                         [RCS] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
2768                                         [VCS] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
2769                                         [BCS] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
2770                                 },
2771                         };
2772                         u32 wait_mbox;
2773                         i915_reg_t mbox_reg;
2774
2775                         if (i == engine->id || i == VCS2) {
2776                                 wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
2777                                 mbox_reg = GEN6_NOSYNC;
2778                         } else {
2779                                 wait_mbox = sem_data[engine->id][i].wait_mbox;
2780                                 mbox_reg = sem_data[engine->id][i].mbox_reg;
2781                         }
2782
2783                         engine->semaphore.mbox.wait[i] = wait_mbox;
2784                         engine->semaphore.mbox.signal[i] = mbox_reg;
2785                 }
2786         }
2787 }
2788
2789 static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
2790                                 struct intel_engine_cs *engine)
2791 {
2792         if (INTEL_GEN(dev_priv) >= 8) {
2793                 engine->irq_enable = gen8_irq_enable;
2794                 engine->irq_disable = gen8_irq_disable;
2795                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2796         } else if (INTEL_GEN(dev_priv) >= 6) {
2797                 engine->irq_enable = gen6_irq_enable;
2798                 engine->irq_disable = gen6_irq_disable;
2799                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2800         } else if (INTEL_GEN(dev_priv) >= 5) {
2801                 engine->irq_enable = gen5_irq_enable;
2802                 engine->irq_disable = gen5_irq_disable;
2803                 engine->irq_seqno_barrier = gen5_seqno_barrier;
2804         } else if (INTEL_GEN(dev_priv) >= 3) {
2805                 engine->irq_enable = i9xx_irq_enable;
2806                 engine->irq_disable = i9xx_irq_disable;
2807         } else {
2808                 engine->irq_enable = i8xx_irq_enable;
2809                 engine->irq_disable = i8xx_irq_disable;
2810         }
2811 }
2812
2813 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
2814                                       struct intel_engine_cs *engine)
2815 {
2816         engine->init_hw = init_ring_common;
2817         engine->write_tail = ring_write_tail;
2818
2819         engine->add_request = i9xx_add_request;
2820         if (INTEL_GEN(dev_priv) >= 6)
2821                 engine->add_request = gen6_add_request;
2822
2823         if (INTEL_GEN(dev_priv) >= 8)
2824                 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2825         else if (INTEL_GEN(dev_priv) >= 6)
2826                 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2827         else if (INTEL_GEN(dev_priv) >= 4)
2828                 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
2829         else if (IS_I830(dev_priv) || IS_845G(dev_priv))
2830                 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
2831         else
2832                 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2833
2834         intel_ring_init_irq(dev_priv, engine);
2835         intel_ring_init_semaphores(dev_priv, engine);
2836 }
2837
2838 int intel_init_render_ring_buffer(struct drm_device *dev)
2839 {
2840         struct drm_i915_private *dev_priv = to_i915(dev);
2841         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
2842         int ret;
2843
2844         engine->name = "render ring";
2845         engine->id = RCS;
2846         engine->exec_id = I915_EXEC_RENDER;
2847         engine->hw_id = 0;
2848         engine->mmio_base = RENDER_RING_BASE;
2849
2850         intel_ring_default_vfuncs(dev_priv, engine);
2851
2852         engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2853         if (HAS_L3_DPF(dev_priv))
2854                 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2855
2856         if (INTEL_GEN(dev_priv) >= 8) {
2857                 engine->init_context = intel_rcs_ctx_init;
2858                 engine->add_request = gen8_render_add_request;
2859                 engine->flush = gen8_render_ring_flush;
2860                 if (i915_semaphore_is_enabled(dev_priv))
2861                         engine->semaphore.signal = gen8_rcs_signal;
2862         } else if (INTEL_GEN(dev_priv) >= 6) {
2863                 engine->init_context = intel_rcs_ctx_init;
2864                 engine->flush = gen7_render_ring_flush;
2865                 if (IS_GEN6(dev_priv))
2866                         engine->flush = gen6_render_ring_flush;
2867         } else if (IS_GEN5(dev_priv)) {
2868                 engine->flush = gen4_render_ring_flush;
2869         } else {
2870                 if (INTEL_GEN(dev_priv) < 4)
2871                         engine->flush = gen2_render_ring_flush;
2872                 else
2873                         engine->flush = gen4_render_ring_flush;
2874                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2875         }
2876
2877         if (IS_HASWELL(dev_priv))
2878                 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
2879
2880         engine->init_hw = init_render_ring;
2881         engine->cleanup = render_ring_cleanup;
2882
2883         ret = intel_init_ring_buffer(dev, engine);
2884         if (ret)
2885                 return ret;
2886
2887         if (INTEL_GEN(dev_priv) >= 6) {
2888                 ret = intel_init_pipe_control(engine, 4096);
2889                 if (ret)
2890                         return ret;
2891         } else if (HAS_BROKEN_CS_TLB(dev_priv)) {
2892                 ret = intel_init_pipe_control(engine, I830_WA_SIZE);
2893                 if (ret)
2894                         return ret;
2895         }
2896
2897         return 0;
2898 }
2899
2900 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2901 {
2902         struct drm_i915_private *dev_priv = to_i915(dev);
2903         struct intel_engine_cs *engine = &dev_priv->engine[VCS];
2904
2905         engine->name = "bsd ring";
2906         engine->id = VCS;
2907         engine->exec_id = I915_EXEC_BSD;
2908         engine->hw_id = 1;
2909
2910         intel_ring_default_vfuncs(dev_priv, engine);
2911
2912         if (INTEL_GEN(dev_priv) >= 6) {
2913                 engine->mmio_base = GEN6_BSD_RING_BASE;
2914                 /* gen6 bsd needs a special wa for tail updates */
2915                 if (IS_GEN6(dev_priv))
2916                         engine->write_tail = gen6_bsd_ring_write_tail;
2917                 engine->flush = gen6_bsd_ring_flush;
2918                 if (INTEL_GEN(dev_priv) >= 8)
2919                         engine->irq_enable_mask =
2920                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2921                 else
2922                         engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2923         } else {
2924                 engine->mmio_base = BSD_RING_BASE;
2925                 engine->flush = bsd_ring_flush;
2926                 if (IS_GEN5(dev_priv))
2927                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2928                 else
2929                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2930         }
2931
2932         return intel_init_ring_buffer(dev, engine);
2933 }
2934
2935 /**
2936  * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
2937  */
2938 int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2939 {
2940         struct drm_i915_private *dev_priv = to_i915(dev);
2941         struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
2942
2943         engine->name = "bsd2 ring";
2944         engine->id = VCS2;
2945         engine->exec_id = I915_EXEC_BSD;
2946         engine->hw_id = 4;
2947         engine->mmio_base = GEN8_BSD2_RING_BASE;
2948
2949         intel_ring_default_vfuncs(dev_priv, engine);
2950
2951         engine->flush = gen6_bsd_ring_flush;
2952         engine->irq_enable_mask =
2953                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
2954
2955         return intel_init_ring_buffer(dev, engine);
2956 }
2957
2958 int intel_init_blt_ring_buffer(struct drm_device *dev)
2959 {
2960         struct drm_i915_private *dev_priv = to_i915(dev);
2961         struct intel_engine_cs *engine = &dev_priv->engine[BCS];
2962
2963         engine->name = "blitter ring";
2964         engine->id = BCS;
2965         engine->exec_id = I915_EXEC_BLT;
2966         engine->hw_id = 2;
2967         engine->mmio_base = BLT_RING_BASE;
2968
2969         intel_ring_default_vfuncs(dev_priv, engine);
2970
2971         engine->flush = gen6_ring_flush;
2972         if (INTEL_GEN(dev_priv) >= 8)
2973                 engine->irq_enable_mask =
2974                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2975         else
2976                 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2977
2978         return intel_init_ring_buffer(dev, engine);
2979 }
2980
2981 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2982 {
2983         struct drm_i915_private *dev_priv = to_i915(dev);
2984         struct intel_engine_cs *engine = &dev_priv->engine[VECS];
2985
2986         engine->name = "video enhancement ring";
2987         engine->id = VECS;
2988         engine->exec_id = I915_EXEC_VEBOX;
2989         engine->hw_id = 3;
2990         engine->mmio_base = VEBOX_RING_BASE;
2991
2992         intel_ring_default_vfuncs(dev_priv, engine);
2993
2994         engine->flush = gen6_ring_flush;
2995
2996         if (INTEL_GEN(dev_priv) >= 8) {
2997                 engine->irq_enable_mask =
2998                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2999         } else {
3000                 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3001                 engine->irq_enable = hsw_vebox_irq_enable;
3002                 engine->irq_disable = hsw_vebox_irq_disable;
3003         }
3004
3005         return intel_init_ring_buffer(dev, engine);
3006 }
3007
3008 int
3009 intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
3010 {
3011         struct intel_engine_cs *engine = req->engine;
3012         int ret;
3013
3014         if (!engine->gpu_caches_dirty)
3015                 return 0;
3016
3017         ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
3018         if (ret)
3019                 return ret;
3020
3021         trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
3022
3023         engine->gpu_caches_dirty = false;
3024         return 0;
3025 }
3026
3027 int
3028 intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
3029 {
3030         struct intel_engine_cs *engine = req->engine;
3031         uint32_t flush_domains;
3032         int ret;
3033
3034         flush_domains = 0;
3035         if (engine->gpu_caches_dirty)
3036                 flush_domains = I915_GEM_GPU_DOMAINS;
3037
3038         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3039         if (ret)
3040                 return ret;
3041
3042         trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
3043
3044         engine->gpu_caches_dirty = false;
3045         return 0;
3046 }
3047
3048 void
3049 intel_stop_engine(struct intel_engine_cs *engine)
3050 {
3051         int ret;
3052
3053         if (!intel_engine_initialized(engine))
3054                 return;
3055
3056         ret = intel_engine_idle(engine);
3057         if (ret)
3058                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
3059                           engine->name, ret);
3060
3061         stop_ring(engine);
3062 }