drivers/gpu/drm/i915/intel_sprite.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *   Jesse Barnes <jbarnes@virtuousgeek.org>
  25  *
  26  * New plane/sprite handling.
  27  *
  28  * The older chips had a separate interface for programming plane related
  29  * registers; newer ones are much simpler and we can use the new DRM plane
  30  * support.
  31  */
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_rect.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_plane_helper.h>
  38 #include "intel_drv.h"
  39 #include "intel_frontbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static bool
  44 format_is_yuv(uint32_t format)
  45 {
  46         switch (format) {
  47         case DRM_FORMAT_YUYV:
  48         case DRM_FORMAT_UYVY:
  49         case DRM_FORMAT_VYUY:
  50         case DRM_FORMAT_YVYU:
  51                 return true;
  52         default:
  53                 return false;
  54         }
  55 }
  56
  57 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
  58                              int usecs)
  59 {
  60         /* paranoia */
  61         if (!adjusted_mode->crtc_htotal)
  62                 return 1;
  63
  64         return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
  65                             1000 * adjusted_mode->crtc_htotal);
  66 }
  67
  68 #define VBLANK_EVASION_TIME_US 100
  69
  70 /**
  71  * intel_pipe_update_start() - start update of a set of display registers
  72  * @crtc: the crtc of which the registers are going to be updated
  73  * @start_vbl_count: vblank counter return pointer used for error checking
  74  *
  75  * Mark the start of an update to pipe registers that should be updated
  76  * atomically regarding vblank. If the next vblank will happens within
  77  * the next 100 us, this function waits until the vblank passes.
  78  *
  79  * After a successful call to this function, interrupts will be disabled
  80  * until a subsequent call to intel_pipe_update_end(). That is done to
  81  * avoid random delays. The value written to @start_vbl_count should be
  82  * supplied to intel_pipe_update_end() for error checking.
  83  */
  84 void intel_pipe_update_start(struct intel_crtc *crtc)
  85 {
  86         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
  87         long timeout = msecs_to_jiffies_timeout(1);
  88         int scanline, min, max, vblank_start;
  89         wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
  90         DEFINE_WAIT(wait);
  91
  92         vblank_start = adjusted_mode->crtc_vblank_start;
  93         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
  94                 vblank_start = DIV_ROUND_UP(vblank_start, 2);
  95
  96         /* FIXME needs to be calibrated sensibly */
  97         min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
  98                                                       VBLANK_EVASION_TIME_US);
  99         max = vblank_start - 1;
 100
 101         local_irq_disable();
 102
 103         if (min <= 0 || max <= 0)
 104                 return;
 105
 106         if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
 107                 return;
 108
 109         crtc->debug.min_vbl = min;
 110         crtc->debug.max_vbl = max;
 111         trace_i915_pipe_update_start(crtc);
 112
 113         for (;;) {
 114                 /*
 115                  * prepare_to_wait() has a memory barrier, which guarantees
 116                  * other CPUs can see the task state update by the time we
 117                  * read the scanline.
 118                  */
 119                 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
 120
 121                 scanline = intel_get_crtc_scanline(crtc);
 122                 if (scanline < min || scanline > max)
 123                         break;
 124
 125                 if (timeout <= 0) {
 126                         DRM_ERROR("Potential atomic update failure on pipe %c\n",
 127                                   pipe_name(crtc->pipe));
 128                         break;
 129                 }
 130
 131                 local_irq_enable();
 132
 133                 timeout = schedule_timeout(timeout);
 134
 135                 local_irq_disable();
 136         }
 137
 138         finish_wait(wq, &wait);
 139
 140         drm_crtc_vblank_put(&crtc->base);
 141
 142         crtc->debug.scanline_start = scanline;
 143         crtc->debug.start_vbl_time = ktime_get();
 144         crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
 145
 146         trace_i915_pipe_update_vblank_evaded(crtc);
 147 }
 148
 149 /**
 150  * intel_pipe_update_end() - end update of a set of display registers
 151  * @crtc: the crtc of which the registers were updated
 152  * @start_vbl_count: start vblank counter (used for error checking)
 153  *
 154  * Mark the end of an update started with intel_pipe_update_start(). This
 155  * re-enables interrupts and verifies the update was actually completed
 156  * before a vblank using the value of @start_vbl_count.
 157  */
 158 void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work)
 159 {
 160         enum pipe pipe = crtc->pipe;
 161         int scanline_end = intel_get_crtc_scanline(crtc);
 162         u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 163         ktime_t end_vbl_time = ktime_get();
 164
 165         if (work) {
 166                 work->flip_queued_vblank = end_vbl_count;
 167                 smp_mb__before_atomic();
 168                 atomic_set(&work->pending, 1);
 169         }
 170
 171         trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
 172
 173         /* We're still in the vblank-evade critical section, this can't race.
 174          * Would be slightly nice to just grab the vblank count and arm the
 175          * event outside of the critical section - the spinlock might spin for a
 176          * while ... */
 177         if (crtc->base.state->event) {
 178                 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
 179
 180                 spin_lock(&crtc->base.dev->event_lock);
 181                 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
 182                 spin_unlock(&crtc->base.dev->event_lock);
 183
 184                 crtc->base.state->event = NULL;
 185         }
 186
 187         local_irq_enable();
 188
 189         if (crtc->debug.start_vbl_count &&
 190             crtc->debug.start_vbl_count != end_vbl_count) {
 191                 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
 192                           pipe_name(pipe), crtc->debug.start_vbl_count,
 193                           end_vbl_count,
 194                           ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 195                           crtc->debug.min_vbl, crtc->debug.max_vbl,
 196                           crtc->debug.scanline_start, scanline_end);
 197         } else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
 198                    VBLANK_EVASION_TIME_US)
 199                 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
 200                          pipe_name(pipe),
 201                          ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
 202                          VBLANK_EVASION_TIME_US);
 203 }
 204
 205 static void
 206 skl_update_plane(struct drm_plane *drm_plane,
 207                  const struct intel_crtc_state *crtc_state,
 208                  const struct intel_plane_state *plane_state)
 209 {
 210         struct drm_device *dev = drm_plane->dev;
 211         struct drm_i915_private *dev_priv = to_i915(dev);
 212         struct intel_plane *intel_plane = to_intel_plane(drm_plane);
 213         struct drm_framebuffer *fb = plane_state->base.fb;
 214         enum plane_id plane_id = intel_plane->id;
 215         enum pipe pipe = intel_plane->pipe;
 216         u32 plane_ctl;
 217         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 218         u32 surf_addr = plane_state->main.offset;
 219         unsigned int rotation = plane_state->base.rotation;
 220         u32 stride = skl_plane_stride(fb, 0, rotation);
 221         int crtc_x = plane_state->base.dst.x1;
 222         int crtc_y = plane_state->base.dst.y1;
 223         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 224         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 225         uint32_t x = plane_state->main.x;
 226         uint32_t y = plane_state->main.y;
 227         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 228         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 229
 230         plane_ctl = PLANE_CTL_ENABLE;
 231
 232         if (IS_GEMINILAKE(dev_priv)) {
 233                 I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id),
 234                            PLANE_COLOR_PIPE_GAMMA_ENABLE |
 235                            PLANE_COLOR_PIPE_CSC_ENABLE |
 236                            PLANE_COLOR_PLANE_GAMMA_DISABLE);
 237         } else {
 238                 plane_ctl |=
 239                         PLANE_CTL_PIPE_GAMMA_ENABLE |
 240                         PLANE_CTL_PIPE_CSC_ENABLE |
 241                         PLANE_CTL_PLANE_GAMMA_DISABLE;
 242         }
 243
 244         plane_ctl |= skl_plane_ctl_format(fb->format->format);
 245         plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
 246         plane_ctl |= skl_plane_ctl_rotation(rotation);
 247
 248         if (key->flags) {
 249                 I915_WRITE(PLANE_KEYVAL(pipe, plane_id), key->min_value);
 250                 I915_WRITE(PLANE_KEYMAX(pipe, plane_id), key->max_value);
 251                 I915_WRITE(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
 252         }
 253
 254         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 255                 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
 256         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 257                 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
 258
 259         /* Sizes are 0 based */
 260         src_w--;
 261         src_h--;
 262         crtc_w--;
 263         crtc_h--;
 264
 265         I915_WRITE(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
 266         I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride);
 267         I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
 268
 269         /* program plane scaler */
 270         if (plane_state->scaler_id >= 0) {
 271                 int scaler_id = plane_state->scaler_id;
 272                 const struct intel_scaler *scaler;
 273
 274                 DRM_DEBUG_KMS("plane = %d PS_PLANE_SEL(plane) = 0x%x\n",
 275                               plane_id, PS_PLANE_SEL(plane_id));
 276
 277                 scaler = &crtc_state->scaler_state.scalers[scaler_id];
 278
 279                 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id),
 280                            PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
 281                 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
 282                 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
 283                 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id),
 284                         ((crtc_w + 1) << 16)|(crtc_h + 1));
 285
 286                 I915_WRITE(PLANE_POS(pipe, plane_id), 0);
 287         } else {
 288                 I915_WRITE(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 289         }
 290
 291         I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl);
 292         I915_WRITE(PLANE_SURF(pipe, plane_id),
 293                    intel_plane_ggtt_offset(plane_state) + surf_addr);
 294         POSTING_READ(PLANE_SURF(pipe, plane_id));
 295 }
 296
 297 static void
 298 skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 299 {
 300         struct drm_device *dev = dplane->dev;
 301         struct drm_i915_private *dev_priv = to_i915(dev);
 302         struct intel_plane *intel_plane = to_intel_plane(dplane);
 303         enum plane_id plane_id = intel_plane->id;
 304         enum pipe pipe = intel_plane->pipe;
 305
 306         I915_WRITE(PLANE_CTL(pipe, plane_id), 0);
 307
 308         I915_WRITE(PLANE_SURF(pipe, plane_id), 0);
 309         POSTING_READ(PLANE_SURF(pipe, plane_id));
 310 }
 311
 312 static void
 313 chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
 314 {
 315         struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
 316         enum plane_id plane_id = intel_plane->id;
 317
 318         /* Seems RGB data bypasses the CSC always */
 319         if (!format_is_yuv(format))
 320                 return;
 321
 322         /*
 323          * BT.601 limited range YCbCr -> full range RGB
 324          *
 325          * |r|   | 6537 4769     0|   |cr  |
 326          * |g| = |-3330 4769 -1605| x |y-64|
 327          * |b|   |    0 4769  8263|   |cb  |
 328          *
 329          * Cb and Cr apparently come in as signed already, so no
 330          * need for any offset. For Y we need to remove the offset.
 331          */
 332         I915_WRITE(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
 333         I915_WRITE(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 334         I915_WRITE(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
 335
 336         I915_WRITE(SPCSCC01(plane_id), SPCSC_C1(4769) | SPCSC_C0(6537));
 337         I915_WRITE(SPCSCC23(plane_id), SPCSC_C1(-3330) | SPCSC_C0(0));
 338         I915_WRITE(SPCSCC45(plane_id), SPCSC_C1(-1605) | SPCSC_C0(4769));
 339         I915_WRITE(SPCSCC67(plane_id), SPCSC_C1(4769) | SPCSC_C0(0));
 340         I915_WRITE(SPCSCC8(plane_id), SPCSC_C0(8263));
 341
 342         I915_WRITE(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) | SPCSC_IMIN(64));
 343         I915_WRITE(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 344         I915_WRITE(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
 345
 346         I915_WRITE(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 347         I915_WRITE(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 348         I915_WRITE(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
 349 }
 350
 351 static void
 352 vlv_update_plane(struct drm_plane *dplane,
 353                  const struct intel_crtc_state *crtc_state,
 354                  const struct intel_plane_state *plane_state)
 355 {
 356         struct drm_device *dev = dplane->dev;
 357         struct drm_i915_private *dev_priv = to_i915(dev);
 358         struct intel_plane *intel_plane = to_intel_plane(dplane);
 359         struct drm_framebuffer *fb = plane_state->base.fb;
 360         enum pipe pipe = intel_plane->pipe;
 361         enum plane_id plane_id = intel_plane->id;
 362         u32 sprctl;
 363         u32 sprsurf_offset, linear_offset;
 364         unsigned int rotation = plane_state->base.rotation;
 365         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 366         int crtc_x = plane_state->base.dst.x1;
 367         int crtc_y = plane_state->base.dst.y1;
 368         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 369         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 370         uint32_t x = plane_state->base.src.x1 >> 16;
 371         uint32_t y = plane_state->base.src.y1 >> 16;
 372         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 373         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 374
 375         sprctl = SP_ENABLE;
 376
 377         switch (fb->format->format) {
 378         case DRM_FORMAT_YUYV:
 379                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
 380                 break;
 381         case DRM_FORMAT_YVYU:
 382                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
 383                 break;
 384         case DRM_FORMAT_UYVY:
 385                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
 386                 break;
 387         case DRM_FORMAT_VYUY:
 388                 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
 389                 break;
 390         case DRM_FORMAT_RGB565:
 391                 sprctl |= SP_FORMAT_BGR565;
 392                 break;
 393         case DRM_FORMAT_XRGB8888:
 394                 sprctl |= SP_FORMAT_BGRX8888;
 395                 break;
 396         case DRM_FORMAT_ARGB8888:
 397                 sprctl |= SP_FORMAT_BGRA8888;
 398                 break;
 399         case DRM_FORMAT_XBGR2101010:
 400                 sprctl |= SP_FORMAT_RGBX1010102;
 401                 break;
 402         case DRM_FORMAT_ABGR2101010:
 403                 sprctl |= SP_FORMAT_RGBA1010102;
 404                 break;
 405         case DRM_FORMAT_XBGR8888:
 406                 sprctl |= SP_FORMAT_RGBX8888;
 407                 break;
 408         case DRM_FORMAT_ABGR8888:
 409                 sprctl |= SP_FORMAT_RGBA8888;
 410                 break;
 411         default:
 412                 /*
 413                  * If we get here one of the upper layers failed to filter
 414                  * out the unsupported plane formats
 415                  */
 416                 BUG();
 417                 break;
 418         }
 419
 420         /*
 421          * Enable gamma to match primary/cursor plane behaviour.
 422          * FIXME should be user controllable via propertiesa.
 423          */
 424         sprctl |= SP_GAMMA_ENABLE;
 425
 426         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 427                 sprctl |= SP_TILED;
 428
 429         if (rotation & DRM_ROTATE_180)
 430                 sprctl |= SP_ROTATE_180;
 431
 432         if (rotation & DRM_REFLECT_X)
 433                 sprctl |= SP_MIRROR;
 434
 435         /* Sizes are 0 based */
 436         src_w--;
 437         src_h--;
 438         crtc_w--;
 439         crtc_h--;
 440
 441         intel_add_fb_offsets(&x, &y, plane_state, 0);
 442         sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 443
 444         if (rotation & DRM_ROTATE_180) {
 445                 x += src_w;
 446                 y += src_h;
 447         } else if (rotation & DRM_REFLECT_X) {
 448                 x += src_w;
 449         }
 450
 451         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 452
 453         if (key->flags) {
 454                 I915_WRITE(SPKEYMINVAL(pipe, plane_id), key->min_value);
 455                 I915_WRITE(SPKEYMAXVAL(pipe, plane_id), key->max_value);
 456                 I915_WRITE(SPKEYMSK(pipe, plane_id), key->channel_mask);
 457         }
 458
 459         if (key->flags & I915_SET_COLORKEY_SOURCE)
 460                 sprctl |= SP_SOURCE_KEY;
 461
 462         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
 463                 chv_update_csc(intel_plane, fb->format->format);
 464
 465         I915_WRITE(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
 466         I915_WRITE(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
 467
 468         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 469                 I915_WRITE(SPTILEOFF(pipe, plane_id), (y << 16) | x);
 470         else
 471                 I915_WRITE(SPLINOFF(pipe, plane_id), linear_offset);
 472
 473         I915_WRITE(SPCONSTALPHA(pipe, plane_id), 0);
 474
 475         I915_WRITE(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
 476         I915_WRITE(SPCNTR(pipe, plane_id), sprctl);
 477         I915_WRITE(SPSURF(pipe, plane_id),
 478                    intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 479         POSTING_READ(SPSURF(pipe, plane_id));
 480 }
 481
 482 static void
 483 vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
 484 {
 485         struct drm_device *dev = dplane->dev;
 486         struct drm_i915_private *dev_priv = to_i915(dev);
 487         struct intel_plane *intel_plane = to_intel_plane(dplane);
 488         enum pipe pipe = intel_plane->pipe;
 489         enum plane_id plane_id = intel_plane->id;
 490
 491         I915_WRITE(SPCNTR(pipe, plane_id), 0);
 492
 493         I915_WRITE(SPSURF(pipe, plane_id), 0);
 494         POSTING_READ(SPSURF(pipe, plane_id));
 495 }
 496
 497 static void
 498 ivb_update_plane(struct drm_plane *plane,
 499                  const struct intel_crtc_state *crtc_state,
 500                  const struct intel_plane_state *plane_state)
 501 {
 502         struct drm_device *dev = plane->dev;
 503         struct drm_i915_private *dev_priv = to_i915(dev);
 504         struct intel_plane *intel_plane = to_intel_plane(plane);
 505         struct drm_framebuffer *fb = plane_state->base.fb;
 506         enum pipe pipe = intel_plane->pipe;
 507         u32 sprctl, sprscale = 0;
 508         u32 sprsurf_offset, linear_offset;
 509         unsigned int rotation = plane_state->base.rotation;
 510         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 511         int crtc_x = plane_state->base.dst.x1;
 512         int crtc_y = plane_state->base.dst.y1;
 513         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 514         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 515         uint32_t x = plane_state->base.src.x1 >> 16;
 516         uint32_t y = plane_state->base.src.y1 >> 16;
 517         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 518         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 519
 520         sprctl = SPRITE_ENABLE;
 521
 522         switch (fb->format->format) {
 523         case DRM_FORMAT_XBGR8888:
 524                 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
 525                 break;
 526         case DRM_FORMAT_XRGB8888:
 527                 sprctl |= SPRITE_FORMAT_RGBX888;
 528                 break;
 529         case DRM_FORMAT_YUYV:
 530                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
 531                 break;
 532         case DRM_FORMAT_YVYU:
 533                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
 534                 break;
 535         case DRM_FORMAT_UYVY:
 536                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
 537                 break;
 538         case DRM_FORMAT_VYUY:
 539                 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
 540                 break;
 541         default:
 542                 BUG();
 543         }
 544
 545         /*
 546          * Enable gamma to match primary/cursor plane behaviour.
 547          * FIXME should be user controllable via propertiesa.
 548          */
 549         sprctl |= SPRITE_GAMMA_ENABLE;
 550
 551         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 552                 sprctl |= SPRITE_TILED;
 553
 554         if (rotation & DRM_ROTATE_180)
 555                 sprctl |= SPRITE_ROTATE_180;
 556
 557         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 558                 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
 559         else
 560                 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
 561
 562         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 563                 sprctl |= SPRITE_PIPE_CSC_ENABLE;
 564
 565         /* Sizes are 0 based */
 566         src_w--;
 567         src_h--;
 568         crtc_w--;
 569         crtc_h--;
 570
 571         if (crtc_w != src_w || crtc_h != src_h)
 572                 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
 573
 574         intel_add_fb_offsets(&x, &y, plane_state, 0);
 575         sprsurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 576
 577         /* HSW+ does this automagically in hardware */
 578         if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) &&
 579             rotation & DRM_ROTATE_180) {
 580                 x += src_w;
 581                 y += src_h;
 582         }
 583
 584         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 585
 586         if (key->flags) {
 587                 I915_WRITE(SPRKEYVAL(pipe), key->min_value);
 588                 I915_WRITE(SPRKEYMAX(pipe), key->max_value);
 589                 I915_WRITE(SPRKEYMSK(pipe), key->channel_mask);
 590         }
 591
 592         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 593                 sprctl |= SPRITE_DEST_KEY;
 594         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 595                 sprctl |= SPRITE_SOURCE_KEY;
 596
 597         I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
 598         I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
 599
 600         /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
 601          * register */
 602         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 603                 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
 604         else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 605                 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 606         else
 607                 I915_WRITE(SPRLINOFF(pipe), linear_offset);
 608
 609         I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
 610         if (intel_plane->can_scale)
 611                 I915_WRITE(SPRSCALE(pipe), sprscale);
 612         I915_WRITE(SPRCTL(pipe), sprctl);
 613         I915_WRITE(SPRSURF(pipe),
 614                    intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
 615         POSTING_READ(SPRSURF(pipe));
 616 }
 617
 618 static void
 619 ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 620 {
 621         struct drm_device *dev = plane->dev;
 622         struct drm_i915_private *dev_priv = to_i915(dev);
 623         struct intel_plane *intel_plane = to_intel_plane(plane);
 624         int pipe = intel_plane->pipe;
 625
 626         I915_WRITE(SPRCTL(pipe), 0);
 627         /* Can't leave the scaler enabled... */
 628         if (intel_plane->can_scale)
 629                 I915_WRITE(SPRSCALE(pipe), 0);
 630
 631         I915_WRITE(SPRSURF(pipe), 0);
 632         POSTING_READ(SPRSURF(pipe));
 633 }
 634
 635 static void
 636 ilk_update_plane(struct drm_plane *plane,
 637                  const struct intel_crtc_state *crtc_state,
 638                  const struct intel_plane_state *plane_state)
 639 {
 640         struct drm_device *dev = plane->dev;
 641         struct drm_i915_private *dev_priv = to_i915(dev);
 642         struct intel_plane *intel_plane = to_intel_plane(plane);
 643         struct drm_framebuffer *fb = plane_state->base.fb;
 644         int pipe = intel_plane->pipe;
 645         u32 dvscntr, dvsscale;
 646         u32 dvssurf_offset, linear_offset;
 647         unsigned int rotation = plane_state->base.rotation;
 648         const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
 649         int crtc_x = plane_state->base.dst.x1;
 650         int crtc_y = plane_state->base.dst.y1;
 651         uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
 652         uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
 653         uint32_t x = plane_state->base.src.x1 >> 16;
 654         uint32_t y = plane_state->base.src.y1 >> 16;
 655         uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
 656         uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
 657
 658         dvscntr = DVS_ENABLE;
 659
 660         switch (fb->format->format) {
 661         case DRM_FORMAT_XBGR8888:
 662                 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
 663                 break;
 664         case DRM_FORMAT_XRGB8888:
 665                 dvscntr |= DVS_FORMAT_RGBX888;
 666                 break;
 667         case DRM_FORMAT_YUYV:
 668                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
 669                 break;
 670         case DRM_FORMAT_YVYU:
 671                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
 672                 break;
 673         case DRM_FORMAT_UYVY:
 674                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
 675                 break;
 676         case DRM_FORMAT_VYUY:
 677                 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
 678                 break;
 679         default:
 680                 BUG();
 681         }
 682
 683         /*
 684          * Enable gamma to match primary/cursor plane behaviour.
 685          * FIXME should be user controllable via propertiesa.
 686          */
 687         dvscntr |= DVS_GAMMA_ENABLE;
 688
 689         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 690                 dvscntr |= DVS_TILED;
 691
 692         if (rotation & DRM_ROTATE_180)
 693                 dvscntr |= DVS_ROTATE_180;
 694
 695         if (IS_GEN6(dev_priv))
 696                 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
 697
 698         /* Sizes are 0 based */
 699         src_w--;
 700         src_h--;
 701         crtc_w--;
 702         crtc_h--;
 703
 704         dvsscale = 0;
 705         if (crtc_w != src_w || crtc_h != src_h)
 706                 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
 707
 708         intel_add_fb_offsets(&x, &y, plane_state, 0);
 709         dvssurf_offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
 710
 711         if (rotation & DRM_ROTATE_180) {
 712                 x += src_w;
 713                 y += src_h;
 714         }
 715
 716         linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
 717
 718         if (key->flags) {
 719                 I915_WRITE(DVSKEYVAL(pipe), key->min_value);
 720                 I915_WRITE(DVSKEYMAX(pipe), key->max_value);
 721                 I915_WRITE(DVSKEYMSK(pipe), key->channel_mask);
 722         }
 723
 724         if (key->flags & I915_SET_COLORKEY_DESTINATION)
 725                 dvscntr |= DVS_DEST_KEY;
 726         else if (key->flags & I915_SET_COLORKEY_SOURCE)
 727                 dvscntr |= DVS_SOURCE_KEY;
 728
 729         I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 730         I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 731
 732         if (fb->modifier == I915_FORMAT_MOD_X_TILED)
 733                 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 734         else
 735                 I915_WRITE(DVSLINOFF(pipe), linear_offset);
 736
 737         I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
 738         I915_WRITE(DVSSCALE(pipe), dvsscale);
 739         I915_WRITE(DVSCNTR(pipe), dvscntr);
 740         I915_WRITE(DVSSURF(pipe),
 741                    intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
 742         POSTING_READ(DVSSURF(pipe));
 743 }
 744
 745 static void
 746 ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
 747 {
 748         struct drm_device *dev = plane->dev;
 749         struct drm_i915_private *dev_priv = to_i915(dev);
 750         struct intel_plane *intel_plane = to_intel_plane(plane);
 751         int pipe = intel_plane->pipe;
 752
 753         I915_WRITE(DVSCNTR(pipe), 0);
 754         /* Disable the scaler */
 755         I915_WRITE(DVSSCALE(pipe), 0);
 756
 757         I915_WRITE(DVSSURF(pipe), 0);
 758         POSTING_READ(DVSSURF(pipe));
 759 }
 760
 761 static int
 762 intel_check_sprite_plane(struct drm_plane *plane,
 763                          struct intel_crtc_state *crtc_state,
 764                          struct intel_plane_state *state)
 765 {
 766         struct drm_i915_private *dev_priv = to_i915(plane->dev);
 767         struct drm_crtc *crtc = state->base.crtc;
 768         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 769         struct intel_plane *intel_plane = to_intel_plane(plane);
 770         struct drm_framebuffer *fb = state->base.fb;
 771         int crtc_x, crtc_y;
 772         unsigned int crtc_w, crtc_h;
 773         uint32_t src_x, src_y, src_w, src_h;
 774         struct drm_rect *src = &state->base.src;
 775         struct drm_rect *dst = &state->base.dst;
 776         const struct drm_rect *clip = &state->clip;
 777         int hscale, vscale;
 778         int max_scale, min_scale;
 779         bool can_scale;
 780         int ret;
 781
 782         *src = drm_plane_state_src(&state->base);
 783         *dst = drm_plane_state_dest(&state->base);
 784
 785         if (!fb) {
 786                 state->base.visible = false;
 787                 return 0;
 788         }
 789
 790         /* Don't modify another pipe's plane */
 791         if (intel_plane->pipe != intel_crtc->pipe) {
 792                 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
 793                 return -EINVAL;
 794         }
 795
 796         /* FIXME check all gen limits */
 797         if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
 798                 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
 799                 return -EINVAL;
 800         }
 801
 802         /* setup can_scale, min_scale, max_scale */
 803         if (INTEL_GEN(dev_priv) >= 9) {
 804                 /* use scaler when colorkey is not required */
 805                 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 806                         can_scale = 1;
 807                         min_scale = 1;
 808                         max_scale = skl_max_scale(intel_crtc, crtc_state);
 809                 } else {
 810                         can_scale = 0;
 811                         min_scale = DRM_PLANE_HELPER_NO_SCALING;
 812                         max_scale = DRM_PLANE_HELPER_NO_SCALING;
 813                 }
 814         } else {
 815                 can_scale = intel_plane->can_scale;
 816                 max_scale = intel_plane->max_downscale << 16;
 817                 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
 818         }
 819
 820         /*
 821          * FIXME the following code does a bunch of fuzzy adjustments to the
 822          * coordinates and sizes. We probably need some way to decide whether
 823          * more strict checking should be done instead.
 824          */
 825         drm_rect_rotate(src, fb->width << 16, fb->height << 16,
 826                         state->base.rotation);
 827
 828         hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
 829         BUG_ON(hscale < 0);
 830
 831         vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
 832         BUG_ON(vscale < 0);
 833
 834         state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
 835
 836         crtc_x = dst->x1;
 837         crtc_y = dst->y1;
 838         crtc_w = drm_rect_width(dst);
 839         crtc_h = drm_rect_height(dst);
 840
 841         if (state->base.visible) {
 842                 /* check again in case clipping clamped the results */
 843                 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 844                 if (hscale < 0) {
 845                         DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
 846                         drm_rect_debug_print("src: ", src, true);
 847                         drm_rect_debug_print("dst: ", dst, false);
 848
 849                         return hscale;
 850                 }
 851
 852                 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 853                 if (vscale < 0) {
 854                         DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
 855                         drm_rect_debug_print("src: ", src, true);
 856                         drm_rect_debug_print("dst: ", dst, false);
 857
 858                         return vscale;
 859                 }
 860
 861                 /* Make the source viewport size an exact multiple of the scaling factors. */
 862                 drm_rect_adjust_size(src,
 863                                      drm_rect_width(dst) * hscale - drm_rect_width(src),
 864                                      drm_rect_height(dst) * vscale - drm_rect_height(src));
 865
 866                 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
 867                                     state->base.rotation);
 868
 869                 /* sanity check to make sure the src viewport wasn't enlarged */
 870                 WARN_ON(src->x1 < (int) state->base.src_x ||
 871                         src->y1 < (int) state->base.src_y ||
 872                         src->x2 > (int) state->base.src_x + state->base.src_w ||
 873                         src->y2 > (int) state->base.src_y + state->base.src_h);
 874
 875                 /*
 876                  * Hardware doesn't handle subpixel coordinates.
 877                  * Adjust to (macro)pixel boundary, but be careful not to
 878                  * increase the source viewport size, because that could
 879                  * push the downscaling factor out of bounds.
 880                  */
 881                 src_x = src->x1 >> 16;
 882                 src_w = drm_rect_width(src) >> 16;
 883                 src_y = src->y1 >> 16;
 884                 src_h = drm_rect_height(src) >> 16;
 885
 886                 if (format_is_yuv(fb->format->format)) {
 887                         src_x &= ~1;
 888                         src_w &= ~1;
 889
 890                         /*
 891                          * Must keep src and dst the
 892                          * same if we can't scale.
 893                          */
 894                         if (!can_scale)
 895                                 crtc_w &= ~1;
 896
 897                         if (crtc_w == 0)
 898                                 state->base.visible = false;
 899                 }
 900         }
 901
 902         /* Check size restrictions when scaling */
 903         if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
 904                 unsigned int width_bytes;
 905                 int cpp = fb->format->cpp[0];
 906
 907                 WARN_ON(!can_scale);
 908
 909                 /* FIXME interlacing min height is 6 */
 910
 911                 if (crtc_w < 3 || crtc_h < 3)
 912                         state->base.visible = false;
 913
 914                 if (src_w < 3 || src_h < 3)
 915                         state->base.visible = false;
 916
 917                 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
 918
 919                 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
 920                     width_bytes > 4096 || fb->pitches[0] > 4096)) {
 921                         DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
 922                         return -EINVAL;
 923                 }
 924         }
 925
 926         if (state->base.visible) {
 927                 src->x1 = src_x << 16;
 928                 src->x2 = (src_x + src_w) << 16;
 929                 src->y1 = src_y << 16;
 930                 src->y2 = (src_y + src_h) << 16;
 931         }
 932
 933         dst->x1 = crtc_x;
 934         dst->x2 = crtc_x + crtc_w;
 935         dst->y1 = crtc_y;
 936         dst->y2 = crtc_y + crtc_h;
 937
 938         if (INTEL_GEN(dev_priv) >= 9) {
 939                 ret = skl_check_plane_surface(state);
 940                 if (ret)
 941                         return ret;
 942         }
 943
 944         return 0;
 945 }
 946
 947 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
 948                               struct drm_file *file_priv)
 949 {
 950         struct drm_i915_private *dev_priv = to_i915(dev);
 951         struct drm_intel_sprite_colorkey *set = data;
 952         struct drm_plane *plane;
 953         struct drm_plane_state *plane_state;
 954         struct drm_atomic_state *state;
 955         struct drm_modeset_acquire_ctx ctx;
 956         int ret = 0;
 957
 958         /* Make sure we don't try to enable both src & dest simultaneously */
 959         if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
 960                 return -EINVAL;
 961
 962         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 963             set->flags & I915_SET_COLORKEY_DESTINATION)
 964                 return -EINVAL;
 965
 966         plane = drm_plane_find(dev, set->plane_id);
 967         if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
 968                 return -ENOENT;
 969
 970         drm_modeset_acquire_init(&ctx, 0);
 971
 972         state = drm_atomic_state_alloc(plane->dev);
 973         if (!state) {
 974                 ret = -ENOMEM;
 975                 goto out;
 976         }
 977         state->acquire_ctx = &ctx;
 978
 979         while (1) {
 980                 plane_state = drm_atomic_get_plane_state(state, plane);
 981                 ret = PTR_ERR_OR_ZERO(plane_state);
 982                 if (!ret) {
 983                         to_intel_plane_state(plane_state)->ckey = *set;
 984                         ret = drm_atomic_commit(state);
 985                 }
 986
 987                 if (ret != -EDEADLK)
 988                         break;
 989
 990                 drm_atomic_state_clear(state);
 991                 drm_modeset_backoff(&ctx);
 992         }
 993
 994         drm_atomic_state_put(state);
 995 out:
 996         drm_modeset_drop_locks(&ctx);
 997         drm_modeset_acquire_fini(&ctx);
 998         return ret;
 999 }
1000
1001 static const uint32_t ilk_plane_formats[] = {
1002         DRM_FORMAT_XRGB8888,
1003         DRM_FORMAT_YUYV,
1004         DRM_FORMAT_YVYU,
1005         DRM_FORMAT_UYVY,
1006         DRM_FORMAT_VYUY,
1007 };
1008
1009 static const uint32_t snb_plane_formats[] = {
1010         DRM_FORMAT_XBGR8888,
1011         DRM_FORMAT_XRGB8888,
1012         DRM_FORMAT_YUYV,
1013         DRM_FORMAT_YVYU,
1014         DRM_FORMAT_UYVY,
1015         DRM_FORMAT_VYUY,
1016 };
1017
1018 static const uint32_t vlv_plane_formats[] = {
1019         DRM_FORMAT_RGB565,
1020         DRM_FORMAT_ABGR8888,
1021         DRM_FORMAT_ARGB8888,
1022         DRM_FORMAT_XBGR8888,
1023         DRM_FORMAT_XRGB8888,
1024         DRM_FORMAT_XBGR2101010,
1025         DRM_FORMAT_ABGR2101010,
1026         DRM_FORMAT_YUYV,
1027         DRM_FORMAT_YVYU,
1028         DRM_FORMAT_UYVY,
1029         DRM_FORMAT_VYUY,
1030 };
1031
1032 static uint32_t skl_plane_formats[] = {
1033         DRM_FORMAT_RGB565,
1034         DRM_FORMAT_ABGR8888,
1035         DRM_FORMAT_ARGB8888,
1036         DRM_FORMAT_XBGR8888,
1037         DRM_FORMAT_XRGB8888,
1038         DRM_FORMAT_YUYV,
1039         DRM_FORMAT_YVYU,
1040         DRM_FORMAT_UYVY,
1041         DRM_FORMAT_VYUY,
1042 };
1043
1044 struct intel_plane *
1045 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1046                           enum pipe pipe, int plane)
1047 {
1048         struct intel_plane *intel_plane = NULL;
1049         struct intel_plane_state *state = NULL;
1050         unsigned long possible_crtcs;
1051         const uint32_t *plane_formats;
1052         unsigned int supported_rotations;
1053         int num_plane_formats;
1054         int ret;
1055
1056         intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1057         if (!intel_plane) {
1058                 ret = -ENOMEM;
1059                 goto fail;
1060         }
1061
1062         state = intel_create_plane_state(&intel_plane->base);
1063         if (!state) {
1064                 ret = -ENOMEM;
1065                 goto fail;
1066         }
1067         intel_plane->base.state = &state->base;
1068
1069         if (INTEL_GEN(dev_priv) >= 9) {
1070                 intel_plane->can_scale = true;
1071                 state->scaler_id = -1;
1072
1073                 intel_plane->update_plane = skl_update_plane;
1074                 intel_plane->disable_plane = skl_disable_plane;
1075
1076                 plane_formats = skl_plane_formats;
1077                 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1078         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1079                 intel_plane->can_scale = false;
1080                 intel_plane->max_downscale = 1;
1081
1082                 intel_plane->update_plane = vlv_update_plane;
1083                 intel_plane->disable_plane = vlv_disable_plane;
1084
1085                 plane_formats = vlv_plane_formats;
1086                 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1087         } else if (INTEL_GEN(dev_priv) >= 7) {
1088                 if (IS_IVYBRIDGE(dev_priv)) {
1089                         intel_plane->can_scale = true;
1090                         intel_plane->max_downscale = 2;
1091                 } else {
1092                         intel_plane->can_scale = false;
1093                         intel_plane->max_downscale = 1;
1094                 }
1095
1096                 intel_plane->update_plane = ivb_update_plane;
1097                 intel_plane->disable_plane = ivb_disable_plane;
1098
1099                 plane_formats = snb_plane_formats;
1100                 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1101         } else {
1102                 intel_plane->can_scale = true;
1103                 intel_plane->max_downscale = 16;
1104
1105                 intel_plane->update_plane = ilk_update_plane;
1106                 intel_plane->disable_plane = ilk_disable_plane;
1107
1108                 if (IS_GEN6(dev_priv)) {
1109                         plane_formats = snb_plane_formats;
1110                         num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1111                 } else {
1112                         plane_formats = ilk_plane_formats;
1113                         num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1114                 }
1115         }
1116
1117         if (INTEL_GEN(dev_priv) >= 9) {
1118                 supported_rotations =
1119                         DRM_ROTATE_0 | DRM_ROTATE_90 |
1120                         DRM_ROTATE_180 | DRM_ROTATE_270;
1121         } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1122                 supported_rotations =
1123                         DRM_ROTATE_0 | DRM_ROTATE_180 |
1124                         DRM_REFLECT_X;
1125         } else {
1126                 supported_rotations =
1127                         DRM_ROTATE_0 | DRM_ROTATE_180;
1128         }
1129
1130         intel_plane->pipe = pipe;
1131         intel_plane->plane = plane;
1132         intel_plane->id = PLANE_SPRITE0 + plane;
1133         intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1134         intel_plane->check_plane = intel_check_sprite_plane;
1135
1136         possible_crtcs = (1 << pipe);
1137
1138         if (INTEL_GEN(dev_priv) >= 9)
1139                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1140                                                possible_crtcs, &intel_plane_funcs,
1141                                                plane_formats, num_plane_formats,
1142                                                DRM_PLANE_TYPE_OVERLAY,
1143                                                "plane %d%c", plane + 2, pipe_name(pipe));
1144         else
1145                 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1146                                                possible_crtcs, &intel_plane_funcs,
1147                                                plane_formats, num_plane_formats,
1148                                                DRM_PLANE_TYPE_OVERLAY,
1149                                                "sprite %c", sprite_name(pipe, plane));
1150         if (ret)
1151                 goto fail;
1152
1153         drm_plane_create_rotation_property(&intel_plane->base,
1154                                            DRM_ROTATE_0,
1155                                            supported_rotations);
1156
1157         drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1158
1159         return intel_plane;
1160
1161 fail:
1162         kfree(state);
1163         kfree(intel_plane);
1164
1165         return ERR_PTR(ret);
1166 }