drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic.h>
  29 #include <drm/drm_atomic_helper.h>
  30 #include <drm/drm_crtc_helper.h>
  31 #include <drm/drm_dp_helper.h>
  32 #include <drm/drm_fb_helper.h>
  33 #include <drm/drm_plane_helper.h>
  34
  35 #include <nvif/class.h>
  36 #include <nvif/cl0002.h>
  37 #include <nvif/cl5070.h>
  38 #include <nvif/cl507a.h>
  39 #include <nvif/cl507b.h>
  40 #include <nvif/cl507c.h>
  41 #include <nvif/cl507d.h>
  42 #include <nvif/cl507e.h>
  43 #include <nvif/event.h>
  44
  45 #include "nouveau_drv.h"
  46 #include "nouveau_dma.h"
  47 #include "nouveau_gem.h"
  48 #include "nouveau_connector.h"
  49 #include "nouveau_encoder.h"
  50 #include "nouveau_crtc.h"
  51 #include "nouveau_fence.h"
  52 #include "nouveau_fbcon.h"
  53 #include "nv50_display.h"
  54
  55 #define EVO_DMA_NR 9
  56
  57 #define EVO_MASTER  (0x00)
  58 #define EVO_FLIP(c) (0x01 + (c))
  59 #define EVO_OVLY(c) (0x05 + (c))
  60 #define EVO_OIMM(c) (0x09 + (c))
  61 #define EVO_CURS(c) (0x0d + (c))
  62
  63 /* offsets in shared sync bo of various structures */
  64 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  65 #define EVO_MAST_NTFY     EVO_SYNC(      0, 0x00)
  66 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c) + 1, 0x00)
  67 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c) + 1, 0x10)
  68 #define EVO_FLIP_NTFY0(c) EVO_SYNC((c) + 1, 0x20)
  69 #define EVO_FLIP_NTFY1(c) EVO_SYNC((c) + 1, 0x30)
  70
  71 /******************************************************************************
  72  * Atomic state
  73  *****************************************************************************/
  74 #define nv50_atom(p) container_of((p), struct nv50_atom, state)
  75
  76 struct nv50_atom {
  77         struct drm_atomic_state state;
  78
  79         struct list_head outp;
  80         bool lock_core;
  81         bool flush_disable;
  82 };
  83
  84 struct nv50_outp_atom {
  85         struct list_head head;
  86
  87         struct drm_encoder *encoder;
  88         bool flush_disable;
  89
  90         union {
  91                 struct {
  92                         bool ctrl:1;
  93                 };
  94                 u8 mask;
  95         } clr;
  96
  97         union {
  98                 struct {
  99                         bool ctrl:1;
 100                 };
 101                 u8 mask;
 102         } set;
 103 };
 104
 105 #define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)
 106
 107 struct nv50_head_atom {
 108         struct drm_crtc_state state;
 109
 110         struct {
 111                 u16 iW;
 112                 u16 iH;
 113                 u16 oW;
 114                 u16 oH;
 115         } view;
 116
 117         struct nv50_head_mode {
 118                 bool interlace;
 119                 u32 clock;
 120                 struct {
 121                         u16 active;
 122                         u16 synce;
 123                         u16 blanke;
 124                         u16 blanks;
 125                 } h;
 126                 struct {
 127                         u32 active;
 128                         u16 synce;
 129                         u16 blanke;
 130                         u16 blanks;
 131                         u16 blank2s;
 132                         u16 blank2e;
 133                         u16 blankus;
 134                 } v;
 135         } mode;
 136
 137         struct {
 138                 u32 handle;
 139                 u64 offset:40;
 140         } lut;
 141
 142         struct {
 143                 bool visible;
 144                 u32 handle;
 145                 u64 offset:40;
 146                 u8  format;
 147                 u8  kind:7;
 148                 u8  layout:1;
 149                 u8  block:4;
 150                 u32 pitch:20;
 151                 u16 x;
 152                 u16 y;
 153                 u16 w;
 154                 u16 h;
 155         } core;
 156
 157         struct {
 158                 bool visible;
 159                 u32 handle;
 160                 u64 offset:40;
 161                 u8  layout:1;
 162                 u8  format:1;
 163         } curs;
 164
 165         struct {
 166                 u8  depth;
 167                 u8  cpp;
 168                 u16 x;
 169                 u16 y;
 170                 u16 w;
 171                 u16 h;
 172         } base;
 173
 174         struct {
 175                 u8 cpp;
 176         } ovly;
 177
 178         struct {
 179                 bool enable:1;
 180                 u8 bits:2;
 181                 u8 mode:4;
 182         } dither;
 183
 184         struct {
 185                 struct {
 186                         u16 cos:12;
 187                         u16 sin:12;
 188                 } sat;
 189         } procamp;
 190
 191         union {
 192                 struct {
 193                         bool core:1;
 194                         bool curs:1;
 195                 };
 196                 u8 mask;
 197         } clr;
 198
 199         union {
 200                 struct {
 201                         bool core:1;
 202                         bool curs:1;
 203                         bool view:1;
 204                         bool mode:1;
 205                         bool base:1;
 206                         bool ovly:1;
 207                         bool dither:1;
 208                         bool procamp:1;
 209                 };
 210                 u16 mask;
 211         } set;
 212 };
 213
 214 static inline struct nv50_head_atom *
 215 nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc)
 216 {
 217         struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);
 218         if (IS_ERR(statec))
 219                 return (void *)statec;
 220         return nv50_head_atom(statec);
 221 }
 222
 223 #define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)
 224
 225 struct nv50_wndw_atom {
 226         struct drm_plane_state state;
 227         u8 interval;
 228
 229         struct drm_rect clip;
 230
 231         struct {
 232                 u32  handle;
 233                 u16  offset:12;
 234                 bool awaken:1;
 235         } ntfy;
 236
 237         struct {
 238                 u32 handle;
 239                 u16 offset:12;
 240                 u32 acquire;
 241                 u32 release;
 242         } sema;
 243
 244         struct {
 245                 u8 enable:2;
 246         } lut;
 247
 248         struct {
 249                 u8  mode:2;
 250                 u8  interval:4;
 251
 252                 u8  format;
 253                 u8  kind:7;
 254                 u8  layout:1;
 255                 u8  block:4;
 256                 u32 pitch:20;
 257                 u16 w;
 258                 u16 h;
 259
 260                 u32 handle;
 261                 u64 offset;
 262         } image;
 263
 264         struct {
 265                 u16 x;
 266                 u16 y;
 267         } point;
 268
 269         union {
 270                 struct {
 271                         bool ntfy:1;
 272                         bool sema:1;
 273                         bool image:1;
 274                 };
 275                 u8 mask;
 276         } clr;
 277
 278         union {
 279                 struct {
 280                         bool ntfy:1;
 281                         bool sema:1;
 282                         bool image:1;
 283                         bool lut:1;
 284                         bool point:1;
 285                 };
 286                 u8 mask;
 287         } set;
 288 };
 289
 290 /******************************************************************************
 291  * EVO channel
 292  *****************************************************************************/
 293
 294 struct nv50_chan {
 295         struct nvif_object user;
 296         struct nvif_device *device;
 297 };
 298
 299 static int
 300 nv50_chan_create(struct nvif_device *device, struct nvif_object *disp,
 301                  const s32 *oclass, u8 head, void *data, u32 size,
 302                  struct nv50_chan *chan)
 303 {
 304         struct nvif_sclass *sclass;
 305         int ret, i, n;
 306
 307         chan->device = device;
 308
 309         ret = n = nvif_object_sclass_get(disp, &sclass);
 310         if (ret < 0)
 311                 return ret;
 312
 313         while (oclass[0]) {
 314                 for (i = 0; i < n; i++) {
 315                         if (sclass[i].oclass == oclass[0]) {
 316                                 ret = nvif_object_init(disp, 0, oclass[0],
 317                                                        data, size, &chan->user);
 318                                 if (ret == 0)
 319                                         nvif_object_map(&chan->user);
 320                                 nvif_object_sclass_put(&sclass);
 321                                 return ret;
 322                         }
 323                 }
 324                 oclass++;
 325         }
 326
 327         nvif_object_sclass_put(&sclass);
 328         return -ENOSYS;
 329 }
 330
 331 static void
 332 nv50_chan_destroy(struct nv50_chan *chan)
 333 {
 334         nvif_object_fini(&chan->user);
 335 }
 336
 337 /******************************************************************************
 338  * PIO EVO channel
 339  *****************************************************************************/
 340
 341 struct nv50_pioc {
 342         struct nv50_chan base;
 343 };
 344
 345 static void
 346 nv50_pioc_destroy(struct nv50_pioc *pioc)
 347 {
 348         nv50_chan_destroy(&pioc->base);
 349 }
 350
 351 static int
 352 nv50_pioc_create(struct nvif_device *device, struct nvif_object *disp,
 353                  const s32 *oclass, u8 head, void *data, u32 size,
 354                  struct nv50_pioc *pioc)
 355 {
 356         return nv50_chan_create(device, disp, oclass, head, data, size,
 357                                 &pioc->base);
 358 }
 359
 360 /******************************************************************************
 361  * Overlay Immediate
 362  *****************************************************************************/
 363
 364 struct nv50_oimm {
 365         struct nv50_pioc base;
 366 };
 367
 368 static int
 369 nv50_oimm_create(struct nvif_device *device, struct nvif_object *disp,
 370                  int head, struct nv50_oimm *oimm)
 371 {
 372         struct nv50_disp_cursor_v0 args = {
 373                 .head = head,
 374         };
 375         static const s32 oclass[] = {
 376                 GK104_DISP_OVERLAY,
 377                 GF110_DISP_OVERLAY,
 378                 GT214_DISP_OVERLAY,
 379                 G82_DISP_OVERLAY,
 380                 NV50_DISP_OVERLAY,
 381                 0
 382         };
 383
 384         return nv50_pioc_create(device, disp, oclass, head, &args, sizeof(args),
 385                                 &oimm->base);
 386 }
 387
 388 /******************************************************************************
 389  * DMA EVO channel
 390  *****************************************************************************/
 391
 392 struct nv50_dmac_ctxdma {
 393         struct list_head head;
 394         struct nvif_object object;
 395 };
 396
 397 struct nv50_dmac {
 398         struct nv50_chan base;
 399         dma_addr_t handle;
 400         u32 *ptr;
 401
 402         struct nvif_object sync;
 403         struct nvif_object vram;
 404         struct list_head ctxdma;
 405
 406         /* Protects against concurrent pushbuf access to this channel, lock is
 407          * grabbed by evo_wait (if the pushbuf reservation is successful) and
 408          * dropped again by evo_kick. */
 409         struct mutex lock;
 410 };
 411
 412 static void
 413 nv50_dmac_ctxdma_del(struct nv50_dmac_ctxdma *ctxdma)
 414 {
 415         nvif_object_fini(&ctxdma->object);
 416         list_del(&ctxdma->head);
 417         kfree(ctxdma);
 418 }
 419
 420 static struct nv50_dmac_ctxdma *
 421 nv50_dmac_ctxdma_new(struct nv50_dmac *dmac, struct nouveau_framebuffer *fb)
 422 {
 423         struct nouveau_drm *drm = nouveau_drm(fb->base.dev);
 424         struct nv50_dmac_ctxdma *ctxdma;
 425         const u8    kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8;
 426         const u32 handle = 0xfb000000 | kind;
 427         struct {
 428                 struct nv_dma_v0 base;
 429                 union {
 430                         struct nv50_dma_v0 nv50;
 431                         struct gf100_dma_v0 gf100;
 432                         struct gf119_dma_v0 gf119;
 433                 };
 434         } args = {};
 435         u32 argc = sizeof(args.base);
 436         int ret;
 437
 438         list_for_each_entry(ctxdma, &dmac->ctxdma, head) {
 439                 if (ctxdma->object.handle == handle)
 440                         return ctxdma;
 441         }
 442
 443         if (!(ctxdma = kzalloc(sizeof(*ctxdma), GFP_KERNEL)))
 444                 return ERR_PTR(-ENOMEM);
 445         list_add(&ctxdma->head, &dmac->ctxdma);
 446
 447         args.base.target = NV_DMA_V0_TARGET_VRAM;
 448         args.base.access = NV_DMA_V0_ACCESS_RDWR;
 449         args.base.start  = 0;
 450         args.base.limit  = drm->client.device.info.ram_user - 1;
 451
 452         if (drm->client.device.info.chipset < 0x80) {
 453                 args.nv50.part = NV50_DMA_V0_PART_256;
 454                 argc += sizeof(args.nv50);
 455         } else
 456         if (drm->client.device.info.chipset < 0xc0) {
 457                 args.nv50.part = NV50_DMA_V0_PART_256;
 458                 args.nv50.kind = kind;
 459                 argc += sizeof(args.nv50);
 460         } else
 461         if (drm->client.device.info.chipset < 0xd0) {
 462                 args.gf100.kind = kind;
 463                 argc += sizeof(args.gf100);
 464         } else {
 465                 args.gf119.page = GF119_DMA_V0_PAGE_LP;
 466                 args.gf119.kind = kind;
 467                 argc += sizeof(args.gf119);
 468         }
 469
 470         ret = nvif_object_init(&dmac->base.user, handle, NV_DMA_IN_MEMORY,
 471                                &args, argc, &ctxdma->object);
 472         if (ret) {
 473                 nv50_dmac_ctxdma_del(ctxdma);
 474                 return ERR_PTR(ret);
 475         }
 476
 477         return ctxdma;
 478 }
 479
 480 static void
 481 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
 482 {
 483         struct nvif_device *device = dmac->base.device;
 484         struct nv50_dmac_ctxdma *ctxdma, *ctxtmp;
 485
 486         list_for_each_entry_safe(ctxdma, ctxtmp, &dmac->ctxdma, head) {
 487                 nv50_dmac_ctxdma_del(ctxdma);
 488         }
 489
 490         nvif_object_fini(&dmac->vram);
 491         nvif_object_fini(&dmac->sync);
 492
 493         nv50_chan_destroy(&dmac->base);
 494
 495         if (dmac->ptr) {
 496                 struct device *dev = nvxx_device(device)->dev;
 497                 dma_free_coherent(dev, PAGE_SIZE, dmac->ptr, dmac->handle);
 498         }
 499 }
 500
 501 static int
 502 nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp,
 503                  const s32 *oclass, u8 head, void *data, u32 size, u64 syncbuf,
 504                  struct nv50_dmac *dmac)
 505 {
 506         struct nv50_disp_core_channel_dma_v0 *args = data;
 507         struct nvif_object pushbuf;
 508         int ret;
 509
 510         mutex_init(&dmac->lock);
 511
 512         dmac->ptr = dma_alloc_coherent(nvxx_device(device)->dev, PAGE_SIZE,
 513                                        &dmac->handle, GFP_KERNEL);
 514         if (!dmac->ptr)
 515                 return -ENOMEM;
 516
 517         ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY,
 518                                &(struct nv_dma_v0) {
 519                                         .target = NV_DMA_V0_TARGET_PCI_US,
 520                                         .access = NV_DMA_V0_ACCESS_RD,
 521                                         .start = dmac->handle + 0x0000,
 522                                         .limit = dmac->handle + 0x0fff,
 523                                }, sizeof(struct nv_dma_v0), &pushbuf);
 524         if (ret)
 525                 return ret;
 526
 527         args->pushbuf = nvif_handle(&pushbuf);
 528
 529         ret = nv50_chan_create(device, disp, oclass, head, data, size,
 530                                &dmac->base);
 531         nvif_object_fini(&pushbuf);
 532         if (ret)
 533                 return ret;
 534
 535         ret = nvif_object_init(&dmac->base.user, 0xf0000000, NV_DMA_IN_MEMORY,
 536                                &(struct nv_dma_v0) {
 537                                         .target = NV_DMA_V0_TARGET_VRAM,
 538                                         .access = NV_DMA_V0_ACCESS_RDWR,
 539                                         .start = syncbuf + 0x0000,
 540                                         .limit = syncbuf + 0x0fff,
 541                                }, sizeof(struct nv_dma_v0),
 542                                &dmac->sync);
 543         if (ret)
 544                 return ret;
 545
 546         ret = nvif_object_init(&dmac->base.user, 0xf0000001, NV_DMA_IN_MEMORY,
 547                                &(struct nv_dma_v0) {
 548                                         .target = NV_DMA_V0_TARGET_VRAM,
 549                                         .access = NV_DMA_V0_ACCESS_RDWR,
 550                                         .start = 0,
 551                                         .limit = device->info.ram_user - 1,
 552                                }, sizeof(struct nv_dma_v0),
 553                                &dmac->vram);
 554         if (ret)
 555                 return ret;
 556
 557         INIT_LIST_HEAD(&dmac->ctxdma);
 558         return ret;
 559 }
 560
 561 /******************************************************************************
 562  * Core
 563  *****************************************************************************/
 564
 565 struct nv50_mast {
 566         struct nv50_dmac base;
 567 };
 568
 569 static int
 570 nv50_core_create(struct nvif_device *device, struct nvif_object *disp,
 571                  u64 syncbuf, struct nv50_mast *core)
 572 {
 573         struct nv50_disp_core_channel_dma_v0 args = {
 574                 .pushbuf = 0xb0007d00,
 575         };
 576         static const s32 oclass[] = {
 577                 GP102_DISP_CORE_CHANNEL_DMA,
 578                 GP100_DISP_CORE_CHANNEL_DMA,
 579                 GM200_DISP_CORE_CHANNEL_DMA,
 580                 GM107_DISP_CORE_CHANNEL_DMA,
 581                 GK110_DISP_CORE_CHANNEL_DMA,
 582                 GK104_DISP_CORE_CHANNEL_DMA,
 583                 GF110_DISP_CORE_CHANNEL_DMA,
 584                 GT214_DISP_CORE_CHANNEL_DMA,
 585                 GT206_DISP_CORE_CHANNEL_DMA,
 586                 GT200_DISP_CORE_CHANNEL_DMA,
 587                 G82_DISP_CORE_CHANNEL_DMA,
 588                 NV50_DISP_CORE_CHANNEL_DMA,
 589                 0
 590         };
 591
 592         return nv50_dmac_create(device, disp, oclass, 0, &args, sizeof(args),
 593                                 syncbuf, &core->base);
 594 }
 595
 596 /******************************************************************************
 597  * Base
 598  *****************************************************************************/
 599
 600 struct nv50_sync {
 601         struct nv50_dmac base;
 602         u32 addr;
 603         u32 data;
 604 };
 605
 606 static int
 607 nv50_base_create(struct nvif_device *device, struct nvif_object *disp,
 608                  int head, u64 syncbuf, struct nv50_sync *base)
 609 {
 610         struct nv50_disp_base_channel_dma_v0 args = {
 611                 .pushbuf = 0xb0007c00 | head,
 612                 .head = head,
 613         };
 614         static const s32 oclass[] = {
 615                 GK110_DISP_BASE_CHANNEL_DMA,
 616                 GK104_DISP_BASE_CHANNEL_DMA,
 617                 GF110_DISP_BASE_CHANNEL_DMA,
 618                 GT214_DISP_BASE_CHANNEL_DMA,
 619                 GT200_DISP_BASE_CHANNEL_DMA,
 620                 G82_DISP_BASE_CHANNEL_DMA,
 621                 NV50_DISP_BASE_CHANNEL_DMA,
 622                 0
 623         };
 624
 625         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 626                                 syncbuf, &base->base);
 627 }
 628
 629 /******************************************************************************
 630  * Overlay
 631  *****************************************************************************/
 632
 633 struct nv50_ovly {
 634         struct nv50_dmac base;
 635 };
 636
 637 static int
 638 nv50_ovly_create(struct nvif_device *device, struct nvif_object *disp,
 639                  int head, u64 syncbuf, struct nv50_ovly *ovly)
 640 {
 641         struct nv50_disp_overlay_channel_dma_v0 args = {
 642                 .pushbuf = 0xb0007e00 | head,
 643                 .head = head,
 644         };
 645         static const s32 oclass[] = {
 646                 GK104_DISP_OVERLAY_CONTROL_DMA,
 647                 GF110_DISP_OVERLAY_CONTROL_DMA,
 648                 GT214_DISP_OVERLAY_CHANNEL_DMA,
 649                 GT200_DISP_OVERLAY_CHANNEL_DMA,
 650                 G82_DISP_OVERLAY_CHANNEL_DMA,
 651                 NV50_DISP_OVERLAY_CHANNEL_DMA,
 652                 0
 653         };
 654
 655         return nv50_dmac_create(device, disp, oclass, head, &args, sizeof(args),
 656                                 syncbuf, &ovly->base);
 657 }
 658
 659 struct nv50_head {
 660         struct nouveau_crtc base;
 661         struct nv50_ovly ovly;
 662         struct nv50_oimm oimm;
 663 };
 664
 665 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 666 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 667 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 668 #define nv50_chan(c) (&(c)->base.base)
 669 #define nv50_vers(c) nv50_chan(c)->user.oclass
 670
 671 struct nv50_disp {
 672         struct nvif_object *disp;
 673         struct nv50_mast mast;
 674
 675         struct nouveau_bo *sync;
 676
 677         struct mutex mutex;
 678 };
 679
 680 static struct nv50_disp *
 681 nv50_disp(struct drm_device *dev)
 682 {
 683         return nouveau_display(dev)->priv;
 684 }
 685
 686 #define nv50_mast(d) (&nv50_disp(d)->mast)
 687
 688 /******************************************************************************
 689  * EVO channel helpers
 690  *****************************************************************************/
 691 static u32 *
 692 evo_wait(void *evoc, int nr)
 693 {
 694         struct nv50_dmac *dmac = evoc;
 695         struct nvif_device *device = dmac->base.device;
 696         u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
 697
 698         mutex_lock(&dmac->lock);
 699         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 700                 dmac->ptr[put] = 0x20000000;
 701
 702                 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
 703                 if (nvif_msec(device, 2000,
 704                         if (!nvif_rd32(&dmac->base.user, 0x0004))
 705                                 break;
 706                 ) < 0) {
 707                         mutex_unlock(&dmac->lock);
 708                         pr_err("nouveau: evo channel stalled\n");
 709                         return NULL;
 710                 }
 711
 712                 put = 0;
 713         }
 714
 715         return dmac->ptr + put;
 716 }
 717
 718 static void
 719 evo_kick(u32 *push, void *evoc)
 720 {
 721         struct nv50_dmac *dmac = evoc;
 722         nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 723         mutex_unlock(&dmac->lock);
 724 }
 725
 726 #define evo_mthd(p, m, s) do {                                          \
 727         const u32 _m = (m), _s = (s);                                   \
 728         if (drm_debug & DRM_UT_KMS)                                     \
 729                 pr_err("%04x %d %s\n", _m, _s, __func__);               \
 730         *((p)++) = ((_s << 18) | _m);                                   \
 731 } while(0)
 732
 733 #define evo_data(p, d) do {                                             \
 734         const u32 _d = (d);                                             \
 735         if (drm_debug & DRM_UT_KMS)                                     \
 736                 pr_err("\t%08x\n", _d);                                 \
 737         *((p)++) = _d;                                                  \
 738 } while(0)
 739
 740 /******************************************************************************
 741  * Plane
 742  *****************************************************************************/
 743 #define nv50_wndw(p) container_of((p), struct nv50_wndw, plane)
 744
 745 struct nv50_wndw {
 746         const struct nv50_wndw_func *func;
 747         struct nv50_dmac *dmac;
 748
 749         struct drm_plane plane;
 750
 751         struct nvif_notify notify;
 752         u16 ntfy;
 753         u16 sema;
 754         u32 data;
 755 };
 756
 757 struct nv50_wndw_func {
 758         void *(*dtor)(struct nv50_wndw *);
 759         int (*acquire)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
 760                        struct nv50_head_atom *asyh);
 761         void (*release)(struct nv50_wndw *, struct nv50_wndw_atom *asyw,
 762                         struct nv50_head_atom *asyh);
 763         void (*prepare)(struct nv50_wndw *, struct nv50_head_atom *asyh,
 764                         struct nv50_wndw_atom *asyw);
 765
 766         void (*sema_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 767         void (*sema_clr)(struct nv50_wndw *);
 768         void (*ntfy_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 769         void (*ntfy_clr)(struct nv50_wndw *);
 770         int (*ntfy_wait_begun)(struct nv50_wndw *, struct nv50_wndw_atom *);
 771         void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *);
 772         void (*image_clr)(struct nv50_wndw *);
 773         void (*lut)(struct nv50_wndw *, struct nv50_wndw_atom *);
 774         void (*point)(struct nv50_wndw *, struct nv50_wndw_atom *);
 775
 776         u32 (*update)(struct nv50_wndw *, u32 interlock);
 777 };
 778
 779 static int
 780 nv50_wndw_wait_armed(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
 781 {
 782         if (asyw->set.ntfy)
 783                 return wndw->func->ntfy_wait_begun(wndw, asyw);
 784         return 0;
 785 }
 786
 787 static u32
 788 nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 interlock, bool flush,
 789                     struct nv50_wndw_atom *asyw)
 790 {
 791         if (asyw->clr.sema && (!asyw->set.sema || flush))
 792                 wndw->func->sema_clr(wndw);
 793         if (asyw->clr.ntfy && (!asyw->set.ntfy || flush))
 794                 wndw->func->ntfy_clr(wndw);
 795         if (asyw->clr.image && (!asyw->set.image || flush))
 796                 wndw->func->image_clr(wndw);
 797
 798         return flush ? wndw->func->update(wndw, interlock) : 0;
 799 }
 800
 801 static u32
 802 nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 interlock,
 803                     struct nv50_wndw_atom *asyw)
 804 {
 805         if (interlock) {
 806                 asyw->image.mode = 0;
 807                 asyw->image.interval = 1;
 808         }
 809
 810         if (asyw->set.sema ) wndw->func->sema_set (wndw, asyw);
 811         if (asyw->set.ntfy ) wndw->func->ntfy_set (wndw, asyw);
 812         if (asyw->set.image) wndw->func->image_set(wndw, asyw);
 813         if (asyw->set.lut  ) wndw->func->lut      (wndw, asyw);
 814         if (asyw->set.point) wndw->func->point    (wndw, asyw);
 815
 816         return wndw->func->update(wndw, interlock);
 817 }
 818
 819 static void
 820 nv50_wndw_atomic_check_release(struct nv50_wndw *wndw,
 821                                struct nv50_wndw_atom *asyw,
 822                                struct nv50_head_atom *asyh)
 823 {
 824         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
 825         NV_ATOMIC(drm, "%s release\n", wndw->plane.name);
 826         wndw->func->release(wndw, asyw, asyh);
 827         asyw->ntfy.handle = 0;
 828         asyw->sema.handle = 0;
 829 }
 830
 831 static int
 832 nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw,
 833                                struct nv50_wndw_atom *asyw,
 834                                struct nv50_head_atom *asyh)
 835 {
 836         struct nouveau_framebuffer *fb = nouveau_framebuffer(asyw->state.fb);
 837         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
 838         int ret;
 839
 840         NV_ATOMIC(drm, "%s acquire\n", wndw->plane.name);
 841         asyw->clip.x1 = 0;
 842         asyw->clip.y1 = 0;
 843         asyw->clip.x2 = asyh->state.mode.hdisplay;
 844         asyw->clip.y2 = asyh->state.mode.vdisplay;
 845
 846         asyw->image.w = fb->base.width;
 847         asyw->image.h = fb->base.height;
 848         asyw->image.kind = (fb->nvbo->tile_flags & 0x0000ff00) >> 8;
 849
 850         if (asyh->state.pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC)
 851                 asyw->interval = 0;
 852         else
 853                 asyw->interval = 1;
 854
 855         if (asyw->image.kind) {
 856                 asyw->image.layout = 0;
 857                 if (drm->client.device.info.chipset >= 0xc0)
 858                         asyw->image.block = fb->nvbo->tile_mode >> 4;
 859                 else
 860                         asyw->image.block = fb->nvbo->tile_mode;
 861                 asyw->image.pitch = (fb->base.pitches[0] / 4) << 4;
 862         } else {
 863                 asyw->image.layout = 1;
 864                 asyw->image.block  = 0;
 865                 asyw->image.pitch  = fb->base.pitches[0];
 866         }
 867
 868         ret = wndw->func->acquire(wndw, asyw, asyh);
 869         if (ret)
 870                 return ret;
 871
 872         if (asyw->set.image) {
 873                 if (!(asyw->image.mode = asyw->interval ? 0 : 1))
 874                         asyw->image.interval = asyw->interval;
 875                 else
 876                         asyw->image.interval = 0;
 877         }
 878
 879         return 0;
 880 }
 881
 882 static int
 883 nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state)
 884 {
 885         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 886         struct nv50_wndw *wndw = nv50_wndw(plane);
 887         struct nv50_wndw_atom *armw = nv50_wndw_atom(wndw->plane.state);
 888         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
 889         struct nv50_head_atom *harm = NULL, *asyh = NULL;
 890         bool varm = false, asyv = false, asym = false;
 891         int ret;
 892
 893         NV_ATOMIC(drm, "%s atomic_check\n", plane->name);
 894         if (asyw->state.crtc) {
 895                 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
 896                 if (IS_ERR(asyh))
 897                         return PTR_ERR(asyh);
 898                 asym = drm_atomic_crtc_needs_modeset(&asyh->state);
 899                 asyv = asyh->state.active;
 900         }
 901
 902         if (armw->state.crtc) {
 903                 harm = nv50_head_atom_get(asyw->state.state, armw->state.crtc);
 904                 if (IS_ERR(harm))
 905                         return PTR_ERR(harm);
 906                 varm = harm->state.crtc->state->active;
 907         }
 908
 909         if (asyv) {
 910                 asyw->point.x = asyw->state.crtc_x;
 911                 asyw->point.y = asyw->state.crtc_y;
 912                 if (memcmp(&armw->point, &asyw->point, sizeof(asyw->point)))
 913                         asyw->set.point = true;
 914
 915                 ret = nv50_wndw_atomic_check_acquire(wndw, asyw, asyh);
 916                 if (ret)
 917                         return ret;
 918         } else
 919         if (varm) {
 920                 nv50_wndw_atomic_check_release(wndw, asyw, harm);
 921         } else {
 922                 return 0;
 923         }
 924
 925         if (!asyv || asym) {
 926                 asyw->clr.ntfy = armw->ntfy.handle != 0;
 927                 asyw->clr.sema = armw->sema.handle != 0;
 928                 if (wndw->func->image_clr)
 929                         asyw->clr.image = armw->image.handle != 0;
 930                 asyw->set.lut = wndw->func->lut && asyv;
 931         }
 932
 933         return 0;
 934 }
 935
 936 static void
 937 nv50_wndw_cleanup_fb(struct drm_plane *plane, struct drm_plane_state *old_state)
 938 {
 939         struct nouveau_framebuffer *fb = nouveau_framebuffer(old_state->fb);
 940         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 941
 942         NV_ATOMIC(drm, "%s cleanup: %p\n", plane->name, old_state->fb);
 943         if (!old_state->fb)
 944                 return;
 945
 946         nouveau_bo_unpin(fb->nvbo);
 947 }
 948
 949 static int
 950 nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)
 951 {
 952         struct nouveau_framebuffer *fb = nouveau_framebuffer(state->fb);
 953         struct nouveau_drm *drm = nouveau_drm(plane->dev);
 954         struct nv50_wndw *wndw = nv50_wndw(plane);
 955         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
 956         struct nv50_head_atom *asyh;
 957         struct nv50_dmac_ctxdma *ctxdma;
 958         int ret;
 959
 960         NV_ATOMIC(drm, "%s prepare: %p\n", plane->name, state->fb);
 961         if (!asyw->state.fb)
 962                 return 0;
 963
 964         ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM, true);
 965         if (ret)
 966                 return ret;
 967
 968         ctxdma = nv50_dmac_ctxdma_new(wndw->dmac, fb);
 969         if (IS_ERR(ctxdma)) {
 970                 nouveau_bo_unpin(fb->nvbo);
 971                 return PTR_ERR(ctxdma);
 972         }
 973
 974         asyw->state.fence = reservation_object_get_excl_rcu(fb->nvbo->bo.resv);
 975         asyw->image.handle = ctxdma->object.handle;
 976         asyw->image.offset = fb->nvbo->bo.offset;
 977
 978         if (wndw->func->prepare) {
 979                 asyh = nv50_head_atom_get(asyw->state.state, asyw->state.crtc);
 980                 if (IS_ERR(asyh))
 981                         return PTR_ERR(asyh);
 982
 983                 wndw->func->prepare(wndw, asyh, asyw);
 984         }
 985
 986         return 0;
 987 }
 988
 989 static const struct drm_plane_helper_funcs
 990 nv50_wndw_helper = {
 991         .prepare_fb = nv50_wndw_prepare_fb,
 992         .cleanup_fb = nv50_wndw_cleanup_fb,
 993         .atomic_check = nv50_wndw_atomic_check,
 994 };
 995
 996 static void
 997 nv50_wndw_atomic_destroy_state(struct drm_plane *plane,
 998                                struct drm_plane_state *state)
 999 {
1000         struct nv50_wndw_atom *asyw = nv50_wndw_atom(state);
1001         __drm_atomic_helper_plane_destroy_state(&asyw->state);
1002         kfree(asyw);
1003 }
1004
1005 static struct drm_plane_state *
1006 nv50_wndw_atomic_duplicate_state(struct drm_plane *plane)
1007 {
1008         struct nv50_wndw_atom *armw = nv50_wndw_atom(plane->state);
1009         struct nv50_wndw_atom *asyw;
1010         if (!(asyw = kmalloc(sizeof(*asyw), GFP_KERNEL)))
1011                 return NULL;
1012         __drm_atomic_helper_plane_duplicate_state(plane, &asyw->state);
1013         asyw->interval = 1;
1014         asyw->sema = armw->sema;
1015         asyw->ntfy = armw->ntfy;
1016         asyw->image = armw->image;
1017         asyw->point = armw->point;
1018         asyw->lut = armw->lut;
1019         asyw->clr.mask = 0;
1020         asyw->set.mask = 0;
1021         return &asyw->state;
1022 }
1023
1024 static void
1025 nv50_wndw_reset(struct drm_plane *plane)
1026 {
1027         struct nv50_wndw_atom *asyw;
1028
1029         if (WARN_ON(!(asyw = kzalloc(sizeof(*asyw), GFP_KERNEL))))
1030                 return;
1031
1032         if (plane->state)
1033                 plane->funcs->atomic_destroy_state(plane, plane->state);
1034         plane->state = &asyw->state;
1035         plane->state->plane = plane;
1036         plane->state->rotation = DRM_ROTATE_0;
1037 }
1038
1039 static void
1040 nv50_wndw_destroy(struct drm_plane *plane)
1041 {
1042         struct nv50_wndw *wndw = nv50_wndw(plane);
1043         void *data;
1044         nvif_notify_fini(&wndw->notify);
1045         data = wndw->func->dtor(wndw);
1046         drm_plane_cleanup(&wndw->plane);
1047         kfree(data);
1048 }
1049
1050 static const struct drm_plane_funcs
1051 nv50_wndw = {
1052         .update_plane = drm_atomic_helper_update_plane,
1053         .disable_plane = drm_atomic_helper_disable_plane,
1054         .destroy = nv50_wndw_destroy,
1055         .reset = nv50_wndw_reset,
1056         .set_property = drm_atomic_helper_plane_set_property,
1057         .atomic_duplicate_state = nv50_wndw_atomic_duplicate_state,
1058         .atomic_destroy_state = nv50_wndw_atomic_destroy_state,
1059 };
1060
1061 static void
1062 nv50_wndw_fini(struct nv50_wndw *wndw)
1063 {
1064         nvif_notify_put(&wndw->notify);
1065 }
1066
1067 static void
1068 nv50_wndw_init(struct nv50_wndw *wndw)
1069 {
1070         nvif_notify_get(&wndw->notify);
1071 }
1072
1073 static int
1074 nv50_wndw_ctor(const struct nv50_wndw_func *func, struct drm_device *dev,
1075                enum drm_plane_type type, const char *name, int index,
1076                struct nv50_dmac *dmac, const u32 *format, int nformat,
1077                struct nv50_wndw *wndw)
1078 {
1079         int ret;
1080
1081         wndw->func = func;
1082         wndw->dmac = dmac;
1083
1084         ret = drm_universal_plane_init(dev, &wndw->plane, 0, &nv50_wndw, format,
1085                                        nformat, type, "%s-%d", name, index);
1086         if (ret)
1087                 return ret;
1088
1089         drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);
1090         return 0;
1091 }
1092
1093 /******************************************************************************
1094  * Cursor plane
1095  *****************************************************************************/
1096 #define nv50_curs(p) container_of((p), struct nv50_curs, wndw)
1097
1098 struct nv50_curs {
1099         struct nv50_wndw wndw;
1100         struct nvif_object chan;
1101 };
1102
1103 static u32
1104 nv50_curs_update(struct nv50_wndw *wndw, u32 interlock)
1105 {
1106         struct nv50_curs *curs = nv50_curs(wndw);
1107         nvif_wr32(&curs->chan, 0x0080, 0x00000000);
1108         return 0;
1109 }
1110
1111 static void
1112 nv50_curs_point(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1113 {
1114         struct nv50_curs *curs = nv50_curs(wndw);
1115         nvif_wr32(&curs->chan, 0x0084, (asyw->point.y << 16) | asyw->point.x);
1116 }
1117
1118 static void
1119 nv50_curs_prepare(struct nv50_wndw *wndw, struct nv50_head_atom *asyh,
1120                   struct nv50_wndw_atom *asyw)
1121 {
1122         asyh->curs.handle = nv50_disp(wndw->plane.dev)->mast.base.vram.handle;
1123         asyh->curs.offset = asyw->image.offset;
1124         asyh->set.curs = asyh->curs.visible;
1125 }
1126
1127 static void
1128 nv50_curs_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1129                   struct nv50_head_atom *asyh)
1130 {
1131         asyh->curs.visible = false;
1132 }
1133
1134 static int
1135 nv50_curs_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1136                   struct nv50_head_atom *asyh)
1137 {
1138         int ret;
1139
1140         ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip,
1141                                            DRM_PLANE_HELPER_NO_SCALING,
1142                                            DRM_PLANE_HELPER_NO_SCALING,
1143                                            true, true);
1144         asyh->curs.visible = asyw->state.visible;
1145         if (ret || !asyh->curs.visible)
1146                 return ret;
1147
1148         switch (asyw->state.fb->width) {
1149         case 32: asyh->curs.layout = 0; break;
1150         case 64: asyh->curs.layout = 1; break;
1151         default:
1152                 return -EINVAL;
1153         }
1154
1155         if (asyw->state.fb->width != asyw->state.fb->height)
1156                 return -EINVAL;
1157
1158         switch (asyw->state.fb->format->format) {
1159         case DRM_FORMAT_ARGB8888: asyh->curs.format = 1; break;
1160         default:
1161                 WARN_ON(1);
1162                 return -EINVAL;
1163         }
1164
1165         return 0;
1166 }
1167
1168 static void *
1169 nv50_curs_dtor(struct nv50_wndw *wndw)
1170 {
1171         struct nv50_curs *curs = nv50_curs(wndw);
1172         nvif_object_fini(&curs->chan);
1173         return curs;
1174 }
1175
1176 static const u32
1177 nv50_curs_format[] = {
1178         DRM_FORMAT_ARGB8888,
1179 };
1180
1181 static const struct nv50_wndw_func
1182 nv50_curs = {
1183         .dtor = nv50_curs_dtor,
1184         .acquire = nv50_curs_acquire,
1185         .release = nv50_curs_release,
1186         .prepare = nv50_curs_prepare,
1187         .point = nv50_curs_point,
1188         .update = nv50_curs_update,
1189 };
1190
1191 static int
1192 nv50_curs_new(struct nouveau_drm *drm, struct nv50_head *head,
1193               struct nv50_curs **pcurs)
1194 {
1195         static const struct nvif_mclass curses[] = {
1196                 { GK104_DISP_CURSOR, 0 },
1197                 { GF110_DISP_CURSOR, 0 },
1198                 { GT214_DISP_CURSOR, 0 },
1199                 {   G82_DISP_CURSOR, 0 },
1200                 {  NV50_DISP_CURSOR, 0 },
1201                 {}
1202         };
1203         struct nv50_disp_cursor_v0 args = {
1204                 .head = head->base.index,
1205         };
1206         struct nv50_disp *disp = nv50_disp(drm->dev);
1207         struct nv50_curs *curs;
1208         int cid, ret;
1209
1210         cid = nvif_mclass(disp->disp, curses);
1211         if (cid < 0) {
1212                 NV_ERROR(drm, "No supported cursor immediate class\n");
1213                 return cid;
1214         }
1215
1216         if (!(curs = *pcurs = kzalloc(sizeof(*curs), GFP_KERNEL)))
1217                 return -ENOMEM;
1218
1219         ret = nv50_wndw_ctor(&nv50_curs, drm->dev, DRM_PLANE_TYPE_CURSOR,
1220                              "curs", head->base.index, &disp->mast.base,
1221                              nv50_curs_format, ARRAY_SIZE(nv50_curs_format),
1222                              &curs->wndw);
1223         if (ret) {
1224                 kfree(curs);
1225                 return ret;
1226         }
1227
1228         ret = nvif_object_init(disp->disp, 0, curses[cid].oclass, &args,
1229                                sizeof(args), &curs->chan);
1230         if (ret) {
1231                 NV_ERROR(drm, "curs%04x allocation failed: %d\n",
1232                          curses[cid].oclass, ret);
1233                 return ret;
1234         }
1235
1236         return 0;
1237 }
1238
1239 /******************************************************************************
1240  * Primary plane
1241  *****************************************************************************/
1242 #define nv50_base(p) container_of((p), struct nv50_base, wndw)
1243
1244 struct nv50_base {
1245         struct nv50_wndw wndw;
1246         struct nv50_sync chan;
1247         int id;
1248 };
1249
1250 static int
1251 nv50_base_notify(struct nvif_notify *notify)
1252 {
1253         return NVIF_NOTIFY_KEEP;
1254 }
1255
1256 static void
1257 nv50_base_lut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1258 {
1259         struct nv50_base *base = nv50_base(wndw);
1260         u32 *push;
1261         if ((push = evo_wait(&base->chan, 2))) {
1262                 evo_mthd(push, 0x00e0, 1);
1263                 evo_data(push, asyw->lut.enable << 30);
1264                 evo_kick(push, &base->chan);
1265         }
1266 }
1267
1268 static void
1269 nv50_base_image_clr(struct nv50_wndw *wndw)
1270 {
1271         struct nv50_base *base = nv50_base(wndw);
1272         u32 *push;
1273         if ((push = evo_wait(&base->chan, 4))) {
1274                 evo_mthd(push, 0x0084, 1);
1275                 evo_data(push, 0x00000000);
1276                 evo_mthd(push, 0x00c0, 1);
1277                 evo_data(push, 0x00000000);
1278                 evo_kick(push, &base->chan);
1279         }
1280 }
1281
1282 static void
1283 nv50_base_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1284 {
1285         struct nv50_base *base = nv50_base(wndw);
1286         const s32 oclass = base->chan.base.base.user.oclass;
1287         u32 *push;
1288         if ((push = evo_wait(&base->chan, 10))) {
1289                 evo_mthd(push, 0x0084, 1);
1290                 evo_data(push, (asyw->image.mode << 8) |
1291                                (asyw->image.interval << 4));
1292                 evo_mthd(push, 0x00c0, 1);
1293                 evo_data(push, asyw->image.handle);
1294                 if (oclass < G82_DISP_BASE_CHANNEL_DMA) {
1295                         evo_mthd(push, 0x0800, 5);
1296                         evo_data(push, asyw->image.offset >> 8);
1297                         evo_data(push, 0x00000000);
1298                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1299                         evo_data(push, (asyw->image.layout << 20) |
1300                                         asyw->image.pitch |
1301                                         asyw->image.block);
1302                         evo_data(push, (asyw->image.kind << 16) |
1303                                        (asyw->image.format << 8));
1304                 } else
1305                 if (oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1306                         evo_mthd(push, 0x0800, 5);
1307                         evo_data(push, asyw->image.offset >> 8);
1308                         evo_data(push, 0x00000000);
1309                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1310                         evo_data(push, (asyw->image.layout << 20) |
1311                                         asyw->image.pitch |
1312                                         asyw->image.block);
1313                         evo_data(push, asyw->image.format << 8);
1314                 } else {
1315                         evo_mthd(push, 0x0400, 5);
1316                         evo_data(push, asyw->image.offset >> 8);
1317                         evo_data(push, 0x00000000);
1318                         evo_data(push, (asyw->image.h << 16) | asyw->image.w);
1319                         evo_data(push, (asyw->image.layout << 24) |
1320                                         asyw->image.pitch |
1321                                         asyw->image.block);
1322                         evo_data(push, asyw->image.format << 8);
1323                 }
1324                 evo_kick(push, &base->chan);
1325         }
1326 }
1327
1328 static void
1329 nv50_base_ntfy_clr(struct nv50_wndw *wndw)
1330 {
1331         struct nv50_base *base = nv50_base(wndw);
1332         u32 *push;
1333         if ((push = evo_wait(&base->chan, 2))) {
1334                 evo_mthd(push, 0x00a4, 1);
1335                 evo_data(push, 0x00000000);
1336                 evo_kick(push, &base->chan);
1337         }
1338 }
1339
1340 static void
1341 nv50_base_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1342 {
1343         struct nv50_base *base = nv50_base(wndw);
1344         u32 *push;
1345         if ((push = evo_wait(&base->chan, 3))) {
1346                 evo_mthd(push, 0x00a0, 2);
1347                 evo_data(push, (asyw->ntfy.awaken << 30) | asyw->ntfy.offset);
1348                 evo_data(push, asyw->ntfy.handle);
1349                 evo_kick(push, &base->chan);
1350         }
1351 }
1352
1353 static void
1354 nv50_base_sema_clr(struct nv50_wndw *wndw)
1355 {
1356         struct nv50_base *base = nv50_base(wndw);
1357         u32 *push;
1358         if ((push = evo_wait(&base->chan, 2))) {
1359                 evo_mthd(push, 0x0094, 1);
1360                 evo_data(push, 0x00000000);
1361                 evo_kick(push, &base->chan);
1362         }
1363 }
1364
1365 static void
1366 nv50_base_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1367 {
1368         struct nv50_base *base = nv50_base(wndw);
1369         u32 *push;
1370         if ((push = evo_wait(&base->chan, 5))) {
1371                 evo_mthd(push, 0x0088, 4);
1372                 evo_data(push, asyw->sema.offset);
1373                 evo_data(push, asyw->sema.acquire);
1374                 evo_data(push, asyw->sema.release);
1375                 evo_data(push, asyw->sema.handle);
1376                 evo_kick(push, &base->chan);
1377         }
1378 }
1379
1380 static u32
1381 nv50_base_update(struct nv50_wndw *wndw, u32 interlock)
1382 {
1383         struct nv50_base *base = nv50_base(wndw);
1384         u32 *push;
1385
1386         if (!(push = evo_wait(&base->chan, 2)))
1387                 return 0;
1388         evo_mthd(push, 0x0080, 1);
1389         evo_data(push, interlock);
1390         evo_kick(push, &base->chan);
1391
1392         if (base->chan.base.base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA)
1393                 return interlock ? 2 << (base->id * 8) : 0;
1394         return interlock ? 2 << (base->id * 4) : 0;
1395 }
1396
1397 static int
1398 nv50_base_ntfy_wait_begun(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
1399 {
1400         struct nouveau_drm *drm = nouveau_drm(wndw->plane.dev);
1401         struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1402         if (nvif_msec(&drm->client.device, 2000ULL,
1403                 u32 data = nouveau_bo_rd32(disp->sync, asyw->ntfy.offset / 4);
1404                 if ((data & 0xc0000000) == 0x40000000)
1405                         break;
1406                 usleep_range(1, 2);
1407         ) < 0)
1408                 return -ETIMEDOUT;
1409         return 0;
1410 }
1411
1412 static void
1413 nv50_base_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1414                   struct nv50_head_atom *asyh)
1415 {
1416         asyh->base.cpp = 0;
1417 }
1418
1419 static int
1420 nv50_base_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
1421                   struct nv50_head_atom *asyh)
1422 {
1423         const struct drm_framebuffer *fb = asyw->state.fb;
1424         int ret;
1425
1426         if (!fb->format->depth)
1427                 return -EINVAL;
1428
1429         ret = drm_plane_helper_check_state(&asyw->state, &asyw->clip,
1430                                            DRM_PLANE_HELPER_NO_SCALING,
1431                                            DRM_PLANE_HELPER_NO_SCALING,
1432                                            false, true);
1433         if (ret)
1434                 return ret;
1435
1436         asyh->base.depth = fb->format->depth;
1437         asyh->base.cpp = fb->format->cpp[0];
1438         asyh->base.x = asyw->state.src.x1 >> 16;
1439         asyh->base.y = asyw->state.src.y1 >> 16;
1440         asyh->base.w = asyw->state.fb->width;
1441         asyh->base.h = asyw->state.fb->height;
1442
1443         switch (fb->format->format) {
1444         case DRM_FORMAT_C8         : asyw->image.format = 0x1e; break;
1445         case DRM_FORMAT_RGB565     : asyw->image.format = 0xe8; break;
1446         case DRM_FORMAT_XRGB1555   :
1447         case DRM_FORMAT_ARGB1555   : asyw->image.format = 0xe9; break;
1448         case DRM_FORMAT_XRGB8888   :
1449         case DRM_FORMAT_ARGB8888   : asyw->image.format = 0xcf; break;
1450         case DRM_FORMAT_XBGR2101010:
1451         case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break;
1452         case DRM_FORMAT_XBGR8888   :
1453         case DRM_FORMAT_ABGR8888   : asyw->image.format = 0xd5; break;
1454         default:
1455                 WARN_ON(1);
1456                 return -EINVAL;
1457         }
1458
1459         asyw->lut.enable = 1;
1460         asyw->set.image = true;
1461         return 0;
1462 }
1463
1464 static void *
1465 nv50_base_dtor(struct nv50_wndw *wndw)
1466 {
1467         struct nv50_disp *disp = nv50_disp(wndw->plane.dev);
1468         struct nv50_base *base = nv50_base(wndw);
1469         nv50_dmac_destroy(&base->chan.base, disp->disp);
1470         return base;
1471 }
1472
1473 static const u32
1474 nv50_base_format[] = {
1475         DRM_FORMAT_C8,
1476         DRM_FORMAT_RGB565,
1477         DRM_FORMAT_XRGB1555,
1478         DRM_FORMAT_ARGB1555,
1479         DRM_FORMAT_XRGB8888,
1480         DRM_FORMAT_ARGB8888,
1481         DRM_FORMAT_XBGR2101010,
1482         DRM_FORMAT_ABGR2101010,
1483         DRM_FORMAT_XBGR8888,
1484         DRM_FORMAT_ABGR8888,
1485 };
1486
1487 static const struct nv50_wndw_func
1488 nv50_base = {
1489         .dtor = nv50_base_dtor,
1490         .acquire = nv50_base_acquire,
1491         .release = nv50_base_release,
1492         .sema_set = nv50_base_sema_set,
1493         .sema_clr = nv50_base_sema_clr,
1494         .ntfy_set = nv50_base_ntfy_set,
1495         .ntfy_clr = nv50_base_ntfy_clr,
1496         .ntfy_wait_begun = nv50_base_ntfy_wait_begun,
1497         .image_set = nv50_base_image_set,
1498         .image_clr = nv50_base_image_clr,
1499         .lut = nv50_base_lut,
1500         .update = nv50_base_update,
1501 };
1502
1503 static int
1504 nv50_base_new(struct nouveau_drm *drm, struct nv50_head *head,
1505               struct nv50_base **pbase)
1506 {
1507         struct nv50_disp *disp = nv50_disp(drm->dev);
1508         struct nv50_base *base;
1509         int ret;
1510
1511         if (!(base = *pbase = kzalloc(sizeof(*base), GFP_KERNEL)))
1512                 return -ENOMEM;
1513         base->id = head->base.index;
1514         base->wndw.ntfy = EVO_FLIP_NTFY0(base->id);
1515         base->wndw.sema = EVO_FLIP_SEM0(base->id);
1516         base->wndw.data = 0x00000000;
1517
1518         ret = nv50_wndw_ctor(&nv50_base, drm->dev, DRM_PLANE_TYPE_PRIMARY,
1519                              "base", base->id, &base->chan.base,
1520                              nv50_base_format, ARRAY_SIZE(nv50_base_format),
1521                              &base->wndw);
1522         if (ret) {
1523                 kfree(base);
1524                 return ret;
1525         }
1526
1527         ret = nv50_base_create(&drm->client.device, disp->disp, base->id,
1528                                disp->sync->bo.offset, &base->chan);
1529         if (ret)
1530                 return ret;
1531
1532         return nvif_notify_init(&base->chan.base.base.user, nv50_base_notify,
1533                                 false,
1534                                 NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT,
1535                                 &(struct nvif_notify_uevent_req) {},
1536                                 sizeof(struct nvif_notify_uevent_req),
1537                                 sizeof(struct nvif_notify_uevent_rep),
1538                                 &base->wndw.notify);
1539 }
1540
1541 /******************************************************************************
1542  * Head
1543  *****************************************************************************/
1544 static void
1545 nv50_head_procamp(struct nv50_head *head, struct nv50_head_atom *asyh)
1546 {
1547         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1548         u32 *push;
1549         if ((push = evo_wait(core, 2))) {
1550                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1551                         evo_mthd(push, 0x08a8 + (head->base.index * 0x400), 1);
1552                 else
1553                         evo_mthd(push, 0x0498 + (head->base.index * 0x300), 1);
1554                 evo_data(push, (asyh->procamp.sat.sin << 20) |
1555                                (asyh->procamp.sat.cos << 8));
1556                 evo_kick(push, core);
1557         }
1558 }
1559
1560 static void
1561 nv50_head_dither(struct nv50_head *head, struct nv50_head_atom *asyh)
1562 {
1563         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1564         u32 *push;
1565         if ((push = evo_wait(core, 2))) {
1566                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1567                         evo_mthd(push, 0x08a0 + (head->base.index * 0x0400), 1);
1568                 else
1569                 if (core->base.user.oclass < GK104_DISP_CORE_CHANNEL_DMA)
1570                         evo_mthd(push, 0x0490 + (head->base.index * 0x0300), 1);
1571                 else
1572                         evo_mthd(push, 0x04a0 + (head->base.index * 0x0300), 1);
1573                 evo_data(push, (asyh->dither.mode << 3) |
1574                                (asyh->dither.bits << 1) |
1575                                 asyh->dither.enable);
1576                 evo_kick(push, core);
1577         }
1578 }
1579
1580 static void
1581 nv50_head_ovly(struct nv50_head *head, struct nv50_head_atom *asyh)
1582 {
1583         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1584         u32 bounds = 0;
1585         u32 *push;
1586
1587         if (asyh->base.cpp) {
1588                 switch (asyh->base.cpp) {
1589                 case 8: bounds |= 0x00000500; break;
1590                 case 4: bounds |= 0x00000300; break;
1591                 case 2: bounds |= 0x00000100; break;
1592                 default:
1593                         WARN_ON(1);
1594                         break;
1595                 }
1596                 bounds |= 0x00000001;
1597         }
1598
1599         if ((push = evo_wait(core, 2))) {
1600                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1601                         evo_mthd(push, 0x0904 + head->base.index * 0x400, 1);
1602                 else
1603                         evo_mthd(push, 0x04d4 + head->base.index * 0x300, 1);
1604                 evo_data(push, bounds);
1605                 evo_kick(push, core);
1606         }
1607 }
1608
1609 static void
1610 nv50_head_base(struct nv50_head *head, struct nv50_head_atom *asyh)
1611 {
1612         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1613         u32 bounds = 0;
1614         u32 *push;
1615
1616         if (asyh->base.cpp) {
1617                 switch (asyh->base.cpp) {
1618                 case 8: bounds |= 0x00000500; break;
1619                 case 4: bounds |= 0x00000300; break;
1620                 case 2: bounds |= 0x00000100; break;
1621                 case 1: bounds |= 0x00000000; break;
1622                 default:
1623                         WARN_ON(1);
1624                         break;
1625                 }
1626                 bounds |= 0x00000001;
1627         }
1628
1629         if ((push = evo_wait(core, 2))) {
1630                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1631                         evo_mthd(push, 0x0900 + head->base.index * 0x400, 1);
1632                 else
1633                         evo_mthd(push, 0x04d0 + head->base.index * 0x300, 1);
1634                 evo_data(push, bounds);
1635                 evo_kick(push, core);
1636         }
1637 }
1638
1639 static void
1640 nv50_head_curs_clr(struct nv50_head *head)
1641 {
1642         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1643         u32 *push;
1644         if ((push = evo_wait(core, 4))) {
1645                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1646                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1647                         evo_data(push, 0x05000000);
1648                 } else
1649                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1650                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 1);
1651                         evo_data(push, 0x05000000);
1652                         evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1653                         evo_data(push, 0x00000000);
1654                 } else {
1655                         evo_mthd(push, 0x0480 + head->base.index * 0x300, 1);
1656                         evo_data(push, 0x05000000);
1657                         evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1658                         evo_data(push, 0x00000000);
1659                 }
1660                 evo_kick(push, core);
1661         }
1662 }
1663
1664 static void
1665 nv50_head_curs_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1666 {
1667         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1668         u32 *push;
1669         if ((push = evo_wait(core, 5))) {
1670                 if (core->base.user.oclass < G82_DISP_BASE_CHANNEL_DMA) {
1671                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1672                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1673                                                     (asyh->curs.format << 24));
1674                         evo_data(push, asyh->curs.offset >> 8);
1675                 } else
1676                 if (core->base.user.oclass < GF110_DISP_BASE_CHANNEL_DMA) {
1677                         evo_mthd(push, 0x0880 + head->base.index * 0x400, 2);
1678                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1679                                                     (asyh->curs.format << 24));
1680                         evo_data(push, asyh->curs.offset >> 8);
1681                         evo_mthd(push, 0x089c + head->base.index * 0x400, 1);
1682                         evo_data(push, asyh->curs.handle);
1683                 } else {
1684                         evo_mthd(push, 0x0480 + head->base.index * 0x300, 2);
1685                         evo_data(push, 0x80000000 | (asyh->curs.layout << 26) |
1686                                                     (asyh->curs.format << 24));
1687                         evo_data(push, asyh->curs.offset >> 8);
1688                         evo_mthd(push, 0x048c + head->base.index * 0x300, 1);
1689                         evo_data(push, asyh->curs.handle);
1690                 }
1691                 evo_kick(push, core);
1692         }
1693 }
1694
1695 static void
1696 nv50_head_core_clr(struct nv50_head *head)
1697 {
1698         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1699         u32 *push;
1700         if ((push = evo_wait(core, 2))) {
1701                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA)
1702                         evo_mthd(push, 0x0874 + head->base.index * 0x400, 1);
1703                 else
1704                         evo_mthd(push, 0x0474 + head->base.index * 0x300, 1);
1705                 evo_data(push, 0x00000000);
1706                 evo_kick(push, core);
1707         }
1708 }
1709
1710 static void
1711 nv50_head_core_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1712 {
1713         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1714         u32 *push;
1715         if ((push = evo_wait(core, 9))) {
1716                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1717                         evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1718                         evo_data(push, asyh->core.offset >> 8);
1719                         evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1720                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1721                         evo_data(push, asyh->core.layout << 20 |
1722                                        (asyh->core.pitch >> 8) << 8 |
1723                                        asyh->core.block);
1724                         evo_data(push, asyh->core.kind << 16 |
1725                                        asyh->core.format << 8);
1726                         evo_data(push, asyh->core.handle);
1727                         evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1728                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1729                         /* EVO will complain with INVALID_STATE if we have an
1730                          * active cursor and (re)specify HeadSetContextDmaIso
1731                          * without also updating HeadSetOffsetCursor.
1732                          */
1733                         asyh->set.curs = asyh->curs.visible;
1734                 } else
1735                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1736                         evo_mthd(push, 0x0860 + head->base.index * 0x400, 1);
1737                         evo_data(push, asyh->core.offset >> 8);
1738                         evo_mthd(push, 0x0868 + head->base.index * 0x400, 4);
1739                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1740                         evo_data(push, asyh->core.layout << 20 |
1741                                        (asyh->core.pitch >> 8) << 8 |
1742                                        asyh->core.block);
1743                         evo_data(push, asyh->core.format << 8);
1744                         evo_data(push, asyh->core.handle);
1745                         evo_mthd(push, 0x08c0 + head->base.index * 0x400, 1);
1746                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1747                 } else {
1748                         evo_mthd(push, 0x0460 + head->base.index * 0x300, 1);
1749                         evo_data(push, asyh->core.offset >> 8);
1750                         evo_mthd(push, 0x0468 + head->base.index * 0x300, 4);
1751                         evo_data(push, (asyh->core.h << 16) | asyh->core.w);
1752                         evo_data(push, asyh->core.layout << 24 |
1753                                        (asyh->core.pitch >> 8) << 8 |
1754                                        asyh->core.block);
1755                         evo_data(push, asyh->core.format << 8);
1756                         evo_data(push, asyh->core.handle);
1757                         evo_mthd(push, 0x04b0 + head->base.index * 0x300, 1);
1758                         evo_data(push, (asyh->core.y << 16) | asyh->core.x);
1759                 }
1760                 evo_kick(push, core);
1761         }
1762 }
1763
1764 static void
1765 nv50_head_lut_clr(struct nv50_head *head)
1766 {
1767         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1768         u32 *push;
1769         if ((push = evo_wait(core, 4))) {
1770                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1771                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1772                         evo_data(push, 0x40000000);
1773                 } else
1774                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1775                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 1);
1776                         evo_data(push, 0x40000000);
1777                         evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1778                         evo_data(push, 0x00000000);
1779                 } else {
1780                         evo_mthd(push, 0x0440 + (head->base.index * 0x300), 1);
1781                         evo_data(push, 0x03000000);
1782                         evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1783                         evo_data(push, 0x00000000);
1784                 }
1785                 evo_kick(push, core);
1786         }
1787 }
1788
1789 static void
1790 nv50_head_lut_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1791 {
1792         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1793         u32 *push;
1794         if ((push = evo_wait(core, 7))) {
1795                 if (core->base.user.oclass < G82_DISP_CORE_CHANNEL_DMA) {
1796                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1797                         evo_data(push, 0xc0000000);
1798                         evo_data(push, asyh->lut.offset >> 8);
1799                 } else
1800                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1801                         evo_mthd(push, 0x0840 + (head->base.index * 0x400), 2);
1802                         evo_data(push, 0xc0000000);
1803                         evo_data(push, asyh->lut.offset >> 8);
1804                         evo_mthd(push, 0x085c + (head->base.index * 0x400), 1);
1805                         evo_data(push, asyh->lut.handle);
1806                 } else {
1807                         evo_mthd(push, 0x0440 + (head->base.index * 0x300), 4);
1808                         evo_data(push, 0x83000000);
1809                         evo_data(push, asyh->lut.offset >> 8);
1810                         evo_data(push, 0x00000000);
1811                         evo_data(push, 0x00000000);
1812                         evo_mthd(push, 0x045c + (head->base.index * 0x300), 1);
1813                         evo_data(push, asyh->lut.handle);
1814                 }
1815                 evo_kick(push, core);
1816         }
1817 }
1818
1819 static void
1820 nv50_head_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
1821 {
1822         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1823         struct nv50_head_mode *m = &asyh->mode;
1824         u32 *push;
1825         if ((push = evo_wait(core, 14))) {
1826                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1827                         evo_mthd(push, 0x0804 + (head->base.index * 0x400), 2);
1828                         evo_data(push, 0x00800000 | m->clock);
1829                         evo_data(push, m->interlace ? 0x00000002 : 0x00000000);
1830                         evo_mthd(push, 0x0810 + (head->base.index * 0x400), 7);
1831                         evo_data(push, 0x00000000);
1832                         evo_data(push, (m->v.active  << 16) | m->h.active );
1833                         evo_data(push, (m->v.synce   << 16) | m->h.synce  );
1834                         evo_data(push, (m->v.blanke  << 16) | m->h.blanke );
1835                         evo_data(push, (m->v.blanks  << 16) | m->h.blanks );
1836                         evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1837                         evo_data(push, asyh->mode.v.blankus);
1838                         evo_mthd(push, 0x082c + (head->base.index * 0x400), 1);
1839                         evo_data(push, 0x00000000);
1840                 } else {
1841                         evo_mthd(push, 0x0410 + (head->base.index * 0x300), 6);
1842                         evo_data(push, 0x00000000);
1843                         evo_data(push, (m->v.active  << 16) | m->h.active );
1844                         evo_data(push, (m->v.synce   << 16) | m->h.synce  );
1845                         evo_data(push, (m->v.blanke  << 16) | m->h.blanke );
1846                         evo_data(push, (m->v.blanks  << 16) | m->h.blanks );
1847                         evo_data(push, (m->v.blank2e << 16) | m->v.blank2s);
1848                         evo_mthd(push, 0x042c + (head->base.index * 0x300), 2);
1849                         evo_data(push, 0x00000000); /* ??? */
1850                         evo_data(push, 0xffffff00);
1851                         evo_mthd(push, 0x0450 + (head->base.index * 0x300), 3);
1852                         evo_data(push, m->clock * 1000);
1853                         evo_data(push, 0x00200000); /* ??? */
1854                         evo_data(push, m->clock * 1000);
1855                 }
1856                 evo_kick(push, core);
1857         }
1858 }
1859
1860 static void
1861 nv50_head_view(struct nv50_head *head, struct nv50_head_atom *asyh)
1862 {
1863         struct nv50_dmac *core = &nv50_disp(head->base.base.dev)->mast.base;
1864         u32 *push;
1865         if ((push = evo_wait(core, 10))) {
1866                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
1867                         evo_mthd(push, 0x08a4 + (head->base.index * 0x400), 1);
1868                         evo_data(push, 0x00000000);
1869                         evo_mthd(push, 0x08c8 + (head->base.index * 0x400), 1);
1870                         evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1871                         evo_mthd(push, 0x08d8 + (head->base.index * 0x400), 2);
1872                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1873                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1874                 } else {
1875                         evo_mthd(push, 0x0494 + (head->base.index * 0x300), 1);
1876                         evo_data(push, 0x00000000);
1877                         evo_mthd(push, 0x04b8 + (head->base.index * 0x300), 1);
1878                         evo_data(push, (asyh->view.iH << 16) | asyh->view.iW);
1879                         evo_mthd(push, 0x04c0 + (head->base.index * 0x300), 3);
1880                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1881                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1882                         evo_data(push, (asyh->view.oH << 16) | asyh->view.oW);
1883                 }
1884                 evo_kick(push, core);
1885         }
1886 }
1887
1888 static void
1889 nv50_head_flush_clr(struct nv50_head *head, struct nv50_head_atom *asyh, bool y)
1890 {
1891         if (asyh->clr.core && (!asyh->set.core || y))
1892                 nv50_head_lut_clr(head);
1893         if (asyh->clr.core && (!asyh->set.core || y))
1894                 nv50_head_core_clr(head);
1895         if (asyh->clr.curs && (!asyh->set.curs || y))
1896                 nv50_head_curs_clr(head);
1897 }
1898
1899 static void
1900 nv50_head_flush_set(struct nv50_head *head, struct nv50_head_atom *asyh)
1901 {
1902         if (asyh->set.view   ) nv50_head_view    (head, asyh);
1903         if (asyh->set.mode   ) nv50_head_mode    (head, asyh);
1904         if (asyh->set.core   ) nv50_head_lut_set (head, asyh);
1905         if (asyh->set.core   ) nv50_head_core_set(head, asyh);
1906         if (asyh->set.curs   ) nv50_head_curs_set(head, asyh);
1907         if (asyh->set.base   ) nv50_head_base    (head, asyh);
1908         if (asyh->set.ovly   ) nv50_head_ovly    (head, asyh);
1909         if (asyh->set.dither ) nv50_head_dither  (head, asyh);
1910         if (asyh->set.procamp) nv50_head_procamp (head, asyh);
1911 }
1912
1913 static void
1914 nv50_head_atomic_check_procamp(struct nv50_head_atom *armh,
1915                                struct nv50_head_atom *asyh,
1916                                struct nouveau_conn_atom *asyc)
1917 {
1918         const int vib = asyc->procamp.color_vibrance - 100;
1919         const int hue = asyc->procamp.vibrant_hue - 90;
1920         const int adj = (vib > 0) ? 50 : 0;
1921         asyh->procamp.sat.cos = ((vib * 2047 + adj) / 100) & 0xfff;
1922         asyh->procamp.sat.sin = ((hue * 2047) / 100) & 0xfff;
1923         asyh->set.procamp = true;
1924 }
1925
1926 static void
1927 nv50_head_atomic_check_dither(struct nv50_head_atom *armh,
1928                               struct nv50_head_atom *asyh,
1929                               struct nouveau_conn_atom *asyc)
1930 {
1931         struct drm_connector *connector = asyc->state.connector;
1932         u32 mode = 0x00;
1933
1934         if (asyc->dither.mode == DITHERING_MODE_AUTO) {
1935                 if (asyh->base.depth > connector->display_info.bpc * 3)
1936                         mode = DITHERING_MODE_DYNAMIC2X2;
1937         } else {
1938                 mode = asyc->dither.mode;
1939         }
1940
1941         if (asyc->dither.depth == DITHERING_DEPTH_AUTO) {
1942                 if (connector->display_info.bpc >= 8)
1943                         mode |= DITHERING_DEPTH_8BPC;
1944         } else {
1945                 mode |= asyc->dither.depth;
1946         }
1947
1948         asyh->dither.enable = mode;
1949         asyh->dither.bits = mode >> 1;
1950         asyh->dither.mode = mode >> 3;
1951         asyh->set.dither = true;
1952 }
1953
1954 static void
1955 nv50_head_atomic_check_view(struct nv50_head_atom *armh,
1956                             struct nv50_head_atom *asyh,
1957                             struct nouveau_conn_atom *asyc)
1958 {
1959         struct drm_connector *connector = asyc->state.connector;
1960         struct drm_display_mode *omode = &asyh->state.adjusted_mode;
1961         struct drm_display_mode *umode = &asyh->state.mode;
1962         int mode = asyc->scaler.mode;
1963         struct edid *edid;
1964
1965         if (connector->edid_blob_ptr)
1966                 edid = (struct edid *)connector->edid_blob_ptr->data;
1967         else
1968                 edid = NULL;
1969
1970         if (!asyc->scaler.full) {
1971                 if (mode == DRM_MODE_SCALE_NONE)
1972                         omode = umode;
1973         } else {
1974                 /* Non-EDID LVDS/eDP mode. */
1975                 mode = DRM_MODE_SCALE_FULLSCREEN;
1976         }
1977
1978         asyh->view.iW = umode->hdisplay;
1979         asyh->view.iH = umode->vdisplay;
1980         asyh->view.oW = omode->hdisplay;
1981         asyh->view.oH = omode->vdisplay;
1982         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
1983                 asyh->view.oH *= 2;
1984
1985         /* Add overscan compensation if necessary, will keep the aspect
1986          * ratio the same as the backend mode unless overridden by the
1987          * user setting both hborder and vborder properties.
1988          */
1989         if ((asyc->scaler.underscan.mode == UNDERSCAN_ON ||
1990             (asyc->scaler.underscan.mode == UNDERSCAN_AUTO &&
1991              drm_detect_hdmi_monitor(edid)))) {
1992                 u32 bX = asyc->scaler.underscan.hborder;
1993                 u32 bY = asyc->scaler.underscan.vborder;
1994                 u32 r = (asyh->view.oH << 19) / asyh->view.oW;
1995
1996                 if (bX) {
1997                         asyh->view.oW -= (bX * 2);
1998                         if (bY) asyh->view.oH -= (bY * 2);
1999                         else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
2000                 } else {
2001                         asyh->view.oW -= (asyh->view.oW >> 4) + 32;
2002                         if (bY) asyh->view.oH -= (bY * 2);
2003                         else    asyh->view.oH  = ((asyh->view.oW * r) + (r / 2)) >> 19;
2004                 }
2005         }
2006
2007         /* Handle CENTER/ASPECT scaling, taking into account the areas
2008          * removed already for overscan compensation.
2009          */
2010         switch (mode) {
2011         case DRM_MODE_SCALE_CENTER:
2012                 asyh->view.oW = min((u16)umode->hdisplay, asyh->view.oW);
2013                 asyh->view.oH = min((u16)umode->vdisplay, asyh->view.oH);
2014                 /* fall-through */
2015         case DRM_MODE_SCALE_ASPECT:
2016                 if (asyh->view.oH < asyh->view.oW) {
2017                         u32 r = (asyh->view.iW << 19) / asyh->view.iH;
2018                         asyh->view.oW = ((asyh->view.oH * r) + (r / 2)) >> 19;
2019                 } else {
2020                         u32 r = (asyh->view.iH << 19) / asyh->view.iW;
2021                         asyh->view.oH = ((asyh->view.oW * r) + (r / 2)) >> 19;
2022                 }
2023                 break;
2024         default:
2025                 break;
2026         }
2027
2028         asyh->set.view = true;
2029 }
2030
2031 static void
2032 nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh)
2033 {
2034         struct drm_display_mode *mode = &asyh->state.adjusted_mode;
2035         u32 ilace   = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
2036         u32 vscan   = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
2037         u32 hbackp  =  mode->htotal - mode->hsync_end;
2038         u32 vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
2039         u32 hfrontp =  mode->hsync_start - mode->hdisplay;
2040         u32 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
2041         u32 blankus;
2042         struct nv50_head_mode *m = &asyh->mode;
2043
2044         m->h.active = mode->htotal;
2045         m->h.synce  = mode->hsync_end - mode->hsync_start - 1;
2046         m->h.blanke = m->h.synce + hbackp;
2047         m->h.blanks = mode->htotal - hfrontp - 1;
2048
2049         m->v.active = mode->vtotal * vscan / ilace;
2050         m->v.synce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
2051         m->v.blanke = m->v.synce + vbackp;
2052         m->v.blanks = m->v.active - vfrontp - 1;
2053
2054         /*XXX: Safe underestimate, even "0" works */
2055         blankus = (m->v.active - mode->vdisplay - 2) * m->h.active;
2056         blankus *= 1000;
2057         blankus /= mode->clock;
2058         m->v.blankus = blankus;
2059
2060         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
2061                 m->v.blank2e =  m->v.active + m->v.synce + vbackp;
2062                 m->v.blank2s =  m->v.blank2e + (mode->vdisplay * vscan / ilace);
2063                 m->v.active  = (m->v.active * 2) + 1;
2064                 m->interlace = true;
2065         } else {
2066                 m->v.blank2e = 0;
2067                 m->v.blank2s = 1;
2068                 m->interlace = false;
2069         }
2070         m->clock = mode->clock;
2071
2072         drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
2073         asyh->set.mode = true;
2074 }
2075
2076 static int
2077 nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state)
2078 {
2079         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
2080         struct nv50_disp *disp = nv50_disp(crtc->dev);
2081         struct nv50_head *head = nv50_head(crtc);
2082         struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2083         struct nv50_head_atom *asyh = nv50_head_atom(state);
2084         struct nouveau_conn_atom *asyc = NULL;
2085         struct drm_connector_state *conns;
2086         struct drm_connector *conn;
2087         int i;
2088
2089         NV_ATOMIC(drm, "%s atomic_check %d\n", crtc->name, asyh->state.active);
2090         if (asyh->state.active) {
2091                 for_each_connector_in_state(asyh->state.state, conn, conns, i) {
2092                         if (conns->crtc == crtc) {
2093                                 asyc = nouveau_conn_atom(conns);
2094                                 break;
2095                         }
2096                 }
2097
2098                 if (armh->state.active) {
2099                         if (asyc) {
2100                                 if (asyh->state.mode_changed)
2101                                         asyc->set.scaler = true;
2102                                 if (armh->base.depth != asyh->base.depth)
2103                                         asyc->set.dither = true;
2104                         }
2105                 } else {
2106                         asyc->set.mask = ~0;
2107                         asyh->set.mask = ~0;
2108                 }
2109
2110                 if (asyh->state.mode_changed)
2111                         nv50_head_atomic_check_mode(head, asyh);
2112
2113                 if (asyc) {
2114                         if (asyc->set.scaler)
2115                                 nv50_head_atomic_check_view(armh, asyh, asyc);
2116                         if (asyc->set.dither)
2117                                 nv50_head_atomic_check_dither(armh, asyh, asyc);
2118                         if (asyc->set.procamp)
2119                                 nv50_head_atomic_check_procamp(armh, asyh, asyc);
2120                 }
2121
2122                 if ((asyh->core.visible = (asyh->base.cpp != 0))) {
2123                         asyh->core.x = asyh->base.x;
2124                         asyh->core.y = asyh->base.y;
2125                         asyh->core.w = asyh->base.w;
2126                         asyh->core.h = asyh->base.h;
2127                 } else
2128                 if ((asyh->core.visible = asyh->curs.visible)) {
2129                         /*XXX: We need to either find some way of having the
2130                          *     primary base layer appear black, while still
2131                          *     being able to display the other layers, or we
2132                          *     need to allocate a dummy black surface here.
2133                          */
2134                         asyh->core.x = 0;
2135                         asyh->core.y = 0;
2136                         asyh->core.w = asyh->state.mode.hdisplay;
2137                         asyh->core.h = asyh->state.mode.vdisplay;
2138                 }
2139                 asyh->core.handle = disp->mast.base.vram.handle;
2140                 asyh->core.offset = 0;
2141                 asyh->core.format = 0xcf;
2142                 asyh->core.kind = 0;
2143                 asyh->core.layout = 1;
2144                 asyh->core.block = 0;
2145                 asyh->core.pitch = ALIGN(asyh->core.w, 64) * 4;
2146                 asyh->lut.handle = disp->mast.base.vram.handle;
2147                 asyh->lut.offset = head->base.lut.nvbo->bo.offset;
2148                 asyh->set.base = armh->base.cpp != asyh->base.cpp;
2149                 asyh->set.ovly = armh->ovly.cpp != asyh->ovly.cpp;
2150         } else {
2151                 asyh->core.visible = false;
2152                 asyh->curs.visible = false;
2153                 asyh->base.cpp = 0;
2154                 asyh->ovly.cpp = 0;
2155         }
2156
2157         if (!drm_atomic_crtc_needs_modeset(&asyh->state)) {
2158                 if (asyh->core.visible) {
2159                         if (memcmp(&armh->core, &asyh->core, sizeof(asyh->core)))
2160                                 asyh->set.core = true;
2161                 } else
2162                 if (armh->core.visible) {
2163                         asyh->clr.core = true;
2164                 }
2165
2166                 if (asyh->curs.visible) {
2167                         if (memcmp(&armh->curs, &asyh->curs, sizeof(asyh->curs)))
2168                                 asyh->set.curs = true;
2169                 } else
2170                 if (armh->curs.visible) {
2171                         asyh->clr.curs = true;
2172                 }
2173         } else {
2174                 asyh->clr.core = armh->core.visible;
2175                 asyh->clr.curs = armh->curs.visible;
2176                 asyh->set.core = asyh->core.visible;
2177                 asyh->set.curs = asyh->curs.visible;
2178         }
2179
2180         if (asyh->clr.mask || asyh->set.mask)
2181                 nv50_atom(asyh->state.state)->lock_core = true;
2182         return 0;
2183 }
2184
2185 static void
2186 nv50_head_lut_load(struct drm_crtc *crtc)
2187 {
2188         struct nv50_disp *disp = nv50_disp(crtc->dev);
2189         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2190         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
2191         int i;
2192
2193         for (i = 0; i < 256; i++) {
2194                 u16 r = nv_crtc->lut.r[i] >> 2;
2195                 u16 g = nv_crtc->lut.g[i] >> 2;
2196                 u16 b = nv_crtc->lut.b[i] >> 2;
2197
2198                 if (disp->disp->oclass < GF110_DISP) {
2199                         writew(r + 0x0000, lut + (i * 0x08) + 0);
2200                         writew(g + 0x0000, lut + (i * 0x08) + 2);
2201                         writew(b + 0x0000, lut + (i * 0x08) + 4);
2202                 } else {
2203                         writew(r + 0x6000, lut + (i * 0x20) + 0);
2204                         writew(g + 0x6000, lut + (i * 0x20) + 2);
2205                         writew(b + 0x6000, lut + (i * 0x20) + 4);
2206                 }
2207         }
2208 }
2209
2210 static int
2211 nv50_head_mode_set_base_atomic(struct drm_crtc *crtc,
2212                                struct drm_framebuffer *fb, int x, int y,
2213                                enum mode_set_atomic state)
2214 {
2215         WARN_ON(1);
2216         return 0;
2217 }
2218
2219 static const struct drm_crtc_helper_funcs
2220 nv50_head_help = {
2221         .mode_set_base_atomic = nv50_head_mode_set_base_atomic,
2222         .load_lut = nv50_head_lut_load,
2223         .atomic_check = nv50_head_atomic_check,
2224 };
2225
2226 static int
2227 nv50_head_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
2228                     uint32_t size)
2229 {
2230         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2231         u32 i;
2232
2233         for (i = 0; i < size; i++) {
2234                 nv_crtc->lut.r[i] = r[i];
2235                 nv_crtc->lut.g[i] = g[i];
2236                 nv_crtc->lut.b[i] = b[i];
2237         }
2238
2239         nv50_head_lut_load(crtc);
2240         return 0;
2241 }
2242
2243 static void
2244 nv50_head_atomic_destroy_state(struct drm_crtc *crtc,
2245                                struct drm_crtc_state *state)
2246 {
2247         struct nv50_head_atom *asyh = nv50_head_atom(state);
2248         __drm_atomic_helper_crtc_destroy_state(&asyh->state);
2249         kfree(asyh);
2250 }
2251
2252 static struct drm_crtc_state *
2253 nv50_head_atomic_duplicate_state(struct drm_crtc *crtc)
2254 {
2255         struct nv50_head_atom *armh = nv50_head_atom(crtc->state);
2256         struct nv50_head_atom *asyh;
2257         if (!(asyh = kmalloc(sizeof(*asyh), GFP_KERNEL)))
2258                 return NULL;
2259         __drm_atomic_helper_crtc_duplicate_state(crtc, &asyh->state);
2260         asyh->view = armh->view;
2261         asyh->mode = armh->mode;
2262         asyh->lut  = armh->lut;
2263         asyh->core = armh->core;
2264         asyh->curs = armh->curs;
2265         asyh->base = armh->base;
2266         asyh->ovly = armh->ovly;
2267         asyh->dither = armh->dither;
2268         asyh->procamp = armh->procamp;
2269         asyh->clr.mask = 0;
2270         asyh->set.mask = 0;
2271         return &asyh->state;
2272 }
2273
2274 static void
2275 __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc,
2276                                struct drm_crtc_state *state)
2277 {
2278         if (crtc->state)
2279                 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
2280         crtc->state = state;
2281         crtc->state->crtc = crtc;
2282 }
2283
2284 static void
2285 nv50_head_reset(struct drm_crtc *crtc)
2286 {
2287         struct nv50_head_atom *asyh;
2288
2289         if (WARN_ON(!(asyh = kzalloc(sizeof(*asyh), GFP_KERNEL))))
2290                 return;
2291
2292         __drm_atomic_helper_crtc_reset(crtc, &asyh->state);
2293 }
2294
2295 static void
2296 nv50_head_destroy(struct drm_crtc *crtc)
2297 {
2298         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
2299         struct nv50_disp *disp = nv50_disp(crtc->dev);
2300         struct nv50_head *head = nv50_head(crtc);
2301
2302         nv50_dmac_destroy(&head->ovly.base, disp->disp);
2303         nv50_pioc_destroy(&head->oimm.base);
2304
2305         nouveau_bo_unmap(nv_crtc->lut.nvbo);
2306         if (nv_crtc->lut.nvbo)
2307                 nouveau_bo_unpin(nv_crtc->lut.nvbo);
2308         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
2309
2310         drm_crtc_cleanup(crtc);
2311         kfree(crtc);
2312 }
2313
2314 static const struct drm_crtc_funcs
2315 nv50_head_func = {
2316         .reset = nv50_head_reset,
2317         .gamma_set = nv50_head_gamma_set,
2318         .destroy = nv50_head_destroy,
2319         .set_config = drm_atomic_helper_set_config,
2320         .page_flip = drm_atomic_helper_page_flip,
2321         .set_property = drm_atomic_helper_crtc_set_property,
2322         .atomic_duplicate_state = nv50_head_atomic_duplicate_state,
2323         .atomic_destroy_state = nv50_head_atomic_destroy_state,
2324 };
2325
2326 static int
2327 nv50_head_create(struct drm_device *dev, int index)
2328 {
2329         struct nouveau_drm *drm = nouveau_drm(dev);
2330         struct nvif_device *device = &drm->client.device;
2331         struct nv50_disp *disp = nv50_disp(dev);
2332         struct nv50_head *head;
2333         struct nv50_base *base;
2334         struct nv50_curs *curs;
2335         struct drm_crtc *crtc;
2336         int ret, i;
2337
2338         head = kzalloc(sizeof(*head), GFP_KERNEL);
2339         if (!head)
2340                 return -ENOMEM;
2341
2342         head->base.index = index;
2343         for (i = 0; i < 256; i++) {
2344                 head->base.lut.r[i] = i << 8;
2345                 head->base.lut.g[i] = i << 8;
2346                 head->base.lut.b[i] = i << 8;
2347         }
2348
2349         ret = nv50_base_new(drm, head, &base);
2350         if (ret == 0)
2351                 ret = nv50_curs_new(drm, head, &curs);
2352         if (ret) {
2353                 kfree(head);
2354                 return ret;
2355         }
2356
2357         crtc = &head->base.base;
2358         drm_crtc_init_with_planes(dev, crtc, &base->wndw.plane,
2359                                   &curs->wndw.plane, &nv50_head_func,
2360                                   "head-%d", head->base.index);
2361         drm_crtc_helper_add(crtc, &nv50_head_help);
2362         drm_mode_crtc_set_gamma_size(crtc, 256);
2363
2364         ret = nouveau_bo_new(&drm->client, 8192, 0x100, TTM_PL_FLAG_VRAM,
2365                              0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
2366         if (!ret) {
2367                 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM, true);
2368                 if (!ret) {
2369                         ret = nouveau_bo_map(head->base.lut.nvbo);
2370                         if (ret)
2371                                 nouveau_bo_unpin(head->base.lut.nvbo);
2372                 }
2373                 if (ret)
2374                         nouveau_bo_ref(NULL, &head->base.lut.nvbo);
2375         }
2376
2377         if (ret)
2378                 goto out;
2379
2380         /* allocate overlay resources */
2381         ret = nv50_oimm_create(device, disp->disp, index, &head->oimm);
2382         if (ret)
2383                 goto out;
2384
2385         ret = nv50_ovly_create(device, disp->disp, index, disp->sync->bo.offset,
2386                                &head->ovly);
2387         if (ret)
2388                 goto out;
2389
2390 out:
2391         if (ret)
2392                 nv50_head_destroy(crtc);
2393         return ret;
2394 }
2395
2396 /******************************************************************************
2397  * Output path helpers
2398  *****************************************************************************/
2399 static int
2400 nv50_outp_atomic_check_view(struct drm_encoder *encoder,
2401                             struct drm_crtc_state *crtc_state,
2402                             struct drm_connector_state *conn_state,
2403                             struct drm_display_mode *native_mode)
2404 {
2405         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
2406         struct drm_display_mode *mode = &crtc_state->mode;
2407         struct drm_connector *connector = conn_state->connector;
2408         struct nouveau_conn_atom *asyc = nouveau_conn_atom(conn_state);
2409         struct nouveau_drm *drm = nouveau_drm(encoder->dev);
2410
2411         NV_ATOMIC(drm, "%s atomic_check\n", encoder->name);
2412         asyc->scaler.full = false;
2413         if (!native_mode)
2414                 return 0;
2415
2416         if (asyc->scaler.mode == DRM_MODE_SCALE_NONE) {
2417                 switch (connector->connector_type) {
2418                 case DRM_MODE_CONNECTOR_LVDS:
2419                 case DRM_MODE_CONNECTOR_eDP:
2420                         /* Force use of scaler for non-EDID modes. */
2421                         if (adjusted_mode->type & DRM_MODE_TYPE_DRIVER)
2422                                 break;
2423                         mode = native_mode;
2424                         asyc->scaler.full = true;
2425                         break;
2426                 default:
2427                         break;
2428                 }
2429         } else {
2430                 mode = native_mode;
2431         }
2432
2433         if (!drm_mode_equal(adjusted_mode, mode)) {
2434                 drm_mode_copy(adjusted_mode, mode);
2435                 crtc_state->mode_changed = true;
2436         }
2437
2438         return 0;
2439 }
2440
2441 static int
2442 nv50_outp_atomic_check(struct drm_encoder *encoder,
2443                        struct drm_crtc_state *crtc_state,
2444                        struct drm_connector_state *conn_state)
2445 {
2446         struct nouveau_connector *nv_connector =
2447                 nouveau_connector(conn_state->connector);
2448         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2449                                            nv_connector->native_mode);
2450 }
2451
2452 /******************************************************************************
2453  * DAC
2454  *****************************************************************************/
2455 static void
2456 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
2457 {
2458         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2459         struct nv50_disp *disp = nv50_disp(encoder->dev);
2460         struct {
2461                 struct nv50_disp_mthd_v1 base;
2462                 struct nv50_disp_dac_pwr_v0 pwr;
2463         } args = {
2464                 .base.version = 1,
2465                 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
2466                 .base.hasht  = nv_encoder->dcb->hasht,
2467                 .base.hashm  = nv_encoder->dcb->hashm,
2468                 .pwr.state = 1,
2469                 .pwr.data  = 1,
2470                 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
2471                               mode != DRM_MODE_DPMS_OFF),
2472                 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
2473                               mode != DRM_MODE_DPMS_OFF),
2474         };
2475
2476         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2477 }
2478
2479 static void
2480 nv50_dac_disable(struct drm_encoder *encoder)
2481 {
2482         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2483         struct nv50_mast *mast = nv50_mast(encoder->dev);
2484         const int or = nv_encoder->or;
2485         u32 *push;
2486
2487         if (nv_encoder->crtc) {
2488                 push = evo_wait(mast, 4);
2489                 if (push) {
2490                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2491                                 evo_mthd(push, 0x0400 + (or * 0x080), 1);
2492                                 evo_data(push, 0x00000000);
2493                         } else {
2494                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
2495                                 evo_data(push, 0x00000000);
2496                         }
2497                         evo_kick(push, mast);
2498                 }
2499         }
2500
2501         nv_encoder->crtc = NULL;
2502 }
2503
2504 static void
2505 nv50_dac_enable(struct drm_encoder *encoder)
2506 {
2507         struct nv50_mast *mast = nv50_mast(encoder->dev);
2508         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2509         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2510         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
2511         u32 *push;
2512
2513         push = evo_wait(mast, 8);
2514         if (push) {
2515                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2516                         u32 syncs = 0x00000000;
2517
2518                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2519                                 syncs |= 0x00000001;
2520                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2521                                 syncs |= 0x00000002;
2522
2523                         evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
2524                         evo_data(push, 1 << nv_crtc->index);
2525                         evo_data(push, syncs);
2526                 } else {
2527                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
2528                         u32 syncs = 0x00000001;
2529
2530                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2531                                 syncs |= 0x00000008;
2532                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2533                                 syncs |= 0x00000010;
2534
2535                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2536                                 magic |= 0x00000001;
2537
2538                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
2539                         evo_data(push, syncs);
2540                         evo_data(push, magic);
2541                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
2542                         evo_data(push, 1 << nv_crtc->index);
2543                 }
2544
2545                 evo_kick(push, mast);
2546         }
2547
2548         nv_encoder->crtc = encoder->crtc;
2549 }
2550
2551 static enum drm_connector_status
2552 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2553 {
2554         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2555         struct nv50_disp *disp = nv50_disp(encoder->dev);
2556         struct {
2557                 struct nv50_disp_mthd_v1 base;
2558                 struct nv50_disp_dac_load_v0 load;
2559         } args = {
2560                 .base.version = 1,
2561                 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
2562                 .base.hasht  = nv_encoder->dcb->hasht,
2563                 .base.hashm  = nv_encoder->dcb->hashm,
2564         };
2565         int ret;
2566
2567         args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
2568         if (args.load.data == 0)
2569                 args.load.data = 340;
2570
2571         ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
2572         if (ret || !args.load.load)
2573                 return connector_status_disconnected;
2574
2575         return connector_status_connected;
2576 }
2577
2578 static const struct drm_encoder_helper_funcs
2579 nv50_dac_help = {
2580         .dpms = nv50_dac_dpms,
2581         .atomic_check = nv50_outp_atomic_check,
2582         .enable = nv50_dac_enable,
2583         .disable = nv50_dac_disable,
2584         .detect = nv50_dac_detect
2585 };
2586
2587 static void
2588 nv50_dac_destroy(struct drm_encoder *encoder)
2589 {
2590         drm_encoder_cleanup(encoder);
2591         kfree(encoder);
2592 }
2593
2594 static const struct drm_encoder_funcs
2595 nv50_dac_func = {
2596         .destroy = nv50_dac_destroy,
2597 };
2598
2599 static int
2600 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
2601 {
2602         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2603         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
2604         struct nvkm_i2c_bus *bus;
2605         struct nouveau_encoder *nv_encoder;
2606         struct drm_encoder *encoder;
2607         int type = DRM_MODE_ENCODER_DAC;
2608
2609         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2610         if (!nv_encoder)
2611                 return -ENOMEM;
2612         nv_encoder->dcb = dcbe;
2613         nv_encoder->or = ffs(dcbe->or) - 1;
2614
2615         bus = nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
2616         if (bus)
2617                 nv_encoder->i2c = &bus->i2c;
2618
2619         encoder = to_drm_encoder(nv_encoder);
2620         encoder->possible_crtcs = dcbe->heads;
2621         encoder->possible_clones = 0;
2622         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type,
2623                          "dac-%04x-%04x", dcbe->hasht, dcbe->hashm);
2624         drm_encoder_helper_add(encoder, &nv50_dac_help);
2625
2626         drm_mode_connector_attach_encoder(connector, encoder);
2627         return 0;
2628 }
2629
2630 /******************************************************************************
2631  * Audio
2632  *****************************************************************************/
2633 static void
2634 nv50_audio_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2635 {
2636         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2637         struct nv50_disp *disp = nv50_disp(encoder->dev);
2638         struct {
2639                 struct nv50_disp_mthd_v1 base;
2640                 struct nv50_disp_sor_hda_eld_v0 eld;
2641         } args = {
2642                 .base.version = 1,
2643                 .base.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2644                 .base.hasht   = nv_encoder->dcb->hasht,
2645                 .base.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
2646                                 (0x0100 << nv_crtc->index),
2647         };
2648
2649         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2650 }
2651
2652 static void
2653 nv50_audio_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2654 {
2655         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2656         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2657         struct nouveau_connector *nv_connector;
2658         struct nv50_disp *disp = nv50_disp(encoder->dev);
2659         struct __packed {
2660                 struct {
2661                         struct nv50_disp_mthd_v1 mthd;
2662                         struct nv50_disp_sor_hda_eld_v0 eld;
2663                 } base;
2664                 u8 data[sizeof(nv_connector->base.eld)];
2665         } args = {
2666                 .base.mthd.version = 1,
2667                 .base.mthd.method  = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
2668                 .base.mthd.hasht   = nv_encoder->dcb->hasht,
2669                 .base.mthd.hashm   = (0xf0ff & nv_encoder->dcb->hashm) |
2670                                      (0x0100 << nv_crtc->index),
2671         };
2672
2673         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2674         if (!drm_detect_monitor_audio(nv_connector->edid))
2675                 return;
2676
2677         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
2678         memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
2679
2680         nvif_mthd(disp->disp, 0, &args,
2681                   sizeof(args.base) + drm_eld_size(args.data));
2682 }
2683
2684 /******************************************************************************
2685  * HDMI
2686  *****************************************************************************/
2687 static void
2688 nv50_hdmi_disable(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
2689 {
2690         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2691         struct nv50_disp *disp = nv50_disp(encoder->dev);
2692         struct {
2693                 struct nv50_disp_mthd_v1 base;
2694                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2695         } args = {
2696                 .base.version = 1,
2697                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2698                 .base.hasht  = nv_encoder->dcb->hasht,
2699                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
2700                                (0x0100 << nv_crtc->index),
2701         };
2702
2703         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2704 }
2705
2706 static void
2707 nv50_hdmi_enable(struct drm_encoder *encoder, struct drm_display_mode *mode)
2708 {
2709         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2710         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2711         struct nv50_disp *disp = nv50_disp(encoder->dev);
2712         struct {
2713                 struct nv50_disp_mthd_v1 base;
2714                 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
2715         } args = {
2716                 .base.version = 1,
2717                 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
2718                 .base.hasht  = nv_encoder->dcb->hasht,
2719                 .base.hashm  = (0xf0ff & nv_encoder->dcb->hashm) |
2720                                (0x0100 << nv_crtc->index),
2721                 .pwr.state = 1,
2722                 .pwr.rekey = 56, /* binary driver, and tegra, constant */
2723         };
2724         struct nouveau_connector *nv_connector;
2725         u32 max_ac_packet;
2726
2727         nv_connector = nouveau_encoder_connector_get(nv_encoder);
2728         if (!drm_detect_hdmi_monitor(nv_connector->edid))
2729                 return;
2730
2731         max_ac_packet  = mode->htotal - mode->hdisplay;
2732         max_ac_packet -= args.pwr.rekey;
2733         max_ac_packet -= 18; /* constant from tegra */
2734         args.pwr.max_ac_packet = max_ac_packet / 32;
2735
2736         nvif_mthd(disp->disp, 0, &args, sizeof(args));
2737         nv50_audio_enable(encoder, mode);
2738 }
2739
2740 /******************************************************************************
2741  * MST
2742  *****************************************************************************/
2743 #define nv50_mstm(p) container_of((p), struct nv50_mstm, mgr)
2744 #define nv50_mstc(p) container_of((p), struct nv50_mstc, connector)
2745 #define nv50_msto(p) container_of((p), struct nv50_msto, encoder)
2746
2747 struct nv50_mstm {
2748         struct nouveau_encoder *outp;
2749
2750         struct drm_dp_mst_topology_mgr mgr;
2751         struct nv50_msto *msto[4];
2752
2753         bool modified;
2754 };
2755
2756 struct nv50_mstc {
2757         struct nv50_mstm *mstm;
2758         struct drm_dp_mst_port *port;
2759         struct drm_connector connector;
2760
2761         struct drm_display_mode *native;
2762         struct edid *edid;
2763
2764         int pbn;
2765 };
2766
2767 struct nv50_msto {
2768         struct drm_encoder encoder;
2769
2770         struct nv50_head *head;
2771         struct nv50_mstc *mstc;
2772         bool disabled;
2773 };
2774
2775 static struct drm_dp_payload *
2776 nv50_msto_payload(struct nv50_msto *msto)
2777 {
2778         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2779         struct nv50_mstc *mstc = msto->mstc;
2780         struct nv50_mstm *mstm = mstc->mstm;
2781         int vcpi = mstc->port->vcpi.vcpi, i;
2782
2783         NV_ATOMIC(drm, "%s: vcpi %d\n", msto->encoder.name, vcpi);
2784         for (i = 0; i < mstm->mgr.max_payloads; i++) {
2785                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2786                 NV_ATOMIC(drm, "%s: %d: vcpi %d start 0x%02x slots 0x%02x\n",
2787                           mstm->outp->base.base.name, i, payload->vcpi,
2788                           payload->start_slot, payload->num_slots);
2789         }
2790
2791         for (i = 0; i < mstm->mgr.max_payloads; i++) {
2792                 struct drm_dp_payload *payload = &mstm->mgr.payloads[i];
2793                 if (payload->vcpi == vcpi)
2794                         return payload;
2795         }
2796
2797         return NULL;
2798 }
2799
2800 static void
2801 nv50_msto_cleanup(struct nv50_msto *msto)
2802 {
2803         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2804         struct nv50_mstc *mstc = msto->mstc;
2805         struct nv50_mstm *mstm = mstc->mstm;
2806
2807         NV_ATOMIC(drm, "%s: msto cleanup\n", msto->encoder.name);
2808         if (mstc->port && mstc->port->vcpi.vcpi > 0 && !nv50_msto_payload(msto))
2809                 drm_dp_mst_deallocate_vcpi(&mstm->mgr, mstc->port);
2810         if (msto->disabled) {
2811                 msto->mstc = NULL;
2812                 msto->head = NULL;
2813                 msto->disabled = false;
2814         }
2815 }
2816
2817 static void
2818 nv50_msto_prepare(struct nv50_msto *msto)
2819 {
2820         struct nouveau_drm *drm = nouveau_drm(msto->encoder.dev);
2821         struct nv50_mstc *mstc = msto->mstc;
2822         struct nv50_mstm *mstm = mstc->mstm;
2823         struct {
2824                 struct nv50_disp_mthd_v1 base;
2825                 struct nv50_disp_sor_dp_mst_vcpi_v0 vcpi;
2826         } args = {
2827                 .base.version = 1,
2828                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI,
2829                 .base.hasht  = mstm->outp->dcb->hasht,
2830                 .base.hashm  = (0xf0ff & mstm->outp->dcb->hashm) |
2831                                (0x0100 << msto->head->base.index),
2832         };
2833
2834         NV_ATOMIC(drm, "%s: msto prepare\n", msto->encoder.name);
2835         if (mstc->port && mstc->port->vcpi.vcpi > 0) {
2836                 struct drm_dp_payload *payload = nv50_msto_payload(msto);
2837                 if (payload) {
2838                         args.vcpi.start_slot = payload->start_slot;
2839                         args.vcpi.num_slots = payload->num_slots;
2840                         args.vcpi.pbn = mstc->port->vcpi.pbn;
2841                         args.vcpi.aligned_pbn = mstc->port->vcpi.aligned_pbn;
2842                 }
2843         }
2844
2845         NV_ATOMIC(drm, "%s: %s: %02x %02x %04x %04x\n",
2846                   msto->encoder.name, msto->head->base.base.name,
2847                   args.vcpi.start_slot, args.vcpi.num_slots,
2848                   args.vcpi.pbn, args.vcpi.aligned_pbn);
2849         nvif_mthd(&drm->display->disp, 0, &args, sizeof(args));
2850 }
2851
2852 static int
2853 nv50_msto_atomic_check(struct drm_encoder *encoder,
2854                        struct drm_crtc_state *crtc_state,
2855                        struct drm_connector_state *conn_state)
2856 {
2857         struct nv50_mstc *mstc = nv50_mstc(conn_state->connector);
2858         struct nv50_mstm *mstm = mstc->mstm;
2859         int bpp = conn_state->connector->display_info.bpc * 3;
2860         int slots;
2861
2862         mstc->pbn = drm_dp_calc_pbn_mode(crtc_state->adjusted_mode.clock, bpp);
2863
2864         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
2865         if (slots < 0)
2866                 return slots;
2867
2868         return nv50_outp_atomic_check_view(encoder, crtc_state, conn_state,
2869                                            mstc->native);
2870 }
2871
2872 static void
2873 nv50_msto_enable(struct drm_encoder *encoder)
2874 {
2875         struct nv50_head *head = nv50_head(encoder->crtc);
2876         struct nv50_msto *msto = nv50_msto(encoder);
2877         struct nv50_mstc *mstc = NULL;
2878         struct nv50_mstm *mstm = NULL;
2879         struct drm_connector *connector;
2880         u8 proto, depth;
2881         int slots;
2882         bool r;
2883
2884         drm_for_each_connector(connector, encoder->dev) {
2885                 if (connector->state->best_encoder == &msto->encoder) {
2886                         mstc = nv50_mstc(connector);
2887                         mstm = mstc->mstm;
2888                         break;
2889                 }
2890         }
2891
2892         if (WARN_ON(!mstc))
2893                 return;
2894
2895         slots = drm_dp_find_vcpi_slots(&mstm->mgr, mstc->pbn);
2896         r = drm_dp_mst_allocate_vcpi(&mstm->mgr, mstc->port, mstc->pbn, slots);
2897         WARN_ON(!r);
2898
2899         if (mstm->outp->dcb->sorconf.link & 1)
2900                 proto = 0x8;
2901         else
2902                 proto = 0x9;
2903
2904         switch (mstc->connector.display_info.bpc) {
2905         case  6: depth = 0x2; break;
2906         case  8: depth = 0x5; break;
2907         case 10:
2908         default: depth = 0x6; break;
2909         }
2910
2911         mstm->outp->update(mstm->outp, head->base.index,
2912                            &head->base.base.state->adjusted_mode, proto, depth);
2913
2914         msto->head = head;
2915         msto->mstc = mstc;
2916         mstm->modified = true;
2917 }
2918
2919 static void
2920 nv50_msto_disable(struct drm_encoder *encoder)
2921 {
2922         struct nv50_msto *msto = nv50_msto(encoder);
2923         struct nv50_mstc *mstc = msto->mstc;
2924         struct nv50_mstm *mstm = mstc->mstm;
2925
2926         if (mstc->port)
2927                 drm_dp_mst_reset_vcpi_slots(&mstm->mgr, mstc->port);
2928
2929         mstm->outp->update(mstm->outp, msto->head->base.index, NULL, 0, 0);
2930         mstm->modified = true;
2931         msto->disabled = true;
2932 }
2933
2934 static const struct drm_encoder_helper_funcs
2935 nv50_msto_help = {
2936         .disable = nv50_msto_disable,
2937         .enable = nv50_msto_enable,
2938         .atomic_check = nv50_msto_atomic_check,
2939 };
2940
2941 static void
2942 nv50_msto_destroy(struct drm_encoder *encoder)
2943 {
2944         struct nv50_msto *msto = nv50_msto(encoder);
2945         drm_encoder_cleanup(&msto->encoder);
2946         kfree(msto);
2947 }
2948
2949 static const struct drm_encoder_funcs
2950 nv50_msto = {
2951         .destroy = nv50_msto_destroy,
2952 };
2953
2954 static int
2955 nv50_msto_new(struct drm_device *dev, u32 heads, const char *name, int id,
2956               struct nv50_msto **pmsto)
2957 {
2958         struct nv50_msto *msto;
2959         int ret;
2960
2961         if (!(msto = *pmsto = kzalloc(sizeof(*msto), GFP_KERNEL)))
2962                 return -ENOMEM;
2963
2964         ret = drm_encoder_init(dev, &msto->encoder, &nv50_msto,
2965                                DRM_MODE_ENCODER_DPMST, "%s-mst-%d", name, id);
2966         if (ret) {
2967                 kfree(*pmsto);
2968                 *pmsto = NULL;
2969                 return ret;
2970         }
2971
2972         drm_encoder_helper_add(&msto->encoder, &nv50_msto_help);
2973         msto->encoder.possible_crtcs = heads;
2974         return 0;
2975 }
2976
2977 static struct drm_encoder *
2978 nv50_mstc_atomic_best_encoder(struct drm_connector *connector,
2979                               struct drm_connector_state *connector_state)
2980 {
2981         struct nv50_head *head = nv50_head(connector_state->crtc);
2982         struct nv50_mstc *mstc = nv50_mstc(connector);
2983         if (mstc->port) {
2984                 struct nv50_mstm *mstm = mstc->mstm;
2985                 return &mstm->msto[head->base.index]->encoder;
2986         }
2987         return NULL;
2988 }
2989
2990 static struct drm_encoder *
2991 nv50_mstc_best_encoder(struct drm_connector *connector)
2992 {
2993         struct nv50_mstc *mstc = nv50_mstc(connector);
2994         if (mstc->port) {
2995                 struct nv50_mstm *mstm = mstc->mstm;
2996                 return &mstm->msto[0]->encoder;
2997         }
2998         return NULL;
2999 }
3000
3001 static enum drm_mode_status
3002 nv50_mstc_mode_valid(struct drm_connector *connector,
3003                      struct drm_display_mode *mode)
3004 {
3005         return MODE_OK;
3006 }
3007
3008 static int
3009 nv50_mstc_get_modes(struct drm_connector *connector)
3010 {
3011         struct nv50_mstc *mstc = nv50_mstc(connector);
3012         int ret = 0;
3013
3014         mstc->edid = drm_dp_mst_get_edid(&mstc->connector, mstc->port->mgr, mstc->port);
3015         drm_mode_connector_update_edid_property(&mstc->connector, mstc->edid);
3016         if (mstc->edid) {
3017                 ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
3018                 drm_edid_to_eld(&mstc->connector, mstc->edid);
3019         }
3020
3021         if (!mstc->connector.display_info.bpc)
3022                 mstc->connector.display_info.bpc = 8;
3023
3024         if (mstc->native)
3025                 drm_mode_destroy(mstc->connector.dev, mstc->native);
3026         mstc->native = nouveau_conn_native_mode(&mstc->connector);
3027         return ret;
3028 }
3029
3030 static const struct drm_connector_helper_funcs
3031 nv50_mstc_help = {
3032         .get_modes = nv50_mstc_get_modes,
3033         .mode_valid = nv50_mstc_mode_valid,
3034         .best_encoder = nv50_mstc_best_encoder,
3035         .atomic_best_encoder = nv50_mstc_atomic_best_encoder,
3036 };
3037
3038 static enum drm_connector_status
3039 nv50_mstc_detect(struct drm_connector *connector, bool force)
3040 {
3041         struct nv50_mstc *mstc = nv50_mstc(connector);
3042         if (!mstc->port)
3043                 return connector_status_disconnected;
3044         return drm_dp_mst_detect_port(connector, mstc->port->mgr, mstc->port);
3045 }
3046
3047 static void
3048 nv50_mstc_destroy(struct drm_connector *connector)
3049 {
3050         struct nv50_mstc *mstc = nv50_mstc(connector);
3051         drm_connector_cleanup(&mstc->connector);
3052         kfree(mstc);
3053 }
3054
3055 static const struct drm_connector_funcs
3056 nv50_mstc = {
3057         .dpms = drm_atomic_helper_connector_dpms,
3058         .reset = nouveau_conn_reset,
3059         .detect = nv50_mstc_detect,
3060         .fill_modes = drm_helper_probe_single_connector_modes,
3061         .set_property = drm_atomic_helper_connector_set_property,
3062         .destroy = nv50_mstc_destroy,
3063         .atomic_duplicate_state = nouveau_conn_atomic_duplicate_state,
3064         .atomic_destroy_state = nouveau_conn_atomic_destroy_state,
3065         .atomic_set_property = nouveau_conn_atomic_set_property,
3066         .atomic_get_property = nouveau_conn_atomic_get_property,
3067 };
3068
3069 static int
3070 nv50_mstc_new(struct nv50_mstm *mstm, struct drm_dp_mst_port *port,
3071               const char *path, struct nv50_mstc **pmstc)
3072 {
3073         struct drm_device *dev = mstm->outp->base.base.dev;
3074         struct nv50_mstc *mstc;
3075         int ret, i;
3076
3077         if (!(mstc = *pmstc = kzalloc(sizeof(*mstc), GFP_KERNEL)))
3078                 return -ENOMEM;
3079         mstc->mstm = mstm;
3080         mstc->port = port;
3081
3082         ret = drm_connector_init(dev, &mstc->connector, &nv50_mstc,
3083                                  DRM_MODE_CONNECTOR_DisplayPort);
3084         if (ret) {
3085                 kfree(*pmstc);
3086                 *pmstc = NULL;
3087                 return ret;
3088         }
3089
3090         drm_connector_helper_add(&mstc->connector, &nv50_mstc_help);
3091
3092         mstc->connector.funcs->reset(&mstc->connector);
3093         nouveau_conn_attach_properties(&mstc->connector);
3094
3095         for (i = 0; i < ARRAY_SIZE(mstm->msto) && mstm->msto; i++)
3096                 drm_mode_connector_attach_encoder(&mstc->connector, &mstm->msto[i]->encoder);
3097
3098         drm_object_attach_property(&mstc->connector.base, dev->mode_config.path_property, 0);
3099         drm_object_attach_property(&mstc->connector.base, dev->mode_config.tile_property, 0);
3100         drm_mode_connector_set_path_property(&mstc->connector, path);
3101         return 0;
3102 }
3103
3104 static void
3105 nv50_mstm_cleanup(struct nv50_mstm *mstm)
3106 {
3107         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3108         struct drm_encoder *encoder;
3109         int ret;
3110
3111         NV_ATOMIC(drm, "%s: mstm cleanup\n", mstm->outp->base.base.name);
3112         ret = drm_dp_check_act_status(&mstm->mgr);
3113
3114         ret = drm_dp_update_payload_part2(&mstm->mgr);
3115
3116         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3117                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3118                         struct nv50_msto *msto = nv50_msto(encoder);
3119                         struct nv50_mstc *mstc = msto->mstc;
3120                         if (mstc && mstc->mstm == mstm)
3121                                 nv50_msto_cleanup(msto);
3122                 }
3123         }
3124
3125         mstm->modified = false;
3126 }
3127
3128 static void
3129 nv50_mstm_prepare(struct nv50_mstm *mstm)
3130 {
3131         struct nouveau_drm *drm = nouveau_drm(mstm->outp->base.base.dev);
3132         struct drm_encoder *encoder;
3133         int ret;
3134
3135         NV_ATOMIC(drm, "%s: mstm prepare\n", mstm->outp->base.base.name);
3136         ret = drm_dp_update_payload_part1(&mstm->mgr);
3137
3138         drm_for_each_encoder(encoder, mstm->outp->base.base.dev) {
3139                 if (encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
3140                         struct nv50_msto *msto = nv50_msto(encoder);
3141                         struct nv50_mstc *mstc = msto->mstc;
3142                         if (mstc && mstc->mstm == mstm)
3143                                 nv50_msto_prepare(msto);
3144                 }
3145         }
3146 }
3147
3148 static void
3149 nv50_mstm_hotplug(struct drm_dp_mst_topology_mgr *mgr)
3150 {
3151         struct nv50_mstm *mstm = nv50_mstm(mgr);
3152         drm_kms_helper_hotplug_event(mstm->outp->base.base.dev);
3153 }
3154
3155 static void
3156 nv50_mstm_destroy_connector(struct drm_dp_mst_topology_mgr *mgr,
3157                             struct drm_connector *connector)
3158 {
3159         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3160         struct nv50_mstc *mstc = nv50_mstc(connector);
3161
3162         drm_connector_unregister(&mstc->connector);
3163
3164         drm_modeset_lock_all(drm->dev);
3165         drm_fb_helper_remove_one_connector(&drm->fbcon->helper, &mstc->connector);
3166         mstc->port = NULL;
3167         drm_modeset_unlock_all(drm->dev);
3168
3169         drm_connector_unreference(&mstc->connector);
3170 }
3171
3172 static void
3173 nv50_mstm_register_connector(struct drm_connector *connector)
3174 {
3175         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3176
3177         drm_modeset_lock_all(drm->dev);
3178         drm_fb_helper_add_one_connector(&drm->fbcon->helper, connector);
3179         drm_modeset_unlock_all(drm->dev);
3180
3181         drm_connector_register(connector);
3182 }
3183
3184 static struct drm_connector *
3185 nv50_mstm_add_connector(struct drm_dp_mst_topology_mgr *mgr,
3186                         struct drm_dp_mst_port *port, const char *path)
3187 {
3188         struct nv50_mstm *mstm = nv50_mstm(mgr);
3189         struct nv50_mstc *mstc;
3190         int ret;
3191
3192         ret = nv50_mstc_new(mstm, port, path, &mstc);
3193         if (ret) {
3194                 if (mstc)
3195                         mstc->connector.funcs->destroy(&mstc->connector);
3196                 return NULL;
3197         }
3198
3199         return &mstc->connector;
3200 }
3201
3202 static const struct drm_dp_mst_topology_cbs
3203 nv50_mstm = {
3204         .add_connector = nv50_mstm_add_connector,
3205         .register_connector = nv50_mstm_register_connector,
3206         .destroy_connector = nv50_mstm_destroy_connector,
3207         .hotplug = nv50_mstm_hotplug,
3208 };
3209
3210 void
3211 nv50_mstm_service(struct nv50_mstm *mstm)
3212 {
3213         struct drm_dp_aux *aux = mstm->mgr.aux;
3214         bool handled = true;
3215         int ret;
3216         u8 esi[8] = {};
3217
3218         while (handled) {
3219                 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT_ESI, esi, 8);
3220                 if (ret != 8) {
3221                         drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3222                         return;
3223                 }
3224
3225                 drm_dp_mst_hpd_irq(&mstm->mgr, esi, &handled);
3226                 if (!handled)
3227                         break;
3228
3229                 drm_dp_dpcd_write(aux, DP_SINK_COUNT_ESI + 1, &esi[1], 3);
3230         }
3231 }
3232
3233 void
3234 nv50_mstm_remove(struct nv50_mstm *mstm)
3235 {
3236         if (mstm)
3237                 drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, false);
3238 }
3239
3240 static int
3241 nv50_mstm_enable(struct nv50_mstm *mstm, u8 dpcd, int state)
3242 {
3243         struct nouveau_encoder *outp = mstm->outp;
3244         struct {
3245                 struct nv50_disp_mthd_v1 base;
3246                 struct nv50_disp_sor_dp_mst_link_v0 mst;
3247         } args = {
3248                 .base.version = 1,
3249                 .base.method = NV50_DISP_MTHD_V1_SOR_DP_MST_LINK,
3250                 .base.hasht = outp->dcb->hasht,
3251                 .base.hashm = outp->dcb->hashm,
3252                 .mst.state = state,
3253         };
3254         struct nouveau_drm *drm = nouveau_drm(outp->base.base.dev);
3255         struct nvif_object *disp = &drm->display->disp;
3256         int ret;
3257
3258         if (dpcd >= 0x12) {
3259                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CTRL, &dpcd);
3260                 if (ret < 0)
3261                         return ret;
3262
3263                 dpcd &= ~DP_MST_EN;
3264                 if (state)
3265                         dpcd |= DP_MST_EN;
3266
3267                 ret = drm_dp_dpcd_writeb(mstm->mgr.aux, DP_MSTM_CTRL, dpcd);
3268                 if (ret < 0)
3269                         return ret;
3270         }
3271
3272         return nvif_mthd(disp, 0, &args, sizeof(args));
3273 }
3274
3275 int
3276 nv50_mstm_detect(struct nv50_mstm *mstm, u8 dpcd[8], int allow)
3277 {
3278         int ret, state = 0;
3279
3280         if (!mstm)
3281                 return 0;
3282
3283         if (dpcd[0] >= 0x12) {
3284                 ret = drm_dp_dpcd_readb(mstm->mgr.aux, DP_MSTM_CAP, &dpcd[1]);
3285                 if (ret < 0)
3286                         return ret;
3287
3288                 if (!(dpcd[1] & DP_MST_CAP))
3289                         dpcd[0] = 0x11;
3290                 else
3291                         state = allow;
3292         }
3293
3294         ret = nv50_mstm_enable(mstm, dpcd[0], state);
3295         if (ret)
3296                 return ret;
3297
3298         ret = drm_dp_mst_topology_mgr_set_mst(&mstm->mgr, state);
3299         if (ret)
3300                 return nv50_mstm_enable(mstm, dpcd[0], 0);
3301
3302         return mstm->mgr.mst_state;
3303 }
3304
3305 static void
3306 nv50_mstm_fini(struct nv50_mstm *mstm)
3307 {
3308         if (mstm && mstm->mgr.mst_state)
3309                 drm_dp_mst_topology_mgr_suspend(&mstm->mgr);
3310 }
3311
3312 static void
3313 nv50_mstm_init(struct nv50_mstm *mstm)
3314 {
3315         if (mstm && mstm->mgr.mst_state)
3316                 drm_dp_mst_topology_mgr_resume(&mstm->mgr);
3317 }
3318
3319 static void
3320 nv50_mstm_del(struct nv50_mstm **pmstm)
3321 {
3322         struct nv50_mstm *mstm = *pmstm;
3323         if (mstm) {
3324                 kfree(*pmstm);
3325                 *pmstm = NULL;
3326         }
3327 }
3328
3329 static int
3330 nv50_mstm_new(struct nouveau_encoder *outp, struct drm_dp_aux *aux, int aux_max,
3331               int conn_base_id, struct nv50_mstm **pmstm)
3332 {
3333         const int max_payloads = hweight8(outp->dcb->heads);
3334         struct drm_device *dev = outp->base.base.dev;
3335         struct nv50_mstm *mstm;
3336         int ret, i;
3337         u8 dpcd;
3338
3339         /* This is a workaround for some monitors not functioning
3340          * correctly in MST mode on initial module load.  I think
3341          * some bad interaction with the VBIOS may be responsible.
3342          *
3343          * A good ol' off and on again seems to work here ;)
3344          */
3345         ret = drm_dp_dpcd_readb(aux, DP_DPCD_REV, &dpcd);
3346         if (ret >= 0 && dpcd >= 0x12)
3347                 drm_dp_dpcd_writeb(aux, DP_MSTM_CTRL, 0);
3348
3349         if (!(mstm = *pmstm = kzalloc(sizeof(*mstm), GFP_KERNEL)))
3350                 return -ENOMEM;
3351         mstm->outp = outp;
3352         mstm->mgr.cbs = &nv50_mstm;
3353
3354         ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
3355                                            max_payloads, conn_base_id);
3356         if (ret)
3357                 return ret;
3358
3359         for (i = 0; i < max_payloads; i++) {
3360                 ret = nv50_msto_new(dev, outp->dcb->heads, outp->base.base.name,
3361                                     i, &mstm->msto[i]);
3362                 if (ret)
3363                         return ret;
3364         }
3365
3366         return 0;
3367 }
3368
3369 /******************************************************************************
3370  * SOR
3371  *****************************************************************************/
3372 static void
3373 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
3374 {
3375         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3376         struct nv50_disp *disp = nv50_disp(encoder->dev);
3377         struct {
3378                 struct nv50_disp_mthd_v1 base;
3379                 struct nv50_disp_sor_pwr_v0 pwr;
3380         } args = {
3381                 .base.version = 1,
3382                 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
3383                 .base.hasht  = nv_encoder->dcb->hasht,
3384                 .base.hashm  = nv_encoder->dcb->hashm,
3385                 .pwr.state = mode == DRM_MODE_DPMS_ON,
3386         };
3387
3388         nvif_mthd(disp->disp, 0, &args, sizeof(args));
3389 }
3390
3391 static void
3392 nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
3393                 struct drm_display_mode *mode, u8 proto, u8 depth)
3394 {
3395         struct nv50_dmac *core = &nv50_mast(nv_encoder->base.base.dev)->base;
3396         u32 *push;
3397
3398         if (!mode) {
3399                 nv_encoder->ctrl &= ~BIT(head);
3400                 if (!(nv_encoder->ctrl & 0x0000000f))
3401                         nv_encoder->ctrl = 0;
3402         } else {
3403                 nv_encoder->ctrl |= proto << 8;
3404                 nv_encoder->ctrl |= BIT(head);
3405         }
3406
3407         if ((push = evo_wait(core, 6))) {
3408                 if (core->base.user.oclass < GF110_DISP_CORE_CHANNEL_DMA) {
3409                         if (mode) {
3410                                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3411                                         nv_encoder->ctrl |= 0x00001000;
3412                                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3413                                         nv_encoder->ctrl |= 0x00002000;
3414                                 nv_encoder->ctrl |= depth << 16;
3415                         }
3416                         evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
3417                 } else {
3418                         if (mode) {
3419                                 u32 magic = 0x31ec6000 | (head << 25);
3420                                 u32 syncs = 0x00000001;
3421                                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3422                                         syncs |= 0x00000008;
3423                                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3424                                         syncs |= 0x00000010;
3425                                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
3426                                         magic |= 0x00000001;
3427
3428                                 evo_mthd(push, 0x0404 + (head * 0x300), 2);
3429                                 evo_data(push, syncs | (depth << 6));
3430                                 evo_data(push, magic);
3431                         }
3432                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
3433                 }
3434                 evo_data(push, nv_encoder->ctrl);
3435                 evo_kick(push, core);
3436         }
3437 }
3438
3439 static void
3440 nv50_sor_disable(struct drm_encoder *encoder)
3441 {
3442         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3443         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
3444
3445         nv_encoder->crtc = NULL;
3446
3447         if (nv_crtc) {
3448                 struct nvkm_i2c_aux *aux = nv_encoder->aux;
3449                 u8 pwr;
3450
3451                 if (aux) {
3452                         int ret = nvkm_rdaux(aux, DP_SET_POWER, &pwr, 1);
3453                         if (ret == 0) {
3454                                 pwr &= ~DP_SET_POWER_MASK;
3455                                 pwr |=  DP_SET_POWER_D3;
3456                                 nvkm_wraux(aux, DP_SET_POWER, &pwr, 1);
3457                         }
3458                 }
3459
3460                 nv_encoder->update(nv_encoder, nv_crtc->index, NULL, 0, 0);
3461                 nv50_audio_disable(encoder, nv_crtc);
3462                 nv50_hdmi_disable(&nv_encoder->base.base, nv_crtc);
3463         }
3464 }
3465
3466 static void
3467 nv50_sor_enable(struct drm_encoder *encoder)
3468 {
3469         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3470         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3471         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3472         struct {
3473                 struct nv50_disp_mthd_v1 base;
3474                 struct nv50_disp_sor_lvds_script_v0 lvds;
3475         } lvds = {
3476                 .base.version = 1,
3477                 .base.method  = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
3478                 .base.hasht   = nv_encoder->dcb->hasht,
3479                 .base.hashm   = nv_encoder->dcb->hashm,
3480         };
3481         struct nv50_disp *disp = nv50_disp(encoder->dev);
3482         struct drm_device *dev = encoder->dev;
3483         struct nouveau_drm *drm = nouveau_drm(dev);
3484         struct nouveau_connector *nv_connector;
3485         struct nvbios *bios = &drm->vbios;
3486         u8 proto = 0xf;
3487         u8 depth = 0x0;
3488
3489         nv_connector = nouveau_encoder_connector_get(nv_encoder);
3490         nv_encoder->crtc = encoder->crtc;
3491
3492         switch (nv_encoder->dcb->type) {
3493         case DCB_OUTPUT_TMDS:
3494                 if (nv_encoder->dcb->sorconf.link & 1) {
3495                         proto = 0x1;
3496                         /* Only enable dual-link if:
3497                          *  - Need to (i.e. rate > 165MHz)
3498                          *  - DCB says we can
3499                          *  - Not an HDMI monitor, since there's no dual-link
3500                          *    on HDMI.
3501                          */
3502                         if (mode->clock >= 165000 &&
3503                             nv_encoder->dcb->duallink_possible &&
3504                             !drm_detect_hdmi_monitor(nv_connector->edid))
3505                                 proto |= 0x4;
3506                 } else {
3507                         proto = 0x2;
3508                 }
3509
3510                 nv50_hdmi_enable(&nv_encoder->base.base, mode);
3511                 break;
3512         case DCB_OUTPUT_LVDS:
3513                 proto = 0x0;
3514
3515                 if (bios->fp_no_ddc) {
3516                         if (bios->fp.dual_link)
3517                                 lvds.lvds.script |= 0x0100;
3518                         if (bios->fp.if_is_24bit)
3519                                 lvds.lvds.script |= 0x0200;
3520                 } else {
3521                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
3522                                 if (((u8 *)nv_connector->edid)[121] == 2)
3523                                         lvds.lvds.script |= 0x0100;
3524                         } else
3525                         if (mode->clock >= bios->fp.duallink_transition_clk) {
3526                                 lvds.lvds.script |= 0x0100;
3527                         }
3528
3529                         if (lvds.lvds.script & 0x0100) {
3530                                 if (bios->fp.strapless_is_24bit & 2)
3531                                         lvds.lvds.script |= 0x0200;
3532                         } else {
3533                                 if (bios->fp.strapless_is_24bit & 1)
3534                                         lvds.lvds.script |= 0x0200;
3535                         }
3536
3537                         if (nv_connector->base.display_info.bpc == 8)
3538                                 lvds.lvds.script |= 0x0200;
3539                 }
3540
3541                 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
3542                 break;
3543         case DCB_OUTPUT_DP:
3544                 if (nv_connector->base.display_info.bpc == 6)
3545                         depth = 0x2;
3546                 else
3547                 if (nv_connector->base.display_info.bpc == 8)
3548                         depth = 0x5;
3549                 else
3550                         depth = 0x6;
3551
3552                 if (nv_encoder->dcb->sorconf.link & 1)
3553                         proto = 0x8;
3554                 else
3555                         proto = 0x9;
3556
3557                 nv50_audio_enable(encoder, mode);
3558                 break;
3559         default:
3560                 BUG();
3561                 break;
3562         }
3563
3564         nv_encoder->update(nv_encoder, nv_crtc->index, mode, proto, depth);
3565 }
3566
3567 static const struct drm_encoder_helper_funcs
3568 nv50_sor_help = {
3569         .dpms = nv50_sor_dpms,
3570         .atomic_check = nv50_outp_atomic_check,
3571         .enable = nv50_sor_enable,
3572         .disable = nv50_sor_disable,
3573 };
3574
3575 static void
3576 nv50_sor_destroy(struct drm_encoder *encoder)
3577 {
3578         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3579         nv50_mstm_del(&nv_encoder->dp.mstm);
3580         drm_encoder_cleanup(encoder);
3581         kfree(encoder);
3582 }
3583
3584 static const struct drm_encoder_funcs
3585 nv50_sor_func = {
3586         .destroy = nv50_sor_destroy,
3587 };
3588
3589 static int
3590 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
3591 {
3592         struct nouveau_connector *nv_connector = nouveau_connector(connector);
3593         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3594         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
3595         struct nouveau_encoder *nv_encoder;
3596         struct drm_encoder *encoder;
3597         int type, ret;
3598
3599         switch (dcbe->type) {
3600         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
3601         case DCB_OUTPUT_TMDS:
3602         case DCB_OUTPUT_DP:
3603         default:
3604                 type = DRM_MODE_ENCODER_TMDS;
3605                 break;
3606         }
3607
3608         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3609         if (!nv_encoder)
3610                 return -ENOMEM;
3611         nv_encoder->dcb = dcbe;
3612         nv_encoder->or = ffs(dcbe->or) - 1;
3613         nv_encoder->update = nv50_sor_update;
3614
3615         encoder = to_drm_encoder(nv_encoder);
3616         encoder->possible_crtcs = dcbe->heads;
3617         encoder->possible_clones = 0;
3618         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type,
3619                          "sor-%04x-%04x", dcbe->hasht, dcbe->hashm);
3620         drm_encoder_helper_add(encoder, &nv50_sor_help);
3621
3622         drm_mode_connector_attach_encoder(connector, encoder);
3623
3624         if (dcbe->type == DCB_OUTPUT_DP) {
3625                 struct nvkm_i2c_aux *aux =
3626                         nvkm_i2c_aux_find(i2c, dcbe->i2c_index);
3627                 if (aux) {
3628                         nv_encoder->i2c = &nv_connector->aux.ddc;
3629                         nv_encoder->aux = aux;
3630                 }
3631
3632                 /*TODO: Use DP Info Table to check for support. */
3633                 if (nv50_disp(encoder->dev)->disp->oclass >= GF110_DISP) {
3634                         ret = nv50_mstm_new(nv_encoder, &nv_connector->aux, 16,
3635                                             nv_connector->base.base.id,
3636                                             &nv_encoder->dp.mstm);
3637                         if (ret)
3638                                 return ret;
3639                 }
3640         } else {
3641                 struct nvkm_i2c_bus *bus =
3642                         nvkm_i2c_bus_find(i2c, dcbe->i2c_index);
3643                 if (bus)
3644                         nv_encoder->i2c = &bus->i2c;
3645         }
3646
3647         return 0;
3648 }
3649
3650 /******************************************************************************
3651  * PIOR
3652  *****************************************************************************/
3653 static void
3654 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
3655 {
3656         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3657         struct nv50_disp *disp = nv50_disp(encoder->dev);
3658         struct {
3659                 struct nv50_disp_mthd_v1 base;
3660                 struct nv50_disp_pior_pwr_v0 pwr;
3661         } args = {
3662                 .base.version = 1,
3663                 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
3664                 .base.hasht  = nv_encoder->dcb->hasht,
3665                 .base.hashm  = nv_encoder->dcb->hashm,
3666                 .pwr.state = mode == DRM_MODE_DPMS_ON,
3667                 .pwr.type = nv_encoder->dcb->type,
3668         };
3669
3670         nvif_mthd(disp->disp, 0, &args, sizeof(args));
3671 }
3672
3673 static int
3674 nv50_pior_atomic_check(struct drm_encoder *encoder,
3675                        struct drm_crtc_state *crtc_state,
3676                        struct drm_connector_state *conn_state)
3677 {
3678         int ret = nv50_outp_atomic_check(encoder, crtc_state, conn_state);
3679         if (ret)
3680                 return ret;
3681         crtc_state->adjusted_mode.clock *= 2;
3682         return 0;
3683 }
3684
3685 static void
3686 nv50_pior_disable(struct drm_encoder *encoder)
3687 {
3688         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3689         struct nv50_mast *mast = nv50_mast(encoder->dev);
3690         const int or = nv_encoder->or;
3691         u32 *push;
3692
3693         if (nv_encoder->crtc) {
3694                 push = evo_wait(mast, 4);
3695                 if (push) {
3696                         if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3697                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
3698                                 evo_data(push, 0x00000000);
3699                         }
3700                         evo_kick(push, mast);
3701                 }
3702         }
3703
3704         nv_encoder->crtc = NULL;
3705 }
3706
3707 static void
3708 nv50_pior_enable(struct drm_encoder *encoder)
3709 {
3710         struct nv50_mast *mast = nv50_mast(encoder->dev);
3711         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
3712         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
3713         struct nouveau_connector *nv_connector;
3714         struct drm_display_mode *mode = &nv_crtc->base.state->adjusted_mode;
3715         u8 owner = 1 << nv_crtc->index;
3716         u8 proto, depth;
3717         u32 *push;
3718
3719         nv_connector = nouveau_encoder_connector_get(nv_encoder);
3720         switch (nv_connector->base.display_info.bpc) {
3721         case 10: depth = 0x6; break;
3722         case  8: depth = 0x5; break;
3723         case  6: depth = 0x2; break;
3724         default: depth = 0x0; break;
3725         }
3726
3727         switch (nv_encoder->dcb->type) {
3728         case DCB_OUTPUT_TMDS:
3729         case DCB_OUTPUT_DP:
3730                 proto = 0x0;
3731                 break;
3732         default:
3733                 BUG();
3734                 break;
3735         }
3736
3737         push = evo_wait(mast, 8);
3738         if (push) {
3739                 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
3740                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
3741                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
3742                                 ctrl |= 0x00001000;
3743                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
3744                                 ctrl |= 0x00002000;
3745                         evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
3746                         evo_data(push, ctrl);
3747                 }
3748
3749                 evo_kick(push, mast);
3750         }
3751
3752         nv_encoder->crtc = encoder->crtc;
3753 }
3754
3755 static const struct drm_encoder_helper_funcs
3756 nv50_pior_help = {
3757         .dpms = nv50_pior_dpms,
3758         .atomic_check = nv50_pior_atomic_check,
3759         .enable = nv50_pior_enable,
3760         .disable = nv50_pior_disable,
3761 };
3762
3763 static void
3764 nv50_pior_destroy(struct drm_encoder *encoder)
3765 {
3766         drm_encoder_cleanup(encoder);
3767         kfree(encoder);
3768 }
3769
3770 static const struct drm_encoder_funcs
3771 nv50_pior_func = {
3772         .destroy = nv50_pior_destroy,
3773 };
3774
3775 static int
3776 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
3777 {
3778         struct nouveau_connector *nv_connector = nouveau_connector(connector);
3779         struct nouveau_drm *drm = nouveau_drm(connector->dev);
3780         struct nvkm_i2c *i2c = nvxx_i2c(&drm->client.device);
3781         struct nvkm_i2c_bus *bus = NULL;
3782         struct nvkm_i2c_aux *aux = NULL;
3783         struct i2c_adapter *ddc;
3784         struct nouveau_encoder *nv_encoder;
3785         struct drm_encoder *encoder;
3786         int type;
3787
3788         switch (dcbe->type) {
3789         case DCB_OUTPUT_TMDS:
3790                 bus  = nvkm_i2c_bus_find(i2c, NVKM_I2C_BUS_EXT(dcbe->extdev));
3791                 ddc  = bus ? &bus->i2c : NULL;
3792                 type = DRM_MODE_ENCODER_TMDS;
3793                 break;
3794         case DCB_OUTPUT_DP:
3795                 aux  = nvkm_i2c_aux_find(i2c, NVKM_I2C_AUX_EXT(dcbe->extdev));
3796                 ddc  = aux ? &nv_connector->aux.ddc : NULL;
3797                 type = DRM_MODE_ENCODER_TMDS;
3798                 break;
3799         default:
3800                 return -ENODEV;
3801         }
3802
3803         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
3804         if (!nv_encoder)
3805                 return -ENOMEM;
3806         nv_encoder->dcb = dcbe;
3807         nv_encoder->or = ffs(dcbe->or) - 1;
3808         nv_encoder->i2c = ddc;
3809         nv_encoder->aux = aux;
3810
3811         encoder = to_drm_encoder(nv_encoder);
3812         encoder->possible_crtcs = dcbe->heads;
3813         encoder->possible_clones = 0;
3814         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type,
3815                          "pior-%04x-%04x", dcbe->hasht, dcbe->hashm);
3816         drm_encoder_helper_add(encoder, &nv50_pior_help);
3817
3818         drm_mode_connector_attach_encoder(connector, encoder);
3819         return 0;
3820 }
3821
3822 /******************************************************************************
3823  * Atomic
3824  *****************************************************************************/
3825
3826 static void
3827 nv50_disp_atomic_commit_core(struct nouveau_drm *drm, u32 interlock)
3828 {
3829         struct nv50_disp *disp = nv50_disp(drm->dev);
3830         struct nv50_dmac *core = &disp->mast.base;
3831         struct nv50_mstm *mstm;
3832         struct drm_encoder *encoder;
3833         u32 *push;
3834
3835         NV_ATOMIC(drm, "commit core %08x\n", interlock);
3836
3837         drm_for_each_encoder(encoder, drm->dev) {
3838                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3839                         mstm = nouveau_encoder(encoder)->dp.mstm;
3840                         if (mstm && mstm->modified)
3841                                 nv50_mstm_prepare(mstm);
3842                 }
3843         }
3844
3845         if ((push = evo_wait(core, 5))) {
3846                 evo_mthd(push, 0x0084, 1);
3847                 evo_data(push, 0x80000000);
3848                 evo_mthd(push, 0x0080, 2);
3849                 evo_data(push, interlock);
3850                 evo_data(push, 0x00000000);
3851                 nouveau_bo_wr32(disp->sync, 0, 0x00000000);
3852                 evo_kick(push, core);
3853                 if (nvif_msec(&drm->client.device, 2000ULL,
3854                         if (nouveau_bo_rd32(disp->sync, 0))
3855                                 break;
3856                         usleep_range(1, 2);
3857                 ) < 0)
3858                         NV_ERROR(drm, "EVO timeout\n");
3859         }
3860
3861         drm_for_each_encoder(encoder, drm->dev) {
3862                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
3863                         mstm = nouveau_encoder(encoder)->dp.mstm;
3864                         if (mstm && mstm->modified)
3865                                 nv50_mstm_cleanup(mstm);
3866                 }
3867         }
3868 }
3869
3870 static void
3871 nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
3872 {
3873         struct drm_device *dev = state->dev;
3874         struct drm_crtc_state *crtc_state;
3875         struct drm_crtc *crtc;
3876         struct drm_plane_state *plane_state;
3877         struct drm_plane *plane;
3878         struct nouveau_drm *drm = nouveau_drm(dev);
3879         struct nv50_disp *disp = nv50_disp(dev);
3880         struct nv50_atom *atom = nv50_atom(state);
3881         struct nv50_outp_atom *outp, *outt;
3882         u32 interlock_core = 0;
3883         u32 interlock_chan = 0;
3884         int i;
3885
3886         NV_ATOMIC(drm, "commit %d %d\n", atom->lock_core, atom->flush_disable);
3887         drm_atomic_helper_wait_for_fences(dev, state, false);
3888         drm_atomic_helper_wait_for_dependencies(state);
3889         drm_atomic_helper_update_legacy_modeset_state(dev, state);
3890
3891         if (atom->lock_core)
3892                 mutex_lock(&disp->mutex);
3893
3894         /* Disable head(s). */
3895         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3896                 struct nv50_head_atom *asyh = nv50_head_atom(crtc->state);
3897                 struct nv50_head *head = nv50_head(crtc);
3898
3899                 NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name,
3900                           asyh->clr.mask, asyh->set.mask);
3901
3902                 if (asyh->clr.mask) {
3903                         nv50_head_flush_clr(head, asyh, atom->flush_disable);
3904                         interlock_core |= 1;
3905                 }
3906         }
3907
3908         /* Disable plane(s). */
3909         for_each_plane_in_state(state, plane, plane_state, i) {
3910                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
3911                 struct nv50_wndw *wndw = nv50_wndw(plane);
3912
3913                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", plane->name,
3914                           asyw->clr.mask, asyw->set.mask);
3915                 if (!asyw->clr.mask)
3916                         continue;
3917
3918                 interlock_chan |= nv50_wndw_flush_clr(wndw, interlock_core,
3919                                                       atom->flush_disable,
3920                                                       asyw);
3921         }
3922
3923         /* Disable output path(s). */
3924         list_for_each_entry(outp, &atom->outp, head) {
3925                 const struct drm_encoder_helper_funcs *help;
3926                 struct drm_encoder *encoder;
3927
3928                 encoder = outp->encoder;
3929                 help = encoder->helper_private;
3930
3931                 NV_ATOMIC(drm, "%s: clr %02x (set %02x)\n", encoder->name,
3932                           outp->clr.mask, outp->set.mask);
3933
3934                 if (outp->clr.mask) {
3935                         help->disable(encoder);
3936                         interlock_core |= 1;
3937                         if (outp->flush_disable) {
3938                                 nv50_disp_atomic_commit_core(drm, interlock_chan);
3939                                 interlock_core = 0;
3940                                 interlock_chan = 0;
3941                         }
3942                 }
3943         }
3944
3945         /* Flush disable. */
3946         if (interlock_core) {
3947                 if (atom->flush_disable) {
3948                         nv50_disp_atomic_commit_core(drm, interlock_chan);
3949                         interlock_core = 0;
3950                         interlock_chan = 0;
3951                 }
3952         }
3953
3954         /* Update output path(s). */
3955         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
3956                 const struct drm_encoder_helper_funcs *help;
3957                 struct drm_encoder *encoder;
3958
3959                 encoder = outp->encoder;
3960                 help = encoder->helper_private;
3961
3962                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", encoder->name,
3963                           outp->set.mask, outp->clr.mask);
3964
3965                 if (outp->set.mask) {
3966                         help->enable(encoder);
3967                         interlock_core = 1;
3968                 }
3969
3970                 list_del(&outp->head);
3971                 kfree(outp);
3972         }
3973
3974         /* Update head(s). */
3975         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3976                 struct nv50_head_atom *asyh = nv50_head_atom(crtc->state);
3977                 struct nv50_head *head = nv50_head(crtc);
3978
3979                 NV_ATOMIC(drm, "%s: set %04x (clr %04x)\n", crtc->name,
3980                           asyh->set.mask, asyh->clr.mask);
3981
3982                 if (asyh->set.mask) {
3983                         nv50_head_flush_set(head, asyh);
3984                         interlock_core = 1;
3985                 }
3986         }
3987
3988         for_each_crtc_in_state(state, crtc, crtc_state, i) {
3989                 if (crtc->state->event)
3990                         drm_crtc_vblank_get(crtc);
3991         }
3992
3993         /* Update plane(s). */
3994         for_each_plane_in_state(state, plane, plane_state, i) {
3995                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
3996                 struct nv50_wndw *wndw = nv50_wndw(plane);
3997
3998                 NV_ATOMIC(drm, "%s: set %02x (clr %02x)\n", plane->name,
3999                           asyw->set.mask, asyw->clr.mask);
4000                 if ( !asyw->set.mask &&
4001                     (!asyw->clr.mask || atom->flush_disable))
4002                         continue;
4003
4004                 interlock_chan |= nv50_wndw_flush_set(wndw, interlock_core, asyw);
4005         }
4006
4007         /* Flush update. */
4008         if (interlock_core) {
4009                 if (!interlock_chan && atom->state.legacy_cursor_update) {
4010                         u32 *push = evo_wait(&disp->mast, 2);
4011                         if (push) {
4012                                 evo_mthd(push, 0x0080, 1);
4013                                 evo_data(push, 0x00000000);
4014                                 evo_kick(push, &disp->mast);
4015                         }
4016                 } else {
4017                         nv50_disp_atomic_commit_core(drm, interlock_chan);
4018                 }
4019         }
4020
4021         if (atom->lock_core)
4022                 mutex_unlock(&disp->mutex);
4023
4024         /* Wait for HW to signal completion. */
4025         for_each_plane_in_state(state, plane, plane_state, i) {
4026                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane->state);
4027                 struct nv50_wndw *wndw = nv50_wndw(plane);
4028                 int ret = nv50_wndw_wait_armed(wndw, asyw);
4029                 if (ret)
4030                         NV_ERROR(drm, "%s: timeout\n", plane->name);
4031         }
4032
4033         for_each_crtc_in_state(state, crtc, crtc_state, i) {
4034                 if (crtc->state->event) {
4035                         unsigned long flags;
4036                         /* Get correct count/ts if racing with vblank irq */
4037                         drm_accurate_vblank_count(crtc);
4038                         spin_lock_irqsave(&crtc->dev->event_lock, flags);
4039                         drm_crtc_send_vblank_event(crtc, crtc->state->event);
4040                         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
4041                         crtc->state->event = NULL;
4042                         drm_crtc_vblank_put(crtc);
4043                 }
4044         }
4045
4046         drm_atomic_helper_commit_hw_done(state);
4047         drm_atomic_helper_cleanup_planes(dev, state);
4048         drm_atomic_helper_commit_cleanup_done(state);
4049         drm_atomic_state_put(state);
4050 }
4051
4052 static void
4053 nv50_disp_atomic_commit_work(struct work_struct *work)
4054 {
4055         struct drm_atomic_state *state =
4056                 container_of(work, typeof(*state), commit_work);
4057         nv50_disp_atomic_commit_tail(state);
4058 }
4059
4060 static int
4061 nv50_disp_atomic_commit(struct drm_device *dev,
4062                         struct drm_atomic_state *state, bool nonblock)
4063 {
4064         struct nouveau_drm *drm = nouveau_drm(dev);
4065         struct nv50_disp *disp = nv50_disp(dev);
4066         struct drm_plane_state *plane_state;
4067         struct drm_plane *plane;
4068         struct drm_crtc *crtc;
4069         bool active = false;
4070         int ret, i;
4071
4072         ret = pm_runtime_get_sync(dev->dev);
4073         if (ret < 0 && ret != -EACCES)
4074                 return ret;
4075
4076         ret = drm_atomic_helper_setup_commit(state, nonblock);
4077         if (ret)
4078                 goto done;
4079
4080         INIT_WORK(&state->commit_work, nv50_disp_atomic_commit_work);
4081
4082         ret = drm_atomic_helper_prepare_planes(dev, state);
4083         if (ret)
4084                 goto done;
4085
4086         if (!nonblock) {
4087                 ret = drm_atomic_helper_wait_for_fences(dev, state, true);
4088                 if (ret)
4089                         goto done;
4090         }
4091
4092         for_each_plane_in_state(state, plane, plane_state, i) {
4093                 struct nv50_wndw_atom *asyw = nv50_wndw_atom(plane_state);
4094                 struct nv50_wndw *wndw = nv50_wndw(plane);
4095                 if (asyw->set.image) {
4096                         asyw->ntfy.handle = wndw->dmac->sync.handle;
4097                         asyw->ntfy.offset = wndw->ntfy;
4098                         asyw->ntfy.awaken = false;
4099                         asyw->set.ntfy = true;
4100                         nouveau_bo_wr32(disp->sync, wndw->ntfy / 4, 0x00000000);
4101                         wndw->ntfy ^= 0x10;
4102                 }
4103         }
4104
4105         drm_atomic_helper_swap_state(state, true);
4106         drm_atomic_state_get(state);
4107
4108         if (nonblock)
4109                 queue_work(system_unbound_wq, &state->commit_work);
4110         else
4111                 nv50_disp_atomic_commit_tail(state);
4112
4113         drm_for_each_crtc(crtc, dev) {
4114                 if (crtc->state->enable) {
4115                         if (!drm->have_disp_power_ref) {
4116                                 drm->have_disp_power_ref = true;
4117                                 return ret;
4118                         }
4119                         active = true;
4120                         break;
4121                 }
4122         }
4123
4124         if (!active && drm->have_disp_power_ref) {
4125                 pm_runtime_put_autosuspend(dev->dev);
4126                 drm->have_disp_power_ref = false;
4127         }
4128
4129 done:
4130         pm_runtime_put_autosuspend(dev->dev);
4131         return ret;
4132 }
4133
4134 static struct nv50_outp_atom *
4135 nv50_disp_outp_atomic_add(struct nv50_atom *atom, struct drm_encoder *encoder)
4136 {
4137         struct nv50_outp_atom *outp;
4138
4139         list_for_each_entry(outp, &atom->outp, head) {
4140                 if (outp->encoder == encoder)
4141                         return outp;
4142         }
4143
4144         outp = kzalloc(sizeof(*outp), GFP_KERNEL);
4145         if (!outp)
4146                 return ERR_PTR(-ENOMEM);
4147
4148         list_add(&outp->head, &atom->outp);
4149         outp->encoder = encoder;
4150         return outp;
4151 }
4152
4153 static int
4154 nv50_disp_outp_atomic_check_clr(struct nv50_atom *atom,
4155                                 struct drm_connector *connector)
4156 {
4157         struct drm_encoder *encoder = connector->state->best_encoder;
4158         struct drm_crtc_state *crtc_state;
4159         struct drm_crtc *crtc;
4160         struct nv50_outp_atom *outp;
4161
4162         if (!(crtc = connector->state->crtc))
4163                 return 0;
4164
4165         crtc_state = drm_atomic_get_existing_crtc_state(&atom->state, crtc);
4166         if (crtc->state->active && drm_atomic_crtc_needs_modeset(crtc_state)) {
4167                 outp = nv50_disp_outp_atomic_add(atom, encoder);
4168                 if (IS_ERR(outp))
4169                         return PTR_ERR(outp);
4170
4171                 if (outp->encoder->encoder_type == DRM_MODE_ENCODER_DPMST) {
4172                         outp->flush_disable = true;
4173                         atom->flush_disable = true;
4174                 }
4175                 outp->clr.ctrl = true;
4176                 atom->lock_core = true;
4177         }
4178
4179         return 0;
4180 }
4181
4182 static int
4183 nv50_disp_outp_atomic_check_set(struct nv50_atom *atom,
4184                                 struct drm_connector_state *connector_state)
4185 {
4186         struct drm_encoder *encoder = connector_state->best_encoder;
4187         struct drm_crtc_state *crtc_state;
4188         struct drm_crtc *crtc;
4189         struct nv50_outp_atom *outp;
4190
4191         if (!(crtc = connector_state->crtc))
4192                 return 0;
4193
4194         crtc_state = drm_atomic_get_existing_crtc_state(&atom->state, crtc);
4195         if (crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state)) {
4196                 outp = nv50_disp_outp_atomic_add(atom, encoder);
4197                 if (IS_ERR(outp))
4198                         return PTR_ERR(outp);
4199
4200                 outp->set.ctrl = true;
4201                 atom->lock_core = true;
4202         }
4203
4204         return 0;
4205 }
4206
4207 static int
4208 nv50_disp_atomic_check(struct drm_device *dev, struct drm_atomic_state *state)
4209 {
4210         struct nv50_atom *atom = nv50_atom(state);
4211         struct drm_connector_state *connector_state;
4212         struct drm_connector *connector;
4213         int ret, i;
4214
4215         ret = drm_atomic_helper_check(dev, state);
4216         if (ret)
4217                 return ret;
4218
4219         for_each_connector_in_state(state, connector, connector_state, i) {
4220                 ret = nv50_disp_outp_atomic_check_clr(atom, connector);
4221                 if (ret)
4222                         return ret;
4223
4224                 ret = nv50_disp_outp_atomic_check_set(atom, connector_state);
4225                 if (ret)
4226                         return ret;
4227         }
4228
4229         return 0;
4230 }
4231
4232 static void
4233 nv50_disp_atomic_state_clear(struct drm_atomic_state *state)
4234 {
4235         struct nv50_atom *atom = nv50_atom(state);
4236         struct nv50_outp_atom *outp, *outt;
4237
4238         list_for_each_entry_safe(outp, outt, &atom->outp, head) {
4239                 list_del(&outp->head);
4240                 kfree(outp);
4241         }
4242
4243         drm_atomic_state_default_clear(state);
4244 }
4245
4246 static void
4247 nv50_disp_atomic_state_free(struct drm_atomic_state *state)
4248 {
4249         struct nv50_atom *atom = nv50_atom(state);
4250         drm_atomic_state_default_release(&atom->state);
4251         kfree(atom);
4252 }
4253
4254 static struct drm_atomic_state *
4255 nv50_disp_atomic_state_alloc(struct drm_device *dev)
4256 {
4257         struct nv50_atom *atom;
4258         if (!(atom = kzalloc(sizeof(*atom), GFP_KERNEL)) ||
4259             drm_atomic_state_init(dev, &atom->state) < 0) {
4260                 kfree(atom);
4261                 return NULL;
4262         }
4263         INIT_LIST_HEAD(&atom->outp);
4264         return &atom->state;
4265 }
4266
4267 static const struct drm_mode_config_funcs
4268 nv50_disp_func = {
4269         .fb_create = nouveau_user_framebuffer_create,
4270         .output_poll_changed = nouveau_fbcon_output_poll_changed,
4271         .atomic_check = nv50_disp_atomic_check,
4272         .atomic_commit = nv50_disp_atomic_commit,
4273         .atomic_state_alloc = nv50_disp_atomic_state_alloc,
4274         .atomic_state_clear = nv50_disp_atomic_state_clear,
4275         .atomic_state_free = nv50_disp_atomic_state_free,
4276 };
4277
4278 /******************************************************************************
4279  * Init
4280  *****************************************************************************/
4281
4282 void
4283 nv50_display_fini(struct drm_device *dev)
4284 {
4285         struct nouveau_encoder *nv_encoder;
4286         struct drm_encoder *encoder;
4287         struct drm_plane *plane;
4288
4289         drm_for_each_plane(plane, dev) {
4290                 struct nv50_wndw *wndw = nv50_wndw(plane);
4291                 if (plane->funcs != &nv50_wndw)
4292                         continue;
4293                 nv50_wndw_fini(wndw);
4294         }
4295
4296         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4297                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4298                         nv_encoder = nouveau_encoder(encoder);
4299                         nv50_mstm_fini(nv_encoder->dp.mstm);
4300                 }
4301         }
4302 }
4303
4304 int
4305 nv50_display_init(struct drm_device *dev)
4306 {
4307         struct drm_encoder *encoder;
4308         struct drm_plane *plane;
4309         struct drm_crtc *crtc;
4310         u32 *push;
4311
4312         push = evo_wait(nv50_mast(dev), 32);
4313         if (!push)
4314                 return -EBUSY;
4315
4316         evo_mthd(push, 0x0088, 1);
4317         evo_data(push, nv50_mast(dev)->base.sync.handle);
4318         evo_kick(push, nv50_mast(dev));
4319
4320         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4321                 if (encoder->encoder_type != DRM_MODE_ENCODER_DPMST) {
4322                         const struct drm_encoder_helper_funcs *help;
4323                         struct nouveau_encoder *nv_encoder;
4324
4325                         nv_encoder = nouveau_encoder(encoder);
4326                         help = encoder->helper_private;
4327                         if (help && help->dpms)
4328                                 help->dpms(encoder, DRM_MODE_DPMS_ON);
4329
4330                         nv50_mstm_init(nv_encoder->dp.mstm);
4331                 }
4332         }
4333
4334         drm_for_each_crtc(crtc, dev) {
4335                 nv50_head_lut_load(crtc);
4336         }
4337
4338         drm_for_each_plane(plane, dev) {
4339                 struct nv50_wndw *wndw = nv50_wndw(plane);
4340                 if (plane->funcs != &nv50_wndw)
4341                         continue;
4342                 nv50_wndw_init(wndw);
4343         }
4344
4345         return 0;
4346 }
4347
4348 void
4349 nv50_display_destroy(struct drm_device *dev)
4350 {
4351         struct nv50_disp *disp = nv50_disp(dev);
4352
4353         nv50_dmac_destroy(&disp->mast.base, disp->disp);
4354
4355         nouveau_bo_unmap(disp->sync);
4356         if (disp->sync)
4357                 nouveau_bo_unpin(disp->sync);
4358         nouveau_bo_ref(NULL, &disp->sync);
4359
4360         nouveau_display(dev)->priv = NULL;
4361         kfree(disp);
4362 }
4363
4364 MODULE_PARM_DESC(atomic, "Expose atomic ioctl (default: disabled)");
4365 static int nouveau_atomic = 0;
4366 module_param_named(atomic, nouveau_atomic, int, 0400);
4367
4368 int
4369 nv50_display_create(struct drm_device *dev)
4370 {
4371         struct nvif_device *device = &nouveau_drm(dev)->client.device;
4372         struct nouveau_drm *drm = nouveau_drm(dev);
4373         struct dcb_table *dcb = &drm->vbios.dcb;
4374         struct drm_connector *connector, *tmp;
4375         struct nv50_disp *disp;
4376         struct dcb_output *dcbe;
4377         int crtcs, ret, i;
4378
4379         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
4380         if (!disp)
4381                 return -ENOMEM;
4382
4383         mutex_init(&disp->mutex);
4384
4385         nouveau_display(dev)->priv = disp;
4386         nouveau_display(dev)->dtor = nv50_display_destroy;
4387         nouveau_display(dev)->init = nv50_display_init;
4388         nouveau_display(dev)->fini = nv50_display_fini;
4389         disp->disp = &nouveau_display(dev)->disp;
4390         dev->mode_config.funcs = &nv50_disp_func;
4391         if (nouveau_atomic)
4392                 dev->driver->driver_features |= DRIVER_ATOMIC;
4393
4394         /* small shared memory area we use for notifiers and semaphores */
4395         ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM,
4396                              0, 0x0000, NULL, NULL, &disp->sync);
4397         if (!ret) {
4398                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM, true);
4399                 if (!ret) {
4400                         ret = nouveau_bo_map(disp->sync);
4401                         if (ret)
4402                                 nouveau_bo_unpin(disp->sync);
4403                 }
4404                 if (ret)
4405                         nouveau_bo_ref(NULL, &disp->sync);
4406         }
4407
4408         if (ret)
4409                 goto out;
4410
4411         /* allocate master evo channel */
4412         ret = nv50_core_create(device, disp->disp, disp->sync->bo.offset,
4413                               &disp->mast);
4414         if (ret)
4415                 goto out;
4416
4417         /* create crtc objects to represent the hw heads */
4418         if (disp->disp->oclass >= GF110_DISP)
4419                 crtcs = nvif_rd32(&device->object, 0x022448);
4420         else
4421                 crtcs = 2;
4422
4423         for (i = 0; i < crtcs; i++) {
4424                 ret = nv50_head_create(dev, i);
4425                 if (ret)
4426                         goto out;
4427         }
4428
4429         /* create encoder/connector objects based on VBIOS DCB table */
4430         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
4431                 connector = nouveau_connector_create(dev, dcbe->connector);
4432                 if (IS_ERR(connector))
4433                         continue;
4434
4435                 if (dcbe->location == DCB_LOC_ON_CHIP) {
4436                         switch (dcbe->type) {
4437                         case DCB_OUTPUT_TMDS:
4438                         case DCB_OUTPUT_LVDS:
4439                         case DCB_OUTPUT_DP:
4440                                 ret = nv50_sor_create(connector, dcbe);
4441                                 break;
4442                         case DCB_OUTPUT_ANALOG:
4443                                 ret = nv50_dac_create(connector, dcbe);
4444                                 break;
4445                         default:
4446                                 ret = -ENODEV;
4447                                 break;
4448                         }
4449                 } else {
4450                         ret = nv50_pior_create(connector, dcbe);
4451                 }
4452
4453                 if (ret) {
4454                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
4455                                      dcbe->location, dcbe->type,
4456                                      ffs(dcbe->or) - 1, ret);
4457                         ret = 0;
4458                 }
4459         }
4460
4461         /* cull any connectors we created that don't have an encoder */
4462         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
4463                 if (connector->encoder_ids[0])
4464                         continue;
4465
4466                 NV_WARN(drm, "%s has no encoders, removing\n",
4467                         connector->name);
4468                 connector->funcs->destroy(connector);
4469         }
4470
4471 out:
4472         if (ret)
4473                 nv50_display_destroy(dev);
4474         return ret;
4475 }