2 * Copyright 2012 Red Hat Inc.
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27 #include <subdev/timer.h>
30 gf119_sor_dp_audio(struct nvkm_ior *sor, int head, bool enable)
32 struct nvkm_device *device = sor->disp->engine.subdev.device;
33 const u32 hoff = 0x800 * head;
34 const u32 data = 0x80000000 | (0x00000001 * enable);
35 const u32 mask = 0x8000000d;
36 nvkm_mask(device, 0x616618 + hoff, mask, data);
37 nvkm_msec(device, 2000,
38 if (!(nvkm_rd32(device, 0x616618 + hoff) & 0x80000000))
44 gf119_sor_dp_vcpi(struct nvkm_output_dp *outp, int head, u8 slot,
45 u8 slot_nr, u16 pbn, u16 aligned)
47 struct nvkm_device *device = outp->base.disp->engine.subdev.device;
48 const u32 hoff = head * 0x800;
50 nvkm_mask(device, 0x616588 + hoff, 0x00003f3f, (slot_nr << 8) | slot);
51 nvkm_mask(device, 0x61658c + hoff, 0xffffffff, (aligned << 16) | pbn);
55 gf119_sor_dp_drive(struct nvkm_ior *sor, int ln, int pc, int dc, int pe, int pu)
57 struct nvkm_device *device = sor->disp->engine.subdev.device;
58 const u32 loff = nv50_sor_link(sor);
59 const u32 shift = sor->func->dp.lanes[ln] * 8;
62 data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
63 data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
64 data[2] = nvkm_rd32(device, 0x61c130 + loff);
65 if ((data[2] & 0x0000ff00) < (pu << 8) || ln == 0)
66 data[2] = (data[2] & ~0x0000ff00) | (pu << 8);
67 nvkm_wr32(device, 0x61c118 + loff, data[0] | (dc << shift));
68 nvkm_wr32(device, 0x61c120 + loff, data[1] | (pe << shift));
69 nvkm_wr32(device, 0x61c130 + loff, data[2]);
70 data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift);
71 nvkm_wr32(device, 0x61c13c + loff, data[3] | (pc << shift));
75 gf119_sor_dp_pattern(struct nvkm_ior *sor, int pattern)
77 struct nvkm_device *device = sor->disp->engine.subdev.device;
78 const u32 soff = nv50_ior_base(sor);
79 nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, 0x01010101 * pattern);
83 gf119_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
85 struct nvkm_device *device = sor->disp->engine.subdev.device;
86 const u32 soff = nv50_ior_base(sor);
87 const u32 loff = nv50_sor_link(sor);
88 u32 dpctrl = 0x00000000;
89 u32 clksor = 0x00000000;
91 clksor |= sor->dp.bw << 18;
92 dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
98 nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
99 nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
103 static const struct nvkm_output_dp_func
104 gf119_sor_dp_func = {
105 .vcpi = gf119_sor_dp_vcpi,
109 gf119_sor_dp_new(struct nvkm_disp *disp, int index,
110 struct dcb_output *dcbE, struct nvkm_output **poutp)
112 return nvkm_output_dp_new_(&gf119_sor_dp_func, disp, index, dcbE, poutp);
116 gf119_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state)
118 struct nvkm_device *device = sor->disp->engine.subdev.device;
119 const u32 coff = (state == &sor->asy) * 0x20000 + sor->id * 0x20;
120 u32 ctrl = nvkm_rd32(device, 0x640200 + coff);
122 state->proto_evo = (ctrl & 0x00000f00) >> 8;
123 switch (state->proto_evo) {
124 case 0: state->proto = LVDS; state->link = 1; break;
125 case 1: state->proto = TMDS; state->link = 1; break;
126 case 2: state->proto = TMDS; state->link = 2; break;
127 case 5: state->proto = TMDS; state->link = 3; break;
128 case 8: state->proto = DP; state->link = 1; break;
129 case 9: state->proto = DP; state->link = 2; break;
131 state->proto = UNKNOWN;
135 state->head = ctrl & 0x0000000f;
138 static const struct nvkm_ior_func
140 .state = gf119_sor_state,
141 .power = nv50_sor_power,
143 .ctrl = gf119_hdmi_ctrl,
146 .lanes = { 2, 1, 0, 3 },
147 .links = gf119_sor_dp_links,
148 .power = g94_sor_dp_power,
149 .pattern = gf119_sor_dp_pattern,
150 .audio = gf119_sor_dp_audio,
153 .hpd = gf119_hda_hpd,
154 .eld = gf119_hda_eld,
159 gf119_sor_new(struct nvkm_disp *disp, int id)
161 return nvkm_ior_new_(&gf119_sor, disp, SOR, id);