drivers/i2c/busses/i2c-designware-core.c

   1 /*
   2  * Synopsys DesignWare I2C adapter driver (master only).
   3  *
   4  * Based on the TI DAVINCI I2C adapter driver.
   5  *
   6  * Copyright (C) 2006 Texas Instruments.
   7  * Copyright (C) 2007 MontaVista Software Inc.
   8  * Copyright (C) 2009 Provigent Ltd.
   9  *
  10  * ----------------------------------------------------------------------------
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  * ----------------------------------------------------------------------------
  22  *
  23  */
  24 #include <linux/delay.h>
  25 #include <linux/export.h>
  26 #include <linux/errno.h>
  27 #include <linux/err.h>
  28 #include <linux/i2c.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/module.h>
  32 #include <linux/pm_runtime.h>
  33
  34 #include "i2c-designware-core.h"
  35 /*
  36  * Registers offset
  37  */
  38 #define DW_IC_CON               0x0
  39 #define DW_IC_TAR               0x4
  40 #define DW_IC_DATA_CMD          0x10
  41 #define DW_IC_SS_SCL_HCNT       0x14
  42 #define DW_IC_SS_SCL_LCNT       0x18
  43 #define DW_IC_FS_SCL_HCNT       0x1c
  44 #define DW_IC_FS_SCL_LCNT       0x20
  45 #define DW_IC_HS_SCL_HCNT       0x24
  46 #define DW_IC_HS_SCL_LCNT       0x28
  47 #define DW_IC_INTR_STAT         0x2c
  48 #define DW_IC_INTR_MASK         0x30
  49 #define DW_IC_RAW_INTR_STAT     0x34
  50 #define DW_IC_RX_TL             0x38
  51 #define DW_IC_TX_TL             0x3c
  52 #define DW_IC_CLR_INTR          0x40
  53 #define DW_IC_CLR_RX_UNDER      0x44
  54 #define DW_IC_CLR_RX_OVER       0x48
  55 #define DW_IC_CLR_TX_OVER       0x4c
  56 #define DW_IC_CLR_RD_REQ        0x50
  57 #define DW_IC_CLR_TX_ABRT       0x54
  58 #define DW_IC_CLR_RX_DONE       0x58
  59 #define DW_IC_CLR_ACTIVITY      0x5c
  60 #define DW_IC_CLR_STOP_DET      0x60
  61 #define DW_IC_CLR_START_DET     0x64
  62 #define DW_IC_CLR_GEN_CALL      0x68
  63 #define DW_IC_ENABLE            0x6c
  64 #define DW_IC_STATUS            0x70
  65 #define DW_IC_TXFLR             0x74
  66 #define DW_IC_RXFLR             0x78
  67 #define DW_IC_SDA_HOLD          0x7c
  68 #define DW_IC_TX_ABRT_SOURCE    0x80
  69 #define DW_IC_ENABLE_STATUS     0x9c
  70 #define DW_IC_COMP_PARAM_1      0xf4
  71 #define DW_IC_COMP_VERSION      0xf8
  72 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
  73 #define DW_IC_COMP_TYPE         0xfc
  74 #define DW_IC_COMP_TYPE_VALUE   0x44570140
  75
  76 #define DW_IC_INTR_RX_UNDER     0x001
  77 #define DW_IC_INTR_RX_OVER      0x002
  78 #define DW_IC_INTR_RX_FULL      0x004
  79 #define DW_IC_INTR_TX_OVER      0x008
  80 #define DW_IC_INTR_TX_EMPTY     0x010
  81 #define DW_IC_INTR_RD_REQ       0x020
  82 #define DW_IC_INTR_TX_ABRT      0x040
  83 #define DW_IC_INTR_RX_DONE      0x080
  84 #define DW_IC_INTR_ACTIVITY     0x100
  85 #define DW_IC_INTR_STOP_DET     0x200
  86 #define DW_IC_INTR_START_DET    0x400
  87 #define DW_IC_INTR_GEN_CALL     0x800
  88
  89 #define DW_IC_INTR_DEFAULT_MASK         (DW_IC_INTR_RX_FULL | \
  90                                          DW_IC_INTR_TX_ABRT | \
  91                                          DW_IC_INTR_STOP_DET)
  92 #define DW_IC_INTR_MASTER_MASK          (DW_IC_INTR_DEFAULT_MASK | \
  93                                          DW_IC_INTR_TX_EMPTY)
  94 #define DW_IC_STATUS_ACTIVITY   0x1
  95
  96 #define DW_IC_SDA_HOLD_RX_SHIFT         16
  97 #define DW_IC_SDA_HOLD_RX_MASK          GENMASK(23, DW_IC_SDA_HOLD_RX_SHIFT)
  98
  99 #define DW_IC_ERR_TX_ABRT       0x1
 100
 101 #define DW_IC_TAR_10BITADDR_MASTER              BIT(12)
 102
 103 #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH      (BIT(2) | BIT(3))
 104 #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK      GENMASK(3, 2)
 105
 106 /*
 107  * status codes
 108  */
 109 #define STATUS_IDLE                     0x0
 110 #define STATUS_WRITE_IN_PROGRESS        0x1
 111 #define STATUS_READ_IN_PROGRESS         0x2
 112
 113 #define TIMEOUT                 20 /* ms */
 114
 115 /*
 116  * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register
 117  *
 118  * Only expected abort codes are listed here,
 119  * refer to the datasheet for the full list.
 120  */
 121 #define ABRT_7B_ADDR_NOACK      0
 122 #define ABRT_10ADDR1_NOACK      1
 123 #define ABRT_10ADDR2_NOACK      2
 124 #define ABRT_TXDATA_NOACK       3
 125 #define ABRT_GCALL_NOACK        4
 126 #define ABRT_GCALL_READ         5
 127 #define ABRT_SBYTE_ACKDET       7
 128 #define ABRT_SBYTE_NORSTRT      9
 129 #define ABRT_10B_RD_NORSTRT     10
 130 #define ABRT_MASTER_DIS         11
 131 #define ARB_LOST                12
 132
 133 #define DW_IC_TX_ABRT_7B_ADDR_NOACK     (1UL << ABRT_7B_ADDR_NOACK)
 134 #define DW_IC_TX_ABRT_10ADDR1_NOACK     (1UL << ABRT_10ADDR1_NOACK)
 135 #define DW_IC_TX_ABRT_10ADDR2_NOACK     (1UL << ABRT_10ADDR2_NOACK)
 136 #define DW_IC_TX_ABRT_TXDATA_NOACK      (1UL << ABRT_TXDATA_NOACK)
 137 #define DW_IC_TX_ABRT_GCALL_NOACK       (1UL << ABRT_GCALL_NOACK)
 138 #define DW_IC_TX_ABRT_GCALL_READ        (1UL << ABRT_GCALL_READ)
 139 #define DW_IC_TX_ABRT_SBYTE_ACKDET      (1UL << ABRT_SBYTE_ACKDET)
 140 #define DW_IC_TX_ABRT_SBYTE_NORSTRT     (1UL << ABRT_SBYTE_NORSTRT)
 141 #define DW_IC_TX_ABRT_10B_RD_NORSTRT    (1UL << ABRT_10B_RD_NORSTRT)
 142 #define DW_IC_TX_ABRT_MASTER_DIS        (1UL << ABRT_MASTER_DIS)
 143 #define DW_IC_TX_ARB_LOST               (1UL << ARB_LOST)
 144
 145 #define DW_IC_TX_ABRT_NOACK             (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
 146                                          DW_IC_TX_ABRT_10ADDR1_NOACK | \
 147                                          DW_IC_TX_ABRT_10ADDR2_NOACK | \
 148                                          DW_IC_TX_ABRT_TXDATA_NOACK | \
 149                                          DW_IC_TX_ABRT_GCALL_NOACK)
 150
 151 static char *abort_sources[] = {
 152         [ABRT_7B_ADDR_NOACK] =
 153                 "slave address not acknowledged (7bit mode)",
 154         [ABRT_10ADDR1_NOACK] =
 155                 "first address byte not acknowledged (10bit mode)",
 156         [ABRT_10ADDR2_NOACK] =
 157                 "second address byte not acknowledged (10bit mode)",
 158         [ABRT_TXDATA_NOACK] =
 159                 "data not acknowledged",
 160         [ABRT_GCALL_NOACK] =
 161                 "no acknowledgement for a general call",
 162         [ABRT_GCALL_READ] =
 163                 "read after general call",
 164         [ABRT_SBYTE_ACKDET] =
 165                 "start byte acknowledged",
 166         [ABRT_SBYTE_NORSTRT] =
 167                 "trying to send start byte when restart is disabled",
 168         [ABRT_10B_RD_NORSTRT] =
 169                 "trying to read when restart is disabled (10bit mode)",
 170         [ABRT_MASTER_DIS] =
 171                 "trying to use disabled adapter",
 172         [ARB_LOST] =
 173                 "lost arbitration",
 174 };
 175
 176 static u32 dw_readl(struct dw_i2c_dev *dev, int offset)
 177 {
 178         u32 value;
 179
 180         if (dev->flags & ACCESS_16BIT)
 181                 value = readw_relaxed(dev->base + offset) |
 182                         (readw_relaxed(dev->base + offset + 2) << 16);
 183         else
 184                 value = readl_relaxed(dev->base + offset);
 185
 186         if (dev->flags & ACCESS_SWAP)
 187                 return swab32(value);
 188         else
 189                 return value;
 190 }
 191
 192 static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset)
 193 {
 194         if (dev->flags & ACCESS_SWAP)
 195                 b = swab32(b);
 196
 197         if (dev->flags & ACCESS_16BIT) {
 198                 writew_relaxed((u16)b, dev->base + offset);
 199                 writew_relaxed((u16)(b >> 16), dev->base + offset + 2);
 200         } else {
 201                 writel_relaxed(b, dev->base + offset);
 202         }
 203 }
 204
 205 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
 206 {
 207         /* Configure Tx/Rx FIFO threshold levels */
 208         dw_writel(dev, dev->tx_fifo_depth / 2, DW_IC_TX_TL);
 209         dw_writel(dev, 0, DW_IC_RX_TL);
 210
 211         /* Configure the I2C master */
 212         dw_writel(dev, dev->master_cfg, DW_IC_CON);
 213 }
 214
 215 static u32
 216 i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset)
 217 {
 218         /*
 219          * DesignWare I2C core doesn't seem to have solid strategy to meet
 220          * the tHD;STA timing spec.  Configuring _HCNT based on tHIGH spec
 221          * will result in violation of the tHD;STA spec.
 222          */
 223         if (cond)
 224                 /*
 225                  * Conditional expression:
 226                  *
 227                  *   IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH
 228                  *
 229                  * This is based on the DW manuals, and represents an ideal
 230                  * configuration.  The resulting I2C bus speed will be
 231                  * faster than any of the others.
 232                  *
 233                  * If your hardware is free from tHD;STA issue, try this one.
 234                  */
 235                 return (ic_clk * tSYMBOL + 500000) / 1000000 - 8 + offset;
 236         else
 237                 /*
 238                  * Conditional expression:
 239                  *
 240                  *   IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
 241                  *
 242                  * This is just experimental rule; the tHD;STA period turned
 243                  * out to be proportinal to (_HCNT + 3).  With this setting,
 244                  * we could meet both tHIGH and tHD;STA timing specs.
 245                  *
 246                  * If unsure, you'd better to take this alternative.
 247                  *
 248                  * The reason why we need to take into account "tf" here,
 249                  * is the same as described in i2c_dw_scl_lcnt().
 250                  */
 251                 return (ic_clk * (tSYMBOL + tf) + 500000) / 1000000
 252                         - 3 + offset;
 253 }
 254
 255 static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset)
 256 {
 257         /*
 258          * Conditional expression:
 259          *
 260          *   IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
 261          *
 262          * DW I2C core starts counting the SCL CNTs for the LOW period
 263          * of the SCL clock (tLOW) as soon as it pulls the SCL line.
 264          * In order to meet the tLOW timing spec, we need to take into
 265          * account the fall time of SCL signal (tf).  Default tf value
 266          * should be 0.3 us, for safety.
 267          */
 268         return ((ic_clk * (tLOW + tf) + 500000) / 1000000) - 1 + offset;
 269 }
 270
 271 static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable)
 272 {
 273         dw_writel(dev, enable, DW_IC_ENABLE);
 274 }
 275
 276 static void __i2c_dw_enable_and_wait(struct dw_i2c_dev *dev, bool enable)
 277 {
 278         int timeout = 100;
 279
 280         do {
 281                 __i2c_dw_enable(dev, enable);
 282                 if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable)
 283                         return;
 284
 285                 /*
 286                  * Wait 10 times the signaling period of the highest I2C
 287                  * transfer supported by the driver (for 400KHz this is
 288                  * 25us) as described in the DesignWare I2C databook.
 289                  */
 290                 usleep_range(25, 250);
 291         } while (timeout--);
 292
 293         dev_warn(dev->dev, "timeout in %sabling adapter\n",
 294                  enable ? "en" : "dis");
 295 }
 296
 297 static unsigned long i2c_dw_clk_rate(struct dw_i2c_dev *dev)
 298 {
 299         /*
 300          * Clock is not necessary if we got LCNT/HCNT values directly from
 301          * the platform code.
 302          */
 303         if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
 304                 return 0;
 305         return dev->get_clk_rate_khz(dev);
 306 }
 307
 308 static int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
 309 {
 310         int ret;
 311
 312         if (!dev->acquire_lock)
 313                 return 0;
 314
 315         ret = dev->acquire_lock(dev);
 316         if (!ret)
 317                 return 0;
 318
 319         dev_err(dev->dev, "couldn't acquire bus ownership\n");
 320
 321         return ret;
 322 }
 323
 324 static void i2c_dw_release_lock(struct dw_i2c_dev *dev)
 325 {
 326         if (dev->release_lock)
 327                 dev->release_lock(dev);
 328 }
 329
 330 /**
 331  * i2c_dw_init() - Initialize the designware I2C master hardware
 332  * @dev: device private data
 333  *
 334  * This functions configures and enables the I2C master.
 335  * This function is called during I2C init function, and in case of timeout at
 336  * run time.
 337  */
 338 int i2c_dw_init(struct dw_i2c_dev *dev)
 339 {
 340         u32 hcnt, lcnt;
 341         u32 reg, comp_param1;
 342         u32 sda_falling_time, scl_falling_time;
 343         int ret;
 344
 345         ret = i2c_dw_acquire_lock(dev);
 346         if (ret)
 347                 return ret;
 348
 349         reg = dw_readl(dev, DW_IC_COMP_TYPE);
 350         if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
 351                 /* Configure register endianess access */
 352                 dev->flags |= ACCESS_SWAP;
 353         } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
 354                 /* Configure register access mode 16bit */
 355                 dev->flags |= ACCESS_16BIT;
 356         } else if (reg != DW_IC_COMP_TYPE_VALUE) {
 357                 dev_err(dev->dev,
 358                         "Unknown Synopsys component type: 0x%08x\n", reg);
 359                 i2c_dw_release_lock(dev);
 360                 return -ENODEV;
 361         }
 362
 363         comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
 364
 365         /* Disable the adapter */
 366         __i2c_dw_enable_and_wait(dev, false);
 367
 368         /* Set standard and fast speed deviders for high/low periods */
 369
 370         sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
 371         scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
 372
 373         /* Set SCL timing parameters for standard-mode */
 374         if (dev->ss_hcnt && dev->ss_lcnt) {
 375                 hcnt = dev->ss_hcnt;
 376                 lcnt = dev->ss_lcnt;
 377         } else {
 378                 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
 379                                         4000,   /* tHD;STA = tHIGH = 4.0 us */
 380                                         sda_falling_time,
 381                                         0,      /* 0: DW default, 1: Ideal */
 382                                         0);     /* No offset */
 383                 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
 384                                         4700,   /* tLOW = 4.7 us */
 385                                         scl_falling_time,
 386                                         0);     /* No offset */
 387         }
 388         dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
 389         dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
 390         dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 391
 392         /* Set SCL timing parameters for fast-mode or fast-mode plus */
 393         if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) {
 394                 hcnt = dev->fp_hcnt;
 395                 lcnt = dev->fp_lcnt;
 396         } else if (dev->fs_hcnt && dev->fs_lcnt) {
 397                 hcnt = dev->fs_hcnt;
 398                 lcnt = dev->fs_lcnt;
 399         } else {
 400                 hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
 401                                         600,    /* tHD;STA = tHIGH = 0.6 us */
 402                                         sda_falling_time,
 403                                         0,      /* 0: DW default, 1: Ideal */
 404                                         0);     /* No offset */
 405                 lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
 406                                         1300,   /* tLOW = 1.3 us */
 407                                         scl_falling_time,
 408                                         0);     /* No offset */
 409         }
 410         dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
 411         dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
 412         dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
 413
 414         if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
 415                 DW_IC_CON_SPEED_HIGH) {
 416                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 417                         != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
 418                         dev_err(dev->dev, "High Speed not supported!\n");
 419                         dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
 420                         dev->master_cfg |= DW_IC_CON_SPEED_FAST;
 421                 } else if (dev->hs_hcnt && dev->hs_lcnt) {
 422                         hcnt = dev->hs_hcnt;
 423                         lcnt = dev->hs_lcnt;
 424                         dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT);
 425                         dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT);
 426                         dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n",
 427                                 hcnt, lcnt);
 428                 }
 429         }
 430
 431         /* Configure SDA Hold Time if required */
 432         reg = dw_readl(dev, DW_IC_COMP_VERSION);
 433         if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
 434                 if (!dev->sda_hold_time) {
 435                         /* Keep previous hold time setting if no one set it */
 436                         dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
 437                 }
 438                 /*
 439                  * Workaround for avoiding TX arbitration lost in case I2C
 440                  * slave pulls SDA down "too quickly" after falling egde of
 441                  * SCL by enabling non-zero SDA RX hold. Specification says it
 442                  * extends incoming SDA low to high transition while SCL is
 443                  * high but it apprears to help also above issue.
 444                  */
 445                 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
 446                         dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
 447                 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
 448         } else {
 449                 dev_warn(dev->dev,
 450                         "Hardware too old to adjust SDA hold time.\n");
 451         }
 452
 453         i2c_dw_configure_fifo_master(dev);
 454         i2c_dw_release_lock(dev);
 455
 456         return 0;
 457 }
 458 EXPORT_SYMBOL_GPL(i2c_dw_init);
 459
 460 /*
 461  * Waiting for bus not busy
 462  */
 463 static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
 464 {
 465         int timeout = TIMEOUT;
 466
 467         while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) {
 468                 if (timeout <= 0) {
 469                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 470                         return -ETIMEDOUT;
 471                 }
 472                 timeout--;
 473                 usleep_range(1000, 1100);
 474         }
 475
 476         return 0;
 477 }
 478
 479 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
 480 {
 481         struct i2c_msg *msgs = dev->msgs;
 482         u32 ic_con, ic_tar = 0;
 483
 484         /* Disable the adapter */
 485         __i2c_dw_enable_and_wait(dev, false);
 486
 487         /* If the slave address is ten bit address, enable 10BITADDR */
 488         ic_con = dw_readl(dev, DW_IC_CON);
 489         if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
 490                 ic_con |= DW_IC_CON_10BITADDR_MASTER;
 491                 /*
 492                  * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
 493                  * mode has to be enabled via bit 12 of IC_TAR register.
 494                  * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
 495                  * detected from registers.
 496                  */
 497                 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
 498         } else {
 499                 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
 500         }
 501
 502         dw_writel(dev, ic_con, DW_IC_CON);
 503
 504         /*
 505          * Set the slave (target) address and enable 10-bit addressing mode
 506          * if applicable.
 507          */
 508         dw_writel(dev, msgs[dev->msg_write_idx].addr | ic_tar, DW_IC_TAR);
 509
 510         /* Enforce disabled interrupts (due to HW issues) */
 511         i2c_dw_disable_int(dev);
 512
 513         /* Enable the adapter */
 514         __i2c_dw_enable(dev, true);
 515
 516         /* Clear and enable interrupts */
 517         dw_readl(dev, DW_IC_CLR_INTR);
 518         dw_writel(dev, DW_IC_INTR_MASTER_MASK, DW_IC_INTR_MASK);
 519 }
 520
 521 /*
 522  * Initiate (and continue) low level master read/write transaction.
 523  * This function is only called from i2c_dw_isr, and pumping i2c_msg
 524  * messages into the tx buffer.  Even if the size of i2c_msg data is
 525  * longer than the size of the tx buffer, it handles everything.
 526  */
 527 static void
 528 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
 529 {
 530         struct i2c_msg *msgs = dev->msgs;
 531         u32 intr_mask;
 532         int tx_limit, rx_limit;
 533         u32 addr = msgs[dev->msg_write_idx].addr;
 534         u32 buf_len = dev->tx_buf_len;
 535         u8 *buf = dev->tx_buf;
 536         bool need_restart = false;
 537
 538         intr_mask = DW_IC_INTR_MASTER_MASK;
 539
 540         for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
 541                 u32 flags = msgs[dev->msg_write_idx].flags;
 542
 543                 /*
 544                  * If target address has changed, we need to
 545                  * reprogram the target address in the I2C
 546                  * adapter when we are done with this transfer.
 547                  */
 548                 if (msgs[dev->msg_write_idx].addr != addr) {
 549                         dev_err(dev->dev,
 550                                 "%s: invalid target address\n", __func__);
 551                         dev->msg_err = -EINVAL;
 552                         break;
 553                 }
 554
 555                 if (msgs[dev->msg_write_idx].len == 0) {
 556                         dev_err(dev->dev,
 557                                 "%s: invalid message length\n", __func__);
 558                         dev->msg_err = -EINVAL;
 559                         break;
 560                 }
 561
 562                 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
 563                         /* new i2c_msg */
 564                         buf = msgs[dev->msg_write_idx].buf;
 565                         buf_len = msgs[dev->msg_write_idx].len;
 566
 567                         /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
 568                          * IC_RESTART_EN are set, we must manually
 569                          * set restart bit between messages.
 570                          */
 571                         if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
 572                                         (dev->msg_write_idx > 0))
 573                                 need_restart = true;
 574                 }
 575
 576                 tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR);
 577                 rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR);
 578
 579                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
 580                         u32 cmd = 0;
 581
 582                         /*
 583                          * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
 584                          * manually set the stop bit. However, it cannot be
 585                          * detected from the registers so we set it always
 586                          * when writing/reading the last byte.
 587                          */
 588
 589                         /*
 590                          * i2c-core always sets the buffer length of
 591                          * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
 592                          * be adjusted when receiving the first byte.
 593                          * Thus we can't stop the transaction here.
 594                          */
 595                         if (dev->msg_write_idx == dev->msgs_num - 1 &&
 596                             buf_len == 1 && !(flags & I2C_M_RECV_LEN))
 597                                 cmd |= BIT(9);
 598
 599                         if (need_restart) {
 600                                 cmd |= BIT(10);
 601                                 need_restart = false;
 602                         }
 603
 604                         if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
 605
 606                                 /* Avoid rx buffer overrun */
 607                                 if (dev->rx_outstanding >= dev->rx_fifo_depth)
 608                                         break;
 609
 610                                 dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD);
 611                                 rx_limit--;
 612                                 dev->rx_outstanding++;
 613                         } else
 614                                 dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD);
 615                         tx_limit--; buf_len--;
 616                 }
 617
 618                 dev->tx_buf = buf;
 619                 dev->tx_buf_len = buf_len;
 620
 621                 /*
 622                  * Because we don't know the buffer length in the
 623                  * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop
 624                  * the transaction here.
 625                  */
 626                 if (buf_len > 0 || flags & I2C_M_RECV_LEN) {
 627                         /* more bytes to be written */
 628                         dev->status |= STATUS_WRITE_IN_PROGRESS;
 629                         break;
 630                 } else
 631                         dev->status &= ~STATUS_WRITE_IN_PROGRESS;
 632         }
 633
 634         /*
 635          * If i2c_msg index search is completed, we don't need TX_EMPTY
 636          * interrupt any more.
 637          */
 638         if (dev->msg_write_idx == dev->msgs_num)
 639                 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
 640
 641         if (dev->msg_err)
 642                 intr_mask = 0;
 643
 644         dw_writel(dev, intr_mask,  DW_IC_INTR_MASK);
 645 }
 646
 647 static u8
 648 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
 649 {
 650         struct i2c_msg *msgs = dev->msgs;
 651         u32 flags = msgs[dev->msg_read_idx].flags;
 652
 653         /*
 654          * Adjust the buffer length and mask the flag
 655          * after receiving the first byte.
 656          */
 657         len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
 658         dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
 659         msgs[dev->msg_read_idx].len = len;
 660         msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
 661
 662         return len;
 663 }
 664
 665 static void
 666 i2c_dw_read(struct dw_i2c_dev *dev)
 667 {
 668         struct i2c_msg *msgs = dev->msgs;
 669         int rx_valid;
 670
 671         for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
 672                 u32 len;
 673                 u8 *buf;
 674
 675                 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
 676                         continue;
 677
 678                 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
 679                         len = msgs[dev->msg_read_idx].len;
 680                         buf = msgs[dev->msg_read_idx].buf;
 681                 } else {
 682                         len = dev->rx_buf_len;
 683                         buf = dev->rx_buf;
 684                 }
 685
 686                 rx_valid = dw_readl(dev, DW_IC_RXFLR);
 687
 688                 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
 689                         u32 flags = msgs[dev->msg_read_idx].flags;
 690
 691                         *buf = dw_readl(dev, DW_IC_DATA_CMD);
 692                         /* Ensure length byte is a valid value */
 693                         if (flags & I2C_M_RECV_LEN &&
 694                                 *buf <= I2C_SMBUS_BLOCK_MAX && *buf > 0) {
 695                                 len = i2c_dw_recv_len(dev, *buf);
 696                         }
 697                         buf++;
 698                         dev->rx_outstanding--;
 699                 }
 700
 701                 if (len > 0) {
 702                         dev->status |= STATUS_READ_IN_PROGRESS;
 703                         dev->rx_buf_len = len;
 704                         dev->rx_buf = buf;
 705                         return;
 706                 } else
 707                         dev->status &= ~STATUS_READ_IN_PROGRESS;
 708         }
 709 }
 710
 711 static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
 712 {
 713         unsigned long abort_source = dev->abort_source;
 714         int i;
 715
 716         if (abort_source & DW_IC_TX_ABRT_NOACK) {
 717                 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
 718                         dev_dbg(dev->dev,
 719                                 "%s: %s\n", __func__, abort_sources[i]);
 720                 return -EREMOTEIO;
 721         }
 722
 723         for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
 724                 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
 725
 726         if (abort_source & DW_IC_TX_ARB_LOST)
 727                 return -EAGAIN;
 728         else if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
 729                 return -EINVAL; /* wrong msgs[] data */
 730         else
 731                 return -EIO;
 732 }
 733
 734 /*
 735  * Prepare controller for a transaction and call i2c_dw_xfer_msg.
 736  */
 737 static int
 738 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 739 {
 740         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 741         int ret;
 742
 743         dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
 744
 745         pm_runtime_get_sync(dev->dev);
 746
 747         reinit_completion(&dev->cmd_complete);
 748         dev->msgs = msgs;
 749         dev->msgs_num = num;
 750         dev->cmd_err = 0;
 751         dev->msg_write_idx = 0;
 752         dev->msg_read_idx = 0;
 753         dev->msg_err = 0;
 754         dev->status = STATUS_IDLE;
 755         dev->abort_source = 0;
 756         dev->rx_outstanding = 0;
 757
 758         ret = i2c_dw_acquire_lock(dev);
 759         if (ret)
 760                 goto done_nolock;
 761
 762         ret = i2c_dw_wait_bus_not_busy(dev);
 763         if (ret < 0)
 764                 goto done;
 765
 766         /* Start the transfers */
 767         i2c_dw_xfer_init(dev);
 768
 769         /* Wait for tx to complete */
 770         if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
 771                 dev_err(dev->dev, "controller timed out\n");
 772                 /* i2c_dw_init implicitly disables the adapter */
 773                 i2c_dw_init(dev);
 774                 ret = -ETIMEDOUT;
 775                 goto done;
 776         }
 777
 778         /*
 779          * We must disable the adapter before returning and signaling the end
 780          * of the current transfer. Otherwise the hardware might continue
 781          * generating interrupts which in turn causes a race condition with
 782          * the following transfer.  Needs some more investigation if the
 783          * additional interrupts are a hardware bug or this driver doesn't
 784          * handle them correctly yet.
 785          */
 786         __i2c_dw_enable(dev, false);
 787
 788         if (dev->msg_err) {
 789                 ret = dev->msg_err;
 790                 goto done;
 791         }
 792
 793         /* No error */
 794         if (likely(!dev->cmd_err && !dev->status)) {
 795                 ret = num;
 796                 goto done;
 797         }
 798
 799         /* We have an error */
 800         if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
 801                 ret = i2c_dw_handle_tx_abort(dev);
 802                 goto done;
 803         }
 804
 805         if (dev->status)
 806                 dev_err(dev->dev,
 807                         "transfer terminated early - interrupt latency too high?\n");
 808
 809         ret = -EIO;
 810
 811 done:
 812         i2c_dw_release_lock(dev);
 813
 814 done_nolock:
 815         pm_runtime_mark_last_busy(dev->dev);
 816         pm_runtime_put_autosuspend(dev->dev);
 817
 818         return ret;
 819 }
 820
 821 static u32 i2c_dw_func(struct i2c_adapter *adap)
 822 {
 823         struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
 824         return dev->functionality;
 825 }
 826
 827 static const struct i2c_algorithm i2c_dw_algo = {
 828         .master_xfer = i2c_dw_xfer,
 829         .functionality = i2c_dw_func,
 830 };
 831
 832 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
 833 {
 834         u32 stat;
 835
 836         /*
 837          * The IC_INTR_STAT register just indicates "enabled" interrupts.
 838          * Ths unmasked raw version of interrupt status bits are available
 839          * in the IC_RAW_INTR_STAT register.
 840          *
 841          * That is,
 842          *   stat = dw_readl(IC_INTR_STAT);
 843          * equals to,
 844          *   stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
 845          *
 846          * The raw version might be useful for debugging purposes.
 847          */
 848         stat = dw_readl(dev, DW_IC_INTR_STAT);
 849
 850         /*
 851          * Do not use the IC_CLR_INTR register to clear interrupts, or
 852          * you'll miss some interrupts, triggered during the period from
 853          * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
 854          *
 855          * Instead, use the separately-prepared IC_CLR_* registers.
 856          */
 857         if (stat & DW_IC_INTR_RX_UNDER)
 858                 dw_readl(dev, DW_IC_CLR_RX_UNDER);
 859         if (stat & DW_IC_INTR_RX_OVER)
 860                 dw_readl(dev, DW_IC_CLR_RX_OVER);
 861         if (stat & DW_IC_INTR_TX_OVER)
 862                 dw_readl(dev, DW_IC_CLR_TX_OVER);
 863         if (stat & DW_IC_INTR_RD_REQ)
 864                 dw_readl(dev, DW_IC_CLR_RD_REQ);
 865         if (stat & DW_IC_INTR_TX_ABRT) {
 866                 /*
 867                  * The IC_TX_ABRT_SOURCE register is cleared whenever
 868                  * the IC_CLR_TX_ABRT is read.  Preserve it beforehand.
 869                  */
 870                 dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE);
 871                 dw_readl(dev, DW_IC_CLR_TX_ABRT);
 872         }
 873         if (stat & DW_IC_INTR_RX_DONE)
 874                 dw_readl(dev, DW_IC_CLR_RX_DONE);
 875         if (stat & DW_IC_INTR_ACTIVITY)
 876                 dw_readl(dev, DW_IC_CLR_ACTIVITY);
 877         if (stat & DW_IC_INTR_STOP_DET)
 878                 dw_readl(dev, DW_IC_CLR_STOP_DET);
 879         if (stat & DW_IC_INTR_START_DET)
 880                 dw_readl(dev, DW_IC_CLR_START_DET);
 881         if (stat & DW_IC_INTR_GEN_CALL)
 882                 dw_readl(dev, DW_IC_CLR_GEN_CALL);
 883
 884         return stat;
 885 }
 886
 887 /*
 888  * Interrupt service routine. This gets called whenever an I2C master interrupt
 889  * occurs.
 890  */
 891 static int i2c_dw_irq_handler_master(struct dw_i2c_dev *dev)
 892 {
 893         u32 stat;
 894
 895         stat = i2c_dw_read_clear_intrbits(dev);
 896         if (stat & DW_IC_INTR_TX_ABRT) {
 897                 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
 898                 dev->status = STATUS_IDLE;
 899
 900                 /*
 901                  * Anytime TX_ABRT is set, the contents of the tx/rx
 902                  * buffers are flushed. Make sure to skip them.
 903                  */
 904                 dw_writel(dev, 0, DW_IC_INTR_MASK);
 905                 goto tx_aborted;
 906         }
 907
 908         if (stat & DW_IC_INTR_RX_FULL)
 909                 i2c_dw_read(dev);
 910
 911         if (stat & DW_IC_INTR_TX_EMPTY)
 912                 i2c_dw_xfer_msg(dev);
 913
 914         /*
 915          * No need to modify or disable the interrupt mask here.
 916          * i2c_dw_xfer_msg() will take care of it according to
 917          * the current transmit status.
 918          */
 919
 920 tx_aborted:
 921         if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err)
 922                 complete(&dev->cmd_complete);
 923         else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
 924                 /* Workaround to trigger pending interrupt */
 925                 stat = dw_readl(dev, DW_IC_INTR_MASK);
 926                 i2c_dw_disable_int(dev);
 927                 dw_writel(dev, stat, DW_IC_INTR_MASK);
 928         }
 929
 930         return 0;
 931 }
 932
 933 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
 934 {
 935         struct dw_i2c_dev *dev = dev_id;
 936         u32 stat, enabled;
 937
 938         enabled = dw_readl(dev, DW_IC_ENABLE);
 939         stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
 940         dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
 941         if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
 942                 return IRQ_NONE;
 943
 944         i2c_dw_irq_handler_master(dev);
 945
 946         return IRQ_HANDLED;
 947 }
 948
 949 void i2c_dw_disable(struct dw_i2c_dev *dev)
 950 {
 951         /* Disable controller */
 952         __i2c_dw_enable_and_wait(dev, false);
 953
 954         /* Disable all interupts */
 955         dw_writel(dev, 0, DW_IC_INTR_MASK);
 956         dw_readl(dev, DW_IC_CLR_INTR);
 957 }
 958 EXPORT_SYMBOL_GPL(i2c_dw_disable);
 959
 960 void i2c_dw_disable_int(struct dw_i2c_dev *dev)
 961 {
 962         dw_writel(dev, 0, DW_IC_INTR_MASK);
 963 }
 964 EXPORT_SYMBOL_GPL(i2c_dw_disable_int);
 965
 966 u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev)
 967 {
 968         return dw_readl(dev, DW_IC_COMP_PARAM_1);
 969 }
 970 EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param);
 971
 972 int i2c_dw_probe(struct dw_i2c_dev *dev)
 973 {
 974         struct i2c_adapter *adap = &dev->adapter;
 975         unsigned long irq_flags;
 976         int ret;
 977
 978         init_completion(&dev->cmd_complete);
 979
 980         ret = i2c_dw_init(dev);
 981         if (ret)
 982                 return ret;
 983
 984         snprintf(adap->name, sizeof(adap->name),
 985                  "Synopsys DesignWare I2C adapter");
 986         adap->retries = 3;
 987         adap->algo = &i2c_dw_algo;
 988         adap->dev.parent = dev->dev;
 989         i2c_set_adapdata(adap, dev);
 990
 991         if (dev->pm_disabled) {
 992                 dev_pm_syscore_device(dev->dev, true);
 993                 irq_flags = IRQF_NO_SUSPEND;
 994         } else {
 995                 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
 996         }
 997
 998         i2c_dw_disable_int(dev);
 999         ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags,
1000                                dev_name(dev->dev), dev);
1001         if (ret) {
1002                 dev_err(dev->dev, "failure requesting irq %i: %d\n",
1003                         dev->irq, ret);
1004                 return ret;
1005         }
1006
1007         /*
1008          * Increment PM usage count during adapter registration in order to
1009          * avoid possible spurious runtime suspend when adapter device is
1010          * registered to the device core and immediate resume in case bus has
1011          * registered I2C slaves that do I2C transfers in their probe.
1012          */
1013         pm_runtime_get_noresume(dev->dev);
1014         ret = i2c_add_numbered_adapter(adap);
1015         if (ret)
1016                 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
1017         pm_runtime_put_noidle(dev->dev);
1018
1019         return ret;
1020 }
1021 EXPORT_SYMBOL_GPL(i2c_dw_probe);
1022
1023 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
1024 MODULE_LICENSE("GPL");