drivers/infiniband/hw/cxgb4/qp.c

   1 /*
   2  * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/module.h>
  34
  35 #include "iw_cxgb4.h"
  36
  37 static int db_delay_usecs = 1;
  38 module_param(db_delay_usecs, int, 0644);
  39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
  40
  41 static int ocqp_support = 1;
  42 module_param(ocqp_support, int, 0644);
  43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
  44
  45 int db_fc_threshold = 1000;
  46 module_param(db_fc_threshold, int, 0644);
  47 MODULE_PARM_DESC(db_fc_threshold,
  48                  "QP count/threshold that triggers"
  49                  " automatic db flow control mode (default = 1000)");
  50
  51 int db_coalescing_threshold;
  52 module_param(db_coalescing_threshold, int, 0644);
  53 MODULE_PARM_DESC(db_coalescing_threshold,
  54                  "QP count/threshold that triggers"
  55                  " disabling db coalescing (default = 0)");
  56
  57 static int max_fr_immd = T4_MAX_FR_IMMD;
  58 module_param(max_fr_immd, int, 0644);
  59 MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
  60
  61 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
  62 {
  63         unsigned long flag;
  64         spin_lock_irqsave(&qhp->lock, flag);
  65         qhp->attr.state = state;
  66         spin_unlock_irqrestore(&qhp->lock, flag);
  67 }
  68
  69 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  70 {
  71         c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
  72 }
  73
  74 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  75 {
  76         dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
  77                           pci_unmap_addr(sq, mapping));
  78 }
  79
  80 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  81 {
  82         if (t4_sq_onchip(sq))
  83                 dealloc_oc_sq(rdev, sq);
  84         else
  85                 dealloc_host_sq(rdev, sq);
  86 }
  87
  88 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  89 {
  90         if (!ocqp_support || !ocqp_supported(&rdev->lldi))
  91                 return -ENOSYS;
  92         sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
  93         if (!sq->dma_addr)
  94                 return -ENOMEM;
  95         sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
  96                         rdev->lldi.vr->ocq.start;
  97         sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
  98                                             rdev->lldi.vr->ocq.start);
  99         sq->flags |= T4_SQ_ONCHIP;
 100         return 0;
 101 }
 102
 103 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
 104 {
 105         sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
 106                                        &(sq->dma_addr), GFP_KERNEL);
 107         if (!sq->queue)
 108                 return -ENOMEM;
 109         sq->phys_addr = virt_to_phys(sq->queue);
 110         pci_unmap_addr_set(sq, mapping, sq->dma_addr);
 111         return 0;
 112 }
 113
 114 static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
 115 {
 116         int ret = -ENOSYS;
 117         if (user)
 118                 ret = alloc_oc_sq(rdev, sq);
 119         if (ret)
 120                 ret = alloc_host_sq(rdev, sq);
 121         return ret;
 122 }
 123
 124 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 125                       struct c4iw_dev_ucontext *uctx)
 126 {
 127         /*
 128          * uP clears EQ contexts when the connection exits rdma mode,
 129          * so no need to post a RESET WR for these EQs.
 130          */
 131         dma_free_coherent(&(rdev->lldi.pdev->dev),
 132                           wq->rq.memsize, wq->rq.queue,
 133                           dma_unmap_addr(&wq->rq, mapping));
 134         dealloc_sq(rdev, &wq->sq);
 135         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 136         kfree(wq->rq.sw_rq);
 137         kfree(wq->sq.sw_sq);
 138         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 139         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 140         return 0;
 141 }
 142
 143 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 144                      struct t4_cq *rcq, struct t4_cq *scq,
 145                      struct c4iw_dev_ucontext *uctx)
 146 {
 147         int user = (uctx != &rdev->uctx);
 148         struct fw_ri_res_wr *res_wr;
 149         struct fw_ri_res *res;
 150         int wr_len;
 151         struct c4iw_wr_wait wr_wait;
 152         struct sk_buff *skb;
 153         int ret = 0;
 154         int eqsize;
 155
 156         wq->sq.qid = c4iw_get_qpid(rdev, uctx);
 157         if (!wq->sq.qid)
 158                 return -ENOMEM;
 159
 160         wq->rq.qid = c4iw_get_qpid(rdev, uctx);
 161         if (!wq->rq.qid) {
 162                 ret = -ENOMEM;
 163                 goto free_sq_qid;
 164         }
 165
 166         if (!user) {
 167                 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
 168                                  GFP_KERNEL);
 169                 if (!wq->sq.sw_sq) {
 170                         ret = -ENOMEM;
 171                         goto free_rq_qid;
 172                 }
 173
 174                 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
 175                                  GFP_KERNEL);
 176                 if (!wq->rq.sw_rq) {
 177                         ret = -ENOMEM;
 178                         goto free_sw_sq;
 179                 }
 180         }
 181
 182         /*
 183          * RQT must be a power of 2.
 184          */
 185         wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
 186         wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
 187         if (!wq->rq.rqt_hwaddr) {
 188                 ret = -ENOMEM;
 189                 goto free_sw_rq;
 190         }
 191
 192         ret = alloc_sq(rdev, &wq->sq, user);
 193         if (ret)
 194                 goto free_hwaddr;
 195         memset(wq->sq.queue, 0, wq->sq.memsize);
 196         dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
 197
 198         wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
 199                                           wq->rq.memsize, &(wq->rq.dma_addr),
 200                                           GFP_KERNEL);
 201         if (!wq->rq.queue) {
 202                 ret = -ENOMEM;
 203                 goto free_sq;
 204         }
 205         PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
 206                 __func__, wq->sq.queue,
 207                 (unsigned long long)virt_to_phys(wq->sq.queue),
 208                 wq->rq.queue,
 209                 (unsigned long long)virt_to_phys(wq->rq.queue));
 210         memset(wq->rq.queue, 0, wq->rq.memsize);
 211         dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
 212
 213         wq->db = rdev->lldi.db_reg;
 214         wq->gts = rdev->lldi.gts_reg;
 215         if (user || is_t5(rdev->lldi.adapter_type)) {
 216                 u32 off;
 217
 218                 off = (wq->sq.qid << rdev->qpshift) & PAGE_MASK;
 219                 if (user) {
 220                         wq->sq.udb = (u64 __iomem *)(rdev->bar2_pa + off);
 221                 } else {
 222                         off += 128 * (wq->sq.qid & rdev->qpmask) + 8;
 223                         wq->sq.udb = (u64 __iomem *)(rdev->bar2_kva + off);
 224                 }
 225                 off = (wq->rq.qid << rdev->qpshift) & PAGE_MASK;
 226                 if (user) {
 227                         wq->rq.udb = (u64 __iomem *)(rdev->bar2_pa + off);
 228                 } else {
 229                         off += 128 * (wq->rq.qid & rdev->qpmask) + 8;
 230                         wq->rq.udb = (u64 __iomem *)(rdev->bar2_kva + off);
 231                 }
 232         }
 233         wq->rdev = rdev;
 234         wq->rq.msn = 1;
 235
 236         /* build fw_ri_res_wr */
 237         wr_len = sizeof *res_wr + 2 * sizeof *res;
 238
 239         skb = alloc_skb(wr_len, GFP_KERNEL);
 240         if (!skb) {
 241                 ret = -ENOMEM;
 242                 goto free_dma;
 243         }
 244         set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
 245
 246         res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
 247         memset(res_wr, 0, wr_len);
 248         res_wr->op_nres = cpu_to_be32(
 249                         FW_WR_OP(FW_RI_RES_WR) |
 250                         V_FW_RI_RES_WR_NRES(2) |
 251                         FW_WR_COMPL(1));
 252         res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
 253         res_wr->cookie = (unsigned long) &wr_wait;
 254         res = res_wr->res;
 255         res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
 256         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 257
 258         /*
 259          * eqsize is the number of 64B entries plus the status page size.
 260          */
 261         eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
 262
 263         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 264                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
 265                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
 266                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
 267                 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
 268                 V_FW_RI_RES_WR_IQID(scq->cqid));
 269         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 270                 V_FW_RI_RES_WR_DCAEN(0) |
 271                 V_FW_RI_RES_WR_DCACPU(0) |
 272                 V_FW_RI_RES_WR_FBMIN(2) |
 273                 V_FW_RI_RES_WR_FBMAX(2) |
 274                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
 275                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
 276                 V_FW_RI_RES_WR_EQSIZE(eqsize));
 277         res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
 278         res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
 279         res++;
 280         res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
 281         res->u.sqrq.op = FW_RI_RES_OP_WRITE;
 282
 283         /*
 284          * eqsize is the number of 64B entries plus the status page size.
 285          */
 286         eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
 287         res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
 288                 V_FW_RI_RES_WR_HOSTFCMODE(0) |  /* no host cidx updates */
 289                 V_FW_RI_RES_WR_CPRIO(0) |       /* don't keep in chip cache */
 290                 V_FW_RI_RES_WR_PCIECHN(0) |     /* set by uP at ri_init time */
 291                 V_FW_RI_RES_WR_IQID(rcq->cqid));
 292         res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
 293                 V_FW_RI_RES_WR_DCAEN(0) |
 294                 V_FW_RI_RES_WR_DCACPU(0) |
 295                 V_FW_RI_RES_WR_FBMIN(2) |
 296                 V_FW_RI_RES_WR_FBMAX(2) |
 297                 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
 298                 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
 299                 V_FW_RI_RES_WR_EQSIZE(eqsize));
 300         res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
 301         res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
 302
 303         c4iw_init_wr_wait(&wr_wait);
 304
 305         ret = c4iw_ofld_send(rdev, skb);
 306         if (ret)
 307                 goto free_dma;
 308         ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
 309         if (ret)
 310                 goto free_dma;
 311
 312         PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%lx rqudb 0x%lx\n",
 313              __func__, wq->sq.qid, wq->rq.qid, wq->db,
 314              (__force unsigned long) wq->sq.udb,
 315              (__force unsigned long) wq->rq.udb);
 316
 317         return 0;
 318 free_dma:
 319         dma_free_coherent(&(rdev->lldi.pdev->dev),
 320                           wq->rq.memsize, wq->rq.queue,
 321                           dma_unmap_addr(&wq->rq, mapping));
 322 free_sq:
 323         dealloc_sq(rdev, &wq->sq);
 324 free_hwaddr:
 325         c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
 326 free_sw_rq:
 327         kfree(wq->rq.sw_rq);
 328 free_sw_sq:
 329         kfree(wq->sq.sw_sq);
 330 free_rq_qid:
 331         c4iw_put_qpid(rdev, wq->rq.qid, uctx);
 332 free_sq_qid:
 333         c4iw_put_qpid(rdev, wq->sq.qid, uctx);
 334         return ret;
 335 }
 336
 337 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
 338                       struct ib_send_wr *wr, int max, u32 *plenp)
 339 {
 340         u8 *dstp, *srcp;
 341         u32 plen = 0;
 342         int i;
 343         int rem, len;
 344
 345         dstp = (u8 *)immdp->data;
 346         for (i = 0; i < wr->num_sge; i++) {
 347                 if ((plen + wr->sg_list[i].length) > max)
 348                         return -EMSGSIZE;
 349                 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
 350                 plen += wr->sg_list[i].length;
 351                 rem = wr->sg_list[i].length;
 352                 while (rem) {
 353                         if (dstp == (u8 *)&sq->queue[sq->size])
 354                                 dstp = (u8 *)sq->queue;
 355                         if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
 356                                 len = rem;
 357                         else
 358                                 len = (u8 *)&sq->queue[sq->size] - dstp;
 359                         memcpy(dstp, srcp, len);
 360                         dstp += len;
 361                         srcp += len;
 362                         rem -= len;
 363                 }
 364         }
 365         len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
 366         if (len)
 367                 memset(dstp, 0, len);
 368         immdp->op = FW_RI_DATA_IMMD;
 369         immdp->r1 = 0;
 370         immdp->r2 = 0;
 371         immdp->immdlen = cpu_to_be32(plen);
 372         *plenp = plen;
 373         return 0;
 374 }
 375
 376 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
 377                       struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
 378                       int num_sge, u32 *plenp)
 379
 380 {
 381         int i;
 382         u32 plen = 0;
 383         __be64 *flitp = (__be64 *)isglp->sge;
 384
 385         for (i = 0; i < num_sge; i++) {
 386                 if ((plen + sg_list[i].length) < plen)
 387                         return -EMSGSIZE;
 388                 plen += sg_list[i].length;
 389                 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
 390                                      sg_list[i].length);
 391                 if (++flitp == queue_end)
 392                         flitp = queue_start;
 393                 *flitp = cpu_to_be64(sg_list[i].addr);
 394                 if (++flitp == queue_end)
 395                         flitp = queue_start;
 396         }
 397         *flitp = (__force __be64)0;
 398         isglp->op = FW_RI_DATA_ISGL;
 399         isglp->r1 = 0;
 400         isglp->nsge = cpu_to_be16(num_sge);
 401         isglp->r2 = 0;
 402         if (plenp)
 403                 *plenp = plen;
 404         return 0;
 405 }
 406
 407 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
 408                            struct ib_send_wr *wr, u8 *len16)
 409 {
 410         u32 plen;
 411         int size;
 412         int ret;
 413
 414         if (wr->num_sge > T4_MAX_SEND_SGE)
 415                 return -EINVAL;
 416         switch (wr->opcode) {
 417         case IB_WR_SEND:
 418                 if (wr->send_flags & IB_SEND_SOLICITED)
 419                         wqe->send.sendop_pkd = cpu_to_be32(
 420                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
 421                 else
 422                         wqe->send.sendop_pkd = cpu_to_be32(
 423                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
 424                 wqe->send.stag_inv = 0;
 425                 break;
 426         case IB_WR_SEND_WITH_INV:
 427                 if (wr->send_flags & IB_SEND_SOLICITED)
 428                         wqe->send.sendop_pkd = cpu_to_be32(
 429                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
 430                 else
 431                         wqe->send.sendop_pkd = cpu_to_be32(
 432                                 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
 433                 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 434                 break;
 435
 436         default:
 437                 return -EINVAL;
 438         }
 439         wqe->send.r3 = 0;
 440         wqe->send.r4 = 0;
 441
 442         plen = 0;
 443         if (wr->num_sge) {
 444                 if (wr->send_flags & IB_SEND_INLINE) {
 445                         ret = build_immd(sq, wqe->send.u.immd_src, wr,
 446                                          T4_MAX_SEND_INLINE, &plen);
 447                         if (ret)
 448                                 return ret;
 449                         size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
 450                                plen;
 451                 } else {
 452                         ret = build_isgl((__be64 *)sq->queue,
 453                                          (__be64 *)&sq->queue[sq->size],
 454                                          wqe->send.u.isgl_src,
 455                                          wr->sg_list, wr->num_sge, &plen);
 456                         if (ret)
 457                                 return ret;
 458                         size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
 459                                wr->num_sge * sizeof(struct fw_ri_sge);
 460                 }
 461         } else {
 462                 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
 463                 wqe->send.u.immd_src[0].r1 = 0;
 464                 wqe->send.u.immd_src[0].r2 = 0;
 465                 wqe->send.u.immd_src[0].immdlen = 0;
 466                 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
 467                 plen = 0;
 468         }
 469         *len16 = DIV_ROUND_UP(size, 16);
 470         wqe->send.plen = cpu_to_be32(plen);
 471         return 0;
 472 }
 473
 474 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
 475                             struct ib_send_wr *wr, u8 *len16)
 476 {
 477         u32 plen;
 478         int size;
 479         int ret;
 480
 481         if (wr->num_sge > T4_MAX_SEND_SGE)
 482                 return -EINVAL;
 483         wqe->write.r2 = 0;
 484         wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
 485         wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
 486         if (wr->num_sge) {
 487                 if (wr->send_flags & IB_SEND_INLINE) {
 488                         ret = build_immd(sq, wqe->write.u.immd_src, wr,
 489                                          T4_MAX_WRITE_INLINE, &plen);
 490                         if (ret)
 491                                 return ret;
 492                         size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
 493                                plen;
 494                 } else {
 495                         ret = build_isgl((__be64 *)sq->queue,
 496                                          (__be64 *)&sq->queue[sq->size],
 497                                          wqe->write.u.isgl_src,
 498                                          wr->sg_list, wr->num_sge, &plen);
 499                         if (ret)
 500                                 return ret;
 501                         size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
 502                                wr->num_sge * sizeof(struct fw_ri_sge);
 503                 }
 504         } else {
 505                 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
 506                 wqe->write.u.immd_src[0].r1 = 0;
 507                 wqe->write.u.immd_src[0].r2 = 0;
 508                 wqe->write.u.immd_src[0].immdlen = 0;
 509                 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
 510                 plen = 0;
 511         }
 512         *len16 = DIV_ROUND_UP(size, 16);
 513         wqe->write.plen = cpu_to_be32(plen);
 514         return 0;
 515 }
 516
 517 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
 518 {
 519         if (wr->num_sge > 1)
 520                 return -EINVAL;
 521         if (wr->num_sge) {
 522                 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
 523                 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
 524                                                         >> 32));
 525                 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
 526                 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
 527                 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
 528                 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
 529                                                          >> 32));
 530                 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
 531         } else {
 532                 wqe->read.stag_src = cpu_to_be32(2);
 533                 wqe->read.to_src_hi = 0;
 534                 wqe->read.to_src_lo = 0;
 535                 wqe->read.stag_sink = cpu_to_be32(2);
 536                 wqe->read.plen = 0;
 537                 wqe->read.to_sink_hi = 0;
 538                 wqe->read.to_sink_lo = 0;
 539         }
 540         wqe->read.r2 = 0;
 541         wqe->read.r5 = 0;
 542         *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
 543         return 0;
 544 }
 545
 546 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
 547                            struct ib_recv_wr *wr, u8 *len16)
 548 {
 549         int ret;
 550
 551         ret = build_isgl((__be64 *)qhp->wq.rq.queue,
 552                          (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
 553                          &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
 554         if (ret)
 555                 return ret;
 556         *len16 = DIV_ROUND_UP(sizeof wqe->recv +
 557                               wr->num_sge * sizeof(struct fw_ri_sge), 16);
 558         return 0;
 559 }
 560
 561 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
 562                          struct ib_send_wr *wr, u8 *len16, u8 t5dev)
 563 {
 564
 565         struct fw_ri_immd *imdp;
 566         __be64 *p;
 567         int i;
 568         int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
 569         int rem;
 570
 571         if (wr->wr.fast_reg.page_list_len >
 572             t4_max_fr_depth(use_dsgl))
 573                 return -EINVAL;
 574
 575         wqe->fr.qpbinde_to_dcacpu = 0;
 576         wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
 577         wqe->fr.addr_type = FW_RI_VA_BASED_TO;
 578         wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
 579         wqe->fr.len_hi = 0;
 580         wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
 581         wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
 582         wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
 583         wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
 584                                         0xffffffff);
 585
 586         if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
 587                 struct c4iw_fr_page_list *c4pl =
 588                         to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
 589                 struct fw_ri_dsgl *sglp;
 590
 591                 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
 592                         wr->wr.fast_reg.page_list->page_list[i] = (__force u64)
 593                                 cpu_to_be64((u64)
 594                                 wr->wr.fast_reg.page_list->page_list[i]);
 595                 }
 596
 597                 sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
 598                 sglp->op = FW_RI_DATA_DSGL;
 599                 sglp->r1 = 0;
 600                 sglp->nsge = cpu_to_be16(1);
 601                 sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
 602                 sglp->len0 = cpu_to_be32(pbllen);
 603
 604                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
 605         } else {
 606                 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
 607                 imdp->op = FW_RI_DATA_IMMD;
 608                 imdp->r1 = 0;
 609                 imdp->r2 = 0;
 610                 imdp->immdlen = cpu_to_be32(pbllen);
 611                 p = (__be64 *)(imdp + 1);
 612                 rem = pbllen;
 613                 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
 614                         *p = cpu_to_be64(
 615                                 (u64)wr->wr.fast_reg.page_list->page_list[i]);
 616                         rem -= sizeof(*p);
 617                         if (++p == (__be64 *)&sq->queue[sq->size])
 618                                 p = (__be64 *)sq->queue;
 619                 }
 620                 BUG_ON(rem < 0);
 621                 while (rem) {
 622                         *p = 0;
 623                         rem -= sizeof(*p);
 624                         if (++p == (__be64 *)&sq->queue[sq->size])
 625                                 p = (__be64 *)sq->queue;
 626                 }
 627                 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
 628                                       + pbllen, 16);
 629         }
 630         return 0;
 631 }
 632
 633 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
 634                           u8 *len16)
 635 {
 636         wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
 637         wqe->inv.r2 = 0;
 638         *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
 639         return 0;
 640 }
 641
 642 void c4iw_qp_add_ref(struct ib_qp *qp)
 643 {
 644         PDBG("%s ib_qp %p\n", __func__, qp);
 645         atomic_inc(&(to_c4iw_qp(qp)->refcnt));
 646 }
 647
 648 void c4iw_qp_rem_ref(struct ib_qp *qp)
 649 {
 650         PDBG("%s ib_qp %p\n", __func__, qp);
 651         if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
 652                 wake_up(&(to_c4iw_qp(qp)->wait));
 653 }
 654
 655 static void add_to_fc_list(struct list_head *head, struct list_head *entry)
 656 {
 657         if (list_empty(entry))
 658                 list_add_tail(entry, head);
 659 }
 660
 661 static int ring_kernel_sq_db(struct c4iw_qp *qhp, u16 inc)
 662 {
 663         unsigned long flags;
 664
 665         spin_lock_irqsave(&qhp->rhp->lock, flags);
 666         spin_lock(&qhp->lock);
 667         if (qhp->rhp->db_state == NORMAL)
 668                 t4_ring_sq_db(&qhp->wq, inc,
 669                               is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL);
 670         else {
 671                 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
 672                 qhp->wq.sq.wq_pidx_inc += inc;
 673         }
 674         spin_unlock(&qhp->lock);
 675         spin_unlock_irqrestore(&qhp->rhp->lock, flags);
 676         return 0;
 677 }
 678
 679 static int ring_kernel_rq_db(struct c4iw_qp *qhp, u16 inc)
 680 {
 681         unsigned long flags;
 682
 683         spin_lock_irqsave(&qhp->rhp->lock, flags);
 684         spin_lock(&qhp->lock);
 685         if (qhp->rhp->db_state == NORMAL)
 686                 t4_ring_rq_db(&qhp->wq, inc,
 687                               is_t5(qhp->rhp->rdev.lldi.adapter_type), NULL);
 688         else {
 689                 add_to_fc_list(&qhp->rhp->db_fc_list, &qhp->db_fc_entry);
 690                 qhp->wq.rq.wq_pidx_inc += inc;
 691         }
 692         spin_unlock(&qhp->lock);
 693         spin_unlock_irqrestore(&qhp->rhp->lock, flags);
 694         return 0;
 695 }
 696
 697 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 698                    struct ib_send_wr **bad_wr)
 699 {
 700         int err = 0;
 701         u8 len16 = 0;
 702         enum fw_wr_opcodes fw_opcode = 0;
 703         enum fw_ri_wr_flags fw_flags;
 704         struct c4iw_qp *qhp;
 705         union t4_wr *wqe = NULL;
 706         u32 num_wrs;
 707         struct t4_swsqe *swsqe;
 708         unsigned long flag;
 709         u16 idx = 0;
 710
 711         qhp = to_c4iw_qp(ibqp);
 712         spin_lock_irqsave(&qhp->lock, flag);
 713         if (t4_wq_in_error(&qhp->wq)) {
 714                 spin_unlock_irqrestore(&qhp->lock, flag);
 715                 return -EINVAL;
 716         }
 717         num_wrs = t4_sq_avail(&qhp->wq);
 718         if (num_wrs == 0) {
 719                 spin_unlock_irqrestore(&qhp->lock, flag);
 720                 return -ENOMEM;
 721         }
 722         while (wr) {
 723                 if (num_wrs == 0) {
 724                         err = -ENOMEM;
 725                         *bad_wr = wr;
 726                         break;
 727                 }
 728                 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
 729                       qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
 730
 731                 fw_flags = 0;
 732                 if (wr->send_flags & IB_SEND_SOLICITED)
 733                         fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
 734                 if (wr->send_flags & IB_SEND_SIGNALED || qhp->sq_sig_all)
 735                         fw_flags |= FW_RI_COMPLETION_FLAG;
 736                 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
 737                 switch (wr->opcode) {
 738                 case IB_WR_SEND_WITH_INV:
 739                 case IB_WR_SEND:
 740                         if (wr->send_flags & IB_SEND_FENCE)
 741                                 fw_flags |= FW_RI_READ_FENCE_FLAG;
 742                         fw_opcode = FW_RI_SEND_WR;
 743                         if (wr->opcode == IB_WR_SEND)
 744                                 swsqe->opcode = FW_RI_SEND;
 745                         else
 746                                 swsqe->opcode = FW_RI_SEND_WITH_INV;
 747                         err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
 748                         break;
 749                 case IB_WR_RDMA_WRITE:
 750                         fw_opcode = FW_RI_RDMA_WRITE_WR;
 751                         swsqe->opcode = FW_RI_RDMA_WRITE;
 752                         err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
 753                         break;
 754                 case IB_WR_RDMA_READ:
 755                 case IB_WR_RDMA_READ_WITH_INV:
 756                         fw_opcode = FW_RI_RDMA_READ_WR;
 757                         swsqe->opcode = FW_RI_READ_REQ;
 758                         if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
 759                                 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
 760                         else
 761                                 fw_flags = 0;
 762                         err = build_rdma_read(wqe, wr, &len16);
 763                         if (err)
 764                                 break;
 765                         swsqe->read_len = wr->sg_list[0].length;
 766                         if (!qhp->wq.sq.oldest_read)
 767                                 qhp->wq.sq.oldest_read = swsqe;
 768                         break;
 769                 case IB_WR_FAST_REG_MR:
 770                         fw_opcode = FW_RI_FR_NSMR_WR;
 771                         swsqe->opcode = FW_RI_FAST_REGISTER;
 772                         err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16,
 773                                             is_t5(
 774                                             qhp->rhp->rdev.lldi.adapter_type) ?
 775                                             1 : 0);
 776                         break;
 777                 case IB_WR_LOCAL_INV:
 778                         if (wr->send_flags & IB_SEND_FENCE)
 779                                 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
 780                         fw_opcode = FW_RI_INV_LSTAG_WR;
 781                         swsqe->opcode = FW_RI_LOCAL_INV;
 782                         err = build_inv_stag(wqe, wr, &len16);
 783                         break;
 784                 default:
 785                         PDBG("%s post of type=%d TBD!\n", __func__,
 786                              wr->opcode);
 787                         err = -EINVAL;
 788                 }
 789                 if (err) {
 790                         *bad_wr = wr;
 791                         break;
 792                 }
 793                 swsqe->idx = qhp->wq.sq.pidx;
 794                 swsqe->complete = 0;
 795                 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED) ||
 796                                   qhp->sq_sig_all;
 797                 swsqe->flushed = 0;
 798                 swsqe->wr_id = wr->wr_id;
 799
 800                 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
 801
 802                 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
 803                      __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
 804                      swsqe->opcode, swsqe->read_len);
 805                 wr = wr->next;
 806                 num_wrs--;
 807                 t4_sq_produce(&qhp->wq, len16);
 808                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 809         }
 810         if (!qhp->rhp->rdev.status_page->db_off) {
 811                 t4_ring_sq_db(&qhp->wq, idx,
 812                               is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe);
 813                 spin_unlock_irqrestore(&qhp->lock, flag);
 814         } else {
 815                 spin_unlock_irqrestore(&qhp->lock, flag);
 816                 ring_kernel_sq_db(qhp, idx);
 817         }
 818         return err;
 819 }
 820
 821 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 822                       struct ib_recv_wr **bad_wr)
 823 {
 824         int err = 0;
 825         struct c4iw_qp *qhp;
 826         union t4_recv_wr *wqe = NULL;
 827         u32 num_wrs;
 828         u8 len16 = 0;
 829         unsigned long flag;
 830         u16 idx = 0;
 831
 832         qhp = to_c4iw_qp(ibqp);
 833         spin_lock_irqsave(&qhp->lock, flag);
 834         if (t4_wq_in_error(&qhp->wq)) {
 835                 spin_unlock_irqrestore(&qhp->lock, flag);
 836                 return -EINVAL;
 837         }
 838         num_wrs = t4_rq_avail(&qhp->wq);
 839         if (num_wrs == 0) {
 840                 spin_unlock_irqrestore(&qhp->lock, flag);
 841                 return -ENOMEM;
 842         }
 843         while (wr) {
 844                 if (wr->num_sge > T4_MAX_RECV_SGE) {
 845                         err = -EINVAL;
 846                         *bad_wr = wr;
 847                         break;
 848                 }
 849                 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
 850                                            qhp->wq.rq.wq_pidx *
 851                                            T4_EQ_ENTRY_SIZE);
 852                 if (num_wrs)
 853                         err = build_rdma_recv(qhp, wqe, wr, &len16);
 854                 else
 855                         err = -ENOMEM;
 856                 if (err) {
 857                         *bad_wr = wr;
 858                         break;
 859                 }
 860
 861                 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
 862
 863                 wqe->recv.opcode = FW_RI_RECV_WR;
 864                 wqe->recv.r1 = 0;
 865                 wqe->recv.wrid = qhp->wq.rq.pidx;
 866                 wqe->recv.r2[0] = 0;
 867                 wqe->recv.r2[1] = 0;
 868                 wqe->recv.r2[2] = 0;
 869                 wqe->recv.len16 = len16;
 870                 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
 871                      (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
 872                 t4_rq_produce(&qhp->wq, len16);
 873                 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
 874                 wr = wr->next;
 875                 num_wrs--;
 876         }
 877         if (!qhp->rhp->rdev.status_page->db_off) {
 878                 t4_ring_rq_db(&qhp->wq, idx,
 879                               is_t5(qhp->rhp->rdev.lldi.adapter_type), wqe);
 880                 spin_unlock_irqrestore(&qhp->lock, flag);
 881         } else {
 882                 spin_unlock_irqrestore(&qhp->lock, flag);
 883                 ring_kernel_rq_db(qhp, idx);
 884         }
 885         return err;
 886 }
 887
 888 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
 889 {
 890         return -ENOSYS;
 891 }
 892
 893 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
 894                                     u8 *ecode)
 895 {
 896         int status;
 897         int tagged;
 898         int opcode;
 899         int rqtype;
 900         int send_inv;
 901
 902         if (!err_cqe) {
 903                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
 904                 *ecode = 0;
 905                 return;
 906         }
 907
 908         status = CQE_STATUS(err_cqe);
 909         opcode = CQE_OPCODE(err_cqe);
 910         rqtype = RQ_TYPE(err_cqe);
 911         send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
 912                    (opcode == FW_RI_SEND_WITH_SE_INV);
 913         tagged = (opcode == FW_RI_RDMA_WRITE) ||
 914                  (rqtype && (opcode == FW_RI_READ_RESP));
 915
 916         switch (status) {
 917         case T4_ERR_STAG:
 918                 if (send_inv) {
 919                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 920                         *ecode = RDMAP_CANT_INV_STAG;
 921                 } else {
 922                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 923                         *ecode = RDMAP_INV_STAG;
 924                 }
 925                 break;
 926         case T4_ERR_PDID:
 927                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 928                 if ((opcode == FW_RI_SEND_WITH_INV) ||
 929                     (opcode == FW_RI_SEND_WITH_SE_INV))
 930                         *ecode = RDMAP_CANT_INV_STAG;
 931                 else
 932                         *ecode = RDMAP_STAG_NOT_ASSOC;
 933                 break;
 934         case T4_ERR_QPID:
 935                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 936                 *ecode = RDMAP_STAG_NOT_ASSOC;
 937                 break;
 938         case T4_ERR_ACCESS:
 939                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 940                 *ecode = RDMAP_ACC_VIOL;
 941                 break;
 942         case T4_ERR_WRAP:
 943                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 944                 *ecode = RDMAP_TO_WRAP;
 945                 break;
 946         case T4_ERR_BOUND:
 947                 if (tagged) {
 948                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 949                         *ecode = DDPT_BASE_BOUNDS;
 950                 } else {
 951                         *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
 952                         *ecode = RDMAP_BASE_BOUNDS;
 953                 }
 954                 break;
 955         case T4_ERR_INVALIDATE_SHARED_MR:
 956         case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
 957                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 958                 *ecode = RDMAP_CANT_INV_STAG;
 959                 break;
 960         case T4_ERR_ECC:
 961         case T4_ERR_ECC_PSTAG:
 962         case T4_ERR_INTERNAL_ERR:
 963                 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
 964                 *ecode = 0;
 965                 break;
 966         case T4_ERR_OUT_OF_RQE:
 967                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 968                 *ecode = DDPU_INV_MSN_NOBUF;
 969                 break;
 970         case T4_ERR_PBL_ADDR_BOUND:
 971                 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 972                 *ecode = DDPT_BASE_BOUNDS;
 973                 break;
 974         case T4_ERR_CRC:
 975                 *layer_type = LAYER_MPA|DDP_LLP;
 976                 *ecode = MPA_CRC_ERR;
 977                 break;
 978         case T4_ERR_MARKER:
 979                 *layer_type = LAYER_MPA|DDP_LLP;
 980                 *ecode = MPA_MARKER_ERR;
 981                 break;
 982         case T4_ERR_PDU_LEN_ERR:
 983                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 984                 *ecode = DDPU_MSG_TOOBIG;
 985                 break;
 986         case T4_ERR_DDP_VERSION:
 987                 if (tagged) {
 988                         *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
 989                         *ecode = DDPT_INV_VERS;
 990                 } else {
 991                         *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
 992                         *ecode = DDPU_INV_VERS;
 993                 }
 994                 break;
 995         case T4_ERR_RDMA_VERSION:
 996                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
 997                 *ecode = RDMAP_INV_VERS;
 998                 break;
 999         case T4_ERR_OPCODE:
1000                 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
1001                 *ecode = RDMAP_INV_OPCODE;
1002                 break;
1003         case T4_ERR_DDP_QUEUE_NUM:
1004                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1005                 *ecode = DDPU_INV_QN;
1006                 break;
1007         case T4_ERR_MSN:
1008         case T4_ERR_MSN_GAP:
1009         case T4_ERR_MSN_RANGE:
1010         case T4_ERR_IRD_OVERFLOW:
1011                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1012                 *ecode = DDPU_INV_MSN_RANGE;
1013                 break;
1014         case T4_ERR_TBIT:
1015                 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
1016                 *ecode = 0;
1017                 break;
1018         case T4_ERR_MO:
1019                 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
1020                 *ecode = DDPU_INV_MO;
1021                 break;
1022         default:
1023                 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
1024                 *ecode = 0;
1025                 break;
1026         }
1027 }
1028
1029 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
1030                            gfp_t gfp)
1031 {
1032         struct fw_ri_wr *wqe;
1033         struct sk_buff *skb;
1034         struct terminate_message *term;
1035
1036         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1037              qhp->ep->hwtid);
1038
1039         skb = alloc_skb(sizeof *wqe, gfp);
1040         if (!skb)
1041                 return;
1042         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1043
1044         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1045         memset(wqe, 0, sizeof *wqe);
1046         wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
1047         wqe->flowid_len16 = cpu_to_be32(
1048                 FW_WR_FLOWID(qhp->ep->hwtid) |
1049                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1050
1051         wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
1052         wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
1053         term = (struct terminate_message *)wqe->u.terminate.termmsg;
1054         if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
1055                 term->layer_etype = qhp->attr.layer_etype;
1056                 term->ecode = qhp->attr.ecode;
1057         } else
1058                 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
1059         c4iw_ofld_send(&qhp->rhp->rdev, skb);
1060 }
1061
1062 /*
1063  * Assumes qhp lock is held.
1064  */
1065 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
1066                        struct c4iw_cq *schp)
1067 {
1068         int count;
1069         int flushed;
1070         unsigned long flag;
1071
1072         PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
1073
1074         /* locking hierarchy: cq lock first, then qp lock. */
1075         spin_lock_irqsave(&rchp->lock, flag);
1076         spin_lock(&qhp->lock);
1077
1078         if (qhp->wq.flushed) {
1079                 spin_unlock(&qhp->lock);
1080                 spin_unlock_irqrestore(&rchp->lock, flag);
1081                 return;
1082         }
1083         qhp->wq.flushed = 1;
1084
1085         c4iw_flush_hw_cq(rchp);
1086         c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
1087         flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
1088         spin_unlock(&qhp->lock);
1089         spin_unlock_irqrestore(&rchp->lock, flag);
1090         if (flushed) {
1091                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1092                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1093                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1094         }
1095
1096         /* locking hierarchy: cq lock first, then qp lock. */
1097         spin_lock_irqsave(&schp->lock, flag);
1098         spin_lock(&qhp->lock);
1099         if (schp != rchp)
1100                 c4iw_flush_hw_cq(schp);
1101         flushed = c4iw_flush_sq(qhp);
1102         spin_unlock(&qhp->lock);
1103         spin_unlock_irqrestore(&schp->lock, flag);
1104         if (flushed) {
1105                 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1106                 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
1107                 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1108         }
1109 }
1110
1111 static void flush_qp(struct c4iw_qp *qhp)
1112 {
1113         struct c4iw_cq *rchp, *schp;
1114         unsigned long flag;
1115
1116         rchp = to_c4iw_cq(qhp->ibqp.recv_cq);
1117         schp = to_c4iw_cq(qhp->ibqp.send_cq);
1118
1119         t4_set_wq_in_error(&qhp->wq);
1120         if (qhp->ibqp.uobject) {
1121                 t4_set_cq_in_error(&rchp->cq);
1122                 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1123                 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1124                 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1125                 if (schp != rchp) {
1126                         t4_set_cq_in_error(&schp->cq);
1127                         spin_lock_irqsave(&schp->comp_handler_lock, flag);
1128                         (*schp->ibcq.comp_handler)(&schp->ibcq,
1129                                         schp->ibcq.cq_context);
1130                         spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1131                 }
1132                 return;
1133         }
1134         __flush_qp(qhp, rchp, schp);
1135 }
1136
1137 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1138                      struct c4iw_ep *ep)
1139 {
1140         struct fw_ri_wr *wqe;
1141         int ret;
1142         struct sk_buff *skb;
1143
1144         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1145              ep->hwtid);
1146
1147         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1148         if (!skb)
1149                 return -ENOMEM;
1150         set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1151
1152         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1153         memset(wqe, 0, sizeof *wqe);
1154         wqe->op_compl = cpu_to_be32(
1155                 FW_WR_OP(FW_RI_INIT_WR) |
1156                 FW_WR_COMPL(1));
1157         wqe->flowid_len16 = cpu_to_be32(
1158                 FW_WR_FLOWID(ep->hwtid) |
1159                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1160         wqe->cookie = (unsigned long) &ep->com.wr_wait;
1161
1162         wqe->u.fini.type = FW_RI_TYPE_FINI;
1163         ret = c4iw_ofld_send(&rhp->rdev, skb);
1164         if (ret)
1165                 goto out;
1166
1167         ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1168                              qhp->wq.sq.qid, __func__);
1169 out:
1170         PDBG("%s ret %d\n", __func__, ret);
1171         return ret;
1172 }
1173
1174 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1175 {
1176         PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1177         memset(&init->u, 0, sizeof init->u);
1178         switch (p2p_type) {
1179         case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1180                 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1181                 init->u.write.stag_sink = cpu_to_be32(1);
1182                 init->u.write.to_sink = cpu_to_be64(1);
1183                 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1184                 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1185                                                    sizeof(struct fw_ri_immd),
1186                                                    16);
1187                 break;
1188         case FW_RI_INIT_P2PTYPE_READ_REQ:
1189                 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1190                 init->u.read.stag_src = cpu_to_be32(1);
1191                 init->u.read.to_src_lo = cpu_to_be32(1);
1192                 init->u.read.stag_sink = cpu_to_be32(1);
1193                 init->u.read.to_sink_lo = cpu_to_be32(1);
1194                 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1195                 break;
1196         }
1197 }
1198
1199 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1200 {
1201         struct fw_ri_wr *wqe;
1202         int ret;
1203         struct sk_buff *skb;
1204
1205         PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1206              qhp->ep->hwtid);
1207
1208         skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1209         if (!skb)
1210                 return -ENOMEM;
1211         set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1212
1213         wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1214         memset(wqe, 0, sizeof *wqe);
1215         wqe->op_compl = cpu_to_be32(
1216                 FW_WR_OP(FW_RI_INIT_WR) |
1217                 FW_WR_COMPL(1));
1218         wqe->flowid_len16 = cpu_to_be32(
1219                 FW_WR_FLOWID(qhp->ep->hwtid) |
1220                 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1221
1222         wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
1223
1224         wqe->u.init.type = FW_RI_TYPE_INIT;
1225         wqe->u.init.mpareqbit_p2ptype =
1226                 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1227                 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1228         wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1229         if (qhp->attr.mpa_attr.recv_marker_enabled)
1230                 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1231         if (qhp->attr.mpa_attr.xmit_marker_enabled)
1232                 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1233         if (qhp->attr.mpa_attr.crc_enabled)
1234                 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1235
1236         wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1237                             FW_RI_QP_RDMA_WRITE_ENABLE |
1238                             FW_RI_QP_BIND_ENABLE;
1239         if (!qhp->ibqp.uobject)
1240                 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1241                                      FW_RI_QP_STAG0_ENABLE;
1242         wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1243         wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1244         wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1245         wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1246         wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1247         wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1248         wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1249         wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1250         wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1251         wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1252         wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1253         wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1254         wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1255                                          rhp->rdev.lldi.vr->rq.start);
1256         if (qhp->attr.mpa_attr.initiator)
1257                 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1258
1259         ret = c4iw_ofld_send(&rhp->rdev, skb);
1260         if (ret)
1261                 goto out;
1262
1263         ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1264                                   qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1265 out:
1266         PDBG("%s ret %d\n", __func__, ret);
1267         return ret;
1268 }
1269
1270 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1271                    enum c4iw_qp_attr_mask mask,
1272                    struct c4iw_qp_attributes *attrs,
1273                    int internal)
1274 {
1275         int ret = 0;
1276         struct c4iw_qp_attributes newattr = qhp->attr;
1277         int disconnect = 0;
1278         int terminate = 0;
1279         int abort = 0;
1280         int free = 0;
1281         struct c4iw_ep *ep = NULL;
1282
1283         PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1284              qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1285              (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1286
1287         mutex_lock(&qhp->mutex);
1288
1289         /* Process attr changes if in IDLE */
1290         if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1291                 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1292                         ret = -EIO;
1293                         goto out;
1294                 }
1295                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1296                         newattr.enable_rdma_read = attrs->enable_rdma_read;
1297                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1298                         newattr.enable_rdma_write = attrs->enable_rdma_write;
1299                 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1300                         newattr.enable_bind = attrs->enable_bind;
1301                 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1302                         if (attrs->max_ord > c4iw_max_read_depth) {
1303                                 ret = -EINVAL;
1304                                 goto out;
1305                         }
1306                         newattr.max_ord = attrs->max_ord;
1307                 }
1308                 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1309                         if (attrs->max_ird > c4iw_max_read_depth) {
1310                                 ret = -EINVAL;
1311                                 goto out;
1312                         }
1313                         newattr.max_ird = attrs->max_ird;
1314                 }
1315                 qhp->attr = newattr;
1316         }
1317
1318         if (mask & C4IW_QP_ATTR_SQ_DB) {
1319                 ret = ring_kernel_sq_db(qhp, attrs->sq_db_inc);
1320                 goto out;
1321         }
1322         if (mask & C4IW_QP_ATTR_RQ_DB) {
1323                 ret = ring_kernel_rq_db(qhp, attrs->rq_db_inc);
1324                 goto out;
1325         }
1326
1327         if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1328                 goto out;
1329         if (qhp->attr.state == attrs->next_state)
1330                 goto out;
1331
1332         switch (qhp->attr.state) {
1333         case C4IW_QP_STATE_IDLE:
1334                 switch (attrs->next_state) {
1335                 case C4IW_QP_STATE_RTS:
1336                         if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1337                                 ret = -EINVAL;
1338                                 goto out;
1339                         }
1340                         if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1341                                 ret = -EINVAL;
1342                                 goto out;
1343                         }
1344                         qhp->attr.mpa_attr = attrs->mpa_attr;
1345                         qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1346                         qhp->ep = qhp->attr.llp_stream_handle;
1347                         set_state(qhp, C4IW_QP_STATE_RTS);
1348
1349                         /*
1350                          * Ref the endpoint here and deref when we
1351                          * disassociate the endpoint from the QP.  This
1352                          * happens in CLOSING->IDLE transition or *->ERROR
1353                          * transition.
1354                          */
1355                         c4iw_get_ep(&qhp->ep->com);
1356                         ret = rdma_init(rhp, qhp);
1357                         if (ret)
1358                                 goto err;
1359                         break;
1360                 case C4IW_QP_STATE_ERROR:
1361                         set_state(qhp, C4IW_QP_STATE_ERROR);
1362                         flush_qp(qhp);
1363                         break;
1364                 default:
1365                         ret = -EINVAL;
1366                         goto out;
1367                 }
1368                 break;
1369         case C4IW_QP_STATE_RTS:
1370                 switch (attrs->next_state) {
1371                 case C4IW_QP_STATE_CLOSING:
1372                         BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1373                         t4_set_wq_in_error(&qhp->wq);
1374                         set_state(qhp, C4IW_QP_STATE_CLOSING);
1375                         ep = qhp->ep;
1376                         if (!internal) {
1377                                 abort = 0;
1378                                 disconnect = 1;
1379                                 c4iw_get_ep(&qhp->ep->com);
1380                         }
1381                         ret = rdma_fini(rhp, qhp, ep);
1382                         if (ret)
1383                                 goto err;
1384                         break;
1385                 case C4IW_QP_STATE_TERMINATE:
1386                         t4_set_wq_in_error(&qhp->wq);
1387                         set_state(qhp, C4IW_QP_STATE_TERMINATE);
1388                         qhp->attr.layer_etype = attrs->layer_etype;
1389                         qhp->attr.ecode = attrs->ecode;
1390                         ep = qhp->ep;
1391                         disconnect = 1;
1392                         c4iw_get_ep(&qhp->ep->com);
1393                         if (!internal)
1394                                 terminate = 1;
1395                         else {
1396                                 ret = rdma_fini(rhp, qhp, ep);
1397                                 if (ret)
1398                                         goto err;
1399                         }
1400                         break;
1401                 case C4IW_QP_STATE_ERROR:
1402                         t4_set_wq_in_error(&qhp->wq);
1403                         set_state(qhp, C4IW_QP_STATE_ERROR);
1404                         if (!internal) {
1405                                 abort = 1;
1406                                 disconnect = 1;
1407                                 ep = qhp->ep;
1408                                 c4iw_get_ep(&qhp->ep->com);
1409                         }
1410                         goto err;
1411                         break;
1412                 default:
1413                         ret = -EINVAL;
1414                         goto out;
1415                 }
1416                 break;
1417         case C4IW_QP_STATE_CLOSING:
1418                 if (!internal) {
1419                         ret = -EINVAL;
1420                         goto out;
1421                 }
1422                 switch (attrs->next_state) {
1423                 case C4IW_QP_STATE_IDLE:
1424                         flush_qp(qhp);
1425                         set_state(qhp, C4IW_QP_STATE_IDLE);
1426                         qhp->attr.llp_stream_handle = NULL;
1427                         c4iw_put_ep(&qhp->ep->com);
1428                         qhp->ep = NULL;
1429                         wake_up(&qhp->wait);
1430                         break;
1431                 case C4IW_QP_STATE_ERROR:
1432                         goto err;
1433                 default:
1434                         ret = -EINVAL;
1435                         goto err;
1436                 }
1437                 break;
1438         case C4IW_QP_STATE_ERROR:
1439                 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1440                         ret = -EINVAL;
1441                         goto out;
1442                 }
1443                 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1444                         ret = -EINVAL;
1445                         goto out;
1446                 }
1447                 set_state(qhp, C4IW_QP_STATE_IDLE);
1448                 break;
1449         case C4IW_QP_STATE_TERMINATE:
1450                 if (!internal) {
1451                         ret = -EINVAL;
1452                         goto out;
1453                 }
1454                 goto err;
1455                 break;
1456         default:
1457                 printk(KERN_ERR "%s in a bad state %d\n",
1458                        __func__, qhp->attr.state);
1459                 ret = -EINVAL;
1460                 goto err;
1461                 break;
1462         }
1463         goto out;
1464 err:
1465         PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1466              qhp->wq.sq.qid);
1467
1468         /* disassociate the LLP connection */
1469         qhp->attr.llp_stream_handle = NULL;
1470         if (!ep)
1471                 ep = qhp->ep;
1472         qhp->ep = NULL;
1473         set_state(qhp, C4IW_QP_STATE_ERROR);
1474         free = 1;
1475         abort = 1;
1476         wake_up(&qhp->wait);
1477         BUG_ON(!ep);
1478         flush_qp(qhp);
1479 out:
1480         mutex_unlock(&qhp->mutex);
1481
1482         if (terminate)
1483                 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1484
1485         /*
1486          * If disconnect is 1, then we need to initiate a disconnect
1487          * on the EP.  This can be a normal close (RTS->CLOSING) or
1488          * an abnormal close (RTS/CLOSING->ERROR).
1489          */
1490         if (disconnect) {
1491                 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1492                                                          GFP_KERNEL);
1493                 c4iw_put_ep(&ep->com);
1494         }
1495
1496         /*
1497          * If free is 1, then we've disassociated the EP from the QP
1498          * and we need to dereference the EP.
1499          */
1500         if (free)
1501                 c4iw_put_ep(&ep->com);
1502         PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1503         return ret;
1504 }
1505
1506 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1507 {
1508         struct c4iw_dev *rhp;
1509         struct c4iw_qp *qhp;
1510         struct c4iw_qp_attributes attrs;
1511         struct c4iw_ucontext *ucontext;
1512
1513         qhp = to_c4iw_qp(ib_qp);
1514         rhp = qhp->rhp;
1515
1516         attrs.next_state = C4IW_QP_STATE_ERROR;
1517         if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1518                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1519         else
1520                 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1521         wait_event(qhp->wait, !qhp->ep);
1522
1523         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1524         atomic_dec(&qhp->refcnt);
1525         wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1526
1527         spin_lock_irq(&rhp->lock);
1528         if (!list_empty(&qhp->db_fc_entry))
1529                 list_del_init(&qhp->db_fc_entry);
1530         spin_unlock_irq(&rhp->lock);
1531
1532         ucontext = ib_qp->uobject ?
1533                    to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1534         destroy_qp(&rhp->rdev, &qhp->wq,
1535                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1536
1537         PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1538         kfree(qhp);
1539         return 0;
1540 }
1541
1542 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1543                              struct ib_udata *udata)
1544 {
1545         struct c4iw_dev *rhp;
1546         struct c4iw_qp *qhp;
1547         struct c4iw_pd *php;
1548         struct c4iw_cq *schp;
1549         struct c4iw_cq *rchp;
1550         struct c4iw_create_qp_resp uresp;
1551         unsigned int sqsize, rqsize;
1552         struct c4iw_ucontext *ucontext;
1553         int ret;
1554         struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
1555
1556         PDBG("%s ib_pd %p\n", __func__, pd);
1557
1558         if (attrs->qp_type != IB_QPT_RC)
1559                 return ERR_PTR(-EINVAL);
1560
1561         php = to_c4iw_pd(pd);
1562         rhp = php->rhp;
1563         schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1564         rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1565         if (!schp || !rchp)
1566                 return ERR_PTR(-EINVAL);
1567
1568         if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1569                 return ERR_PTR(-EINVAL);
1570
1571         rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1572         if (rqsize > T4_MAX_RQ_SIZE)
1573                 return ERR_PTR(-E2BIG);
1574
1575         sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1576         if (sqsize > T4_MAX_SQ_SIZE)
1577                 return ERR_PTR(-E2BIG);
1578
1579         ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1580
1581         qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1582         if (!qhp)
1583                 return ERR_PTR(-ENOMEM);
1584         qhp->wq.sq.size = sqsize;
1585         qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1586         qhp->wq.sq.flush_cidx = -1;
1587         qhp->wq.rq.size = rqsize;
1588         qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1589
1590         if (ucontext) {
1591                 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1592                 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1593         }
1594
1595         PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1596              __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1597
1598         ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1599                         ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1600         if (ret)
1601                 goto err1;
1602
1603         attrs->cap.max_recv_wr = rqsize - 1;
1604         attrs->cap.max_send_wr = sqsize - 1;
1605         attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1606
1607         qhp->rhp = rhp;
1608         qhp->attr.pd = php->pdid;
1609         qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1610         qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1611         qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1612         qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1613         qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1614         qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1615         qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1616         qhp->attr.state = C4IW_QP_STATE_IDLE;
1617         qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1618         qhp->attr.enable_rdma_read = 1;
1619         qhp->attr.enable_rdma_write = 1;
1620         qhp->attr.enable_bind = 1;
1621         qhp->attr.max_ord = 1;
1622         qhp->attr.max_ird = 1;
1623         qhp->sq_sig_all = attrs->sq_sig_type == IB_SIGNAL_ALL_WR;
1624         spin_lock_init(&qhp->lock);
1625         mutex_init(&qhp->mutex);
1626         init_waitqueue_head(&qhp->wait);
1627         atomic_set(&qhp->refcnt, 1);
1628
1629         ret = insert_handle(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1630         if (ret)
1631                 goto err2;
1632
1633         if (udata) {
1634                 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1635                 if (!mm1) {
1636                         ret = -ENOMEM;
1637                         goto err3;
1638                 }
1639                 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1640                 if (!mm2) {
1641                         ret = -ENOMEM;
1642                         goto err4;
1643                 }
1644                 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1645                 if (!mm3) {
1646                         ret = -ENOMEM;
1647                         goto err5;
1648                 }
1649                 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1650                 if (!mm4) {
1651                         ret = -ENOMEM;
1652                         goto err6;
1653                 }
1654                 if (t4_sq_onchip(&qhp->wq.sq)) {
1655                         mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1656                         if (!mm5) {
1657                                 ret = -ENOMEM;
1658                                 goto err7;
1659                         }
1660                         uresp.flags = C4IW_QPF_ONCHIP;
1661                 } else
1662                         uresp.flags = 0;
1663                 uresp.qid_mask = rhp->rdev.qpmask;
1664                 uresp.sqid = qhp->wq.sq.qid;
1665                 uresp.sq_size = qhp->wq.sq.size;
1666                 uresp.sq_memsize = qhp->wq.sq.memsize;
1667                 uresp.rqid = qhp->wq.rq.qid;
1668                 uresp.rq_size = qhp->wq.rq.size;
1669                 uresp.rq_memsize = qhp->wq.rq.memsize;
1670                 spin_lock(&ucontext->mmap_lock);
1671                 if (mm5) {
1672                         uresp.ma_sync_key = ucontext->key;
1673                         ucontext->key += PAGE_SIZE;
1674                 } else {
1675                         uresp.ma_sync_key =  0;
1676                 }
1677                 uresp.sq_key = ucontext->key;
1678                 ucontext->key += PAGE_SIZE;
1679                 uresp.rq_key = ucontext->key;
1680                 ucontext->key += PAGE_SIZE;
1681                 uresp.sq_db_gts_key = ucontext->key;
1682                 ucontext->key += PAGE_SIZE;
1683                 uresp.rq_db_gts_key = ucontext->key;
1684                 ucontext->key += PAGE_SIZE;
1685                 spin_unlock(&ucontext->mmap_lock);
1686                 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1687                 if (ret)
1688                         goto err8;
1689                 mm1->key = uresp.sq_key;
1690                 mm1->addr = qhp->wq.sq.phys_addr;
1691                 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1692                 insert_mmap(ucontext, mm1);
1693                 mm2->key = uresp.rq_key;
1694                 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1695                 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1696                 insert_mmap(ucontext, mm2);
1697                 mm3->key = uresp.sq_db_gts_key;
1698                 mm3->addr = (__force unsigned long) qhp->wq.sq.udb;
1699                 mm3->len = PAGE_SIZE;
1700                 insert_mmap(ucontext, mm3);
1701                 mm4->key = uresp.rq_db_gts_key;
1702                 mm4->addr = (__force unsigned long) qhp->wq.rq.udb;
1703                 mm4->len = PAGE_SIZE;
1704                 insert_mmap(ucontext, mm4);
1705                 if (mm5) {
1706                         mm5->key = uresp.ma_sync_key;
1707                         mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1708                                     + A_PCIE_MA_SYNC) & PAGE_MASK;
1709                         mm5->len = PAGE_SIZE;
1710                         insert_mmap(ucontext, mm5);
1711                 }
1712         }
1713         qhp->ibqp.qp_num = qhp->wq.sq.qid;
1714         init_timer(&(qhp->timer));
1715         INIT_LIST_HEAD(&qhp->db_fc_entry);
1716         PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1717              __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1718              qhp->wq.sq.qid);
1719         return &qhp->ibqp;
1720 err8:
1721         kfree(mm5);
1722 err7:
1723         kfree(mm4);
1724 err6:
1725         kfree(mm3);
1726 err5:
1727         kfree(mm2);
1728 err4:
1729         kfree(mm1);
1730 err3:
1731         remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1732 err2:
1733         destroy_qp(&rhp->rdev, &qhp->wq,
1734                    ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1735 err1:
1736         kfree(qhp);
1737         return ERR_PTR(ret);
1738 }
1739
1740 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1741                       int attr_mask, struct ib_udata *udata)
1742 {
1743         struct c4iw_dev *rhp;
1744         struct c4iw_qp *qhp;
1745         enum c4iw_qp_attr_mask mask = 0;
1746         struct c4iw_qp_attributes attrs;
1747
1748         PDBG("%s ib_qp %p\n", __func__, ibqp);
1749
1750         /* iwarp does not support the RTR state */
1751         if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1752                 attr_mask &= ~IB_QP_STATE;
1753
1754         /* Make sure we still have something left to do */
1755         if (!attr_mask)
1756                 return 0;
1757
1758         memset(&attrs, 0, sizeof attrs);
1759         qhp = to_c4iw_qp(ibqp);
1760         rhp = qhp->rhp;
1761
1762         attrs.next_state = c4iw_convert_state(attr->qp_state);
1763         attrs.enable_rdma_read = (attr->qp_access_flags &
1764                                IB_ACCESS_REMOTE_READ) ?  1 : 0;
1765         attrs.enable_rdma_write = (attr->qp_access_flags &
1766                                 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1767         attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1768
1769
1770         mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1771         mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1772                         (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1773                          C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1774                          C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1775
1776         /*
1777          * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1778          * ringing the queue db when we're in DB_FULL mode.
1779          */
1780         attrs.sq_db_inc = attr->sq_psn;
1781         attrs.rq_db_inc = attr->rq_psn;
1782         mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1783         mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1784
1785         return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1786 }
1787
1788 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1789 {
1790         PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1791         return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1792 }
1793
1794 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1795                      int attr_mask, struct ib_qp_init_attr *init_attr)
1796 {
1797         struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1798
1799         memset(attr, 0, sizeof *attr);
1800         memset(init_attr, 0, sizeof *init_attr);
1801         attr->qp_state = to_ib_qp_state(qhp->attr.state);
1802         return 0;
1803 }