1 /*******************************************************************************
3 * Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenFabrics.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 *******************************************************************************/
38 #define I40IW_FIRST_USER_QP_ID 2
40 #define I40IW_DB_ADDR_OFFSET (4 * 1024 * 1024 - 64 * 1024)
41 #define I40IW_VF_DB_ADDR_OFFSET (64 * 1024)
43 #define I40IW_PUSH_OFFSET (4 * 1024 * 1024)
44 #define I40IW_PF_FIRST_PUSH_PAGE_INDEX 16
45 #define I40IW_VF_PUSH_OFFSET ((8 + 64) * 1024)
46 #define I40IW_VF_FIRST_PUSH_PAGE_INDEX 2
48 #define I40IW_PE_DB_SIZE_4M 1
49 #define I40IW_PE_DB_SIZE_8M 2
51 #define I40IW_DDP_VER 1
52 #define I40IW_RDMAP_VER 1
54 #define I40IW_RDMA_MODE_RDMAC 0
55 #define I40IW_RDMA_MODE_IETF 1
57 #define I40IW_QP_STATE_INVALID 0
58 #define I40IW_QP_STATE_IDLE 1
59 #define I40IW_QP_STATE_RTS 2
60 #define I40IW_QP_STATE_CLOSING 3
61 #define I40IW_QP_STATE_RESERVED 4
62 #define I40IW_QP_STATE_TERMINATE 5
63 #define I40IW_QP_STATE_ERROR 6
65 #define I40IW_STAG_STATE_INVALID 0
66 #define I40IW_STAG_STATE_VALID 1
68 #define I40IW_STAG_TYPE_SHARED 0
69 #define I40IW_STAG_TYPE_NONSHARED 1
71 #define I40IW_MAX_USER_PRIORITY 8
73 #define LS_64_1(val, bits) ((u64)(uintptr_t)val << bits)
74 #define RS_64_1(val, bits) ((u64)(uintptr_t)val >> bits)
75 #define LS_32_1(val, bits) (u32)(val << bits)
76 #define RS_32_1(val, bits) (u32)(val >> bits)
77 #define I40E_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
79 #define QS_HANDLE_UNKNOWN 0xffff
81 #define LS_64(val, field) (((u64)val << field ## _SHIFT) & (field ## _MASK))
83 #define RS_64(val, field) ((u64)(val & field ## _MASK) >> field ## _SHIFT)
84 #define LS_32(val, field) ((val << field ## _SHIFT) & (field ## _MASK))
85 #define RS_32(val, field) ((val & field ## _MASK) >> field ## _SHIFT)
87 #define TERM_DDP_LEN_TAGGED 14
88 #define TERM_DDP_LEN_UNTAGGED 18
89 #define TERM_RDMA_LEN 28
90 #define RDMA_OPCODE_MASK 0x0f
91 #define RDMA_READ_REQ_OPCODE 1
92 #define Q2_BAD_FRAME_OFFSET 72
93 #define CQE_MAJOR_DRV 0x8000
95 #define I40IW_TERM_SENT 0x01
96 #define I40IW_TERM_RCVD 0x02
97 #define I40IW_TERM_DONE 0x04
98 #define I40IW_MAC_HLEN 14
100 #define I40IW_INVALID_WQE_INDEX 0xffffffff
102 #define I40IW_CQP_WAIT_POLL_REGS 1
103 #define I40IW_CQP_WAIT_POLL_CQ 2
104 #define I40IW_CQP_WAIT_EVENT 3
106 #define I40IW_CQP_INIT_WQE(wqe) memset(wqe, 0, 64)
108 #define I40IW_GET_CURRENT_CQ_ELEMENT(_cq) \
110 &((_cq)->cq_base[I40IW_RING_GETCURRENT_HEAD((_cq)->cq_ring)]) \
112 #define I40IW_GET_CURRENT_EXTENDED_CQ_ELEMENT(_cq) \
114 &(((struct i40iw_extended_cqe *) \
115 ((_cq)->cq_base))[I40IW_RING_GETCURRENT_HEAD((_cq)->cq_ring)]) \
118 #define I40IW_GET_CURRENT_AEQ_ELEMENT(_aeq) \
120 &_aeq->aeqe_base[I40IW_RING_GETCURRENT_TAIL(_aeq->aeq_ring)] \
123 #define I40IW_GET_CURRENT_CEQ_ELEMENT(_ceq) \
125 &_ceq->ceqe_base[I40IW_RING_GETCURRENT_TAIL(_ceq->ceq_ring)] \
128 #define I40IW_AE_SOURCE_RQ 0x1
129 #define I40IW_AE_SOURCE_RQ_0011 0x3
131 #define I40IW_AE_SOURCE_CQ 0x2
132 #define I40IW_AE_SOURCE_CQ_0110 0x6
133 #define I40IW_AE_SOURCE_CQ_1010 0xA
134 #define I40IW_AE_SOURCE_CQ_1110 0xE
136 #define I40IW_AE_SOURCE_SQ 0x5
137 #define I40IW_AE_SOURCE_SQ_0111 0x7
139 #define I40IW_AE_SOURCE_IN_RR_WR 0x9
140 #define I40IW_AE_SOURCE_IN_RR_WR_1011 0xB
141 #define I40IW_AE_SOURCE_OUT_RR 0xD
142 #define I40IW_AE_SOURCE_OUT_RR_1111 0xF
144 #define I40IW_TCP_STATE_NON_EXISTENT 0
145 #define I40IW_TCP_STATE_CLOSED 1
146 #define I40IW_TCP_STATE_LISTEN 2
147 #define I40IW_STATE_SYN_SEND 3
148 #define I40IW_TCP_STATE_SYN_RECEIVED 4
149 #define I40IW_TCP_STATE_ESTABLISHED 5
150 #define I40IW_TCP_STATE_CLOSE_WAIT 6
151 #define I40IW_TCP_STATE_FIN_WAIT_1 7
152 #define I40IW_TCP_STATE_CLOSING 8
153 #define I40IW_TCP_STATE_LAST_ACK 9
154 #define I40IW_TCP_STATE_FIN_WAIT_2 10
155 #define I40IW_TCP_STATE_TIME_WAIT 11
156 #define I40IW_TCP_STATE_RESERVED_1 12
157 #define I40IW_TCP_STATE_RESERVED_2 13
158 #define I40IW_TCP_STATE_RESERVED_3 14
159 #define I40IW_TCP_STATE_RESERVED_4 15
161 /* ILQ CQP hash table fields */
162 #define I40IW_CQPSQ_QHASH_VLANID_SHIFT 32
163 #define I40IW_CQPSQ_QHASH_VLANID_MASK \
164 ((u64)0xfff << I40IW_CQPSQ_QHASH_VLANID_SHIFT)
166 #define I40IW_CQPSQ_QHASH_QPN_SHIFT 32
167 #define I40IW_CQPSQ_QHASH_QPN_MASK \
168 ((u64)0x3ffff << I40IW_CQPSQ_QHASH_QPN_SHIFT)
170 #define I40IW_CQPSQ_QHASH_QS_HANDLE_SHIFT 0
171 #define I40IW_CQPSQ_QHASH_QS_HANDLE_MASK ((u64)0x3ff << I40IW_CQPSQ_QHASH_QS_HANDLE_SHIFT)
173 #define I40IW_CQPSQ_QHASH_SRC_PORT_SHIFT 16
174 #define I40IW_CQPSQ_QHASH_SRC_PORT_MASK \
175 ((u64)0xffff << I40IW_CQPSQ_QHASH_SRC_PORT_SHIFT)
177 #define I40IW_CQPSQ_QHASH_DEST_PORT_SHIFT 0
178 #define I40IW_CQPSQ_QHASH_DEST_PORT_MASK \
179 ((u64)0xffff << I40IW_CQPSQ_QHASH_DEST_PORT_SHIFT)
181 #define I40IW_CQPSQ_QHASH_ADDR0_SHIFT 32
182 #define I40IW_CQPSQ_QHASH_ADDR0_MASK \
183 ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR0_SHIFT)
185 #define I40IW_CQPSQ_QHASH_ADDR1_SHIFT 0
186 #define I40IW_CQPSQ_QHASH_ADDR1_MASK \
187 ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR1_SHIFT)
189 #define I40IW_CQPSQ_QHASH_ADDR2_SHIFT 32
190 #define I40IW_CQPSQ_QHASH_ADDR2_MASK \
191 ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR2_SHIFT)
193 #define I40IW_CQPSQ_QHASH_ADDR3_SHIFT 0
194 #define I40IW_CQPSQ_QHASH_ADDR3_MASK \
195 ((u64)0xffffffff << I40IW_CQPSQ_QHASH_ADDR3_SHIFT)
197 #define I40IW_CQPSQ_QHASH_WQEVALID_SHIFT 63
198 #define I40IW_CQPSQ_QHASH_WQEVALID_MASK \
199 ((u64)0x1 << I40IW_CQPSQ_QHASH_WQEVALID_SHIFT)
200 #define I40IW_CQPSQ_QHASH_OPCODE_SHIFT 32
201 #define I40IW_CQPSQ_QHASH_OPCODE_MASK \
202 ((u64)0x3f << I40IW_CQPSQ_QHASH_OPCODE_SHIFT)
204 #define I40IW_CQPSQ_QHASH_MANAGE_SHIFT 61
205 #define I40IW_CQPSQ_QHASH_MANAGE_MASK \
206 ((u64)0x3 << I40IW_CQPSQ_QHASH_MANAGE_SHIFT)
208 #define I40IW_CQPSQ_QHASH_IPV4VALID_SHIFT 60
209 #define I40IW_CQPSQ_QHASH_IPV4VALID_MASK \
210 ((u64)0x1 << I40IW_CQPSQ_QHASH_IPV4VALID_SHIFT)
212 #define I40IW_CQPSQ_QHASH_VLANVALID_SHIFT 59
213 #define I40IW_CQPSQ_QHASH_VLANVALID_MASK \
214 ((u64)0x1 << I40IW_CQPSQ_QHASH_VLANVALID_SHIFT)
216 #define I40IW_CQPSQ_QHASH_ENTRYTYPE_SHIFT 42
217 #define I40IW_CQPSQ_QHASH_ENTRYTYPE_MASK \
218 ((u64)0x7 << I40IW_CQPSQ_QHASH_ENTRYTYPE_SHIFT)
219 /* CQP Host Context */
220 #define I40IW_CQPHC_EN_DC_TCP_SHIFT 0
221 #define I40IW_CQPHC_EN_DC_TCP_MASK (1UL << I40IW_CQPHC_EN_DC_TCP_SHIFT)
223 #define I40IW_CQPHC_SQSIZE_SHIFT 8
224 #define I40IW_CQPHC_SQSIZE_MASK (0xfUL << I40IW_CQPHC_SQSIZE_SHIFT)
226 #define I40IW_CQPHC_DISABLE_PFPDUS_SHIFT 1
227 #define I40IW_CQPHC_DISABLE_PFPDUS_MASK (0x1UL << I40IW_CQPHC_DISABLE_PFPDUS_SHIFT)
229 #define I40IW_CQPHC_ENABLED_VFS_SHIFT 32
230 #define I40IW_CQPHC_ENABLED_VFS_MASK (0x3fULL << I40IW_CQPHC_ENABLED_VFS_SHIFT)
232 #define I40IW_CQPHC_HMC_PROFILE_SHIFT 0
233 #define I40IW_CQPHC_HMC_PROFILE_MASK (0x7ULL << I40IW_CQPHC_HMC_PROFILE_SHIFT)
235 #define I40IW_CQPHC_SVER_SHIFT 24
236 #define I40IW_CQPHC_SVER_MASK (0xffUL << I40IW_CQPHC_SVER_SHIFT)
238 #define I40IW_CQPHC_SQBASE_SHIFT 9
239 #define I40IW_CQPHC_SQBASE_MASK \
240 (0xfffffffffffffeULL << I40IW_CQPHC_SQBASE_SHIFT)
242 #define I40IW_CQPHC_QPCTX_SHIFT 0
243 #define I40IW_CQPHC_QPCTX_MASK \
244 (0xffffffffffffffffULL << I40IW_CQPHC_QPCTX_SHIFT)
245 #define I40IW_CQPHC_SVER 1
247 #define I40IW_CQP_SW_SQSIZE_4 4
248 #define I40IW_CQP_SW_SQSIZE_2048 2048
250 /* iWARP QP Doorbell shadow area */
251 #define I40IW_QP_DBSA_HW_SQ_TAIL_SHIFT 0
252 #define I40IW_QP_DBSA_HW_SQ_TAIL_MASK \
253 (0x3fffUL << I40IW_QP_DBSA_HW_SQ_TAIL_SHIFT)
255 /* Completion Queue Doorbell shadow area */
256 #define I40IW_CQ_DBSA_CQEIDX_SHIFT 0
257 #define I40IW_CQ_DBSA_CQEIDX_MASK (0xfffffUL << I40IW_CQ_DBSA_CQEIDX_SHIFT)
259 #define I40IW_CQ_DBSA_SW_CQ_SELECT_SHIFT 0
260 #define I40IW_CQ_DBSA_SW_CQ_SELECT_MASK \
261 (0x3fffUL << I40IW_CQ_DBSA_SW_CQ_SELECT_SHIFT)
263 #define I40IW_CQ_DBSA_ARM_NEXT_SHIFT 14
264 #define I40IW_CQ_DBSA_ARM_NEXT_MASK (1UL << I40IW_CQ_DBSA_ARM_NEXT_SHIFT)
266 #define I40IW_CQ_DBSA_ARM_NEXT_SE_SHIFT 15
267 #define I40IW_CQ_DBSA_ARM_NEXT_SE_MASK (1UL << I40IW_CQ_DBSA_ARM_NEXT_SE_SHIFT)
269 #define I40IW_CQ_DBSA_ARM_SEQ_NUM_SHIFT 16
270 #define I40IW_CQ_DBSA_ARM_SEQ_NUM_MASK \
271 (0x3UL << I40IW_CQ_DBSA_ARM_SEQ_NUM_SHIFT)
273 /* CQP and iWARP Completion Queue */
274 #define I40IW_CQ_QPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT
275 #define I40IW_CQ_QPCTX_MASK I40IW_CQPHC_QPCTX_MASK
277 #define I40IW_CCQ_OPRETVAL_SHIFT 0
278 #define I40IW_CCQ_OPRETVAL_MASK (0xffffffffUL << I40IW_CCQ_OPRETVAL_SHIFT)
280 #define I40IW_CQ_MINERR_SHIFT 0
281 #define I40IW_CQ_MINERR_MASK (0xffffUL << I40IW_CQ_MINERR_SHIFT)
283 #define I40IW_CQ_MAJERR_SHIFT 16
284 #define I40IW_CQ_MAJERR_MASK (0xffffUL << I40IW_CQ_MAJERR_SHIFT)
286 #define I40IW_CQ_WQEIDX_SHIFT 32
287 #define I40IW_CQ_WQEIDX_MASK (0x3fffULL << I40IW_CQ_WQEIDX_SHIFT)
289 #define I40IW_CQ_ERROR_SHIFT 55
290 #define I40IW_CQ_ERROR_MASK (1ULL << I40IW_CQ_ERROR_SHIFT)
292 #define I40IW_CQ_SQ_SHIFT 62
293 #define I40IW_CQ_SQ_MASK (1ULL << I40IW_CQ_SQ_SHIFT)
295 #define I40IW_CQ_VALID_SHIFT 63
296 #define I40IW_CQ_VALID_MASK (1ULL << I40IW_CQ_VALID_SHIFT)
298 #define I40IWCQ_PAYLDLEN_SHIFT 0
299 #define I40IWCQ_PAYLDLEN_MASK (0xffffffffUL << I40IWCQ_PAYLDLEN_SHIFT)
301 #define I40IWCQ_TCPSEQNUM_SHIFT 32
302 #define I40IWCQ_TCPSEQNUM_MASK (0xffffffffULL << I40IWCQ_TCPSEQNUM_SHIFT)
304 #define I40IWCQ_INVSTAG_SHIFT 0
305 #define I40IWCQ_INVSTAG_MASK (0xffffffffUL << I40IWCQ_INVSTAG_SHIFT)
307 #define I40IWCQ_QPID_SHIFT 32
308 #define I40IWCQ_QPID_MASK (0x3ffffULL << I40IWCQ_QPID_SHIFT)
310 #define I40IWCQ_PSHDROP_SHIFT 51
311 #define I40IWCQ_PSHDROP_MASK (1ULL << I40IWCQ_PSHDROP_SHIFT)
313 #define I40IWCQ_SRQ_SHIFT 52
314 #define I40IWCQ_SRQ_MASK (1ULL << I40IWCQ_SRQ_SHIFT)
316 #define I40IWCQ_STAG_SHIFT 53
317 #define I40IWCQ_STAG_MASK (1ULL << I40IWCQ_STAG_SHIFT)
319 #define I40IWCQ_SOEVENT_SHIFT 54
320 #define I40IWCQ_SOEVENT_MASK (1ULL << I40IWCQ_SOEVENT_SHIFT)
322 #define I40IWCQ_OP_SHIFT 56
323 #define I40IWCQ_OP_MASK (0x3fULL << I40IWCQ_OP_SHIFT)
326 #define I40IW_CEQE_CQCTX_SHIFT 0
327 #define I40IW_CEQE_CQCTX_MASK \
328 (0x7fffffffffffffffULL << I40IW_CEQE_CQCTX_SHIFT)
330 #define I40IW_CEQE_VALID_SHIFT 63
331 #define I40IW_CEQE_VALID_MASK (1ULL << I40IW_CEQE_VALID_SHIFT)
334 #define I40IW_AEQE_COMPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT
335 #define I40IW_AEQE_COMPCTX_MASK I40IW_CQPHC_QPCTX_MASK
337 #define I40IW_AEQE_QPCQID_SHIFT 0
338 #define I40IW_AEQE_QPCQID_MASK (0x3ffffUL << I40IW_AEQE_QPCQID_SHIFT)
340 #define I40IW_AEQE_WQDESCIDX_SHIFT 18
341 #define I40IW_AEQE_WQDESCIDX_MASK (0x3fffULL << I40IW_AEQE_WQDESCIDX_SHIFT)
343 #define I40IW_AEQE_OVERFLOW_SHIFT 33
344 #define I40IW_AEQE_OVERFLOW_MASK (1ULL << I40IW_AEQE_OVERFLOW_SHIFT)
346 #define I40IW_AEQE_AECODE_SHIFT 34
347 #define I40IW_AEQE_AECODE_MASK (0xffffULL << I40IW_AEQE_AECODE_SHIFT)
349 #define I40IW_AEQE_AESRC_SHIFT 50
350 #define I40IW_AEQE_AESRC_MASK (0xfULL << I40IW_AEQE_AESRC_SHIFT)
352 #define I40IW_AEQE_IWSTATE_SHIFT 54
353 #define I40IW_AEQE_IWSTATE_MASK (0x7ULL << I40IW_AEQE_IWSTATE_SHIFT)
355 #define I40IW_AEQE_TCPSTATE_SHIFT 57
356 #define I40IW_AEQE_TCPSTATE_MASK (0xfULL << I40IW_AEQE_TCPSTATE_SHIFT)
358 #define I40IW_AEQE_Q2DATA_SHIFT 61
359 #define I40IW_AEQE_Q2DATA_MASK (0x3ULL << I40IW_AEQE_Q2DATA_SHIFT)
361 #define I40IW_AEQE_VALID_SHIFT 63
362 #define I40IW_AEQE_VALID_MASK (1ULL << I40IW_AEQE_VALID_SHIFT)
365 #define I40IW_QP_TYPE_IWARP 1
366 #define I40IW_QP_TYPE_UDA 2
367 #define I40IW_QP_TYPE_CQP 4
369 #define I40IW_CQ_TYPE_IWARP 1
370 #define I40IW_CQ_TYPE_ILQ 2
371 #define I40IW_CQ_TYPE_IEQ 3
372 #define I40IW_CQ_TYPE_CQP 4
374 #define I40IWQP_TERM_SEND_TERM_AND_FIN 0
375 #define I40IWQP_TERM_SEND_TERM_ONLY 1
376 #define I40IWQP_TERM_SEND_FIN_ONLY 2
377 #define I40IWQP_TERM_DONOT_SEND_TERM_OR_FIN 3
379 #define I40IW_CQP_OP_CREATE_QP 0
380 #define I40IW_CQP_OP_MODIFY_QP 0x1
381 #define I40IW_CQP_OP_DESTROY_QP 0x02
382 #define I40IW_CQP_OP_CREATE_CQ 0x03
383 #define I40IW_CQP_OP_MODIFY_CQ 0x04
384 #define I40IW_CQP_OP_DESTROY_CQ 0x05
385 #define I40IW_CQP_OP_CREATE_SRQ 0x06
386 #define I40IW_CQP_OP_MODIFY_SRQ 0x07
387 #define I40IW_CQP_OP_DESTROY_SRQ 0x08
388 #define I40IW_CQP_OP_ALLOC_STAG 0x09
389 #define I40IW_CQP_OP_REG_MR 0x0a
390 #define I40IW_CQP_OP_QUERY_STAG 0x0b
391 #define I40IW_CQP_OP_REG_SMR 0x0c
392 #define I40IW_CQP_OP_DEALLOC_STAG 0x0d
393 #define I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE 0x0e
394 #define I40IW_CQP_OP_MANAGE_ARP 0x0f
395 #define I40IW_CQP_OP_MANAGE_VF_PBLE_BP 0x10
396 #define I40IW_CQP_OP_MANAGE_PUSH_PAGES 0x11
397 #define I40IW_CQP_OP_MANAGE_PE_TEAM 0x12
398 #define I40IW_CQP_OP_UPLOAD_CONTEXT 0x13
399 #define I40IW_CQP_OP_ALLOCATE_LOC_MAC_IP_TABLE_ENTRY 0x14
400 #define I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE 0x15
401 #define I40IW_CQP_OP_CREATE_CEQ 0x16
402 #define I40IW_CQP_OP_DESTROY_CEQ 0x18
403 #define I40IW_CQP_OP_CREATE_AEQ 0x19
404 #define I40IW_CQP_OP_DESTROY_AEQ 0x1b
405 #define I40IW_CQP_OP_CREATE_ADDR_VECT 0x1c
406 #define I40IW_CQP_OP_MODIFY_ADDR_VECT 0x1d
407 #define I40IW_CQP_OP_DESTROY_ADDR_VECT 0x1e
408 #define I40IW_CQP_OP_UPDATE_PE_SDS 0x1f
409 #define I40IW_CQP_OP_QUERY_FPM_VALUES 0x20
410 #define I40IW_CQP_OP_COMMIT_FPM_VALUES 0x21
411 #define I40IW_CQP_OP_FLUSH_WQES 0x22
412 #define I40IW_CQP_OP_MANAGE_APBVT 0x23
413 #define I40IW_CQP_OP_NOP 0x24
414 #define I40IW_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY 0x25
415 #define I40IW_CQP_OP_CREATE_UDA_MCAST_GROUP 0x26
416 #define I40IW_CQP_OP_MODIFY_UDA_MCAST_GROUP 0x27
417 #define I40IW_CQP_OP_DESTROY_UDA_MCAST_GROUP 0x28
418 #define I40IW_CQP_OP_SUSPEND_QP 0x29
419 #define I40IW_CQP_OP_RESUME_QP 0x2a
420 #define I40IW_CQP_OP_SHMC_PAGES_ALLOCATED 0x2b
421 #define I40IW_CQP_OP_SET_HMC_RESOURCE_PROFILE 0x2d
423 #define I40IW_UDA_QPSQ_NEXT_HEADER_SHIFT 16
424 #define I40IW_UDA_QPSQ_NEXT_HEADER_MASK ((u64)0xff << I40IW_UDA_QPSQ_NEXT_HEADER_SHIFT)
426 #define I40IW_UDA_QPSQ_OPCODE_SHIFT 32
427 #define I40IW_UDA_QPSQ_OPCODE_MASK ((u64)0x3f << I40IW_UDA_QPSQ_OPCODE_SHIFT)
429 #define I40IW_UDA_QPSQ_MACLEN_SHIFT 56
430 #define I40IW_UDA_QPSQ_MACLEN_MASK \
431 ((u64)0x7f << I40IW_UDA_QPSQ_MACLEN_SHIFT)
433 #define I40IW_UDA_QPSQ_IPLEN_SHIFT 48
434 #define I40IW_UDA_QPSQ_IPLEN_MASK \
435 ((u64)0x7f << I40IW_UDA_QPSQ_IPLEN_SHIFT)
437 #define I40IW_UDA_QPSQ_L4T_SHIFT 30
438 #define I40IW_UDA_QPSQ_L4T_MASK \
439 ((u64)0x3 << I40IW_UDA_QPSQ_L4T_SHIFT)
441 #define I40IW_UDA_QPSQ_IIPT_SHIFT 28
442 #define I40IW_UDA_QPSQ_IIPT_MASK \
443 ((u64)0x3 << I40IW_UDA_QPSQ_IIPT_SHIFT)
445 #define I40IW_UDA_QPSQ_L4LEN_SHIFT 24
446 #define I40IW_UDA_QPSQ_L4LEN_MASK ((u64)0xf << I40IW_UDA_QPSQ_L4LEN_SHIFT)
448 #define I40IW_UDA_QPSQ_AVIDX_SHIFT 0
449 #define I40IW_UDA_QPSQ_AVIDX_MASK ((u64)0xffff << I40IW_UDA_QPSQ_AVIDX_SHIFT)
451 #define I40IW_UDA_QPSQ_VALID_SHIFT 63
452 #define I40IW_UDA_QPSQ_VALID_MASK \
453 ((u64)0x1 << I40IW_UDA_QPSQ_VALID_SHIFT)
455 #define I40IW_UDA_QPSQ_SIGCOMPL_SHIFT 62
456 #define I40IW_UDA_QPSQ_SIGCOMPL_MASK ((u64)0x1 << I40IW_UDA_QPSQ_SIGCOMPL_SHIFT)
458 #define I40IW_UDA_PAYLOADLEN_SHIFT 0
459 #define I40IW_UDA_PAYLOADLEN_MASK ((u64)0x3fff << I40IW_UDA_PAYLOADLEN_SHIFT)
461 #define I40IW_UDA_HDRLEN_SHIFT 16
462 #define I40IW_UDA_HDRLEN_MASK ((u64)0x1ff << I40IW_UDA_HDRLEN_SHIFT)
464 #define I40IW_VLAN_TAG_VALID_SHIFT 50
465 #define I40IW_VLAN_TAG_VALID_MASK ((u64)0x1 << I40IW_VLAN_TAG_VALID_SHIFT)
467 #define I40IW_UDA_L3PROTO_SHIFT 0
468 #define I40IW_UDA_L3PROTO_MASK ((u64)0x3 << I40IW_UDA_L3PROTO_SHIFT)
470 #define I40IW_UDA_L4PROTO_SHIFT 16
471 #define I40IW_UDA_L4PROTO_MASK ((u64)0x3 << I40IW_UDA_L4PROTO_SHIFT)
473 #define I40IW_UDA_QPSQ_DOLOOPBACK_SHIFT 44
474 #define I40IW_UDA_QPSQ_DOLOOPBACK_MASK \
475 ((u64)0x1 << I40IW_UDA_QPSQ_DOLOOPBACK_SHIFT)
477 /* CQP SQ WQE common fields */
478 #define I40IW_CQPSQ_OPCODE_SHIFT 32
479 #define I40IW_CQPSQ_OPCODE_MASK (0x3fULL << I40IW_CQPSQ_OPCODE_SHIFT)
481 #define I40IW_CQPSQ_WQEVALID_SHIFT 63
482 #define I40IW_CQPSQ_WQEVALID_MASK (1ULL << I40IW_CQPSQ_WQEVALID_SHIFT)
484 #define I40IW_CQPSQ_TPHVAL_SHIFT 0
485 #define I40IW_CQPSQ_TPHVAL_MASK (0xffUL << I40IW_CQPSQ_TPHVAL_SHIFT)
487 #define I40IW_CQPSQ_TPHEN_SHIFT 60
488 #define I40IW_CQPSQ_TPHEN_MASK (1ULL << I40IW_CQPSQ_TPHEN_SHIFT)
490 #define I40IW_CQPSQ_PBUFADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT
491 #define I40IW_CQPSQ_PBUFADDR_MASK I40IW_CQPHC_QPCTX_MASK
493 /* Create/Modify/Destroy QP */
495 #define I40IW_CQPSQ_QP_NEWMSS_SHIFT 32
496 #define I40IW_CQPSQ_QP_NEWMSS_MASK (0x3fffULL << I40IW_CQPSQ_QP_NEWMSS_SHIFT)
498 #define I40IW_CQPSQ_QP_TERMLEN_SHIFT 48
499 #define I40IW_CQPSQ_QP_TERMLEN_MASK (0xfULL << I40IW_CQPSQ_QP_TERMLEN_SHIFT)
501 #define I40IW_CQPSQ_QP_QPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT
502 #define I40IW_CQPSQ_QP_QPCTX_MASK I40IW_CQPHC_QPCTX_MASK
504 #define I40IW_CQPSQ_QP_QPID_SHIFT 0
505 #define I40IW_CQPSQ_QP_QPID_MASK (0x3FFFFUL)
506 /* I40IWCQ_QPID_MASK */
508 #define I40IW_CQPSQ_QP_OP_SHIFT 32
509 #define I40IW_CQPSQ_QP_OP_MASK I40IWCQ_OP_MASK
511 #define I40IW_CQPSQ_QP_ORDVALID_SHIFT 42
512 #define I40IW_CQPSQ_QP_ORDVALID_MASK (1ULL << I40IW_CQPSQ_QP_ORDVALID_SHIFT)
514 #define I40IW_CQPSQ_QP_TOECTXVALID_SHIFT 43
515 #define I40IW_CQPSQ_QP_TOECTXVALID_MASK \
516 (1ULL << I40IW_CQPSQ_QP_TOECTXVALID_SHIFT)
518 #define I40IW_CQPSQ_QP_CACHEDVARVALID_SHIFT 44
519 #define I40IW_CQPSQ_QP_CACHEDVARVALID_MASK \
520 (1ULL << I40IW_CQPSQ_QP_CACHEDVARVALID_SHIFT)
522 #define I40IW_CQPSQ_QP_VQ_SHIFT 45
523 #define I40IW_CQPSQ_QP_VQ_MASK (1ULL << I40IW_CQPSQ_QP_VQ_SHIFT)
525 #define I40IW_CQPSQ_QP_FORCELOOPBACK_SHIFT 46
526 #define I40IW_CQPSQ_QP_FORCELOOPBACK_MASK \
527 (1ULL << I40IW_CQPSQ_QP_FORCELOOPBACK_SHIFT)
529 #define I40IW_CQPSQ_QP_CQNUMVALID_SHIFT 47
530 #define I40IW_CQPSQ_QP_CQNUMVALID_MASK \
531 (1ULL << I40IW_CQPSQ_QP_CQNUMVALID_SHIFT)
533 #define I40IW_CQPSQ_QP_QPTYPE_SHIFT 48
534 #define I40IW_CQPSQ_QP_QPTYPE_MASK (0x3ULL << I40IW_CQPSQ_QP_QPTYPE_SHIFT)
536 #define I40IW_CQPSQ_QP_MSSCHANGE_SHIFT 52
537 #define I40IW_CQPSQ_QP_MSSCHANGE_MASK (1ULL << I40IW_CQPSQ_QP_MSSCHANGE_SHIFT)
539 #define I40IW_CQPSQ_QP_STATRSRC_SHIFT 53
540 #define I40IW_CQPSQ_QP_STATRSRC_MASK (1ULL << I40IW_CQPSQ_QP_STATRSRC_SHIFT)
542 #define I40IW_CQPSQ_QP_IGNOREMWBOUND_SHIFT 54
543 #define I40IW_CQPSQ_QP_IGNOREMWBOUND_MASK \
544 (1ULL << I40IW_CQPSQ_QP_IGNOREMWBOUND_SHIFT)
546 #define I40IW_CQPSQ_QP_REMOVEHASHENTRY_SHIFT 55
547 #define I40IW_CQPSQ_QP_REMOVEHASHENTRY_MASK \
548 (1ULL << I40IW_CQPSQ_QP_REMOVEHASHENTRY_SHIFT)
550 #define I40IW_CQPSQ_QP_TERMACT_SHIFT 56
551 #define I40IW_CQPSQ_QP_TERMACT_MASK (0x3ULL << I40IW_CQPSQ_QP_TERMACT_SHIFT)
553 #define I40IW_CQPSQ_QP_RESETCON_SHIFT 58
554 #define I40IW_CQPSQ_QP_RESETCON_MASK (1ULL << I40IW_CQPSQ_QP_RESETCON_SHIFT)
556 #define I40IW_CQPSQ_QP_ARPTABIDXVALID_SHIFT 59
557 #define I40IW_CQPSQ_QP_ARPTABIDXVALID_MASK \
558 (1ULL << I40IW_CQPSQ_QP_ARPTABIDXVALID_SHIFT)
560 #define I40IW_CQPSQ_QP_NEXTIWSTATE_SHIFT 60
561 #define I40IW_CQPSQ_QP_NEXTIWSTATE_MASK \
562 (0x7ULL << I40IW_CQPSQ_QP_NEXTIWSTATE_SHIFT)
564 #define I40IW_CQPSQ_QP_DBSHADOWADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT
565 #define I40IW_CQPSQ_QP_DBSHADOWADDR_MASK I40IW_CQPHC_QPCTX_MASK
567 /* Create/Modify/Destroy CQ */
568 #define I40IW_CQPSQ_CQ_CQSIZE_SHIFT 0
569 #define I40IW_CQPSQ_CQ_CQSIZE_MASK (0x3ffffUL << I40IW_CQPSQ_CQ_CQSIZE_SHIFT)
571 #define I40IW_CQPSQ_CQ_CQCTX_SHIFT 0
572 #define I40IW_CQPSQ_CQ_CQCTX_MASK \
573 (0x7fffffffffffffffULL << I40IW_CQPSQ_CQ_CQCTX_SHIFT)
575 #define I40IW_CQPSQ_CQ_CQCTX_SHIFT 0
576 #define I40IW_CQPSQ_CQ_CQCTX_MASK \
577 (0x7fffffffffffffffULL << I40IW_CQPSQ_CQ_CQCTX_SHIFT)
579 #define I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD_SHIFT 0
580 #define I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD_MASK \
581 (0x3ffff << I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD_SHIFT)
583 #define I40IW_CQPSQ_CQ_CEQID_SHIFT 24
584 #define I40IW_CQPSQ_CQ_CEQID_MASK (0x7fUL << I40IW_CQPSQ_CQ_CEQID_SHIFT)
586 #define I40IW_CQPSQ_CQ_OP_SHIFT 32
587 #define I40IW_CQPSQ_CQ_OP_MASK (0x3fULL << I40IW_CQPSQ_CQ_OP_SHIFT)
589 #define I40IW_CQPSQ_CQ_CQRESIZE_SHIFT 43
590 #define I40IW_CQPSQ_CQ_CQRESIZE_MASK (1ULL << I40IW_CQPSQ_CQ_CQRESIZE_SHIFT)
592 #define I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT 44
593 #define I40IW_CQPSQ_CQ_LPBLSIZE_MASK (3ULL << I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT)
595 #define I40IW_CQPSQ_CQ_CHKOVERFLOW_SHIFT 46
596 #define I40IW_CQPSQ_CQ_CHKOVERFLOW_MASK \
597 (1ULL << I40IW_CQPSQ_CQ_CHKOVERFLOW_SHIFT)
599 #define I40IW_CQPSQ_CQ_VIRTMAP_SHIFT 47
600 #define I40IW_CQPSQ_CQ_VIRTMAP_MASK (1ULL << I40IW_CQPSQ_CQ_VIRTMAP_SHIFT)
602 #define I40IW_CQPSQ_CQ_ENCEQEMASK_SHIFT 48
603 #define I40IW_CQPSQ_CQ_ENCEQEMASK_MASK \
604 (1ULL << I40IW_CQPSQ_CQ_ENCEQEMASK_SHIFT)
606 #define I40IW_CQPSQ_CQ_CEQIDVALID_SHIFT 49
607 #define I40IW_CQPSQ_CQ_CEQIDVALID_MASK \
608 (1ULL << I40IW_CQPSQ_CQ_CEQIDVALID_SHIFT)
610 #define I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT_SHIFT 61
611 #define I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT_MASK \
612 (1ULL << I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT_SHIFT)
614 /* Create/Modify/Destroy Shared Receive Queue */
616 #define I40IW_CQPSQ_SRQ_RQSIZE_SHIFT 0
617 #define I40IW_CQPSQ_SRQ_RQSIZE_MASK (0xfUL << I40IW_CQPSQ_SRQ_RQSIZE_SHIFT)
619 #define I40IW_CQPSQ_SRQ_RQWQESIZE_SHIFT 4
620 #define I40IW_CQPSQ_SRQ_RQWQESIZE_MASK \
621 (0x7UL << I40IW_CQPSQ_SRQ_RQWQESIZE_SHIFT)
623 #define I40IW_CQPSQ_SRQ_SRQLIMIT_SHIFT 32
624 #define I40IW_CQPSQ_SRQ_SRQLIMIT_MASK \
625 (0xfffULL << I40IW_CQPSQ_SRQ_SRQLIMIT_SHIFT)
627 #define I40IW_CQPSQ_SRQ_SRQCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT
628 #define I40IW_CQPSQ_SRQ_SRQCTX_MASK I40IW_CQPHC_QPCTX_MASK
630 #define I40IW_CQPSQ_SRQ_PDID_SHIFT 16
631 #define I40IW_CQPSQ_SRQ_PDID_MASK \
632 (0x7fffULL << I40IW_CQPSQ_SRQ_PDID_SHIFT)
634 #define I40IW_CQPSQ_SRQ_SRQID_SHIFT 0
635 #define I40IW_CQPSQ_SRQ_SRQID_MASK (0x7fffUL << I40IW_CQPSQ_SRQ_SRQID_SHIFT)
637 #define I40IW_CQPSQ_SRQ_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT
638 #define I40IW_CQPSQ_SRQ_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK
640 #define I40IW_CQPSQ_SRQ_VIRTMAP_SHIFT I40IW_CQPSQ_CQ_VIRTMAP_SHIFT
641 #define I40IW_CQPSQ_SRQ_VIRTMAP_MASK I40IW_CQPSQ_CQ_VIRTMAP_MASK
643 #define I40IW_CQPSQ_SRQ_TPHEN_SHIFT I40IW_CQPSQ_TPHEN_SHIFT
644 #define I40IW_CQPSQ_SRQ_TPHEN_MASK I40IW_CQPSQ_TPHEN_MASK
646 #define I40IW_CQPSQ_SRQ_ARMLIMITEVENT_SHIFT 61
647 #define I40IW_CQPSQ_SRQ_ARMLIMITEVENT_MASK \
648 (1ULL << I40IW_CQPSQ_SRQ_ARMLIMITEVENT_SHIFT)
650 #define I40IW_CQPSQ_SRQ_DBSHADOWAREA_SHIFT 6
651 #define I40IW_CQPSQ_SRQ_DBSHADOWAREA_MASK \
652 (0x3ffffffffffffffULL << I40IW_CQPSQ_SRQ_DBSHADOWAREA_SHIFT)
654 #define I40IW_CQPSQ_SRQ_FIRSTPMPBLIDX_SHIFT 0
655 #define I40IW_CQPSQ_SRQ_FIRSTPMPBLIDX_MASK \
656 (0xfffffffUL << I40IW_CQPSQ_SRQ_FIRSTPMPBLIDX_SHIFT)
658 /* Allocate/Register/Register Shared/Deallocate Stag */
659 #define I40IW_CQPSQ_STAG_VA_FBO_SHIFT I40IW_CQPHC_QPCTX_SHIFT
660 #define I40IW_CQPSQ_STAG_VA_FBO_MASK I40IW_CQPHC_QPCTX_MASK
662 #define I40IW_CQPSQ_STAG_STAGLEN_SHIFT 0
663 #define I40IW_CQPSQ_STAG_STAGLEN_MASK \
664 (0x3fffffffffffULL << I40IW_CQPSQ_STAG_STAGLEN_SHIFT)
666 #define I40IW_CQPSQ_STAG_PDID_SHIFT 48
667 #define I40IW_CQPSQ_STAG_PDID_MASK (0x7fffULL << I40IW_CQPSQ_STAG_PDID_SHIFT)
669 #define I40IW_CQPSQ_STAG_KEY_SHIFT 0
670 #define I40IW_CQPSQ_STAG_KEY_MASK (0xffUL << I40IW_CQPSQ_STAG_KEY_SHIFT)
672 #define I40IW_CQPSQ_STAG_IDX_SHIFT 8
673 #define I40IW_CQPSQ_STAG_IDX_MASK (0xffffffUL << I40IW_CQPSQ_STAG_IDX_SHIFT)
675 #define I40IW_CQPSQ_STAG_PARENTSTAGIDX_SHIFT 32
676 #define I40IW_CQPSQ_STAG_PARENTSTAGIDX_MASK \
677 (0xffffffULL << I40IW_CQPSQ_STAG_PARENTSTAGIDX_SHIFT)
679 #define I40IW_CQPSQ_STAG_MR_SHIFT 43
680 #define I40IW_CQPSQ_STAG_MR_MASK (1ULL << I40IW_CQPSQ_STAG_MR_SHIFT)
682 #define I40IW_CQPSQ_STAG_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT
683 #define I40IW_CQPSQ_STAG_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK
685 #define I40IW_CQPSQ_STAG_HPAGESIZE_SHIFT 46
686 #define I40IW_CQPSQ_STAG_HPAGESIZE_MASK \
687 (1ULL << I40IW_CQPSQ_STAG_HPAGESIZE_SHIFT)
689 #define I40IW_CQPSQ_STAG_ARIGHTS_SHIFT 48
690 #define I40IW_CQPSQ_STAG_ARIGHTS_MASK \
691 (0x1fULL << I40IW_CQPSQ_STAG_ARIGHTS_SHIFT)
693 #define I40IW_CQPSQ_STAG_REMACCENABLED_SHIFT 53
694 #define I40IW_CQPSQ_STAG_REMACCENABLED_MASK \
695 (1ULL << I40IW_CQPSQ_STAG_REMACCENABLED_SHIFT)
697 #define I40IW_CQPSQ_STAG_VABASEDTO_SHIFT 59
698 #define I40IW_CQPSQ_STAG_VABASEDTO_MASK \
699 (1ULL << I40IW_CQPSQ_STAG_VABASEDTO_SHIFT)
701 #define I40IW_CQPSQ_STAG_USEHMCFNIDX_SHIFT 60
702 #define I40IW_CQPSQ_STAG_USEHMCFNIDX_MASK \
703 (1ULL << I40IW_CQPSQ_STAG_USEHMCFNIDX_SHIFT)
705 #define I40IW_CQPSQ_STAG_USEPFRID_SHIFT 61
706 #define I40IW_CQPSQ_STAG_USEPFRID_MASK \
707 (1ULL << I40IW_CQPSQ_STAG_USEPFRID_SHIFT)
709 #define I40IW_CQPSQ_STAG_PBA_SHIFT I40IW_CQPHC_QPCTX_SHIFT
710 #define I40IW_CQPSQ_STAG_PBA_MASK I40IW_CQPHC_QPCTX_MASK
712 #define I40IW_CQPSQ_STAG_HMCFNIDX_SHIFT 0
713 #define I40IW_CQPSQ_STAG_HMCFNIDX_MASK \
714 (0x3fUL << I40IW_CQPSQ_STAG_HMCFNIDX_SHIFT)
716 #define I40IW_CQPSQ_STAG_FIRSTPMPBLIDX_SHIFT 0
717 #define I40IW_CQPSQ_STAG_FIRSTPMPBLIDX_MASK \
718 (0xfffffffUL << I40IW_CQPSQ_STAG_FIRSTPMPBLIDX_SHIFT)
721 #define I40IW_CQPSQ_QUERYSTAG_IDX_SHIFT I40IW_CQPSQ_STAG_IDX_SHIFT
722 #define I40IW_CQPSQ_QUERYSTAG_IDX_MASK I40IW_CQPSQ_STAG_IDX_MASK
724 /* Allocate Local IP Address Entry */
726 /* Manage Local IP Address Table - MLIPA */
727 #define I40IW_CQPSQ_MLIPA_IPV6LO_SHIFT I40IW_CQPHC_QPCTX_SHIFT
728 #define I40IW_CQPSQ_MLIPA_IPV6LO_MASK I40IW_CQPHC_QPCTX_MASK
730 #define I40IW_CQPSQ_MLIPA_IPV6HI_SHIFT I40IW_CQPHC_QPCTX_SHIFT
731 #define I40IW_CQPSQ_MLIPA_IPV6HI_MASK I40IW_CQPHC_QPCTX_MASK
733 #define I40IW_CQPSQ_MLIPA_IPV4_SHIFT 0
734 #define I40IW_CQPSQ_MLIPA_IPV4_MASK \
735 (0xffffffffUL << I40IW_CQPSQ_MLIPA_IPV4_SHIFT)
737 #define I40IW_CQPSQ_MLIPA_IPTABLEIDX_SHIFT 0
738 #define I40IW_CQPSQ_MLIPA_IPTABLEIDX_MASK \
739 (0x3fUL << I40IW_CQPSQ_MLIPA_IPTABLEIDX_SHIFT)
741 #define I40IW_CQPSQ_MLIPA_IPV4VALID_SHIFT 42
742 #define I40IW_CQPSQ_MLIPA_IPV4VALID_MASK \
743 (1ULL << I40IW_CQPSQ_MLIPA_IPV4VALID_SHIFT)
745 #define I40IW_CQPSQ_MLIPA_IPV6VALID_SHIFT 43
746 #define I40IW_CQPSQ_MLIPA_IPV6VALID_MASK \
747 (1ULL << I40IW_CQPSQ_MLIPA_IPV6VALID_SHIFT)
749 #define I40IW_CQPSQ_MLIPA_FREEENTRY_SHIFT 62
750 #define I40IW_CQPSQ_MLIPA_FREEENTRY_MASK \
751 (1ULL << I40IW_CQPSQ_MLIPA_FREEENTRY_SHIFT)
753 #define I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT_SHIFT 61
754 #define I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT_MASK \
755 (1ULL << I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT_SHIFT)
757 #define I40IW_CQPSQ_MLIPA_MAC0_SHIFT 0
758 #define I40IW_CQPSQ_MLIPA_MAC0_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC0_SHIFT)
760 #define I40IW_CQPSQ_MLIPA_MAC1_SHIFT 8
761 #define I40IW_CQPSQ_MLIPA_MAC1_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC1_SHIFT)
763 #define I40IW_CQPSQ_MLIPA_MAC2_SHIFT 16
764 #define I40IW_CQPSQ_MLIPA_MAC2_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC2_SHIFT)
766 #define I40IW_CQPSQ_MLIPA_MAC3_SHIFT 24
767 #define I40IW_CQPSQ_MLIPA_MAC3_MASK (0xffUL << I40IW_CQPSQ_MLIPA_MAC3_SHIFT)
769 #define I40IW_CQPSQ_MLIPA_MAC4_SHIFT 32
770 #define I40IW_CQPSQ_MLIPA_MAC4_MASK (0xffULL << I40IW_CQPSQ_MLIPA_MAC4_SHIFT)
772 #define I40IW_CQPSQ_MLIPA_MAC5_SHIFT 40
773 #define I40IW_CQPSQ_MLIPA_MAC5_MASK (0xffULL << I40IW_CQPSQ_MLIPA_MAC5_SHIFT)
775 /* Manage ARP Table - MAT */
776 #define I40IW_CQPSQ_MAT_REACHMAX_SHIFT 0
777 #define I40IW_CQPSQ_MAT_REACHMAX_MASK \
778 (0xffffffffUL << I40IW_CQPSQ_MAT_REACHMAX_SHIFT)
780 #define I40IW_CQPSQ_MAT_MACADDR_SHIFT 0
781 #define I40IW_CQPSQ_MAT_MACADDR_MASK \
782 (0xffffffffffffULL << I40IW_CQPSQ_MAT_MACADDR_SHIFT)
784 #define I40IW_CQPSQ_MAT_ARPENTRYIDX_SHIFT 0
785 #define I40IW_CQPSQ_MAT_ARPENTRYIDX_MASK \
786 (0xfffUL << I40IW_CQPSQ_MAT_ARPENTRYIDX_SHIFT)
788 #define I40IW_CQPSQ_MAT_ENTRYVALID_SHIFT 42
789 #define I40IW_CQPSQ_MAT_ENTRYVALID_MASK \
790 (1ULL << I40IW_CQPSQ_MAT_ENTRYVALID_SHIFT)
792 #define I40IW_CQPSQ_MAT_PERMANENT_SHIFT 43
793 #define I40IW_CQPSQ_MAT_PERMANENT_MASK \
794 (1ULL << I40IW_CQPSQ_MAT_PERMANENT_SHIFT)
796 #define I40IW_CQPSQ_MAT_QUERY_SHIFT 44
797 #define I40IW_CQPSQ_MAT_QUERY_MASK (1ULL << I40IW_CQPSQ_MAT_QUERY_SHIFT)
799 /* Manage VF PBLE Backing Pages - MVPBP*/
800 #define I40IW_CQPSQ_MVPBP_PD_ENTRY_CNT_SHIFT 0
801 #define I40IW_CQPSQ_MVPBP_PD_ENTRY_CNT_MASK \
802 (0x3ffULL << I40IW_CQPSQ_MVPBP_PD_ENTRY_CNT_SHIFT)
804 #define I40IW_CQPSQ_MVPBP_FIRST_PD_INX_SHIFT 16
805 #define I40IW_CQPSQ_MVPBP_FIRST_PD_INX_MASK \
806 (0x1ffULL << I40IW_CQPSQ_MVPBP_FIRST_PD_INX_SHIFT)
808 #define I40IW_CQPSQ_MVPBP_SD_INX_SHIFT 32
809 #define I40IW_CQPSQ_MVPBP_SD_INX_MASK \
810 (0xfffULL << I40IW_CQPSQ_MVPBP_SD_INX_SHIFT)
812 #define I40IW_CQPSQ_MVPBP_INV_PD_ENT_SHIFT 62
813 #define I40IW_CQPSQ_MVPBP_INV_PD_ENT_MASK \
814 (0x1ULL << I40IW_CQPSQ_MVPBP_INV_PD_ENT_SHIFT)
816 #define I40IW_CQPSQ_MVPBP_PD_PLPBA_SHIFT 3
817 #define I40IW_CQPSQ_MVPBP_PD_PLPBA_MASK \
818 (0x1fffffffffffffffULL << I40IW_CQPSQ_MVPBP_PD_PLPBA_SHIFT)
820 /* Manage Push Page - MPP */
821 #define I40IW_INVALID_PUSH_PAGE_INDEX 0xffff
823 #define I40IW_CQPSQ_MPP_QS_HANDLE_SHIFT 0
824 #define I40IW_CQPSQ_MPP_QS_HANDLE_MASK (0xffffUL << \
825 I40IW_CQPSQ_MPP_QS_HANDLE_SHIFT)
827 #define I40IW_CQPSQ_MPP_PPIDX_SHIFT 0
828 #define I40IW_CQPSQ_MPP_PPIDX_MASK (0x3ffUL << I40IW_CQPSQ_MPP_PPIDX_SHIFT)
830 #define I40IW_CQPSQ_MPP_FREE_PAGE_SHIFT 62
831 #define I40IW_CQPSQ_MPP_FREE_PAGE_MASK (1ULL << I40IW_CQPSQ_MPP_FREE_PAGE_SHIFT)
833 /* Upload Context - UCTX */
834 #define I40IW_CQPSQ_UCTX_QPCTXADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT
835 #define I40IW_CQPSQ_UCTX_QPCTXADDR_MASK I40IW_CQPHC_QPCTX_MASK
837 #define I40IW_CQPSQ_UCTX_QPID_SHIFT 0
838 #define I40IW_CQPSQ_UCTX_QPID_MASK (0x3ffffUL << I40IW_CQPSQ_UCTX_QPID_SHIFT)
840 #define I40IW_CQPSQ_UCTX_QPTYPE_SHIFT 48
841 #define I40IW_CQPSQ_UCTX_QPTYPE_MASK (0xfULL << I40IW_CQPSQ_UCTX_QPTYPE_SHIFT)
843 #define I40IW_CQPSQ_UCTX_RAWFORMAT_SHIFT 61
844 #define I40IW_CQPSQ_UCTX_RAWFORMAT_MASK \
845 (1ULL << I40IW_CQPSQ_UCTX_RAWFORMAT_SHIFT)
847 #define I40IW_CQPSQ_UCTX_FREEZEQP_SHIFT 62
848 #define I40IW_CQPSQ_UCTX_FREEZEQP_MASK \
849 (1ULL << I40IW_CQPSQ_UCTX_FREEZEQP_SHIFT)
851 /* Manage HMC PM Function Table - MHMC */
852 #define I40IW_CQPSQ_MHMC_VFIDX_SHIFT 0
853 #define I40IW_CQPSQ_MHMC_VFIDX_MASK (0x7fUL << I40IW_CQPSQ_MHMC_VFIDX_SHIFT)
855 #define I40IW_CQPSQ_MHMC_FREEPMFN_SHIFT 62
856 #define I40IW_CQPSQ_MHMC_FREEPMFN_MASK \
857 (1ULL << I40IW_CQPSQ_MHMC_FREEPMFN_SHIFT)
859 /* Set HMC Resource Profile - SHMCRP */
860 #define I40IW_CQPSQ_SHMCRP_HMC_PROFILE_SHIFT 0
861 #define I40IW_CQPSQ_SHMCRP_HMC_PROFILE_MASK \
862 (0x7ULL << I40IW_CQPSQ_SHMCRP_HMC_PROFILE_SHIFT)
863 #define I40IW_CQPSQ_SHMCRP_VFNUM_SHIFT 32
864 #define I40IW_CQPSQ_SHMCRP_VFNUM_MASK (0x3fULL << I40IW_CQPSQ_SHMCRP_VFNUM_SHIFT)
866 /* Create/Destroy CEQ */
867 #define I40IW_CQPSQ_CEQ_CEQSIZE_SHIFT 0
868 #define I40IW_CQPSQ_CEQ_CEQSIZE_MASK \
869 (0x1ffffUL << I40IW_CQPSQ_CEQ_CEQSIZE_SHIFT)
871 #define I40IW_CQPSQ_CEQ_CEQID_SHIFT 0
872 #define I40IW_CQPSQ_CEQ_CEQID_MASK (0x7fUL << I40IW_CQPSQ_CEQ_CEQID_SHIFT)
874 #define I40IW_CQPSQ_CEQ_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT
875 #define I40IW_CQPSQ_CEQ_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK
877 #define I40IW_CQPSQ_CEQ_VMAP_SHIFT 47
878 #define I40IW_CQPSQ_CEQ_VMAP_MASK (1ULL << I40IW_CQPSQ_CEQ_VMAP_SHIFT)
880 #define I40IW_CQPSQ_CEQ_FIRSTPMPBLIDX_SHIFT 0
881 #define I40IW_CQPSQ_CEQ_FIRSTPMPBLIDX_MASK \
882 (0xfffffffUL << I40IW_CQPSQ_CEQ_FIRSTPMPBLIDX_SHIFT)
884 /* Create/Destroy AEQ */
885 #define I40IW_CQPSQ_AEQ_AEQECNT_SHIFT 0
886 #define I40IW_CQPSQ_AEQ_AEQECNT_MASK \
887 (0x7ffffUL << I40IW_CQPSQ_AEQ_AEQECNT_SHIFT)
889 #define I40IW_CQPSQ_AEQ_LPBLSIZE_SHIFT I40IW_CQPSQ_CQ_LPBLSIZE_SHIFT
890 #define I40IW_CQPSQ_AEQ_LPBLSIZE_MASK I40IW_CQPSQ_CQ_LPBLSIZE_MASK
892 #define I40IW_CQPSQ_AEQ_VMAP_SHIFT 47
893 #define I40IW_CQPSQ_AEQ_VMAP_MASK (1ULL << I40IW_CQPSQ_AEQ_VMAP_SHIFT)
895 #define I40IW_CQPSQ_AEQ_FIRSTPMPBLIDX_SHIFT 0
896 #define I40IW_CQPSQ_AEQ_FIRSTPMPBLIDX_MASK \
897 (0xfffffffUL << I40IW_CQPSQ_AEQ_FIRSTPMPBLIDX_SHIFT)
899 /* Commit FPM Values - CFPM */
900 #define I40IW_CQPSQ_CFPM_HMCFNID_SHIFT 0
901 #define I40IW_CQPSQ_CFPM_HMCFNID_MASK (0x3fUL << I40IW_CQPSQ_CFPM_HMCFNID_SHIFT)
903 /* Flush WQEs - FWQE */
904 #define I40IW_CQPSQ_FWQE_AECODE_SHIFT 0
905 #define I40IW_CQPSQ_FWQE_AECODE_MASK (0xffffUL << I40IW_CQPSQ_FWQE_AECODE_SHIFT)
907 #define I40IW_CQPSQ_FWQE_AESOURCE_SHIFT 16
908 #define I40IW_CQPSQ_FWQE_AESOURCE_MASK \
909 (0xfUL << I40IW_CQPSQ_FWQE_AESOURCE_SHIFT)
911 #define I40IW_CQPSQ_FWQE_RQMNERR_SHIFT 0
912 #define I40IW_CQPSQ_FWQE_RQMNERR_MASK \
913 (0xffffUL << I40IW_CQPSQ_FWQE_RQMNERR_SHIFT)
915 #define I40IW_CQPSQ_FWQE_RQMJERR_SHIFT 16
916 #define I40IW_CQPSQ_FWQE_RQMJERR_MASK \
917 (0xffffUL << I40IW_CQPSQ_FWQE_RQMJERR_SHIFT)
919 #define I40IW_CQPSQ_FWQE_SQMNERR_SHIFT 32
920 #define I40IW_CQPSQ_FWQE_SQMNERR_MASK \
921 (0xffffULL << I40IW_CQPSQ_FWQE_SQMNERR_SHIFT)
923 #define I40IW_CQPSQ_FWQE_SQMJERR_SHIFT 48
924 #define I40IW_CQPSQ_FWQE_SQMJERR_MASK \
925 (0xffffULL << I40IW_CQPSQ_FWQE_SQMJERR_SHIFT)
927 #define I40IW_CQPSQ_FWQE_QPID_SHIFT 0
928 #define I40IW_CQPSQ_FWQE_QPID_MASK (0x3ffffULL << I40IW_CQPSQ_FWQE_QPID_SHIFT)
930 #define I40IW_CQPSQ_FWQE_GENERATE_AE_SHIFT 59
931 #define I40IW_CQPSQ_FWQE_GENERATE_AE_MASK (1ULL << \
932 I40IW_CQPSQ_FWQE_GENERATE_AE_SHIFT)
934 #define I40IW_CQPSQ_FWQE_USERFLCODE_SHIFT 60
935 #define I40IW_CQPSQ_FWQE_USERFLCODE_MASK \
936 (1ULL << I40IW_CQPSQ_FWQE_USERFLCODE_SHIFT)
938 #define I40IW_CQPSQ_FWQE_FLUSHSQ_SHIFT 61
939 #define I40IW_CQPSQ_FWQE_FLUSHSQ_MASK (1ULL << I40IW_CQPSQ_FWQE_FLUSHSQ_SHIFT)
941 #define I40IW_CQPSQ_FWQE_FLUSHRQ_SHIFT 62
942 #define I40IW_CQPSQ_FWQE_FLUSHRQ_MASK (1ULL << I40IW_CQPSQ_FWQE_FLUSHRQ_SHIFT)
944 /* Manage Accelerated Port Table - MAPT */
945 #define I40IW_CQPSQ_MAPT_PORT_SHIFT 0
946 #define I40IW_CQPSQ_MAPT_PORT_MASK (0xffffUL << I40IW_CQPSQ_MAPT_PORT_SHIFT)
948 #define I40IW_CQPSQ_MAPT_ADDPORT_SHIFT 62
949 #define I40IW_CQPSQ_MAPT_ADDPORT_MASK (1ULL << I40IW_CQPSQ_MAPT_ADDPORT_SHIFT)
951 /* Update Protocol Engine SDs */
952 #define I40IW_CQPSQ_UPESD_SDCMD_SHIFT 0
953 #define I40IW_CQPSQ_UPESD_SDCMD_MASK (0xffffffffUL << I40IW_CQPSQ_UPESD_SDCMD_SHIFT)
955 #define I40IW_CQPSQ_UPESD_SDDATALOW_SHIFT 0
956 #define I40IW_CQPSQ_UPESD_SDDATALOW_MASK \
957 (0xffffffffUL << I40IW_CQPSQ_UPESD_SDDATALOW_SHIFT)
959 #define I40IW_CQPSQ_UPESD_SDDATAHI_SHIFT 32
960 #define I40IW_CQPSQ_UPESD_SDDATAHI_MASK \
961 (0xffffffffULL << I40IW_CQPSQ_UPESD_SDDATAHI_SHIFT)
962 #define I40IW_CQPSQ_UPESD_HMCFNID_SHIFT 0
963 #define I40IW_CQPSQ_UPESD_HMCFNID_MASK \
964 (0x3fUL << I40IW_CQPSQ_UPESD_HMCFNID_SHIFT)
966 #define I40IW_CQPSQ_UPESD_ENTRY_VALID_SHIFT 63
967 #define I40IW_CQPSQ_UPESD_ENTRY_VALID_MASK \
968 ((u64)1 << I40IW_CQPSQ_UPESD_ENTRY_VALID_SHIFT)
970 #define I40IW_CQPSQ_UPESD_ENTRY_COUNT_SHIFT 0
971 #define I40IW_CQPSQ_UPESD_ENTRY_COUNT_MASK \
972 (0xfUL << I40IW_CQPSQ_UPESD_ENTRY_COUNT_SHIFT)
974 #define I40IW_CQPSQ_UPESD_SKIP_ENTRY_SHIFT 7
975 #define I40IW_CQPSQ_UPESD_SKIP_ENTRY_MASK \
976 (0x1UL << I40IW_CQPSQ_UPESD_SKIP_ENTRY_SHIFT)
979 #define I40IW_CQPSQ_SUSPENDQP_QPID_SHIFT 0
980 #define I40IW_CQPSQ_SUSPENDQP_QPID_MASK (0x3FFFFUL)
981 /* I40IWCQ_QPID_MASK */
984 #define I40IW_CQPSQ_RESUMEQP_QSHANDLE_SHIFT 0
985 #define I40IW_CQPSQ_RESUMEQP_QSHANDLE_MASK \
986 (0xffffffffUL << I40IW_CQPSQ_RESUMEQP_QSHANDLE_SHIFT)
988 #define I40IW_CQPSQ_RESUMEQP_QPID_SHIFT 0
989 #define I40IW_CQPSQ_RESUMEQP_QPID_MASK (0x3FFFFUL)
990 /* I40IWCQ_QPID_MASK */
993 #define I40IWQPC_DDP_VER_SHIFT 0
994 #define I40IWQPC_DDP_VER_MASK (3UL << I40IWQPC_DDP_VER_SHIFT)
996 #define I40IWQPC_SNAP_SHIFT 2
997 #define I40IWQPC_SNAP_MASK (1UL << I40IWQPC_SNAP_SHIFT)
999 #define I40IWQPC_IPV4_SHIFT 3
1000 #define I40IWQPC_IPV4_MASK (1UL << I40IWQPC_IPV4_SHIFT)
1002 #define I40IWQPC_NONAGLE_SHIFT 4
1003 #define I40IWQPC_NONAGLE_MASK (1UL << I40IWQPC_NONAGLE_SHIFT)
1005 #define I40IWQPC_INSERTVLANTAG_SHIFT 5
1006 #define I40IWQPC_INSERTVLANTAG_MASK (1 << I40IWQPC_INSERTVLANTAG_SHIFT)
1008 #define I40IWQPC_USESRQ_SHIFT 6
1009 #define I40IWQPC_USESRQ_MASK (1UL << I40IWQPC_USESRQ_SHIFT)
1011 #define I40IWQPC_TIMESTAMP_SHIFT 7
1012 #define I40IWQPC_TIMESTAMP_MASK (1UL << I40IWQPC_TIMESTAMP_SHIFT)
1014 #define I40IWQPC_RQWQESIZE_SHIFT 8
1015 #define I40IWQPC_RQWQESIZE_MASK (3UL << I40IWQPC_RQWQESIZE_SHIFT)
1017 #define I40IWQPC_INSERTL2TAG2_SHIFT 11
1018 #define I40IWQPC_INSERTL2TAG2_MASK (1UL << I40IWQPC_INSERTL2TAG2_SHIFT)
1020 #define I40IWQPC_LIMIT_SHIFT 12
1021 #define I40IWQPC_LIMIT_MASK (3UL << I40IWQPC_LIMIT_SHIFT)
1023 #define I40IWQPC_DROPOOOSEG_SHIFT 15
1024 #define I40IWQPC_DROPOOOSEG_MASK (1UL << I40IWQPC_DROPOOOSEG_SHIFT)
1026 #define I40IWQPC_DUPACK_THRESH_SHIFT 16
1027 #define I40IWQPC_DUPACK_THRESH_MASK (7UL << I40IWQPC_DUPACK_THRESH_SHIFT)
1029 #define I40IWQPC_ERR_RQ_IDX_VALID_SHIFT 19
1030 #define I40IWQPC_ERR_RQ_IDX_VALID_MASK (1UL << I40IWQPC_ERR_RQ_IDX_VALID_SHIFT)
1032 #define I40IWQPC_DIS_VLAN_CHECKS_SHIFT 19
1033 #define I40IWQPC_DIS_VLAN_CHECKS_MASK (7UL << I40IWQPC_DIS_VLAN_CHECKS_SHIFT)
1035 #define I40IWQPC_RCVTPHEN_SHIFT 28
1036 #define I40IWQPC_RCVTPHEN_MASK (1UL << I40IWQPC_RCVTPHEN_SHIFT)
1038 #define I40IWQPC_XMITTPHEN_SHIFT 29
1039 #define I40IWQPC_XMITTPHEN_MASK (1ULL << I40IWQPC_XMITTPHEN_SHIFT)
1041 #define I40IWQPC_RQTPHEN_SHIFT 30
1042 #define I40IWQPC_RQTPHEN_MASK (1UL << I40IWQPC_RQTPHEN_SHIFT)
1044 #define I40IWQPC_SQTPHEN_SHIFT 31
1045 #define I40IWQPC_SQTPHEN_MASK (1ULL << I40IWQPC_SQTPHEN_SHIFT)
1047 #define I40IWQPC_PPIDX_SHIFT 32
1048 #define I40IWQPC_PPIDX_MASK (0x3ffULL << I40IWQPC_PPIDX_SHIFT)
1050 #define I40IWQPC_PMENA_SHIFT 47
1051 #define I40IWQPC_PMENA_MASK (1ULL << I40IWQPC_PMENA_SHIFT)
1053 #define I40IWQPC_RDMAP_VER_SHIFT 62
1054 #define I40IWQPC_RDMAP_VER_MASK (3ULL << I40IWQPC_RDMAP_VER_SHIFT)
1056 #define I40IWQPC_SQADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1057 #define I40IWQPC_SQADDR_MASK I40IW_CQPHC_QPCTX_MASK
1059 #define I40IWQPC_RQADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1060 #define I40IWQPC_RQADDR_MASK I40IW_CQPHC_QPCTX_MASK
1062 #define I40IWQPC_TTL_SHIFT 0
1063 #define I40IWQPC_TTL_MASK (0xffUL << I40IWQPC_TTL_SHIFT)
1065 #define I40IWQPC_RQSIZE_SHIFT 8
1066 #define I40IWQPC_RQSIZE_MASK (0xfUL << I40IWQPC_RQSIZE_SHIFT)
1068 #define I40IWQPC_SQSIZE_SHIFT 12
1069 #define I40IWQPC_SQSIZE_MASK (0xfUL << I40IWQPC_SQSIZE_SHIFT)
1071 #define I40IWQPC_SRCMACADDRIDX_SHIFT 16
1072 #define I40IWQPC_SRCMACADDRIDX_MASK (0x3fUL << I40IWQPC_SRCMACADDRIDX_SHIFT)
1074 #define I40IWQPC_AVOIDSTRETCHACK_SHIFT 23
1075 #define I40IWQPC_AVOIDSTRETCHACK_MASK (1UL << I40IWQPC_AVOIDSTRETCHACK_SHIFT)
1077 #define I40IWQPC_TOS_SHIFT 24
1078 #define I40IWQPC_TOS_MASK (0xffUL << I40IWQPC_TOS_SHIFT)
1080 #define I40IWQPC_SRCPORTNUM_SHIFT 32
1081 #define I40IWQPC_SRCPORTNUM_MASK (0xffffULL << I40IWQPC_SRCPORTNUM_SHIFT)
1083 #define I40IWQPC_DESTPORTNUM_SHIFT 48
1084 #define I40IWQPC_DESTPORTNUM_MASK (0xffffULL << I40IWQPC_DESTPORTNUM_SHIFT)
1086 #define I40IWQPC_DESTIPADDR0_SHIFT 32
1087 #define I40IWQPC_DESTIPADDR0_MASK \
1088 (0xffffffffULL << I40IWQPC_DESTIPADDR0_SHIFT)
1090 #define I40IWQPC_DESTIPADDR1_SHIFT 0
1091 #define I40IWQPC_DESTIPADDR1_MASK \
1092 (0xffffffffULL << I40IWQPC_DESTIPADDR1_SHIFT)
1094 #define I40IWQPC_DESTIPADDR2_SHIFT 32
1095 #define I40IWQPC_DESTIPADDR2_MASK \
1096 (0xffffffffULL << I40IWQPC_DESTIPADDR2_SHIFT)
1098 #define I40IWQPC_DESTIPADDR3_SHIFT 0
1099 #define I40IWQPC_DESTIPADDR3_MASK \
1100 (0xffffffffULL << I40IWQPC_DESTIPADDR3_SHIFT)
1102 #define I40IWQPC_SNDMSS_SHIFT 16
1103 #define I40IWQPC_SNDMSS_MASK (0x3fffUL << I40IWQPC_SNDMSS_SHIFT)
1105 #define I40IWQPC_VLANTAG_SHIFT 32
1106 #define I40IWQPC_VLANTAG_MASK (0xffffULL << I40IWQPC_VLANTAG_SHIFT)
1108 #define I40IWQPC_ARPIDX_SHIFT 48
1109 #define I40IWQPC_ARPIDX_MASK (0xfffULL << I40IWQPC_ARPIDX_SHIFT)
1111 #define I40IWQPC_FLOWLABEL_SHIFT 0
1112 #define I40IWQPC_FLOWLABEL_MASK (0xfffffUL << I40IWQPC_FLOWLABEL_SHIFT)
1114 #define I40IWQPC_WSCALE_SHIFT 20
1115 #define I40IWQPC_WSCALE_MASK (1UL << I40IWQPC_WSCALE_SHIFT)
1117 #define I40IWQPC_KEEPALIVE_SHIFT 21
1118 #define I40IWQPC_KEEPALIVE_MASK (1UL << I40IWQPC_KEEPALIVE_SHIFT)
1120 #define I40IWQPC_IGNORE_TCP_OPT_SHIFT 22
1121 #define I40IWQPC_IGNORE_TCP_OPT_MASK (1UL << I40IWQPC_IGNORE_TCP_OPT_SHIFT)
1123 #define I40IWQPC_IGNORE_TCP_UNS_OPT_SHIFT 23
1124 #define I40IWQPC_IGNORE_TCP_UNS_OPT_MASK \
1125 (1UL << I40IWQPC_IGNORE_TCP_UNS_OPT_SHIFT)
1127 #define I40IWQPC_TCPSTATE_SHIFT 28
1128 #define I40IWQPC_TCPSTATE_MASK (0xfUL << I40IWQPC_TCPSTATE_SHIFT)
1130 #define I40IWQPC_RCVSCALE_SHIFT 32
1131 #define I40IWQPC_RCVSCALE_MASK (0xfULL << I40IWQPC_RCVSCALE_SHIFT)
1133 #define I40IWQPC_SNDSCALE_SHIFT 40
1134 #define I40IWQPC_SNDSCALE_MASK (0xfULL << I40IWQPC_SNDSCALE_SHIFT)
1136 #define I40IWQPC_PDIDX_SHIFT 48
1137 #define I40IWQPC_PDIDX_MASK (0x7fffULL << I40IWQPC_PDIDX_SHIFT)
1139 #define I40IWQPC_KALIVE_TIMER_MAX_PROBES_SHIFT 16
1140 #define I40IWQPC_KALIVE_TIMER_MAX_PROBES_MASK \
1141 (0xffUL << I40IWQPC_KALIVE_TIMER_MAX_PROBES_SHIFT)
1143 #define I40IWQPC_KEEPALIVE_INTERVAL_SHIFT 24
1144 #define I40IWQPC_KEEPALIVE_INTERVAL_MASK \
1145 (0xffUL << I40IWQPC_KEEPALIVE_INTERVAL_SHIFT)
1147 #define I40IWQPC_TIMESTAMP_RECENT_SHIFT 0
1148 #define I40IWQPC_TIMESTAMP_RECENT_MASK \
1149 (0xffffffffUL << I40IWQPC_TIMESTAMP_RECENT_SHIFT)
1151 #define I40IWQPC_TIMESTAMP_AGE_SHIFT 32
1152 #define I40IWQPC_TIMESTAMP_AGE_MASK \
1153 (0xffffffffULL << I40IWQPC_TIMESTAMP_AGE_SHIFT)
1155 #define I40IWQPC_SNDNXT_SHIFT 0
1156 #define I40IWQPC_SNDNXT_MASK (0xffffffffUL << I40IWQPC_SNDNXT_SHIFT)
1158 #define I40IWQPC_SNDWND_SHIFT 32
1159 #define I40IWQPC_SNDWND_MASK (0xffffffffULL << I40IWQPC_SNDWND_SHIFT)
1161 #define I40IWQPC_RCVNXT_SHIFT 0
1162 #define I40IWQPC_RCVNXT_MASK (0xffffffffUL << I40IWQPC_RCVNXT_SHIFT)
1164 #define I40IWQPC_RCVWND_SHIFT 32
1165 #define I40IWQPC_RCVWND_MASK (0xffffffffULL << I40IWQPC_RCVWND_SHIFT)
1167 #define I40IWQPC_SNDMAX_SHIFT 0
1168 #define I40IWQPC_SNDMAX_MASK (0xffffffffUL << I40IWQPC_SNDMAX_SHIFT)
1170 #define I40IWQPC_SNDUNA_SHIFT 32
1171 #define I40IWQPC_SNDUNA_MASK (0xffffffffULL << I40IWQPC_SNDUNA_SHIFT)
1173 #define I40IWQPC_SRTT_SHIFT 0
1174 #define I40IWQPC_SRTT_MASK (0xffffffffUL << I40IWQPC_SRTT_SHIFT)
1176 #define I40IWQPC_RTTVAR_SHIFT 32
1177 #define I40IWQPC_RTTVAR_MASK (0xffffffffULL << I40IWQPC_RTTVAR_SHIFT)
1179 #define I40IWQPC_SSTHRESH_SHIFT 0
1180 #define I40IWQPC_SSTHRESH_MASK (0xffffffffUL << I40IWQPC_SSTHRESH_SHIFT)
1182 #define I40IWQPC_CWND_SHIFT 32
1183 #define I40IWQPC_CWND_MASK (0xffffffffULL << I40IWQPC_CWND_SHIFT)
1185 #define I40IWQPC_SNDWL1_SHIFT 0
1186 #define I40IWQPC_SNDWL1_MASK (0xffffffffUL << I40IWQPC_SNDWL1_SHIFT)
1188 #define I40IWQPC_SNDWL2_SHIFT 32
1189 #define I40IWQPC_SNDWL2_MASK (0xffffffffULL << I40IWQPC_SNDWL2_SHIFT)
1191 #define I40IWQPC_ERR_RQ_IDX_SHIFT 32
1192 #define I40IWQPC_ERR_RQ_IDX_MASK (0x3fffULL << I40IWQPC_ERR_RQ_IDX_SHIFT)
1194 #define I40IWQPC_MAXSNDWND_SHIFT 0
1195 #define I40IWQPC_MAXSNDWND_MASK (0xffffffffUL << I40IWQPC_MAXSNDWND_SHIFT)
1197 #define I40IWQPC_REXMIT_THRESH_SHIFT 48
1198 #define I40IWQPC_REXMIT_THRESH_MASK (0x3fULL << I40IWQPC_REXMIT_THRESH_SHIFT)
1200 #define I40IWQPC_TXCQNUM_SHIFT 0
1201 #define I40IWQPC_TXCQNUM_MASK (0x1ffffUL << I40IWQPC_TXCQNUM_SHIFT)
1203 #define I40IWQPC_RXCQNUM_SHIFT 32
1204 #define I40IWQPC_RXCQNUM_MASK (0x1ffffULL << I40IWQPC_RXCQNUM_SHIFT)
1206 #define I40IWQPC_Q2ADDR_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1207 #define I40IWQPC_Q2ADDR_MASK I40IW_CQPHC_QPCTX_MASK
1209 #define I40IWQPC_LASTBYTESENT_SHIFT 0
1210 #define I40IWQPC_LASTBYTESENT_MASK (0xffUL << I40IWQPC_LASTBYTESENT_SHIFT)
1212 #define I40IWQPC_SRQID_SHIFT 32
1213 #define I40IWQPC_SRQID_MASK (0xffULL << I40IWQPC_SRQID_SHIFT)
1215 #define I40IWQPC_ORDSIZE_SHIFT 0
1216 #define I40IWQPC_ORDSIZE_MASK (0x7fUL << I40IWQPC_ORDSIZE_SHIFT)
1218 #define I40IWQPC_IRDSIZE_SHIFT 16
1219 #define I40IWQPC_IRDSIZE_MASK (0x3UL << I40IWQPC_IRDSIZE_SHIFT)
1221 #define I40IWQPC_WRRDRSPOK_SHIFT 20
1222 #define I40IWQPC_WRRDRSPOK_MASK (1UL << I40IWQPC_WRRDRSPOK_SHIFT)
1224 #define I40IWQPC_RDOK_SHIFT 21
1225 #define I40IWQPC_RDOK_MASK (1UL << I40IWQPC_RDOK_SHIFT)
1227 #define I40IWQPC_SNDMARKERS_SHIFT 22
1228 #define I40IWQPC_SNDMARKERS_MASK (1UL << I40IWQPC_SNDMARKERS_SHIFT)
1230 #define I40IWQPC_BINDEN_SHIFT 23
1231 #define I40IWQPC_BINDEN_MASK (1UL << I40IWQPC_BINDEN_SHIFT)
1233 #define I40IWQPC_FASTREGEN_SHIFT 24
1234 #define I40IWQPC_FASTREGEN_MASK (1UL << I40IWQPC_FASTREGEN_SHIFT)
1236 #define I40IWQPC_PRIVEN_SHIFT 25
1237 #define I40IWQPC_PRIVEN_MASK (1UL << I40IWQPC_PRIVEN_SHIFT)
1239 #define I40IWQPC_LSMMPRESENT_SHIFT 26
1240 #define I40IWQPC_LSMMPRESENT_MASK (1UL << I40IWQPC_LSMMPRESENT_SHIFT)
1242 #define I40IWQPC_ADJUSTFORLSMM_SHIFT 27
1243 #define I40IWQPC_ADJUSTFORLSMM_MASK (1UL << I40IWQPC_ADJUSTFORLSMM_SHIFT)
1245 #define I40IWQPC_IWARPMODE_SHIFT 28
1246 #define I40IWQPC_IWARPMODE_MASK (1UL << I40IWQPC_IWARPMODE_SHIFT)
1248 #define I40IWQPC_RCVMARKERS_SHIFT 29
1249 #define I40IWQPC_RCVMARKERS_MASK (1UL << I40IWQPC_RCVMARKERS_SHIFT)
1251 #define I40IWQPC_ALIGNHDRS_SHIFT 30
1252 #define I40IWQPC_ALIGNHDRS_MASK (1UL << I40IWQPC_ALIGNHDRS_SHIFT)
1254 #define I40IWQPC_RCVNOMPACRC_SHIFT 31
1255 #define I40IWQPC_RCVNOMPACRC_MASK (1UL << I40IWQPC_RCVNOMPACRC_SHIFT)
1257 #define I40IWQPC_RCVMARKOFFSET_SHIFT 33
1258 #define I40IWQPC_RCVMARKOFFSET_MASK (0x1ffULL << I40IWQPC_RCVMARKOFFSET_SHIFT)
1260 #define I40IWQPC_SNDMARKOFFSET_SHIFT 48
1261 #define I40IWQPC_SNDMARKOFFSET_MASK (0x1ffULL << I40IWQPC_SNDMARKOFFSET_SHIFT)
1263 #define I40IWQPC_QPCOMPCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1264 #define I40IWQPC_QPCOMPCTX_MASK I40IW_CQPHC_QPCTX_MASK
1266 #define I40IWQPC_SQTPHVAL_SHIFT 0
1267 #define I40IWQPC_SQTPHVAL_MASK (0xffUL << I40IWQPC_SQTPHVAL_SHIFT)
1269 #define I40IWQPC_RQTPHVAL_SHIFT 8
1270 #define I40IWQPC_RQTPHVAL_MASK (0xffUL << I40IWQPC_RQTPHVAL_SHIFT)
1272 #define I40IWQPC_QSHANDLE_SHIFT 16
1273 #define I40IWQPC_QSHANDLE_MASK (0x3ffUL << I40IWQPC_QSHANDLE_SHIFT)
1275 #define I40IWQPC_EXCEPTION_LAN_QUEUE_SHIFT 32
1276 #define I40IWQPC_EXCEPTION_LAN_QUEUE_MASK (0xfffULL << \
1277 I40IWQPC_EXCEPTION_LAN_QUEUE_SHIFT)
1279 #define I40IWQPC_LOCAL_IPADDR3_SHIFT 0
1280 #define I40IWQPC_LOCAL_IPADDR3_MASK \
1281 (0xffffffffUL << I40IWQPC_LOCAL_IPADDR3_SHIFT)
1283 #define I40IWQPC_LOCAL_IPADDR2_SHIFT 32
1284 #define I40IWQPC_LOCAL_IPADDR2_MASK \
1285 (0xffffffffULL << I40IWQPC_LOCAL_IPADDR2_SHIFT)
1287 #define I40IWQPC_LOCAL_IPADDR1_SHIFT 0
1288 #define I40IWQPC_LOCAL_IPADDR1_MASK \
1289 (0xffffffffUL << I40IWQPC_LOCAL_IPADDR1_SHIFT)
1291 #define I40IWQPC_LOCAL_IPADDR0_SHIFT 32
1292 #define I40IWQPC_LOCAL_IPADDR0_MASK \
1293 (0xffffffffULL << I40IWQPC_LOCAL_IPADDR0_SHIFT)
1295 /* wqe size considering 32 bytes per wqe*/
1296 #define I40IWQP_SW_MIN_WQSIZE 4 /* 128 bytes */
1297 #define I40IWQP_SW_MAX_WQSIZE 2048 /* 2048 bytes */
1299 #define I40IWQP_OP_RDMA_WRITE 0
1300 #define I40IWQP_OP_RDMA_READ 1
1301 #define I40IWQP_OP_RDMA_SEND 3
1302 #define I40IWQP_OP_RDMA_SEND_INV 4
1303 #define I40IWQP_OP_RDMA_SEND_SOL_EVENT 5
1304 #define I40IWQP_OP_RDMA_SEND_SOL_EVENT_INV 6
1305 #define I40IWQP_OP_BIND_MW 8
1306 #define I40IWQP_OP_FAST_REGISTER 9
1307 #define I40IWQP_OP_LOCAL_INVALIDATE 10
1308 #define I40IWQP_OP_RDMA_READ_LOC_INV 11
1309 #define I40IWQP_OP_NOP 12
1311 #define I40IW_RSVD_SHIFT 41
1312 #define I40IW_RSVD_MASK (0x7fffULL << I40IW_RSVD_SHIFT)
1314 /* iwarp QP SQ WQE common fields */
1315 #define I40IWQPSQ_OPCODE_SHIFT 32
1316 #define I40IWQPSQ_OPCODE_MASK (0x3fULL << I40IWQPSQ_OPCODE_SHIFT)
1318 #define I40IWQPSQ_ADDFRAGCNT_SHIFT 38
1319 #define I40IWQPSQ_ADDFRAGCNT_MASK (0x7ULL << I40IWQPSQ_ADDFRAGCNT_SHIFT)
1321 #define I40IWQPSQ_PUSHWQE_SHIFT 56
1322 #define I40IWQPSQ_PUSHWQE_MASK (1ULL << I40IWQPSQ_PUSHWQE_SHIFT)
1324 #define I40IWQPSQ_STREAMMODE_SHIFT 58
1325 #define I40IWQPSQ_STREAMMODE_MASK (1ULL << I40IWQPSQ_STREAMMODE_SHIFT)
1327 #define I40IWQPSQ_WAITFORRCVPDU_SHIFT 59
1328 #define I40IWQPSQ_WAITFORRCVPDU_MASK (1ULL << I40IWQPSQ_WAITFORRCVPDU_SHIFT)
1330 #define I40IWQPSQ_READFENCE_SHIFT 60
1331 #define I40IWQPSQ_READFENCE_MASK (1ULL << I40IWQPSQ_READFENCE_SHIFT)
1333 #define I40IWQPSQ_LOCALFENCE_SHIFT 61
1334 #define I40IWQPSQ_LOCALFENCE_MASK (1ULL << I40IWQPSQ_LOCALFENCE_SHIFT)
1336 #define I40IWQPSQ_SIGCOMPL_SHIFT 62
1337 #define I40IWQPSQ_SIGCOMPL_MASK (1ULL << I40IWQPSQ_SIGCOMPL_SHIFT)
1339 #define I40IWQPSQ_VALID_SHIFT 63
1340 #define I40IWQPSQ_VALID_MASK (1ULL << I40IWQPSQ_VALID_SHIFT)
1342 #define I40IWQPSQ_FRAG_TO_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1343 #define I40IWQPSQ_FRAG_TO_MASK I40IW_CQPHC_QPCTX_MASK
1345 #define I40IWQPSQ_FRAG_LEN_SHIFT 0
1346 #define I40IWQPSQ_FRAG_LEN_MASK (0xffffffffUL << I40IWQPSQ_FRAG_LEN_SHIFT)
1348 #define I40IWQPSQ_FRAG_STAG_SHIFT 32
1349 #define I40IWQPSQ_FRAG_STAG_MASK (0xffffffffULL << I40IWQPSQ_FRAG_STAG_SHIFT)
1351 #define I40IWQPSQ_REMSTAGINV_SHIFT 0
1352 #define I40IWQPSQ_REMSTAGINV_MASK (0xffffffffUL << I40IWQPSQ_REMSTAGINV_SHIFT)
1354 #define I40IWQPSQ_INLINEDATAFLAG_SHIFT 57
1355 #define I40IWQPSQ_INLINEDATAFLAG_MASK (1ULL << I40IWQPSQ_INLINEDATAFLAG_SHIFT)
1357 #define I40IWQPSQ_INLINEDATALEN_SHIFT 48
1358 #define I40IWQPSQ_INLINEDATALEN_MASK \
1359 (0x7fULL << I40IWQPSQ_INLINEDATALEN_SHIFT)
1361 /* iwarp send with push mode */
1362 #define I40IWQPSQ_WQDESCIDX_SHIFT 0
1363 #define I40IWQPSQ_WQDESCIDX_MASK (0x3fffUL << I40IWQPSQ_WQDESCIDX_SHIFT)
1366 #define I40IWQPSQ_REMSTAG_SHIFT 0
1367 #define I40IWQPSQ_REMSTAG_MASK (0xffffffffUL << I40IWQPSQ_REMSTAG_SHIFT)
1369 #define I40IWQPSQ_REMTO_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1370 #define I40IWQPSQ_REMTO_MASK I40IW_CQPHC_QPCTX_MASK
1373 #define I40IWQPSQ_STAGRIGHTS_SHIFT 48
1374 #define I40IWQPSQ_STAGRIGHTS_MASK (0x1fULL << I40IWQPSQ_STAGRIGHTS_SHIFT)
1376 #define I40IWQPSQ_VABASEDTO_SHIFT 53
1377 #define I40IWQPSQ_VABASEDTO_MASK (1ULL << I40IWQPSQ_VABASEDTO_SHIFT)
1379 #define I40IWQPSQ_MWLEN_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1380 #define I40IWQPSQ_MWLEN_MASK I40IW_CQPHC_QPCTX_MASK
1382 #define I40IWQPSQ_PARENTMRSTAG_SHIFT 0
1383 #define I40IWQPSQ_PARENTMRSTAG_MASK \
1384 (0xffffffffUL << I40IWQPSQ_PARENTMRSTAG_SHIFT)
1386 #define I40IWQPSQ_MWSTAG_SHIFT 32
1387 #define I40IWQPSQ_MWSTAG_MASK (0xffffffffULL << I40IWQPSQ_MWSTAG_SHIFT)
1389 #define I40IWQPSQ_BASEVA_TO_FBO_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1390 #define I40IWQPSQ_BASEVA_TO_FBO_MASK I40IW_CQPHC_QPCTX_MASK
1392 /* Local Invalidate */
1393 #define I40IWQPSQ_LOCSTAG_SHIFT 32
1394 #define I40IWQPSQ_LOCSTAG_MASK (0xffffffffULL << I40IWQPSQ_LOCSTAG_SHIFT)
1397 #define I40IWQPSQ_STAGKEY_SHIFT 0
1398 #define I40IWQPSQ_STAGKEY_MASK (0xffUL << I40IWQPSQ_STAGKEY_SHIFT)
1400 #define I40IWQPSQ_STAGINDEX_SHIFT 8
1401 #define I40IWQPSQ_STAGINDEX_MASK (0xffffffUL << I40IWQPSQ_STAGINDEX_SHIFT)
1403 #define I40IWQPSQ_COPYHOSTPBLS_SHIFT 43
1404 #define I40IWQPSQ_COPYHOSTPBLS_MASK (1ULL << I40IWQPSQ_COPYHOSTPBLS_SHIFT)
1406 #define I40IWQPSQ_LPBLSIZE_SHIFT 44
1407 #define I40IWQPSQ_LPBLSIZE_MASK (3ULL << I40IWQPSQ_LPBLSIZE_SHIFT)
1409 #define I40IWQPSQ_HPAGESIZE_SHIFT 46
1410 #define I40IWQPSQ_HPAGESIZE_MASK (3ULL << I40IWQPSQ_HPAGESIZE_SHIFT)
1412 #define I40IWQPSQ_STAGLEN_SHIFT 0
1413 #define I40IWQPSQ_STAGLEN_MASK (0x1ffffffffffULL << I40IWQPSQ_STAGLEN_SHIFT)
1415 #define I40IWQPSQ_FIRSTPMPBLIDXLO_SHIFT 48
1416 #define I40IWQPSQ_FIRSTPMPBLIDXLO_MASK \
1417 (0xffffULL << I40IWQPSQ_FIRSTPMPBLIDXLO_SHIFT)
1419 #define I40IWQPSQ_FIRSTPMPBLIDXHI_SHIFT 0
1420 #define I40IWQPSQ_FIRSTPMPBLIDXHI_MASK \
1421 (0xfffUL << I40IWQPSQ_FIRSTPMPBLIDXHI_SHIFT)
1423 #define I40IWQPSQ_PBLADDR_SHIFT 12
1424 #define I40IWQPSQ_PBLADDR_MASK (0xfffffffffffffULL << I40IWQPSQ_PBLADDR_SHIFT)
1426 /* iwarp QP RQ WQE common fields */
1427 #define I40IWQPRQ_ADDFRAGCNT_SHIFT I40IWQPSQ_ADDFRAGCNT_SHIFT
1428 #define I40IWQPRQ_ADDFRAGCNT_MASK I40IWQPSQ_ADDFRAGCNT_MASK
1430 #define I40IWQPRQ_VALID_SHIFT I40IWQPSQ_VALID_SHIFT
1431 #define I40IWQPRQ_VALID_MASK I40IWQPSQ_VALID_MASK
1433 #define I40IWQPRQ_COMPLCTX_SHIFT I40IW_CQPHC_QPCTX_SHIFT
1434 #define I40IWQPRQ_COMPLCTX_MASK I40IW_CQPHC_QPCTX_MASK
1436 #define I40IWQPRQ_FRAG_LEN_SHIFT I40IWQPSQ_FRAG_LEN_SHIFT
1437 #define I40IWQPRQ_FRAG_LEN_MASK I40IWQPSQ_FRAG_LEN_MASK
1439 #define I40IWQPRQ_STAG_SHIFT I40IWQPSQ_FRAG_STAG_SHIFT
1440 #define I40IWQPRQ_STAG_MASK I40IWQPSQ_FRAG_STAG_MASK
1442 #define I40IWQPRQ_TO_SHIFT I40IWQPSQ_FRAG_TO_SHIFT
1443 #define I40IWQPRQ_TO_MASK I40IWQPSQ_FRAG_TO_MASK
1445 /* Query FPM CQP buf */
1446 #define I40IW_QUERY_FPM_MAX_QPS_SHIFT 0
1447 #define I40IW_QUERY_FPM_MAX_QPS_MASK \
1448 (0x7ffffUL << I40IW_QUERY_FPM_MAX_QPS_SHIFT)
1450 #define I40IW_QUERY_FPM_MAX_CQS_SHIFT 0
1451 #define I40IW_QUERY_FPM_MAX_CQS_MASK \
1452 (0x3ffffUL << I40IW_QUERY_FPM_MAX_CQS_SHIFT)
1454 #define I40IW_QUERY_FPM_FIRST_PE_SD_INDEX_SHIFT 0
1455 #define I40IW_QUERY_FPM_FIRST_PE_SD_INDEX_MASK \
1456 (0x3fffUL << I40IW_QUERY_FPM_FIRST_PE_SD_INDEX_SHIFT)
1458 #define I40IW_QUERY_FPM_MAX_PE_SDS_SHIFT 32
1459 #define I40IW_QUERY_FPM_MAX_PE_SDS_MASK \
1460 (0x3fffULL << I40IW_QUERY_FPM_MAX_PE_SDS_SHIFT)
1462 #define I40IW_QUERY_FPM_MAX_QPS_SHIFT 0
1463 #define I40IW_QUERY_FPM_MAX_QPS_MASK \
1464 (0x7ffffUL << I40IW_QUERY_FPM_MAX_QPS_SHIFT)
1466 #define I40IW_QUERY_FPM_MAX_CQS_SHIFT 0
1467 #define I40IW_QUERY_FPM_MAX_CQS_MASK \
1468 (0x3ffffUL << I40IW_QUERY_FPM_MAX_CQS_SHIFT)
1470 #define I40IW_QUERY_FPM_MAX_CEQS_SHIFT 0
1471 #define I40IW_QUERY_FPM_MAX_CEQS_MASK \
1472 (0xffUL << I40IW_QUERY_FPM_MAX_CEQS_SHIFT)
1474 #define I40IW_QUERY_FPM_XFBLOCKSIZE_SHIFT 32
1475 #define I40IW_QUERY_FPM_XFBLOCKSIZE_MASK \
1476 (0xffffffffULL << I40IW_QUERY_FPM_XFBLOCKSIZE_SHIFT)
1478 #define I40IW_QUERY_FPM_Q1BLOCKSIZE_SHIFT 32
1479 #define I40IW_QUERY_FPM_Q1BLOCKSIZE_MASK \
1480 (0xffffffffULL << I40IW_QUERY_FPM_Q1BLOCKSIZE_SHIFT)
1482 #define I40IW_QUERY_FPM_HTMULTIPLIER_SHIFT 16
1483 #define I40IW_QUERY_FPM_HTMULTIPLIER_MASK \
1484 (0xfUL << I40IW_QUERY_FPM_HTMULTIPLIER_SHIFT)
1486 #define I40IW_QUERY_FPM_TIMERBUCKET_SHIFT 32
1487 #define I40IW_QUERY_FPM_TIMERBUCKET_MASK \
1488 (0xffFFULL << I40IW_QUERY_FPM_TIMERBUCKET_SHIFT)
1490 /* Static HMC pages allocated buf */
1491 #define I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID_SHIFT 0
1492 #define I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID_MASK \
1493 (0x3fUL << I40IW_SHMC_PAGE_ALLOCATED_HMC_FN_ID_SHIFT)
1495 #define I40IW_HW_PAGE_SIZE 4096
1496 #define I40IW_DONE_COUNT 1000
1497 #define I40IW_SLEEP_COUNT 10
1500 I40IW_QUEUES_ALIGNMENT_MASK = (128 - 1),
1501 I40IW_AEQ_ALIGNMENT_MASK = (256 - 1),
1502 I40IW_Q2_ALIGNMENT_MASK = (256 - 1),
1503 I40IW_CEQ_ALIGNMENT_MASK = (256 - 1),
1504 I40IW_CQ0_ALIGNMENT_MASK = (256 - 1),
1505 I40IW_HOST_CTX_ALIGNMENT_MASK = (4 - 1),
1506 I40IW_SHADOWAREA_MASK = (128 - 1),
1507 I40IW_FPM_QUERY_BUF_ALIGNMENT_MASK = 0,
1508 I40IW_FPM_COMMIT_BUF_ALIGNMENT_MASK = 0
1511 enum i40iw_alignment {
1512 I40IW_CQP_ALIGNMENT = 0x200,
1513 I40IW_AEQ_ALIGNMENT = 0x100,
1514 I40IW_CEQ_ALIGNMENT = 0x100,
1515 I40IW_CQ0_ALIGNMENT = 0x100,
1516 I40IW_SD_BUF_ALIGNMENT = 0x100
1519 #define I40IW_WQE_SIZE_64 64
1521 #define I40IW_QP_WQE_MIN_SIZE 32
1522 #define I40IW_QP_WQE_MAX_SIZE 128
1524 #define I40IW_CQE_QTYPE_RQ 0
1525 #define I40IW_CQE_QTYPE_SQ 1
1527 #define I40IW_RING_INIT(_ring, _size) \
1531 (_ring).size = (_size); \
1533 #define I40IW_RING_GETSIZE(_ring) ((_ring).size)
1534 #define I40IW_RING_GETCURRENT_HEAD(_ring) ((_ring).head)
1535 #define I40IW_RING_GETCURRENT_TAIL(_ring) ((_ring).tail)
1537 #define I40IW_RING_MOVE_HEAD(_ring, _retcode) \
1539 register u32 size; \
1540 size = (_ring).size; \
1541 if (!I40IW_RING_FULL_ERR(_ring)) { \
1542 (_ring).head = ((_ring).head + 1) % size; \
1545 (_retcode) = I40IW_ERR_RING_FULL; \
1549 #define I40IW_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \
1551 register u32 size; \
1552 size = (_ring).size; \
1553 if ((I40IW_RING_WORK_AVAILABLE(_ring) + (_count)) < size) { \
1554 (_ring).head = ((_ring).head + (_count)) % size; \
1557 (_retcode) = I40IW_ERR_RING_FULL; \
1561 #define I40IW_RING_MOVE_TAIL(_ring) \
1562 (_ring).tail = ((_ring).tail + 1) % (_ring).size
1564 #define I40IW_RING_MOVE_HEAD_NOCHECK(_ring) \
1565 (_ring).head = ((_ring).head + 1) % (_ring).size
1567 #define I40IW_RING_MOVE_TAIL_BY_COUNT(_ring, _count) \
1568 (_ring).tail = ((_ring).tail + (_count)) % (_ring).size
1570 #define I40IW_RING_SET_TAIL(_ring, _pos) \
1571 (_ring).tail = (_pos) % (_ring).size
1573 #define I40IW_RING_FULL_ERR(_ring) \
1575 (I40IW_RING_WORK_AVAILABLE(_ring) == ((_ring).size - 1)) \
1578 #define I40IW_ERR_RING_FULL2(_ring) \
1580 (I40IW_RING_WORK_AVAILABLE(_ring) == ((_ring).size - 2)) \
1583 #define I40IW_ERR_RING_FULL3(_ring) \
1585 (I40IW_RING_WORK_AVAILABLE(_ring) == ((_ring).size - 3)) \
1588 #define I40IW_RING_MORE_WORK(_ring) \
1590 (I40IW_RING_WORK_AVAILABLE(_ring) != 0) \
1593 #define I40IW_RING_WORK_AVAILABLE(_ring) \
1595 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1598 #define I40IW_RING_GET_WQES_AVAILABLE(_ring) \
1600 ((_ring).size - I40IW_RING_WORK_AVAILABLE(_ring) - 1) \
1603 #define I40IW_ATOMIC_RING_MOVE_HEAD(_ring, index, _retcode) \
1605 index = I40IW_RING_GETCURRENT_HEAD(_ring); \
1606 I40IW_RING_MOVE_HEAD(_ring, _retcode); \
1609 /* Async Events codes */
1610 #define I40IW_AE_AMP_UNALLOCATED_STAG 0x0102
1611 #define I40IW_AE_AMP_INVALID_STAG 0x0103
1612 #define I40IW_AE_AMP_BAD_QP 0x0104
1613 #define I40IW_AE_AMP_BAD_PD 0x0105
1614 #define I40IW_AE_AMP_BAD_STAG_KEY 0x0106
1615 #define I40IW_AE_AMP_BAD_STAG_INDEX 0x0107
1616 #define I40IW_AE_AMP_BOUNDS_VIOLATION 0x0108
1617 #define I40IW_AE_AMP_RIGHTS_VIOLATION 0x0109
1618 #define I40IW_AE_AMP_TO_WRAP 0x010a
1619 #define I40IW_AE_AMP_FASTREG_SHARED 0x010b
1620 #define I40IW_AE_AMP_FASTREG_VALID_STAG 0x010c
1621 #define I40IW_AE_AMP_FASTREG_MW_STAG 0x010d
1622 #define I40IW_AE_AMP_FASTREG_INVALID_RIGHTS 0x010e
1623 #define I40IW_AE_AMP_FASTREG_PBL_TABLE_OVERFLOW 0x010f
1624 #define I40IW_AE_AMP_FASTREG_INVALID_LENGTH 0x0110
1625 #define I40IW_AE_AMP_INVALIDATE_SHARED 0x0111
1626 #define I40IW_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS 0x0112
1627 #define I40IW_AE_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS 0x0113
1628 #define I40IW_AE_AMP_MWBIND_VALID_STAG 0x0114
1629 #define I40IW_AE_AMP_MWBIND_OF_MR_STAG 0x0115
1630 #define I40IW_AE_AMP_MWBIND_TO_ZERO_BASED_STAG 0x0116
1631 #define I40IW_AE_AMP_MWBIND_TO_MW_STAG 0x0117
1632 #define I40IW_AE_AMP_MWBIND_INVALID_RIGHTS 0x0118
1633 #define I40IW_AE_AMP_MWBIND_INVALID_BOUNDS 0x0119
1634 #define I40IW_AE_AMP_MWBIND_TO_INVALID_PARENT 0x011a
1635 #define I40IW_AE_AMP_MWBIND_BIND_DISABLED 0x011b
1636 #define I40IW_AE_AMP_WQE_INVALID_PARAMETER 0x0130
1637 #define I40IW_AE_BAD_CLOSE 0x0201
1638 #define I40IW_AE_RDMAP_ROE_BAD_LLP_CLOSE 0x0202
1639 #define I40IW_AE_CQ_OPERATION_ERROR 0x0203
1640 #define I40IW_AE_PRIV_OPERATION_DENIED 0x011c
1641 #define I40IW_AE_RDMA_READ_WHILE_ORD_ZERO 0x0205
1642 #define I40IW_AE_STAG_ZERO_INVALID 0x0206
1643 #define I40IW_AE_IB_RREQ_AND_Q1_FULL 0x0207
1644 #define I40IW_AE_SRQ_LIMIT 0x0209
1645 #define I40IW_AE_WQE_UNEXPECTED_OPCODE 0x020a
1646 #define I40IW_AE_WQE_INVALID_PARAMETER 0x020b
1647 #define I40IW_AE_WQE_LSMM_TOO_LONG 0x0220
1648 #define I40IW_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301
1649 #define I40IW_AE_DDP_INVALID_MSN_RANGE_IS_NOT_VALID 0x0302
1650 #define I40IW_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303
1651 #define I40IW_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304
1652 #define I40IW_AE_DDP_UBE_INVALID_MO 0x0305
1653 #define I40IW_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE 0x0306
1654 #define I40IW_AE_DDP_UBE_INVALID_QN 0x0307
1655 #define I40IW_AE_DDP_NO_L_BIT 0x0308
1656 #define I40IW_AE_RDMAP_ROE_INVALID_RDMAP_VERSION 0x0311
1657 #define I40IW_AE_RDMAP_ROE_UNEXPECTED_OPCODE 0x0312
1658 #define I40IW_AE_ROE_INVALID_RDMA_READ_REQUEST 0x0313
1659 #define I40IW_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP 0x0314
1660 #define I40IW_AE_INVALID_ARP_ENTRY 0x0401
1661 #define I40IW_AE_INVALID_TCP_OPTION_RCVD 0x0402
1662 #define I40IW_AE_STALE_ARP_ENTRY 0x0403
1663 #define I40IW_AE_INVALID_WQE_LENGTH 0x0404
1664 #define I40IW_AE_INVALID_MAC_ENTRY 0x0405
1665 #define I40IW_AE_LLP_CLOSE_COMPLETE 0x0501
1666 #define I40IW_AE_LLP_CONNECTION_RESET 0x0502
1667 #define I40IW_AE_LLP_FIN_RECEIVED 0x0503
1668 #define I40IW_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH 0x0504
1669 #define I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR 0x0505
1670 #define I40IW_AE_LLP_SEGMENT_TOO_LARGE 0x0506
1671 #define I40IW_AE_LLP_SEGMENT_TOO_SMALL 0x0507
1672 #define I40IW_AE_LLP_SYN_RECEIVED 0x0508
1673 #define I40IW_AE_LLP_TERMINATE_RECEIVED 0x0509
1674 #define I40IW_AE_LLP_TOO_MANY_RETRIES 0x050a
1675 #define I40IW_AE_LLP_TOO_MANY_KEEPALIVE_RETRIES 0x050b
1676 #define I40IW_AE_LLP_DOUBT_REACHABILITY 0x050c
1677 #define I40IW_AE_LLP_RX_VLAN_MISMATCH 0x050d
1678 #define I40IW_AE_RESOURCE_EXHAUSTION 0x0520
1679 #define I40IW_AE_RESET_SENT 0x0601
1680 #define I40IW_AE_TERMINATE_SENT 0x0602
1681 #define I40IW_AE_RESET_NOT_SENT 0x0603
1682 #define I40IW_AE_LCE_QP_CATASTROPHIC 0x0700
1683 #define I40IW_AE_LCE_FUNCTION_CATASTROPHIC 0x0701
1684 #define I40IW_AE_LCE_CQ_CATASTROPHIC 0x0702
1685 #define I40IW_AE_UDA_XMIT_FRAG_SEQ 0x0800
1686 #define I40IW_AE_UDA_XMIT_DGRAM_TOO_LONG 0x0801
1687 #define I40IW_AE_UDA_XMIT_IPADDR_MISMATCH 0x0802
1688 #define I40IW_AE_QP_SUSPEND_COMPLETE 0x0900
1690 #define OP_DELETE_LOCAL_MAC_IPADDR_ENTRY 1
1691 #define OP_CEQ_DESTROY 2
1692 #define OP_AEQ_DESTROY 3
1693 #define OP_DELETE_ARP_CACHE_ENTRY 4
1694 #define OP_MANAGE_APBVT_ENTRY 5
1695 #define OP_CEQ_CREATE 6
1696 #define OP_AEQ_CREATE 7
1697 #define OP_ALLOC_LOCAL_MAC_IPADDR_ENTRY 8
1698 #define OP_ADD_LOCAL_MAC_IPADDR_ENTRY 9
1699 #define OP_MANAGE_QHASH_TABLE_ENTRY 10
1700 #define OP_QP_MODIFY 11
1701 #define OP_QP_UPLOAD_CONTEXT 12
1702 #define OP_CQ_CREATE 13
1703 #define OP_CQ_DESTROY 14
1704 #define OP_QP_CREATE 15
1705 #define OP_QP_DESTROY 16
1706 #define OP_ALLOC_STAG 17
1707 #define OP_MR_REG_NON_SHARED 18
1708 #define OP_DEALLOC_STAG 19
1709 #define OP_MW_ALLOC 20
1710 #define OP_QP_FLUSH_WQES 21
1711 #define OP_ADD_ARP_CACHE_ENTRY 22
1712 #define OP_MANAGE_PUSH_PAGE 23
1713 #define OP_UPDATE_PE_SDS 24
1714 #define OP_MANAGE_HMC_PM_FUNC_TABLE 25
1715 #define OP_SUSPEND 26
1716 #define OP_RESUME 27
1717 #define OP_MANAGE_VF_PBLE_BP 28
1718 #define OP_QUERY_FPM_VALUES 29
1719 #define OP_COMMIT_FPM_VALUES 30
1720 #define OP_SIZE_CQP_STAT_ARRAY 31