70a6b41980fa873968adf59ce534e1610e9535c1
[karo-tx-linux.git] / drivers / infiniband / hw / i40iw / i40iw_uk.c
1 /*******************************************************************************
2 *
3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses.  You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenFabrics.org BSD license below:
10 *
11 *   Redistribution and use in source and binary forms, with or
12 *   without modification, are permitted provided that the following
13 *   conditions are met:
14 *
15 *    - Redistributions of source code must retain the above
16 *       copyright notice, this list of conditions and the following
17 *       disclaimer.
18 *
19 *    - Redistributions in binary form must reproduce the above
20 *       copyright notice, this list of conditions and the following
21 *       disclaimer in the documentation and/or other materials
22 *       provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 *
33 *******************************************************************************/
34
35 #include "i40iw_osdep.h"
36 #include "i40iw_status.h"
37 #include "i40iw_d.h"
38 #include "i40iw_user.h"
39 #include "i40iw_register.h"
40
41 static u32 nop_signature = 0x55550000;
42
43 /**
44  * i40iw_nop_1 - insert a nop wqe and move head. no post work
45  * @qp: hw qp ptr
46  */
47 static enum i40iw_status_code i40iw_nop_1(struct i40iw_qp_uk *qp)
48 {
49         u64 header, *wqe;
50         u64 *wqe_0 = NULL;
51         u32 wqe_idx, peek_head;
52         bool signaled = false;
53
54         if (!qp->sq_ring.head)
55                 return I40IW_ERR_PARAM;
56
57         wqe_idx = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
58         wqe = qp->sq_base[wqe_idx].elem;
59
60         qp->sq_wrtrk_array[wqe_idx].wqe_size = I40IW_QP_WQE_MIN_SIZE;
61
62         peek_head = (qp->sq_ring.head + 1) % qp->sq_ring.size;
63         wqe_0 = qp->sq_base[peek_head].elem;
64         if (peek_head)
65                 wqe_0[3] = LS_64(!qp->swqe_polarity, I40IWQPSQ_VALID);
66         else
67                 wqe_0[3] = LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
68
69         set_64bit_val(wqe, 0, 0);
70         set_64bit_val(wqe, 8, 0);
71         set_64bit_val(wqe, 16, 0);
72
73         header = LS_64(I40IWQP_OP_NOP, I40IWQPSQ_OPCODE) |
74             LS_64(signaled, I40IWQPSQ_SIGCOMPL) |
75             LS_64(qp->swqe_polarity, I40IWQPSQ_VALID) | nop_signature++;
76
77         wmb();  /* Memory barrier to ensure data is written before valid bit is set */
78
79         set_64bit_val(wqe, 24, header);
80         return 0;
81 }
82
83 /**
84  * i40iw_qp_post_wr - post wr to hrdware
85  * @qp: hw qp ptr
86  */
87 void i40iw_qp_post_wr(struct i40iw_qp_uk *qp)
88 {
89         u64 temp;
90         u32 hw_sq_tail;
91         u32 sw_sq_head;
92
93         mb(); /* valid bit is written and loads completed before reading shadow */
94
95         /* read the doorbell shadow area */
96         get_64bit_val(qp->shadow_area, 0, &temp);
97
98         hw_sq_tail = (u32)RS_64(temp, I40IW_QP_DBSA_HW_SQ_TAIL);
99         sw_sq_head = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
100         if (sw_sq_head != hw_sq_tail) {
101                 if (sw_sq_head > qp->initial_ring.head) {
102                         if ((hw_sq_tail >= qp->initial_ring.head) &&
103                             (hw_sq_tail < sw_sq_head)) {
104                                 writel(qp->qp_id, qp->wqe_alloc_reg);
105                         }
106                 } else if (sw_sq_head != qp->initial_ring.head) {
107                         if ((hw_sq_tail >= qp->initial_ring.head) ||
108                             (hw_sq_tail < sw_sq_head)) {
109                                 writel(qp->qp_id, qp->wqe_alloc_reg);
110                         }
111                 }
112         }
113
114         qp->initial_ring.head = qp->sq_ring.head;
115 }
116
117 /**
118  * i40iw_qp_ring_push_db -  ring qp doorbell
119  * @qp: hw qp ptr
120  * @wqe_idx: wqe index
121  */
122 static void i40iw_qp_ring_push_db(struct i40iw_qp_uk *qp, u32 wqe_idx)
123 {
124         set_32bit_val(qp->push_db, 0, LS_32((wqe_idx >> 2), I40E_PFPE_WQEALLOC_WQE_DESC_INDEX) | qp->qp_id);
125         qp->initial_ring.head = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
126 }
127
128 /**
129  * i40iw_qp_get_next_send_wqe - return next wqe ptr
130  * @qp: hw qp ptr
131  * @wqe_idx: return wqe index
132  * @wqe_size: size of sq wqe
133  */
134 u64 *i40iw_qp_get_next_send_wqe(struct i40iw_qp_uk *qp,
135                                 u32 *wqe_idx,
136                                 u8 wqe_size,
137                                 u32 total_size,
138                                 u64 wr_id
139                                 )
140 {
141         u64 *wqe = NULL;
142         u64 wqe_ptr;
143         u32 peek_head = 0;
144         u16 offset;
145         enum i40iw_status_code ret_code = 0;
146         u8 nop_wqe_cnt = 0, i;
147         u64 *wqe_0 = NULL;
148
149         *wqe_idx = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
150
151         if (!*wqe_idx)
152                 qp->swqe_polarity = !qp->swqe_polarity;
153         wqe_ptr = (uintptr_t)qp->sq_base[*wqe_idx].elem;
154         offset = (u16)(wqe_ptr) & 0x7F;
155         if ((offset + wqe_size) > I40IW_QP_WQE_MAX_SIZE) {
156                 nop_wqe_cnt = (u8)(I40IW_QP_WQE_MAX_SIZE - offset) / I40IW_QP_WQE_MIN_SIZE;
157                 for (i = 0; i < nop_wqe_cnt; i++) {
158                         i40iw_nop_1(qp);
159                         I40IW_RING_MOVE_HEAD(qp->sq_ring, ret_code);
160                         if (ret_code)
161                                 return NULL;
162                 }
163
164                 *wqe_idx = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
165                 if (!*wqe_idx)
166                         qp->swqe_polarity = !qp->swqe_polarity;
167         }
168
169         if (((*wqe_idx & 3) == 1) && (wqe_size == I40IW_WQE_SIZE_64)) {
170                 i40iw_nop_1(qp);
171                 I40IW_RING_MOVE_HEAD(qp->sq_ring, ret_code);
172                 if (ret_code)
173                         return NULL;
174                 *wqe_idx = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
175                 if (!*wqe_idx)
176                         qp->swqe_polarity = !qp->swqe_polarity;
177         }
178         I40IW_RING_MOVE_HEAD_BY_COUNT(qp->sq_ring,
179                                       wqe_size / I40IW_QP_WQE_MIN_SIZE, ret_code);
180         if (ret_code)
181                 return NULL;
182
183         wqe = qp->sq_base[*wqe_idx].elem;
184
185         peek_head = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
186         wqe_0 = qp->sq_base[peek_head].elem;
187
188         if (((peek_head & 3) == 1) || ((peek_head & 3) == 3)) {
189                 if (RS_64(wqe_0[3], I40IWQPSQ_VALID) != !qp->swqe_polarity)
190                         wqe_0[3] = LS_64(!qp->swqe_polarity, I40IWQPSQ_VALID);
191         }
192
193         qp->sq_wrtrk_array[*wqe_idx].wrid = wr_id;
194         qp->sq_wrtrk_array[*wqe_idx].wr_len = total_size;
195         qp->sq_wrtrk_array[*wqe_idx].wqe_size = wqe_size;
196         return wqe;
197 }
198
199 /**
200  * i40iw_set_fragment - set fragment in wqe
201  * @wqe: wqe for setting fragment
202  * @offset: offset value
203  * @sge: sge length and stag
204  */
205 static void i40iw_set_fragment(u64 *wqe, u32 offset, struct i40iw_sge *sge)
206 {
207         if (sge) {
208                 set_64bit_val(wqe, offset, LS_64(sge->tag_off, I40IWQPSQ_FRAG_TO));
209                 set_64bit_val(wqe, (offset + 8),
210                               (LS_64(sge->len, I40IWQPSQ_FRAG_LEN) |
211                                LS_64(sge->stag, I40IWQPSQ_FRAG_STAG)));
212         }
213 }
214
215 /**
216  * i40iw_qp_get_next_recv_wqe - get next qp's rcv wqe
217  * @qp: hw qp ptr
218  * @wqe_idx: return wqe index
219  */
220 u64 *i40iw_qp_get_next_recv_wqe(struct i40iw_qp_uk *qp, u32 *wqe_idx)
221 {
222         u64 *wqe = NULL;
223         enum i40iw_status_code ret_code;
224
225         if (I40IW_RING_FULL_ERR(qp->rq_ring))
226                 return NULL;
227
228         I40IW_ATOMIC_RING_MOVE_HEAD(qp->rq_ring, *wqe_idx, ret_code);
229         if (ret_code)
230                 return NULL;
231         if (!*wqe_idx)
232                 qp->rwqe_polarity = !qp->rwqe_polarity;
233         /* rq_wqe_size_multiplier is no of qwords in one rq wqe */
234         wqe = qp->rq_base[*wqe_idx * (qp->rq_wqe_size_multiplier >> 2)].elem;
235
236         return wqe;
237 }
238
239 /**
240  * i40iw_rdma_write - rdma write operation
241  * @qp: hw qp ptr
242  * @info: post sq information
243  * @post_sq: flag to post sq
244  */
245 static enum i40iw_status_code i40iw_rdma_write(struct i40iw_qp_uk *qp,
246                                                struct i40iw_post_sq_info *info,
247                                                bool post_sq)
248 {
249         u64 header;
250         u64 *wqe;
251         struct i40iw_rdma_write *op_info;
252         u32 i, wqe_idx;
253         u32 total_size = 0, byte_off;
254         enum i40iw_status_code ret_code;
255         bool read_fence = false;
256         u8 wqe_size;
257
258         op_info = &info->op.rdma_write;
259         if (op_info->num_lo_sges > qp->max_sq_frag_cnt)
260                 return I40IW_ERR_INVALID_FRAG_COUNT;
261
262         for (i = 0; i < op_info->num_lo_sges; i++)
263                 total_size += op_info->lo_sg_list[i].len;
264
265         if (total_size > I40IW_MAX_OUTBOUND_MESSAGE_SIZE)
266                 return I40IW_ERR_QP_INVALID_MSG_SIZE;
267
268         read_fence |= info->read_fence;
269
270         ret_code = i40iw_fragcnt_to_wqesize_sq(op_info->num_lo_sges, &wqe_size);
271         if (ret_code)
272                 return ret_code;
273
274         wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, wqe_size, total_size, info->wr_id);
275         if (!wqe)
276                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
277         set_64bit_val(wqe, 16,
278                       LS_64(op_info->rem_addr.tag_off, I40IWQPSQ_FRAG_TO));
279         if (!op_info->rem_addr.stag)
280                 return I40IW_ERR_BAD_STAG;
281
282         header = LS_64(op_info->rem_addr.stag, I40IWQPSQ_REMSTAG) |
283                  LS_64(I40IWQP_OP_RDMA_WRITE, I40IWQPSQ_OPCODE) |
284                  LS_64((op_info->num_lo_sges > 1 ?  (op_info->num_lo_sges - 1) : 0), I40IWQPSQ_ADDFRAGCNT) |
285                  LS_64(read_fence, I40IWQPSQ_READFENCE) |
286                  LS_64(info->local_fence, I40IWQPSQ_LOCALFENCE) |
287                  LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
288                  LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
289
290         i40iw_set_fragment(wqe, 0, op_info->lo_sg_list);
291
292         for (i = 1, byte_off = 32; i < op_info->num_lo_sges; i++) {
293                 i40iw_set_fragment(wqe, byte_off, &op_info->lo_sg_list[i]);
294                 byte_off += 16;
295         }
296
297         wmb(); /* make sure WQE is populated before valid bit is set */
298
299         set_64bit_val(wqe, 24, header);
300
301         if (post_sq)
302                 i40iw_qp_post_wr(qp);
303
304         return 0;
305 }
306
307 /**
308  * i40iw_rdma_read - rdma read command
309  * @qp: hw qp ptr
310  * @info: post sq information
311  * @inv_stag: flag for inv_stag
312  * @post_sq: flag to post sq
313  */
314 static enum i40iw_status_code i40iw_rdma_read(struct i40iw_qp_uk *qp,
315                                               struct i40iw_post_sq_info *info,
316                                               bool inv_stag,
317                                               bool post_sq)
318 {
319         u64 *wqe;
320         struct i40iw_rdma_read *op_info;
321         u64 header;
322         u32 wqe_idx;
323         enum i40iw_status_code ret_code;
324         u8 wqe_size;
325         bool local_fence = false;
326
327         op_info = &info->op.rdma_read;
328         ret_code = i40iw_fragcnt_to_wqesize_sq(1, &wqe_size);
329         if (ret_code)
330                 return ret_code;
331         wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, wqe_size, op_info->lo_addr.len, info->wr_id);
332         if (!wqe)
333                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
334         local_fence |= info->local_fence;
335
336         set_64bit_val(wqe, 16, LS_64(op_info->rem_addr.tag_off, I40IWQPSQ_FRAG_TO));
337         header = LS_64(op_info->rem_addr.stag, I40IWQPSQ_REMSTAG) |
338                  LS_64((inv_stag ? I40IWQP_OP_RDMA_READ_LOC_INV : I40IWQP_OP_RDMA_READ), I40IWQPSQ_OPCODE) |
339                  LS_64(info->read_fence, I40IWQPSQ_READFENCE) |
340                  LS_64(local_fence, I40IWQPSQ_LOCALFENCE) |
341                  LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
342                  LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
343
344         i40iw_set_fragment(wqe, 0, &op_info->lo_addr);
345
346         wmb(); /* make sure WQE is populated before valid bit is set */
347
348         set_64bit_val(wqe, 24, header);
349         if (post_sq)
350                 i40iw_qp_post_wr(qp);
351
352         return 0;
353 }
354
355 /**
356  * i40iw_send - rdma send command
357  * @qp: hw qp ptr
358  * @info: post sq information
359  * @stag_to_inv: stag_to_inv value
360  * @post_sq: flag to post sq
361  */
362 static enum i40iw_status_code i40iw_send(struct i40iw_qp_uk *qp,
363                                          struct i40iw_post_sq_info *info,
364                                          u32 stag_to_inv,
365                                          bool post_sq)
366 {
367         u64 *wqe;
368         struct i40iw_post_send *op_info;
369         u64 header;
370         u32 i, wqe_idx, total_size = 0, byte_off;
371         enum i40iw_status_code ret_code;
372         bool read_fence = false;
373         u8 wqe_size;
374
375         op_info = &info->op.send;
376         if (qp->max_sq_frag_cnt < op_info->num_sges)
377                 return I40IW_ERR_INVALID_FRAG_COUNT;
378
379         for (i = 0; i < op_info->num_sges; i++)
380                 total_size += op_info->sg_list[i].len;
381         ret_code = i40iw_fragcnt_to_wqesize_sq(op_info->num_sges, &wqe_size);
382         if (ret_code)
383                 return ret_code;
384
385         wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, wqe_size, total_size, info->wr_id);
386         if (!wqe)
387                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
388
389         read_fence |= info->read_fence;
390         set_64bit_val(wqe, 16, 0);
391         header = LS_64(stag_to_inv, I40IWQPSQ_REMSTAG) |
392                  LS_64(info->op_type, I40IWQPSQ_OPCODE) |
393                  LS_64((op_info->num_sges > 1 ? (op_info->num_sges - 1) : 0),
394                        I40IWQPSQ_ADDFRAGCNT) |
395                  LS_64(read_fence, I40IWQPSQ_READFENCE) |
396                  LS_64(info->local_fence, I40IWQPSQ_LOCALFENCE) |
397                  LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
398                  LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
399
400         i40iw_set_fragment(wqe, 0, op_info->sg_list);
401
402         for (i = 1, byte_off = 32; i < op_info->num_sges; i++) {
403                 i40iw_set_fragment(wqe, byte_off, &op_info->sg_list[i]);
404                 byte_off += 16;
405         }
406
407         wmb(); /* make sure WQE is populated before valid bit is set */
408
409         set_64bit_val(wqe, 24, header);
410         if (post_sq)
411                 i40iw_qp_post_wr(qp);
412
413         return 0;
414 }
415
416 /**
417  * i40iw_inline_rdma_write - inline rdma write operation
418  * @qp: hw qp ptr
419  * @info: post sq information
420  * @post_sq: flag to post sq
421  */
422 static enum i40iw_status_code i40iw_inline_rdma_write(struct i40iw_qp_uk *qp,
423                                                       struct i40iw_post_sq_info *info,
424                                                       bool post_sq)
425 {
426         u64 *wqe;
427         u8 *dest, *src;
428         struct i40iw_inline_rdma_write *op_info;
429         u64 *push;
430         u64 header = 0;
431         u32 wqe_idx;
432         enum i40iw_status_code ret_code;
433         bool read_fence = false;
434         u8 wqe_size;
435
436         op_info = &info->op.inline_rdma_write;
437         if (op_info->len > I40IW_MAX_INLINE_DATA_SIZE)
438                 return I40IW_ERR_INVALID_INLINE_DATA_SIZE;
439
440         ret_code = i40iw_inline_data_size_to_wqesize(op_info->len, &wqe_size);
441         if (ret_code)
442                 return ret_code;
443
444         wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, wqe_size, op_info->len, info->wr_id);
445         if (!wqe)
446                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
447
448         read_fence |= info->read_fence;
449         set_64bit_val(wqe, 16,
450                       LS_64(op_info->rem_addr.tag_off, I40IWQPSQ_FRAG_TO));
451
452         header = LS_64(op_info->rem_addr.stag, I40IWQPSQ_REMSTAG) |
453                  LS_64(I40IWQP_OP_RDMA_WRITE, I40IWQPSQ_OPCODE) |
454                  LS_64(op_info->len, I40IWQPSQ_INLINEDATALEN) |
455                  LS_64(1, I40IWQPSQ_INLINEDATAFLAG) |
456                  LS_64((qp->push_db ? 1 : 0), I40IWQPSQ_PUSHWQE) |
457                  LS_64(read_fence, I40IWQPSQ_READFENCE) |
458                  LS_64(info->local_fence, I40IWQPSQ_LOCALFENCE) |
459                  LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
460                  LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
461
462         dest = (u8 *)wqe;
463         src = (u8 *)(op_info->data);
464
465         if (op_info->len <= 16) {
466                 memcpy(dest, src, op_info->len);
467         } else {
468                 memcpy(dest, src, 16);
469                 src += 16;
470                 dest = (u8 *)wqe + 32;
471                 memcpy(dest, src, op_info->len - 16);
472         }
473
474         wmb(); /* make sure WQE is populated before valid bit is set */
475
476         set_64bit_val(wqe, 24, header);
477
478         if (qp->push_db) {
479                 push = (u64 *)((uintptr_t)qp->push_wqe + (wqe_idx & 0x3) * 0x20);
480                 memcpy(push, wqe, (op_info->len > 16) ? op_info->len + 16 : 32);
481                 i40iw_qp_ring_push_db(qp, wqe_idx);
482         } else {
483                 if (post_sq)
484                         i40iw_qp_post_wr(qp);
485         }
486
487         return 0;
488 }
489
490 /**
491  * i40iw_inline_send - inline send operation
492  * @qp: hw qp ptr
493  * @info: post sq information
494  * @stag_to_inv: remote stag
495  * @post_sq: flag to post sq
496  */
497 static enum i40iw_status_code i40iw_inline_send(struct i40iw_qp_uk *qp,
498                                                 struct i40iw_post_sq_info *info,
499                                                 u32 stag_to_inv,
500                                                 bool post_sq)
501 {
502         u64 *wqe;
503         u8 *dest, *src;
504         struct i40iw_post_inline_send *op_info;
505         u64 header;
506         u32 wqe_idx;
507         enum i40iw_status_code ret_code;
508         bool read_fence = false;
509         u8 wqe_size;
510         u64 *push;
511
512         op_info = &info->op.inline_send;
513         if (op_info->len > I40IW_MAX_INLINE_DATA_SIZE)
514                 return I40IW_ERR_INVALID_INLINE_DATA_SIZE;
515
516         ret_code = i40iw_inline_data_size_to_wqesize(op_info->len, &wqe_size);
517         if (ret_code)
518                 return ret_code;
519
520         wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, wqe_size, op_info->len, info->wr_id);
521         if (!wqe)
522                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
523
524         read_fence |= info->read_fence;
525         header = LS_64(stag_to_inv, I40IWQPSQ_REMSTAG) |
526             LS_64(info->op_type, I40IWQPSQ_OPCODE) |
527             LS_64(op_info->len, I40IWQPSQ_INLINEDATALEN) |
528             LS_64(1, I40IWQPSQ_INLINEDATAFLAG) |
529             LS_64((qp->push_db ? 1 : 0), I40IWQPSQ_PUSHWQE) |
530             LS_64(read_fence, I40IWQPSQ_READFENCE) |
531             LS_64(info->local_fence, I40IWQPSQ_LOCALFENCE) |
532             LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
533             LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
534
535         dest = (u8 *)wqe;
536         src = (u8 *)(op_info->data);
537
538         if (op_info->len <= 16) {
539                 memcpy(dest, src, op_info->len);
540         } else {
541                 memcpy(dest, src, 16);
542                 src += 16;
543                 dest = (u8 *)wqe + 32;
544                 memcpy(dest, src, op_info->len - 16);
545         }
546
547         wmb(); /* make sure WQE is populated before valid bit is set */
548
549         set_64bit_val(wqe, 24, header);
550
551         if (qp->push_db) {
552                 push = (u64 *)((uintptr_t)qp->push_wqe + (wqe_idx & 0x3) * 0x20);
553                 memcpy(push, wqe, (op_info->len > 16) ? op_info->len + 16 : 32);
554                 i40iw_qp_ring_push_db(qp, wqe_idx);
555         } else {
556                 if (post_sq)
557                         i40iw_qp_post_wr(qp);
558         }
559
560         return 0;
561 }
562
563 /**
564  * i40iw_stag_local_invalidate - stag invalidate operation
565  * @qp: hw qp ptr
566  * @info: post sq information
567  * @post_sq: flag to post sq
568  */
569 static enum i40iw_status_code i40iw_stag_local_invalidate(struct i40iw_qp_uk *qp,
570                                                           struct i40iw_post_sq_info *info,
571                                                           bool post_sq)
572 {
573         u64 *wqe;
574         struct i40iw_inv_local_stag *op_info;
575         u64 header;
576         u32 wqe_idx;
577         bool local_fence = false;
578
579         op_info = &info->op.inv_local_stag;
580         local_fence = info->local_fence;
581
582         wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, I40IW_QP_WQE_MIN_SIZE, 0, info->wr_id);
583         if (!wqe)
584                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
585         set_64bit_val(wqe, 0, 0);
586         set_64bit_val(wqe, 8,
587                       LS_64(op_info->target_stag, I40IWQPSQ_LOCSTAG));
588         set_64bit_val(wqe, 16, 0);
589         header = LS_64(I40IW_OP_TYPE_INV_STAG, I40IWQPSQ_OPCODE) |
590             LS_64(info->read_fence, I40IWQPSQ_READFENCE) |
591             LS_64(local_fence, I40IWQPSQ_LOCALFENCE) |
592             LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
593             LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
594
595         wmb(); /* make sure WQE is populated before valid bit is set */
596
597         set_64bit_val(wqe, 24, header);
598
599         if (post_sq)
600                 i40iw_qp_post_wr(qp);
601
602         return 0;
603 }
604
605 /**
606  * i40iw_mw_bind - Memory Window bind operation
607  * @qp: hw qp ptr
608  * @info: post sq information
609  * @post_sq: flag to post sq
610  */
611 static enum i40iw_status_code i40iw_mw_bind(struct i40iw_qp_uk *qp,
612                                             struct i40iw_post_sq_info *info,
613                                             bool post_sq)
614 {
615         u64 *wqe;
616         struct i40iw_bind_window *op_info;
617         u64 header;
618         u32 wqe_idx;
619         bool local_fence = false;
620
621         op_info = &info->op.bind_window;
622
623         local_fence |= info->local_fence;
624         wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, I40IW_QP_WQE_MIN_SIZE, 0, info->wr_id);
625         if (!wqe)
626                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
627         set_64bit_val(wqe, 0, (uintptr_t)op_info->va);
628         set_64bit_val(wqe, 8,
629                       LS_64(op_info->mr_stag, I40IWQPSQ_PARENTMRSTAG) |
630                       LS_64(op_info->mw_stag, I40IWQPSQ_MWSTAG));
631         set_64bit_val(wqe, 16, op_info->bind_length);
632         header = LS_64(I40IW_OP_TYPE_BIND_MW, I40IWQPSQ_OPCODE) |
633             LS_64(((op_info->enable_reads << 2) |
634                    (op_info->enable_writes << 3)),
635                   I40IWQPSQ_STAGRIGHTS) |
636             LS_64((op_info->addressing_type == I40IW_ADDR_TYPE_VA_BASED ?  1 : 0),
637                   I40IWQPSQ_VABASEDTO) |
638             LS_64(info->read_fence, I40IWQPSQ_READFENCE) |
639             LS_64(local_fence, I40IWQPSQ_LOCALFENCE) |
640             LS_64(info->signaled, I40IWQPSQ_SIGCOMPL) |
641             LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
642
643         wmb(); /* make sure WQE is populated before valid bit is set */
644
645         set_64bit_val(wqe, 24, header);
646
647         if (post_sq)
648                 i40iw_qp_post_wr(qp);
649
650         return 0;
651 }
652
653 /**
654  * i40iw_post_receive - post receive wqe
655  * @qp: hw qp ptr
656  * @info: post rq information
657  */
658 static enum i40iw_status_code i40iw_post_receive(struct i40iw_qp_uk *qp,
659                                                  struct i40iw_post_rq_info *info)
660 {
661         u64 *wqe;
662         u64 header;
663         u32 total_size = 0, wqe_idx, i, byte_off;
664
665         if (qp->max_rq_frag_cnt < info->num_sges)
666                 return I40IW_ERR_INVALID_FRAG_COUNT;
667         for (i = 0; i < info->num_sges; i++)
668                 total_size += info->sg_list[i].len;
669         wqe = i40iw_qp_get_next_recv_wqe(qp, &wqe_idx);
670         if (!wqe)
671                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
672
673         qp->rq_wrid_array[wqe_idx] = info->wr_id;
674         set_64bit_val(wqe, 16, 0);
675
676         header = LS_64((info->num_sges > 1 ? (info->num_sges - 1) : 0),
677                        I40IWQPSQ_ADDFRAGCNT) |
678             LS_64(qp->rwqe_polarity, I40IWQPSQ_VALID);
679
680         i40iw_set_fragment(wqe, 0, info->sg_list);
681
682         for (i = 1, byte_off = 32; i < info->num_sges; i++) {
683                 i40iw_set_fragment(wqe, byte_off, &info->sg_list[i]);
684                 byte_off += 16;
685         }
686
687         wmb(); /* make sure WQE is populated before valid bit is set */
688
689         set_64bit_val(wqe, 24, header);
690
691         return 0;
692 }
693
694 /**
695  * i40iw_cq_request_notification - cq notification request (door bell)
696  * @cq: hw cq
697  * @cq_notify: notification type
698  */
699 static void i40iw_cq_request_notification(struct i40iw_cq_uk *cq,
700                                           enum i40iw_completion_notify cq_notify)
701 {
702         u64 temp_val;
703         u16 sw_cq_sel;
704         u8 arm_next_se = 0;
705         u8 arm_next = 0;
706         u8 arm_seq_num;
707
708         get_64bit_val(cq->shadow_area, 32, &temp_val);
709         arm_seq_num = (u8)RS_64(temp_val, I40IW_CQ_DBSA_ARM_SEQ_NUM);
710         arm_seq_num++;
711
712         sw_cq_sel = (u16)RS_64(temp_val, I40IW_CQ_DBSA_SW_CQ_SELECT);
713         arm_next_se = (u8)RS_64(temp_val, I40IW_CQ_DBSA_ARM_NEXT_SE);
714         arm_next_se |= 1;
715         if (cq_notify == IW_CQ_COMPL_EVENT)
716                 arm_next = 1;
717         temp_val = LS_64(arm_seq_num, I40IW_CQ_DBSA_ARM_SEQ_NUM) |
718             LS_64(sw_cq_sel, I40IW_CQ_DBSA_SW_CQ_SELECT) |
719             LS_64(arm_next_se, I40IW_CQ_DBSA_ARM_NEXT_SE) |
720             LS_64(arm_next, I40IW_CQ_DBSA_ARM_NEXT);
721
722         set_64bit_val(cq->shadow_area, 32, temp_val);
723
724         wmb(); /* make sure WQE is populated before valid bit is set */
725
726         writel(cq->cq_id, cq->cqe_alloc_reg);
727 }
728
729 /**
730  * i40iw_cq_post_entries - update tail in shadow memory
731  * @cq: hw cq
732  * @count: # of entries processed
733  */
734 static enum i40iw_status_code i40iw_cq_post_entries(struct i40iw_cq_uk *cq,
735                                                     u8 count)
736 {
737         I40IW_RING_MOVE_TAIL_BY_COUNT(cq->cq_ring, count);
738         set_64bit_val(cq->shadow_area, 0,
739                       I40IW_RING_GETCURRENT_HEAD(cq->cq_ring));
740         return 0;
741 }
742
743 /**
744  * i40iw_cq_poll_completion - get cq completion info
745  * @cq: hw cq
746  * @info: cq poll information returned
747  * @post_cq: update cq tail
748  */
749 static enum i40iw_status_code i40iw_cq_poll_completion(struct i40iw_cq_uk *cq,
750                                                        struct i40iw_cq_poll_info *info)
751 {
752         u64 comp_ctx, qword0, qword2, qword3, wqe_qword;
753         u64 *cqe, *sw_wqe;
754         struct i40iw_qp_uk *qp;
755         struct i40iw_ring *pring = NULL;
756         u32 wqe_idx, q_type, array_idx = 0;
757         enum i40iw_status_code ret_code = 0;
758         bool move_cq_head = true;
759         u8 polarity;
760         u8 addl_wqes = 0;
761
762         if (cq->avoid_mem_cflct)
763                 cqe = (u64 *)I40IW_GET_CURRENT_EXTENDED_CQ_ELEMENT(cq);
764         else
765                 cqe = (u64 *)I40IW_GET_CURRENT_CQ_ELEMENT(cq);
766
767         get_64bit_val(cqe, 24, &qword3);
768         polarity = (u8)RS_64(qword3, I40IW_CQ_VALID);
769
770         if (polarity != cq->polarity)
771                 return I40IW_ERR_QUEUE_EMPTY;
772
773         q_type = (u8)RS_64(qword3, I40IW_CQ_SQ);
774         info->error = (bool)RS_64(qword3, I40IW_CQ_ERROR);
775         info->push_dropped = (bool)RS_64(qword3, I40IWCQ_PSHDROP);
776         if (info->error) {
777                 info->comp_status = I40IW_COMPL_STATUS_FLUSHED;
778                 info->major_err = (bool)RS_64(qword3, I40IW_CQ_MAJERR);
779                 info->minor_err = (bool)RS_64(qword3, I40IW_CQ_MINERR);
780         } else {
781                 info->comp_status = I40IW_COMPL_STATUS_SUCCESS;
782         }
783
784         get_64bit_val(cqe, 0, &qword0);
785         get_64bit_val(cqe, 16, &qword2);
786
787         info->tcp_seq_num = (u8)RS_64(qword0, I40IWCQ_TCPSEQNUM);
788
789         info->qp_id = (u32)RS_64(qword2, I40IWCQ_QPID);
790
791         get_64bit_val(cqe, 8, &comp_ctx);
792
793         info->solicited_event = (bool)RS_64(qword3, I40IWCQ_SOEVENT);
794         info->is_srq = (bool)RS_64(qword3, I40IWCQ_SRQ);
795
796         qp = (struct i40iw_qp_uk *)(unsigned long)comp_ctx;
797         if (!qp) {
798                 ret_code = I40IW_ERR_QUEUE_DESTROYED;
799                 goto exit;
800         }
801         wqe_idx = (u32)RS_64(qword3, I40IW_CQ_WQEIDX);
802         info->qp_handle = (i40iw_qp_handle)(unsigned long)qp;
803
804         if (q_type == I40IW_CQE_QTYPE_RQ) {
805                 array_idx = (wqe_idx * 4) / qp->rq_wqe_size_multiplier;
806                 if (info->comp_status == I40IW_COMPL_STATUS_FLUSHED) {
807                         info->wr_id = qp->rq_wrid_array[qp->rq_ring.tail];
808                         array_idx = qp->rq_ring.tail;
809                 } else {
810                         info->wr_id = qp->rq_wrid_array[array_idx];
811                 }
812
813                 info->op_type = I40IW_OP_TYPE_REC;
814                 if (qword3 & I40IWCQ_STAG_MASK) {
815                         info->stag_invalid_set = true;
816                         info->inv_stag = (u32)RS_64(qword2, I40IWCQ_INVSTAG);
817                 } else {
818                         info->stag_invalid_set = false;
819                 }
820                 info->bytes_xfered = (u32)RS_64(qword0, I40IWCQ_PAYLDLEN);
821                 I40IW_RING_SET_TAIL(qp->rq_ring, array_idx + 1);
822                 pring = &qp->rq_ring;
823         } else {
824                 if (info->comp_status != I40IW_COMPL_STATUS_FLUSHED) {
825                         info->wr_id = qp->sq_wrtrk_array[wqe_idx].wrid;
826                         info->bytes_xfered = qp->sq_wrtrk_array[wqe_idx].wr_len;
827
828                         info->op_type = (u8)RS_64(qword3, I40IWCQ_OP);
829                         sw_wqe = qp->sq_base[wqe_idx].elem;
830                         get_64bit_val(sw_wqe, 24, &wqe_qword);
831
832                         addl_wqes = qp->sq_wrtrk_array[wqe_idx].wqe_size / I40IW_QP_WQE_MIN_SIZE;
833                         I40IW_RING_SET_TAIL(qp->sq_ring, (wqe_idx + addl_wqes));
834                 } else {
835                         do {
836                                 u8 op_type;
837                                 u32 tail;
838
839                                 tail = qp->sq_ring.tail;
840                                 sw_wqe = qp->sq_base[tail].elem;
841                                 get_64bit_val(sw_wqe, 24, &wqe_qword);
842                                 op_type = (u8)RS_64(wqe_qword, I40IWQPSQ_OPCODE);
843                                 info->op_type = op_type;
844                                 addl_wqes = qp->sq_wrtrk_array[tail].wqe_size / I40IW_QP_WQE_MIN_SIZE;
845                                 I40IW_RING_SET_TAIL(qp->sq_ring, (tail + addl_wqes));
846                                 if (op_type != I40IWQP_OP_NOP) {
847                                         info->wr_id = qp->sq_wrtrk_array[tail].wrid;
848                                         info->bytes_xfered = qp->sq_wrtrk_array[tail].wr_len;
849                                         break;
850                                 }
851                         } while (1);
852                 }
853                 pring = &qp->sq_ring;
854         }
855
856         ret_code = 0;
857
858 exit:
859         if (!ret_code &&
860             (info->comp_status == I40IW_COMPL_STATUS_FLUSHED))
861                 if (pring && (I40IW_RING_MORE_WORK(*pring)))
862                         move_cq_head = false;
863
864         if (move_cq_head) {
865                 I40IW_RING_MOVE_HEAD_NOCHECK(cq->cq_ring);
866
867                 if (I40IW_RING_GETCURRENT_HEAD(cq->cq_ring) == 0)
868                         cq->polarity ^= 1;
869
870                 I40IW_RING_MOVE_TAIL(cq->cq_ring);
871                 set_64bit_val(cq->shadow_area, 0,
872                               I40IW_RING_GETCURRENT_HEAD(cq->cq_ring));
873         } else {
874                 if (info->is_srq)
875                         return ret_code;
876                 qword3 &= ~I40IW_CQ_WQEIDX_MASK;
877                 qword3 |= LS_64(pring->tail, I40IW_CQ_WQEIDX);
878                 set_64bit_val(cqe, 24, qword3);
879         }
880
881         return ret_code;
882 }
883
884 /**
885  * i40iw_get_wqe_shift - get shift count for maximum wqe size
886  * @wqdepth: depth of wq required.
887  * @sge: Maximum Scatter Gather Elements wqe
888  * @inline_data: Maximum inline data size
889  * @shift: Returns the shift needed based on sge
890  *
891  * Shift can be used to left shift the wqe size based on number of SGEs and inlind data size.
892  * For 1 SGE or inline data <= 16, shift = 0 (wqe size of 32 bytes).
893  * For 2 or 3 SGEs or inline data <= 48, shift = 1 (wqe size of 64 bytes).
894  * Shift of 2 otherwise (wqe size of 128 bytes).
895  */
896 enum i40iw_status_code i40iw_get_wqe_shift(u32 wqdepth, u32 sge, u32 inline_data, u8 *shift)
897 {
898         u32 size;
899
900         *shift = 0;
901         if (sge > 1 || inline_data > 16)
902                 *shift = (sge < 4 && inline_data <= 48) ? 1 : 2;
903
904         /* check if wqdepth is multiple of 2 or not */
905
906         if ((wqdepth < I40IWQP_SW_MIN_WQSIZE) || (wqdepth & (wqdepth - 1)))
907                 return I40IW_ERR_INVALID_SIZE;
908
909         size = wqdepth << *shift;       /* multiple of 32 bytes count */
910         if (size > I40IWQP_SW_MAX_WQSIZE)
911                 return I40IW_ERR_INVALID_SIZE;
912         return 0;
913 }
914
915 static struct i40iw_qp_uk_ops iw_qp_uk_ops = {
916         .iw_qp_post_wr = i40iw_qp_post_wr,
917         .iw_qp_ring_push_db = i40iw_qp_ring_push_db,
918         .iw_rdma_write = i40iw_rdma_write,
919         .iw_rdma_read = i40iw_rdma_read,
920         .iw_send = i40iw_send,
921         .iw_inline_rdma_write = i40iw_inline_rdma_write,
922         .iw_inline_send = i40iw_inline_send,
923         .iw_stag_local_invalidate = i40iw_stag_local_invalidate,
924         .iw_mw_bind = i40iw_mw_bind,
925         .iw_post_receive = i40iw_post_receive,
926         .iw_post_nop = i40iw_nop
927 };
928
929 static struct i40iw_cq_ops iw_cq_ops = {
930         .iw_cq_request_notification = i40iw_cq_request_notification,
931         .iw_cq_poll_completion = i40iw_cq_poll_completion,
932         .iw_cq_post_entries = i40iw_cq_post_entries,
933         .iw_cq_clean = i40iw_clean_cq
934 };
935
936 static struct i40iw_device_uk_ops iw_device_uk_ops = {
937         .iwarp_cq_uk_init = i40iw_cq_uk_init,
938         .iwarp_qp_uk_init = i40iw_qp_uk_init,
939 };
940
941 /**
942  * i40iw_qp_uk_init - initialize shared qp
943  * @qp: hw qp (user and kernel)
944  * @info: qp initialization info
945  *
946  * initializes the vars used in both user and kernel mode.
947  * size of the wqe depends on numbers of max. fragements
948  * allowed. Then size of wqe * the number of wqes should be the
949  * amount of memory allocated for sq and rq. If srq is used,
950  * then rq_base will point to one rq wqe only (not the whole
951  * array of wqes)
952  */
953 enum i40iw_status_code i40iw_qp_uk_init(struct i40iw_qp_uk *qp,
954                                         struct i40iw_qp_uk_init_info *info)
955 {
956         enum i40iw_status_code ret_code = 0;
957         u32 sq_ring_size;
958         u8 sqshift, rqshift;
959
960         if (info->max_sq_frag_cnt > I40IW_MAX_WQ_FRAGMENT_COUNT)
961                 return I40IW_ERR_INVALID_FRAG_COUNT;
962
963         if (info->max_rq_frag_cnt > I40IW_MAX_WQ_FRAGMENT_COUNT)
964                 return I40IW_ERR_INVALID_FRAG_COUNT;
965         ret_code = i40iw_get_wqe_shift(info->sq_size, info->max_sq_frag_cnt, info->max_inline_data, &sqshift);
966         if (ret_code)
967                 return ret_code;
968
969         qp->sq_base = info->sq;
970         qp->rq_base = info->rq;
971         qp->shadow_area = info->shadow_area;
972         qp->sq_wrtrk_array = info->sq_wrtrk_array;
973         qp->rq_wrid_array = info->rq_wrid_array;
974
975         qp->wqe_alloc_reg = info->wqe_alloc_reg;
976         qp->qp_id = info->qp_id;
977
978         qp->sq_size = info->sq_size;
979         qp->push_db = info->push_db;
980         qp->push_wqe = info->push_wqe;
981
982         qp->max_sq_frag_cnt = info->max_sq_frag_cnt;
983         sq_ring_size = qp->sq_size << sqshift;
984
985         I40IW_RING_INIT(qp->sq_ring, sq_ring_size);
986         I40IW_RING_INIT(qp->initial_ring, sq_ring_size);
987         I40IW_RING_MOVE_HEAD(qp->sq_ring, ret_code);
988         I40IW_RING_MOVE_TAIL(qp->sq_ring);
989         I40IW_RING_MOVE_HEAD(qp->initial_ring, ret_code);
990         qp->swqe_polarity = 1;
991         qp->swqe_polarity_deferred = 1;
992         qp->rwqe_polarity = 0;
993
994         if (!qp->use_srq) {
995                 qp->rq_size = info->rq_size;
996                 qp->max_rq_frag_cnt = info->max_rq_frag_cnt;
997                 I40IW_RING_INIT(qp->rq_ring, qp->rq_size);
998                 switch (info->abi_ver) {
999                 case 4:
1000                         ret_code = i40iw_get_wqe_shift(info->rq_size, info->max_rq_frag_cnt, 0, &rqshift);
1001                         if (ret_code)
1002                                 return ret_code;
1003                         break;
1004                 case 5: /* fallthrough until next ABI version */
1005                 default:
1006                         rqshift = I40IW_MAX_RQ_WQE_SHIFT;
1007                         break;
1008                 }
1009                 qp->rq_wqe_size = rqshift;
1010                 qp->rq_wqe_size_multiplier = 4 << rqshift;
1011         }
1012         qp->ops = iw_qp_uk_ops;
1013
1014         return ret_code;
1015 }
1016
1017 /**
1018  * i40iw_cq_uk_init - initialize shared cq (user and kernel)
1019  * @cq: hw cq
1020  * @info: hw cq initialization info
1021  */
1022 enum i40iw_status_code i40iw_cq_uk_init(struct i40iw_cq_uk *cq,
1023                                         struct i40iw_cq_uk_init_info *info)
1024 {
1025         if ((info->cq_size < I40IW_MIN_CQ_SIZE) ||
1026             (info->cq_size > I40IW_MAX_CQ_SIZE))
1027                 return I40IW_ERR_INVALID_SIZE;
1028         cq->cq_base = (struct i40iw_cqe *)info->cq_base;
1029         cq->cq_id = info->cq_id;
1030         cq->cq_size = info->cq_size;
1031         cq->cqe_alloc_reg = info->cqe_alloc_reg;
1032         cq->shadow_area = info->shadow_area;
1033         cq->avoid_mem_cflct = info->avoid_mem_cflct;
1034
1035         I40IW_RING_INIT(cq->cq_ring, cq->cq_size);
1036         cq->polarity = 1;
1037         cq->ops = iw_cq_ops;
1038
1039         return 0;
1040 }
1041
1042 /**
1043  * i40iw_device_init_uk - setup routines for iwarp shared device
1044  * @dev: iwarp shared (user and kernel)
1045  */
1046 void i40iw_device_init_uk(struct i40iw_dev_uk *dev)
1047 {
1048         dev->ops_uk = iw_device_uk_ops;
1049 }
1050
1051 /**
1052  * i40iw_clean_cq - clean cq entries
1053  * @ queue completion context
1054  * @cq: cq to clean
1055  */
1056 void i40iw_clean_cq(void *queue, struct i40iw_cq_uk *cq)
1057 {
1058         u64 *cqe;
1059         u64 qword3, comp_ctx;
1060         u32 cq_head;
1061         u8 polarity, temp;
1062
1063         cq_head = cq->cq_ring.head;
1064         temp = cq->polarity;
1065         do {
1066                 if (cq->avoid_mem_cflct)
1067                         cqe = (u64 *)&(((struct i40iw_extended_cqe *)cq->cq_base)[cq_head]);
1068                 else
1069                         cqe = (u64 *)&cq->cq_base[cq_head];
1070                 get_64bit_val(cqe, 24, &qword3);
1071                 polarity = (u8)RS_64(qword3, I40IW_CQ_VALID);
1072
1073                 if (polarity != temp)
1074                         break;
1075
1076                 get_64bit_val(cqe, 8, &comp_ctx);
1077                 if ((void *)(unsigned long)comp_ctx == queue)
1078                         set_64bit_val(cqe, 8, 0);
1079
1080                 cq_head = (cq_head + 1) % cq->cq_ring.size;
1081                 if (!cq_head)
1082                         temp ^= 1;
1083         } while (true);
1084 }
1085
1086 /**
1087  * i40iw_nop - send a nop
1088  * @qp: hw qp ptr
1089  * @wr_id: work request id
1090  * @signaled: flag if signaled for completion
1091  * @post_sq: flag to post sq
1092  */
1093 enum i40iw_status_code i40iw_nop(struct i40iw_qp_uk *qp,
1094                                  u64 wr_id,
1095                                  bool signaled,
1096                                  bool post_sq)
1097 {
1098         u64 header, *wqe;
1099         u32 wqe_idx;
1100
1101         wqe = i40iw_qp_get_next_send_wqe(qp, &wqe_idx, I40IW_QP_WQE_MIN_SIZE, 0, wr_id);
1102         if (!wqe)
1103                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
1104         set_64bit_val(wqe, 0, 0);
1105         set_64bit_val(wqe, 8, 0);
1106         set_64bit_val(wqe, 16, 0);
1107
1108         header = LS_64(I40IWQP_OP_NOP, I40IWQPSQ_OPCODE) |
1109             LS_64(signaled, I40IWQPSQ_SIGCOMPL) |
1110             LS_64(qp->swqe_polarity, I40IWQPSQ_VALID);
1111
1112         wmb(); /* make sure WQE is populated before valid bit is set */
1113
1114         set_64bit_val(wqe, 24, header);
1115         if (post_sq)
1116                 i40iw_qp_post_wr(qp);
1117
1118         return 0;
1119 }
1120
1121 /**
1122  * i40iw_fragcnt_to_wqesize_sq - calculate wqe size based on fragment count for SQ
1123  * @frag_cnt: number of fragments
1124  * @wqe_size: size of sq wqe returned
1125  */
1126 enum i40iw_status_code i40iw_fragcnt_to_wqesize_sq(u32 frag_cnt, u8 *wqe_size)
1127 {
1128         switch (frag_cnt) {
1129         case 0:
1130         case 1:
1131                 *wqe_size = I40IW_QP_WQE_MIN_SIZE;
1132                 break;
1133         case 2:
1134         case 3:
1135                 *wqe_size = 64;
1136                 break;
1137         case 4:
1138         case 5:
1139                 *wqe_size = 96;
1140                 break;
1141         case 6:
1142         case 7:
1143                 *wqe_size = 128;
1144                 break;
1145         default:
1146                 return I40IW_ERR_INVALID_FRAG_COUNT;
1147         }
1148
1149         return 0;
1150 }
1151
1152 /**
1153  * i40iw_fragcnt_to_wqesize_rq - calculate wqe size based on fragment count for RQ
1154  * @frag_cnt: number of fragments
1155  * @wqe_size: size of rq wqe returned
1156  */
1157 enum i40iw_status_code i40iw_fragcnt_to_wqesize_rq(u32 frag_cnt, u8 *wqe_size)
1158 {
1159         switch (frag_cnt) {
1160         case 0:
1161         case 1:
1162                 *wqe_size = 32;
1163                 break;
1164         case 2:
1165         case 3:
1166                 *wqe_size = 64;
1167                 break;
1168         case 4:
1169         case 5:
1170         case 6:
1171         case 7:
1172                 *wqe_size = 128;
1173                 break;
1174         default:
1175                 return I40IW_ERR_INVALID_FRAG_COUNT;
1176         }
1177
1178         return 0;
1179 }
1180
1181 /**
1182  * i40iw_inline_data_size_to_wqesize - based on inline data, wqe size
1183  * @data_size: data size for inline
1184  * @wqe_size: size of sq wqe returned
1185  */
1186 enum i40iw_status_code i40iw_inline_data_size_to_wqesize(u32 data_size,
1187                                                          u8 *wqe_size)
1188 {
1189         if (data_size > I40IW_MAX_INLINE_DATA_SIZE)
1190                 return I40IW_ERR_INVALID_INLINE_DATA_SIZE;
1191
1192         if (data_size <= 16)
1193                 *wqe_size = I40IW_QP_WQE_MIN_SIZE;
1194         else
1195                 *wqe_size = 64;
1196
1197         return 0;
1198 }