drivers/infiniband/hw/mlx4/qp.c

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/log2.h>
  35 #include <linux/slab.h>
  36 #include <linux/netdevice.h>
  37
  38 #include <rdma/ib_cache.h>
  39 #include <rdma/ib_pack.h>
  40 #include <rdma/ib_addr.h>
  41 #include <rdma/ib_mad.h>
  42
  43 #include <linux/mlx4/driver.h>
  44 #include <linux/mlx4/qp.h>
  45
  46 #include "mlx4_ib.h"
  47 #include "user.h"
  48
  49 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
  50                              struct mlx4_ib_cq *recv_cq);
  51 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
  52                                struct mlx4_ib_cq *recv_cq);
  53
  54 enum {
  55         MLX4_IB_ACK_REQ_FREQ    = 8,
  56 };
  57
  58 enum {
  59         MLX4_IB_DEFAULT_SCHED_QUEUE     = 0x83,
  60         MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
  61         MLX4_IB_LINK_TYPE_IB            = 0,
  62         MLX4_IB_LINK_TYPE_ETH           = 1
  63 };
  64
  65 enum {
  66         /*
  67          * Largest possible UD header: send with GRH and immediate
  68          * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
  69          * tag.  (LRH would only use 8 bytes, so Ethernet is the
  70          * biggest case)
  71          */
  72         MLX4_IB_UD_HEADER_SIZE          = 82,
  73         MLX4_IB_LSO_HEADER_SPARE        = 128,
  74 };
  75
  76 enum {
  77         MLX4_IB_IBOE_ETHERTYPE          = 0x8915
  78 };
  79
  80 struct mlx4_ib_sqp {
  81         struct mlx4_ib_qp       qp;
  82         int                     pkey_index;
  83         u32                     qkey;
  84         u32                     send_psn;
  85         struct ib_ud_header     ud_header;
  86         u8                      header_buf[MLX4_IB_UD_HEADER_SIZE];
  87 };
  88
  89 enum {
  90         MLX4_IB_MIN_SQ_STRIDE   = 6,
  91         MLX4_IB_CACHE_LINE_SIZE = 64,
  92 };
  93
  94 enum {
  95         MLX4_RAW_QP_MTU         = 7,
  96         MLX4_RAW_QP_MSGMAX      = 31,
  97 };
  98
  99 #ifndef ETH_ALEN
 100 #define ETH_ALEN        6
 101 #endif
 102
 103 static const __be32 mlx4_ib_opcode[] = {
 104         [IB_WR_SEND]                            = cpu_to_be32(MLX4_OPCODE_SEND),
 105         [IB_WR_LSO]                             = cpu_to_be32(MLX4_OPCODE_LSO),
 106         [IB_WR_SEND_WITH_IMM]                   = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
 107         [IB_WR_RDMA_WRITE]                      = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
 108         [IB_WR_RDMA_WRITE_WITH_IMM]             = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
 109         [IB_WR_RDMA_READ]                       = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
 110         [IB_WR_ATOMIC_CMP_AND_SWP]              = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
 111         [IB_WR_ATOMIC_FETCH_AND_ADD]            = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
 112         [IB_WR_SEND_WITH_INV]                   = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
 113         [IB_WR_LOCAL_INV]                       = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
 114         [IB_WR_REG_MR]                          = cpu_to_be32(MLX4_OPCODE_FMR),
 115         [IB_WR_MASKED_ATOMIC_CMP_AND_SWP]       = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
 116         [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD]     = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
 117         [IB_WR_BIND_MW]                         = cpu_to_be32(MLX4_OPCODE_BIND_MW),
 118 };
 119
 120 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
 121 {
 122         return container_of(mqp, struct mlx4_ib_sqp, qp);
 123 }
 124
 125 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 126 {
 127         if (!mlx4_is_master(dev->dev))
 128                 return 0;
 129
 130         return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
 131                qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
 132                 8 * MLX4_MFUNC_MAX;
 133 }
 134
 135 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 136 {
 137         int proxy_sqp = 0;
 138         int real_sqp = 0;
 139         int i;
 140         /* PPF or Native -- real SQP */
 141         real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 142                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 143                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
 144         if (real_sqp)
 145                 return 1;
 146         /* VF or PF -- proxy SQP */
 147         if (mlx4_is_mfunc(dev->dev)) {
 148                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 149                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i] ||
 150                             qp->mqp.qpn == dev->dev->caps.qp1_proxy[i]) {
 151                                 proxy_sqp = 1;
 152                                 break;
 153                         }
 154                 }
 155         }
 156         return proxy_sqp;
 157 }
 158
 159 /* used for INIT/CLOSE port logic */
 160 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
 161 {
 162         int proxy_qp0 = 0;
 163         int real_qp0 = 0;
 164         int i;
 165         /* PPF or Native -- real QP0 */
 166         real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
 167                     qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
 168                     qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
 169         if (real_qp0)
 170                 return 1;
 171         /* VF or PF -- proxy QP0 */
 172         if (mlx4_is_mfunc(dev->dev)) {
 173                 for (i = 0; i < dev->dev->caps.num_ports; i++) {
 174                         if (qp->mqp.qpn == dev->dev->caps.qp0_proxy[i]) {
 175                                 proxy_qp0 = 1;
 176                                 break;
 177                         }
 178                 }
 179         }
 180         return proxy_qp0;
 181 }
 182
 183 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
 184 {
 185         return mlx4_buf_offset(&qp->buf, offset);
 186 }
 187
 188 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
 189 {
 190         return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
 191 }
 192
 193 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
 194 {
 195         return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
 196 }
 197
 198 /*
 199  * Stamp a SQ WQE so that it is invalid if prefetched by marking the
 200  * first four bytes of every 64 byte chunk with
 201  *     0x7FFFFFF | (invalid_ownership_value << 31).
 202  *
 203  * When the max work request size is less than or equal to the WQE
 204  * basic block size, as an optimization, we can stamp all WQEs with
 205  * 0xffffffff, and skip the very first chunk of each WQE.
 206  */
 207 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
 208 {
 209         __be32 *wqe;
 210         int i;
 211         int s;
 212         int ind;
 213         void *buf;
 214         __be32 stamp;
 215         struct mlx4_wqe_ctrl_seg *ctrl;
 216
 217         if (qp->sq_max_wqes_per_wr > 1) {
 218                 s = roundup(size, 1U << qp->sq.wqe_shift);
 219                 for (i = 0; i < s; i += 64) {
 220                         ind = (i >> qp->sq.wqe_shift) + n;
 221                         stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
 222                                                        cpu_to_be32(0xffffffff);
 223                         buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
 224                         wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
 225                         *wqe = stamp;
 226                 }
 227         } else {
 228                 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 229                 s = (ctrl->fence_size & 0x3f) << 4;
 230                 for (i = 64; i < s; i += 64) {
 231                         wqe = buf + i;
 232                         *wqe = cpu_to_be32(0xffffffff);
 233                 }
 234         }
 235 }
 236
 237 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
 238 {
 239         struct mlx4_wqe_ctrl_seg *ctrl;
 240         struct mlx4_wqe_inline_seg *inl;
 241         void *wqe;
 242         int s;
 243
 244         ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
 245         s = sizeof(struct mlx4_wqe_ctrl_seg);
 246
 247         if (qp->ibqp.qp_type == IB_QPT_UD) {
 248                 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
 249                 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
 250                 memset(dgram, 0, sizeof *dgram);
 251                 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
 252                 s += sizeof(struct mlx4_wqe_datagram_seg);
 253         }
 254
 255         /* Pad the remainder of the WQE with an inline data segment. */
 256         if (size > s) {
 257                 inl = wqe + s;
 258                 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
 259         }
 260         ctrl->srcrb_flags = 0;
 261         ctrl->fence_size = size / 16;
 262         /*
 263          * Make sure descriptor is fully written before setting ownership bit
 264          * (because HW can start executing as soon as we do).
 265          */
 266         wmb();
 267
 268         ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
 269                 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
 270
 271         stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
 272 }
 273
 274 /* Post NOP WQE to prevent wrap-around in the middle of WR */
 275 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
 276 {
 277         unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
 278         if (unlikely(s < qp->sq_max_wqes_per_wr)) {
 279                 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
 280                 ind += s;
 281         }
 282         return ind;
 283 }
 284
 285 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
 286 {
 287         struct ib_event event;
 288         struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
 289
 290         if (type == MLX4_EVENT_TYPE_PATH_MIG)
 291                 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
 292
 293         if (ibqp->event_handler) {
 294                 event.device     = ibqp->device;
 295                 event.element.qp = ibqp;
 296                 switch (type) {
 297                 case MLX4_EVENT_TYPE_PATH_MIG:
 298                         event.event = IB_EVENT_PATH_MIG;
 299                         break;
 300                 case MLX4_EVENT_TYPE_COMM_EST:
 301                         event.event = IB_EVENT_COMM_EST;
 302                         break;
 303                 case MLX4_EVENT_TYPE_SQ_DRAINED:
 304                         event.event = IB_EVENT_SQ_DRAINED;
 305                         break;
 306                 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
 307                         event.event = IB_EVENT_QP_LAST_WQE_REACHED;
 308                         break;
 309                 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
 310                         event.event = IB_EVENT_QP_FATAL;
 311                         break;
 312                 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
 313                         event.event = IB_EVENT_PATH_MIG_ERR;
 314                         break;
 315                 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
 316                         event.event = IB_EVENT_QP_REQ_ERR;
 317                         break;
 318                 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
 319                         event.event = IB_EVENT_QP_ACCESS_ERR;
 320                         break;
 321                 default:
 322                         pr_warn("Unexpected event type %d "
 323                                "on QP %06x\n", type, qp->qpn);
 324                         return;
 325                 }
 326
 327                 ibqp->event_handler(&event, ibqp->qp_context);
 328         }
 329 }
 330
 331 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
 332 {
 333         /*
 334          * UD WQEs must have a datagram segment.
 335          * RC and UC WQEs might have a remote address segment.
 336          * MLX WQEs need two extra inline data segments (for the UD
 337          * header and space for the ICRC).
 338          */
 339         switch (type) {
 340         case MLX4_IB_QPT_UD:
 341                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 342                         sizeof (struct mlx4_wqe_datagram_seg) +
 343                         ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
 344         case MLX4_IB_QPT_PROXY_SMI_OWNER:
 345         case MLX4_IB_QPT_PROXY_SMI:
 346         case MLX4_IB_QPT_PROXY_GSI:
 347                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 348                         sizeof (struct mlx4_wqe_datagram_seg) + 64;
 349         case MLX4_IB_QPT_TUN_SMI_OWNER:
 350         case MLX4_IB_QPT_TUN_GSI:
 351                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 352                         sizeof (struct mlx4_wqe_datagram_seg);
 353
 354         case MLX4_IB_QPT_UC:
 355                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 356                         sizeof (struct mlx4_wqe_raddr_seg);
 357         case MLX4_IB_QPT_RC:
 358                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 359                         sizeof (struct mlx4_wqe_atomic_seg) +
 360                         sizeof (struct mlx4_wqe_raddr_seg);
 361         case MLX4_IB_QPT_SMI:
 362         case MLX4_IB_QPT_GSI:
 363                 return sizeof (struct mlx4_wqe_ctrl_seg) +
 364                         ALIGN(MLX4_IB_UD_HEADER_SIZE +
 365                               DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
 366                                            MLX4_INLINE_ALIGN) *
 367                               sizeof (struct mlx4_wqe_inline_seg),
 368                               sizeof (struct mlx4_wqe_data_seg)) +
 369                         ALIGN(4 +
 370                               sizeof (struct mlx4_wqe_inline_seg),
 371                               sizeof (struct mlx4_wqe_data_seg));
 372         default:
 373                 return sizeof (struct mlx4_wqe_ctrl_seg);
 374         }
 375 }
 376
 377 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 378                        int is_user, int has_rq, struct mlx4_ib_qp *qp)
 379 {
 380         /* Sanity check RQ size before proceeding */
 381         if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
 382             cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
 383                 return -EINVAL;
 384
 385         if (!has_rq) {
 386                 if (cap->max_recv_wr)
 387                         return -EINVAL;
 388
 389                 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
 390         } else {
 391                 /* HW requires >= 1 RQ entry with >= 1 gather entry */
 392                 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
 393                         return -EINVAL;
 394
 395                 qp->rq.wqe_cnt   = roundup_pow_of_two(max(1U, cap->max_recv_wr));
 396                 qp->rq.max_gs    = roundup_pow_of_two(max(1U, cap->max_recv_sge));
 397                 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
 398         }
 399
 400         /* leave userspace return values as they were, so as not to break ABI */
 401         if (is_user) {
 402                 cap->max_recv_wr  = qp->rq.max_post = qp->rq.wqe_cnt;
 403                 cap->max_recv_sge = qp->rq.max_gs;
 404         } else {
 405                 cap->max_recv_wr  = qp->rq.max_post =
 406                         min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
 407                 cap->max_recv_sge = min(qp->rq.max_gs,
 408                                         min(dev->dev->caps.max_sq_sg,
 409                                             dev->dev->caps.max_rq_sg));
 410         }
 411
 412         return 0;
 413 }
 414
 415 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
 416                               enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
 417 {
 418         int s;
 419
 420         /* Sanity check SQ size before proceeding */
 421         if (cap->max_send_wr  > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
 422             cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
 423             cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
 424             sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
 425                 return -EINVAL;
 426
 427         /*
 428          * For MLX transport we need 2 extra S/G entries:
 429          * one for the header and one for the checksum at the end
 430          */
 431         if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
 432              type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
 433             cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
 434                 return -EINVAL;
 435
 436         s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
 437                 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
 438                 send_wqe_overhead(type, qp->flags);
 439
 440         if (s > dev->dev->caps.max_sq_desc_sz)
 441                 return -EINVAL;
 442
 443         /*
 444          * Hermon supports shrinking WQEs, such that a single work
 445          * request can include multiple units of 1 << wqe_shift.  This
 446          * way, work requests can differ in size, and do not have to
 447          * be a power of 2 in size, saving memory and speeding up send
 448          * WR posting.  Unfortunately, if we do this then the
 449          * wqe_index field in CQEs can't be used to look up the WR ID
 450          * anymore, so we do this only if selective signaling is off.
 451          *
 452          * Further, on 32-bit platforms, we can't use vmap() to make
 453          * the QP buffer virtually contiguous.  Thus we have to use
 454          * constant-sized WRs to make sure a WR is always fully within
 455          * a single page-sized chunk.
 456          *
 457          * Finally, we use NOP work requests to pad the end of the
 458          * work queue, to avoid wrap-around in the middle of WR.  We
 459          * set NEC bit to avoid getting completions with error for
 460          * these NOP WRs, but since NEC is only supported starting
 461          * with firmware 2.2.232, we use constant-sized WRs for older
 462          * firmware.
 463          *
 464          * And, since MLX QPs only support SEND, we use constant-sized
 465          * WRs in this case.
 466          *
 467          * We look for the smallest value of wqe_shift such that the
 468          * resulting number of wqes does not exceed device
 469          * capabilities.
 470          *
 471          * We set WQE size to at least 64 bytes, this way stamping
 472          * invalidates each WQE.
 473          */
 474         if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
 475             qp->sq_signal_bits && BITS_PER_LONG == 64 &&
 476             type != MLX4_IB_QPT_SMI && type != MLX4_IB_QPT_GSI &&
 477             !(type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_PROXY_SMI |
 478                       MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER)))
 479                 qp->sq.wqe_shift = ilog2(64);
 480         else
 481                 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
 482
 483         for (;;) {
 484                 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
 485
 486                 /*
 487                  * We need to leave 2 KB + 1 WR of headroom in the SQ to
 488                  * allow HW to prefetch.
 489                  */
 490                 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
 491                 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
 492                                                     qp->sq_max_wqes_per_wr +
 493                                                     qp->sq_spare_wqes);
 494
 495                 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
 496                         break;
 497
 498                 if (qp->sq_max_wqes_per_wr <= 1)
 499                         return -EINVAL;
 500
 501                 ++qp->sq.wqe_shift;
 502         }
 503
 504         qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
 505                              (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
 506                          send_wqe_overhead(type, qp->flags)) /
 507                 sizeof (struct mlx4_wqe_data_seg);
 508
 509         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 510                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 511         if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
 512                 qp->rq.offset = 0;
 513                 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
 514         } else {
 515                 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
 516                 qp->sq.offset = 0;
 517         }
 518
 519         cap->max_send_wr  = qp->sq.max_post =
 520                 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
 521         cap->max_send_sge = min(qp->sq.max_gs,
 522                                 min(dev->dev->caps.max_sq_sg,
 523                                     dev->dev->caps.max_rq_sg));
 524         /* We don't support inline sends for kernel QPs (yet) */
 525         cap->max_inline_data = 0;
 526
 527         return 0;
 528 }
 529
 530 static int set_user_sq_size(struct mlx4_ib_dev *dev,
 531                             struct mlx4_ib_qp *qp,
 532                             struct mlx4_ib_create_qp *ucmd)
 533 {
 534         /* Sanity check SQ size before proceeding */
 535         if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes       ||
 536             ucmd->log_sq_stride >
 537                 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
 538             ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
 539                 return -EINVAL;
 540
 541         qp->sq.wqe_cnt   = 1 << ucmd->log_sq_bb_count;
 542         qp->sq.wqe_shift = ucmd->log_sq_stride;
 543
 544         qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
 545                 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
 546
 547         return 0;
 548 }
 549
 550 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 551 {
 552         int i;
 553
 554         qp->sqp_proxy_rcv =
 555                 kmalloc(sizeof (struct mlx4_ib_buf) * qp->rq.wqe_cnt,
 556                         GFP_KERNEL);
 557         if (!qp->sqp_proxy_rcv)
 558                 return -ENOMEM;
 559         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 560                 qp->sqp_proxy_rcv[i].addr =
 561                         kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
 562                                 GFP_KERNEL);
 563                 if (!qp->sqp_proxy_rcv[i].addr)
 564                         goto err;
 565                 qp->sqp_proxy_rcv[i].map =
 566                         ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
 567                                           sizeof (struct mlx4_ib_proxy_sqp_hdr),
 568                                           DMA_FROM_DEVICE);
 569                 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
 570                         kfree(qp->sqp_proxy_rcv[i].addr);
 571                         goto err;
 572                 }
 573         }
 574         return 0;
 575
 576 err:
 577         while (i > 0) {
 578                 --i;
 579                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 580                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 581                                     DMA_FROM_DEVICE);
 582                 kfree(qp->sqp_proxy_rcv[i].addr);
 583         }
 584         kfree(qp->sqp_proxy_rcv);
 585         qp->sqp_proxy_rcv = NULL;
 586         return -ENOMEM;
 587 }
 588
 589 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
 590 {
 591         int i;
 592
 593         for (i = 0; i < qp->rq.wqe_cnt; i++) {
 594                 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
 595                                     sizeof (struct mlx4_ib_proxy_sqp_hdr),
 596                                     DMA_FROM_DEVICE);
 597                 kfree(qp->sqp_proxy_rcv[i].addr);
 598         }
 599         kfree(qp->sqp_proxy_rcv);
 600 }
 601
 602 static int qp_has_rq(struct ib_qp_init_attr *attr)
 603 {
 604         if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
 605                 return 0;
 606
 607         return !attr->srq;
 608 }
 609
 610 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
 611 {
 612         int i;
 613         for (i = 0; i < dev->caps.num_ports; i++) {
 614                 if (qpn == dev->caps.qp0_proxy[i])
 615                         return !!dev->caps.qp0_qkey[i];
 616         }
 617         return 0;
 618 }
 619
 620 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
 621                                     struct mlx4_ib_qp *qp)
 622 {
 623         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
 624         mlx4_counter_free(dev->dev, qp->counter_index->index);
 625         list_del(&qp->counter_index->list);
 626         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
 627
 628         kfree(qp->counter_index);
 629         qp->counter_index = NULL;
 630 }
 631
 632 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
 633                             struct ib_qp_init_attr *init_attr,
 634                             struct ib_udata *udata, int sqpn, struct mlx4_ib_qp **caller_qp,
 635                             gfp_t gfp)
 636 {
 637         int qpn;
 638         int err;
 639         struct mlx4_ib_sqp *sqp;
 640         struct mlx4_ib_qp *qp;
 641         enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
 642         struct mlx4_ib_cq *mcq;
 643         unsigned long flags;
 644
 645         /* When tunneling special qps, we use a plain UD qp */
 646         if (sqpn) {
 647                 if (mlx4_is_mfunc(dev->dev) &&
 648                     (!mlx4_is_master(dev->dev) ||
 649                      !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
 650                         if (init_attr->qp_type == IB_QPT_GSI)
 651                                 qp_type = MLX4_IB_QPT_PROXY_GSI;
 652                         else {
 653                                 if (mlx4_is_master(dev->dev) ||
 654                                     qp0_enabled_vf(dev->dev, sqpn))
 655                                         qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
 656                                 else
 657                                         qp_type = MLX4_IB_QPT_PROXY_SMI;
 658                         }
 659                 }
 660                 qpn = sqpn;
 661                 /* add extra sg entry for tunneling */
 662                 init_attr->cap.max_recv_sge++;
 663         } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
 664                 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
 665                         container_of(init_attr,
 666                                      struct mlx4_ib_qp_tunnel_init_attr, init_attr);
 667                 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
 668                      tnl_init->proxy_qp_type != IB_QPT_GSI)   ||
 669                     !mlx4_is_master(dev->dev))
 670                         return -EINVAL;
 671                 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
 672                         qp_type = MLX4_IB_QPT_TUN_GSI;
 673                 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
 674                          mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
 675                                              tnl_init->port))
 676                         qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
 677                 else
 678                         qp_type = MLX4_IB_QPT_TUN_SMI;
 679                 /* we are definitely in the PPF here, since we are creating
 680                  * tunnel QPs. base_tunnel_sqpn is therefore valid. */
 681                 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
 682                         + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
 683                 sqpn = qpn;
 684         }
 685
 686         if (!*caller_qp) {
 687                 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
 688                     (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
 689                                 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
 690                         sqp = kzalloc(sizeof (struct mlx4_ib_sqp), gfp);
 691                         if (!sqp)
 692                                 return -ENOMEM;
 693                         qp = &sqp->qp;
 694                         qp->pri.vid = 0xFFFF;
 695                         qp->alt.vid = 0xFFFF;
 696                 } else {
 697                         qp = kzalloc(sizeof (struct mlx4_ib_qp), gfp);
 698                         if (!qp)
 699                                 return -ENOMEM;
 700                         qp->pri.vid = 0xFFFF;
 701                         qp->alt.vid = 0xFFFF;
 702                 }
 703         } else
 704                 qp = *caller_qp;
 705
 706         qp->mlx4_ib_qp_type = qp_type;
 707
 708         mutex_init(&qp->mutex);
 709         spin_lock_init(&qp->sq.lock);
 710         spin_lock_init(&qp->rq.lock);
 711         INIT_LIST_HEAD(&qp->gid_list);
 712         INIT_LIST_HEAD(&qp->steering_rules);
 713
 714         qp->state        = IB_QPS_RESET;
 715         if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
 716                 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
 717
 718         err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, qp_has_rq(init_attr), qp);
 719         if (err)
 720                 goto err;
 721
 722         if (pd->uobject) {
 723                 struct mlx4_ib_create_qp ucmd;
 724
 725                 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
 726                         err = -EFAULT;
 727                         goto err;
 728                 }
 729
 730                 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
 731
 732                 err = set_user_sq_size(dev, qp, &ucmd);
 733                 if (err)
 734                         goto err;
 735
 736                 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
 737                                        qp->buf_size, 0, 0);
 738                 if (IS_ERR(qp->umem)) {
 739                         err = PTR_ERR(qp->umem);
 740                         goto err;
 741                 }
 742
 743                 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
 744                                     ilog2(qp->umem->page_size), &qp->mtt);
 745                 if (err)
 746                         goto err_buf;
 747
 748                 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
 749                 if (err)
 750                         goto err_mtt;
 751
 752                 if (qp_has_rq(init_attr)) {
 753                         err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
 754                                                   ucmd.db_addr, &qp->db);
 755                         if (err)
 756                                 goto err_mtt;
 757                 }
 758         } else {
 759                 qp->sq_no_prefetch = 0;
 760
 761                 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
 762                         qp->flags |= MLX4_IB_QP_LSO;
 763
 764                 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
 765                         if (dev->steering_support ==
 766                             MLX4_STEERING_MODE_DEVICE_MANAGED)
 767                                 qp->flags |= MLX4_IB_QP_NETIF;
 768                         else
 769                                 goto err;
 770                 }
 771
 772                 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
 773                 if (err)
 774                         goto err;
 775
 776                 if (qp_has_rq(init_attr)) {
 777                         err = mlx4_db_alloc(dev->dev, &qp->db, 0, gfp);
 778                         if (err)
 779                                 goto err;
 780
 781                         *qp->db.db = 0;
 782                 }
 783
 784                 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) {
 785                         err = -ENOMEM;
 786                         goto err_db;
 787                 }
 788
 789                 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
 790                                     &qp->mtt);
 791                 if (err)
 792                         goto err_buf;
 793
 794                 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf, gfp);
 795                 if (err)
 796                         goto err_mtt;
 797
 798                 qp->sq.wrid  = kmalloc(qp->sq.wqe_cnt * sizeof (u64), gfp);
 799                 qp->rq.wrid  = kmalloc(qp->rq.wqe_cnt * sizeof (u64), gfp);
 800                 if (!qp->sq.wrid || !qp->rq.wrid) {
 801                         err = -ENOMEM;
 802                         goto err_wrid;
 803                 }
 804         }
 805
 806         if (sqpn) {
 807                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
 808                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
 809                         if (alloc_proxy_bufs(pd->device, qp)) {
 810                                 err = -ENOMEM;
 811                                 goto err_wrid;
 812                         }
 813                 }
 814         } else {
 815                 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
 816                  * otherwise, the WQE BlueFlame setup flow wrongly causes
 817                  * VLAN insertion. */
 818                 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
 819                         err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
 820                                                     (init_attr->cap.max_send_wr ?
 821                                                      MLX4_RESERVE_ETH_BF_QP : 0) |
 822                                                     (init_attr->cap.max_recv_wr ?
 823                                                      MLX4_RESERVE_A0_QP : 0));
 824                 else
 825                         if (qp->flags & MLX4_IB_QP_NETIF)
 826                                 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
 827                         else
 828                                 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
 829                                                             &qpn, 0);
 830                 if (err)
 831                         goto err_proxy;
 832         }
 833
 834         if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
 835                 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
 836
 837         err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp, gfp);
 838         if (err)
 839                 goto err_qpn;
 840
 841         if (init_attr->qp_type == IB_QPT_XRC_TGT)
 842                 qp->mqp.qpn |= (1 << 23);
 843
 844         /*
 845          * Hardware wants QPN written in big-endian order (after
 846          * shifting) for send doorbell.  Precompute this value to save
 847          * a little bit when posting sends.
 848          */
 849         qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
 850
 851         qp->mqp.event = mlx4_ib_qp_event;
 852         if (!*caller_qp)
 853                 *caller_qp = qp;
 854
 855         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
 856         mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
 857                          to_mcq(init_attr->recv_cq));
 858         /* Maintain device to QPs access, needed for further handling
 859          * via reset flow
 860          */
 861         list_add_tail(&qp->qps_list, &dev->qp_list);
 862         /* Maintain CQ to QPs access, needed for further handling
 863          * via reset flow
 864          */
 865         mcq = to_mcq(init_attr->send_cq);
 866         list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
 867         mcq = to_mcq(init_attr->recv_cq);
 868         list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
 869         mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
 870                            to_mcq(init_attr->recv_cq));
 871         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
 872         return 0;
 873
 874 err_qpn:
 875         if (!sqpn) {
 876                 if (qp->flags & MLX4_IB_QP_NETIF)
 877                         mlx4_ib_steer_qp_free(dev, qpn, 1);
 878                 else
 879                         mlx4_qp_release_range(dev->dev, qpn, 1);
 880         }
 881 err_proxy:
 882         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
 883                 free_proxy_bufs(pd->device, qp);
 884 err_wrid:
 885         if (pd->uobject) {
 886                 if (qp_has_rq(init_attr))
 887                         mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
 888         } else {
 889                 kfree(qp->sq.wrid);
 890                 kfree(qp->rq.wrid);
 891         }
 892
 893 err_mtt:
 894         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
 895
 896 err_buf:
 897         if (pd->uobject)
 898                 ib_umem_release(qp->umem);
 899         else
 900                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
 901
 902 err_db:
 903         if (!pd->uobject && qp_has_rq(init_attr))
 904                 mlx4_db_free(dev->dev, &qp->db);
 905
 906 err:
 907         if (!*caller_qp)
 908                 kfree(qp);
 909         return err;
 910 }
 911
 912 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
 913 {
 914         switch (state) {
 915         case IB_QPS_RESET:      return MLX4_QP_STATE_RST;
 916         case IB_QPS_INIT:       return MLX4_QP_STATE_INIT;
 917         case IB_QPS_RTR:        return MLX4_QP_STATE_RTR;
 918         case IB_QPS_RTS:        return MLX4_QP_STATE_RTS;
 919         case IB_QPS_SQD:        return MLX4_QP_STATE_SQD;
 920         case IB_QPS_SQE:        return MLX4_QP_STATE_SQER;
 921         case IB_QPS_ERR:        return MLX4_QP_STATE_ERR;
 922         default:                return -1;
 923         }
 924 }
 925
 926 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 927         __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
 928 {
 929         if (send_cq == recv_cq) {
 930                 spin_lock(&send_cq->lock);
 931                 __acquire(&recv_cq->lock);
 932         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 933                 spin_lock(&send_cq->lock);
 934                 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
 935         } else {
 936                 spin_lock(&recv_cq->lock);
 937                 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
 938         }
 939 }
 940
 941 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
 942         __releases(&send_cq->lock) __releases(&recv_cq->lock)
 943 {
 944         if (send_cq == recv_cq) {
 945                 __release(&recv_cq->lock);
 946                 spin_unlock(&send_cq->lock);
 947         } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
 948                 spin_unlock(&recv_cq->lock);
 949                 spin_unlock(&send_cq->lock);
 950         } else {
 951                 spin_unlock(&send_cq->lock);
 952                 spin_unlock(&recv_cq->lock);
 953         }
 954 }
 955
 956 static void del_gid_entries(struct mlx4_ib_qp *qp)
 957 {
 958         struct mlx4_ib_gid_entry *ge, *tmp;
 959
 960         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
 961                 list_del(&ge->list);
 962                 kfree(ge);
 963         }
 964 }
 965
 966 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
 967 {
 968         if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
 969                 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
 970         else
 971                 return to_mpd(qp->ibqp.pd);
 972 }
 973
 974 static void get_cqs(struct mlx4_ib_qp *qp,
 975                     struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
 976 {
 977         switch (qp->ibqp.qp_type) {
 978         case IB_QPT_XRC_TGT:
 979                 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
 980                 *recv_cq = *send_cq;
 981                 break;
 982         case IB_QPT_XRC_INI:
 983                 *send_cq = to_mcq(qp->ibqp.send_cq);
 984                 *recv_cq = *send_cq;
 985                 break;
 986         default:
 987                 *send_cq = to_mcq(qp->ibqp.send_cq);
 988                 *recv_cq = to_mcq(qp->ibqp.recv_cq);
 989                 break;
 990         }
 991 }
 992
 993 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
 994                               int is_user)
 995 {
 996         struct mlx4_ib_cq *send_cq, *recv_cq;
 997         unsigned long flags;
 998
 999         if (qp->state != IB_QPS_RESET) {
1000                 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1001                                    MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1002                         pr_warn("modify QP %06x to RESET failed.\n",
1003                                qp->mqp.qpn);
1004                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1005                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1006                         qp->pri.smac = 0;
1007                         qp->pri.smac_port = 0;
1008                 }
1009                 if (qp->alt.smac) {
1010                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1011                         qp->alt.smac = 0;
1012                 }
1013                 if (qp->pri.vid < 0x1000) {
1014                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1015                         qp->pri.vid = 0xFFFF;
1016                         qp->pri.candidate_vid = 0xFFFF;
1017                         qp->pri.update_vid = 0;
1018                 }
1019                 if (qp->alt.vid < 0x1000) {
1020                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1021                         qp->alt.vid = 0xFFFF;
1022                         qp->alt.candidate_vid = 0xFFFF;
1023                         qp->alt.update_vid = 0;
1024                 }
1025         }
1026
1027         get_cqs(qp, &send_cq, &recv_cq);
1028
1029         spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1030         mlx4_ib_lock_cqs(send_cq, recv_cq);
1031
1032         /* del from lists under both locks above to protect reset flow paths */
1033         list_del(&qp->qps_list);
1034         list_del(&qp->cq_send_list);
1035         list_del(&qp->cq_recv_list);
1036         if (!is_user) {
1037                 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1038                                  qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1039                 if (send_cq != recv_cq)
1040                         __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1041         }
1042
1043         mlx4_qp_remove(dev->dev, &qp->mqp);
1044
1045         mlx4_ib_unlock_cqs(send_cq, recv_cq);
1046         spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1047
1048         mlx4_qp_free(dev->dev, &qp->mqp);
1049
1050         if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1051                 if (qp->flags & MLX4_IB_QP_NETIF)
1052                         mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1053                 else
1054                         mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1055         }
1056
1057         mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1058
1059         if (is_user) {
1060                 if (qp->rq.wqe_cnt)
1061                         mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
1062                                               &qp->db);
1063                 ib_umem_release(qp->umem);
1064         } else {
1065                 kfree(qp->sq.wrid);
1066                 kfree(qp->rq.wrid);
1067                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1068                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1069                         free_proxy_bufs(&dev->ib_dev, qp);
1070                 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1071                 if (qp->rq.wqe_cnt)
1072                         mlx4_db_free(dev->dev, &qp->db);
1073         }
1074
1075         del_gid_entries(qp);
1076 }
1077
1078 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1079 {
1080         /* Native or PPF */
1081         if (!mlx4_is_mfunc(dev->dev) ||
1082             (mlx4_is_master(dev->dev) &&
1083              attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1084                 return  dev->dev->phys_caps.base_sqpn +
1085                         (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1086                         attr->port_num - 1;
1087         }
1088         /* PF or VF -- creating proxies */
1089         if (attr->qp_type == IB_QPT_SMI)
1090                 return dev->dev->caps.qp0_proxy[attr->port_num - 1];
1091         else
1092                 return dev->dev->caps.qp1_proxy[attr->port_num - 1];
1093 }
1094
1095 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1096                                 struct ib_qp_init_attr *init_attr,
1097                                 struct ib_udata *udata)
1098 {
1099         struct mlx4_ib_qp *qp = NULL;
1100         int err;
1101         int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1102         u16 xrcdn = 0;
1103         gfp_t gfp;
1104
1105         gfp = (init_attr->create_flags & MLX4_IB_QP_CREATE_USE_GFP_NOIO) ?
1106                 GFP_NOIO : GFP_KERNEL;
1107         /*
1108          * We only support LSO, vendor flag1, and multicast loopback blocking,
1109          * and only for kernel UD QPs.
1110          */
1111         if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1112                                         MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1113                                         MLX4_IB_SRIOV_TUNNEL_QP |
1114                                         MLX4_IB_SRIOV_SQP |
1115                                         MLX4_IB_QP_NETIF |
1116                                         MLX4_IB_QP_CREATE_USE_GFP_NOIO))
1117                 return ERR_PTR(-EINVAL);
1118
1119         if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1120                 if (init_attr->qp_type != IB_QPT_UD)
1121                         return ERR_PTR(-EINVAL);
1122         }
1123
1124         if (init_attr->create_flags &&
1125             ((udata && init_attr->create_flags & ~(sup_u_create_flags)) ||
1126              ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1127                                            MLX4_IB_QP_CREATE_USE_GFP_NOIO |
1128                                            MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)) &&
1129               init_attr->qp_type != IB_QPT_UD) ||
1130              ((init_attr->create_flags & MLX4_IB_SRIOV_SQP) &&
1131               init_attr->qp_type > IB_QPT_GSI)))
1132                 return ERR_PTR(-EINVAL);
1133
1134         switch (init_attr->qp_type) {
1135         case IB_QPT_XRC_TGT:
1136                 pd = to_mxrcd(init_attr->xrcd)->pd;
1137                 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1138                 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1139                 /* fall through */
1140         case IB_QPT_XRC_INI:
1141                 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1142                         return ERR_PTR(-ENOSYS);
1143                 init_attr->recv_cq = init_attr->send_cq;
1144                 /* fall through */
1145         case IB_QPT_RC:
1146         case IB_QPT_UC:
1147         case IB_QPT_RAW_PACKET:
1148                 qp = kzalloc(sizeof *qp, gfp);
1149                 if (!qp)
1150                         return ERR_PTR(-ENOMEM);
1151                 qp->pri.vid = 0xFFFF;
1152                 qp->alt.vid = 0xFFFF;
1153                 /* fall through */
1154         case IB_QPT_UD:
1155         {
1156                 err = create_qp_common(to_mdev(pd->device), pd, init_attr,
1157                                        udata, 0, &qp, gfp);
1158                 if (err)
1159                         return ERR_PTR(err);
1160
1161                 qp->ibqp.qp_num = qp->mqp.qpn;
1162                 qp->xrcdn = xrcdn;
1163
1164                 break;
1165         }
1166         case IB_QPT_SMI:
1167         case IB_QPT_GSI:
1168         {
1169                 /* Userspace is not allowed to create special QPs: */
1170                 if (udata)
1171                         return ERR_PTR(-EINVAL);
1172
1173                 err = create_qp_common(to_mdev(pd->device), pd, init_attr, udata,
1174                                        get_sqp_num(to_mdev(pd->device), init_attr),
1175                                        &qp, gfp);
1176                 if (err)
1177                         return ERR_PTR(err);
1178
1179                 qp->port        = init_attr->port_num;
1180                 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
1181
1182                 break;
1183         }
1184         default:
1185                 /* Don't support raw QPs */
1186                 return ERR_PTR(-EINVAL);
1187         }
1188
1189         return &qp->ibqp;
1190 }
1191
1192 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1193 {
1194         struct mlx4_ib_dev *dev = to_mdev(qp->device);
1195         struct mlx4_ib_qp *mqp = to_mqp(qp);
1196         struct mlx4_ib_pd *pd;
1197
1198         if (is_qp0(dev, mqp))
1199                 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1200
1201         if (dev->qp1_proxy[mqp->port - 1] == mqp) {
1202                 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1203                 dev->qp1_proxy[mqp->port - 1] = NULL;
1204                 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1205         }
1206
1207         if (mqp->counter_index)
1208                 mlx4_ib_free_qp_counter(dev, mqp);
1209
1210         pd = get_pd(mqp);
1211         destroy_qp_common(dev, mqp, !!pd->ibpd.uobject);
1212
1213         if (is_sqp(dev, mqp))
1214                 kfree(to_msqp(mqp));
1215         else
1216                 kfree(mqp);
1217
1218         return 0;
1219 }
1220
1221 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1222 {
1223         switch (type) {
1224         case MLX4_IB_QPT_RC:            return MLX4_QP_ST_RC;
1225         case MLX4_IB_QPT_UC:            return MLX4_QP_ST_UC;
1226         case MLX4_IB_QPT_UD:            return MLX4_QP_ST_UD;
1227         case MLX4_IB_QPT_XRC_INI:
1228         case MLX4_IB_QPT_XRC_TGT:       return MLX4_QP_ST_XRC;
1229         case MLX4_IB_QPT_SMI:
1230         case MLX4_IB_QPT_GSI:
1231         case MLX4_IB_QPT_RAW_PACKET:    return MLX4_QP_ST_MLX;
1232
1233         case MLX4_IB_QPT_PROXY_SMI_OWNER:
1234         case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1235                                                 MLX4_QP_ST_MLX : -1);
1236         case MLX4_IB_QPT_PROXY_SMI:
1237         case MLX4_IB_QPT_TUN_SMI:
1238         case MLX4_IB_QPT_PROXY_GSI:
1239         case MLX4_IB_QPT_TUN_GSI:       return (mlx4_is_mfunc(dev->dev) ?
1240                                                 MLX4_QP_ST_UD : -1);
1241         default:                        return -1;
1242         }
1243 }
1244
1245 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1246                                    int attr_mask)
1247 {
1248         u8 dest_rd_atomic;
1249         u32 access_flags;
1250         u32 hw_access_flags = 0;
1251
1252         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1253                 dest_rd_atomic = attr->max_dest_rd_atomic;
1254         else
1255                 dest_rd_atomic = qp->resp_depth;
1256
1257         if (attr_mask & IB_QP_ACCESS_FLAGS)
1258                 access_flags = attr->qp_access_flags;
1259         else
1260                 access_flags = qp->atomic_rd_en;
1261
1262         if (!dest_rd_atomic)
1263                 access_flags &= IB_ACCESS_REMOTE_WRITE;
1264
1265         if (access_flags & IB_ACCESS_REMOTE_READ)
1266                 hw_access_flags |= MLX4_QP_BIT_RRE;
1267         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1268                 hw_access_flags |= MLX4_QP_BIT_RAE;
1269         if (access_flags & IB_ACCESS_REMOTE_WRITE)
1270                 hw_access_flags |= MLX4_QP_BIT_RWE;
1271
1272         return cpu_to_be32(hw_access_flags);
1273 }
1274
1275 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1276                             int attr_mask)
1277 {
1278         if (attr_mask & IB_QP_PKEY_INDEX)
1279                 sqp->pkey_index = attr->pkey_index;
1280         if (attr_mask & IB_QP_QKEY)
1281                 sqp->qkey = attr->qkey;
1282         if (attr_mask & IB_QP_SQ_PSN)
1283                 sqp->send_psn = attr->sq_psn;
1284 }
1285
1286 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1287 {
1288         path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1289 }
1290
1291 static int _mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
1292                           u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1293                           struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1294 {
1295         int is_eth = rdma_port_get_link_layer(&dev->ib_dev, port) ==
1296                 IB_LINK_LAYER_ETHERNET;
1297         int vidx;
1298         int smac_index;
1299         int err;
1300
1301
1302         path->grh_mylmc     = ah->src_path_bits & 0x7f;
1303         path->rlid          = cpu_to_be16(ah->dlid);
1304         if (ah->static_rate) {
1305                 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
1306                 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1307                        !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1308                         --path->static_rate;
1309         } else
1310                 path->static_rate = 0;
1311
1312         if (ah->ah_flags & IB_AH_GRH) {
1313                 int real_sgid_index = mlx4_ib_gid_index_to_real_index(dev,
1314                                                                       port,
1315                                                                       ah->grh.sgid_index);
1316
1317                 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1318                         pr_err("sgid_index (%u) too large. max is %d\n",
1319                                real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1320                         return -1;
1321                 }
1322
1323                 path->grh_mylmc |= 1 << 7;
1324                 path->mgid_index = real_sgid_index;
1325                 path->hop_limit  = ah->grh.hop_limit;
1326                 path->tclass_flowlabel =
1327                         cpu_to_be32((ah->grh.traffic_class << 20) |
1328                                     (ah->grh.flow_label));
1329                 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1330         }
1331
1332         if (is_eth) {
1333                 if (!(ah->ah_flags & IB_AH_GRH))
1334                         return -1;
1335
1336                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1337                         ((port - 1) << 6) | ((ah->sl & 7) << 3);
1338
1339                 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1340                 if (vlan_tag < 0x1000) {
1341                         if (smac_info->vid < 0x1000) {
1342                                 /* both valid vlan ids */
1343                                 if (smac_info->vid != vlan_tag) {
1344                                         /* different VIDs.  unreg old and reg new */
1345                                         err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1346                                         if (err)
1347                                                 return err;
1348                                         smac_info->candidate_vid = vlan_tag;
1349                                         smac_info->candidate_vlan_index = vidx;
1350                                         smac_info->candidate_vlan_port = port;
1351                                         smac_info->update_vid = 1;
1352                                         path->vlan_index = vidx;
1353                                 } else {
1354                                         path->vlan_index = smac_info->vlan_index;
1355                                 }
1356                         } else {
1357                                 /* no current vlan tag in qp */
1358                                 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1359                                 if (err)
1360                                         return err;
1361                                 smac_info->candidate_vid = vlan_tag;
1362                                 smac_info->candidate_vlan_index = vidx;
1363                                 smac_info->candidate_vlan_port = port;
1364                                 smac_info->update_vid = 1;
1365                                 path->vlan_index = vidx;
1366                         }
1367                         path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1368                         path->fl = 1 << 6;
1369                 } else {
1370                         /* have current vlan tag. unregister it at modify-qp success */
1371                         if (smac_info->vid < 0x1000) {
1372                                 smac_info->candidate_vid = 0xFFFF;
1373                                 smac_info->update_vid = 1;
1374                         }
1375                 }
1376
1377                 /* get smac_index for RoCE use.
1378                  * If no smac was yet assigned, register one.
1379                  * If one was already assigned, but the new mac differs,
1380                  * unregister the old one and register the new one.
1381                 */
1382                 if ((!smac_info->smac && !smac_info->smac_port) ||
1383                     smac_info->smac != smac) {
1384                         /* register candidate now, unreg if needed, after success */
1385                         smac_index = mlx4_register_mac(dev->dev, port, smac);
1386                         if (smac_index >= 0) {
1387                                 smac_info->candidate_smac_index = smac_index;
1388                                 smac_info->candidate_smac = smac;
1389                                 smac_info->candidate_smac_port = port;
1390                         } else {
1391                                 return -EINVAL;
1392                         }
1393                 } else {
1394                         smac_index = smac_info->smac_index;
1395                 }
1396
1397                 memcpy(path->dmac, ah->dmac, 6);
1398                 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1399                 /* put MAC table smac index for IBoE */
1400                 path->grh_mylmc = (u8) (smac_index) | 0x80;
1401         } else {
1402                 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1403                         ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
1404         }
1405
1406         return 0;
1407 }
1408
1409 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1410                          enum ib_qp_attr_mask qp_attr_mask,
1411                          struct mlx4_ib_qp *mqp,
1412                          struct mlx4_qp_path *path, u8 port,
1413                          u16 vlan_id, u8 *smac)
1414 {
1415         return _mlx4_set_path(dev, &qp->ah_attr,
1416                               mlx4_mac_to_u64(smac),
1417                               vlan_id,
1418                               path, &mqp->pri, port);
1419 }
1420
1421 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1422                              const struct ib_qp_attr *qp,
1423                              enum ib_qp_attr_mask qp_attr_mask,
1424                              struct mlx4_ib_qp *mqp,
1425                              struct mlx4_qp_path *path, u8 port)
1426 {
1427         return _mlx4_set_path(dev, &qp->alt_ah_attr,
1428                               0,
1429                               0xffff,
1430                               path, &mqp->alt, port);
1431 }
1432
1433 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1434 {
1435         struct mlx4_ib_gid_entry *ge, *tmp;
1436
1437         list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1438                 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1439                         ge->added = 1;
1440                         ge->port = qp->port;
1441                 }
1442         }
1443 }
1444
1445 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1446                                     struct mlx4_ib_qp *qp,
1447                                     struct mlx4_qp_context *context)
1448 {
1449         u64 u64_mac;
1450         int smac_index;
1451
1452         u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1453
1454         context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1455         if (!qp->pri.smac && !qp->pri.smac_port) {
1456                 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1457                 if (smac_index >= 0) {
1458                         qp->pri.candidate_smac_index = smac_index;
1459                         qp->pri.candidate_smac = u64_mac;
1460                         qp->pri.candidate_smac_port = qp->port;
1461                         context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1462                 } else {
1463                         return -ENOENT;
1464                 }
1465         }
1466         return 0;
1467 }
1468
1469 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1470 {
1471         struct counter_index *new_counter_index;
1472         int err;
1473         u32 tmp_idx;
1474
1475         if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1476             IB_LINK_LAYER_ETHERNET ||
1477             !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1478             !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1479                 return 0;
1480
1481         err = mlx4_counter_alloc(dev->dev, &tmp_idx);
1482         if (err)
1483                 return err;
1484
1485         new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1486         if (!new_counter_index) {
1487                 mlx4_counter_free(dev->dev, tmp_idx);
1488                 return -ENOMEM;
1489         }
1490
1491         new_counter_index->index = tmp_idx;
1492         new_counter_index->allocated = 1;
1493         qp->counter_index = new_counter_index;
1494
1495         mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1496         list_add_tail(&new_counter_index->list,
1497                       &dev->counters_table[qp->port - 1].counters_list);
1498         mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1499
1500         return 0;
1501 }
1502
1503 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
1504                                const struct ib_qp_attr *attr, int attr_mask,
1505                                enum ib_qp_state cur_state, enum ib_qp_state new_state)
1506 {
1507         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1508         struct mlx4_ib_qp *qp = to_mqp(ibqp);
1509         struct mlx4_ib_pd *pd;
1510         struct mlx4_ib_cq *send_cq, *recv_cq;
1511         struct mlx4_qp_context *context;
1512         enum mlx4_qp_optpar optpar = 0;
1513         int sqd_event;
1514         int steer_qp = 0;
1515         int err = -EINVAL;
1516         int counter_index;
1517
1518         /* APM is not supported under RoCE */
1519         if (attr_mask & IB_QP_ALT_PATH &&
1520             rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1521             IB_LINK_LAYER_ETHERNET)
1522                 return -ENOTSUPP;
1523
1524         context = kzalloc(sizeof *context, GFP_KERNEL);
1525         if (!context)
1526                 return -ENOMEM;
1527
1528         context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
1529                                      (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
1530
1531         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
1532                 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1533         else {
1534                 optpar |= MLX4_QP_OPTPAR_PM_STATE;
1535                 switch (attr->path_mig_state) {
1536                 case IB_MIG_MIGRATED:
1537                         context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
1538                         break;
1539                 case IB_MIG_REARM:
1540                         context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
1541                         break;
1542                 case IB_MIG_ARMED:
1543                         context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
1544                         break;
1545                 }
1546         }
1547
1548         if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
1549                 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
1550         else if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1551                 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
1552         else if (ibqp->qp_type == IB_QPT_UD) {
1553                 if (qp->flags & MLX4_IB_QP_LSO)
1554                         context->mtu_msgmax = (IB_MTU_4096 << 5) |
1555                                               ilog2(dev->dev->caps.max_gso_sz);
1556                 else
1557                         context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1558         } else if (attr_mask & IB_QP_PATH_MTU) {
1559                 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
1560                         pr_err("path MTU (%u) is invalid\n",
1561                                attr->path_mtu);
1562                         goto out;
1563                 }
1564                 context->mtu_msgmax = (attr->path_mtu << 5) |
1565                         ilog2(dev->dev->caps.max_msg_sz);
1566         }
1567
1568         if (qp->rq.wqe_cnt)
1569                 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
1570         context->rq_size_stride |= qp->rq.wqe_shift - 4;
1571
1572         if (qp->sq.wqe_cnt)
1573                 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
1574         context->sq_size_stride |= qp->sq.wqe_shift - 4;
1575
1576         if (new_state == IB_QPS_RESET && qp->counter_index)
1577                 mlx4_ib_free_qp_counter(dev, qp);
1578
1579         if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1580                 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
1581                 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
1582                 if (ibqp->qp_type == IB_QPT_RAW_PACKET)
1583                         context->param3 |= cpu_to_be32(1 << 30);
1584         }
1585
1586         if (qp->ibqp.uobject)
1587                 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
1588         else
1589                 context->usr_page = cpu_to_be32(dev->priv_uar.index);
1590
1591         if (attr_mask & IB_QP_DEST_QPN)
1592                 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
1593
1594         if (attr_mask & IB_QP_PORT) {
1595                 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
1596                     !(attr_mask & IB_QP_AV)) {
1597                         mlx4_set_sched(&context->pri_path, attr->port_num);
1598                         optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
1599                 }
1600         }
1601
1602         if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
1603                 err = create_qp_lb_counter(dev, qp);
1604                 if (err)
1605                         goto out;
1606
1607                 counter_index =
1608                         dev->counters_table[qp->port - 1].default_counter;
1609                 if (qp->counter_index)
1610                         counter_index = qp->counter_index->index;
1611
1612                 if (counter_index != -1) {
1613                         context->pri_path.counter_index = counter_index;
1614                         optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
1615                         if (qp->counter_index) {
1616                                 context->pri_path.fl |=
1617                                         MLX4_FL_ETH_SRC_CHECK_MC_LB;
1618                                 context->pri_path.vlan_control |=
1619                                         MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
1620                         }
1621                 } else
1622                         context->pri_path.counter_index =
1623                                 MLX4_SINK_COUNTER_INDEX(dev->dev);
1624
1625                 if (qp->flags & MLX4_IB_QP_NETIF) {
1626                         mlx4_ib_steer_qp_reg(dev, qp, 1);
1627                         steer_qp = 1;
1628                 }
1629         }
1630
1631         if (attr_mask & IB_QP_PKEY_INDEX) {
1632                 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1633                         context->pri_path.disable_pkey_check = 0x40;
1634                 context->pri_path.pkey_index = attr->pkey_index;
1635                 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
1636         }
1637
1638         if (attr_mask & IB_QP_AV) {
1639                 u8 port_num = mlx4_is_bonded(to_mdev(ibqp->device)->dev) ? 1 :
1640                         attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1641                 union ib_gid gid;
1642                 struct ib_gid_attr gid_attr;
1643                 u16 vlan = 0xffff;
1644                 u8 smac[ETH_ALEN];
1645                 int status = 0;
1646
1647                 if (rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
1648                     attr->ah_attr.ah_flags & IB_AH_GRH) {
1649                         int index = attr->ah_attr.grh.sgid_index;
1650
1651                         status = ib_get_cached_gid(ibqp->device, port_num,
1652                                                    index, &gid, &gid_attr);
1653                         if (!status && !memcmp(&gid, &zgid, sizeof(gid)))
1654                                 status = -ENOENT;
1655                         if (!status && gid_attr.ndev) {
1656                                 vlan = rdma_vlan_dev_vlan_id(gid_attr.ndev);
1657                                 memcpy(smac, gid_attr.ndev->dev_addr, ETH_ALEN);
1658                                 dev_put(gid_attr.ndev);
1659                         }
1660                 }
1661                 if (status)
1662                         goto out;
1663
1664                 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
1665                                   port_num, vlan, smac))
1666                         goto out;
1667
1668                 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
1669                            MLX4_QP_OPTPAR_SCHED_QUEUE);
1670         }
1671
1672         if (attr_mask & IB_QP_TIMEOUT) {
1673                 context->pri_path.ackto |= attr->timeout << 3;
1674                 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
1675         }
1676
1677         if (attr_mask & IB_QP_ALT_PATH) {
1678                 if (attr->alt_port_num == 0 ||
1679                     attr->alt_port_num > dev->dev->caps.num_ports)
1680                         goto out;
1681
1682                 if (attr->alt_pkey_index >=
1683                     dev->dev->caps.pkey_table_len[attr->alt_port_num])
1684                         goto out;
1685
1686                 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
1687                                       &context->alt_path,
1688                                       attr->alt_port_num))
1689                         goto out;
1690
1691                 context->alt_path.pkey_index = attr->alt_pkey_index;
1692                 context->alt_path.ackto = attr->alt_timeout << 3;
1693                 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
1694         }
1695
1696         pd = get_pd(qp);
1697         get_cqs(qp, &send_cq, &recv_cq);
1698         context->pd       = cpu_to_be32(pd->pdn);
1699         context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
1700         context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
1701         context->params1  = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
1702
1703         /* Set "fast registration enabled" for all kernel QPs */
1704         if (!qp->ibqp.uobject)
1705                 context->params1 |= cpu_to_be32(1 << 11);
1706
1707         if (attr_mask & IB_QP_RNR_RETRY) {
1708                 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1709                 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1710         }
1711
1712         if (attr_mask & IB_QP_RETRY_CNT) {
1713                 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1714                 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1715         }
1716
1717         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1718                 if (attr->max_rd_atomic)
1719                         context->params1 |=
1720                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1721                 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1722         }
1723
1724         if (attr_mask & IB_QP_SQ_PSN)
1725                 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1726
1727         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1728                 if (attr->max_dest_rd_atomic)
1729                         context->params2 |=
1730                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1731                 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1732         }
1733
1734         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1735                 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1736                 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1737         }
1738
1739         if (ibqp->srq)
1740                 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1741
1742         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1743                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1744                 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1745         }
1746         if (attr_mask & IB_QP_RQ_PSN)
1747                 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1748
1749         /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
1750         if (attr_mask & IB_QP_QKEY) {
1751                 if (qp->mlx4_ib_qp_type &
1752                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
1753                         context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
1754                 else {
1755                         if (mlx4_is_mfunc(dev->dev) &&
1756                             !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
1757                             (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
1758                             MLX4_RESERVED_QKEY_BASE) {
1759                                 pr_err("Cannot use reserved QKEY"
1760                                        " 0x%x (range 0xffff0000..0xffffffff"
1761                                        " is reserved)\n", attr->qkey);
1762                                 err = -EINVAL;
1763                                 goto out;
1764                         }
1765                         context->qkey = cpu_to_be32(attr->qkey);
1766                 }
1767                 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1768         }
1769
1770         if (ibqp->srq)
1771                 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1772
1773         if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1774                 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1775
1776         if (cur_state == IB_QPS_INIT &&
1777             new_state == IB_QPS_RTR  &&
1778             (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1779              ibqp->qp_type == IB_QPT_UD ||
1780              ibqp->qp_type == IB_QPT_RAW_PACKET)) {
1781                 context->pri_path.sched_queue = (qp->port - 1) << 6;
1782                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
1783                     qp->mlx4_ib_qp_type &
1784                     (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
1785                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1786                         if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
1787                                 context->pri_path.fl = 0x80;
1788                 } else {
1789                         if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
1790                                 context->pri_path.fl = 0x80;
1791                         context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1792                 }
1793                 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
1794                     IB_LINK_LAYER_ETHERNET) {
1795                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
1796                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
1797                                 context->pri_path.feup = 1 << 7; /* don't fsm */
1798                         /* handle smac_index */
1799                         if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
1800                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
1801                             qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
1802                                 err = handle_eth_ud_smac_index(dev, qp, context);
1803                                 if (err) {
1804                                         err = -EINVAL;
1805                                         goto out;
1806                                 }
1807                                 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1808                                         dev->qp1_proxy[qp->port - 1] = qp;
1809                         }
1810                 }
1811         }
1812
1813         if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1814                 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
1815                                         MLX4_IB_LINK_TYPE_ETH;
1816                 if (dev->dev->caps.tunnel_offload_mode ==  MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1817                         /* set QP to receive both tunneled & non-tunneled packets */
1818                         if (!(context->flags & cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET)))
1819                                 context->srqn = cpu_to_be32(7 << 28);
1820                 }
1821         }
1822
1823         if (ibqp->qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
1824                 int is_eth = rdma_port_get_link_layer(
1825                                 &dev->ib_dev, qp->port) ==
1826                                 IB_LINK_LAYER_ETHERNET;
1827                 if (is_eth) {
1828                         context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
1829                         optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
1830                 }
1831         }
1832
1833
1834         if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD  &&
1835             attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1836                 sqd_event = 1;
1837         else
1838                 sqd_event = 0;
1839
1840         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1841                 context->rlkey |= (1 << 4);
1842
1843         /*
1844          * Before passing a kernel QP to the HW, make sure that the
1845          * ownership bits of the send queue are set and the SQ
1846          * headroom is stamped so that the hardware doesn't start
1847          * processing stale work requests.
1848          */
1849         if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1850                 struct mlx4_wqe_ctrl_seg *ctrl;
1851                 int i;
1852
1853                 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1854                         ctrl = get_send_wqe(qp, i);
1855                         ctrl->owner_opcode = cpu_to_be32(1 << 31);
1856                         if (qp->sq_max_wqes_per_wr == 1)
1857                                 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1858
1859                         stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1860                 }
1861         }
1862
1863         err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1864                              to_mlx4_state(new_state), context, optpar,
1865                              sqd_event, &qp->mqp);
1866         if (err)
1867                 goto out;
1868
1869         qp->state = new_state;
1870
1871         if (attr_mask & IB_QP_ACCESS_FLAGS)
1872                 qp->atomic_rd_en = attr->qp_access_flags;
1873         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1874                 qp->resp_depth = attr->max_dest_rd_atomic;
1875         if (attr_mask & IB_QP_PORT) {
1876                 qp->port = attr->port_num;
1877                 update_mcg_macs(dev, qp);
1878         }
1879         if (attr_mask & IB_QP_ALT_PATH)
1880                 qp->alt_port = attr->alt_port_num;
1881
1882         if (is_sqp(dev, qp))
1883                 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1884
1885         /*
1886          * If we moved QP0 to RTR, bring the IB link up; if we moved
1887          * QP0 to RESET or ERROR, bring the link back down.
1888          */
1889         if (is_qp0(dev, qp)) {
1890                 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1891                         if (mlx4_INIT_PORT(dev->dev, qp->port))
1892                                 pr_warn("INIT_PORT failed for port %d\n",
1893                                        qp->port);
1894
1895                 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1896                     (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1897                         mlx4_CLOSE_PORT(dev->dev, qp->port);
1898         }
1899
1900         /*
1901          * If we moved a kernel QP to RESET, clean up all old CQ
1902          * entries and reinitialize the QP.
1903          */
1904         if (new_state == IB_QPS_RESET) {
1905                 if (!ibqp->uobject) {
1906                         mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1907                                          ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1908                         if (send_cq != recv_cq)
1909                                 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1910
1911                         qp->rq.head = 0;
1912                         qp->rq.tail = 0;
1913                         qp->sq.head = 0;
1914                         qp->sq.tail = 0;
1915                         qp->sq_next_wqe = 0;
1916                         if (qp->rq.wqe_cnt)
1917                                 *qp->db.db  = 0;
1918
1919                         if (qp->flags & MLX4_IB_QP_NETIF)
1920                                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1921                 }
1922                 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1923                         mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1924                         qp->pri.smac = 0;
1925                         qp->pri.smac_port = 0;
1926                 }
1927                 if (qp->alt.smac) {
1928                         mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1929                         qp->alt.smac = 0;
1930                 }
1931                 if (qp->pri.vid < 0x1000) {
1932                         mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1933                         qp->pri.vid = 0xFFFF;
1934                         qp->pri.candidate_vid = 0xFFFF;
1935                         qp->pri.update_vid = 0;
1936                 }
1937
1938                 if (qp->alt.vid < 0x1000) {
1939                         mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1940                         qp->alt.vid = 0xFFFF;
1941                         qp->alt.candidate_vid = 0xFFFF;
1942                         qp->alt.update_vid = 0;
1943                 }
1944         }
1945 out:
1946         if (err && qp->counter_index)
1947                 mlx4_ib_free_qp_counter(dev, qp);
1948         if (err && steer_qp)
1949                 mlx4_ib_steer_qp_reg(dev, qp, 0);
1950         kfree(context);
1951         if (qp->pri.candidate_smac ||
1952             (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
1953                 if (err) {
1954                         mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
1955                 } else {
1956                         if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
1957                                 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1958                         qp->pri.smac = qp->pri.candidate_smac;
1959                         qp->pri.smac_index = qp->pri.candidate_smac_index;
1960                         qp->pri.smac_port = qp->pri.candidate_smac_port;
1961                 }
1962                 qp->pri.candidate_smac = 0;
1963                 qp->pri.candidate_smac_index = 0;
1964                 qp->pri.candidate_smac_port = 0;
1965         }
1966         if (qp->alt.candidate_smac) {
1967                 if (err) {
1968                         mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
1969                 } else {
1970                         if (qp->alt.smac)
1971                                 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1972                         qp->alt.smac = qp->alt.candidate_smac;
1973                         qp->alt.smac_index = qp->alt.candidate_smac_index;
1974                         qp->alt.smac_port = qp->alt.candidate_smac_port;
1975                 }
1976                 qp->alt.candidate_smac = 0;
1977                 qp->alt.candidate_smac_index = 0;
1978                 qp->alt.candidate_smac_port = 0;
1979         }
1980
1981         if (qp->pri.update_vid) {
1982                 if (err) {
1983                         if (qp->pri.candidate_vid < 0x1000)
1984                                 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
1985                                                      qp->pri.candidate_vid);
1986                 } else {
1987                         if (qp->pri.vid < 0x1000)
1988                                 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
1989                                                      qp->pri.vid);
1990                         qp->pri.vid = qp->pri.candidate_vid;
1991                         qp->pri.vlan_port = qp->pri.candidate_vlan_port;
1992                         qp->pri.vlan_index =  qp->pri.candidate_vlan_index;
1993                 }
1994                 qp->pri.candidate_vid = 0xFFFF;
1995                 qp->pri.update_vid = 0;
1996         }
1997
1998         if (qp->alt.update_vid) {
1999                 if (err) {
2000                         if (qp->alt.candidate_vid < 0x1000)
2001                                 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2002                                                      qp->alt.candidate_vid);
2003                 } else {
2004                         if (qp->alt.vid < 0x1000)
2005                                 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2006                                                      qp->alt.vid);
2007                         qp->alt.vid = qp->alt.candidate_vid;
2008                         qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2009                         qp->alt.vlan_index =  qp->alt.candidate_vlan_index;
2010                 }
2011                 qp->alt.candidate_vid = 0xFFFF;
2012                 qp->alt.update_vid = 0;
2013         }
2014
2015         return err;
2016 }
2017
2018 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2019                       int attr_mask, struct ib_udata *udata)
2020 {
2021         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2022         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2023         enum ib_qp_state cur_state, new_state;
2024         int err = -EINVAL;
2025         int ll;
2026         mutex_lock(&qp->mutex);
2027
2028         cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2029         new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2030
2031         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2032                 ll = IB_LINK_LAYER_UNSPECIFIED;
2033         } else {
2034                 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2035                 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2036         }
2037
2038         if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2039                                 attr_mask, ll)) {
2040                 pr_debug("qpn 0x%x: invalid attribute mask specified "
2041                          "for transition %d to %d. qp_type %d,"
2042                          " attr_mask 0x%x\n",
2043                          ibqp->qp_num, cur_state, new_state,
2044                          ibqp->qp_type, attr_mask);
2045                 goto out;
2046         }
2047
2048         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2049                 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2050                         if ((ibqp->qp_type == IB_QPT_RC) ||
2051                             (ibqp->qp_type == IB_QPT_UD) ||
2052                             (ibqp->qp_type == IB_QPT_UC) ||
2053                             (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2054                             (ibqp->qp_type == IB_QPT_XRC_INI)) {
2055                                 attr->port_num = mlx4_ib_bond_next_port(dev);
2056                         }
2057                 } else {
2058                         /* no sense in changing port_num
2059                          * when ports are bonded */
2060                         attr_mask &= ~IB_QP_PORT;
2061                 }
2062         }
2063
2064         if ((attr_mask & IB_QP_PORT) &&
2065             (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2066                 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2067                          "for transition %d to %d. qp_type %d\n",
2068                          ibqp->qp_num, attr->port_num, cur_state,
2069                          new_state, ibqp->qp_type);
2070                 goto out;
2071         }
2072
2073         if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2074             (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2075              IB_LINK_LAYER_ETHERNET))
2076                 goto out;
2077
2078         if (attr_mask & IB_QP_PKEY_INDEX) {
2079                 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2080                 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2081                         pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2082                                  "for transition %d to %d. qp_type %d\n",
2083                                  ibqp->qp_num, attr->pkey_index, cur_state,
2084                                  new_state, ibqp->qp_type);
2085                         goto out;
2086                 }
2087         }
2088
2089         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2090             attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2091                 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2092                          "Transition %d to %d. qp_type %d\n",
2093                          ibqp->qp_num, attr->max_rd_atomic, cur_state,
2094                          new_state, ibqp->qp_type);
2095                 goto out;
2096         }
2097
2098         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2099             attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2100                 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2101                          "Transition %d to %d. qp_type %d\n",
2102                          ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2103                          new_state, ibqp->qp_type);
2104                 goto out;
2105         }
2106
2107         if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2108                 err = 0;
2109                 goto out;
2110         }
2111
2112         err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2113
2114         if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2115                 attr->port_num = 1;
2116
2117 out:
2118         mutex_unlock(&qp->mutex);
2119         return err;
2120 }
2121
2122 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2123 {
2124         int i;
2125         for (i = 0; i < dev->caps.num_ports; i++) {
2126                 if (qpn == dev->caps.qp0_proxy[i] ||
2127                     qpn == dev->caps.qp0_tunnel[i]) {
2128                         *qkey = dev->caps.qp0_qkey[i];
2129                         return 0;
2130                 }
2131         }
2132         return -EINVAL;
2133 }
2134
2135 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2136                                   struct ib_ud_wr *wr,
2137                                   void *wqe, unsigned *mlx_seg_len)
2138 {
2139         struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2140         struct ib_device *ib_dev = &mdev->ib_dev;
2141         struct mlx4_wqe_mlx_seg *mlx = wqe;
2142         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2143         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2144         u16 pkey;
2145         u32 qkey;
2146         int send_size;
2147         int header_size;
2148         int spc;
2149         int i;
2150
2151         if (wr->wr.opcode != IB_WR_SEND)
2152                 return -EINVAL;
2153
2154         send_size = 0;
2155
2156         for (i = 0; i < wr->wr.num_sge; ++i)
2157                 send_size += wr->wr.sg_list[i].length;
2158
2159         /* for proxy-qp0 sends, need to add in size of tunnel header */
2160         /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2161         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2162                 send_size += sizeof (struct mlx4_ib_tunnel_header);
2163
2164         ib_ud_header_init(send_size, 1, 0, 0, 0, 0, &sqp->ud_header);
2165
2166         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2167                 sqp->ud_header.lrh.service_level =
2168                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2169                 sqp->ud_header.lrh.destination_lid =
2170                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2171                 sqp->ud_header.lrh.source_lid =
2172                         cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2173         }
2174
2175         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2176
2177         /* force loopback */
2178         mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2179         mlx->rlid = sqp->ud_header.lrh.destination_lid;
2180
2181         sqp->ud_header.lrh.virtual_lane    = 0;
2182         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2183         ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2184         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2185         if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2186                 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2187         else
2188                 sqp->ud_header.bth.destination_qpn =
2189                         cpu_to_be32(mdev->dev->caps.qp0_tunnel[sqp->qp.port - 1]);
2190
2191         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2192         if (mlx4_is_master(mdev->dev)) {
2193                 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2194                         return -EINVAL;
2195         } else {
2196                 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2197                         return -EINVAL;
2198         }
2199         sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2200         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2201
2202         sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2203         sqp->ud_header.immediate_present = 0;
2204
2205         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2206
2207         /*
2208          * Inline data segments may not cross a 64 byte boundary.  If
2209          * our UD header is bigger than the space available up to the
2210          * next 64 byte boundary in the WQE, use two inline data
2211          * segments to hold the UD header.
2212          */
2213         spc = MLX4_INLINE_ALIGN -
2214               ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2215         if (header_size <= spc) {
2216                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2217                 memcpy(inl + 1, sqp->header_buf, header_size);
2218                 i = 1;
2219         } else {
2220                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2221                 memcpy(inl + 1, sqp->header_buf, spc);
2222
2223                 inl = (void *) (inl + 1) + spc;
2224                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2225                 /*
2226                  * Need a barrier here to make sure all the data is
2227                  * visible before the byte_count field is set.
2228                  * Otherwise the HCA prefetcher could grab the 64-byte
2229                  * chunk with this inline segment and get a valid (!=
2230                  * 0xffffffff) byte count but stale data, and end up
2231                  * generating a packet with bad headers.
2232                  *
2233                  * The first inline segment's byte_count field doesn't
2234                  * need a barrier, because it comes after a
2235                  * control/MLX segment and therefore is at an offset
2236                  * of 16 mod 64.
2237                  */
2238                 wmb();
2239                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2240                 i = 2;
2241         }
2242
2243         *mlx_seg_len =
2244         ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2245         return 0;
2246 }
2247
2248 static void mlx4_u64_to_smac(u8 *dst_mac, u64 src_mac)
2249 {
2250         int i;
2251
2252         for (i = ETH_ALEN; i; i--) {
2253                 dst_mac[i - 1] = src_mac & 0xff;
2254                 src_mac >>= 8;
2255         }
2256 }
2257
2258 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_ud_wr *wr,
2259                             void *wqe, unsigned *mlx_seg_len)
2260 {
2261         struct ib_device *ib_dev = sqp->qp.ibqp.device;
2262         struct mlx4_wqe_mlx_seg *mlx = wqe;
2263         struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2264         struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2265         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2266         union ib_gid sgid;
2267         u16 pkey;
2268         int send_size;
2269         int header_size;
2270         int spc;
2271         int i;
2272         int err = 0;
2273         u16 vlan = 0xffff;
2274         bool is_eth;
2275         bool is_vlan = false;
2276         bool is_grh;
2277
2278         send_size = 0;
2279         for (i = 0; i < wr->wr.num_sge; ++i)
2280                 send_size += wr->wr.sg_list[i].length;
2281
2282         is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2283         is_grh = mlx4_ib_ah_grh_present(ah);
2284         if (is_eth) {
2285                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2286                         /* When multi-function is enabled, the ib_core gid
2287                          * indexes don't necessarily match the hw ones, so
2288                          * we must use our own cache */
2289                         err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2290                                                            be32_to_cpu(ah->av.ib.port_pd) >> 24,
2291                                                            ah->av.ib.gid_index, &sgid.raw[0]);
2292                         if (err)
2293                                 return err;
2294                 } else  {
2295                         err = ib_get_cached_gid(ib_dev,
2296                                                 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2297                                                 ah->av.ib.gid_index, &sgid,
2298                                                 NULL);
2299                         if (!err && !memcmp(&sgid, &zgid, sizeof(sgid)))
2300                                 err = -ENOENT;
2301                         if (err)
2302                                 return err;
2303                 }
2304
2305                 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
2306                         vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
2307                         is_vlan = 1;
2308                 }
2309         }
2310         ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh, 0, &sqp->ud_header);
2311
2312         if (!is_eth) {
2313                 sqp->ud_header.lrh.service_level =
2314                         be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2315                 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
2316                 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2317         }
2318
2319         if (is_grh) {
2320                 sqp->ud_header.grh.traffic_class =
2321                         (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
2322                 sqp->ud_header.grh.flow_label    =
2323                         ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
2324                 sqp->ud_header.grh.hop_limit     = ah->av.ib.hop_limit;
2325                 if (is_eth)
2326                         memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
2327                 else {
2328                 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2329                         /* When multi-function is enabled, the ib_core gid
2330                          * indexes don't necessarily match the hw ones, so
2331                          * we must use our own cache */
2332                         sqp->ud_header.grh.source_gid.global.subnet_prefix =
2333                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2334                                                        subnet_prefix;
2335                         sqp->ud_header.grh.source_gid.global.interface_id =
2336                                 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
2337                                                guid_cache[ah->av.ib.gid_index];
2338                 } else
2339                         ib_get_cached_gid(ib_dev,
2340                                           be32_to_cpu(ah->av.ib.port_pd) >> 24,
2341                                           ah->av.ib.gid_index,
2342                                           &sqp->ud_header.grh.source_gid, NULL);
2343                 }
2344                 memcpy(sqp->ud_header.grh.destination_gid.raw,
2345                        ah->av.ib.dgid, 16);
2346         }
2347
2348         mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2349
2350         if (!is_eth) {
2351                 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
2352                                           (sqp->ud_header.lrh.destination_lid ==
2353                                            IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
2354                                           (sqp->ud_header.lrh.service_level << 8));
2355                 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
2356                         mlx->flags |= cpu_to_be32(0x1); /* force loopback */
2357                 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2358         }
2359
2360         switch (wr->wr.opcode) {
2361         case IB_WR_SEND:
2362                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY;
2363                 sqp->ud_header.immediate_present = 0;
2364                 break;
2365         case IB_WR_SEND_WITH_IMM:
2366                 sqp->ud_header.bth.opcode        = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2367                 sqp->ud_header.immediate_present = 1;
2368                 sqp->ud_header.immediate_data    = wr->wr.ex.imm_data;
2369                 break;
2370         default:
2371                 return -EINVAL;
2372         }
2373
2374         if (is_eth) {
2375                 struct in6_addr in6;
2376
2377                 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
2378
2379                 mlx->sched_prio = cpu_to_be16(pcp);
2380
2381                 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
2382                 /* FIXME: cache smac value? */
2383                 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
2384                 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
2385                 memcpy(&in6, sgid.raw, sizeof(in6));
2386
2387                 if (!mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2388                         u64 mac = atomic64_read(&to_mdev(ib_dev)->iboe.mac[sqp->qp.port - 1]);
2389                         u8 smac[ETH_ALEN];
2390
2391                         mlx4_u64_to_smac(smac, mac);
2392                         memcpy(sqp->ud_header.eth.smac_h, smac, ETH_ALEN);
2393                 } else {
2394                         /* use the src mac of the tunnel */
2395                         memcpy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac, ETH_ALEN);
2396                 }
2397
2398                 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
2399                         mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2400                 if (!is_vlan) {
2401                         sqp->ud_header.eth.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2402                 } else {
2403                         sqp->ud_header.vlan.type = cpu_to_be16(MLX4_IB_IBOE_ETHERTYPE);
2404                         sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
2405                 }
2406         } else {
2407                 sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
2408                 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
2409                         sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
2410         }
2411         sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2412         if (!sqp->qp.ibqp.qp_num)
2413                 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
2414         else
2415                 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index, &pkey);
2416         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2417         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2418         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2419         sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
2420                                                sqp->qkey : wr->remote_qkey);
2421         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
2422
2423         header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2424
2425         if (0) {
2426                 pr_err("built UD header of size %d:\n", header_size);
2427                 for (i = 0; i < header_size / 4; ++i) {
2428                         if (i % 8 == 0)
2429                                 pr_err("  [%02x] ", i * 4);
2430                         pr_cont(" %08x",
2431                                 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
2432                         if ((i + 1) % 8 == 0)
2433                                 pr_cont("\n");
2434                 }
2435                 pr_err("\n");
2436         }
2437
2438         /*
2439          * Inline data segments may not cross a 64 byte boundary.  If
2440          * our UD header is bigger than the space available up to the
2441          * next 64 byte boundary in the WQE, use two inline data
2442          * segments to hold the UD header.
2443          */
2444         spc = MLX4_INLINE_ALIGN -
2445                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2446         if (header_size <= spc) {
2447                 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2448                 memcpy(inl + 1, sqp->header_buf, header_size);
2449                 i = 1;
2450         } else {
2451                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2452                 memcpy(inl + 1, sqp->header_buf, spc);
2453
2454                 inl = (void *) (inl + 1) + spc;
2455                 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2456                 /*
2457                  * Need a barrier here to make sure all the data is
2458                  * visible before the byte_count field is set.
2459                  * Otherwise the HCA prefetcher could grab the 64-byte
2460                  * chunk with this inline segment and get a valid (!=
2461                  * 0xffffffff) byte count but stale data, and end up
2462                  * generating a packet with bad headers.
2463                  *
2464                  * The first inline segment's byte_count field doesn't
2465                  * need a barrier, because it comes after a
2466                  * control/MLX segment and therefore is at an offset
2467                  * of 16 mod 64.
2468                  */
2469                 wmb();
2470                 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2471                 i = 2;
2472         }
2473
2474         *mlx_seg_len =
2475                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2476         return 0;
2477 }
2478
2479 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2480 {
2481         unsigned cur;
2482         struct mlx4_ib_cq *cq;
2483
2484         cur = wq->head - wq->tail;
2485         if (likely(cur + nreq < wq->max_post))
2486                 return 0;
2487
2488         cq = to_mcq(ib_cq);
2489         spin_lock(&cq->lock);
2490         cur = wq->head - wq->tail;
2491         spin_unlock(&cq->lock);
2492
2493         return cur + nreq >= wq->max_post;
2494 }
2495
2496 static __be32 convert_access(int acc)
2497 {
2498         return (acc & IB_ACCESS_REMOTE_ATOMIC ?
2499                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC)       : 0) |
2500                (acc & IB_ACCESS_REMOTE_WRITE  ?
2501                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
2502                (acc & IB_ACCESS_REMOTE_READ   ?
2503                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ)  : 0) |
2504                (acc & IB_ACCESS_LOCAL_WRITE   ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE)  : 0) |
2505                 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
2506 }
2507
2508 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
2509                         struct ib_reg_wr *wr)
2510 {
2511         struct mlx4_ib_mr *mr = to_mmr(wr->mr);
2512
2513         fseg->flags             = convert_access(wr->access);
2514         fseg->mem_key           = cpu_to_be32(wr->key);
2515         fseg->buf_list          = cpu_to_be64(mr->page_map);
2516         fseg->start_addr        = cpu_to_be64(mr->ibmr.iova);
2517         fseg->reg_len           = cpu_to_be64(mr->ibmr.length);
2518         fseg->offset            = 0; /* XXX -- is this just for ZBVA? */
2519         fseg->page_size         = cpu_to_be32(ilog2(mr->ibmr.page_size));
2520         fseg->reserved[0]       = 0;
2521         fseg->reserved[1]       = 0;
2522 }
2523
2524 static void set_bind_seg(struct mlx4_wqe_bind_seg *bseg,
2525                 struct ib_bind_mw_wr *wr)
2526 {
2527         bseg->flags1 =
2528                 convert_access(wr->bind_info.mw_access_flags) &
2529                 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  |
2530                             MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE |
2531                             MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC);
2532         bseg->flags2 = 0;
2533         if (wr->mw->type == IB_MW_TYPE_2)
2534                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_TYPE_2);
2535         if (wr->bind_info.mw_access_flags & IB_ZERO_BASED)
2536                 bseg->flags2 |= cpu_to_be32(MLX4_WQE_BIND_ZERO_BASED);
2537         bseg->new_rkey = cpu_to_be32(wr->rkey);
2538         bseg->lkey = cpu_to_be32(wr->bind_info.mr->lkey);
2539         bseg->addr = cpu_to_be64(wr->bind_info.addr);
2540         bseg->length = cpu_to_be64(wr->bind_info.length);
2541 }
2542
2543 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
2544 {
2545         memset(iseg, 0, sizeof(*iseg));
2546         iseg->mem_key = cpu_to_be32(rkey);
2547 }
2548
2549 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
2550                                           u64 remote_addr, u32 rkey)
2551 {
2552         rseg->raddr    = cpu_to_be64(remote_addr);
2553         rseg->rkey     = cpu_to_be32(rkey);
2554         rseg->reserved = 0;
2555 }
2556
2557 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
2558                 struct ib_atomic_wr *wr)
2559 {
2560         if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
2561                 aseg->swap_add = cpu_to_be64(wr->swap);
2562                 aseg->compare  = cpu_to_be64(wr->compare_add);
2563         } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
2564                 aseg->swap_add = cpu_to_be64(wr->compare_add);
2565                 aseg->compare  = cpu_to_be64(wr->compare_add_mask);
2566         } else {
2567                 aseg->swap_add = cpu_to_be64(wr->compare_add);
2568                 aseg->compare  = 0;
2569         }
2570
2571 }
2572
2573 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
2574                                   struct ib_atomic_wr *wr)
2575 {
2576         aseg->swap_add          = cpu_to_be64(wr->swap);
2577         aseg->swap_add_mask     = cpu_to_be64(wr->swap_mask);
2578         aseg->compare           = cpu_to_be64(wr->compare_add);
2579         aseg->compare_mask      = cpu_to_be64(wr->compare_add_mask);
2580 }
2581
2582 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
2583                              struct ib_ud_wr *wr)
2584 {
2585         memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
2586         dseg->dqpn = cpu_to_be32(wr->remote_qpn);
2587         dseg->qkey = cpu_to_be32(wr->remote_qkey);
2588         dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
2589         memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
2590 }
2591
2592 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
2593                                     struct mlx4_wqe_datagram_seg *dseg,
2594                                     struct ib_ud_wr *wr,
2595                                     enum mlx4_ib_qp_type qpt)
2596 {
2597         union mlx4_ext_av *av = &to_mah(wr->ah)->av;
2598         struct mlx4_av sqp_av = {0};
2599         int port = *((u8 *) &av->ib.port_pd) & 0x3;
2600
2601         /* force loopback */
2602         sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
2603         sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
2604         sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
2605                         cpu_to_be32(0xf0000000);
2606
2607         memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
2608         if (qpt == MLX4_IB_QPT_PROXY_GSI)
2609                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp1_tunnel[port - 1]);
2610         else
2611                 dseg->dqpn = cpu_to_be32(dev->dev->caps.qp0_tunnel[port - 1]);
2612         /* Use QKEY from the QP context, which is set by master */
2613         dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2614 }
2615
2616 static void build_tunnel_header(struct ib_ud_wr *wr, void *wqe, unsigned *mlx_seg_len)
2617 {
2618         struct mlx4_wqe_inline_seg *inl = wqe;
2619         struct mlx4_ib_tunnel_header hdr;
2620         struct mlx4_ib_ah *ah = to_mah(wr->ah);
2621         int spc;
2622         int i;
2623
2624         memcpy(&hdr.av, &ah->av, sizeof hdr.av);
2625         hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
2626         hdr.pkey_index = cpu_to_be16(wr->pkey_index);
2627         hdr.qkey = cpu_to_be32(wr->remote_qkey);
2628         memcpy(hdr.mac, ah->av.eth.mac, 6);
2629         hdr.vlan = ah->av.eth.vlan;
2630
2631         spc = MLX4_INLINE_ALIGN -
2632                 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2633         if (sizeof (hdr) <= spc) {
2634                 memcpy(inl + 1, &hdr, sizeof (hdr));
2635                 wmb();
2636                 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
2637                 i = 1;
2638         } else {
2639                 memcpy(inl + 1, &hdr, spc);
2640                 wmb();
2641                 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2642
2643                 inl = (void *) (inl + 1) + spc;
2644                 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
2645                 wmb();
2646                 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
2647                 i = 2;
2648         }
2649
2650         *mlx_seg_len =
2651                 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
2652 }
2653
2654 static void set_mlx_icrc_seg(void *dseg)
2655 {
2656         u32 *t = dseg;
2657         struct mlx4_wqe_inline_seg *iseg = dseg;
2658
2659         t[1] = 0;
2660
2661         /*
2662          * Need a barrier here before writing the byte_count field to
2663          * make sure that all the data is visible before the
2664          * byte_count field is set.  Otherwise, if the segment begins
2665          * a new cacheline, the HCA prefetcher could grab the 64-byte
2666          * chunk and get a valid (!= * 0xffffffff) byte count but
2667          * stale data, and end up sending the wrong data.
2668          */
2669         wmb();
2670
2671         iseg->byte_count = cpu_to_be32((1 << 31) | 4);
2672 }
2673
2674 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2675 {
2676         dseg->lkey       = cpu_to_be32(sg->lkey);
2677         dseg->addr       = cpu_to_be64(sg->addr);
2678
2679         /*
2680          * Need a barrier here before writing the byte_count field to
2681          * make sure that all the data is visible before the
2682          * byte_count field is set.  Otherwise, if the segment begins
2683          * a new cacheline, the HCA prefetcher could grab the 64-byte
2684          * chunk and get a valid (!= * 0xffffffff) byte count but
2685          * stale data, and end up sending the wrong data.
2686          */
2687         wmb();
2688
2689         dseg->byte_count = cpu_to_be32(sg->length);
2690 }
2691
2692 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
2693 {
2694         dseg->byte_count = cpu_to_be32(sg->length);
2695         dseg->lkey       = cpu_to_be32(sg->lkey);
2696         dseg->addr       = cpu_to_be64(sg->addr);
2697 }
2698
2699 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_ud_wr *wr,
2700                          struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
2701                          __be32 *lso_hdr_sz, __be32 *blh)
2702 {
2703         unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
2704
2705         if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
2706                 *blh = cpu_to_be32(1 << 6);
2707
2708         if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
2709                      wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
2710                 return -EINVAL;
2711
2712         memcpy(wqe->header, wr->header, wr->hlen);
2713
2714         *lso_hdr_sz  = cpu_to_be32(wr->mss << 16 | wr->hlen);
2715         *lso_seg_len = halign;
2716         return 0;
2717 }
2718
2719 static __be32 send_ieth(struct ib_send_wr *wr)
2720 {
2721         switch (wr->opcode) {
2722         case IB_WR_SEND_WITH_IMM:
2723         case IB_WR_RDMA_WRITE_WITH_IMM:
2724                 return wr->ex.imm_data;
2725
2726         case IB_WR_SEND_WITH_INV:
2727                 return cpu_to_be32(wr->ex.invalidate_rkey);
2728
2729         default:
2730                 return 0;
2731         }
2732 }
2733
2734 static void add_zero_len_inline(void *wqe)
2735 {
2736         struct mlx4_wqe_inline_seg *inl = wqe;
2737         memset(wqe, 0, 16);
2738         inl->byte_count = cpu_to_be32(1 << 31);
2739 }
2740
2741 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2742                       struct ib_send_wr **bad_wr)
2743 {
2744         struct mlx4_ib_qp *qp = to_mqp(ibqp);
2745         void *wqe;
2746         struct mlx4_wqe_ctrl_seg *ctrl;
2747         struct mlx4_wqe_data_seg *dseg;
2748         unsigned long flags;
2749         int nreq;
2750         int err = 0;
2751         unsigned ind;
2752         int uninitialized_var(stamp);
2753         int uninitialized_var(size);
2754         unsigned uninitialized_var(seglen);
2755         __be32 dummy;
2756         __be32 *lso_wqe;
2757         __be32 uninitialized_var(lso_hdr_sz);
2758         __be32 blh;
2759         int i;
2760         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2761
2762         spin_lock_irqsave(&qp->sq.lock, flags);
2763         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
2764                 err = -EIO;
2765                 *bad_wr = wr;
2766                 nreq = 0;
2767                 goto out;
2768         }
2769
2770         ind = qp->sq_next_wqe;
2771
2772         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2773                 lso_wqe = &dummy;
2774                 blh = 0;
2775
2776                 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
2777                         err = -ENOMEM;
2778                         *bad_wr = wr;
2779                         goto out;
2780                 }
2781
2782                 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
2783                         err = -EINVAL;
2784                         *bad_wr = wr;
2785                         goto out;
2786                 }
2787
2788                 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
2789                 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
2790
2791                 ctrl->srcrb_flags =
2792                         (wr->send_flags & IB_SEND_SIGNALED ?
2793                          cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
2794                         (wr->send_flags & IB_SEND_SOLICITED ?
2795                          cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
2796                         ((wr->send_flags & IB_SEND_IP_CSUM) ?
2797                          cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
2798                                      MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
2799                         qp->sq_signal_bits;
2800
2801                 ctrl->imm = send_ieth(wr);
2802
2803                 wqe += sizeof *ctrl;
2804                 size = sizeof *ctrl / 16;
2805
2806                 switch (qp->mlx4_ib_qp_type) {
2807                 case MLX4_IB_QPT_RC:
2808                 case MLX4_IB_QPT_UC:
2809                         switch (wr->opcode) {
2810                         case IB_WR_ATOMIC_CMP_AND_SWP:
2811                         case IB_WR_ATOMIC_FETCH_AND_ADD:
2812                         case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
2813                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2814                                               atomic_wr(wr)->rkey);
2815                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2816
2817                                 set_atomic_seg(wqe, atomic_wr(wr));
2818                                 wqe  += sizeof (struct mlx4_wqe_atomic_seg);
2819
2820                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2821                                          sizeof (struct mlx4_wqe_atomic_seg)) / 16;
2822
2823                                 break;
2824
2825                         case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2826                                 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2827                                               atomic_wr(wr)->rkey);
2828                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2829
2830                                 set_masked_atomic_seg(wqe, atomic_wr(wr));
2831                                 wqe  += sizeof (struct mlx4_wqe_masked_atomic_seg);
2832
2833                                 size += (sizeof (struct mlx4_wqe_raddr_seg) +
2834                                          sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
2835
2836                                 break;
2837
2838                         case IB_WR_RDMA_READ:
2839                         case IB_WR_RDMA_WRITE:
2840                         case IB_WR_RDMA_WRITE_WITH_IMM:
2841                                 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2842                                               rdma_wr(wr)->rkey);
2843                                 wqe  += sizeof (struct mlx4_wqe_raddr_seg);
2844                                 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
2845                                 break;
2846
2847                         case IB_WR_LOCAL_INV:
2848                                 ctrl->srcrb_flags |=
2849                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2850                                 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
2851                                 wqe  += sizeof (struct mlx4_wqe_local_inval_seg);
2852                                 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
2853                                 break;
2854
2855                         case IB_WR_REG_MR:
2856                                 ctrl->srcrb_flags |=
2857                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2858                                 set_reg_seg(wqe, reg_wr(wr));
2859                                 wqe  += sizeof(struct mlx4_wqe_fmr_seg);
2860                                 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
2861                                 break;
2862
2863                         case IB_WR_BIND_MW:
2864                                 ctrl->srcrb_flags |=
2865                                         cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
2866                                 set_bind_seg(wqe, bind_mw_wr(wr));
2867                                 wqe  += sizeof(struct mlx4_wqe_bind_seg);
2868                                 size += sizeof(struct mlx4_wqe_bind_seg) / 16;
2869                                 break;
2870                         default:
2871                                 /* No extra segments required for sends */
2872                                 break;
2873                         }
2874                         break;
2875
2876                 case MLX4_IB_QPT_TUN_SMI_OWNER:
2877                         err =  build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2878                                         ctrl, &seglen);
2879                         if (unlikely(err)) {
2880                                 *bad_wr = wr;
2881                                 goto out;
2882                         }
2883                         wqe  += seglen;
2884                         size += seglen / 16;
2885                         break;
2886                 case MLX4_IB_QPT_TUN_SMI:
2887                 case MLX4_IB_QPT_TUN_GSI:
2888                         /* this is a UD qp used in MAD responses to slaves. */
2889                         set_datagram_seg(wqe, ud_wr(wr));
2890                         /* set the forced-loopback bit in the data seg av */
2891                         *(__be32 *) wqe |= cpu_to_be32(0x80000000);
2892                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2893                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2894                         break;
2895                 case MLX4_IB_QPT_UD:
2896                         set_datagram_seg(wqe, ud_wr(wr));
2897                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2898                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2899
2900                         if (wr->opcode == IB_WR_LSO) {
2901                                 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
2902                                                 &lso_hdr_sz, &blh);
2903                                 if (unlikely(err)) {
2904                                         *bad_wr = wr;
2905                                         goto out;
2906                                 }
2907                                 lso_wqe = (__be32 *) wqe;
2908                                 wqe  += seglen;
2909                                 size += seglen / 16;
2910                         }
2911                         break;
2912
2913                 case MLX4_IB_QPT_PROXY_SMI_OWNER:
2914                         err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
2915                                         ctrl, &seglen);
2916                         if (unlikely(err)) {
2917                                 *bad_wr = wr;
2918                                 goto out;
2919                         }
2920                         wqe  += seglen;
2921                         size += seglen / 16;
2922                         /* to start tunnel header on a cache-line boundary */
2923                         add_zero_len_inline(wqe);
2924                         wqe += 16;
2925                         size++;
2926                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
2927                         wqe  += seglen;
2928                         size += seglen / 16;
2929                         break;
2930                 case MLX4_IB_QPT_PROXY_SMI:
2931                 case MLX4_IB_QPT_PROXY_GSI:
2932                         /* If we are tunneling special qps, this is a UD qp.
2933                          * In this case we first add a UD segment targeting
2934                          * the tunnel qp, and then add a header with address
2935                          * information */
2936                         set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
2937                                                 ud_wr(wr),
2938                                                 qp->mlx4_ib_qp_type);
2939                         wqe  += sizeof (struct mlx4_wqe_datagram_seg);
2940                         size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
2941                         build_tunnel_header(ud_wr(wr), wqe, &seglen);
2942                         wqe  += seglen;
2943                         size += seglen / 16;
2944                         break;
2945
2946                 case MLX4_IB_QPT_SMI:
2947                 case MLX4_IB_QPT_GSI:
2948                         err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
2949                                         &seglen);
2950                         if (unlikely(err)) {
2951                                 *bad_wr = wr;
2952                                 goto out;
2953                         }
2954                         wqe  += seglen;
2955                         size += seglen / 16;
2956                         break;
2957
2958                 default:
2959                         break;
2960                 }
2961
2962                 /*
2963                  * Write data segments in reverse order, so as to
2964                  * overwrite cacheline stamp last within each
2965                  * cacheline.  This avoids issues with WQE
2966                  * prefetching.
2967                  */
2968
2969                 dseg = wqe;
2970                 dseg += wr->num_sge - 1;
2971                 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
2972
2973                 /* Add one more inline data segment for ICRC for MLX sends */
2974                 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2975                              qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
2976                              qp->mlx4_ib_qp_type &
2977                              (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
2978                         set_mlx_icrc_seg(dseg + 1);
2979                         size += sizeof (struct mlx4_wqe_data_seg) / 16;
2980                 }
2981
2982                 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
2983                         set_data_seg(dseg, wr->sg_list + i);
2984
2985                 /*
2986                  * Possibly overwrite stamping in cacheline with LSO
2987                  * segment only after making sure all data segments
2988                  * are written.
2989                  */
2990                 wmb();
2991                 *lso_wqe = lso_hdr_sz;
2992
2993                 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
2994                                     MLX4_WQE_CTRL_FENCE : 0) | size;
2995
2996                 /*
2997                  * Make sure descriptor is fully written before
2998                  * setting ownership bit (because HW can start
2999                  * executing as soon as we do).
3000                  */
3001                 wmb();
3002
3003                 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3004                         *bad_wr = wr;
3005                         err = -EINVAL;
3006                         goto out;
3007                 }
3008
3009                 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3010                         (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3011
3012                 stamp = ind + qp->sq_spare_wqes;
3013                 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
3014
3015                 /*
3016                  * We can improve latency by not stamping the last
3017                  * send queue WQE until after ringing the doorbell, so
3018                  * only stamp here if there are still more WQEs to post.
3019                  *
3020                  * Same optimization applies to padding with NOP wqe
3021                  * in case of WQE shrinking (used to prevent wrap-around
3022                  * in the middle of WR).
3023                  */
3024                 if (wr->next) {
3025                         stamp_send_wqe(qp, stamp, size * 16);
3026                         ind = pad_wraparound(qp, ind);
3027                 }
3028         }
3029
3030 out:
3031         if (likely(nreq)) {
3032                 qp->sq.head += nreq;
3033
3034                 /*
3035                  * Make sure that descriptors are written before
3036                  * doorbell record.
3037                  */
3038                 wmb();
3039
3040                 writel(qp->doorbell_qpn,
3041                        to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3042
3043                 /*
3044                  * Make sure doorbells don't leak out of SQ spinlock
3045                  * and reach the HCA out of order.
3046                  */
3047                 mmiowb();
3048
3049                 stamp_send_wqe(qp, stamp, size * 16);
3050
3051                 ind = pad_wraparound(qp, ind);
3052                 qp->sq_next_wqe = ind;
3053         }
3054
3055         spin_unlock_irqrestore(&qp->sq.lock, flags);
3056
3057         return err;
3058 }
3059
3060 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3061                       struct ib_recv_wr **bad_wr)
3062 {
3063         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3064         struct mlx4_wqe_data_seg *scat;
3065         unsigned long flags;
3066         int err = 0;
3067         int nreq;
3068         int ind;
3069         int max_gs;
3070         int i;
3071         struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3072
3073         max_gs = qp->rq.max_gs;
3074         spin_lock_irqsave(&qp->rq.lock, flags);
3075
3076         if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
3077                 err = -EIO;
3078                 *bad_wr = wr;
3079                 nreq = 0;
3080                 goto out;
3081         }
3082
3083         ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3084
3085         for (nreq = 0; wr; ++nreq, wr = wr->next) {
3086                 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3087                         err = -ENOMEM;
3088                         *bad_wr = wr;
3089                         goto out;
3090                 }
3091
3092                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3093                         err = -EINVAL;
3094                         *bad_wr = wr;
3095                         goto out;
3096                 }
3097
3098                 scat = get_recv_wqe(qp, ind);
3099
3100                 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3101                     MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3102                         ib_dma_sync_single_for_device(ibqp->device,
3103                                                       qp->sqp_proxy_rcv[ind].map,
3104                                                       sizeof (struct mlx4_ib_proxy_sqp_hdr),
3105                                                       DMA_FROM_DEVICE);
3106                         scat->byte_count =
3107                                 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3108                         /* use dma lkey from upper layer entry */
3109                         scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3110                         scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3111                         scat++;
3112                         max_gs--;
3113                 }
3114
3115                 for (i = 0; i < wr->num_sge; ++i)
3116                         __set_data_seg(scat + i, wr->sg_list + i);
3117
3118                 if (i < max_gs) {
3119                         scat[i].byte_count = 0;
3120                         scat[i].lkey       = cpu_to_be32(MLX4_INVALID_LKEY);
3121                         scat[i].addr       = 0;
3122                 }
3123
3124                 qp->rq.wrid[ind] = wr->wr_id;
3125
3126                 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3127         }
3128
3129 out:
3130         if (likely(nreq)) {
3131                 qp->rq.head += nreq;
3132
3133                 /*
3134                  * Make sure that descriptors are written before
3135                  * doorbell record.
3136                  */
3137                 wmb();
3138
3139                 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3140         }
3141
3142         spin_unlock_irqrestore(&qp->rq.lock, flags);
3143
3144         return err;
3145 }
3146
3147 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3148 {
3149         switch (mlx4_state) {
3150         case MLX4_QP_STATE_RST:      return IB_QPS_RESET;
3151         case MLX4_QP_STATE_INIT:     return IB_QPS_INIT;
3152         case MLX4_QP_STATE_RTR:      return IB_QPS_RTR;
3153         case MLX4_QP_STATE_RTS:      return IB_QPS_RTS;
3154         case MLX4_QP_STATE_SQ_DRAINING:
3155         case MLX4_QP_STATE_SQD:      return IB_QPS_SQD;
3156         case MLX4_QP_STATE_SQER:     return IB_QPS_SQE;
3157         case MLX4_QP_STATE_ERR:      return IB_QPS_ERR;
3158         default:                     return -1;
3159         }
3160 }
3161
3162 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3163 {
3164         switch (mlx4_mig_state) {
3165         case MLX4_QP_PM_ARMED:          return IB_MIG_ARMED;
3166         case MLX4_QP_PM_REARM:          return IB_MIG_REARM;
3167         case MLX4_QP_PM_MIGRATED:       return IB_MIG_MIGRATED;
3168         default: return -1;
3169         }
3170 }
3171
3172 static int to_ib_qp_access_flags(int mlx4_flags)
3173 {
3174         int ib_flags = 0;
3175
3176         if (mlx4_flags & MLX4_QP_BIT_RRE)
3177                 ib_flags |= IB_ACCESS_REMOTE_READ;
3178         if (mlx4_flags & MLX4_QP_BIT_RWE)
3179                 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3180         if (mlx4_flags & MLX4_QP_BIT_RAE)
3181                 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3182
3183         return ib_flags;
3184 }
3185
3186 static void to_ib_ah_attr(struct mlx4_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3187                                 struct mlx4_qp_path *path)
3188 {
3189         struct mlx4_dev *dev = ibdev->dev;
3190         int is_eth;
3191
3192         memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
3193         ib_ah_attr->port_num      = path->sched_queue & 0x40 ? 2 : 1;
3194
3195         if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
3196                 return;
3197
3198         is_eth = rdma_port_get_link_layer(&ibdev->ib_dev, ib_ah_attr->port_num) ==
3199                 IB_LINK_LAYER_ETHERNET;
3200         if (is_eth)
3201                 ib_ah_attr->sl = ((path->sched_queue >> 3) & 0x7) |
3202                 ((path->sched_queue & 4) << 1);
3203         else
3204                 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
3205
3206         ib_ah_attr->dlid          = be16_to_cpu(path->rlid);
3207         ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
3208         ib_ah_attr->static_rate   = path->static_rate ? path->static_rate - 5 : 0;
3209         ib_ah_attr->ah_flags      = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
3210         if (ib_ah_attr->ah_flags) {
3211                 ib_ah_attr->grh.sgid_index = path->mgid_index;
3212                 ib_ah_attr->grh.hop_limit  = path->hop_limit;
3213                 ib_ah_attr->grh.traffic_class =
3214                         (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3215                 ib_ah_attr->grh.flow_label =
3216                         be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3217                 memcpy(ib_ah_attr->grh.dgid.raw,
3218                         path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
3219         }
3220 }
3221
3222 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3223                      struct ib_qp_init_attr *qp_init_attr)
3224 {
3225         struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3226         struct mlx4_ib_qp *qp = to_mqp(ibqp);
3227         struct mlx4_qp_context context;
3228         int mlx4_state;
3229         int err = 0;
3230
3231         mutex_lock(&qp->mutex);
3232
3233         if (qp->state == IB_QPS_RESET) {
3234                 qp_attr->qp_state = IB_QPS_RESET;
3235                 goto done;
3236         }
3237
3238         err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3239         if (err) {
3240                 err = -EINVAL;
3241                 goto out;
3242         }
3243
3244         mlx4_state = be32_to_cpu(context.flags) >> 28;
3245
3246         qp->state                    = to_ib_qp_state(mlx4_state);
3247         qp_attr->qp_state            = qp->state;
3248         qp_attr->path_mtu            = context.mtu_msgmax >> 5;
3249         qp_attr->path_mig_state      =
3250                 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3251         qp_attr->qkey                = be32_to_cpu(context.qkey);
3252         qp_attr->rq_psn              = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3253         qp_attr->sq_psn              = be32_to_cpu(context.next_send_psn) & 0xffffff;
3254         qp_attr->dest_qp_num         = be32_to_cpu(context.remote_qpn) & 0xffffff;
3255         qp_attr->qp_access_flags     =
3256                 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3257
3258         if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3259                 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3260                 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3261                 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3262                 qp_attr->alt_port_num   = qp_attr->alt_ah_attr.port_num;
3263         }
3264
3265         qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3266         if (qp_attr->qp_state == IB_QPS_INIT)
3267                 qp_attr->port_num = qp->port;
3268         else
3269                 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3270
3271         /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3272         qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3273
3274         qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
3275
3276         qp_attr->max_dest_rd_atomic =
3277                 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
3278         qp_attr->min_rnr_timer      =
3279                 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
3280         qp_attr->timeout            = context.pri_path.ackto >> 3;
3281         qp_attr->retry_cnt          = (be32_to_cpu(context.params1) >> 16) & 0x7;
3282         qp_attr->rnr_retry          = (be32_to_cpu(context.params1) >> 13) & 0x7;
3283         qp_attr->alt_timeout        = context.alt_path.ackto >> 3;
3284
3285 done:
3286         qp_attr->cur_qp_state        = qp_attr->qp_state;
3287         qp_attr->cap.max_recv_wr     = qp->rq.wqe_cnt;
3288         qp_attr->cap.max_recv_sge    = qp->rq.max_gs;
3289
3290         if (!ibqp->uobject) {
3291                 qp_attr->cap.max_send_wr  = qp->sq.wqe_cnt;
3292                 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3293         } else {
3294                 qp_attr->cap.max_send_wr  = 0;
3295                 qp_attr->cap.max_send_sge = 0;
3296         }
3297
3298         /*
3299          * We don't support inline sends for kernel QPs (yet), and we
3300          * don't know what userspace's value should be.
3301          */
3302         qp_attr->cap.max_inline_data = 0;
3303
3304         qp_init_attr->cap            = qp_attr->cap;
3305
3306         qp_init_attr->create_flags = 0;
3307         if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3308                 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3309
3310         if (qp->flags & MLX4_IB_QP_LSO)
3311                 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
3312
3313         if (qp->flags & MLX4_IB_QP_NETIF)
3314                 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
3315
3316         qp_init_attr->sq_sig_type =
3317                 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
3318                 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3319
3320 out:
3321         mutex_unlock(&qp->mutex);
3322         return err;
3323 }
3324