2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #if defined(CONFIG_X86)
44 #include <linux/sched.h>
45 #include <linux/delay.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/ib_addr.h>
48 #include <rdma/ib_cache.h>
49 #include <linux/mlx5/port.h>
50 #include <linux/mlx5/vport.h>
51 #include <linux/list.h>
52 #include <rdma/ib_smi.h>
53 #include <rdma/ib_umem.h>
55 #include <linux/etherdevice.h>
56 #include <linux/mlx5/fs.h>
60 #define DRIVER_NAME "mlx5_ib"
61 #define DRIVER_VERSION "2.2-1"
62 #define DRIVER_RELDATE "Feb 2014"
64 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
65 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
66 MODULE_LICENSE("Dual BSD/GPL");
67 MODULE_VERSION(DRIVER_VERSION);
69 static int deprecated_prof_sel = 2;
70 module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
71 MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
73 static char mlx5_version[] =
74 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
75 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
78 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
81 static enum rdma_link_layer
82 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
84 switch (port_type_cap) {
85 case MLX5_CAP_PORT_TYPE_IB:
86 return IB_LINK_LAYER_INFINIBAND;
87 case MLX5_CAP_PORT_TYPE_ETH:
88 return IB_LINK_LAYER_ETHERNET;
90 return IB_LINK_LAYER_UNSPECIFIED;
94 static enum rdma_link_layer
95 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
97 struct mlx5_ib_dev *dev = to_mdev(device);
98 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
100 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
103 static int mlx5_netdev_event(struct notifier_block *this,
104 unsigned long event, void *ptr)
106 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
107 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
110 if ((event != NETDEV_UNREGISTER) && (event != NETDEV_REGISTER))
113 write_lock(&ibdev->roce.netdev_lock);
114 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
115 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? NULL : ndev;
116 write_unlock(&ibdev->roce.netdev_lock);
121 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
124 struct mlx5_ib_dev *ibdev = to_mdev(device);
125 struct net_device *ndev;
127 /* Ensure ndev does not disappear before we invoke dev_hold()
129 read_lock(&ibdev->roce.netdev_lock);
130 ndev = ibdev->roce.netdev;
133 read_unlock(&ibdev->roce.netdev_lock);
138 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
139 struct ib_port_attr *props)
141 struct mlx5_ib_dev *dev = to_mdev(device);
142 struct net_device *ndev;
143 enum ib_mtu ndev_ib_mtu;
146 memset(props, 0, sizeof(*props));
148 props->port_cap_flags |= IB_PORT_CM_SUP;
149 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
151 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
152 roce_address_table_size);
153 props->max_mtu = IB_MTU_4096;
154 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
155 props->pkey_tbl_len = 1;
156 props->state = IB_PORT_DOWN;
157 props->phys_state = 3;
159 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
160 props->qkey_viol_cntr = qkey_viol_cntr;
162 ndev = mlx5_ib_get_netdev(device, port_num);
166 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
167 props->state = IB_PORT_ACTIVE;
168 props->phys_state = 5;
171 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
175 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
177 props->active_width = IB_WIDTH_4X; /* TODO */
178 props->active_speed = IB_SPEED_QDR; /* TODO */
183 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
184 const struct ib_gid_attr *attr,
187 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
188 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
190 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
196 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
198 if (is_vlan_dev(attr->ndev)) {
199 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
200 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
203 switch (attr->gid_type) {
205 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
207 case IB_GID_TYPE_ROCE_UDP_ENCAP:
208 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
215 if (attr->gid_type != IB_GID_TYPE_IB) {
216 if (ipv6_addr_v4mapped((void *)gid))
217 MLX5_SET_RA(mlx5_addr, roce_l3_type,
218 MLX5_ROCE_L3_TYPE_IPV4);
220 MLX5_SET_RA(mlx5_addr, roce_l3_type,
221 MLX5_ROCE_L3_TYPE_IPV6);
224 if ((attr->gid_type == IB_GID_TYPE_IB) ||
225 !ipv6_addr_v4mapped((void *)gid))
226 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
228 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
231 static int set_roce_addr(struct ib_device *device, u8 port_num,
233 const union ib_gid *gid,
234 const struct ib_gid_attr *attr)
236 struct mlx5_ib_dev *dev = to_mdev(device);
237 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
238 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
239 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
240 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
242 if (ll != IB_LINK_LAYER_ETHERNET)
245 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
247 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
248 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
249 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
252 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
253 unsigned int index, const union ib_gid *gid,
254 const struct ib_gid_attr *attr,
255 __always_unused void **context)
257 return set_roce_addr(device, port_num, index, gid, attr);
260 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
261 unsigned int index, __always_unused void **context)
263 return set_roce_addr(device, port_num, index, NULL, NULL);
266 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
269 struct ib_gid_attr attr;
272 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
280 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
283 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
286 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
288 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
292 MLX5_VPORT_ACCESS_METHOD_MAD,
293 MLX5_VPORT_ACCESS_METHOD_HCA,
294 MLX5_VPORT_ACCESS_METHOD_NIC,
297 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
299 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
300 return MLX5_VPORT_ACCESS_METHOD_MAD;
302 if (mlx5_ib_port_link_layer(ibdev, 1) ==
303 IB_LINK_LAYER_ETHERNET)
304 return MLX5_VPORT_ACCESS_METHOD_NIC;
306 return MLX5_VPORT_ACCESS_METHOD_HCA;
309 static void get_atomic_caps(struct mlx5_ib_dev *dev,
310 struct ib_device_attr *props)
313 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
314 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
315 u8 atomic_req_8B_endianness_mode =
316 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
318 /* Check if HW supports 8 bytes standard atomic operations and capable
319 * of host endianness respond
321 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
322 if (((atomic_operations & tmp) == tmp) &&
323 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
324 (atomic_req_8B_endianness_mode)) {
325 props->atomic_cap = IB_ATOMIC_HCA;
327 props->atomic_cap = IB_ATOMIC_NONE;
331 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
332 __be64 *sys_image_guid)
334 struct mlx5_ib_dev *dev = to_mdev(ibdev);
335 struct mlx5_core_dev *mdev = dev->mdev;
339 switch (mlx5_get_vport_access_method(ibdev)) {
340 case MLX5_VPORT_ACCESS_METHOD_MAD:
341 return mlx5_query_mad_ifc_system_image_guid(ibdev,
344 case MLX5_VPORT_ACCESS_METHOD_HCA:
345 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
348 case MLX5_VPORT_ACCESS_METHOD_NIC:
349 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
357 *sys_image_guid = cpu_to_be64(tmp);
363 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
366 struct mlx5_ib_dev *dev = to_mdev(ibdev);
367 struct mlx5_core_dev *mdev = dev->mdev;
369 switch (mlx5_get_vport_access_method(ibdev)) {
370 case MLX5_VPORT_ACCESS_METHOD_MAD:
371 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
373 case MLX5_VPORT_ACCESS_METHOD_HCA:
374 case MLX5_VPORT_ACCESS_METHOD_NIC:
375 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
384 static int mlx5_query_vendor_id(struct ib_device *ibdev,
387 struct mlx5_ib_dev *dev = to_mdev(ibdev);
389 switch (mlx5_get_vport_access_method(ibdev)) {
390 case MLX5_VPORT_ACCESS_METHOD_MAD:
391 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
393 case MLX5_VPORT_ACCESS_METHOD_HCA:
394 case MLX5_VPORT_ACCESS_METHOD_NIC:
395 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
402 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
408 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
409 case MLX5_VPORT_ACCESS_METHOD_MAD:
410 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
412 case MLX5_VPORT_ACCESS_METHOD_HCA:
413 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
416 case MLX5_VPORT_ACCESS_METHOD_NIC:
417 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
425 *node_guid = cpu_to_be64(tmp);
430 struct mlx5_reg_node_desc {
434 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
436 struct mlx5_reg_node_desc in;
438 if (mlx5_use_mad_ifc(dev))
439 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
441 memset(&in, 0, sizeof(in));
443 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
444 sizeof(struct mlx5_reg_node_desc),
445 MLX5_REG_NODE_DESC, 0, 0);
448 static int mlx5_ib_query_device(struct ib_device *ibdev,
449 struct ib_device_attr *props,
450 struct ib_udata *uhw)
452 struct mlx5_ib_dev *dev = to_mdev(ibdev);
453 struct mlx5_core_dev *mdev = dev->mdev;
457 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
458 struct mlx5_ib_query_device_resp resp = {};
462 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
463 if (uhw->outlen && uhw->outlen < resp_len)
466 resp.response_length = resp_len;
468 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
471 memset(props, 0, sizeof(*props));
472 err = mlx5_query_system_image_guid(ibdev,
473 &props->sys_image_guid);
477 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
481 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
485 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
486 (fw_rev_min(dev->mdev) << 16) |
487 fw_rev_sub(dev->mdev);
488 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
489 IB_DEVICE_PORT_ACTIVE_EVENT |
490 IB_DEVICE_SYS_IMAGE_GUID |
491 IB_DEVICE_RC_RNR_NAK_GEN;
493 if (MLX5_CAP_GEN(mdev, pkv))
494 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
495 if (MLX5_CAP_GEN(mdev, qkv))
496 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
497 if (MLX5_CAP_GEN(mdev, apm))
498 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
499 if (MLX5_CAP_GEN(mdev, xrc))
500 props->device_cap_flags |= IB_DEVICE_XRC;
501 if (MLX5_CAP_GEN(mdev, imaicl)) {
502 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
503 IB_DEVICE_MEM_WINDOW_TYPE_2B;
504 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
505 /* We support 'Gappy' memory registration too */
506 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
508 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
509 if (MLX5_CAP_GEN(mdev, sho)) {
510 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
511 /* At this stage no support for signature handover */
512 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
513 IB_PROT_T10DIF_TYPE_2 |
514 IB_PROT_T10DIF_TYPE_3;
515 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
516 IB_GUARD_T10DIF_CSUM;
518 if (MLX5_CAP_GEN(mdev, block_lb_mc))
519 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
521 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
522 if (MLX5_CAP_ETH(mdev, csum_cap))
523 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
525 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
526 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
528 resp.tso_caps.max_tso = 1 << max_tso;
529 resp.tso_caps.supported_qpts |=
530 1 << IB_QPT_RAW_PACKET;
531 resp.response_length += sizeof(resp.tso_caps);
535 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
536 resp.rss_caps.rx_hash_function =
537 MLX5_RX_HASH_FUNC_TOEPLITZ;
538 resp.rss_caps.rx_hash_fields_mask =
539 MLX5_RX_HASH_SRC_IPV4 |
540 MLX5_RX_HASH_DST_IPV4 |
541 MLX5_RX_HASH_SRC_IPV6 |
542 MLX5_RX_HASH_DST_IPV6 |
543 MLX5_RX_HASH_SRC_PORT_TCP |
544 MLX5_RX_HASH_DST_PORT_TCP |
545 MLX5_RX_HASH_SRC_PORT_UDP |
546 MLX5_RX_HASH_DST_PORT_UDP;
547 resp.response_length += sizeof(resp.rss_caps);
550 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
551 resp.response_length += sizeof(resp.tso_caps);
552 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
553 resp.response_length += sizeof(resp.rss_caps);
556 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
557 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
558 props->device_cap_flags |= IB_DEVICE_UD_TSO;
561 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
562 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
563 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
565 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
566 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
568 props->vendor_part_id = mdev->pdev->device;
569 props->hw_ver = mdev->pdev->revision;
571 props->max_mr_size = ~0ull;
572 props->page_size_cap = ~(min_page_size - 1);
573 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
574 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
575 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
576 sizeof(struct mlx5_wqe_data_seg);
577 max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
578 sizeof(struct mlx5_wqe_ctrl_seg)) /
579 sizeof(struct mlx5_wqe_data_seg);
580 props->max_sge = min(max_rq_sg, max_sq_sg);
581 props->max_sge_rd = MLX5_MAX_SGE_RD;
582 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
583 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
584 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
585 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
586 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
587 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
588 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
589 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
590 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
591 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
592 props->max_srq_sge = max_rq_sg - 1;
593 props->max_fast_reg_page_list_len =
594 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
595 get_atomic_caps(dev, props);
596 props->masked_atomic_cap = IB_ATOMIC_NONE;
597 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
598 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
599 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
600 props->max_mcast_grp;
601 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
602 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
603 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
605 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
606 if (MLX5_CAP_GEN(mdev, pg))
607 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
608 props->odp_caps = dev->odp_caps;
611 if (MLX5_CAP_GEN(mdev, cd))
612 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
614 if (!mlx5_core_is_pf(mdev))
615 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
617 if (mlx5_ib_port_link_layer(ibdev, 1) ==
618 IB_LINK_LAYER_ETHERNET) {
619 props->rss_caps.max_rwq_indirection_tables =
620 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
621 props->rss_caps.max_rwq_indirection_table_size =
622 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
623 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
624 props->max_wq_type_rq =
625 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
629 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
639 MLX5_IB_WIDTH_1X = 1 << 0,
640 MLX5_IB_WIDTH_2X = 1 << 1,
641 MLX5_IB_WIDTH_4X = 1 << 2,
642 MLX5_IB_WIDTH_8X = 1 << 3,
643 MLX5_IB_WIDTH_12X = 1 << 4
646 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
649 struct mlx5_ib_dev *dev = to_mdev(ibdev);
652 if (active_width & MLX5_IB_WIDTH_1X) {
653 *ib_width = IB_WIDTH_1X;
654 } else if (active_width & MLX5_IB_WIDTH_2X) {
655 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
658 } else if (active_width & MLX5_IB_WIDTH_4X) {
659 *ib_width = IB_WIDTH_4X;
660 } else if (active_width & MLX5_IB_WIDTH_8X) {
661 *ib_width = IB_WIDTH_8X;
662 } else if (active_width & MLX5_IB_WIDTH_12X) {
663 *ib_width = IB_WIDTH_12X;
665 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
673 static int mlx5_mtu_to_ib_mtu(int mtu)
682 pr_warn("invalid mtu\n");
692 __IB_MAX_VL_0_14 = 5,
695 enum mlx5_vl_hw_cap {
707 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
712 *max_vl_num = __IB_MAX_VL_0;
715 *max_vl_num = __IB_MAX_VL_0_1;
718 *max_vl_num = __IB_MAX_VL_0_3;
721 *max_vl_num = __IB_MAX_VL_0_7;
723 case MLX5_VL_HW_0_14:
724 *max_vl_num = __IB_MAX_VL_0_14;
734 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
735 struct ib_port_attr *props)
737 struct mlx5_ib_dev *dev = to_mdev(ibdev);
738 struct mlx5_core_dev *mdev = dev->mdev;
739 struct mlx5_hca_vport_context *rep;
743 u8 ib_link_width_oper;
746 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
752 memset(props, 0, sizeof(*props));
754 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
758 props->lid = rep->lid;
759 props->lmc = rep->lmc;
760 props->sm_lid = rep->sm_lid;
761 props->sm_sl = rep->sm_sl;
762 props->state = rep->vport_state;
763 props->phys_state = rep->port_physical_state;
764 props->port_cap_flags = rep->cap_mask1;
765 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
766 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
767 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
768 props->bad_pkey_cntr = rep->pkey_violation_counter;
769 props->qkey_viol_cntr = rep->qkey_violation_counter;
770 props->subnet_timeout = rep->subnet_timeout;
771 props->init_type_reply = rep->init_type_reply;
772 props->grh_required = rep->grh_required;
774 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
778 err = translate_active_width(ibdev, ib_link_width_oper,
779 &props->active_width);
782 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
786 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
788 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
790 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
792 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
794 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
798 err = translate_max_vl_num(ibdev, vl_hw_cap,
805 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
806 struct ib_port_attr *props)
808 switch (mlx5_get_vport_access_method(ibdev)) {
809 case MLX5_VPORT_ACCESS_METHOD_MAD:
810 return mlx5_query_mad_ifc_port(ibdev, port, props);
812 case MLX5_VPORT_ACCESS_METHOD_HCA:
813 return mlx5_query_hca_port(ibdev, port, props);
815 case MLX5_VPORT_ACCESS_METHOD_NIC:
816 return mlx5_query_port_roce(ibdev, port, props);
823 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
826 struct mlx5_ib_dev *dev = to_mdev(ibdev);
827 struct mlx5_core_dev *mdev = dev->mdev;
829 switch (mlx5_get_vport_access_method(ibdev)) {
830 case MLX5_VPORT_ACCESS_METHOD_MAD:
831 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
833 case MLX5_VPORT_ACCESS_METHOD_HCA:
834 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
842 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
845 struct mlx5_ib_dev *dev = to_mdev(ibdev);
846 struct mlx5_core_dev *mdev = dev->mdev;
848 switch (mlx5_get_vport_access_method(ibdev)) {
849 case MLX5_VPORT_ACCESS_METHOD_MAD:
850 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
852 case MLX5_VPORT_ACCESS_METHOD_HCA:
853 case MLX5_VPORT_ACCESS_METHOD_NIC:
854 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
861 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
862 struct ib_device_modify *props)
864 struct mlx5_ib_dev *dev = to_mdev(ibdev);
865 struct mlx5_reg_node_desc in;
866 struct mlx5_reg_node_desc out;
869 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
872 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
876 * If possible, pass node desc to FW, so it can generate
877 * a 144 trap. If cmd fails, just ignore.
879 memcpy(&in, props->node_desc, 64);
880 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
881 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
885 memcpy(ibdev->node_desc, props->node_desc, 64);
890 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
891 struct ib_port_modify *props)
893 struct mlx5_ib_dev *dev = to_mdev(ibdev);
894 struct ib_port_attr attr;
898 mutex_lock(&dev->cap_mask_mutex);
900 err = mlx5_ib_query_port(ibdev, port, &attr);
904 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
905 ~props->clr_port_cap_mask;
907 err = mlx5_set_port_caps(dev->mdev, port, tmp);
910 mutex_unlock(&dev->cap_mask_mutex);
914 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
915 struct ib_udata *udata)
917 struct mlx5_ib_dev *dev = to_mdev(ibdev);
918 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
919 struct mlx5_ib_alloc_ucontext_resp resp = {};
920 struct mlx5_ib_ucontext *context;
921 struct mlx5_uuar_info *uuari;
922 struct mlx5_uar *uars;
930 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
934 return ERR_PTR(-EAGAIN);
936 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
937 return ERR_PTR(-EINVAL);
939 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
940 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
942 else if (reqlen >= min_req_v2)
945 return ERR_PTR(-EINVAL);
947 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
952 return ERR_PTR(-EINVAL);
954 if (req.total_num_uuars > MLX5_MAX_UUARS)
955 return ERR_PTR(-ENOMEM);
957 if (req.total_num_uuars == 0)
958 return ERR_PTR(-EINVAL);
960 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
961 return ERR_PTR(-EOPNOTSUPP);
963 if (reqlen > sizeof(req) &&
964 !ib_is_udata_cleared(udata, sizeof(req),
965 reqlen - sizeof(req)))
966 return ERR_PTR(-EOPNOTSUPP);
968 req.total_num_uuars = ALIGN(req.total_num_uuars,
969 MLX5_NON_FP_BF_REGS_PER_PAGE);
970 if (req.num_low_latency_uuars > req.total_num_uuars - 1)
971 return ERR_PTR(-EINVAL);
973 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
974 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
975 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
976 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
977 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
978 resp.cache_line_size = L1_CACHE_BYTES;
979 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
980 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
981 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
982 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
983 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
984 resp.cqe_version = min_t(__u8,
985 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
986 req.max_cqe_version);
987 resp.response_length = min(offsetof(typeof(resp), response_length) +
988 sizeof(resp.response_length), udata->outlen);
990 context = kzalloc(sizeof(*context), GFP_KERNEL);
992 return ERR_PTR(-ENOMEM);
994 uuari = &context->uuari;
995 mutex_init(&uuari->lock);
996 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
1002 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
1003 sizeof(*uuari->bitmap),
1005 if (!uuari->bitmap) {
1010 * clear all fast path uuars
1012 for (i = 0; i < gross_uuars; i++) {
1014 if (uuarn == 2 || uuarn == 3)
1015 set_bit(i, uuari->bitmap);
1018 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
1019 if (!uuari->count) {
1024 for (i = 0; i < num_uars; i++) {
1025 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
1030 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1031 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1034 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1035 err = mlx5_core_alloc_transport_domain(dev->mdev,
1041 INIT_LIST_HEAD(&context->vma_private_list);
1042 INIT_LIST_HEAD(&context->db_page_list);
1043 mutex_init(&context->db_page_mutex);
1045 resp.tot_uuars = req.total_num_uuars;
1046 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1048 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1049 resp.response_length += sizeof(resp.cqe_version);
1051 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1052 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE;
1053 resp.response_length += sizeof(resp.cmds_supp_uhw);
1057 * We don't want to expose information from the PCI bar that is located
1058 * after 4096 bytes, so if the arch only supports larger pages, let's
1059 * pretend we don't support reading the HCA's core clock. This is also
1060 * forced by mmap function.
1062 if (PAGE_SIZE <= 4096 &&
1063 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1065 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1066 resp.hca_core_clock_offset =
1067 offsetof(struct mlx5_init_seg, internal_timer_h) %
1069 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1070 sizeof(resp.reserved2);
1073 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1078 uuari->num_low_latency_uuars = req.num_low_latency_uuars;
1080 uuari->num_uars = num_uars;
1081 context->cqe_version = resp.cqe_version;
1083 return &context->ibucontext;
1086 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1087 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1090 for (i--; i >= 0; i--)
1091 mlx5_cmd_free_uar(dev->mdev, uars[i].index);
1093 kfree(uuari->count);
1096 kfree(uuari->bitmap);
1103 return ERR_PTR(err);
1106 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1108 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1109 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1110 struct mlx5_uuar_info *uuari = &context->uuari;
1113 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1114 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1116 for (i = 0; i < uuari->num_uars; i++) {
1117 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
1118 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
1121 kfree(uuari->count);
1122 kfree(uuari->bitmap);
1129 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
1131 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
1134 static int get_command(unsigned long offset)
1136 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1139 static int get_arg(unsigned long offset)
1141 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1144 static int get_index(unsigned long offset)
1146 return get_arg(offset);
1149 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1151 /* vma_open is called when a new VMA is created on top of our VMA. This
1152 * is done through either mremap flow or split_vma (usually due to
1153 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1154 * as this VMA is strongly hardware related. Therefore we set the
1155 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1156 * calling us again and trying to do incorrect actions. We assume that
1157 * the original VMA size is exactly a single page, and therefore all
1158 * "splitting" operation will not happen to it.
1160 area->vm_ops = NULL;
1163 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1165 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1167 /* It's guaranteed that all VMAs opened on a FD are closed before the
1168 * file itself is closed, therefore no sync is needed with the regular
1169 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1170 * However need a sync with accessing the vma as part of
1171 * mlx5_ib_disassociate_ucontext.
1172 * The close operation is usually called under mm->mmap_sem except when
1173 * process is exiting.
1174 * The exiting case is handled explicitly as part of
1175 * mlx5_ib_disassociate_ucontext.
1177 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1179 /* setting the vma context pointer to null in the mlx5_ib driver's
1180 * private data, to protect a race condition in
1181 * mlx5_ib_disassociate_ucontext().
1183 mlx5_ib_vma_priv_data->vma = NULL;
1184 list_del(&mlx5_ib_vma_priv_data->list);
1185 kfree(mlx5_ib_vma_priv_data);
1188 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1189 .open = mlx5_ib_vma_open,
1190 .close = mlx5_ib_vma_close
1193 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1194 struct mlx5_ib_ucontext *ctx)
1196 struct mlx5_ib_vma_private_data *vma_prv;
1197 struct list_head *vma_head = &ctx->vma_private_list;
1199 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1204 vma->vm_private_data = vma_prv;
1205 vma->vm_ops = &mlx5_ib_vm_ops;
1207 list_add(&vma_prv->list, vma_head);
1212 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1215 struct vm_area_struct *vma;
1216 struct mlx5_ib_vma_private_data *vma_private, *n;
1217 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1218 struct task_struct *owning_process = NULL;
1219 struct mm_struct *owning_mm = NULL;
1221 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1222 if (!owning_process)
1225 owning_mm = get_task_mm(owning_process);
1227 pr_info("no mm, disassociate ucontext is pending task termination\n");
1229 put_task_struct(owning_process);
1230 usleep_range(1000, 2000);
1231 owning_process = get_pid_task(ibcontext->tgid,
1233 if (!owning_process ||
1234 owning_process->state == TASK_DEAD) {
1235 pr_info("disassociate ucontext done, task was terminated\n");
1236 /* in case task was dead need to release the
1240 put_task_struct(owning_process);
1246 /* need to protect from a race on closing the vma as part of
1247 * mlx5_ib_vma_close.
1249 down_read(&owning_mm->mmap_sem);
1250 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1252 vma = vma_private->vma;
1253 ret = zap_vma_ptes(vma, vma->vm_start,
1255 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1256 /* context going to be destroyed, should
1257 * not access ops any more.
1260 list_del(&vma_private->list);
1263 up_read(&owning_mm->mmap_sem);
1265 put_task_struct(owning_process);
1268 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1271 case MLX5_IB_MMAP_WC_PAGE:
1273 case MLX5_IB_MMAP_REGULAR_PAGE:
1274 return "best effort WC";
1275 case MLX5_IB_MMAP_NC_PAGE:
1282 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1283 struct vm_area_struct *vma,
1284 struct mlx5_ib_ucontext *context)
1286 struct mlx5_uuar_info *uuari = &context->uuari;
1289 phys_addr_t pfn, pa;
1293 case MLX5_IB_MMAP_WC_PAGE:
1294 /* Some architectures don't support WC memory */
1295 #if defined(CONFIG_X86)
1298 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1302 case MLX5_IB_MMAP_REGULAR_PAGE:
1303 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1304 prot = pgprot_writecombine(vma->vm_page_prot);
1306 case MLX5_IB_MMAP_NC_PAGE:
1307 prot = pgprot_noncached(vma->vm_page_prot);
1313 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1316 idx = get_index(vma->vm_pgoff);
1317 if (idx >= uuari->num_uars)
1320 pfn = uar_index2pfn(dev, uuari->uars[idx].index);
1321 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1323 vma->vm_page_prot = prot;
1324 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1325 PAGE_SIZE, vma->vm_page_prot);
1327 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1328 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1332 pa = pfn << PAGE_SHIFT;
1333 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1334 vma->vm_start, &pa);
1336 return mlx5_ib_set_vma_data(vma, context);
1339 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1341 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1342 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1343 unsigned long command;
1346 command = get_command(vma->vm_pgoff);
1348 case MLX5_IB_MMAP_WC_PAGE:
1349 case MLX5_IB_MMAP_NC_PAGE:
1350 case MLX5_IB_MMAP_REGULAR_PAGE:
1351 return uar_mmap(dev, command, vma, context);
1353 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1356 case MLX5_IB_MMAP_CORE_CLOCK:
1357 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1360 if (vma->vm_flags & VM_WRITE)
1363 /* Don't expose to user-space information it shouldn't have */
1364 if (PAGE_SIZE > 4096)
1367 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1368 pfn = (dev->mdev->iseg_base +
1369 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1371 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1372 PAGE_SIZE, vma->vm_page_prot))
1375 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1377 (unsigned long long)pfn << PAGE_SHIFT);
1387 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1388 struct ib_ucontext *context,
1389 struct ib_udata *udata)
1391 struct mlx5_ib_alloc_pd_resp resp;
1392 struct mlx5_ib_pd *pd;
1395 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1397 return ERR_PTR(-ENOMEM);
1399 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1402 return ERR_PTR(err);
1407 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1408 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1410 return ERR_PTR(-EFAULT);
1417 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1419 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1420 struct mlx5_ib_pd *mpd = to_mpd(pd);
1422 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1428 static bool outer_header_zero(u32 *match_criteria)
1430 int size = MLX5_ST_SZ_BYTES(fte_match_param);
1431 char *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_criteria,
1434 return outer_headers_c[0] == 0 && !memcmp(outer_headers_c,
1435 outer_headers_c + 1,
1439 #define LAST_ETH_FIELD vlan_tag
1440 #define LAST_IB_FIELD sl
1441 #define LAST_IPV4_FIELD dst_ip
1442 #define LAST_IPV6_FIELD dst_ip
1443 #define LAST_TCP_UDP_FIELD src_port
1445 /* Field is the last supported field */
1446 #define FIELDS_NOT_SUPPORTED(filter, field)\
1447 memchr_inv((void *)&filter.field +\
1448 sizeof(filter.field), 0,\
1450 offsetof(typeof(filter), field) -\
1451 sizeof(filter.field))
1453 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1454 const union ib_flow_spec *ib_spec)
1456 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1458 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1460 switch (ib_spec->type) {
1461 case IB_FLOW_SPEC_ETH:
1462 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1465 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1467 ib_spec->eth.mask.dst_mac);
1468 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1470 ib_spec->eth.val.dst_mac);
1472 if (ib_spec->eth.mask.vlan_tag) {
1473 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1475 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1478 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1479 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1480 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1481 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1483 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1485 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1486 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1488 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1490 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1492 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1493 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1495 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1497 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1498 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1499 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1500 ethertype, ntohs(ib_spec->eth.val.ether_type));
1502 case IB_FLOW_SPEC_IPV4:
1503 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1506 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1508 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1509 ethertype, ETH_P_IP);
1511 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1512 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1513 &ib_spec->ipv4.mask.src_ip,
1514 sizeof(ib_spec->ipv4.mask.src_ip));
1515 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1516 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1517 &ib_spec->ipv4.val.src_ip,
1518 sizeof(ib_spec->ipv4.val.src_ip));
1519 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1520 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1521 &ib_spec->ipv4.mask.dst_ip,
1522 sizeof(ib_spec->ipv4.mask.dst_ip));
1523 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1524 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1525 &ib_spec->ipv4.val.dst_ip,
1526 sizeof(ib_spec->ipv4.val.dst_ip));
1528 case IB_FLOW_SPEC_IPV6:
1529 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1532 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c,
1534 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v,
1535 ethertype, ETH_P_IPV6);
1537 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1538 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1539 &ib_spec->ipv6.mask.src_ip,
1540 sizeof(ib_spec->ipv6.mask.src_ip));
1541 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1542 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1543 &ib_spec->ipv6.val.src_ip,
1544 sizeof(ib_spec->ipv6.val.src_ip));
1545 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c,
1546 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1547 &ib_spec->ipv6.mask.dst_ip,
1548 sizeof(ib_spec->ipv6.mask.dst_ip));
1549 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v,
1550 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1551 &ib_spec->ipv6.val.dst_ip,
1552 sizeof(ib_spec->ipv6.val.dst_ip));
1554 case IB_FLOW_SPEC_TCP:
1555 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1556 LAST_TCP_UDP_FIELD))
1559 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1561 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1564 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport,
1565 ntohs(ib_spec->tcp_udp.mask.src_port));
1566 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport,
1567 ntohs(ib_spec->tcp_udp.val.src_port));
1569 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport,
1570 ntohs(ib_spec->tcp_udp.mask.dst_port));
1571 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport,
1572 ntohs(ib_spec->tcp_udp.val.dst_port));
1574 case IB_FLOW_SPEC_UDP:
1575 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1576 LAST_TCP_UDP_FIELD))
1579 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol,
1581 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol,
1584 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport,
1585 ntohs(ib_spec->tcp_udp.mask.src_port));
1586 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport,
1587 ntohs(ib_spec->tcp_udp.val.src_port));
1589 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport,
1590 ntohs(ib_spec->tcp_udp.mask.dst_port));
1591 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport,
1592 ntohs(ib_spec->tcp_udp.val.dst_port));
1601 /* If a flow could catch both multicast and unicast packets,
1602 * it won't fall into the multicast flow steering table and this rule
1603 * could steal other multicast packets.
1605 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1607 struct ib_flow_spec_eth *eth_spec;
1609 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1610 ib_attr->size < sizeof(struct ib_flow_attr) +
1611 sizeof(struct ib_flow_spec_eth) ||
1612 ib_attr->num_of_specs < 1)
1615 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1616 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1617 eth_spec->size != sizeof(*eth_spec))
1620 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1621 is_multicast_ether_addr(eth_spec->val.dst_mac);
1624 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1626 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1627 bool has_ipv4_spec = false;
1628 bool eth_type_ipv4 = true;
1629 unsigned int spec_index;
1631 /* Validate that ethertype is correct */
1632 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1633 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1634 ib_spec->eth.mask.ether_type) {
1635 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1636 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1637 eth_type_ipv4 = false;
1638 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1639 has_ipv4_spec = true;
1641 ib_spec = (void *)ib_spec + ib_spec->size;
1643 return !has_ipv4_spec || eth_type_ipv4;
1646 static void put_flow_table(struct mlx5_ib_dev *dev,
1647 struct mlx5_ib_flow_prio *prio, bool ft_added)
1649 prio->refcount -= !!ft_added;
1650 if (!prio->refcount) {
1651 mlx5_destroy_flow_table(prio->flow_table);
1652 prio->flow_table = NULL;
1656 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1658 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1659 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1660 struct mlx5_ib_flow_handler,
1662 struct mlx5_ib_flow_handler *iter, *tmp;
1664 mutex_lock(&dev->flow_db.lock);
1666 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1667 mlx5_del_flow_rule(iter->rule);
1668 put_flow_table(dev, iter->prio, true);
1669 list_del(&iter->list);
1673 mlx5_del_flow_rule(handler->rule);
1674 put_flow_table(dev, handler->prio, true);
1675 mutex_unlock(&dev->flow_db.lock);
1682 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1690 enum flow_table_type {
1695 #define MLX5_FS_MAX_TYPES 10
1696 #define MLX5_FS_MAX_ENTRIES 32000UL
1697 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1698 struct ib_flow_attr *flow_attr,
1699 enum flow_table_type ft_type)
1701 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1702 struct mlx5_flow_namespace *ns = NULL;
1703 struct mlx5_ib_flow_prio *prio;
1704 struct mlx5_flow_table *ft;
1710 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1711 if (flow_is_multicast_only(flow_attr) &&
1713 priority = MLX5_IB_FLOW_MCAST_PRIO;
1715 priority = ib_prio_to_core_prio(flow_attr->priority,
1717 ns = mlx5_get_flow_namespace(dev->mdev,
1718 MLX5_FLOW_NAMESPACE_BYPASS);
1719 num_entries = MLX5_FS_MAX_ENTRIES;
1720 num_groups = MLX5_FS_MAX_TYPES;
1721 prio = &dev->flow_db.prios[priority];
1722 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
1723 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
1724 ns = mlx5_get_flow_namespace(dev->mdev,
1725 MLX5_FLOW_NAMESPACE_LEFTOVERS);
1726 build_leftovers_ft_param(&priority,
1729 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
1730 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1731 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
1732 allow_sniffer_and_nic_rx_shared_tir))
1733 return ERR_PTR(-ENOTSUPP);
1735 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
1736 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
1737 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
1739 prio = &dev->flow_db.sniffer[ft_type];
1746 return ERR_PTR(-ENOTSUPP);
1748 ft = prio->flow_table;
1750 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
1757 prio->flow_table = ft;
1763 return err ? ERR_PTR(err) : prio;
1766 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
1767 struct mlx5_ib_flow_prio *ft_prio,
1768 const struct ib_flow_attr *flow_attr,
1769 struct mlx5_flow_destination *dst)
1771 struct mlx5_flow_table *ft = ft_prio->flow_table;
1772 struct mlx5_ib_flow_handler *handler;
1773 struct mlx5_flow_spec *spec;
1774 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
1775 unsigned int spec_index;
1779 if (!is_valid_attr(flow_attr))
1780 return ERR_PTR(-EINVAL);
1782 spec = mlx5_vzalloc(sizeof(*spec));
1783 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
1784 if (!handler || !spec) {
1789 INIT_LIST_HEAD(&handler->list);
1791 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1792 err = parse_flow_attr(spec->match_criteria,
1793 spec->match_value, ib_flow);
1797 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
1800 /* Outer header support only */
1801 spec->match_criteria_enable = (!outer_header_zero(spec->match_criteria))
1803 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
1804 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
1805 handler->rule = mlx5_add_flow_rule(ft, spec,
1807 MLX5_FS_DEFAULT_FLOW_TAG,
1810 if (IS_ERR(handler->rule)) {
1811 err = PTR_ERR(handler->rule);
1815 ft_prio->refcount++;
1816 handler->prio = ft_prio;
1818 ft_prio->flow_table = ft;
1823 return err ? ERR_PTR(err) : handler;
1826 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
1827 struct mlx5_ib_flow_prio *ft_prio,
1828 struct ib_flow_attr *flow_attr,
1829 struct mlx5_flow_destination *dst)
1831 struct mlx5_ib_flow_handler *handler_dst = NULL;
1832 struct mlx5_ib_flow_handler *handler = NULL;
1834 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
1835 if (!IS_ERR(handler)) {
1836 handler_dst = create_flow_rule(dev, ft_prio,
1838 if (IS_ERR(handler_dst)) {
1839 mlx5_del_flow_rule(handler->rule);
1840 ft_prio->refcount--;
1842 handler = handler_dst;
1844 list_add(&handler_dst->list, &handler->list);
1855 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
1856 struct mlx5_ib_flow_prio *ft_prio,
1857 struct ib_flow_attr *flow_attr,
1858 struct mlx5_flow_destination *dst)
1860 struct mlx5_ib_flow_handler *handler_ucast = NULL;
1861 struct mlx5_ib_flow_handler *handler = NULL;
1864 struct ib_flow_attr flow_attr;
1865 struct ib_flow_spec_eth eth_flow;
1866 } leftovers_specs[] = {
1870 .size = sizeof(leftovers_specs[0])
1873 .type = IB_FLOW_SPEC_ETH,
1874 .size = sizeof(struct ib_flow_spec_eth),
1875 .mask = {.dst_mac = {0x1} },
1876 .val = {.dst_mac = {0x1} }
1882 .size = sizeof(leftovers_specs[0])
1885 .type = IB_FLOW_SPEC_ETH,
1886 .size = sizeof(struct ib_flow_spec_eth),
1887 .mask = {.dst_mac = {0x1} },
1888 .val = {.dst_mac = {} }
1893 handler = create_flow_rule(dev, ft_prio,
1894 &leftovers_specs[LEFTOVERS_MC].flow_attr,
1896 if (!IS_ERR(handler) &&
1897 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
1898 handler_ucast = create_flow_rule(dev, ft_prio,
1899 &leftovers_specs[LEFTOVERS_UC].flow_attr,
1901 if (IS_ERR(handler_ucast)) {
1902 mlx5_del_flow_rule(handler->rule);
1903 ft_prio->refcount--;
1905 handler = handler_ucast;
1907 list_add(&handler_ucast->list, &handler->list);
1914 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
1915 struct mlx5_ib_flow_prio *ft_rx,
1916 struct mlx5_ib_flow_prio *ft_tx,
1917 struct mlx5_flow_destination *dst)
1919 struct mlx5_ib_flow_handler *handler_rx;
1920 struct mlx5_ib_flow_handler *handler_tx;
1922 static const struct ib_flow_attr flow_attr = {
1924 .size = sizeof(flow_attr)
1927 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
1928 if (IS_ERR(handler_rx)) {
1929 err = PTR_ERR(handler_rx);
1933 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
1934 if (IS_ERR(handler_tx)) {
1935 err = PTR_ERR(handler_tx);
1939 list_add(&handler_tx->list, &handler_rx->list);
1944 mlx5_del_flow_rule(handler_rx->rule);
1948 return ERR_PTR(err);
1951 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
1952 struct ib_flow_attr *flow_attr,
1955 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1956 struct mlx5_ib_flow_handler *handler = NULL;
1957 struct mlx5_flow_destination *dst = NULL;
1958 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
1959 struct mlx5_ib_flow_prio *ft_prio;
1962 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
1963 return ERR_PTR(-ENOSPC);
1965 if (domain != IB_FLOW_DOMAIN_USER ||
1966 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
1967 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
1968 return ERR_PTR(-EINVAL);
1970 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
1972 return ERR_PTR(-ENOMEM);
1974 mutex_lock(&dev->flow_db.lock);
1976 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
1977 if (IS_ERR(ft_prio)) {
1978 err = PTR_ERR(ft_prio);
1981 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
1982 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
1983 if (IS_ERR(ft_prio_tx)) {
1984 err = PTR_ERR(ft_prio_tx);
1990 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1991 dst->tir_num = to_mqp(qp)->raw_packet_qp.rq.tirn;
1993 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1994 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
1995 handler = create_dont_trap_rule(dev, ft_prio,
1998 handler = create_flow_rule(dev, ft_prio, flow_attr,
2001 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2002 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2003 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2005 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2006 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2012 if (IS_ERR(handler)) {
2013 err = PTR_ERR(handler);
2018 mutex_unlock(&dev->flow_db.lock);
2021 return &handler->ibflow;
2024 put_flow_table(dev, ft_prio, false);
2026 put_flow_table(dev, ft_prio_tx, false);
2028 mutex_unlock(&dev->flow_db.lock);
2031 return ERR_PTR(err);
2034 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2036 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2039 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2041 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2042 ibqp->qp_num, gid->raw);
2047 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2049 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2052 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2054 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2055 ibqp->qp_num, gid->raw);
2060 static int init_node_data(struct mlx5_ib_dev *dev)
2064 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2068 dev->mdev->rev_id = dev->mdev->pdev->revision;
2070 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2073 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2076 struct mlx5_ib_dev *dev =
2077 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2079 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2082 static ssize_t show_reg_pages(struct device *device,
2083 struct device_attribute *attr, char *buf)
2085 struct mlx5_ib_dev *dev =
2086 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2088 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2091 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2094 struct mlx5_ib_dev *dev =
2095 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2096 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2099 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2102 struct mlx5_ib_dev *dev =
2103 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2104 return sprintf(buf, "%x\n", dev->mdev->rev_id);
2107 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2110 struct mlx5_ib_dev *dev =
2111 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2112 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2113 dev->mdev->board_id);
2116 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2117 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2118 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2119 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2120 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2122 static struct device_attribute *mlx5_class_attributes[] = {
2127 &dev_attr_reg_pages,
2130 static void pkey_change_handler(struct work_struct *work)
2132 struct mlx5_ib_port_resources *ports =
2133 container_of(work, struct mlx5_ib_port_resources,
2136 mutex_lock(&ports->devr->mutex);
2137 mlx5_ib_gsi_pkey_change(ports->gsi);
2138 mutex_unlock(&ports->devr->mutex);
2141 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2143 struct mlx5_ib_qp *mqp;
2144 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2145 struct mlx5_core_cq *mcq;
2146 struct list_head cq_armed_list;
2147 unsigned long flags_qp;
2148 unsigned long flags_cq;
2149 unsigned long flags;
2151 INIT_LIST_HEAD(&cq_armed_list);
2153 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2154 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2155 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2156 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2157 if (mqp->sq.tail != mqp->sq.head) {
2158 send_mcq = to_mcq(mqp->ibqp.send_cq);
2159 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2160 if (send_mcq->mcq.comp &&
2161 mqp->ibqp.send_cq->comp_handler) {
2162 if (!send_mcq->mcq.reset_notify_added) {
2163 send_mcq->mcq.reset_notify_added = 1;
2164 list_add_tail(&send_mcq->mcq.reset_notify,
2168 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2170 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2171 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2172 /* no handling is needed for SRQ */
2173 if (!mqp->ibqp.srq) {
2174 if (mqp->rq.tail != mqp->rq.head) {
2175 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2176 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2177 if (recv_mcq->mcq.comp &&
2178 mqp->ibqp.recv_cq->comp_handler) {
2179 if (!recv_mcq->mcq.reset_notify_added) {
2180 recv_mcq->mcq.reset_notify_added = 1;
2181 list_add_tail(&recv_mcq->mcq.reset_notify,
2185 spin_unlock_irqrestore(&recv_mcq->lock,
2189 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2191 /*At that point all inflight post send were put to be executed as of we
2192 * lock/unlock above locks Now need to arm all involved CQs.
2194 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2197 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2200 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2201 enum mlx5_dev_event event, unsigned long param)
2203 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2204 struct ib_event ibev;
2209 case MLX5_DEV_EVENT_SYS_ERROR:
2210 ibdev->ib_active = false;
2211 ibev.event = IB_EVENT_DEVICE_FATAL;
2212 mlx5_ib_handle_internal_error(ibdev);
2215 case MLX5_DEV_EVENT_PORT_UP:
2216 ibev.event = IB_EVENT_PORT_ACTIVE;
2220 case MLX5_DEV_EVENT_PORT_DOWN:
2221 case MLX5_DEV_EVENT_PORT_INITIALIZED:
2222 ibev.event = IB_EVENT_PORT_ERR;
2226 case MLX5_DEV_EVENT_LID_CHANGE:
2227 ibev.event = IB_EVENT_LID_CHANGE;
2231 case MLX5_DEV_EVENT_PKEY_CHANGE:
2232 ibev.event = IB_EVENT_PKEY_CHANGE;
2235 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2238 case MLX5_DEV_EVENT_GUID_CHANGE:
2239 ibev.event = IB_EVENT_GID_CHANGE;
2243 case MLX5_DEV_EVENT_CLIENT_REREG:
2244 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2249 ibev.device = &ibdev->ib_dev;
2250 ibev.element.port_num = port;
2252 if (port < 1 || port > ibdev->num_ports) {
2253 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2257 if (ibdev->ib_active)
2258 ib_dispatch_event(&ibev);
2261 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2265 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2266 mlx5_query_ext_port_caps(dev, port);
2269 static int get_port_caps(struct mlx5_ib_dev *dev)
2271 struct ib_device_attr *dprops = NULL;
2272 struct ib_port_attr *pprops = NULL;
2275 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2277 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2281 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2285 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2287 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2291 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2292 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2294 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2298 dev->mdev->port_caps[port - 1].pkey_table_len =
2300 dev->mdev->port_caps[port - 1].gid_table_len =
2301 pprops->gid_tbl_len;
2302 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2303 dprops->max_pkeys, pprops->gid_tbl_len);
2313 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2317 err = mlx5_mr_cache_cleanup(dev);
2319 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2321 mlx5_ib_destroy_qp(dev->umrc.qp);
2322 ib_free_cq(dev->umrc.cq);
2323 ib_dealloc_pd(dev->umrc.pd);
2330 static int create_umr_res(struct mlx5_ib_dev *dev)
2332 struct ib_qp_init_attr *init_attr = NULL;
2333 struct ib_qp_attr *attr = NULL;
2339 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2340 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2341 if (!attr || !init_attr) {
2346 pd = ib_alloc_pd(&dev->ib_dev, 0);
2348 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2353 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2355 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2360 init_attr->send_cq = cq;
2361 init_attr->recv_cq = cq;
2362 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2363 init_attr->cap.max_send_wr = MAX_UMR_WR;
2364 init_attr->cap.max_send_sge = 1;
2365 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2366 init_attr->port_num = 1;
2367 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2369 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2373 qp->device = &dev->ib_dev;
2376 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2378 attr->qp_state = IB_QPS_INIT;
2380 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2383 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2387 memset(attr, 0, sizeof(*attr));
2388 attr->qp_state = IB_QPS_RTR;
2389 attr->path_mtu = IB_MTU_256;
2391 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2393 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2397 memset(attr, 0, sizeof(*attr));
2398 attr->qp_state = IB_QPS_RTS;
2399 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2401 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2409 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2410 ret = mlx5_mr_cache_init(dev);
2412 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2422 mlx5_ib_destroy_qp(qp);
2436 static int create_dev_resources(struct mlx5_ib_resources *devr)
2438 struct ib_srq_init_attr attr;
2439 struct mlx5_ib_dev *dev;
2440 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2444 dev = container_of(devr, struct mlx5_ib_dev, devr);
2446 mutex_init(&devr->mutex);
2448 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2449 if (IS_ERR(devr->p0)) {
2450 ret = PTR_ERR(devr->p0);
2453 devr->p0->device = &dev->ib_dev;
2454 devr->p0->uobject = NULL;
2455 atomic_set(&devr->p0->usecnt, 0);
2457 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2458 if (IS_ERR(devr->c0)) {
2459 ret = PTR_ERR(devr->c0);
2462 devr->c0->device = &dev->ib_dev;
2463 devr->c0->uobject = NULL;
2464 devr->c0->comp_handler = NULL;
2465 devr->c0->event_handler = NULL;
2466 devr->c0->cq_context = NULL;
2467 atomic_set(&devr->c0->usecnt, 0);
2469 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2470 if (IS_ERR(devr->x0)) {
2471 ret = PTR_ERR(devr->x0);
2474 devr->x0->device = &dev->ib_dev;
2475 devr->x0->inode = NULL;
2476 atomic_set(&devr->x0->usecnt, 0);
2477 mutex_init(&devr->x0->tgt_qp_mutex);
2478 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2480 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2481 if (IS_ERR(devr->x1)) {
2482 ret = PTR_ERR(devr->x1);
2485 devr->x1->device = &dev->ib_dev;
2486 devr->x1->inode = NULL;
2487 atomic_set(&devr->x1->usecnt, 0);
2488 mutex_init(&devr->x1->tgt_qp_mutex);
2489 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2491 memset(&attr, 0, sizeof(attr));
2492 attr.attr.max_sge = 1;
2493 attr.attr.max_wr = 1;
2494 attr.srq_type = IB_SRQT_XRC;
2495 attr.ext.xrc.cq = devr->c0;
2496 attr.ext.xrc.xrcd = devr->x0;
2498 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2499 if (IS_ERR(devr->s0)) {
2500 ret = PTR_ERR(devr->s0);
2503 devr->s0->device = &dev->ib_dev;
2504 devr->s0->pd = devr->p0;
2505 devr->s0->uobject = NULL;
2506 devr->s0->event_handler = NULL;
2507 devr->s0->srq_context = NULL;
2508 devr->s0->srq_type = IB_SRQT_XRC;
2509 devr->s0->ext.xrc.xrcd = devr->x0;
2510 devr->s0->ext.xrc.cq = devr->c0;
2511 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2512 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2513 atomic_inc(&devr->p0->usecnt);
2514 atomic_set(&devr->s0->usecnt, 0);
2516 memset(&attr, 0, sizeof(attr));
2517 attr.attr.max_sge = 1;
2518 attr.attr.max_wr = 1;
2519 attr.srq_type = IB_SRQT_BASIC;
2520 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2521 if (IS_ERR(devr->s1)) {
2522 ret = PTR_ERR(devr->s1);
2525 devr->s1->device = &dev->ib_dev;
2526 devr->s1->pd = devr->p0;
2527 devr->s1->uobject = NULL;
2528 devr->s1->event_handler = NULL;
2529 devr->s1->srq_context = NULL;
2530 devr->s1->srq_type = IB_SRQT_BASIC;
2531 devr->s1->ext.xrc.cq = devr->c0;
2532 atomic_inc(&devr->p0->usecnt);
2533 atomic_set(&devr->s0->usecnt, 0);
2535 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2536 INIT_WORK(&devr->ports[port].pkey_change_work,
2537 pkey_change_handler);
2538 devr->ports[port].devr = devr;
2544 mlx5_ib_destroy_srq(devr->s0);
2546 mlx5_ib_dealloc_xrcd(devr->x1);
2548 mlx5_ib_dealloc_xrcd(devr->x0);
2550 mlx5_ib_destroy_cq(devr->c0);
2552 mlx5_ib_dealloc_pd(devr->p0);
2557 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2559 struct mlx5_ib_dev *dev =
2560 container_of(devr, struct mlx5_ib_dev, devr);
2563 mlx5_ib_destroy_srq(devr->s1);
2564 mlx5_ib_destroy_srq(devr->s0);
2565 mlx5_ib_dealloc_xrcd(devr->x0);
2566 mlx5_ib_dealloc_xrcd(devr->x1);
2567 mlx5_ib_destroy_cq(devr->c0);
2568 mlx5_ib_dealloc_pd(devr->p0);
2570 /* Make sure no change P_Key work items are still executing */
2571 for (port = 0; port < dev->num_ports; ++port)
2572 cancel_work_sync(&devr->ports[port].pkey_change_work);
2575 static u32 get_core_cap_flags(struct ib_device *ibdev)
2577 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2578 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2579 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2580 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2583 if (ll == IB_LINK_LAYER_INFINIBAND)
2584 return RDMA_CORE_PORT_IBA_IB;
2586 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2589 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2592 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2593 ret |= RDMA_CORE_PORT_IBA_ROCE;
2595 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2596 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2601 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2602 struct ib_port_immutable *immutable)
2604 struct ib_port_attr attr;
2607 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2611 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2612 immutable->gid_tbl_len = attr.gid_tbl_len;
2613 immutable->core_cap_flags = get_core_cap_flags(ibdev);
2614 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2619 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2622 struct mlx5_ib_dev *dev =
2623 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2624 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2625 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2628 static int mlx5_enable_roce(struct mlx5_ib_dev *dev)
2632 dev->roce.nb.notifier_call = mlx5_netdev_event;
2633 err = register_netdevice_notifier(&dev->roce.nb);
2637 err = mlx5_nic_vport_enable_roce(dev->mdev);
2639 goto err_unregister_netdevice_notifier;
2643 err_unregister_netdevice_notifier:
2644 unregister_netdevice_notifier(&dev->roce.nb);
2648 static void mlx5_disable_roce(struct mlx5_ib_dev *dev)
2650 mlx5_nic_vport_disable_roce(dev->mdev);
2651 unregister_netdevice_notifier(&dev->roce.nb);
2654 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
2658 for (i = 0; i < dev->num_ports; i++)
2659 mlx5_core_dealloc_q_counter(dev->mdev,
2660 dev->port[i].q_cnt_id);
2663 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
2668 for (i = 0; i < dev->num_ports; i++) {
2669 ret = mlx5_core_alloc_q_counter(dev->mdev,
2670 &dev->port[i].q_cnt_id);
2673 "couldn't allocate queue counter for port %d, err %d\n",
2675 goto dealloc_counters;
2683 mlx5_core_dealloc_q_counter(dev->mdev,
2684 dev->port[i].q_cnt_id);
2689 static const char * const names[] = {
2690 "rx_write_requests",
2692 "rx_atomic_requests",
2695 "duplicate_request",
2696 "rnr_nak_retry_err",
2698 "implied_nak_seq_err",
2699 "local_ack_timeout_err",
2702 static const size_t stats_offsets[] = {
2703 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
2704 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
2705 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
2706 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
2707 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
2708 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
2709 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
2710 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
2711 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
2712 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
2715 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
2718 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
2720 /* We support only per port stats */
2724 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
2725 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2728 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
2729 struct rdma_hw_stats *stats,
2732 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2733 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
2739 if (!port || !stats)
2742 out = mlx5_vzalloc(outlen);
2746 ret = mlx5_core_query_q_counter(dev->mdev,
2747 dev->port[port - 1].q_cnt_id, 0,
2752 for (i = 0; i < ARRAY_SIZE(names); i++) {
2753 val = *(__be32 *)(out + stats_offsets[i]);
2754 stats->value[i] = (u64)be32_to_cpu(val);
2758 return ARRAY_SIZE(names);
2761 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
2763 struct mlx5_ib_dev *dev;
2764 enum rdma_link_layer ll;
2769 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
2770 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
2772 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce))
2775 printk_once(KERN_INFO "%s", mlx5_version);
2777 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
2783 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
2788 rwlock_init(&dev->roce.netdev_lock);
2789 err = get_port_caps(dev);
2793 if (mlx5_use_mad_ifc(dev))
2794 get_ext_port_caps(dev);
2796 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
2798 strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
2799 dev->ib_dev.owner = THIS_MODULE;
2800 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
2801 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
2802 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
2803 dev->ib_dev.phys_port_cnt = dev->num_ports;
2804 dev->ib_dev.num_comp_vectors =
2805 dev->mdev->priv.eq_table.num_comp_vectors;
2806 dev->ib_dev.dma_device = &mdev->pdev->dev;
2808 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
2809 dev->ib_dev.uverbs_cmd_mask =
2810 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2811 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2812 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2813 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2814 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2815 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2816 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
2817 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2818 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2819 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2820 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2821 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2822 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2823 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2824 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2825 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2826 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2827 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2828 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2829 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2830 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2831 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2832 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2833 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2834 dev->ib_dev.uverbs_ex_cmd_mask =
2835 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2836 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2837 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2839 dev->ib_dev.query_device = mlx5_ib_query_device;
2840 dev->ib_dev.query_port = mlx5_ib_query_port;
2841 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
2842 if (ll == IB_LINK_LAYER_ETHERNET)
2843 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
2844 dev->ib_dev.query_gid = mlx5_ib_query_gid;
2845 dev->ib_dev.add_gid = mlx5_ib_add_gid;
2846 dev->ib_dev.del_gid = mlx5_ib_del_gid;
2847 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
2848 dev->ib_dev.modify_device = mlx5_ib_modify_device;
2849 dev->ib_dev.modify_port = mlx5_ib_modify_port;
2850 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
2851 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
2852 dev->ib_dev.mmap = mlx5_ib_mmap;
2853 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
2854 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
2855 dev->ib_dev.create_ah = mlx5_ib_create_ah;
2856 dev->ib_dev.query_ah = mlx5_ib_query_ah;
2857 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
2858 dev->ib_dev.create_srq = mlx5_ib_create_srq;
2859 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
2860 dev->ib_dev.query_srq = mlx5_ib_query_srq;
2861 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
2862 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
2863 dev->ib_dev.create_qp = mlx5_ib_create_qp;
2864 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
2865 dev->ib_dev.query_qp = mlx5_ib_query_qp;
2866 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
2867 dev->ib_dev.post_send = mlx5_ib_post_send;
2868 dev->ib_dev.post_recv = mlx5_ib_post_recv;
2869 dev->ib_dev.create_cq = mlx5_ib_create_cq;
2870 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
2871 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
2872 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
2873 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
2874 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
2875 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
2876 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
2877 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
2878 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
2879 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
2880 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
2881 dev->ib_dev.process_mad = mlx5_ib_process_mad;
2882 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
2883 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
2884 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
2885 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
2886 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
2887 if (mlx5_core_is_pf(mdev)) {
2888 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
2889 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
2890 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
2891 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
2894 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
2896 mlx5_ib_internal_fill_odp_caps(dev);
2898 if (MLX5_CAP_GEN(mdev, imaicl)) {
2899 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
2900 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
2901 dev->ib_dev.uverbs_cmd_mask |=
2902 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2903 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2906 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
2907 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
2908 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
2909 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
2912 if (MLX5_CAP_GEN(mdev, xrc)) {
2913 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
2914 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
2915 dev->ib_dev.uverbs_cmd_mask |=
2916 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2917 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2920 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
2921 IB_LINK_LAYER_ETHERNET) {
2922 dev->ib_dev.create_flow = mlx5_ib_create_flow;
2923 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
2924 dev->ib_dev.create_wq = mlx5_ib_create_wq;
2925 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
2926 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
2927 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
2928 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
2929 dev->ib_dev.uverbs_ex_cmd_mask |=
2930 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2931 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
2932 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
2933 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
2934 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
2935 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
2936 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
2938 err = init_node_data(dev);
2942 mutex_init(&dev->flow_db.lock);
2943 mutex_init(&dev->cap_mask_mutex);
2944 INIT_LIST_HEAD(&dev->qp_list);
2945 spin_lock_init(&dev->reset_flow_resource_lock);
2947 if (ll == IB_LINK_LAYER_ETHERNET) {
2948 err = mlx5_enable_roce(dev);
2953 err = create_dev_resources(&dev->devr);
2955 goto err_disable_roce;
2957 err = mlx5_ib_odp_init_one(dev);
2961 err = mlx5_ib_alloc_q_counters(dev);
2965 err = ib_register_device(&dev->ib_dev, NULL);
2969 err = create_umr_res(dev);
2973 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
2974 err = device_create_file(&dev->ib_dev.dev,
2975 mlx5_class_attributes[i]);
2980 dev->ib_active = true;
2985 destroy_umrc_res(dev);
2988 ib_unregister_device(&dev->ib_dev);
2991 mlx5_ib_dealloc_q_counters(dev);
2994 mlx5_ib_odp_remove_one(dev);
2997 destroy_dev_resources(&dev->devr);
3000 if (ll == IB_LINK_LAYER_ETHERNET)
3001 mlx5_disable_roce(dev);
3007 ib_dealloc_device((struct ib_device *)dev);
3012 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3014 struct mlx5_ib_dev *dev = context;
3015 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3017 ib_unregister_device(&dev->ib_dev);
3018 mlx5_ib_dealloc_q_counters(dev);
3019 destroy_umrc_res(dev);
3020 mlx5_ib_odp_remove_one(dev);
3021 destroy_dev_resources(&dev->devr);
3022 if (ll == IB_LINK_LAYER_ETHERNET)
3023 mlx5_disable_roce(dev);
3025 ib_dealloc_device(&dev->ib_dev);
3028 static struct mlx5_interface mlx5_ib_interface = {
3030 .remove = mlx5_ib_remove,
3031 .event = mlx5_ib_event,
3032 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
3035 static int __init mlx5_ib_init(void)
3039 if (deprecated_prof_sel != 2)
3040 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3042 err = mlx5_ib_odp_init();
3046 err = mlx5_register_interface(&mlx5_ib_interface);
3053 mlx5_ib_odp_cleanup();
3057 static void __exit mlx5_ib_cleanup(void)
3059 mlx5_unregister_interface(&mlx5_ib_interface);
3060 mlx5_ib_odp_cleanup();
3063 module_init(mlx5_ib_init);
3064 module_exit(mlx5_ib_cleanup);