drivers/infiniband/hw/qedr/qedr_cm.c

   1 /* QLogic qedr NIC Driver
   2  * Copyright (c) 2015-2016  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #include <linux/dma-mapping.h>
  33 #include <linux/crc32.h>
  34 #include <linux/iommu.h>
  35 #include <net/ip.h>
  36 #include <net/ipv6.h>
  37 #include <net/udp.h>
  38
  39 #include <rdma/ib_verbs.h>
  40 #include <rdma/ib_user_verbs.h>
  41 #include <rdma/iw_cm.h>
  42 #include <rdma/ib_umem.h>
  43 #include <rdma/ib_addr.h>
  44 #include <rdma/ib_cache.h>
  45
  46 #include "qedr_hsi.h"
  47 #include <linux/qed/qed_if.h>
  48 #include <linux/qed/qed_roce_if.h>
  49 #include "qedr.h"
  50 #include "qedr_hsi.h"
  51 #include "verbs.h"
  52 #include <rdma/qedr-abi.h>
  53 #include "qedr_hsi.h"
  54 #include "qedr_cm.h"
  55
  56 void qedr_inc_sw_gsi_cons(struct qedr_qp_hwq_info *info)
  57 {
  58         info->gsi_cons = (info->gsi_cons + 1) % info->max_wr;
  59 }
  60
  61 void qedr_store_gsi_qp_cq(struct qedr_dev *dev, struct qedr_qp *qp,
  62                           struct ib_qp_init_attr *attrs)
  63 {
  64         dev->gsi_qp_created = 1;
  65         dev->gsi_sqcq = get_qedr_cq(attrs->send_cq);
  66         dev->gsi_rqcq = get_qedr_cq(attrs->recv_cq);
  67         dev->gsi_qp = qp;
  68 }
  69
  70 void qedr_ll2_tx_cb(void *_qdev, struct qed_roce_ll2_packet *pkt)
  71 {
  72         struct qedr_dev *dev = (struct qedr_dev *)_qdev;
  73         struct qedr_cq *cq = dev->gsi_sqcq;
  74         struct qedr_qp *qp = dev->gsi_qp;
  75         unsigned long flags;
  76
  77         DP_DEBUG(dev, QEDR_MSG_GSI,
  78                  "LL2 TX CB: gsi_sqcq=%p, gsi_rqcq=%p, gsi_cons=%d, ibcq_comp=%s\n",
  79                  dev->gsi_sqcq, dev->gsi_rqcq, qp->sq.gsi_cons,
  80                  cq->ibcq.comp_handler ? "Yes" : "No");
  81
  82         dma_free_coherent(&dev->pdev->dev, pkt->header.len, pkt->header.vaddr,
  83                           pkt->header.baddr);
  84         kfree(pkt);
  85
  86         spin_lock_irqsave(&qp->q_lock, flags);
  87         qedr_inc_sw_gsi_cons(&qp->sq);
  88         spin_unlock_irqrestore(&qp->q_lock, flags);
  89
  90         if (cq->ibcq.comp_handler)
  91                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
  92 }
  93
  94 void qedr_ll2_rx_cb(void *_dev, struct qed_roce_ll2_packet *pkt,
  95                     struct qed_roce_ll2_rx_params *params)
  96 {
  97         struct qedr_dev *dev = (struct qedr_dev *)_dev;
  98         struct qedr_cq *cq = dev->gsi_rqcq;
  99         struct qedr_qp *qp = dev->gsi_qp;
 100         unsigned long flags;
 101
 102         spin_lock_irqsave(&qp->q_lock, flags);
 103
 104         qp->rqe_wr_id[qp->rq.gsi_cons].rc = params->rc;
 105         qp->rqe_wr_id[qp->rq.gsi_cons].vlan_id = params->vlan_id;
 106         qp->rqe_wr_id[qp->rq.gsi_cons].sg_list[0].length = pkt->payload[0].len;
 107         ether_addr_copy(qp->rqe_wr_id[qp->rq.gsi_cons].smac, params->smac);
 108
 109         qedr_inc_sw_gsi_cons(&qp->rq);
 110
 111         spin_unlock_irqrestore(&qp->q_lock, flags);
 112
 113         if (cq->ibcq.comp_handler)
 114                 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
 115 }
 116
 117 static void qedr_destroy_gsi_cq(struct qedr_dev *dev,
 118                                 struct ib_qp_init_attr *attrs)
 119 {
 120         struct qed_rdma_destroy_cq_in_params iparams;
 121         struct qed_rdma_destroy_cq_out_params oparams;
 122         struct qedr_cq *cq;
 123
 124         cq = get_qedr_cq(attrs->send_cq);
 125         iparams.icid = cq->icid;
 126         dev->ops->rdma_destroy_cq(dev->rdma_ctx, &iparams, &oparams);
 127         dev->ops->common->chain_free(dev->cdev, &cq->pbl);
 128
 129         cq = get_qedr_cq(attrs->recv_cq);
 130         /* if a dedicated recv_cq was used, delete it too */
 131         if (iparams.icid != cq->icid) {
 132                 iparams.icid = cq->icid;
 133                 dev->ops->rdma_destroy_cq(dev->rdma_ctx, &iparams, &oparams);
 134                 dev->ops->common->chain_free(dev->cdev, &cq->pbl);
 135         }
 136 }
 137
 138 static inline int qedr_check_gsi_qp_attrs(struct qedr_dev *dev,
 139                                           struct ib_qp_init_attr *attrs)
 140 {
 141         if (attrs->cap.max_recv_sge > QEDR_GSI_MAX_RECV_SGE) {
 142                 DP_ERR(dev,
 143                        " create gsi qp: failed. max_recv_sge is larger the max %d>%d\n",
 144                        attrs->cap.max_recv_sge, QEDR_GSI_MAX_RECV_SGE);
 145                 return -EINVAL;
 146         }
 147
 148         if (attrs->cap.max_recv_wr > QEDR_GSI_MAX_RECV_WR) {
 149                 DP_ERR(dev,
 150                        " create gsi qp: failed. max_recv_wr is too large %d>%d\n",
 151                        attrs->cap.max_recv_wr, QEDR_GSI_MAX_RECV_WR);
 152                 return -EINVAL;
 153         }
 154
 155         if (attrs->cap.max_send_wr > QEDR_GSI_MAX_SEND_WR) {
 156                 DP_ERR(dev,
 157                        " create gsi qp: failed. max_send_wr is too large %d>%d\n",
 158                        attrs->cap.max_send_wr, QEDR_GSI_MAX_SEND_WR);
 159                 return -EINVAL;
 160         }
 161
 162         return 0;
 163 }
 164
 165 struct ib_qp *qedr_create_gsi_qp(struct qedr_dev *dev,
 166                                  struct ib_qp_init_attr *attrs,
 167                                  struct qedr_qp *qp)
 168 {
 169         struct qed_roce_ll2_params ll2_params;
 170         int rc;
 171
 172         rc = qedr_check_gsi_qp_attrs(dev, attrs);
 173         if (rc)
 174                 return ERR_PTR(rc);
 175
 176         /* configure and start LL2 */
 177         memset(&ll2_params, 0, sizeof(ll2_params));
 178         ll2_params.max_tx_buffers = attrs->cap.max_send_wr;
 179         ll2_params.max_rx_buffers = attrs->cap.max_recv_wr;
 180         ll2_params.cbs.tx_cb = qedr_ll2_tx_cb;
 181         ll2_params.cbs.rx_cb = qedr_ll2_rx_cb;
 182         ll2_params.cb_cookie = (void *)dev;
 183         ll2_params.mtu = dev->ndev->mtu;
 184         ether_addr_copy(ll2_params.mac_address, dev->ndev->dev_addr);
 185         rc = dev->ops->roce_ll2_start(dev->cdev, &ll2_params);
 186         if (rc) {
 187                 DP_ERR(dev, "create gsi qp: failed on ll2 start. rc=%d\n", rc);
 188                 return ERR_PTR(rc);
 189         }
 190
 191         /* create QP */
 192         qp->ibqp.qp_num = 1;
 193         qp->rq.max_wr = attrs->cap.max_recv_wr;
 194         qp->sq.max_wr = attrs->cap.max_send_wr;
 195
 196         qp->rqe_wr_id = kcalloc(qp->rq.max_wr, sizeof(*qp->rqe_wr_id),
 197                                 GFP_KERNEL);
 198         if (!qp->rqe_wr_id)
 199                 goto err;
 200         qp->wqe_wr_id = kcalloc(qp->sq.max_wr, sizeof(*qp->wqe_wr_id),
 201                                 GFP_KERNEL);
 202         if (!qp->wqe_wr_id)
 203                 goto err;
 204
 205         qedr_store_gsi_qp_cq(dev, qp, attrs);
 206         ether_addr_copy(dev->gsi_ll2_mac_address, dev->ndev->dev_addr);
 207
 208         /* the GSI CQ is handled by the driver so remove it from the FW */
 209         qedr_destroy_gsi_cq(dev, attrs);
 210         dev->gsi_rqcq->cq_type = QEDR_CQ_TYPE_GSI;
 211         dev->gsi_rqcq->cq_type = QEDR_CQ_TYPE_GSI;
 212
 213         DP_DEBUG(dev, QEDR_MSG_GSI, "created GSI QP %p\n", qp);
 214
 215         return &qp->ibqp;
 216
 217 err:
 218         kfree(qp->rqe_wr_id);
 219
 220         rc = dev->ops->roce_ll2_stop(dev->cdev);
 221         if (rc)
 222                 DP_ERR(dev, "create gsi qp: failed destroy on create\n");
 223
 224         return ERR_PTR(-ENOMEM);
 225 }
 226
 227 int qedr_destroy_gsi_qp(struct qedr_dev *dev)
 228 {
 229         int rc;
 230
 231         rc = dev->ops->roce_ll2_stop(dev->cdev);
 232         if (rc)
 233                 DP_ERR(dev, "destroy gsi qp: failed (rc=%d)\n", rc);
 234         else
 235                 DP_DEBUG(dev, QEDR_MSG_GSI, "destroy gsi qp: success\n");
 236
 237         return rc;
 238 }
 239
 240 #define QEDR_MAX_UD_HEADER_SIZE (100)
 241 #define QEDR_GSI_QPN            (1)
 242 static inline int qedr_gsi_build_header(struct qedr_dev *dev,
 243                                         struct qedr_qp *qp,
 244                                         struct ib_send_wr *swr,
 245                                         struct ib_ud_header *udh,
 246                                         int *roce_mode)
 247 {
 248         bool has_vlan = false, has_grh_ipv6 = true;
 249         struct ib_ah_attr *ah_attr = &get_qedr_ah(ud_wr(swr)->ah)->attr;
 250         struct ib_global_route *grh = &ah_attr->grh;
 251         union ib_gid sgid;
 252         int send_size = 0;
 253         u16 vlan_id = 0;
 254         u16 ether_type;
 255         struct ib_gid_attr sgid_attr;
 256         int rc;
 257         int ip_ver = 0;
 258
 259         bool has_udp = false;
 260         int i;
 261
 262         send_size = 0;
 263         for (i = 0; i < swr->num_sge; ++i)
 264                 send_size += swr->sg_list[i].length;
 265
 266         rc = ib_get_cached_gid(qp->ibqp.device, ah_attr->port_num,
 267                                grh->sgid_index, &sgid, &sgid_attr);
 268         if (rc) {
 269                 DP_ERR(dev,
 270                        "gsi post send: failed to get cached GID (port=%d, ix=%d)\n",
 271                        ah_attr->port_num, grh->sgid_index);
 272                 return rc;
 273         }
 274
 275         vlan_id = rdma_vlan_dev_vlan_id(sgid_attr.ndev);
 276         if (vlan_id < VLAN_CFI_MASK)
 277                 has_vlan = true;
 278         if (sgid_attr.ndev)
 279                 dev_put(sgid_attr.ndev);
 280
 281         if (!memcmp(&sgid, &zgid, sizeof(sgid))) {
 282                 DP_ERR(dev, "gsi post send: GID not found GID index %d\n",
 283                        ah_attr->grh.sgid_index);
 284                 return -ENOENT;
 285         }
 286
 287         has_udp = (sgid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP);
 288         if (!has_udp) {
 289                 /* RoCE v1 */
 290                 ether_type = ETH_P_ROCE;
 291                 *roce_mode = ROCE_V1;
 292         } else if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) {
 293                 /* RoCE v2 IPv4 */
 294                 ip_ver = 4;
 295                 ether_type = ETH_P_IP;
 296                 has_grh_ipv6 = false;
 297                 *roce_mode = ROCE_V2_IPV4;
 298         } else {
 299                 /* RoCE v2 IPv6 */
 300                 ip_ver = 6;
 301                 ether_type = ETH_P_IPV6;
 302                 *roce_mode = ROCE_V2_IPV6;
 303         }
 304
 305         rc = ib_ud_header_init(send_size, false, true, has_vlan,
 306                                has_grh_ipv6, ip_ver, has_udp, 0, udh);
 307         if (rc) {
 308                 DP_ERR(dev, "gsi post send: failed to init header\n");
 309                 return rc;
 310         }
 311
 312         /* ENET + VLAN headers */
 313         ether_addr_copy(udh->eth.dmac_h, ah_attr->dmac);
 314         ether_addr_copy(udh->eth.smac_h, dev->ndev->dev_addr);
 315         if (has_vlan) {
 316                 udh->eth.type = htons(ETH_P_8021Q);
 317                 udh->vlan.tag = htons(vlan_id);
 318                 udh->vlan.type = htons(ether_type);
 319         } else {
 320                 udh->eth.type = htons(ether_type);
 321         }
 322
 323         /* BTH */
 324         udh->bth.solicited_event = !!(swr->send_flags & IB_SEND_SOLICITED);
 325         udh->bth.pkey = QEDR_ROCE_PKEY_DEFAULT;
 326         udh->bth.destination_qpn = htonl(ud_wr(swr)->remote_qpn);
 327         udh->bth.psn = htonl((qp->sq_psn++) & ((1 << 24) - 1));
 328         udh->bth.opcode = IB_OPCODE_UD_SEND_ONLY;
 329
 330         /* DETH */
 331         udh->deth.qkey = htonl(0x80010000);
 332         udh->deth.source_qpn = htonl(QEDR_GSI_QPN);
 333
 334         if (has_grh_ipv6) {
 335                 /* GRH / IPv6 header */
 336                 udh->grh.traffic_class = grh->traffic_class;
 337                 udh->grh.flow_label = grh->flow_label;
 338                 udh->grh.hop_limit = grh->hop_limit;
 339                 udh->grh.destination_gid = grh->dgid;
 340                 memcpy(&udh->grh.source_gid.raw, &sgid.raw,
 341                        sizeof(udh->grh.source_gid.raw));
 342         } else {
 343                 /* IPv4 header */
 344                 u32 ipv4_addr;
 345
 346                 udh->ip4.protocol = IPPROTO_UDP;
 347                 udh->ip4.tos = htonl(ah_attr->grh.flow_label);
 348                 udh->ip4.frag_off = htons(IP_DF);
 349                 udh->ip4.ttl = ah_attr->grh.hop_limit;
 350
 351                 ipv4_addr = qedr_get_ipv4_from_gid(sgid.raw);
 352                 udh->ip4.saddr = ipv4_addr;
 353                 ipv4_addr = qedr_get_ipv4_from_gid(ah_attr->grh.dgid.raw);
 354                 udh->ip4.daddr = ipv4_addr;
 355                 /* note: checksum is calculated by the device */
 356         }
 357
 358         /* UDP */
 359         if (has_udp) {
 360                 udh->udp.sport = htons(QEDR_ROCE_V2_UDP_SPORT);
 361                 udh->udp.dport = htons(ROCE_V2_UDP_DPORT);
 362                 udh->udp.csum = 0;
 363                 /* UDP length is untouched hence is zero */
 364         }
 365         return 0;
 366 }
 367
 368 static inline int qedr_gsi_build_packet(struct qedr_dev *dev,
 369                                         struct qedr_qp *qp,
 370                                         struct ib_send_wr *swr,
 371                                         struct qed_roce_ll2_packet **p_packet)
 372 {
 373         u8 ud_header_buffer[QEDR_MAX_UD_HEADER_SIZE];
 374         struct qed_roce_ll2_packet *packet;
 375         struct pci_dev *pdev = dev->pdev;
 376         int roce_mode, header_size;
 377         struct ib_ud_header udh;
 378         int i, rc;
 379
 380         *p_packet = NULL;
 381
 382         rc = qedr_gsi_build_header(dev, qp, swr, &udh, &roce_mode);
 383         if (rc)
 384                 return rc;
 385
 386         header_size = ib_ud_header_pack(&udh, &ud_header_buffer);
 387
 388         packet = kzalloc(sizeof(*packet), GFP_ATOMIC);
 389         if (!packet)
 390                 return -ENOMEM;
 391
 392         packet->header.vaddr = dma_alloc_coherent(&pdev->dev, header_size,
 393                                                   &packet->header.baddr,
 394                                                   GFP_ATOMIC);
 395         if (!packet->header.vaddr) {
 396                 kfree(packet);
 397                 return -ENOMEM;
 398         }
 399
 400         if (ether_addr_equal(udh.eth.smac_h, udh.eth.dmac_h))
 401                 packet->tx_dest = QED_ROCE_LL2_TX_DEST_LB;
 402         else
 403                 packet->tx_dest = QED_ROCE_LL2_TX_DEST_NW;
 404
 405         packet->roce_mode = roce_mode;
 406         memcpy(packet->header.vaddr, ud_header_buffer, header_size);
 407         packet->header.len = header_size;
 408         packet->n_seg = swr->num_sge;
 409         for (i = 0; i < packet->n_seg; i++) {
 410                 packet->payload[i].baddr = swr->sg_list[i].addr;
 411                 packet->payload[i].len = swr->sg_list[i].length;
 412         }
 413
 414         *p_packet = packet;
 415
 416         return 0;
 417 }
 418
 419 int qedr_gsi_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
 420                        struct ib_send_wr **bad_wr)
 421 {
 422         struct qed_roce_ll2_packet *pkt = NULL;
 423         struct qedr_qp *qp = get_qedr_qp(ibqp);
 424         struct qed_roce_ll2_tx_params params;
 425         struct qedr_dev *dev = qp->dev;
 426         unsigned long flags;
 427         int rc;
 428
 429         if (qp->state != QED_ROCE_QP_STATE_RTS) {
 430                 *bad_wr = wr;
 431                 DP_ERR(dev,
 432                        "gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTS\n",
 433                        qp->state);
 434                 return -EINVAL;
 435         }
 436
 437         if (wr->num_sge > RDMA_MAX_SGE_PER_SQ_WQE) {
 438                 DP_ERR(dev, "gsi post send: num_sge is too large (%d>%d)\n",
 439                        wr->num_sge, RDMA_MAX_SGE_PER_SQ_WQE);
 440                 rc = -EINVAL;
 441                 goto err;
 442         }
 443
 444         if (wr->opcode != IB_WR_SEND) {
 445                 DP_ERR(dev,
 446                        "gsi post send: failed due to unsupported opcode %d\n",
 447                        wr->opcode);
 448                 rc = -EINVAL;
 449                 goto err;
 450         }
 451
 452         memset(&params, 0, sizeof(params));
 453
 454         spin_lock_irqsave(&qp->q_lock, flags);
 455
 456         rc = qedr_gsi_build_packet(dev, qp, wr, &pkt);
 457         if (rc) {
 458                 spin_unlock_irqrestore(&qp->q_lock, flags);
 459                 goto err;
 460         }
 461
 462         rc = dev->ops->roce_ll2_tx(dev->cdev, pkt, &params);
 463         if (!rc) {
 464                 qp->wqe_wr_id[qp->sq.prod].wr_id = wr->wr_id;
 465                 qedr_inc_sw_prod(&qp->sq);
 466                 DP_DEBUG(qp->dev, QEDR_MSG_GSI,
 467                          "gsi post send: opcode=%d, in_irq=%ld, irqs_disabled=%d, wr_id=%llx\n",
 468                          wr->opcode, in_irq(), irqs_disabled(), wr->wr_id);
 469         } else {
 470                 if (rc == QED_ROCE_TX_HEAD_FAILURE) {
 471                         /* TX failed while posting header - release resources */
 472                         dma_free_coherent(&dev->pdev->dev, pkt->header.len,
 473                                           pkt->header.vaddr, pkt->header.baddr);
 474                         kfree(pkt);
 475                 } else if (rc == QED_ROCE_TX_FRAG_FAILURE) {
 476                         /* NTD since TX failed while posting a fragment. We will
 477                          * release the resources on TX callback
 478                          */
 479                 }
 480
 481                 DP_ERR(dev, "gsi post send: failed to transmit (rc=%d)\n", rc);
 482                 rc = -EAGAIN;
 483                 *bad_wr = wr;
 484         }
 485
 486         spin_unlock_irqrestore(&qp->q_lock, flags);
 487
 488         if (wr->next) {
 489                 DP_ERR(dev,
 490                        "gsi post send: failed second WR. Only one WR may be passed at a time\n");
 491                 *bad_wr = wr->next;
 492                 rc = -EINVAL;
 493         }
 494
 495         return rc;
 496
 497 err:
 498         *bad_wr = wr;
 499         return rc;
 500 }
 501
 502 int qedr_gsi_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
 503                        struct ib_recv_wr **bad_wr)
 504 {
 505         struct qedr_dev *dev = get_qedr_dev(ibqp->device);
 506         struct qedr_qp *qp = get_qedr_qp(ibqp);
 507         struct qed_roce_ll2_buffer buf;
 508         unsigned long flags;
 509         int status = 0;
 510         int rc;
 511
 512         if ((qp->state != QED_ROCE_QP_STATE_RTR) &&
 513             (qp->state != QED_ROCE_QP_STATE_RTS)) {
 514                 *bad_wr = wr;
 515                 DP_ERR(dev,
 516                        "gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTR/S\n",
 517                        qp->state);
 518                 return -EINVAL;
 519         }
 520
 521         memset(&buf, 0, sizeof(buf));
 522
 523         spin_lock_irqsave(&qp->q_lock, flags);
 524
 525         while (wr) {
 526                 if (wr->num_sge > QEDR_GSI_MAX_RECV_SGE) {
 527                         DP_ERR(dev,
 528                                "gsi post recv: failed to post rx buffer. too many sges %d>%d\n",
 529                                wr->num_sge, QEDR_GSI_MAX_RECV_SGE);
 530                         goto err;
 531                 }
 532
 533                 buf.baddr = wr->sg_list[0].addr;
 534                 buf.len = wr->sg_list[0].length;
 535
 536                 rc = dev->ops->roce_ll2_post_rx_buffer(dev->cdev, &buf, 0, 1);
 537                 if (rc) {
 538                         DP_ERR(dev,
 539                                "gsi post recv: failed to post rx buffer (rc=%d)\n",
 540                                rc);
 541                         goto err;
 542                 }
 543
 544                 memset(&qp->rqe_wr_id[qp->rq.prod], 0,
 545                        sizeof(qp->rqe_wr_id[qp->rq.prod]));
 546                 qp->rqe_wr_id[qp->rq.prod].sg_list[0] = wr->sg_list[0];
 547                 qp->rqe_wr_id[qp->rq.prod].wr_id = wr->wr_id;
 548
 549                 qedr_inc_sw_prod(&qp->rq);
 550
 551                 wr = wr->next;
 552         }
 553
 554         spin_unlock_irqrestore(&qp->q_lock, flags);
 555
 556         return status;
 557 err:
 558         spin_unlock_irqrestore(&qp->q_lock, flags);
 559         *bad_wr = wr;
 560         return -ENOMEM;
 561 }
 562
 563 int qedr_gsi_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
 564 {
 565         struct qedr_dev *dev = get_qedr_dev(ibcq->device);
 566         struct qedr_cq *cq = get_qedr_cq(ibcq);
 567         struct qedr_qp *qp = dev->gsi_qp;
 568         unsigned long flags;
 569         int i = 0;
 570
 571         spin_lock_irqsave(&cq->cq_lock, flags);
 572
 573         while (i < num_entries && qp->rq.cons != qp->rq.gsi_cons) {
 574                 memset(&wc[i], 0, sizeof(*wc));
 575
 576                 wc[i].qp = &qp->ibqp;
 577                 wc[i].wr_id = qp->rqe_wr_id[qp->rq.cons].wr_id;
 578                 wc[i].opcode = IB_WC_RECV;
 579                 wc[i].pkey_index = 0;
 580                 wc[i].status = (qp->rqe_wr_id[qp->rq.cons].rc) ?
 581                     IB_WC_GENERAL_ERR : IB_WC_SUCCESS;
 582                 /* 0 - currently only one recv sg is supported */
 583                 wc[i].byte_len = qp->rqe_wr_id[qp->rq.cons].sg_list[0].length;
 584                 wc[i].wc_flags |= IB_WC_GRH | IB_WC_IP_CSUM_OK;
 585                 ether_addr_copy(wc[i].smac, qp->rqe_wr_id[qp->rq.cons].smac);
 586                 wc[i].wc_flags |= IB_WC_WITH_SMAC;
 587                 if (qp->rqe_wr_id[qp->rq.cons].vlan_id) {
 588                         wc[i].wc_flags |= IB_WC_WITH_VLAN;
 589                         wc[i].vlan_id = qp->rqe_wr_id[qp->rq.cons].vlan_id;
 590                 }
 591
 592                 qedr_inc_sw_cons(&qp->rq);
 593                 i++;
 594         }
 595
 596         while (i < num_entries && qp->sq.cons != qp->sq.gsi_cons) {
 597                 memset(&wc[i], 0, sizeof(*wc));
 598
 599                 wc[i].qp = &qp->ibqp;
 600                 wc[i].wr_id = qp->wqe_wr_id[qp->sq.cons].wr_id;
 601                 wc[i].opcode = IB_WC_SEND;
 602                 wc[i].status = IB_WC_SUCCESS;
 603
 604                 qedr_inc_sw_cons(&qp->sq);
 605                 i++;
 606         }
 607
 608         spin_unlock_irqrestore(&cq->cq_lock, flags);
 609
 610         DP_DEBUG(dev, QEDR_MSG_GSI,
 611                  "gsi poll_cq: requested entries=%d, actual=%d, qp->rq.cons=%d, qp->rq.gsi_cons=%x, qp->sq.cons=%d, qp->sq.gsi_cons=%d, qp_num=%d\n",
 612                  num_entries, i, qp->rq.cons, qp->rq.gsi_cons, qp->sq.cons,
 613                  qp->sq.gsi_cons, qp->ibqp.qp_num);
 614
 615         return i;
 616 }