drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/slot-gpio.h>
  32
  33 #include "sdhci.h"
  34
  35 #define DRIVER_NAME "sdhci"
  36
  37 #define DBG(f, x...) \
  38         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  39
  40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  41         defined(CONFIG_MMC_SDHCI_MODULE))
  42 #define SDHCI_USE_LEDS_CLASS
  43 #endif
  44
  45 #define MAX_TUNING_LOOP 40
  46
  47 static unsigned int debug_quirks = 0;
  48 static unsigned int debug_quirks2;
  49
  50 static void sdhci_finish_data(struct sdhci_host *);
  51
  52 static void sdhci_finish_command(struct sdhci_host *);
  53 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  54 static void sdhci_tuning_timer(unsigned long data);
  55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  56
  57 #ifdef CONFIG_PM_RUNTIME
  58 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  59 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  60 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  61 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  62 #else
  63 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  64 {
  65         return 0;
  66 }
  67 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  68 {
  69         return 0;
  70 }
  71 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  72 {
  73 }
  74 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  75 {
  76 }
  77 #endif
  78
  79 static void sdhci_dumpregs(struct sdhci_host *host)
  80 {
  81         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  82                 mmc_hostname(host->mmc));
  83
  84         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  85                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  86                 sdhci_readw(host, SDHCI_HOST_VERSION));
  87         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  88                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  89                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  90         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  91                 sdhci_readl(host, SDHCI_ARGUMENT),
  92                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  93         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  94                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  95                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  96         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  97                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  98                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  99         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 100                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 101                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 102         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 103                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 104                 sdhci_readl(host, SDHCI_INT_STATUS));
 105         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 106                 sdhci_readl(host, SDHCI_INT_ENABLE),
 107                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 108         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 109                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 110                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 111         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 112                 sdhci_readl(host, SDHCI_CAPABILITIES),
 113                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 114         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 115                 sdhci_readw(host, SDHCI_COMMAND),
 116                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 117         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 118                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 119
 120         if (host->flags & SDHCI_USE_ADMA)
 121                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 122                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
 123                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 124
 125         pr_debug(DRIVER_NAME ": ===========================================\n");
 126 }
 127
 128 /*****************************************************************************\
 129  *                                                                           *
 130  * Low level functions                                                       *
 131  *                                                                           *
 132 \*****************************************************************************/
 133
 134 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 135 {
 136         u32 ier;
 137
 138         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 139         ier &= ~clear;
 140         ier |= set;
 141         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 142         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 143 }
 144
 145 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 146 {
 147         sdhci_clear_set_irqs(host, 0, irqs);
 148 }
 149
 150 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 151 {
 152         sdhci_clear_set_irqs(host, irqs, 0);
 153 }
 154
 155 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 156 {
 157         u32 present, irqs;
 158
 159         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 160             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 161                 return;
 162
 163         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 164                               SDHCI_CARD_PRESENT;
 165         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
 166
 167         if (enable)
 168                 sdhci_unmask_irqs(host, irqs);
 169         else
 170                 sdhci_mask_irqs(host, irqs);
 171 }
 172
 173 static void sdhci_enable_card_detection(struct sdhci_host *host)
 174 {
 175         sdhci_set_card_detection(host, true);
 176 }
 177
 178 static void sdhci_disable_card_detection(struct sdhci_host *host)
 179 {
 180         sdhci_set_card_detection(host, false);
 181 }
 182
 183 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 184 {
 185         unsigned long timeout;
 186         u32 uninitialized_var(ier);
 187
 188         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 189                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 190                         SDHCI_CARD_PRESENT))
 191                         return;
 192         }
 193
 194         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 195                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 196
 197         if (host->ops->platform_reset_enter)
 198                 host->ops->platform_reset_enter(host, mask);
 199
 200         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 201
 202         if (mask & SDHCI_RESET_ALL) {
 203                 host->clock = 0;
 204                 /* Reset-all turns off SD Bus Power */
 205                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 206                         sdhci_runtime_pm_bus_off(host);
 207         }
 208
 209         /* Wait max 100 ms */
 210         timeout = 100;
 211
 212         /* hw clears the bit when it's done */
 213         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 214                 if (timeout == 0) {
 215                         pr_err("%s: Reset 0x%x never completed.\n",
 216                                 mmc_hostname(host->mmc), (int)mask);
 217                         sdhci_dumpregs(host);
 218                         return;
 219                 }
 220                 timeout--;
 221                 mdelay(1);
 222         }
 223
 224         if (host->ops->platform_reset_exit)
 225                 host->ops->platform_reset_exit(host, mask);
 226
 227         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 228                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 229
 230         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 231                 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
 232                         host->ops->enable_dma(host);
 233         }
 234 }
 235
 236 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 237
 238 static void sdhci_init(struct sdhci_host *host, int soft)
 239 {
 240         if (soft)
 241                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 242         else
 243                 sdhci_reset(host, SDHCI_RESET_ALL);
 244
 245         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 246                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 247                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 248                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 249                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 250
 251         if (soft) {
 252                 /* force clock reconfiguration */
 253                 host->clock = 0;
 254                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 255         }
 256 }
 257
 258 static void sdhci_reinit(struct sdhci_host *host)
 259 {
 260         sdhci_init(host, 0);
 261         /*
 262          * Retuning stuffs are affected by different cards inserted and only
 263          * applicable to UHS-I cards. So reset these fields to their initial
 264          * value when card is removed.
 265          */
 266         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
 267                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
 268
 269                 del_timer_sync(&host->tuning_timer);
 270                 host->flags &= ~SDHCI_NEEDS_RETUNING;
 271                 host->mmc->max_blk_count =
 272                         (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
 273         }
 274         sdhci_enable_card_detection(host);
 275 }
 276
 277 static void sdhci_activate_led(struct sdhci_host *host)
 278 {
 279         u8 ctrl;
 280
 281         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 282         ctrl |= SDHCI_CTRL_LED;
 283         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 284 }
 285
 286 static void sdhci_deactivate_led(struct sdhci_host *host)
 287 {
 288         u8 ctrl;
 289
 290         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 291         ctrl &= ~SDHCI_CTRL_LED;
 292         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 293 }
 294
 295 #ifdef SDHCI_USE_LEDS_CLASS
 296 static void sdhci_led_control(struct led_classdev *led,
 297         enum led_brightness brightness)
 298 {
 299         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 300         unsigned long flags;
 301
 302         spin_lock_irqsave(&host->lock, flags);
 303
 304         if (host->runtime_suspended)
 305                 goto out;
 306
 307         if (brightness == LED_OFF)
 308                 sdhci_deactivate_led(host);
 309         else
 310                 sdhci_activate_led(host);
 311 out:
 312         spin_unlock_irqrestore(&host->lock, flags);
 313 }
 314 #endif
 315
 316 /*****************************************************************************\
 317  *                                                                           *
 318  * Core functions                                                            *
 319  *                                                                           *
 320 \*****************************************************************************/
 321
 322 static void sdhci_read_block_pio(struct sdhci_host *host)
 323 {
 324         unsigned long flags;
 325         size_t blksize, len, chunk;
 326         u32 uninitialized_var(scratch);
 327         u8 *buf;
 328
 329         DBG("PIO reading\n");
 330
 331         blksize = host->data->blksz;
 332         chunk = 0;
 333
 334         local_irq_save(flags);
 335
 336         while (blksize) {
 337                 if (!sg_miter_next(&host->sg_miter))
 338                         BUG();
 339
 340                 len = min(host->sg_miter.length, blksize);
 341
 342                 blksize -= len;
 343                 host->sg_miter.consumed = len;
 344
 345                 buf = host->sg_miter.addr;
 346
 347                 while (len) {
 348                         if (chunk == 0) {
 349                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 350                                 chunk = 4;
 351                         }
 352
 353                         *buf = scratch & 0xFF;
 354
 355                         buf++;
 356                         scratch >>= 8;
 357                         chunk--;
 358                         len--;
 359                 }
 360         }
 361
 362         sg_miter_stop(&host->sg_miter);
 363
 364         local_irq_restore(flags);
 365 }
 366
 367 static void sdhci_write_block_pio(struct sdhci_host *host)
 368 {
 369         unsigned long flags;
 370         size_t blksize, len, chunk;
 371         u32 scratch;
 372         u8 *buf;
 373
 374         DBG("PIO writing\n");
 375
 376         blksize = host->data->blksz;
 377         chunk = 0;
 378         scratch = 0;
 379
 380         local_irq_save(flags);
 381
 382         while (blksize) {
 383                 if (!sg_miter_next(&host->sg_miter))
 384                         BUG();
 385
 386                 len = min(host->sg_miter.length, blksize);
 387
 388                 blksize -= len;
 389                 host->sg_miter.consumed = len;
 390
 391                 buf = host->sg_miter.addr;
 392
 393                 while (len) {
 394                         scratch |= (u32)*buf << (chunk * 8);
 395
 396                         buf++;
 397                         chunk++;
 398                         len--;
 399
 400                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 401                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 402                                 chunk = 0;
 403                                 scratch = 0;
 404                         }
 405                 }
 406         }
 407
 408         sg_miter_stop(&host->sg_miter);
 409
 410         local_irq_restore(flags);
 411 }
 412
 413 static void sdhci_transfer_pio(struct sdhci_host *host)
 414 {
 415         u32 mask;
 416
 417         BUG_ON(!host->data);
 418
 419         if (host->blocks == 0)
 420                 return;
 421
 422         if (host->data->flags & MMC_DATA_READ)
 423                 mask = SDHCI_DATA_AVAILABLE;
 424         else
 425                 mask = SDHCI_SPACE_AVAILABLE;
 426
 427         /*
 428          * Some controllers (JMicron JMB38x) mess up the buffer bits
 429          * for transfers < 4 bytes. As long as it is just one block,
 430          * we can ignore the bits.
 431          */
 432         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 433                 (host->data->blocks == 1))
 434                 mask = ~0;
 435
 436         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 437                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 438                         udelay(100);
 439
 440                 if (host->data->flags & MMC_DATA_READ)
 441                         sdhci_read_block_pio(host);
 442                 else
 443                         sdhci_write_block_pio(host);
 444
 445                 host->blocks--;
 446                 if (host->blocks == 0)
 447                         break;
 448         }
 449
 450         DBG("PIO transfer complete.\n");
 451 }
 452
 453 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 454 {
 455         local_irq_save(*flags);
 456         return kmap_atomic(sg_page(sg)) + sg->offset;
 457 }
 458
 459 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 460 {
 461         kunmap_atomic(buffer);
 462         local_irq_restore(*flags);
 463 }
 464
 465 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 466 {
 467         __le32 *dataddr = (__le32 __force *)(desc + 4);
 468         __le16 *cmdlen = (__le16 __force *)desc;
 469
 470         /* SDHCI specification says ADMA descriptors should be 4 byte
 471          * aligned, so using 16 or 32bit operations should be safe. */
 472
 473         cmdlen[0] = cpu_to_le16(cmd);
 474         cmdlen[1] = cpu_to_le16(len);
 475
 476         dataddr[0] = cpu_to_le32(addr);
 477 }
 478
 479 static int sdhci_adma_table_pre(struct sdhci_host *host,
 480         struct mmc_data *data)
 481 {
 482         int direction;
 483
 484         u8 *desc;
 485         u8 *align;
 486         dma_addr_t addr;
 487         dma_addr_t align_addr;
 488         int len, offset;
 489
 490         struct scatterlist *sg;
 491         int i;
 492         char *buffer;
 493         unsigned long flags;
 494
 495         /*
 496          * The spec does not specify endianness of descriptor table.
 497          * We currently guess that it is LE.
 498          */
 499
 500         if (data->flags & MMC_DATA_READ)
 501                 direction = DMA_FROM_DEVICE;
 502         else
 503                 direction = DMA_TO_DEVICE;
 504
 505         /*
 506          * The ADMA descriptor table is mapped further down as we
 507          * need to fill it with data first.
 508          */
 509
 510         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 511                 host->align_buffer, 128 * 4, direction);
 512         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 513                 goto fail;
 514         BUG_ON(host->align_addr & 0x3);
 515
 516         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 517                 data->sg, data->sg_len, direction);
 518         if (host->sg_count == 0)
 519                 goto unmap_align;
 520
 521         desc = host->adma_desc;
 522         align = host->align_buffer;
 523
 524         align_addr = host->align_addr;
 525
 526         for_each_sg(data->sg, sg, host->sg_count, i) {
 527                 addr = sg_dma_address(sg);
 528                 len = sg_dma_len(sg);
 529
 530                 /*
 531                  * The SDHCI specification states that ADMA
 532                  * addresses must be 32-bit aligned. If they
 533                  * aren't, then we use a bounce buffer for
 534                  * the (up to three) bytes that screw up the
 535                  * alignment.
 536                  */
 537                 offset = (4 - (addr & 0x3)) & 0x3;
 538                 if (offset) {
 539                         if (data->flags & MMC_DATA_WRITE) {
 540                                 buffer = sdhci_kmap_atomic(sg, &flags);
 541                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 542                                 memcpy(align, buffer, offset);
 543                                 sdhci_kunmap_atomic(buffer, &flags);
 544                         }
 545
 546                         /* tran, valid */
 547                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 548
 549                         BUG_ON(offset > 65536);
 550
 551                         align += 4;
 552                         align_addr += 4;
 553
 554                         desc += 8;
 555
 556                         addr += offset;
 557                         len -= offset;
 558                 }
 559
 560                 BUG_ON(len > 65536);
 561
 562                 /* tran, valid */
 563                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 564                 desc += 8;
 565
 566                 /*
 567                  * If this triggers then we have a calculation bug
 568                  * somewhere. :/
 569                  */
 570                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 571         }
 572
 573         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 574                 /*
 575                 * Mark the last descriptor as the terminating descriptor
 576                 */
 577                 if (desc != host->adma_desc) {
 578                         desc -= 8;
 579                         desc[0] |= 0x2; /* end */
 580                 }
 581         } else {
 582                 /*
 583                 * Add a terminating entry.
 584                 */
 585
 586                 /* nop, end, valid */
 587                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 588         }
 589
 590         /*
 591          * Resync align buffer as we might have changed it.
 592          */
 593         if (data->flags & MMC_DATA_WRITE) {
 594                 dma_sync_single_for_device(mmc_dev(host->mmc),
 595                         host->align_addr, 128 * 4, direction);
 596         }
 597
 598         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 599                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 600         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 601                 goto unmap_entries;
 602         BUG_ON(host->adma_addr & 0x3);
 603
 604         return 0;
 605
 606 unmap_entries:
 607         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 608                 data->sg_len, direction);
 609 unmap_align:
 610         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 611                 128 * 4, direction);
 612 fail:
 613         return -EINVAL;
 614 }
 615
 616 static void sdhci_adma_table_post(struct sdhci_host *host,
 617         struct mmc_data *data)
 618 {
 619         int direction;
 620
 621         struct scatterlist *sg;
 622         int i, size;
 623         u8 *align;
 624         char *buffer;
 625         unsigned long flags;
 626
 627         if (data->flags & MMC_DATA_READ)
 628                 direction = DMA_FROM_DEVICE;
 629         else
 630                 direction = DMA_TO_DEVICE;
 631
 632         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 633                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 634
 635         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 636                 128 * 4, direction);
 637
 638         if (data->flags & MMC_DATA_READ) {
 639                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 640                         data->sg_len, direction);
 641
 642                 align = host->align_buffer;
 643
 644                 for_each_sg(data->sg, sg, host->sg_count, i) {
 645                         if (sg_dma_address(sg) & 0x3) {
 646                                 size = 4 - (sg_dma_address(sg) & 0x3);
 647
 648                                 buffer = sdhci_kmap_atomic(sg, &flags);
 649                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 650                                 memcpy(buffer, align, size);
 651                                 sdhci_kunmap_atomic(buffer, &flags);
 652
 653                                 align += 4;
 654                         }
 655                 }
 656         }
 657
 658         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 659                 data->sg_len, direction);
 660 }
 661
 662 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 663 {
 664         u8 count;
 665         struct mmc_data *data = cmd->data;
 666         unsigned target_timeout, current_timeout;
 667
 668         /*
 669          * If the host controller provides us with an incorrect timeout
 670          * value, just skip the check and use 0xE.  The hardware may take
 671          * longer to time out, but that's much better than having a too-short
 672          * timeout value.
 673          */
 674         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 675                 return 0xE;
 676
 677         /* Unspecified timeout, assume max */
 678         if (!data && !cmd->busy_timeout)
 679                 return 0xE;
 680
 681         /* timeout in us */
 682         if (!data)
 683                 target_timeout = cmd->busy_timeout * 1000;
 684         else {
 685                 target_timeout = data->timeout_ns / 1000;
 686                 if (host->clock)
 687                         target_timeout += data->timeout_clks / host->clock;
 688         }
 689
 690         /*
 691          * Figure out needed cycles.
 692          * We do this in steps in order to fit inside a 32 bit int.
 693          * The first step is the minimum timeout, which will have a
 694          * minimum resolution of 6 bits:
 695          * (1) 2^13*1000 > 2^22,
 696          * (2) host->timeout_clk < 2^16
 697          *     =>
 698          *     (1) / (2) > 2^6
 699          */
 700         count = 0;
 701         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 702         while (current_timeout < target_timeout) {
 703                 count++;
 704                 current_timeout <<= 1;
 705                 if (count >= 0xF)
 706                         break;
 707         }
 708
 709         if (count >= 0xF) {
 710                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 711                     mmc_hostname(host->mmc), count, cmd->opcode);
 712                 count = 0xE;
 713         }
 714
 715         return count;
 716 }
 717
 718 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 719 {
 720         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 721         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 722
 723         if (host->flags & SDHCI_REQ_USE_DMA)
 724                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 725         else
 726                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 727 }
 728
 729 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 730 {
 731         u8 count;
 732         u8 ctrl;
 733         struct mmc_data *data = cmd->data;
 734         int ret;
 735
 736         WARN_ON(host->data);
 737
 738         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 739                 count = sdhci_calc_timeout(host, cmd);
 740                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 741         }
 742
 743         if (!data)
 744                 return;
 745
 746         /* Sanity checks */
 747         BUG_ON(data->blksz * data->blocks > 524288);
 748         BUG_ON(data->blksz > host->mmc->max_blk_size);
 749         BUG_ON(data->blocks > 65535);
 750
 751         host->data = data;
 752         host->data_early = 0;
 753         host->data->bytes_xfered = 0;
 754
 755         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 756                 host->flags |= SDHCI_REQ_USE_DMA;
 757
 758         /*
 759          * FIXME: This doesn't account for merging when mapping the
 760          * scatterlist.
 761          */
 762         if (host->flags & SDHCI_REQ_USE_DMA) {
 763                 int broken, i;
 764                 struct scatterlist *sg;
 765
 766                 broken = 0;
 767                 if (host->flags & SDHCI_USE_ADMA) {
 768                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 769                                 broken = 1;
 770                 } else {
 771                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 772                                 broken = 1;
 773                 }
 774
 775                 if (unlikely(broken)) {
 776                         for_each_sg(data->sg, sg, data->sg_len, i) {
 777                                 if (sg->length & 0x3) {
 778                                         DBG("Reverting to PIO because of "
 779                                                 "transfer size (%d)\n",
 780                                                 sg->length);
 781                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 782                                         break;
 783                                 }
 784                         }
 785                 }
 786         }
 787
 788         /*
 789          * The assumption here being that alignment is the same after
 790          * translation to device address space.
 791          */
 792         if (host->flags & SDHCI_REQ_USE_DMA) {
 793                 int broken, i;
 794                 struct scatterlist *sg;
 795
 796                 broken = 0;
 797                 if (host->flags & SDHCI_USE_ADMA) {
 798                         /*
 799                          * As we use 3 byte chunks to work around
 800                          * alignment problems, we need to check this
 801                          * quirk.
 802                          */
 803                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 804                                 broken = 1;
 805                 } else {
 806                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 807                                 broken = 1;
 808                 }
 809
 810                 if (unlikely(broken)) {
 811                         for_each_sg(data->sg, sg, data->sg_len, i) {
 812                                 if (sg->offset & 0x3) {
 813                                         DBG("Reverting to PIO because of "
 814                                                 "bad alignment\n");
 815                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 816                                         break;
 817                                 }
 818                         }
 819                 }
 820         }
 821
 822         if (host->flags & SDHCI_REQ_USE_DMA) {
 823                 if (host->flags & SDHCI_USE_ADMA) {
 824                         ret = sdhci_adma_table_pre(host, data);
 825                         if (ret) {
 826                                 /*
 827                                  * This only happens when someone fed
 828                                  * us an invalid request.
 829                                  */
 830                                 WARN_ON(1);
 831                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 832                         } else {
 833                                 sdhci_writel(host, host->adma_addr,
 834                                         SDHCI_ADMA_ADDRESS);
 835                         }
 836                 } else {
 837                         int sg_cnt;
 838
 839                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 840                                         data->sg, data->sg_len,
 841                                         (data->flags & MMC_DATA_READ) ?
 842                                                 DMA_FROM_DEVICE :
 843                                                 DMA_TO_DEVICE);
 844                         if (sg_cnt == 0) {
 845                                 /*
 846                                  * This only happens when someone fed
 847                                  * us an invalid request.
 848                                  */
 849                                 WARN_ON(1);
 850                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 851                         } else {
 852                                 WARN_ON(sg_cnt != 1);
 853                                 sdhci_writel(host, sg_dma_address(data->sg),
 854                                         SDHCI_DMA_ADDRESS);
 855                         }
 856                 }
 857         }
 858
 859         /*
 860          * Always adjust the DMA selection as some controllers
 861          * (e.g. JMicron) can't do PIO properly when the selection
 862          * is ADMA.
 863          */
 864         if (host->version >= SDHCI_SPEC_200) {
 865                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 866                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 867                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 868                         (host->flags & SDHCI_USE_ADMA))
 869                         ctrl |= SDHCI_CTRL_ADMA32;
 870                 else
 871                         ctrl |= SDHCI_CTRL_SDMA;
 872                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 873         }
 874
 875         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 876                 int flags;
 877
 878                 flags = SG_MITER_ATOMIC;
 879                 if (host->data->flags & MMC_DATA_READ)
 880                         flags |= SG_MITER_TO_SG;
 881                 else
 882                         flags |= SG_MITER_FROM_SG;
 883                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 884                 host->blocks = data->blocks;
 885         }
 886
 887         sdhci_set_transfer_irqs(host);
 888
 889         /* Set the DMA boundary value and block size */
 890         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 891                 data->blksz), SDHCI_BLOCK_SIZE);
 892         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 893 }
 894
 895 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 896         struct mmc_command *cmd)
 897 {
 898         u16 mode;
 899         struct mmc_data *data = cmd->data;
 900
 901         if (data == NULL) {
 902                 /* clear Auto CMD settings for no data CMDs */
 903                 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 904                 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 905                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 906                 return;
 907         }
 908
 909         WARN_ON(!host->data);
 910
 911         mode = SDHCI_TRNS_BLK_CNT_EN;
 912         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 913                 mode |= SDHCI_TRNS_MULTI;
 914                 /*
 915                  * If we are sending CMD23, CMD12 never gets sent
 916                  * on successful completion (so no Auto-CMD12).
 917                  */
 918                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 919                         mode |= SDHCI_TRNS_AUTO_CMD12;
 920                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 921                         mode |= SDHCI_TRNS_AUTO_CMD23;
 922                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 923                 }
 924         }
 925
 926         if (data->flags & MMC_DATA_READ)
 927                 mode |= SDHCI_TRNS_READ;
 928         if (host->flags & SDHCI_REQ_USE_DMA)
 929                 mode |= SDHCI_TRNS_DMA;
 930
 931         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 932 }
 933
 934 static void sdhci_finish_data(struct sdhci_host *host)
 935 {
 936         struct mmc_data *data;
 937
 938         BUG_ON(!host->data);
 939
 940         data = host->data;
 941         host->data = NULL;
 942
 943         if (host->flags & SDHCI_REQ_USE_DMA) {
 944                 if (host->flags & SDHCI_USE_ADMA)
 945                         sdhci_adma_table_post(host, data);
 946                 else {
 947                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 948                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 949                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 950                 }
 951         }
 952
 953         /*
 954          * The specification states that the block count register must
 955          * be updated, but it does not specify at what point in the
 956          * data flow. That makes the register entirely useless to read
 957          * back so we have to assume that nothing made it to the card
 958          * in the event of an error.
 959          */
 960         if (data->error)
 961                 data->bytes_xfered = 0;
 962         else
 963                 data->bytes_xfered = data->blksz * data->blocks;
 964
 965         /*
 966          * Need to send CMD12 if -
 967          * a) open-ended multiblock transfer (no CMD23)
 968          * b) error in multiblock transfer
 969          */
 970         if (data->stop &&
 971             (data->error ||
 972              !host->mrq->sbc)) {
 973
 974                 /*
 975                  * The controller needs a reset of internal state machines
 976                  * upon error conditions.
 977                  */
 978                 if (data->error) {
 979                         sdhci_reset(host, SDHCI_RESET_CMD);
 980                         sdhci_reset(host, SDHCI_RESET_DATA);
 981                 }
 982
 983                 sdhci_send_command(host, data->stop);
 984         } else
 985                 tasklet_schedule(&host->finish_tasklet);
 986 }
 987
 988 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 989 {
 990         int flags;
 991         u32 mask;
 992         unsigned long timeout;
 993
 994         WARN_ON(host->cmd);
 995
 996         /* Wait max 10 ms */
 997         timeout = 10;
 998
 999         mask = SDHCI_CMD_INHIBIT;
1000         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1001                 mask |= SDHCI_DATA_INHIBIT;
1002
1003         /* We shouldn't wait for data inihibit for stop commands, even
1004            though they might use busy signaling */
1005         if (host->mrq->data && (cmd == host->mrq->data->stop))
1006                 mask &= ~SDHCI_DATA_INHIBIT;
1007
1008         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1009                 if (timeout == 0) {
1010                         pr_err("%s: Controller never released "
1011                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1012                         sdhci_dumpregs(host);
1013                         cmd->error = -EIO;
1014                         tasklet_schedule(&host->finish_tasklet);
1015                         return;
1016                 }
1017                 timeout--;
1018                 mdelay(1);
1019         }
1020
1021         timeout = jiffies;
1022         if (!cmd->data && cmd->busy_timeout > 9000)
1023                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1024         else
1025                 timeout += 10 * HZ;
1026         mod_timer(&host->timer, timeout);
1027
1028         host->cmd = cmd;
1029
1030         sdhci_prepare_data(host, cmd);
1031
1032         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1033
1034         sdhci_set_transfer_mode(host, cmd);
1035
1036         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1037                 pr_err("%s: Unsupported response type!\n",
1038                         mmc_hostname(host->mmc));
1039                 cmd->error = -EINVAL;
1040                 tasklet_schedule(&host->finish_tasklet);
1041                 return;
1042         }
1043
1044         if (!(cmd->flags & MMC_RSP_PRESENT))
1045                 flags = SDHCI_CMD_RESP_NONE;
1046         else if (cmd->flags & MMC_RSP_136)
1047                 flags = SDHCI_CMD_RESP_LONG;
1048         else if (cmd->flags & MMC_RSP_BUSY)
1049                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1050         else
1051                 flags = SDHCI_CMD_RESP_SHORT;
1052
1053         if (cmd->flags & MMC_RSP_CRC)
1054                 flags |= SDHCI_CMD_CRC;
1055         if (cmd->flags & MMC_RSP_OPCODE)
1056                 flags |= SDHCI_CMD_INDEX;
1057
1058         /* CMD19 is special in that the Data Present Select should be set */
1059         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1060             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1061                 flags |= SDHCI_CMD_DATA;
1062
1063         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1064 }
1065 EXPORT_SYMBOL_GPL(sdhci_send_command);
1066
1067 static void sdhci_finish_command(struct sdhci_host *host)
1068 {
1069         int i;
1070
1071         BUG_ON(host->cmd == NULL);
1072
1073         if (host->cmd->flags & MMC_RSP_PRESENT) {
1074                 if (host->cmd->flags & MMC_RSP_136) {
1075                         /* CRC is stripped so we need to do some shifting. */
1076                         for (i = 0;i < 4;i++) {
1077                                 host->cmd->resp[i] = sdhci_readl(host,
1078                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1079                                 if (i != 3)
1080                                         host->cmd->resp[i] |=
1081                                                 sdhci_readb(host,
1082                                                 SDHCI_RESPONSE + (3-i)*4-1);
1083                         }
1084                 } else {
1085                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1086                 }
1087         }
1088
1089         host->cmd->error = 0;
1090
1091         /* Finished CMD23, now send actual command. */
1092         if (host->cmd == host->mrq->sbc) {
1093                 host->cmd = NULL;
1094                 sdhci_send_command(host, host->mrq->cmd);
1095         } else {
1096
1097                 /* Processed actual command. */
1098                 if (host->data && host->data_early)
1099                         sdhci_finish_data(host);
1100
1101                 if (!host->cmd->data)
1102                         tasklet_schedule(&host->finish_tasklet);
1103
1104                 host->cmd = NULL;
1105         }
1106 }
1107
1108 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1109 {
1110         u16 ctrl, preset = 0;
1111
1112         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1113
1114         switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1115         case SDHCI_CTRL_UHS_SDR12:
1116                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1117                 break;
1118         case SDHCI_CTRL_UHS_SDR25:
1119                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1120                 break;
1121         case SDHCI_CTRL_UHS_SDR50:
1122                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1123                 break;
1124         case SDHCI_CTRL_UHS_SDR104:
1125                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1126                 break;
1127         case SDHCI_CTRL_UHS_DDR50:
1128                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1129                 break;
1130         default:
1131                 pr_warn("%s: Invalid UHS-I mode selected\n",
1132                         mmc_hostname(host->mmc));
1133                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1134                 break;
1135         }
1136         return preset;
1137 }
1138
1139 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1140 {
1141         int div = 0; /* Initialized for compiler warning */
1142         int real_div = div, clk_mul = 1;
1143         u16 clk = 0;
1144         unsigned long timeout;
1145
1146         if (clock && clock == host->clock)
1147                 return;
1148
1149         host->mmc->actual_clock = 0;
1150
1151         if (host->ops->set_clock) {
1152                 host->ops->set_clock(host, clock);
1153                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1154                         return;
1155         }
1156
1157         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1158
1159         if (clock == 0)
1160                 goto out;
1161
1162         if (host->version >= SDHCI_SPEC_300) {
1163                 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1164                         SDHCI_CTRL_PRESET_VAL_ENABLE) {
1165                         u16 pre_val;
1166
1167                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1168                         pre_val = sdhci_get_preset_value(host);
1169                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1170                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1171                         if (host->clk_mul &&
1172                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1173                                 clk = SDHCI_PROG_CLOCK_MODE;
1174                                 real_div = div + 1;
1175                                 clk_mul = host->clk_mul;
1176                         } else {
1177                                 real_div = max_t(int, 1, div << 1);
1178                         }
1179                         goto clock_set;
1180                 }
1181
1182                 /*
1183                  * Check if the Host Controller supports Programmable Clock
1184                  * Mode.
1185                  */
1186                 if (host->clk_mul) {
1187                         for (div = 1; div <= 1024; div++) {
1188                                 if ((host->max_clk * host->clk_mul / div)
1189                                         <= clock)
1190                                         break;
1191                         }
1192                         /*
1193                          * Set Programmable Clock Mode in the Clock
1194                          * Control register.
1195                          */
1196                         clk = SDHCI_PROG_CLOCK_MODE;
1197                         real_div = div;
1198                         clk_mul = host->clk_mul;
1199                         div--;
1200                 } else {
1201                         /* Version 3.00 divisors must be a multiple of 2. */
1202                         if (host->max_clk <= clock)
1203                                 div = 1;
1204                         else {
1205                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1206                                      div += 2) {
1207                                         if ((host->max_clk / div) <= clock)
1208                                                 break;
1209                                 }
1210                         }
1211                         real_div = div;
1212                         div >>= 1;
1213                 }
1214         } else {
1215                 /* Version 2.00 divisors must be a power of 2. */
1216                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1217                         if ((host->max_clk / div) <= clock)
1218                                 break;
1219                 }
1220                 real_div = div;
1221                 div >>= 1;
1222         }
1223
1224 clock_set:
1225         if (real_div)
1226                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1227
1228         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1229         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1230                 << SDHCI_DIVIDER_HI_SHIFT;
1231         clk |= SDHCI_CLOCK_INT_EN;
1232         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1233
1234         /* Wait max 20 ms */
1235         timeout = 20;
1236         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1237                 & SDHCI_CLOCK_INT_STABLE)) {
1238                 if (timeout == 0) {
1239                         pr_err("%s: Internal clock never "
1240                                 "stabilised.\n", mmc_hostname(host->mmc));
1241                         sdhci_dumpregs(host);
1242                         return;
1243                 }
1244                 timeout--;
1245                 mdelay(1);
1246         }
1247
1248         clk |= SDHCI_CLOCK_CARD_EN;
1249         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1250
1251 out:
1252         host->clock = clock;
1253 }
1254
1255 static inline void sdhci_update_clock(struct sdhci_host *host)
1256 {
1257         unsigned int clock;
1258
1259         clock = host->clock;
1260         host->clock = 0;
1261         sdhci_set_clock(host, clock);
1262 }
1263
1264 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1265 {
1266         u8 pwr = 0;
1267
1268         if (power != (unsigned short)-1) {
1269                 switch (1 << power) {
1270                 case MMC_VDD_165_195:
1271                         pwr = SDHCI_POWER_180;
1272                         break;
1273                 case MMC_VDD_29_30:
1274                 case MMC_VDD_30_31:
1275                         pwr = SDHCI_POWER_300;
1276                         break;
1277                 case MMC_VDD_32_33:
1278                 case MMC_VDD_33_34:
1279                         pwr = SDHCI_POWER_330;
1280                         break;
1281                 default:
1282                         BUG();
1283                 }
1284         }
1285
1286         if (host->pwr == pwr)
1287                 return -1;
1288
1289         host->pwr = pwr;
1290
1291         if (pwr == 0) {
1292                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1293                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1294                         sdhci_runtime_pm_bus_off(host);
1295                 return 0;
1296         }
1297
1298         /*
1299          * Spec says that we should clear the power reg before setting
1300          * a new value. Some controllers don't seem to like this though.
1301          */
1302         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1303                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1304
1305         /*
1306          * At least the Marvell CaFe chip gets confused if we set the voltage
1307          * and set turn on power at the same time, so set the voltage first.
1308          */
1309         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1310                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1311
1312         pwr |= SDHCI_POWER_ON;
1313
1314         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1315
1316         if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1317                 sdhci_runtime_pm_bus_on(host);
1318
1319         /*
1320          * Some controllers need an extra 10ms delay of 10ms before they
1321          * can apply clock after applying power
1322          */
1323         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1324                 mdelay(10);
1325
1326         return power;
1327 }
1328
1329 /*****************************************************************************\
1330  *                                                                           *
1331  * MMC callbacks                                                             *
1332  *                                                                           *
1333 \*****************************************************************************/
1334
1335 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1336 {
1337         struct sdhci_host *host;
1338         int present;
1339         unsigned long flags;
1340         u32 tuning_opcode;
1341
1342         host = mmc_priv(mmc);
1343
1344         sdhci_runtime_pm_get(host);
1345
1346         spin_lock_irqsave(&host->lock, flags);
1347
1348         WARN_ON(host->mrq != NULL);
1349
1350 #ifndef SDHCI_USE_LEDS_CLASS
1351         sdhci_activate_led(host);
1352 #endif
1353
1354         /*
1355          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1356          * requests if Auto-CMD12 is enabled.
1357          */
1358         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1359                 if (mrq->stop) {
1360                         mrq->data->stop = NULL;
1361                         mrq->stop = NULL;
1362                 }
1363         }
1364
1365         host->mrq = mrq;
1366
1367         /*
1368          * Firstly check card presence from cd-gpio.  The return could
1369          * be one of the following possibilities:
1370          *     negative: cd-gpio is not available
1371          *     zero: cd-gpio is used, and card is removed
1372          *     one: cd-gpio is used, and card is present
1373          */
1374         present = mmc_gpio_get_cd(host->mmc);
1375         if (present < 0) {
1376                 /* If polling, assume that the card is always present. */
1377                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1378                         present = 1;
1379                 else
1380                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1381                                         SDHCI_CARD_PRESENT;
1382         }
1383
1384         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1385                 host->mrq->cmd->error = -ENOMEDIUM;
1386                 tasklet_schedule(&host->finish_tasklet);
1387         } else {
1388                 u32 present_state;
1389
1390                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1391                 /*
1392                  * Check if the re-tuning timer has already expired and there
1393                  * is no on-going data transfer. If so, we need to execute
1394                  * tuning procedure before sending command.
1395                  */
1396                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1397                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1398                         if (mmc->card) {
1399                                 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1400                                 tuning_opcode =
1401                                         mmc->card->type == MMC_TYPE_MMC ?
1402                                         MMC_SEND_TUNING_BLOCK_HS200 :
1403                                         MMC_SEND_TUNING_BLOCK;
1404
1405                                 /* Here we need to set the host->mrq to NULL,
1406                                  * in case the pending finish_tasklet
1407                                  * finishes it incorrectly.
1408                                  */
1409                                 host->mrq = NULL;
1410
1411                                 spin_unlock_irqrestore(&host->lock, flags);
1412                                 sdhci_execute_tuning(mmc, tuning_opcode);
1413                                 spin_lock_irqsave(&host->lock, flags);
1414
1415                                 /* Restore original mmc_request structure */
1416                                 host->mrq = mrq;
1417                         }
1418                 }
1419
1420                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1421                         sdhci_send_command(host, mrq->sbc);
1422                 else
1423                         sdhci_send_command(host, mrq->cmd);
1424         }
1425
1426         mmiowb();
1427         spin_unlock_irqrestore(&host->lock, flags);
1428 }
1429
1430 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1431 {
1432         unsigned long flags;
1433         int vdd_bit = -1;
1434         u8 ctrl;
1435
1436         spin_lock_irqsave(&host->lock, flags);
1437
1438         if (host->flags & SDHCI_DEVICE_DEAD) {
1439                 spin_unlock_irqrestore(&host->lock, flags);
1440                 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1441                         mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1442                 return;
1443         }
1444
1445         /*
1446          * Reset the chip on each power off.
1447          * Should clear out any weird states.
1448          */
1449         if (ios->power_mode == MMC_POWER_OFF) {
1450                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1451                 sdhci_reinit(host);
1452         }
1453
1454         if (host->version >= SDHCI_SPEC_300 &&
1455                 (ios->power_mode == MMC_POWER_UP) &&
1456                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1457                 sdhci_enable_preset_value(host, false);
1458
1459         sdhci_set_clock(host, ios->clock);
1460
1461         if (ios->power_mode == MMC_POWER_OFF)
1462                 vdd_bit = sdhci_set_power(host, -1);
1463         else
1464                 vdd_bit = sdhci_set_power(host, ios->vdd);
1465
1466         if (host->vmmc && vdd_bit != -1) {
1467                 spin_unlock_irqrestore(&host->lock, flags);
1468                 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1469                 spin_lock_irqsave(&host->lock, flags);
1470         }
1471
1472         if (host->ops->platform_send_init_74_clocks)
1473                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1474
1475         /*
1476          * If your platform has 8-bit width support but is not a v3 controller,
1477          * or if it requires special setup code, you should implement that in
1478          * platform_bus_width().
1479          */
1480         if (host->ops->platform_bus_width) {
1481                 host->ops->platform_bus_width(host, ios->bus_width);
1482         } else {
1483                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1484                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1485                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1486                         if (host->version >= SDHCI_SPEC_300)
1487                                 ctrl |= SDHCI_CTRL_8BITBUS;
1488                 } else {
1489                         if (host->version >= SDHCI_SPEC_300)
1490                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1491                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1492                                 ctrl |= SDHCI_CTRL_4BITBUS;
1493                         else
1494                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1495                 }
1496                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1497         }
1498
1499         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1500
1501         if ((ios->timing == MMC_TIMING_SD_HS ||
1502              ios->timing == MMC_TIMING_MMC_HS)
1503             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1504                 ctrl |= SDHCI_CTRL_HISPD;
1505         else
1506                 ctrl &= ~SDHCI_CTRL_HISPD;
1507
1508         if (host->version >= SDHCI_SPEC_300) {
1509                 u16 clk, ctrl_2;
1510
1511                 /* In case of UHS-I modes, set High Speed Enable */
1512                 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1513                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1514                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1515                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1516                     (ios->timing == MMC_TIMING_UHS_SDR25))
1517                         ctrl |= SDHCI_CTRL_HISPD;
1518
1519                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1520                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1521                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1522                         /*
1523                          * We only need to set Driver Strength if the
1524                          * preset value enable is not set.
1525                          */
1526                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1527                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1528                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1529                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1530                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1531
1532                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1533                 } else {
1534                         /*
1535                          * According to SDHC Spec v3.00, if the Preset Value
1536                          * Enable in the Host Control 2 register is set, we
1537                          * need to reset SD Clock Enable before changing High
1538                          * Speed Enable to avoid generating clock gliches.
1539                          */
1540
1541                         /* Reset SD Clock Enable */
1542                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1543                         clk &= ~SDHCI_CLOCK_CARD_EN;
1544                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1545
1546                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1547
1548                         /* Re-enable SD Clock */
1549                         sdhci_update_clock(host);
1550                 }
1551
1552
1553                 /* Reset SD Clock Enable */
1554                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1555                 clk &= ~SDHCI_CLOCK_CARD_EN;
1556                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1557
1558                 if (host->ops->set_uhs_signaling)
1559                         host->ops->set_uhs_signaling(host, ios->timing);
1560                 else {
1561                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1562                         /* Select Bus Speed Mode for host */
1563                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1564                         if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1565                             (ios->timing == MMC_TIMING_UHS_SDR104))
1566                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1567                         else if (ios->timing == MMC_TIMING_UHS_SDR12)
1568                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1569                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1570                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1571                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1572                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1573                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1574                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1575                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1576                 }
1577
1578                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1579                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1580                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1581                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1582                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1583                                  (ios->timing == MMC_TIMING_UHS_DDR50))) {
1584                         u16 preset;
1585
1586                         sdhci_enable_preset_value(host, true);
1587                         preset = sdhci_get_preset_value(host);
1588                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1589                                 >> SDHCI_PRESET_DRV_SHIFT;
1590                 }
1591
1592                 /* Re-enable SD Clock */
1593                 sdhci_update_clock(host);
1594         } else
1595                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1596
1597         /*
1598          * Some (ENE) controllers go apeshit on some ios operation,
1599          * signalling timeout and CRC errors even on CMD0. Resetting
1600          * it on each ios seems to solve the problem.
1601          */
1602         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1603                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1604
1605         mmiowb();
1606         spin_unlock_irqrestore(&host->lock, flags);
1607 }
1608
1609 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1610 {
1611         struct sdhci_host *host = mmc_priv(mmc);
1612
1613         sdhci_runtime_pm_get(host);
1614         sdhci_do_set_ios(host, ios);
1615         sdhci_runtime_pm_put(host);
1616 }
1617
1618 static int sdhci_do_get_cd(struct sdhci_host *host)
1619 {
1620         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1621
1622         if (host->flags & SDHCI_DEVICE_DEAD)
1623                 return 0;
1624
1625         /* If polling/nonremovable, assume that the card is always present. */
1626         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1627             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1628                 return 1;
1629
1630         /* Try slot gpio detect */
1631         if (!IS_ERR_VALUE(gpio_cd))
1632                 return !!gpio_cd;
1633
1634         /* Host native card detect */
1635         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1636 }
1637
1638 static int sdhci_get_cd(struct mmc_host *mmc)
1639 {
1640         struct sdhci_host *host = mmc_priv(mmc);
1641         int ret;
1642
1643         sdhci_runtime_pm_get(host);
1644         ret = sdhci_do_get_cd(host);
1645         sdhci_runtime_pm_put(host);
1646         return ret;
1647 }
1648
1649 static int sdhci_check_ro(struct sdhci_host *host)
1650 {
1651         unsigned long flags;
1652         int is_readonly;
1653
1654         spin_lock_irqsave(&host->lock, flags);
1655
1656         if (host->flags & SDHCI_DEVICE_DEAD)
1657                 is_readonly = 0;
1658         else if (host->ops->get_ro)
1659                 is_readonly = host->ops->get_ro(host);
1660         else
1661                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1662                                 & SDHCI_WRITE_PROTECT);
1663
1664         spin_unlock_irqrestore(&host->lock, flags);
1665
1666         /* This quirk needs to be replaced by a callback-function later */
1667         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1668                 !is_readonly : is_readonly;
1669 }
1670
1671 #define SAMPLE_COUNT    5
1672
1673 static int sdhci_do_get_ro(struct sdhci_host *host)
1674 {
1675         int i, ro_count;
1676
1677         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1678                 return sdhci_check_ro(host);
1679
1680         ro_count = 0;
1681         for (i = 0; i < SAMPLE_COUNT; i++) {
1682                 if (sdhci_check_ro(host)) {
1683                         if (++ro_count > SAMPLE_COUNT / 2)
1684                                 return 1;
1685                 }
1686                 msleep(30);
1687         }
1688         return 0;
1689 }
1690
1691 static void sdhci_hw_reset(struct mmc_host *mmc)
1692 {
1693         struct sdhci_host *host = mmc_priv(mmc);
1694
1695         if (host->ops && host->ops->hw_reset)
1696                 host->ops->hw_reset(host);
1697 }
1698
1699 static int sdhci_get_ro(struct mmc_host *mmc)
1700 {
1701         struct sdhci_host *host = mmc_priv(mmc);
1702         int ret;
1703
1704         sdhci_runtime_pm_get(host);
1705         ret = sdhci_do_get_ro(host);
1706         sdhci_runtime_pm_put(host);
1707         return ret;
1708 }
1709
1710 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1711 {
1712         if (host->flags & SDHCI_DEVICE_DEAD)
1713                 goto out;
1714
1715         if (enable)
1716                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1717         else
1718                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1719
1720         /* SDIO IRQ will be enabled as appropriate in runtime resume */
1721         if (host->runtime_suspended)
1722                 goto out;
1723
1724         if (enable)
1725                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1726         else
1727                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1728 out:
1729         mmiowb();
1730 }
1731
1732 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1733 {
1734         struct sdhci_host *host = mmc_priv(mmc);
1735         unsigned long flags;
1736
1737         spin_lock_irqsave(&host->lock, flags);
1738         sdhci_enable_sdio_irq_nolock(host, enable);
1739         spin_unlock_irqrestore(&host->lock, flags);
1740 }
1741
1742 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1743                                                 struct mmc_ios *ios)
1744 {
1745         u16 ctrl;
1746         int ret;
1747
1748         /*
1749          * Signal Voltage Switching is only applicable for Host Controllers
1750          * v3.00 and above.
1751          */
1752         if (host->version < SDHCI_SPEC_300)
1753                 return 0;
1754
1755         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1756
1757         switch (ios->signal_voltage) {
1758         case MMC_SIGNAL_VOLTAGE_330:
1759                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1760                 ctrl &= ~SDHCI_CTRL_VDD_180;
1761                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1762
1763                 if (host->vqmmc) {
1764                         ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1765                         if (ret) {
1766                                 pr_warning("%s: Switching to 3.3V signalling voltage "
1767                                                 " failed\n", mmc_hostname(host->mmc));
1768                                 return -EIO;
1769                         }
1770                 }
1771                 /* Wait for 5ms */
1772                 usleep_range(5000, 5500);
1773
1774                 /* 3.3V regulator output should be stable within 5 ms */
1775                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1776                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1777                         return 0;
1778
1779                 pr_warning("%s: 3.3V regulator output did not became stable\n",
1780                                 mmc_hostname(host->mmc));
1781
1782                 return -EAGAIN;
1783         case MMC_SIGNAL_VOLTAGE_180:
1784                 if (host->vqmmc) {
1785                         ret = regulator_set_voltage(host->vqmmc,
1786                                         1700000, 1950000);
1787                         if (ret) {
1788                                 pr_warning("%s: Switching to 1.8V signalling voltage "
1789                                                 " failed\n", mmc_hostname(host->mmc));
1790                                 return -EIO;
1791                         }
1792                 }
1793
1794                 /*
1795                  * Enable 1.8V Signal Enable in the Host Control2
1796                  * register
1797                  */
1798                 ctrl |= SDHCI_CTRL_VDD_180;
1799                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1800
1801                 /* Wait for 5ms */
1802                 usleep_range(5000, 5500);
1803
1804                 /* 1.8V regulator output should be stable within 5 ms */
1805                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1806                 if (ctrl & SDHCI_CTRL_VDD_180)
1807                         return 0;
1808
1809                 pr_warning("%s: 1.8V regulator output did not became stable\n",
1810                                 mmc_hostname(host->mmc));
1811
1812                 return -EAGAIN;
1813         case MMC_SIGNAL_VOLTAGE_120:
1814                 if (host->vqmmc) {
1815                         ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1816                         if (ret) {
1817                                 pr_warning("%s: Switching to 1.2V signalling voltage "
1818                                                 " failed\n", mmc_hostname(host->mmc));
1819                                 return -EIO;
1820                         }
1821                 }
1822                 return 0;
1823         default:
1824                 /* No signal voltage switch required */
1825                 return 0;
1826         }
1827 }
1828
1829 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1830         struct mmc_ios *ios)
1831 {
1832         struct sdhci_host *host = mmc_priv(mmc);
1833         int err;
1834
1835         if (host->version < SDHCI_SPEC_300)
1836                 return 0;
1837         sdhci_runtime_pm_get(host);
1838         err = sdhci_do_start_signal_voltage_switch(host, ios);
1839         sdhci_runtime_pm_put(host);
1840         return err;
1841 }
1842
1843 static int sdhci_card_busy(struct mmc_host *mmc)
1844 {
1845         struct sdhci_host *host = mmc_priv(mmc);
1846         u32 present_state;
1847
1848         sdhci_runtime_pm_get(host);
1849         /* Check whether DAT[3:0] is 0000 */
1850         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1851         sdhci_runtime_pm_put(host);
1852
1853         return !(present_state & SDHCI_DATA_LVL_MASK);
1854 }
1855
1856 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1857 {
1858         struct sdhci_host *host;
1859         u16 ctrl;
1860         u32 ier;
1861         int tuning_loop_counter = MAX_TUNING_LOOP;
1862         unsigned long timeout;
1863         int err = 0;
1864         bool requires_tuning_nonuhs = false;
1865         unsigned long flags;
1866
1867         host = mmc_priv(mmc);
1868
1869         sdhci_runtime_pm_get(host);
1870         spin_lock_irqsave(&host->lock, flags);
1871
1872         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1873
1874         /*
1875          * The Host Controller needs tuning only in case of SDR104 mode
1876          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1877          * Capabilities register.
1878          * If the Host Controller supports the HS200 mode then the
1879          * tuning function has to be executed.
1880          */
1881         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1882             (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1883              host->flags & SDHCI_SDR104_NEEDS_TUNING))
1884                 requires_tuning_nonuhs = true;
1885
1886         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1887             requires_tuning_nonuhs)
1888                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1889         else {
1890                 spin_unlock_irqrestore(&host->lock, flags);
1891                 sdhci_runtime_pm_put(host);
1892                 return 0;
1893         }
1894
1895         if (host->ops->platform_execute_tuning) {
1896                 spin_unlock_irqrestore(&host->lock, flags);
1897                 err = host->ops->platform_execute_tuning(host, opcode);
1898                 sdhci_runtime_pm_put(host);
1899                 return err;
1900         }
1901
1902         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1903
1904         /*
1905          * As per the Host Controller spec v3.00, tuning command
1906          * generates Buffer Read Ready interrupt, so enable that.
1907          *
1908          * Note: The spec clearly says that when tuning sequence
1909          * is being performed, the controller does not generate
1910          * interrupts other than Buffer Read Ready interrupt. But
1911          * to make sure we don't hit a controller bug, we _only_
1912          * enable Buffer Read Ready interrupt here.
1913          */
1914         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1915         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1916
1917         /*
1918          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1919          * of loops reaches 40 times or a timeout of 150ms occurs.
1920          */
1921         timeout = 150;
1922         do {
1923                 struct mmc_command cmd = {0};
1924                 struct mmc_request mrq = {NULL};
1925
1926                 if (!tuning_loop_counter && !timeout)
1927                         break;
1928
1929                 cmd.opcode = opcode;
1930                 cmd.arg = 0;
1931                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1932                 cmd.retries = 0;
1933                 cmd.data = NULL;
1934                 cmd.error = 0;
1935
1936                 mrq.cmd = &cmd;
1937                 host->mrq = &mrq;
1938
1939                 /*
1940                  * In response to CMD19, the card sends 64 bytes of tuning
1941                  * block to the Host Controller. So we set the block size
1942                  * to 64 here.
1943                  */
1944                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1945                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1946                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1947                                              SDHCI_BLOCK_SIZE);
1948                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1949                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1950                                              SDHCI_BLOCK_SIZE);
1951                 } else {
1952                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1953                                      SDHCI_BLOCK_SIZE);
1954                 }
1955
1956                 /*
1957                  * The tuning block is sent by the card to the host controller.
1958                  * So we set the TRNS_READ bit in the Transfer Mode register.
1959                  * This also takes care of setting DMA Enable and Multi Block
1960                  * Select in the same register to 0.
1961                  */
1962                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1963
1964                 sdhci_send_command(host, &cmd);
1965
1966                 host->cmd = NULL;
1967                 host->mrq = NULL;
1968
1969                 spin_unlock_irqrestore(&host->lock, flags);
1970                 /* Wait for Buffer Read Ready interrupt */
1971                 wait_event_interruptible_timeout(host->buf_ready_int,
1972                                         (host->tuning_done == 1),
1973                                         msecs_to_jiffies(50));
1974                 spin_lock_irqsave(&host->lock, flags);
1975
1976                 if (!host->tuning_done) {
1977                         pr_info(DRIVER_NAME ": Timeout waiting for "
1978                                 "Buffer Read Ready interrupt during tuning "
1979                                 "procedure, falling back to fixed sampling "
1980                                 "clock\n");
1981                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1982                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1983                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1984                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1985
1986                         err = -EIO;
1987                         goto out;
1988                 }
1989
1990                 host->tuning_done = 0;
1991
1992                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1993                 tuning_loop_counter--;
1994                 timeout--;
1995                 mdelay(1);
1996         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1997
1998         /*
1999          * The Host Driver has exhausted the maximum number of loops allowed,
2000          * so use fixed sampling frequency.
2001          */
2002         if (!tuning_loop_counter || !timeout) {
2003                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2004                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2005                 err = -EIO;
2006         } else {
2007                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2008                         pr_info(DRIVER_NAME ": Tuning procedure"
2009                                 " failed, falling back to fixed sampling"
2010                                 " clock\n");
2011                         err = -EIO;
2012                 }
2013         }
2014
2015 out:
2016         /*
2017          * If this is the very first time we are here, we start the retuning
2018          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2019          * flag won't be set, we check this condition before actually starting
2020          * the timer.
2021          */
2022         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2023             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2024                 host->flags |= SDHCI_USING_RETUNING_TIMER;
2025                 mod_timer(&host->tuning_timer, jiffies +
2026                         host->tuning_count * HZ);
2027                 /* Tuning mode 1 limits the maximum data length to 4MB */
2028                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2029         } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2030                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2031                 /* Reload the new initial value for timer */
2032                 mod_timer(&host->tuning_timer, jiffies +
2033                           host->tuning_count * HZ);
2034         }
2035
2036         /*
2037          * In case tuning fails, host controllers which support re-tuning can
2038          * try tuning again at a later time, when the re-tuning timer expires.
2039          * So for these controllers, we return 0. Since there might be other
2040          * controllers who do not have this capability, we return error for
2041          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2042          * a retuning timer to do the retuning for the card.
2043          */
2044         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2045                 err = 0;
2046
2047         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2048         spin_unlock_irqrestore(&host->lock, flags);
2049         sdhci_runtime_pm_put(host);
2050
2051         return err;
2052 }
2053
2054
2055 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2056 {
2057         u16 ctrl;
2058
2059         /* Host Controller v3.00 defines preset value registers */
2060         if (host->version < SDHCI_SPEC_300)
2061                 return;
2062
2063         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2064
2065         /*
2066          * We only enable or disable Preset Value if they are not already
2067          * enabled or disabled respectively. Otherwise, we bail out.
2068          */
2069         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2070                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2071                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2072                 host->flags |= SDHCI_PV_ENABLED;
2073         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2074                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2075                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2076                 host->flags &= ~SDHCI_PV_ENABLED;
2077         }
2078 }
2079
2080 static void sdhci_card_event(struct mmc_host *mmc)
2081 {
2082         struct sdhci_host *host = mmc_priv(mmc);
2083         unsigned long flags;
2084
2085         /* First check if client has provided their own card event */
2086         if (host->ops->card_event)
2087                 host->ops->card_event(host);
2088
2089         spin_lock_irqsave(&host->lock, flags);
2090
2091         /* Check host->mrq first in case we are runtime suspended */
2092         if (host->mrq && !sdhci_do_get_cd(host)) {
2093                 pr_err("%s: Card removed during transfer!\n",
2094                         mmc_hostname(host->mmc));
2095                 pr_err("%s: Resetting controller.\n",
2096                         mmc_hostname(host->mmc));
2097
2098                 sdhci_reset(host, SDHCI_RESET_CMD);
2099                 sdhci_reset(host, SDHCI_RESET_DATA);
2100
2101                 host->mrq->cmd->error = -ENOMEDIUM;
2102                 tasklet_schedule(&host->finish_tasklet);
2103         }
2104
2105         spin_unlock_irqrestore(&host->lock, flags);
2106 }
2107
2108 static const struct mmc_host_ops sdhci_ops = {
2109         .request        = sdhci_request,
2110         .set_ios        = sdhci_set_ios,
2111         .get_cd         = sdhci_get_cd,
2112         .get_ro         = sdhci_get_ro,
2113         .hw_reset       = sdhci_hw_reset,
2114         .enable_sdio_irq = sdhci_enable_sdio_irq,
2115         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2116         .execute_tuning                 = sdhci_execute_tuning,
2117         .card_event                     = sdhci_card_event,
2118         .card_busy      = sdhci_card_busy,
2119 };
2120
2121 /*****************************************************************************\
2122  *                                                                           *
2123  * Tasklets                                                                  *
2124  *                                                                           *
2125 \*****************************************************************************/
2126
2127 static void sdhci_tasklet_card(unsigned long param)
2128 {
2129         struct sdhci_host *host = (struct sdhci_host*)param;
2130
2131         sdhci_card_event(host->mmc);
2132
2133         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2134 }
2135
2136 static void sdhci_tasklet_finish(unsigned long param)
2137 {
2138         struct sdhci_host *host;
2139         unsigned long flags;
2140         struct mmc_request *mrq;
2141
2142         host = (struct sdhci_host*)param;
2143
2144         spin_lock_irqsave(&host->lock, flags);
2145
2146         /*
2147          * If this tasklet gets rescheduled while running, it will
2148          * be run again afterwards but without any active request.
2149          */
2150         if (!host->mrq) {
2151                 spin_unlock_irqrestore(&host->lock, flags);
2152                 return;
2153         }
2154
2155         del_timer(&host->timer);
2156
2157         mrq = host->mrq;
2158
2159         /*
2160          * The controller needs a reset of internal state machines
2161          * upon error conditions.
2162          */
2163         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2164             ((mrq->cmd && mrq->cmd->error) ||
2165                  (mrq->data && (mrq->data->error ||
2166                   (mrq->data->stop && mrq->data->stop->error))) ||
2167                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2168
2169                 /* Some controllers need this kick or reset won't work here */
2170                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2171                         /* This is to force an update */
2172                         sdhci_update_clock(host);
2173
2174                 /* Spec says we should do both at the same time, but Ricoh
2175                    controllers do not like that. */
2176                 sdhci_reset(host, SDHCI_RESET_CMD);
2177                 sdhci_reset(host, SDHCI_RESET_DATA);
2178         }
2179
2180         host->mrq = NULL;
2181         host->cmd = NULL;
2182         host->data = NULL;
2183
2184 #ifndef SDHCI_USE_LEDS_CLASS
2185         sdhci_deactivate_led(host);
2186 #endif
2187
2188         mmiowb();
2189         spin_unlock_irqrestore(&host->lock, flags);
2190
2191         mmc_request_done(host->mmc, mrq);
2192         sdhci_runtime_pm_put(host);
2193 }
2194
2195 static void sdhci_timeout_timer(unsigned long data)
2196 {
2197         struct sdhci_host *host;
2198         unsigned long flags;
2199
2200         host = (struct sdhci_host*)data;
2201
2202         spin_lock_irqsave(&host->lock, flags);
2203
2204         if (host->mrq) {
2205                 pr_err("%s: Timeout waiting for hardware "
2206                         "interrupt.\n", mmc_hostname(host->mmc));
2207                 sdhci_dumpregs(host);
2208
2209                 if (host->data) {
2210                         host->data->error = -ETIMEDOUT;
2211                         sdhci_finish_data(host);
2212                 } else {
2213                         if (host->cmd)
2214                                 host->cmd->error = -ETIMEDOUT;
2215                         else
2216                                 host->mrq->cmd->error = -ETIMEDOUT;
2217
2218                         tasklet_schedule(&host->finish_tasklet);
2219                 }
2220         }
2221
2222         mmiowb();
2223         spin_unlock_irqrestore(&host->lock, flags);
2224 }
2225
2226 static void sdhci_tuning_timer(unsigned long data)
2227 {
2228         struct sdhci_host *host;
2229         unsigned long flags;
2230
2231         host = (struct sdhci_host *)data;
2232
2233         spin_lock_irqsave(&host->lock, flags);
2234
2235         host->flags |= SDHCI_NEEDS_RETUNING;
2236
2237         spin_unlock_irqrestore(&host->lock, flags);
2238 }
2239
2240 /*****************************************************************************\
2241  *                                                                           *
2242  * Interrupt handling                                                        *
2243  *                                                                           *
2244 \*****************************************************************************/
2245
2246 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2247 {
2248         BUG_ON(intmask == 0);
2249
2250         if (!host->cmd) {
2251                 pr_err("%s: Got command interrupt 0x%08x even "
2252                         "though no command operation was in progress.\n",
2253                         mmc_hostname(host->mmc), (unsigned)intmask);
2254                 sdhci_dumpregs(host);
2255                 return;
2256         }
2257
2258         if (intmask & SDHCI_INT_TIMEOUT)
2259                 host->cmd->error = -ETIMEDOUT;
2260         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2261                         SDHCI_INT_INDEX))
2262                 host->cmd->error = -EILSEQ;
2263
2264         if (host->cmd->error) {
2265                 tasklet_schedule(&host->finish_tasklet);
2266                 return;
2267         }
2268
2269         /*
2270          * The host can send and interrupt when the busy state has
2271          * ended, allowing us to wait without wasting CPU cycles.
2272          * Unfortunately this is overloaded on the "data complete"
2273          * interrupt, so we need to take some care when handling
2274          * it.
2275          *
2276          * Note: The 1.0 specification is a bit ambiguous about this
2277          *       feature so there might be some problems with older
2278          *       controllers.
2279          */
2280         if (host->cmd->flags & MMC_RSP_BUSY) {
2281                 if (host->cmd->data)
2282                         DBG("Cannot wait for busy signal when also "
2283                                 "doing a data transfer");
2284                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2285                         return;
2286
2287                 /* The controller does not support the end-of-busy IRQ,
2288                  * fall through and take the SDHCI_INT_RESPONSE */
2289         }
2290
2291         if (intmask & SDHCI_INT_RESPONSE)
2292                 sdhci_finish_command(host);
2293 }
2294
2295 #ifdef CONFIG_MMC_DEBUG
2296 static void sdhci_show_adma_error(struct sdhci_host *host)
2297 {
2298         const char *name = mmc_hostname(host->mmc);
2299         u8 *desc = host->adma_desc;
2300         __le32 *dma;
2301         __le16 *len;
2302         u8 attr;
2303
2304         sdhci_dumpregs(host);
2305
2306         while (true) {
2307                 dma = (__le32 *)(desc + 4);
2308                 len = (__le16 *)(desc + 2);
2309                 attr = *desc;
2310
2311                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2312                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2313
2314                 desc += 8;
2315
2316                 if (attr & 2)
2317                         break;
2318         }
2319 }
2320 #else
2321 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2322 #endif
2323
2324 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2325 {
2326         u32 command;
2327         BUG_ON(intmask == 0);
2328
2329         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2330         if (intmask & SDHCI_INT_DATA_AVAIL) {
2331                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2332                 if (command == MMC_SEND_TUNING_BLOCK ||
2333                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2334                         host->tuning_done = 1;
2335                         wake_up(&host->buf_ready_int);
2336                         return;
2337                 }
2338         }
2339
2340         if (!host->data) {
2341                 /*
2342                  * The "data complete" interrupt is also used to
2343                  * indicate that a busy state has ended. See comment
2344                  * above in sdhci_cmd_irq().
2345                  */
2346                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2347                         if (intmask & SDHCI_INT_DATA_END) {
2348                                 sdhci_finish_command(host);
2349                                 return;
2350                         }
2351                 }
2352
2353                 pr_err("%s: Got data interrupt 0x%08x even "
2354                         "though no data operation was in progress.\n",
2355                         mmc_hostname(host->mmc), (unsigned)intmask);
2356                 sdhci_dumpregs(host);
2357
2358                 return;
2359         }
2360
2361         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2362                 host->data->error = -ETIMEDOUT;
2363         else if (intmask & SDHCI_INT_DATA_END_BIT)
2364                 host->data->error = -EILSEQ;
2365         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2366                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2367                         != MMC_BUS_TEST_R)
2368                 host->data->error = -EILSEQ;
2369         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2370                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2371                 sdhci_show_adma_error(host);
2372                 host->data->error = -EIO;
2373                 if (host->ops->adma_workaround)
2374                         host->ops->adma_workaround(host, intmask);
2375         }
2376
2377         if (host->data->error)
2378                 sdhci_finish_data(host);
2379         else {
2380                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2381                         sdhci_transfer_pio(host);
2382
2383                 /*
2384                  * We currently don't do anything fancy with DMA
2385                  * boundaries, but as we can't disable the feature
2386                  * we need to at least restart the transfer.
2387                  *
2388                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2389                  * should return a valid address to continue from, but as
2390                  * some controllers are faulty, don't trust them.
2391                  */
2392                 if (intmask & SDHCI_INT_DMA_END) {
2393                         u32 dmastart, dmanow;
2394                         dmastart = sg_dma_address(host->data->sg);
2395                         dmanow = dmastart + host->data->bytes_xfered;
2396                         /*
2397                          * Force update to the next DMA block boundary.
2398                          */
2399                         dmanow = (dmanow &
2400                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2401                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2402                         host->data->bytes_xfered = dmanow - dmastart;
2403                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2404                                 " next 0x%08x\n",
2405                                 mmc_hostname(host->mmc), dmastart,
2406                                 host->data->bytes_xfered, dmanow);
2407                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2408                 }
2409
2410                 if (intmask & SDHCI_INT_DATA_END) {
2411                         if (host->cmd) {
2412                                 /*
2413                                  * Data managed to finish before the
2414                                  * command completed. Make sure we do
2415                                  * things in the proper order.
2416                                  */
2417                                 host->data_early = 1;
2418                         } else {
2419                                 sdhci_finish_data(host);
2420                         }
2421                 }
2422         }
2423 }
2424
2425 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2426 {
2427         irqreturn_t result;
2428         struct sdhci_host *host = dev_id;
2429         u32 intmask, unexpected = 0;
2430         int cardint = 0, max_loops = 16;
2431
2432         spin_lock(&host->lock);
2433
2434         if (host->runtime_suspended) {
2435                 spin_unlock(&host->lock);
2436                 return IRQ_NONE;
2437         }
2438
2439         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2440
2441         if (!intmask || intmask == 0xffffffff) {
2442                 result = IRQ_NONE;
2443                 goto out;
2444         }
2445
2446 again:
2447         DBG("*** %s got interrupt: 0x%08x\n",
2448                 mmc_hostname(host->mmc), intmask);
2449
2450         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2451                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2452                               SDHCI_CARD_PRESENT;
2453
2454                 /*
2455                  * There is a observation on i.mx esdhc.  INSERT bit will be
2456                  * immediately set again when it gets cleared, if a card is
2457                  * inserted.  We have to mask the irq to prevent interrupt
2458                  * storm which will freeze the system.  And the REMOVE gets
2459                  * the same situation.
2460                  *
2461                  * More testing are needed here to ensure it works for other
2462                  * platforms though.
2463                  */
2464                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2465                                                 SDHCI_INT_CARD_REMOVE);
2466                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2467                                                   SDHCI_INT_CARD_INSERT);
2468
2469                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2470                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2471                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2472                 tasklet_schedule(&host->card_tasklet);
2473         }
2474
2475         if (intmask & SDHCI_INT_CMD_MASK) {
2476                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2477                         SDHCI_INT_STATUS);
2478                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2479         }
2480
2481         if (intmask & SDHCI_INT_DATA_MASK) {
2482                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2483                         SDHCI_INT_STATUS);
2484                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2485         }
2486
2487         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2488
2489         intmask &= ~SDHCI_INT_ERROR;
2490
2491         if (intmask & SDHCI_INT_BUS_POWER) {
2492                 pr_err("%s: Card is consuming too much power!\n",
2493                         mmc_hostname(host->mmc));
2494                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2495         }
2496
2497         intmask &= ~SDHCI_INT_BUS_POWER;
2498
2499         if (intmask & SDHCI_INT_CARD_INT)
2500                 cardint = 1;
2501
2502         intmask &= ~SDHCI_INT_CARD_INT;
2503
2504         if (intmask) {
2505                 unexpected |= intmask;
2506                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2507         }
2508
2509         result = IRQ_HANDLED;
2510
2511         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2512
2513         /*
2514          * If we know we'll call the driver to signal SDIO IRQ, disregard
2515          * further indications of Card Interrupt in the status to avoid a
2516          * needless loop.
2517          */
2518         if (cardint)
2519                 intmask &= ~SDHCI_INT_CARD_INT;
2520         if (intmask && --max_loops)
2521                 goto again;
2522 out:
2523         spin_unlock(&host->lock);
2524
2525         if (unexpected) {
2526                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2527                            mmc_hostname(host->mmc), unexpected);
2528                 sdhci_dumpregs(host);
2529         }
2530         /*
2531          * We have to delay this as it calls back into the driver.
2532          */
2533         if (cardint)
2534                 mmc_signal_sdio_irq(host->mmc);
2535
2536         return result;
2537 }
2538
2539 /*****************************************************************************\
2540  *                                                                           *
2541  * Suspend/resume                                                            *
2542  *                                                                           *
2543 \*****************************************************************************/
2544
2545 #ifdef CONFIG_PM
2546 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2547 {
2548         u8 val;
2549         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2550                         | SDHCI_WAKE_ON_INT;
2551
2552         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2553         val |= mask ;
2554         /* Avoid fake wake up */
2555         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2556                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2557         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2558 }
2559 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2560
2561 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2562 {
2563         u8 val;
2564         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2565                         | SDHCI_WAKE_ON_INT;
2566
2567         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2568         val &= ~mask;
2569         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2570 }
2571 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2572
2573 int sdhci_suspend_host(struct sdhci_host *host)
2574 {
2575         if (host->ops->platform_suspend)
2576                 host->ops->platform_suspend(host);
2577
2578         sdhci_disable_card_detection(host);
2579
2580         /* Disable tuning since we are suspending */
2581         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2582                 del_timer_sync(&host->tuning_timer);
2583                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2584         }
2585
2586         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2587                 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2588                 free_irq(host->irq, host);
2589         } else {
2590                 sdhci_enable_irq_wakeups(host);
2591                 enable_irq_wake(host->irq);
2592         }
2593         return 0;
2594 }
2595
2596 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2597
2598 int sdhci_resume_host(struct sdhci_host *host)
2599 {
2600         int ret = 0;
2601
2602         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2603                 if (host->ops->enable_dma)
2604                         host->ops->enable_dma(host);
2605         }
2606
2607         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2608                 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2609                                   mmc_hostname(host->mmc), host);
2610                 if (ret)
2611                         return ret;
2612         } else {
2613                 sdhci_disable_irq_wakeups(host);
2614                 disable_irq_wake(host->irq);
2615         }
2616
2617         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2618             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2619                 /* Card keeps power but host controller does not */
2620                 sdhci_init(host, 0);
2621                 host->pwr = 0;
2622                 host->clock = 0;
2623                 sdhci_do_set_ios(host, &host->mmc->ios);
2624         } else {
2625                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2626                 mmiowb();
2627         }
2628
2629         sdhci_enable_card_detection(host);
2630
2631         if (host->ops->platform_resume)
2632                 host->ops->platform_resume(host);
2633
2634         /* Set the re-tuning expiration flag */
2635         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2636                 host->flags |= SDHCI_NEEDS_RETUNING;
2637
2638         return ret;
2639 }
2640
2641 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2642 #endif /* CONFIG_PM */
2643
2644 #ifdef CONFIG_PM_RUNTIME
2645
2646 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2647 {
2648         return pm_runtime_get_sync(host->mmc->parent);
2649 }
2650
2651 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2652 {
2653         pm_runtime_mark_last_busy(host->mmc->parent);
2654         return pm_runtime_put_autosuspend(host->mmc->parent);
2655 }
2656
2657 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2658 {
2659         if (host->runtime_suspended || host->bus_on)
2660                 return;
2661         host->bus_on = true;
2662         pm_runtime_get_noresume(host->mmc->parent);
2663 }
2664
2665 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2666 {
2667         if (host->runtime_suspended || !host->bus_on)
2668                 return;
2669         host->bus_on = false;
2670         pm_runtime_put_noidle(host->mmc->parent);
2671 }
2672
2673 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2674 {
2675         unsigned long flags;
2676         int ret = 0;
2677
2678         /* Disable tuning since we are suspending */
2679         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2680                 del_timer_sync(&host->tuning_timer);
2681                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2682         }
2683
2684         spin_lock_irqsave(&host->lock, flags);
2685         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2686         spin_unlock_irqrestore(&host->lock, flags);
2687
2688         synchronize_irq(host->irq);
2689
2690         spin_lock_irqsave(&host->lock, flags);
2691         host->runtime_suspended = true;
2692         spin_unlock_irqrestore(&host->lock, flags);
2693
2694         return ret;
2695 }
2696 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2697
2698 int sdhci_runtime_resume_host(struct sdhci_host *host)
2699 {
2700         unsigned long flags;
2701         int ret = 0, host_flags = host->flags;
2702
2703         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2704                 if (host->ops->enable_dma)
2705                         host->ops->enable_dma(host);
2706         }
2707
2708         sdhci_init(host, 0);
2709
2710         /* Force clock and power re-program */
2711         host->pwr = 0;
2712         host->clock = 0;
2713         sdhci_do_set_ios(host, &host->mmc->ios);
2714
2715         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2716         if ((host_flags & SDHCI_PV_ENABLED) &&
2717                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2718                 spin_lock_irqsave(&host->lock, flags);
2719                 sdhci_enable_preset_value(host, true);
2720                 spin_unlock_irqrestore(&host->lock, flags);
2721         }
2722
2723         /* Set the re-tuning expiration flag */
2724         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2725                 host->flags |= SDHCI_NEEDS_RETUNING;
2726
2727         spin_lock_irqsave(&host->lock, flags);
2728
2729         host->runtime_suspended = false;
2730
2731         /* Enable SDIO IRQ */
2732         if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2733                 sdhci_enable_sdio_irq_nolock(host, true);
2734
2735         /* Enable Card Detection */
2736         sdhci_enable_card_detection(host);
2737
2738         spin_unlock_irqrestore(&host->lock, flags);
2739
2740         return ret;
2741 }
2742 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2743
2744 #endif
2745
2746 /*****************************************************************************\
2747  *                                                                           *
2748  * Device allocation/registration                                            *
2749  *                                                                           *
2750 \*****************************************************************************/
2751
2752 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2753         size_t priv_size)
2754 {
2755         struct mmc_host *mmc;
2756         struct sdhci_host *host;
2757
2758         WARN_ON(dev == NULL);
2759
2760         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2761         if (!mmc)
2762                 return ERR_PTR(-ENOMEM);
2763
2764         host = mmc_priv(mmc);
2765         host->mmc = mmc;
2766
2767         return host;
2768 }
2769
2770 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2771
2772 int sdhci_add_host(struct sdhci_host *host)
2773 {
2774         struct mmc_host *mmc;
2775         u32 caps[2] = {0, 0};
2776         u32 max_current_caps;
2777         unsigned int ocr_avail;
2778         int ret;
2779
2780         WARN_ON(host == NULL);
2781         if (host == NULL)
2782                 return -EINVAL;
2783
2784         mmc = host->mmc;
2785
2786         if (debug_quirks)
2787                 host->quirks = debug_quirks;
2788         if (debug_quirks2)
2789                 host->quirks2 = debug_quirks2;
2790
2791         sdhci_reset(host, SDHCI_RESET_ALL);
2792
2793         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2794         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2795                                 >> SDHCI_SPEC_VER_SHIFT;
2796         if (host->version > SDHCI_SPEC_300) {
2797                 pr_err("%s: Unknown controller version (%d). "
2798                         "You may experience problems.\n", mmc_hostname(mmc),
2799                         host->version);
2800         }
2801
2802         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2803                 sdhci_readl(host, SDHCI_CAPABILITIES);
2804
2805         if (host->version >= SDHCI_SPEC_300)
2806                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2807                         host->caps1 :
2808                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2809
2810         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2811                 host->flags |= SDHCI_USE_SDMA;
2812         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2813                 DBG("Controller doesn't have SDMA capability\n");
2814         else
2815                 host->flags |= SDHCI_USE_SDMA;
2816
2817         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2818                 (host->flags & SDHCI_USE_SDMA)) {
2819                 DBG("Disabling DMA as it is marked broken\n");
2820                 host->flags &= ~SDHCI_USE_SDMA;
2821         }
2822
2823         if ((host->version >= SDHCI_SPEC_200) &&
2824                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2825                 host->flags |= SDHCI_USE_ADMA;
2826
2827         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2828                 (host->flags & SDHCI_USE_ADMA)) {
2829                 DBG("Disabling ADMA as it is marked broken\n");
2830                 host->flags &= ~SDHCI_USE_ADMA;
2831         }
2832
2833         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2834                 if (host->ops->enable_dma) {
2835                         if (host->ops->enable_dma(host)) {
2836                                 pr_warning("%s: No suitable DMA "
2837                                         "available. Falling back to PIO.\n",
2838                                         mmc_hostname(mmc));
2839                                 host->flags &=
2840                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2841                         }
2842                 }
2843         }
2844
2845         if (host->flags & SDHCI_USE_ADMA) {
2846                 /*
2847                  * We need to allocate descriptors for all sg entries
2848                  * (128) and potentially one alignment transfer for
2849                  * each of those entries.
2850                  */
2851                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2852                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2853                 if (!host->adma_desc || !host->align_buffer) {
2854                         kfree(host->adma_desc);
2855                         kfree(host->align_buffer);
2856                         pr_warning("%s: Unable to allocate ADMA "
2857                                 "buffers. Falling back to standard DMA.\n",
2858                                 mmc_hostname(mmc));
2859                         host->flags &= ~SDHCI_USE_ADMA;
2860                 }
2861         }
2862
2863         /*
2864          * If we use DMA, then it's up to the caller to set the DMA
2865          * mask, but PIO does not need the hw shim so we set a new
2866          * mask here in that case.
2867          */
2868         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2869                 host->dma_mask = DMA_BIT_MASK(64);
2870                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2871         }
2872
2873         if (host->version >= SDHCI_SPEC_300)
2874                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2875                         >> SDHCI_CLOCK_BASE_SHIFT;
2876         else
2877                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2878                         >> SDHCI_CLOCK_BASE_SHIFT;
2879
2880         host->max_clk *= 1000000;
2881         if (host->max_clk == 0 || host->quirks &
2882                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2883                 if (!host->ops->get_max_clock) {
2884                         pr_err("%s: Hardware doesn't specify base clock "
2885                                "frequency.\n", mmc_hostname(mmc));
2886                         return -ENODEV;
2887                 }
2888                 host->max_clk = host->ops->get_max_clock(host);
2889         }
2890
2891         /*
2892          * In case of Host Controller v3.00, find out whether clock
2893          * multiplier is supported.
2894          */
2895         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2896                         SDHCI_CLOCK_MUL_SHIFT;
2897
2898         /*
2899          * In case the value in Clock Multiplier is 0, then programmable
2900          * clock mode is not supported, otherwise the actual clock
2901          * multiplier is one more than the value of Clock Multiplier
2902          * in the Capabilities Register.
2903          */
2904         if (host->clk_mul)
2905                 host->clk_mul += 1;
2906
2907         /*
2908          * Set host parameters.
2909          */
2910         mmc->ops = &sdhci_ops;
2911         mmc->f_max = host->max_clk;
2912         if (host->ops->get_min_clock)
2913                 mmc->f_min = host->ops->get_min_clock(host);
2914         else if (host->version >= SDHCI_SPEC_300) {
2915                 if (host->clk_mul) {
2916                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2917                         mmc->f_max = host->max_clk * host->clk_mul;
2918                 } else
2919                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2920         } else
2921                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2922
2923         host->timeout_clk =
2924                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2925         if (host->timeout_clk == 0) {
2926                 if (host->ops->get_timeout_clock) {
2927                         host->timeout_clk = host->ops->get_timeout_clock(host);
2928                 } else if (!(host->quirks &
2929                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2930                         pr_err("%s: Hardware doesn't specify timeout clock "
2931                                "frequency.\n", mmc_hostname(mmc));
2932                         return -ENODEV;
2933                 }
2934         }
2935         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2936                 host->timeout_clk *= 1000;
2937
2938         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2939                 host->timeout_clk = mmc->f_max / 1000;
2940
2941         mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
2942
2943         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2944
2945         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2946                 host->flags |= SDHCI_AUTO_CMD12;
2947
2948         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2949         if ((host->version >= SDHCI_SPEC_300) &&
2950             ((host->flags & SDHCI_USE_ADMA) ||
2951              !(host->flags & SDHCI_USE_SDMA))) {
2952                 host->flags |= SDHCI_AUTO_CMD23;
2953                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2954         } else {
2955                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2956         }
2957
2958         /*
2959          * A controller may support 8-bit width, but the board itself
2960          * might not have the pins brought out.  Boards that support
2961          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2962          * their platform code before calling sdhci_add_host(), and we
2963          * won't assume 8-bit width for hosts without that CAP.
2964          */
2965         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2966                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2967
2968         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2969                 mmc->caps &= ~MMC_CAP_CMD23;
2970
2971         if (caps[0] & SDHCI_CAN_DO_HISPD)
2972                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2973
2974         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2975             !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2976                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2977
2978         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2979         host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
2980         if (IS_ERR_OR_NULL(host->vqmmc)) {
2981                 if (PTR_ERR(host->vqmmc) < 0) {
2982                         pr_info("%s: no vqmmc regulator found\n",
2983                                 mmc_hostname(mmc));
2984                         host->vqmmc = NULL;
2985                 }
2986         } else {
2987                 ret = regulator_enable(host->vqmmc);
2988                 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2989                         1950000))
2990                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2991                                         SDHCI_SUPPORT_SDR50 |
2992                                         SDHCI_SUPPORT_DDR50);
2993                 if (ret) {
2994                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2995                                 mmc_hostname(mmc), ret);
2996                         host->vqmmc = NULL;
2997                 }
2998         }
2999
3000         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3001                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3002                        SDHCI_SUPPORT_DDR50);
3003
3004         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3005         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3006                        SDHCI_SUPPORT_DDR50))
3007                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3008
3009         /* SDR104 supports also implies SDR50 support */
3010         if (caps[1] & SDHCI_SUPPORT_SDR104) {
3011                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3012                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3013                  * field can be promoted to support HS200.
3014                  */
3015                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3016                         mmc->caps2 |= MMC_CAP2_HS200;
3017         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3018                 mmc->caps |= MMC_CAP_UHS_SDR50;
3019
3020         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3021                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3022                 mmc->caps |= MMC_CAP_UHS_DDR50;
3023
3024         /* Does the host need tuning for SDR50? */
3025         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3026                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3027
3028         /* Does the host need tuning for SDR104 / HS200? */
3029         if (mmc->caps2 & MMC_CAP2_HS200)
3030                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3031
3032         /* Driver Type(s) (A, C, D) supported by the host */
3033         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3034                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3035         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3036                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3037         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3038                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3039
3040         /* Initial value for re-tuning timer count */
3041         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3042                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3043
3044         /*
3045          * In case Re-tuning Timer is not disabled, the actual value of
3046          * re-tuning timer will be 2 ^ (n - 1).
3047          */
3048         if (host->tuning_count)
3049                 host->tuning_count = 1 << (host->tuning_count - 1);
3050
3051         /* Re-tuning mode supported by the Host Controller */
3052         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3053                              SDHCI_RETUNING_MODE_SHIFT;
3054
3055         ocr_avail = 0;
3056
3057         host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
3058         if (IS_ERR_OR_NULL(host->vmmc)) {
3059                 if (PTR_ERR(host->vmmc) < 0) {
3060                         pr_info("%s: no vmmc regulator found\n",
3061                                 mmc_hostname(mmc));
3062                         host->vmmc = NULL;
3063                 }
3064         }
3065
3066 #ifdef CONFIG_REGULATOR
3067         /*
3068          * Voltage range check makes sense only if regulator reports
3069          * any voltage value.
3070          */
3071         if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
3072                 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3073                         3600000);
3074                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3075                         caps[0] &= ~SDHCI_CAN_VDD_330;
3076                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3077                         caps[0] &= ~SDHCI_CAN_VDD_300;
3078                 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3079                         1950000);
3080                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3081                         caps[0] &= ~SDHCI_CAN_VDD_180;
3082         }
3083 #endif /* CONFIG_REGULATOR */
3084
3085         /*
3086          * According to SD Host Controller spec v3.00, if the Host System
3087          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3088          * the value is meaningful only if Voltage Support in the Capabilities
3089          * register is set. The actual current value is 4 times the register
3090          * value.
3091          */
3092         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3093         if (!max_current_caps && host->vmmc) {
3094                 u32 curr = regulator_get_current_limit(host->vmmc);
3095                 if (curr > 0) {
3096
3097                         /* convert to SDHCI_MAX_CURRENT format */
3098                         curr = curr/1000;  /* convert to mA */
3099                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3100
3101                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3102                         max_current_caps =
3103                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3104                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3105                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3106                 }
3107         }
3108
3109         if (caps[0] & SDHCI_CAN_VDD_330) {
3110                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3111
3112                 mmc->max_current_330 = ((max_current_caps &
3113                                    SDHCI_MAX_CURRENT_330_MASK) >>
3114                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3115                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3116         }
3117         if (caps[0] & SDHCI_CAN_VDD_300) {
3118                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3119
3120                 mmc->max_current_300 = ((max_current_caps &
3121                                    SDHCI_MAX_CURRENT_300_MASK) >>
3122                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3123                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3124         }
3125         if (caps[0] & SDHCI_CAN_VDD_180) {
3126                 ocr_avail |= MMC_VDD_165_195;
3127
3128                 mmc->max_current_180 = ((max_current_caps &
3129                                    SDHCI_MAX_CURRENT_180_MASK) >>
3130                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3131                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3132         }
3133
3134         if (host->ocr_mask)
3135                 ocr_avail = host->ocr_mask;
3136
3137         mmc->ocr_avail = ocr_avail;
3138         mmc->ocr_avail_sdio = ocr_avail;
3139         if (host->ocr_avail_sdio)
3140                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3141         mmc->ocr_avail_sd = ocr_avail;
3142         if (host->ocr_avail_sd)
3143                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3144         else /* normal SD controllers don't support 1.8V */
3145                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3146         mmc->ocr_avail_mmc = ocr_avail;
3147         if (host->ocr_avail_mmc)
3148                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3149
3150         if (mmc->ocr_avail == 0) {
3151                 pr_err("%s: Hardware doesn't report any "
3152                         "support voltages.\n", mmc_hostname(mmc));
3153                 return -ENODEV;
3154         }
3155
3156         spin_lock_init(&host->lock);
3157
3158         /*
3159          * Maximum number of segments. Depends on if the hardware
3160          * can do scatter/gather or not.
3161          */
3162         if (host->flags & SDHCI_USE_ADMA)
3163                 mmc->max_segs = 128;
3164         else if (host->flags & SDHCI_USE_SDMA)
3165                 mmc->max_segs = 1;
3166         else /* PIO */
3167                 mmc->max_segs = 128;
3168
3169         /*
3170          * Maximum number of sectors in one transfer. Limited by DMA boundary
3171          * size (512KiB).
3172          */
3173         mmc->max_req_size = 524288;
3174
3175         /*
3176          * Maximum segment size. Could be one segment with the maximum number
3177          * of bytes. When doing hardware scatter/gather, each entry cannot
3178          * be larger than 64 KiB though.
3179          */
3180         if (host->flags & SDHCI_USE_ADMA) {
3181                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3182                         mmc->max_seg_size = 65535;
3183                 else
3184                         mmc->max_seg_size = 65536;
3185         } else {
3186                 mmc->max_seg_size = mmc->max_req_size;
3187         }
3188
3189         /*
3190          * Maximum block size. This varies from controller to controller and
3191          * is specified in the capabilities register.
3192          */
3193         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3194                 mmc->max_blk_size = 2;
3195         } else {
3196                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3197                                 SDHCI_MAX_BLOCK_SHIFT;
3198                 if (mmc->max_blk_size >= 3) {
3199                         pr_warning("%s: Invalid maximum block size, "
3200                                 "assuming 512 bytes\n", mmc_hostname(mmc));
3201                         mmc->max_blk_size = 0;
3202                 }
3203         }
3204
3205         mmc->max_blk_size = 512 << mmc->max_blk_size;
3206
3207         /*
3208          * Maximum block count.
3209          */
3210         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3211
3212         /*
3213          * Init tasklets.
3214          */
3215         tasklet_init(&host->card_tasklet,
3216                 sdhci_tasklet_card, (unsigned long)host);
3217         tasklet_init(&host->finish_tasklet,
3218                 sdhci_tasklet_finish, (unsigned long)host);
3219
3220         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3221
3222         if (host->version >= SDHCI_SPEC_300) {
3223                 init_waitqueue_head(&host->buf_ready_int);
3224
3225                 /* Initialize re-tuning timer */
3226                 init_timer(&host->tuning_timer);
3227                 host->tuning_timer.data = (unsigned long)host;
3228                 host->tuning_timer.function = sdhci_tuning_timer;
3229         }
3230
3231         sdhci_init(host, 0);
3232
3233         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3234                 mmc_hostname(mmc), host);
3235         if (ret) {
3236                 pr_err("%s: Failed to request IRQ %d: %d\n",
3237                        mmc_hostname(mmc), host->irq, ret);
3238                 goto untasklet;
3239         }
3240
3241 #ifdef CONFIG_MMC_DEBUG
3242         sdhci_dumpregs(host);
3243 #endif
3244
3245 #ifdef SDHCI_USE_LEDS_CLASS
3246         snprintf(host->led_name, sizeof(host->led_name),
3247                 "%s::", mmc_hostname(mmc));
3248         host->led.name = host->led_name;
3249         host->led.brightness = LED_OFF;
3250         host->led.default_trigger = mmc_hostname(mmc);
3251         host->led.brightness_set = sdhci_led_control;
3252
3253         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3254         if (ret) {
3255                 pr_err("%s: Failed to register LED device: %d\n",
3256                        mmc_hostname(mmc), ret);
3257                 goto reset;
3258         }
3259 #endif
3260
3261         mmiowb();
3262
3263         mmc_add_host(mmc);
3264
3265         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3266                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3267                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3268                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3269
3270         sdhci_enable_card_detection(host);
3271
3272         return 0;
3273
3274 #ifdef SDHCI_USE_LEDS_CLASS
3275 reset:
3276         sdhci_reset(host, SDHCI_RESET_ALL);
3277         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3278         free_irq(host->irq, host);
3279 #endif
3280 untasklet:
3281         tasklet_kill(&host->card_tasklet);
3282         tasklet_kill(&host->finish_tasklet);
3283
3284         return ret;
3285 }
3286
3287 EXPORT_SYMBOL_GPL(sdhci_add_host);
3288
3289 void sdhci_remove_host(struct sdhci_host *host, int dead)
3290 {
3291         unsigned long flags;
3292
3293         if (dead) {
3294                 spin_lock_irqsave(&host->lock, flags);
3295
3296                 host->flags |= SDHCI_DEVICE_DEAD;
3297
3298                 if (host->mrq) {
3299                         pr_err("%s: Controller removed during "
3300                                 " transfer!\n", mmc_hostname(host->mmc));
3301
3302                         host->mrq->cmd->error = -ENOMEDIUM;
3303                         tasklet_schedule(&host->finish_tasklet);
3304                 }
3305
3306                 spin_unlock_irqrestore(&host->lock, flags);
3307         }
3308
3309         sdhci_disable_card_detection(host);
3310
3311         mmc_remove_host(host->mmc);
3312
3313 #ifdef SDHCI_USE_LEDS_CLASS
3314         led_classdev_unregister(&host->led);
3315 #endif
3316
3317         if (!dead)
3318                 sdhci_reset(host, SDHCI_RESET_ALL);
3319
3320         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3321         free_irq(host->irq, host);
3322
3323         del_timer_sync(&host->timer);
3324
3325         tasklet_kill(&host->card_tasklet);
3326         tasklet_kill(&host->finish_tasklet);
3327
3328         if (host->vmmc) {
3329                 regulator_disable(host->vmmc);
3330                 regulator_put(host->vmmc);
3331         }
3332
3333         if (host->vqmmc) {
3334                 regulator_disable(host->vqmmc);
3335                 regulator_put(host->vqmmc);
3336         }
3337
3338         kfree(host->adma_desc);
3339         kfree(host->align_buffer);
3340
3341         host->adma_desc = NULL;
3342         host->align_buffer = NULL;
3343 }
3344
3345 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3346
3347 void sdhci_free_host(struct sdhci_host *host)
3348 {
3349         mmc_free_host(host->mmc);
3350 }
3351
3352 EXPORT_SYMBOL_GPL(sdhci_free_host);
3353
3354 /*****************************************************************************\
3355  *                                                                           *
3356  * Driver init/exit                                                          *
3357  *                                                                           *
3358 \*****************************************************************************/
3359
3360 static int __init sdhci_drv_init(void)
3361 {
3362         pr_info(DRIVER_NAME
3363                 ": Secure Digital Host Controller Interface driver\n");
3364         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3365
3366         return 0;
3367 }
3368
3369 static void __exit sdhci_drv_exit(void)
3370 {
3371 }
3372
3373 module_init(sdhci_drv_init);
3374 module_exit(sdhci_drv_exit);
3375
3376 module_param(debug_quirks, uint, 0444);
3377 module_param(debug_quirks2, uint, 0444);
3378
3379 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3380 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3381 MODULE_LICENSE("GPL");
3382
3383 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3384 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");