2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/slot-gpio.h>
35 #define DRIVER_NAME "sdhci"
37 #define DBG(f, x...) \
38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42 #define SDHCI_USE_LEDS_CLASS
45 #define MAX_TUNING_LOOP 40
47 #define ADMA_SIZE ((128 * 2 + 1) * 4)
49 static unsigned int debug_quirks = 0;
50 static unsigned int debug_quirks2;
52 static void sdhci_finish_data(struct sdhci_host *);
54 static void sdhci_finish_command(struct sdhci_host *);
55 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
56 static void sdhci_tuning_timer(unsigned long data);
57 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
59 #ifdef CONFIG_PM_RUNTIME
60 static int sdhci_runtime_pm_get(struct sdhci_host *host);
61 static int sdhci_runtime_pm_put(struct sdhci_host *host);
62 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
63 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
65 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
69 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
73 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
76 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
81 static void sdhci_dumpregs(struct sdhci_host *host)
83 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
84 mmc_hostname(host->mmc));
86 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
87 sdhci_readl(host, SDHCI_DMA_ADDRESS),
88 sdhci_readw(host, SDHCI_HOST_VERSION));
89 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
90 sdhci_readw(host, SDHCI_BLOCK_SIZE),
91 sdhci_readw(host, SDHCI_BLOCK_COUNT));
92 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
93 sdhci_readl(host, SDHCI_ARGUMENT),
94 sdhci_readw(host, SDHCI_TRANSFER_MODE));
95 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
96 sdhci_readl(host, SDHCI_PRESENT_STATE),
97 sdhci_readb(host, SDHCI_HOST_CONTROL));
98 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
99 sdhci_readb(host, SDHCI_POWER_CONTROL),
100 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
101 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
102 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
103 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
104 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
105 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
106 sdhci_readl(host, SDHCI_INT_STATUS));
107 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
108 sdhci_readl(host, SDHCI_INT_ENABLE),
109 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
110 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
111 sdhci_readw(host, SDHCI_ACMD12_ERR),
112 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
113 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
114 sdhci_readl(host, SDHCI_CAPABILITIES),
115 sdhci_readl(host, SDHCI_CAPABILITIES_1));
116 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
117 sdhci_readw(host, SDHCI_COMMAND),
118 sdhci_readl(host, SDHCI_MAX_CURRENT));
119 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
120 sdhci_readw(host, SDHCI_HOST_CONTROL2));
122 if (host->flags & SDHCI_USE_ADMA)
123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
127 pr_debug(DRIVER_NAME ": ===========================================\n");
130 /*****************************************************************************\
132 * Low level functions *
134 \*****************************************************************************/
136 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
140 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
141 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
145 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
148 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
149 SDHCI_INT_CARD_INSERT;
151 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
154 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
155 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
158 static void sdhci_enable_card_detection(struct sdhci_host *host)
160 sdhci_set_card_detection(host, true);
163 static void sdhci_disable_card_detection(struct sdhci_host *host)
165 sdhci_set_card_detection(host, false);
168 void sdhci_reset(struct sdhci_host *host, u8 mask)
170 unsigned long timeout;
172 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
174 if (mask & SDHCI_RESET_ALL) {
176 /* Reset-all turns off SD Bus Power */
177 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
178 sdhci_runtime_pm_bus_off(host);
181 /* Wait max 100 ms */
184 /* hw clears the bit when it's done */
185 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
187 pr_err("%s: Reset 0x%x never completed.\n",
188 mmc_hostname(host->mmc), (int)mask);
189 sdhci_dumpregs(host);
196 EXPORT_SYMBOL_GPL(sdhci_reset);
198 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
200 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
201 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
206 host->ops->reset(host, mask);
208 if (mask & SDHCI_RESET_ALL) {
209 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
210 if (host->ops->enable_dma)
211 host->ops->enable_dma(host);
214 /* Resetting the controller clears many */
215 host->preset_enabled = false;
219 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
221 static void sdhci_init(struct sdhci_host *host, int soft)
224 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
226 sdhci_do_reset(host, SDHCI_RESET_ALL);
228 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
229 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
230 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
231 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
234 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
235 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
238 /* force clock reconfiguration */
240 sdhci_set_ios(host->mmc, &host->mmc->ios);
244 static void sdhci_reinit(struct sdhci_host *host)
248 * Retuning stuffs are affected by different cards inserted and only
249 * applicable to UHS-I cards. So reset these fields to their initial
250 * value when card is removed.
252 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
253 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
255 del_timer_sync(&host->tuning_timer);
256 host->flags &= ~SDHCI_NEEDS_RETUNING;
257 host->mmc->max_blk_count =
258 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
260 sdhci_enable_card_detection(host);
263 static void sdhci_activate_led(struct sdhci_host *host)
267 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
268 ctrl |= SDHCI_CTRL_LED;
269 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
272 static void sdhci_deactivate_led(struct sdhci_host *host)
276 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
277 ctrl &= ~SDHCI_CTRL_LED;
278 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
281 #ifdef SDHCI_USE_LEDS_CLASS
282 static void sdhci_led_control(struct led_classdev *led,
283 enum led_brightness brightness)
285 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
288 spin_lock_irqsave(&host->lock, flags);
290 if (host->runtime_suspended)
293 if (brightness == LED_OFF)
294 sdhci_deactivate_led(host);
296 sdhci_activate_led(host);
298 spin_unlock_irqrestore(&host->lock, flags);
302 /*****************************************************************************\
306 \*****************************************************************************/
308 static void sdhci_read_block_pio(struct sdhci_host *host)
311 size_t blksize, len, chunk;
312 u32 uninitialized_var(scratch);
315 DBG("PIO reading\n");
317 blksize = host->data->blksz;
320 local_irq_save(flags);
323 if (!sg_miter_next(&host->sg_miter))
326 len = min(host->sg_miter.length, blksize);
329 host->sg_miter.consumed = len;
331 buf = host->sg_miter.addr;
335 scratch = sdhci_readl(host, SDHCI_BUFFER);
339 *buf = scratch & 0xFF;
348 sg_miter_stop(&host->sg_miter);
350 local_irq_restore(flags);
353 static void sdhci_write_block_pio(struct sdhci_host *host)
356 size_t blksize, len, chunk;
360 DBG("PIO writing\n");
362 blksize = host->data->blksz;
366 local_irq_save(flags);
369 if (!sg_miter_next(&host->sg_miter))
372 len = min(host->sg_miter.length, blksize);
375 host->sg_miter.consumed = len;
377 buf = host->sg_miter.addr;
380 scratch |= (u32)*buf << (chunk * 8);
386 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
387 sdhci_writel(host, scratch, SDHCI_BUFFER);
394 sg_miter_stop(&host->sg_miter);
396 local_irq_restore(flags);
399 static void sdhci_transfer_pio(struct sdhci_host *host)
405 if (host->blocks == 0)
408 if (host->data->flags & MMC_DATA_READ)
409 mask = SDHCI_DATA_AVAILABLE;
411 mask = SDHCI_SPACE_AVAILABLE;
414 * Some controllers (JMicron JMB38x) mess up the buffer bits
415 * for transfers < 4 bytes. As long as it is just one block,
416 * we can ignore the bits.
418 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
419 (host->data->blocks == 1))
422 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
423 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
426 if (host->data->flags & MMC_DATA_READ)
427 sdhci_read_block_pio(host);
429 sdhci_write_block_pio(host);
432 if (host->blocks == 0)
436 DBG("PIO transfer complete.\n");
439 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
441 local_irq_save(*flags);
442 return kmap_atomic(sg_page(sg)) + sg->offset;
445 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
447 kunmap_atomic(buffer);
448 local_irq_restore(*flags);
451 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
453 __le32 *dataddr = (__le32 __force *)(desc + 4);
454 __le16 *cmdlen = (__le16 __force *)desc;
456 /* SDHCI specification says ADMA descriptors should be 4 byte
457 * aligned, so using 16 or 32bit operations should be safe. */
459 cmdlen[0] = cpu_to_le16(cmd);
460 cmdlen[1] = cpu_to_le16(len);
462 dataddr[0] = cpu_to_le32(addr);
465 static int sdhci_adma_table_pre(struct sdhci_host *host,
466 struct mmc_data *data)
473 dma_addr_t align_addr;
476 struct scatterlist *sg;
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
486 if (data->flags & MMC_DATA_READ)
487 direction = DMA_FROM_DEVICE;
489 direction = DMA_TO_DEVICE;
491 host->align_addr = dma_map_single(mmc_dev(host->mmc),
492 host->align_buffer, 128 * 4, direction);
493 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
495 BUG_ON(host->align_addr & 0x3);
497 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
498 data->sg, data->sg_len, direction);
499 if (host->sg_count == 0)
502 desc = host->adma_desc;
503 align = host->align_buffer;
505 align_addr = host->align_addr;
507 for_each_sg(data->sg, sg, host->sg_count, i) {
508 addr = sg_dma_address(sg);
509 len = sg_dma_len(sg);
512 * The SDHCI specification states that ADMA
513 * addresses must be 32-bit aligned. If they
514 * aren't, then we use a bounce buffer for
515 * the (up to three) bytes that screw up the
518 offset = (4 - (addr & 0x3)) & 0x3;
520 if (data->flags & MMC_DATA_WRITE) {
521 buffer = sdhci_kmap_atomic(sg, &flags);
522 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
523 memcpy(align, buffer, offset);
524 sdhci_kunmap_atomic(buffer, &flags);
528 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
530 BUG_ON(offset > 65536);
544 sdhci_set_adma_desc(desc, addr, len, 0x21);
548 * If this triggers then we have a calculation bug
551 WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
554 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
556 * Mark the last descriptor as the terminating descriptor
558 if (desc != host->adma_desc) {
560 desc[0] |= 0x2; /* end */
564 * Add a terminating entry.
567 /* nop, end, valid */
568 sdhci_set_adma_desc(desc, 0, 0, 0x3);
572 * Resync align buffer as we might have changed it.
574 if (data->flags & MMC_DATA_WRITE) {
575 dma_sync_single_for_device(mmc_dev(host->mmc),
576 host->align_addr, 128 * 4, direction);
582 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
588 static void sdhci_adma_table_post(struct sdhci_host *host,
589 struct mmc_data *data)
593 struct scatterlist *sg;
600 if (data->flags & MMC_DATA_READ)
601 direction = DMA_FROM_DEVICE;
603 direction = DMA_TO_DEVICE;
605 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
608 /* Do a quick scan of the SG list for any unaligned mappings */
609 has_unaligned = false;
610 for_each_sg(data->sg, sg, host->sg_count, i)
611 if (sg_dma_address(sg) & 3) {
612 has_unaligned = true;
616 if (has_unaligned && data->flags & MMC_DATA_READ) {
617 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
618 data->sg_len, direction);
620 align = host->align_buffer;
622 for_each_sg(data->sg, sg, host->sg_count, i) {
623 if (sg_dma_address(sg) & 0x3) {
624 size = 4 - (sg_dma_address(sg) & 0x3);
626 buffer = sdhci_kmap_atomic(sg, &flags);
627 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
628 memcpy(buffer, align, size);
629 sdhci_kunmap_atomic(buffer, &flags);
636 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
637 data->sg_len, direction);
640 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
643 struct mmc_data *data = cmd->data;
644 unsigned target_timeout, current_timeout;
647 * If the host controller provides us with an incorrect timeout
648 * value, just skip the check and use 0xE. The hardware may take
649 * longer to time out, but that's much better than having a too-short
652 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
655 /* Unspecified timeout, assume max */
656 if (!data && !cmd->busy_timeout)
661 target_timeout = cmd->busy_timeout * 1000;
663 target_timeout = data->timeout_ns / 1000;
665 target_timeout += data->timeout_clks / host->clock;
669 * Figure out needed cycles.
670 * We do this in steps in order to fit inside a 32 bit int.
671 * The first step is the minimum timeout, which will have a
672 * minimum resolution of 6 bits:
673 * (1) 2^13*1000 > 2^22,
674 * (2) host->timeout_clk < 2^16
679 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
680 while (current_timeout < target_timeout) {
682 current_timeout <<= 1;
688 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
689 mmc_hostname(host->mmc), count, cmd->opcode);
696 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
698 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
699 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
701 if (host->flags & SDHCI_REQ_USE_DMA)
702 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
704 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
706 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
707 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
710 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
714 struct mmc_data *data = cmd->data;
719 if (data || (cmd->flags & MMC_RSP_BUSY)) {
720 count = sdhci_calc_timeout(host, cmd);
721 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
728 BUG_ON(data->blksz * data->blocks > 524288);
729 BUG_ON(data->blksz > host->mmc->max_blk_size);
730 BUG_ON(data->blocks > 65535);
733 host->data_early = 0;
734 host->data->bytes_xfered = 0;
736 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
737 host->flags |= SDHCI_REQ_USE_DMA;
740 * FIXME: This doesn't account for merging when mapping the
743 if (host->flags & SDHCI_REQ_USE_DMA) {
745 struct scatterlist *sg;
748 if (host->flags & SDHCI_USE_ADMA) {
749 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
752 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
756 if (unlikely(broken)) {
757 for_each_sg(data->sg, sg, data->sg_len, i) {
758 if (sg->length & 0x3) {
759 DBG("Reverting to PIO because of "
760 "transfer size (%d)\n",
762 host->flags &= ~SDHCI_REQ_USE_DMA;
770 * The assumption here being that alignment is the same after
771 * translation to device address space.
773 if (host->flags & SDHCI_REQ_USE_DMA) {
775 struct scatterlist *sg;
778 if (host->flags & SDHCI_USE_ADMA) {
780 * As we use 3 byte chunks to work around
781 * alignment problems, we need to check this
784 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
787 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
791 if (unlikely(broken)) {
792 for_each_sg(data->sg, sg, data->sg_len, i) {
793 if (sg->offset & 0x3) {
794 DBG("Reverting to PIO because of "
796 host->flags &= ~SDHCI_REQ_USE_DMA;
803 if (host->flags & SDHCI_REQ_USE_DMA) {
804 if (host->flags & SDHCI_USE_ADMA) {
805 ret = sdhci_adma_table_pre(host, data);
808 * This only happens when someone fed
809 * us an invalid request.
812 host->flags &= ~SDHCI_REQ_USE_DMA;
814 sdhci_writel(host, host->adma_addr,
820 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
821 data->sg, data->sg_len,
822 (data->flags & MMC_DATA_READ) ?
827 * This only happens when someone fed
828 * us an invalid request.
831 host->flags &= ~SDHCI_REQ_USE_DMA;
833 WARN_ON(sg_cnt != 1);
834 sdhci_writel(host, sg_dma_address(data->sg),
841 * Always adjust the DMA selection as some controllers
842 * (e.g. JMicron) can't do PIO properly when the selection
845 if (host->version >= SDHCI_SPEC_200) {
846 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
847 ctrl &= ~SDHCI_CTRL_DMA_MASK;
848 if ((host->flags & SDHCI_REQ_USE_DMA) &&
849 (host->flags & SDHCI_USE_ADMA))
850 ctrl |= SDHCI_CTRL_ADMA32;
852 ctrl |= SDHCI_CTRL_SDMA;
853 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
856 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
859 flags = SG_MITER_ATOMIC;
860 if (host->data->flags & MMC_DATA_READ)
861 flags |= SG_MITER_TO_SG;
863 flags |= SG_MITER_FROM_SG;
864 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
865 host->blocks = data->blocks;
868 sdhci_set_transfer_irqs(host);
870 /* Set the DMA boundary value and block size */
871 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
872 data->blksz), SDHCI_BLOCK_SIZE);
873 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
876 static void sdhci_set_transfer_mode(struct sdhci_host *host,
877 struct mmc_command *cmd)
880 struct mmc_data *data = cmd->data;
883 /* clear Auto CMD settings for no data CMDs */
884 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
885 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
886 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
890 WARN_ON(!host->data);
892 mode = SDHCI_TRNS_BLK_CNT_EN;
893 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
894 mode |= SDHCI_TRNS_MULTI;
896 * If we are sending CMD23, CMD12 never gets sent
897 * on successful completion (so no Auto-CMD12).
899 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
900 mode |= SDHCI_TRNS_AUTO_CMD12;
901 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
902 mode |= SDHCI_TRNS_AUTO_CMD23;
903 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
907 if (data->flags & MMC_DATA_READ)
908 mode |= SDHCI_TRNS_READ;
909 if (host->flags & SDHCI_REQ_USE_DMA)
910 mode |= SDHCI_TRNS_DMA;
912 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
915 static void sdhci_finish_data(struct sdhci_host *host)
917 struct mmc_data *data;
924 if (host->flags & SDHCI_REQ_USE_DMA) {
925 if (host->flags & SDHCI_USE_ADMA)
926 sdhci_adma_table_post(host, data);
928 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
929 data->sg_len, (data->flags & MMC_DATA_READ) ?
930 DMA_FROM_DEVICE : DMA_TO_DEVICE);
935 * The specification states that the block count register must
936 * be updated, but it does not specify at what point in the
937 * data flow. That makes the register entirely useless to read
938 * back so we have to assume that nothing made it to the card
939 * in the event of an error.
942 data->bytes_xfered = 0;
944 data->bytes_xfered = data->blksz * data->blocks;
947 * Need to send CMD12 if -
948 * a) open-ended multiblock transfer (no CMD23)
949 * b) error in multiblock transfer
956 * The controller needs a reset of internal state machines
957 * upon error conditions.
960 sdhci_do_reset(host, SDHCI_RESET_CMD);
961 sdhci_do_reset(host, SDHCI_RESET_DATA);
964 sdhci_send_command(host, data->stop);
966 tasklet_schedule(&host->finish_tasklet);
969 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
973 unsigned long timeout;
980 mask = SDHCI_CMD_INHIBIT;
981 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
982 mask |= SDHCI_DATA_INHIBIT;
984 /* We shouldn't wait for data inihibit for stop commands, even
985 though they might use busy signaling */
986 if (host->mrq->data && (cmd == host->mrq->data->stop))
987 mask &= ~SDHCI_DATA_INHIBIT;
989 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
991 pr_err("%s: Controller never released "
992 "inhibit bit(s).\n", mmc_hostname(host->mmc));
993 sdhci_dumpregs(host);
995 tasklet_schedule(&host->finish_tasklet);
1003 if (!cmd->data && cmd->busy_timeout > 9000)
1004 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1007 mod_timer(&host->timer, timeout);
1011 sdhci_prepare_data(host, cmd);
1013 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1015 sdhci_set_transfer_mode(host, cmd);
1017 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1018 pr_err("%s: Unsupported response type!\n",
1019 mmc_hostname(host->mmc));
1020 cmd->error = -EINVAL;
1021 tasklet_schedule(&host->finish_tasklet);
1025 if (!(cmd->flags & MMC_RSP_PRESENT))
1026 flags = SDHCI_CMD_RESP_NONE;
1027 else if (cmd->flags & MMC_RSP_136)
1028 flags = SDHCI_CMD_RESP_LONG;
1029 else if (cmd->flags & MMC_RSP_BUSY)
1030 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1032 flags = SDHCI_CMD_RESP_SHORT;
1034 if (cmd->flags & MMC_RSP_CRC)
1035 flags |= SDHCI_CMD_CRC;
1036 if (cmd->flags & MMC_RSP_OPCODE)
1037 flags |= SDHCI_CMD_INDEX;
1039 /* CMD19 is special in that the Data Present Select should be set */
1040 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1041 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1042 flags |= SDHCI_CMD_DATA;
1044 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1046 EXPORT_SYMBOL_GPL(sdhci_send_command);
1048 static void sdhci_finish_command(struct sdhci_host *host)
1052 BUG_ON(host->cmd == NULL);
1054 if (host->cmd->flags & MMC_RSP_PRESENT) {
1055 if (host->cmd->flags & MMC_RSP_136) {
1056 /* CRC is stripped so we need to do some shifting. */
1057 for (i = 0;i < 4;i++) {
1058 host->cmd->resp[i] = sdhci_readl(host,
1059 SDHCI_RESPONSE + (3-i)*4) << 8;
1061 host->cmd->resp[i] |=
1063 SDHCI_RESPONSE + (3-i)*4-1);
1066 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1070 host->cmd->error = 0;
1072 /* Finished CMD23, now send actual command. */
1073 if (host->cmd == host->mrq->sbc) {
1075 sdhci_send_command(host, host->mrq->cmd);
1078 /* Processed actual command. */
1079 if (host->data && host->data_early)
1080 sdhci_finish_data(host);
1082 if (!host->cmd->data)
1083 tasklet_schedule(&host->finish_tasklet);
1089 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1093 switch (host->timing) {
1094 case MMC_TIMING_UHS_SDR12:
1095 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1097 case MMC_TIMING_UHS_SDR25:
1098 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1100 case MMC_TIMING_UHS_SDR50:
1101 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1103 case MMC_TIMING_UHS_SDR104:
1104 case MMC_TIMING_MMC_HS200:
1105 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1107 case MMC_TIMING_UHS_DDR50:
1108 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1111 pr_warn("%s: Invalid UHS-I mode selected\n",
1112 mmc_hostname(host->mmc));
1113 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1119 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1121 int div = 0; /* Initialized for compiler warning */
1122 int real_div = div, clk_mul = 1;
1124 unsigned long timeout;
1126 host->mmc->actual_clock = 0;
1128 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1133 if (host->version >= SDHCI_SPEC_300) {
1134 if (host->preset_enabled) {
1137 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1138 pre_val = sdhci_get_preset_value(host);
1139 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1140 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1141 if (host->clk_mul &&
1142 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1143 clk = SDHCI_PROG_CLOCK_MODE;
1145 clk_mul = host->clk_mul;
1147 real_div = max_t(int, 1, div << 1);
1153 * Check if the Host Controller supports Programmable Clock
1156 if (host->clk_mul) {
1157 for (div = 1; div <= 1024; div++) {
1158 if ((host->max_clk * host->clk_mul / div)
1163 * Set Programmable Clock Mode in the Clock
1166 clk = SDHCI_PROG_CLOCK_MODE;
1168 clk_mul = host->clk_mul;
1171 /* Version 3.00 divisors must be a multiple of 2. */
1172 if (host->max_clk <= clock)
1175 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1177 if ((host->max_clk / div) <= clock)
1185 /* Version 2.00 divisors must be a power of 2. */
1186 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1187 if ((host->max_clk / div) <= clock)
1196 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1198 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1199 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1200 << SDHCI_DIVIDER_HI_SHIFT;
1201 clk |= SDHCI_CLOCK_INT_EN;
1202 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1204 /* Wait max 20 ms */
1206 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1207 & SDHCI_CLOCK_INT_STABLE)) {
1209 pr_err("%s: Internal clock never "
1210 "stabilised.\n", mmc_hostname(host->mmc));
1211 sdhci_dumpregs(host);
1218 clk |= SDHCI_CLOCK_CARD_EN;
1219 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1221 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1223 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1228 if (mode != MMC_POWER_OFF) {
1230 case MMC_VDD_165_195:
1231 pwr = SDHCI_POWER_180;
1235 pwr = SDHCI_POWER_300;
1239 pwr = SDHCI_POWER_330;
1246 if (host->pwr == pwr)
1252 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1253 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1254 sdhci_runtime_pm_bus_off(host);
1258 * Spec says that we should clear the power reg before setting
1259 * a new value. Some controllers don't seem to like this though.
1261 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1262 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1265 * At least the Marvell CaFe chip gets confused if we set the
1266 * voltage and set turn on power at the same time, so set the
1269 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1270 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1272 pwr |= SDHCI_POWER_ON;
1274 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1276 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1277 sdhci_runtime_pm_bus_on(host);
1280 * Some controllers need an extra 10ms delay of 10ms before
1281 * they can apply clock after applying power
1283 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1288 spin_unlock_irq(&host->lock);
1289 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd);
1290 spin_lock_irq(&host->lock);
1294 /*****************************************************************************\
1298 \*****************************************************************************/
1300 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1302 struct sdhci_host *host;
1304 unsigned long flags;
1307 host = mmc_priv(mmc);
1309 sdhci_runtime_pm_get(host);
1311 spin_lock_irqsave(&host->lock, flags);
1313 WARN_ON(host->mrq != NULL);
1315 #ifndef SDHCI_USE_LEDS_CLASS
1316 sdhci_activate_led(host);
1320 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1321 * requests if Auto-CMD12 is enabled.
1323 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1325 mrq->data->stop = NULL;
1333 * Firstly check card presence from cd-gpio. The return could
1334 * be one of the following possibilities:
1335 * negative: cd-gpio is not available
1336 * zero: cd-gpio is used, and card is removed
1337 * one: cd-gpio is used, and card is present
1339 present = mmc_gpio_get_cd(host->mmc);
1341 /* If polling, assume that the card is always present. */
1342 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1345 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1349 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1350 host->mrq->cmd->error = -ENOMEDIUM;
1351 tasklet_schedule(&host->finish_tasklet);
1355 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1357 * Check if the re-tuning timer has already expired and there
1358 * is no on-going data transfer. If so, we need to execute
1359 * tuning procedure before sending command.
1361 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1362 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1364 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1366 mmc->card->type == MMC_TYPE_MMC ?
1367 MMC_SEND_TUNING_BLOCK_HS200 :
1368 MMC_SEND_TUNING_BLOCK;
1370 /* Here we need to set the host->mrq to NULL,
1371 * in case the pending finish_tasklet
1372 * finishes it incorrectly.
1376 spin_unlock_irqrestore(&host->lock, flags);
1377 sdhci_execute_tuning(mmc, tuning_opcode);
1378 spin_lock_irqsave(&host->lock, flags);
1380 /* Restore original mmc_request structure */
1385 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1386 sdhci_send_command(host, mrq->sbc);
1388 sdhci_send_command(host, mrq->cmd);
1392 spin_unlock_irqrestore(&host->lock, flags);
1395 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1399 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1400 if (width == MMC_BUS_WIDTH_8) {
1401 ctrl &= ~SDHCI_CTRL_4BITBUS;
1402 if (host->version >= SDHCI_SPEC_300)
1403 ctrl |= SDHCI_CTRL_8BITBUS;
1405 if (host->version >= SDHCI_SPEC_300)
1406 ctrl &= ~SDHCI_CTRL_8BITBUS;
1407 if (width == MMC_BUS_WIDTH_4)
1408 ctrl |= SDHCI_CTRL_4BITBUS;
1410 ctrl &= ~SDHCI_CTRL_4BITBUS;
1412 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1414 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1416 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1420 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1421 /* Select Bus Speed Mode for host */
1422 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1423 if ((timing == MMC_TIMING_MMC_HS200) ||
1424 (timing == MMC_TIMING_UHS_SDR104))
1425 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1426 else if (timing == MMC_TIMING_UHS_SDR12)
1427 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1428 else if (timing == MMC_TIMING_UHS_SDR25)
1429 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1430 else if (timing == MMC_TIMING_UHS_SDR50)
1431 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1432 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1433 (timing == MMC_TIMING_MMC_DDR52))
1434 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1435 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1437 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1439 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1441 unsigned long flags;
1444 spin_lock_irqsave(&host->lock, flags);
1446 if (host->flags & SDHCI_DEVICE_DEAD) {
1447 spin_unlock_irqrestore(&host->lock, flags);
1448 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1449 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1454 * Reset the chip on each power off.
1455 * Should clear out any weird states.
1457 if (ios->power_mode == MMC_POWER_OFF) {
1458 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1462 if (host->version >= SDHCI_SPEC_300 &&
1463 (ios->power_mode == MMC_POWER_UP) &&
1464 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1465 sdhci_enable_preset_value(host, false);
1467 if (!ios->clock || ios->clock != host->clock) {
1468 host->ops->set_clock(host, ios->clock);
1469 host->clock = ios->clock;
1472 sdhci_set_power(host, ios->power_mode, ios->vdd);
1474 if (host->ops->platform_send_init_74_clocks)
1475 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1477 host->ops->set_bus_width(host, ios->bus_width);
1479 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1481 if ((ios->timing == MMC_TIMING_SD_HS ||
1482 ios->timing == MMC_TIMING_MMC_HS)
1483 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1484 ctrl |= SDHCI_CTRL_HISPD;
1486 ctrl &= ~SDHCI_CTRL_HISPD;
1488 if (host->version >= SDHCI_SPEC_300) {
1491 /* In case of UHS-I modes, set High Speed Enable */
1492 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1493 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1494 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1495 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1496 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1497 (ios->timing == MMC_TIMING_UHS_SDR25))
1498 ctrl |= SDHCI_CTRL_HISPD;
1500 if (!host->preset_enabled) {
1501 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1503 * We only need to set Driver Strength if the
1504 * preset value enable is not set.
1506 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1507 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1508 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1509 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1510 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1511 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1513 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1516 * According to SDHC Spec v3.00, if the Preset Value
1517 * Enable in the Host Control 2 register is set, we
1518 * need to reset SD Clock Enable before changing High
1519 * Speed Enable to avoid generating clock gliches.
1522 /* Reset SD Clock Enable */
1523 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1524 clk &= ~SDHCI_CLOCK_CARD_EN;
1525 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1527 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1529 /* Re-enable SD Clock */
1530 host->ops->set_clock(host, host->clock);
1534 /* Reset SD Clock Enable */
1535 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1536 clk &= ~SDHCI_CLOCK_CARD_EN;
1537 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1539 host->ops->set_uhs_signaling(host, ios->timing);
1540 host->timing = ios->timing;
1542 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1543 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1544 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1545 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1546 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1547 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1550 sdhci_enable_preset_value(host, true);
1551 preset = sdhci_get_preset_value(host);
1552 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1553 >> SDHCI_PRESET_DRV_SHIFT;
1556 /* Re-enable SD Clock */
1557 host->ops->set_clock(host, host->clock);
1559 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1562 * Some (ENE) controllers go apeshit on some ios operation,
1563 * signalling timeout and CRC errors even on CMD0. Resetting
1564 * it on each ios seems to solve the problem.
1566 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1567 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1570 spin_unlock_irqrestore(&host->lock, flags);
1573 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1575 struct sdhci_host *host = mmc_priv(mmc);
1577 sdhci_runtime_pm_get(host);
1578 sdhci_do_set_ios(host, ios);
1579 sdhci_runtime_pm_put(host);
1582 static int sdhci_do_get_cd(struct sdhci_host *host)
1584 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1586 if (host->flags & SDHCI_DEVICE_DEAD)
1589 /* If polling/nonremovable, assume that the card is always present. */
1590 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1591 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1594 /* Try slot gpio detect */
1595 if (!IS_ERR_VALUE(gpio_cd))
1598 /* Host native card detect */
1599 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1602 static int sdhci_get_cd(struct mmc_host *mmc)
1604 struct sdhci_host *host = mmc_priv(mmc);
1607 sdhci_runtime_pm_get(host);
1608 ret = sdhci_do_get_cd(host);
1609 sdhci_runtime_pm_put(host);
1613 static int sdhci_check_ro(struct sdhci_host *host)
1615 unsigned long flags;
1618 spin_lock_irqsave(&host->lock, flags);
1620 if (host->flags & SDHCI_DEVICE_DEAD)
1622 else if (host->ops->get_ro)
1623 is_readonly = host->ops->get_ro(host);
1625 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1626 & SDHCI_WRITE_PROTECT);
1628 spin_unlock_irqrestore(&host->lock, flags);
1630 /* This quirk needs to be replaced by a callback-function later */
1631 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1632 !is_readonly : is_readonly;
1635 #define SAMPLE_COUNT 5
1637 static int sdhci_do_get_ro(struct sdhci_host *host)
1641 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1642 return sdhci_check_ro(host);
1645 for (i = 0; i < SAMPLE_COUNT; i++) {
1646 if (sdhci_check_ro(host)) {
1647 if (++ro_count > SAMPLE_COUNT / 2)
1655 static void sdhci_hw_reset(struct mmc_host *mmc)
1657 struct sdhci_host *host = mmc_priv(mmc);
1659 if (host->ops && host->ops->hw_reset)
1660 host->ops->hw_reset(host);
1663 static int sdhci_get_ro(struct mmc_host *mmc)
1665 struct sdhci_host *host = mmc_priv(mmc);
1668 sdhci_runtime_pm_get(host);
1669 ret = sdhci_do_get_ro(host);
1670 sdhci_runtime_pm_put(host);
1674 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1676 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1678 host->ier |= SDHCI_INT_CARD_INT;
1680 host->ier &= ~SDHCI_INT_CARD_INT;
1682 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1683 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1688 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1690 struct sdhci_host *host = mmc_priv(mmc);
1691 unsigned long flags;
1693 sdhci_runtime_pm_get(host);
1695 spin_lock_irqsave(&host->lock, flags);
1697 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1699 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1701 sdhci_enable_sdio_irq_nolock(host, enable);
1702 spin_unlock_irqrestore(&host->lock, flags);
1704 sdhci_runtime_pm_put(host);
1707 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1708 struct mmc_ios *ios)
1714 * Signal Voltage Switching is only applicable for Host Controllers
1717 if (host->version < SDHCI_SPEC_300)
1720 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1722 switch (ios->signal_voltage) {
1723 case MMC_SIGNAL_VOLTAGE_330:
1724 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1725 ctrl &= ~SDHCI_CTRL_VDD_180;
1726 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1729 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1731 pr_warning("%s: Switching to 3.3V signalling voltage "
1732 " failed\n", mmc_hostname(host->mmc));
1737 usleep_range(5000, 5500);
1739 /* 3.3V regulator output should be stable within 5 ms */
1740 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1741 if (!(ctrl & SDHCI_CTRL_VDD_180))
1744 pr_warning("%s: 3.3V regulator output did not became stable\n",
1745 mmc_hostname(host->mmc));
1748 case MMC_SIGNAL_VOLTAGE_180:
1750 ret = regulator_set_voltage(host->vqmmc,
1753 pr_warning("%s: Switching to 1.8V signalling voltage "
1754 " failed\n", mmc_hostname(host->mmc));
1760 * Enable 1.8V Signal Enable in the Host Control2
1763 ctrl |= SDHCI_CTRL_VDD_180;
1764 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1767 usleep_range(5000, 5500);
1769 /* 1.8V regulator output should be stable within 5 ms */
1770 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1771 if (ctrl & SDHCI_CTRL_VDD_180)
1774 pr_warning("%s: 1.8V regulator output did not became stable\n",
1775 mmc_hostname(host->mmc));
1778 case MMC_SIGNAL_VOLTAGE_120:
1780 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1782 pr_warning("%s: Switching to 1.2V signalling voltage "
1783 " failed\n", mmc_hostname(host->mmc));
1789 /* No signal voltage switch required */
1794 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1795 struct mmc_ios *ios)
1797 struct sdhci_host *host = mmc_priv(mmc);
1800 if (host->version < SDHCI_SPEC_300)
1802 sdhci_runtime_pm_get(host);
1803 err = sdhci_do_start_signal_voltage_switch(host, ios);
1804 sdhci_runtime_pm_put(host);
1808 static int sdhci_card_busy(struct mmc_host *mmc)
1810 struct sdhci_host *host = mmc_priv(mmc);
1813 sdhci_runtime_pm_get(host);
1814 /* Check whether DAT[3:0] is 0000 */
1815 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1816 sdhci_runtime_pm_put(host);
1818 return !(present_state & SDHCI_DATA_LVL_MASK);
1821 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1823 struct sdhci_host *host = mmc_priv(mmc);
1825 int tuning_loop_counter = MAX_TUNING_LOOP;
1826 unsigned long timeout;
1828 unsigned long flags;
1830 sdhci_runtime_pm_get(host);
1831 spin_lock_irqsave(&host->lock, flags);
1834 * The Host Controller needs tuning only in case of SDR104 mode
1835 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1836 * Capabilities register.
1837 * If the Host Controller supports the HS200 mode then the
1838 * tuning function has to be executed.
1840 switch (host->timing) {
1841 case MMC_TIMING_MMC_HS200:
1842 case MMC_TIMING_UHS_SDR104:
1845 case MMC_TIMING_UHS_SDR50:
1846 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1847 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1852 spin_unlock_irqrestore(&host->lock, flags);
1853 sdhci_runtime_pm_put(host);
1857 if (host->ops->platform_execute_tuning) {
1858 spin_unlock_irqrestore(&host->lock, flags);
1859 err = host->ops->platform_execute_tuning(host, opcode);
1860 sdhci_runtime_pm_put(host);
1864 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1865 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1866 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1869 * As per the Host Controller spec v3.00, tuning command
1870 * generates Buffer Read Ready interrupt, so enable that.
1872 * Note: The spec clearly says that when tuning sequence
1873 * is being performed, the controller does not generate
1874 * interrupts other than Buffer Read Ready interrupt. But
1875 * to make sure we don't hit a controller bug, we _only_
1876 * enable Buffer Read Ready interrupt here.
1878 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1879 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1882 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1883 * of loops reaches 40 times or a timeout of 150ms occurs.
1887 struct mmc_command cmd = {0};
1888 struct mmc_request mrq = {NULL};
1890 if (!tuning_loop_counter && !timeout)
1893 cmd.opcode = opcode;
1895 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1904 * In response to CMD19, the card sends 64 bytes of tuning
1905 * block to the Host Controller. So we set the block size
1908 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1909 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1910 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1912 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1913 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1916 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1921 * The tuning block is sent by the card to the host controller.
1922 * So we set the TRNS_READ bit in the Transfer Mode register.
1923 * This also takes care of setting DMA Enable and Multi Block
1924 * Select in the same register to 0.
1926 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1928 sdhci_send_command(host, &cmd);
1933 spin_unlock_irqrestore(&host->lock, flags);
1934 /* Wait for Buffer Read Ready interrupt */
1935 wait_event_interruptible_timeout(host->buf_ready_int,
1936 (host->tuning_done == 1),
1937 msecs_to_jiffies(50));
1938 spin_lock_irqsave(&host->lock, flags);
1940 if (!host->tuning_done) {
1941 pr_info(DRIVER_NAME ": Timeout waiting for "
1942 "Buffer Read Ready interrupt during tuning "
1943 "procedure, falling back to fixed sampling "
1945 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1946 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1947 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1948 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1954 host->tuning_done = 0;
1956 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1957 tuning_loop_counter--;
1960 /* eMMC spec does not require a delay between tuning cycles */
1961 if (opcode == MMC_SEND_TUNING_BLOCK)
1963 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1966 * The Host Driver has exhausted the maximum number of loops allowed,
1967 * so use fixed sampling frequency.
1969 if (!tuning_loop_counter || !timeout) {
1970 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1971 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1974 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1975 pr_info(DRIVER_NAME ": Tuning procedure"
1976 " failed, falling back to fixed sampling"
1984 * If this is the very first time we are here, we start the retuning
1985 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1986 * flag won't be set, we check this condition before actually starting
1989 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1990 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1991 host->flags |= SDHCI_USING_RETUNING_TIMER;
1992 mod_timer(&host->tuning_timer, jiffies +
1993 host->tuning_count * HZ);
1994 /* Tuning mode 1 limits the maximum data length to 4MB */
1995 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1996 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
1997 host->flags &= ~SDHCI_NEEDS_RETUNING;
1998 /* Reload the new initial value for timer */
1999 mod_timer(&host->tuning_timer, jiffies +
2000 host->tuning_count * HZ);
2004 * In case tuning fails, host controllers which support re-tuning can
2005 * try tuning again at a later time, when the re-tuning timer expires.
2006 * So for these controllers, we return 0. Since there might be other
2007 * controllers who do not have this capability, we return error for
2008 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2009 * a retuning timer to do the retuning for the card.
2011 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2014 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2015 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2016 spin_unlock_irqrestore(&host->lock, flags);
2017 sdhci_runtime_pm_put(host);
2023 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2025 /* Host Controller v3.00 defines preset value registers */
2026 if (host->version < SDHCI_SPEC_300)
2030 * We only enable or disable Preset Value if they are not already
2031 * enabled or disabled respectively. Otherwise, we bail out.
2033 if (host->preset_enabled != enable) {
2034 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2037 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2039 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2041 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2044 host->flags |= SDHCI_PV_ENABLED;
2046 host->flags &= ~SDHCI_PV_ENABLED;
2048 host->preset_enabled = enable;
2052 static void sdhci_card_event(struct mmc_host *mmc)
2054 struct sdhci_host *host = mmc_priv(mmc);
2055 unsigned long flags;
2057 /* First check if client has provided their own card event */
2058 if (host->ops->card_event)
2059 host->ops->card_event(host);
2061 spin_lock_irqsave(&host->lock, flags);
2063 /* Check host->mrq first in case we are runtime suspended */
2064 if (host->mrq && !sdhci_do_get_cd(host)) {
2065 pr_err("%s: Card removed during transfer!\n",
2066 mmc_hostname(host->mmc));
2067 pr_err("%s: Resetting controller.\n",
2068 mmc_hostname(host->mmc));
2070 sdhci_do_reset(host, SDHCI_RESET_CMD);
2071 sdhci_do_reset(host, SDHCI_RESET_DATA);
2073 host->mrq->cmd->error = -ENOMEDIUM;
2074 tasklet_schedule(&host->finish_tasklet);
2077 spin_unlock_irqrestore(&host->lock, flags);
2080 static const struct mmc_host_ops sdhci_ops = {
2081 .request = sdhci_request,
2082 .set_ios = sdhci_set_ios,
2083 .get_cd = sdhci_get_cd,
2084 .get_ro = sdhci_get_ro,
2085 .hw_reset = sdhci_hw_reset,
2086 .enable_sdio_irq = sdhci_enable_sdio_irq,
2087 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2088 .execute_tuning = sdhci_execute_tuning,
2089 .card_event = sdhci_card_event,
2090 .card_busy = sdhci_card_busy,
2093 /*****************************************************************************\
2097 \*****************************************************************************/
2099 static void sdhci_tasklet_finish(unsigned long param)
2101 struct sdhci_host *host;
2102 unsigned long flags;
2103 struct mmc_request *mrq;
2105 host = (struct sdhci_host*)param;
2107 spin_lock_irqsave(&host->lock, flags);
2110 * If this tasklet gets rescheduled while running, it will
2111 * be run again afterwards but without any active request.
2114 spin_unlock_irqrestore(&host->lock, flags);
2118 del_timer(&host->timer);
2123 * The controller needs a reset of internal state machines
2124 * upon error conditions.
2126 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2127 ((mrq->cmd && mrq->cmd->error) ||
2128 (mrq->data && (mrq->data->error ||
2129 (mrq->data->stop && mrq->data->stop->error))) ||
2130 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2132 /* Some controllers need this kick or reset won't work here */
2133 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2134 /* This is to force an update */
2135 host->ops->set_clock(host, host->clock);
2137 /* Spec says we should do both at the same time, but Ricoh
2138 controllers do not like that. */
2139 sdhci_do_reset(host, SDHCI_RESET_CMD);
2140 sdhci_do_reset(host, SDHCI_RESET_DATA);
2147 #ifndef SDHCI_USE_LEDS_CLASS
2148 sdhci_deactivate_led(host);
2152 spin_unlock_irqrestore(&host->lock, flags);
2154 mmc_request_done(host->mmc, mrq);
2155 sdhci_runtime_pm_put(host);
2158 static void sdhci_timeout_timer(unsigned long data)
2160 struct sdhci_host *host;
2161 unsigned long flags;
2163 host = (struct sdhci_host*)data;
2165 spin_lock_irqsave(&host->lock, flags);
2168 pr_err("%s: Timeout waiting for hardware "
2169 "interrupt.\n", mmc_hostname(host->mmc));
2170 sdhci_dumpregs(host);
2173 host->data->error = -ETIMEDOUT;
2174 sdhci_finish_data(host);
2177 host->cmd->error = -ETIMEDOUT;
2179 host->mrq->cmd->error = -ETIMEDOUT;
2181 tasklet_schedule(&host->finish_tasklet);
2186 spin_unlock_irqrestore(&host->lock, flags);
2189 static void sdhci_tuning_timer(unsigned long data)
2191 struct sdhci_host *host;
2192 unsigned long flags;
2194 host = (struct sdhci_host *)data;
2196 spin_lock_irqsave(&host->lock, flags);
2198 host->flags |= SDHCI_NEEDS_RETUNING;
2200 spin_unlock_irqrestore(&host->lock, flags);
2203 /*****************************************************************************\
2205 * Interrupt handling *
2207 \*****************************************************************************/
2209 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2211 BUG_ON(intmask == 0);
2214 pr_err("%s: Got command interrupt 0x%08x even "
2215 "though no command operation was in progress.\n",
2216 mmc_hostname(host->mmc), (unsigned)intmask);
2217 sdhci_dumpregs(host);
2221 if (intmask & SDHCI_INT_TIMEOUT)
2222 host->cmd->error = -ETIMEDOUT;
2223 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2225 host->cmd->error = -EILSEQ;
2227 if (host->cmd->error) {
2228 tasklet_schedule(&host->finish_tasklet);
2233 * The host can send and interrupt when the busy state has
2234 * ended, allowing us to wait without wasting CPU cycles.
2235 * Unfortunately this is overloaded on the "data complete"
2236 * interrupt, so we need to take some care when handling
2239 * Note: The 1.0 specification is a bit ambiguous about this
2240 * feature so there might be some problems with older
2243 if (host->cmd->flags & MMC_RSP_BUSY) {
2244 if (host->cmd->data)
2245 DBG("Cannot wait for busy signal when also "
2246 "doing a data transfer");
2247 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2250 /* The controller does not support the end-of-busy IRQ,
2251 * fall through and take the SDHCI_INT_RESPONSE */
2254 if (intmask & SDHCI_INT_RESPONSE)
2255 sdhci_finish_command(host);
2258 #ifdef CONFIG_MMC_DEBUG
2259 static void sdhci_show_adma_error(struct sdhci_host *host)
2261 const char *name = mmc_hostname(host->mmc);
2262 u8 *desc = host->adma_desc;
2267 sdhci_dumpregs(host);
2270 dma = (__le32 *)(desc + 4);
2271 len = (__le16 *)(desc + 2);
2274 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2275 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2284 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2287 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2290 BUG_ON(intmask == 0);
2292 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2293 if (intmask & SDHCI_INT_DATA_AVAIL) {
2294 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2295 if (command == MMC_SEND_TUNING_BLOCK ||
2296 command == MMC_SEND_TUNING_BLOCK_HS200) {
2297 host->tuning_done = 1;
2298 wake_up(&host->buf_ready_int);
2305 * The "data complete" interrupt is also used to
2306 * indicate that a busy state has ended. See comment
2307 * above in sdhci_cmd_irq().
2309 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2310 if (intmask & SDHCI_INT_DATA_END) {
2311 sdhci_finish_command(host);
2316 pr_err("%s: Got data interrupt 0x%08x even "
2317 "though no data operation was in progress.\n",
2318 mmc_hostname(host->mmc), (unsigned)intmask);
2319 sdhci_dumpregs(host);
2324 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2325 host->data->error = -ETIMEDOUT;
2326 else if (intmask & SDHCI_INT_DATA_END_BIT)
2327 host->data->error = -EILSEQ;
2328 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2329 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2331 host->data->error = -EILSEQ;
2332 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2333 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2334 sdhci_show_adma_error(host);
2335 host->data->error = -EIO;
2336 if (host->ops->adma_workaround)
2337 host->ops->adma_workaround(host, intmask);
2340 if (host->data->error)
2341 sdhci_finish_data(host);
2343 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2344 sdhci_transfer_pio(host);
2347 * We currently don't do anything fancy with DMA
2348 * boundaries, but as we can't disable the feature
2349 * we need to at least restart the transfer.
2351 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2352 * should return a valid address to continue from, but as
2353 * some controllers are faulty, don't trust them.
2355 if (intmask & SDHCI_INT_DMA_END) {
2356 u32 dmastart, dmanow;
2357 dmastart = sg_dma_address(host->data->sg);
2358 dmanow = dmastart + host->data->bytes_xfered;
2360 * Force update to the next DMA block boundary.
2363 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2364 SDHCI_DEFAULT_BOUNDARY_SIZE;
2365 host->data->bytes_xfered = dmanow - dmastart;
2366 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2368 mmc_hostname(host->mmc), dmastart,
2369 host->data->bytes_xfered, dmanow);
2370 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2373 if (intmask & SDHCI_INT_DATA_END) {
2376 * Data managed to finish before the
2377 * command completed. Make sure we do
2378 * things in the proper order.
2380 host->data_early = 1;
2382 sdhci_finish_data(host);
2388 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2390 irqreturn_t result = IRQ_NONE;
2391 struct sdhci_host *host = dev_id;
2392 u32 intmask, mask, unexpected = 0;
2395 spin_lock(&host->lock);
2397 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2398 spin_unlock(&host->lock);
2402 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2403 if (!intmask || intmask == 0xffffffff) {
2409 /* Clear selected interrupts. */
2410 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2411 SDHCI_INT_BUS_POWER);
2412 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2414 DBG("*** %s got interrupt: 0x%08x\n",
2415 mmc_hostname(host->mmc), intmask);
2417 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2418 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2422 * There is a observation on i.mx esdhc. INSERT
2423 * bit will be immediately set again when it gets
2424 * cleared, if a card is inserted. We have to mask
2425 * the irq to prevent interrupt storm which will
2426 * freeze the system. And the REMOVE gets the
2429 * More testing are needed here to ensure it works
2430 * for other platforms though.
2432 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2433 SDHCI_INT_CARD_REMOVE);
2434 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2435 SDHCI_INT_CARD_INSERT;
2436 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2437 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2439 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2440 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2442 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2443 SDHCI_INT_CARD_REMOVE);
2444 result = IRQ_WAKE_THREAD;
2447 if (intmask & SDHCI_INT_CMD_MASK)
2448 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2450 if (intmask & SDHCI_INT_DATA_MASK)
2451 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2453 if (intmask & SDHCI_INT_BUS_POWER)
2454 pr_err("%s: Card is consuming too much power!\n",
2455 mmc_hostname(host->mmc));
2457 if (intmask & SDHCI_INT_CARD_INT) {
2458 sdhci_enable_sdio_irq_nolock(host, false);
2459 host->thread_isr |= SDHCI_INT_CARD_INT;
2460 result = IRQ_WAKE_THREAD;
2463 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2464 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2465 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2466 SDHCI_INT_CARD_INT);
2469 unexpected |= intmask;
2470 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2473 if (result == IRQ_NONE)
2474 result = IRQ_HANDLED;
2476 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2477 } while (intmask && --max_loops);
2479 spin_unlock(&host->lock);
2482 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2483 mmc_hostname(host->mmc), unexpected);
2484 sdhci_dumpregs(host);
2490 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2492 struct sdhci_host *host = dev_id;
2493 unsigned long flags;
2496 spin_lock_irqsave(&host->lock, flags);
2497 isr = host->thread_isr;
2498 host->thread_isr = 0;
2499 spin_unlock_irqrestore(&host->lock, flags);
2501 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2502 sdhci_card_event(host->mmc);
2503 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2506 if (isr & SDHCI_INT_CARD_INT) {
2507 sdio_run_irqs(host->mmc);
2509 spin_lock_irqsave(&host->lock, flags);
2510 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2511 sdhci_enable_sdio_irq_nolock(host, true);
2512 spin_unlock_irqrestore(&host->lock, flags);
2515 return isr ? IRQ_HANDLED : IRQ_NONE;
2518 /*****************************************************************************\
2522 \*****************************************************************************/
2525 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2528 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2529 | SDHCI_WAKE_ON_INT;
2531 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2533 /* Avoid fake wake up */
2534 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2535 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2536 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2538 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2540 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2543 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2544 | SDHCI_WAKE_ON_INT;
2546 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2548 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2550 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2552 int sdhci_suspend_host(struct sdhci_host *host)
2554 sdhci_disable_card_detection(host);
2556 /* Disable tuning since we are suspending */
2557 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2558 del_timer_sync(&host->tuning_timer);
2559 host->flags &= ~SDHCI_NEEDS_RETUNING;
2562 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2564 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2565 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2566 free_irq(host->irq, host);
2568 sdhci_enable_irq_wakeups(host);
2569 enable_irq_wake(host->irq);
2574 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2576 int sdhci_resume_host(struct sdhci_host *host)
2580 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2581 if (host->ops->enable_dma)
2582 host->ops->enable_dma(host);
2585 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2586 ret = request_threaded_irq(host->irq, sdhci_irq,
2587 sdhci_thread_irq, IRQF_SHARED,
2588 mmc_hostname(host->mmc), host);
2592 sdhci_disable_irq_wakeups(host);
2593 disable_irq_wake(host->irq);
2596 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2597 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2598 /* Card keeps power but host controller does not */
2599 sdhci_init(host, 0);
2602 sdhci_do_set_ios(host, &host->mmc->ios);
2604 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2608 sdhci_enable_card_detection(host);
2610 /* Set the re-tuning expiration flag */
2611 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2612 host->flags |= SDHCI_NEEDS_RETUNING;
2617 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2618 #endif /* CONFIG_PM */
2620 #ifdef CONFIG_PM_RUNTIME
2622 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2624 return pm_runtime_get_sync(host->mmc->parent);
2627 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2629 pm_runtime_mark_last_busy(host->mmc->parent);
2630 return pm_runtime_put_autosuspend(host->mmc->parent);
2633 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2635 if (host->runtime_suspended || host->bus_on)
2637 host->bus_on = true;
2638 pm_runtime_get_noresume(host->mmc->parent);
2641 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2643 if (host->runtime_suspended || !host->bus_on)
2645 host->bus_on = false;
2646 pm_runtime_put_noidle(host->mmc->parent);
2649 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2651 unsigned long flags;
2654 /* Disable tuning since we are suspending */
2655 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2656 del_timer_sync(&host->tuning_timer);
2657 host->flags &= ~SDHCI_NEEDS_RETUNING;
2660 spin_lock_irqsave(&host->lock, flags);
2661 host->ier &= SDHCI_INT_CARD_INT;
2662 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2663 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2664 spin_unlock_irqrestore(&host->lock, flags);
2666 synchronize_hardirq(host->irq);
2668 spin_lock_irqsave(&host->lock, flags);
2669 host->runtime_suspended = true;
2670 spin_unlock_irqrestore(&host->lock, flags);
2674 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2676 int sdhci_runtime_resume_host(struct sdhci_host *host)
2678 unsigned long flags;
2679 int ret = 0, host_flags = host->flags;
2681 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2682 if (host->ops->enable_dma)
2683 host->ops->enable_dma(host);
2686 sdhci_init(host, 0);
2688 /* Force clock and power re-program */
2691 sdhci_do_set_ios(host, &host->mmc->ios);
2693 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2694 if ((host_flags & SDHCI_PV_ENABLED) &&
2695 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2696 spin_lock_irqsave(&host->lock, flags);
2697 sdhci_enable_preset_value(host, true);
2698 spin_unlock_irqrestore(&host->lock, flags);
2701 /* Set the re-tuning expiration flag */
2702 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2703 host->flags |= SDHCI_NEEDS_RETUNING;
2705 spin_lock_irqsave(&host->lock, flags);
2707 host->runtime_suspended = false;
2709 /* Enable SDIO IRQ */
2710 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2711 sdhci_enable_sdio_irq_nolock(host, true);
2713 /* Enable Card Detection */
2714 sdhci_enable_card_detection(host);
2716 spin_unlock_irqrestore(&host->lock, flags);
2720 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2724 /*****************************************************************************\
2726 * Device allocation/registration *
2728 \*****************************************************************************/
2730 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2733 struct mmc_host *mmc;
2734 struct sdhci_host *host;
2736 WARN_ON(dev == NULL);
2738 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2740 return ERR_PTR(-ENOMEM);
2742 host = mmc_priv(mmc);
2748 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2750 int sdhci_add_host(struct sdhci_host *host)
2752 struct mmc_host *mmc;
2753 u32 caps[2] = {0, 0};
2754 u32 max_current_caps;
2755 unsigned int ocr_avail;
2758 WARN_ON(host == NULL);
2765 host->quirks = debug_quirks;
2767 host->quirks2 = debug_quirks2;
2769 sdhci_do_reset(host, SDHCI_RESET_ALL);
2771 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2772 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2773 >> SDHCI_SPEC_VER_SHIFT;
2774 if (host->version > SDHCI_SPEC_300) {
2775 pr_err("%s: Unknown controller version (%d). "
2776 "You may experience problems.\n", mmc_hostname(mmc),
2780 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2781 sdhci_readl(host, SDHCI_CAPABILITIES);
2783 if (host->version >= SDHCI_SPEC_300)
2784 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2786 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2788 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2789 host->flags |= SDHCI_USE_SDMA;
2790 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2791 DBG("Controller doesn't have SDMA capability\n");
2793 host->flags |= SDHCI_USE_SDMA;
2795 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2796 (host->flags & SDHCI_USE_SDMA)) {
2797 DBG("Disabling DMA as it is marked broken\n");
2798 host->flags &= ~SDHCI_USE_SDMA;
2801 if ((host->version >= SDHCI_SPEC_200) &&
2802 (caps[0] & SDHCI_CAN_DO_ADMA2))
2803 host->flags |= SDHCI_USE_ADMA;
2805 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2806 (host->flags & SDHCI_USE_ADMA)) {
2807 DBG("Disabling ADMA as it is marked broken\n");
2808 host->flags &= ~SDHCI_USE_ADMA;
2811 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2812 if (host->ops->enable_dma) {
2813 if (host->ops->enable_dma(host)) {
2814 pr_warning("%s: No suitable DMA "
2815 "available. Falling back to PIO.\n",
2818 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2823 if (host->flags & SDHCI_USE_ADMA) {
2825 * We need to allocate descriptors for all sg entries
2826 * (128) and potentially one alignment transfer for
2827 * each of those entries.
2829 host->adma_desc = dma_alloc_coherent(mmc_dev(host->mmc),
2830 ADMA_SIZE, &host->adma_addr,
2832 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2833 if (!host->adma_desc || !host->align_buffer) {
2834 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
2835 host->adma_desc, host->adma_addr);
2836 kfree(host->align_buffer);
2837 pr_warning("%s: Unable to allocate ADMA "
2838 "buffers. Falling back to standard DMA.\n",
2840 host->flags &= ~SDHCI_USE_ADMA;
2841 host->adma_desc = NULL;
2842 host->align_buffer = NULL;
2843 } else if (host->adma_addr & 3) {
2844 pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
2846 host->flags &= ~SDHCI_USE_ADMA;
2847 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
2848 host->adma_desc, host->adma_addr);
2849 kfree(host->align_buffer);
2850 host->adma_desc = NULL;
2851 host->align_buffer = NULL;
2856 * If we use DMA, then it's up to the caller to set the DMA
2857 * mask, but PIO does not need the hw shim so we set a new
2858 * mask here in that case.
2860 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2861 host->dma_mask = DMA_BIT_MASK(64);
2862 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2865 if (host->version >= SDHCI_SPEC_300)
2866 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2867 >> SDHCI_CLOCK_BASE_SHIFT;
2869 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2870 >> SDHCI_CLOCK_BASE_SHIFT;
2872 host->max_clk *= 1000000;
2873 if (host->max_clk == 0 || host->quirks &
2874 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2875 if (!host->ops->get_max_clock) {
2876 pr_err("%s: Hardware doesn't specify base clock "
2877 "frequency.\n", mmc_hostname(mmc));
2880 host->max_clk = host->ops->get_max_clock(host);
2884 * In case of Host Controller v3.00, find out whether clock
2885 * multiplier is supported.
2887 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2888 SDHCI_CLOCK_MUL_SHIFT;
2891 * In case the value in Clock Multiplier is 0, then programmable
2892 * clock mode is not supported, otherwise the actual clock
2893 * multiplier is one more than the value of Clock Multiplier
2894 * in the Capabilities Register.
2900 * Set host parameters.
2902 mmc->ops = &sdhci_ops;
2903 mmc->f_max = host->max_clk;
2904 if (host->ops->get_min_clock)
2905 mmc->f_min = host->ops->get_min_clock(host);
2906 else if (host->version >= SDHCI_SPEC_300) {
2907 if (host->clk_mul) {
2908 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2909 mmc->f_max = host->max_clk * host->clk_mul;
2911 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2913 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2916 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2917 if (host->timeout_clk == 0) {
2918 if (host->ops->get_timeout_clock) {
2919 host->timeout_clk = host->ops->get_timeout_clock(host);
2920 } else if (!(host->quirks &
2921 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2922 pr_err("%s: Hardware doesn't specify timeout clock "
2923 "frequency.\n", mmc_hostname(mmc));
2927 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2928 host->timeout_clk *= 1000;
2930 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2931 host->timeout_clk = mmc->f_max / 1000;
2933 mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
2935 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2936 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2938 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2939 host->flags |= SDHCI_AUTO_CMD12;
2941 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2942 if ((host->version >= SDHCI_SPEC_300) &&
2943 ((host->flags & SDHCI_USE_ADMA) ||
2944 !(host->flags & SDHCI_USE_SDMA))) {
2945 host->flags |= SDHCI_AUTO_CMD23;
2946 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2948 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2952 * A controller may support 8-bit width, but the board itself
2953 * might not have the pins brought out. Boards that support
2954 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2955 * their platform code before calling sdhci_add_host(), and we
2956 * won't assume 8-bit width for hosts without that CAP.
2958 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2959 mmc->caps |= MMC_CAP_4_BIT_DATA;
2961 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2962 mmc->caps &= ~MMC_CAP_CMD23;
2964 if (caps[0] & SDHCI_CAN_DO_HISPD)
2965 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2967 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2968 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2969 mmc->caps |= MMC_CAP_NEEDS_POLL;
2971 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2972 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
2973 if (IS_ERR_OR_NULL(host->vqmmc)) {
2974 if (PTR_ERR(host->vqmmc) < 0) {
2975 pr_info("%s: no vqmmc regulator found\n",
2980 ret = regulator_enable(host->vqmmc);
2981 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2983 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2984 SDHCI_SUPPORT_SDR50 |
2985 SDHCI_SUPPORT_DDR50);
2987 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2988 mmc_hostname(mmc), ret);
2993 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2994 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2995 SDHCI_SUPPORT_DDR50);
2997 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2998 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2999 SDHCI_SUPPORT_DDR50))
3000 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3002 /* SDR104 supports also implies SDR50 support */
3003 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3004 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3005 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3006 * field can be promoted to support HS200.
3008 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3009 mmc->caps2 |= MMC_CAP2_HS200;
3010 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3011 mmc->caps |= MMC_CAP_UHS_SDR50;
3013 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3014 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3015 mmc->caps |= MMC_CAP_UHS_DDR50;
3017 /* Does the host need tuning for SDR50? */
3018 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3019 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3021 /* Does the host need tuning for SDR104 / HS200? */
3022 if (mmc->caps2 & MMC_CAP2_HS200)
3023 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3025 /* Driver Type(s) (A, C, D) supported by the host */
3026 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3027 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3028 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3029 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3030 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3031 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3033 /* Initial value for re-tuning timer count */
3034 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3035 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3038 * In case Re-tuning Timer is not disabled, the actual value of
3039 * re-tuning timer will be 2 ^ (n - 1).
3041 if (host->tuning_count)
3042 host->tuning_count = 1 << (host->tuning_count - 1);
3044 /* Re-tuning mode supported by the Host Controller */
3045 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3046 SDHCI_RETUNING_MODE_SHIFT;
3050 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
3051 if (IS_ERR_OR_NULL(host->vmmc)) {
3052 if (PTR_ERR(host->vmmc) < 0) {
3053 pr_info("%s: no vmmc regulator found\n",
3059 #ifdef CONFIG_REGULATOR
3061 * Voltage range check makes sense only if regulator reports
3062 * any voltage value.
3064 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
3065 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3067 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3068 caps[0] &= ~SDHCI_CAN_VDD_330;
3069 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3070 caps[0] &= ~SDHCI_CAN_VDD_300;
3071 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3073 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3074 caps[0] &= ~SDHCI_CAN_VDD_180;
3076 #endif /* CONFIG_REGULATOR */
3079 * According to SD Host Controller spec v3.00, if the Host System
3080 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3081 * the value is meaningful only if Voltage Support in the Capabilities
3082 * register is set. The actual current value is 4 times the register
3085 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3086 if (!max_current_caps && host->vmmc) {
3087 u32 curr = regulator_get_current_limit(host->vmmc);
3090 /* convert to SDHCI_MAX_CURRENT format */
3091 curr = curr/1000; /* convert to mA */
3092 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3094 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3096 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3097 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3098 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3102 if (caps[0] & SDHCI_CAN_VDD_330) {
3103 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3105 mmc->max_current_330 = ((max_current_caps &
3106 SDHCI_MAX_CURRENT_330_MASK) >>
3107 SDHCI_MAX_CURRENT_330_SHIFT) *
3108 SDHCI_MAX_CURRENT_MULTIPLIER;
3110 if (caps[0] & SDHCI_CAN_VDD_300) {
3111 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3113 mmc->max_current_300 = ((max_current_caps &
3114 SDHCI_MAX_CURRENT_300_MASK) >>
3115 SDHCI_MAX_CURRENT_300_SHIFT) *
3116 SDHCI_MAX_CURRENT_MULTIPLIER;
3118 if (caps[0] & SDHCI_CAN_VDD_180) {
3119 ocr_avail |= MMC_VDD_165_195;
3121 mmc->max_current_180 = ((max_current_caps &
3122 SDHCI_MAX_CURRENT_180_MASK) >>
3123 SDHCI_MAX_CURRENT_180_SHIFT) *
3124 SDHCI_MAX_CURRENT_MULTIPLIER;
3128 ocr_avail = host->ocr_mask;
3130 mmc->ocr_avail = ocr_avail;
3131 mmc->ocr_avail_sdio = ocr_avail;
3132 if (host->ocr_avail_sdio)
3133 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3134 mmc->ocr_avail_sd = ocr_avail;
3135 if (host->ocr_avail_sd)
3136 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3137 else /* normal SD controllers don't support 1.8V */
3138 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3139 mmc->ocr_avail_mmc = ocr_avail;
3140 if (host->ocr_avail_mmc)
3141 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3143 if (mmc->ocr_avail == 0) {
3144 pr_err("%s: Hardware doesn't report any "
3145 "support voltages.\n", mmc_hostname(mmc));
3149 spin_lock_init(&host->lock);
3152 * Maximum number of segments. Depends on if the hardware
3153 * can do scatter/gather or not.
3155 if (host->flags & SDHCI_USE_ADMA)
3156 mmc->max_segs = 128;
3157 else if (host->flags & SDHCI_USE_SDMA)
3160 mmc->max_segs = 128;
3163 * Maximum number of sectors in one transfer. Limited by DMA boundary
3166 mmc->max_req_size = 524288;
3169 * Maximum segment size. Could be one segment with the maximum number
3170 * of bytes. When doing hardware scatter/gather, each entry cannot
3171 * be larger than 64 KiB though.
3173 if (host->flags & SDHCI_USE_ADMA) {
3174 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3175 mmc->max_seg_size = 65535;
3177 mmc->max_seg_size = 65536;
3179 mmc->max_seg_size = mmc->max_req_size;
3183 * Maximum block size. This varies from controller to controller and
3184 * is specified in the capabilities register.
3186 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3187 mmc->max_blk_size = 2;
3189 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3190 SDHCI_MAX_BLOCK_SHIFT;
3191 if (mmc->max_blk_size >= 3) {
3192 pr_warning("%s: Invalid maximum block size, "
3193 "assuming 512 bytes\n", mmc_hostname(mmc));
3194 mmc->max_blk_size = 0;
3198 mmc->max_blk_size = 512 << mmc->max_blk_size;
3201 * Maximum block count.
3203 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3208 tasklet_init(&host->finish_tasklet,
3209 sdhci_tasklet_finish, (unsigned long)host);
3211 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3213 if (host->version >= SDHCI_SPEC_300) {
3214 init_waitqueue_head(&host->buf_ready_int);
3216 /* Initialize re-tuning timer */
3217 init_timer(&host->tuning_timer);
3218 host->tuning_timer.data = (unsigned long)host;
3219 host->tuning_timer.function = sdhci_tuning_timer;
3222 sdhci_init(host, 0);
3224 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3225 IRQF_SHARED, mmc_hostname(mmc), host);
3227 pr_err("%s: Failed to request IRQ %d: %d\n",
3228 mmc_hostname(mmc), host->irq, ret);
3232 #ifdef CONFIG_MMC_DEBUG
3233 sdhci_dumpregs(host);
3236 #ifdef SDHCI_USE_LEDS_CLASS
3237 snprintf(host->led_name, sizeof(host->led_name),
3238 "%s::", mmc_hostname(mmc));
3239 host->led.name = host->led_name;
3240 host->led.brightness = LED_OFF;
3241 host->led.default_trigger = mmc_hostname(mmc);
3242 host->led.brightness_set = sdhci_led_control;
3244 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3246 pr_err("%s: Failed to register LED device: %d\n",
3247 mmc_hostname(mmc), ret);
3256 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3257 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3258 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3259 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3261 sdhci_enable_card_detection(host);
3265 #ifdef SDHCI_USE_LEDS_CLASS
3267 sdhci_do_reset(host, SDHCI_RESET_ALL);
3268 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3269 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3270 free_irq(host->irq, host);
3273 tasklet_kill(&host->finish_tasklet);
3278 EXPORT_SYMBOL_GPL(sdhci_add_host);
3280 void sdhci_remove_host(struct sdhci_host *host, int dead)
3282 unsigned long flags;
3285 spin_lock_irqsave(&host->lock, flags);
3287 host->flags |= SDHCI_DEVICE_DEAD;
3290 pr_err("%s: Controller removed during "
3291 " transfer!\n", mmc_hostname(host->mmc));
3293 host->mrq->cmd->error = -ENOMEDIUM;
3294 tasklet_schedule(&host->finish_tasklet);
3297 spin_unlock_irqrestore(&host->lock, flags);
3300 sdhci_disable_card_detection(host);
3302 mmc_remove_host(host->mmc);
3304 #ifdef SDHCI_USE_LEDS_CLASS
3305 led_classdev_unregister(&host->led);
3309 sdhci_do_reset(host, SDHCI_RESET_ALL);
3311 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3312 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3313 free_irq(host->irq, host);
3315 del_timer_sync(&host->timer);
3317 tasklet_kill(&host->finish_tasklet);
3320 regulator_disable(host->vmmc);
3321 regulator_put(host->vmmc);
3325 regulator_disable(host->vqmmc);
3326 regulator_put(host->vqmmc);
3329 if (host->adma_desc)
3330 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
3331 host->adma_desc, host->adma_addr);
3332 kfree(host->align_buffer);
3334 host->adma_desc = NULL;
3335 host->align_buffer = NULL;
3338 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3340 void sdhci_free_host(struct sdhci_host *host)
3342 mmc_free_host(host->mmc);
3345 EXPORT_SYMBOL_GPL(sdhci_free_host);
3347 /*****************************************************************************\
3349 * Driver init/exit *
3351 \*****************************************************************************/
3353 static int __init sdhci_drv_init(void)
3356 ": Secure Digital Host Controller Interface driver\n");
3357 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3362 static void __exit sdhci_drv_exit(void)
3366 module_init(sdhci_drv_init);
3367 module_exit(sdhci_drv_exit);
3369 module_param(debug_quirks, uint, 0444);
3370 module_param(debug_quirks2, uint, 0444);
3372 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3373 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3374 MODULE_LICENSE("GPL");
3376 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3377 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");