3 * Copyright 2017 Free Electrons
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
7 * Derived from the atmel_nand.c driver which contained the following
10 * Copyright 2003 Rick Bronson
12 * Derived from drivers/mtd/nand/autcpu12.c
13 * Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
15 * Derived from drivers/mtd/spia.c
16 * Copyright 2000 Steven J. Hill (sjhill@cotw.com)
19 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
20 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
22 * Derived from Das U-Boot source code
23 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
24 * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
26 * Add Programmable Multibit ECC support for various AT91 SoC
27 * Copyright 2012 ATMEL, Hong Xu
29 * Add Nand Flash Controller support for SAMA5 SoC
30 * Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
32 * This program is free software; you can redistribute it and/or modify
33 * it under the terms of the GNU General Public License version 2 as
34 * published by the Free Software Foundation.
36 * A few words about the naming convention in this file. This convention
37 * applies to structure and function names.
41 * - atmel_nand_: all generic structures/functions
42 * - atmel_smc_nand_: all structures/functions specific to the SMC interface
43 * (at91sam9 and avr32 SoCs)
44 * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
45 * (sama5 SoCs and later)
46 * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
47 * that is available in the HSMC block
48 * - <soc>_nand_: all SoC specific structures/functions
51 #include <linux/clk.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/dmaengine.h>
54 #include <linux/genalloc.h>
55 #include <linux/gpio.h>
56 #include <linux/gpio/consumer.h>
57 #include <linux/interrupt.h>
58 #include <linux/mfd/syscon.h>
59 #include <linux/mfd/syscon/atmel-matrix.h>
60 #include <linux/module.h>
61 #include <linux/mtd/nand.h>
62 #include <linux/of_address.h>
63 #include <linux/of_irq.h>
64 #include <linux/of_platform.h>
65 #include <linux/iopoll.h>
66 #include <linux/platform_device.h>
67 #include <linux/platform_data/atmel.h>
68 #include <linux/regmap.h>
72 #define ATMEL_HSMC_NFC_CFG 0x0
73 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x) (((x) / 4) << 24)
74 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK GENMASK(30, 24)
75 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul) (((cyc) << 16) | ((mul) << 20))
76 #define ATMEL_HSMC_NFC_CFG_DTO_MAX GENMASK(22, 16)
77 #define ATMEL_HSMC_NFC_CFG_RBEDGE BIT(13)
78 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE BIT(12)
79 #define ATMEL_HSMC_NFC_CFG_RSPARE BIT(9)
80 #define ATMEL_HSMC_NFC_CFG_WSPARE BIT(8)
81 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK GENMASK(2, 0)
82 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x) (fls((x) / 512) - 1)
84 #define ATMEL_HSMC_NFC_CTRL 0x4
85 #define ATMEL_HSMC_NFC_CTRL_EN BIT(0)
86 #define ATMEL_HSMC_NFC_CTRL_DIS BIT(1)
88 #define ATMEL_HSMC_NFC_SR 0x8
89 #define ATMEL_HSMC_NFC_IER 0xc
90 #define ATMEL_HSMC_NFC_IDR 0x10
91 #define ATMEL_HSMC_NFC_IMR 0x14
92 #define ATMEL_HSMC_NFC_SR_ENABLED BIT(1)
93 #define ATMEL_HSMC_NFC_SR_RB_RISE BIT(4)
94 #define ATMEL_HSMC_NFC_SR_RB_FALL BIT(5)
95 #define ATMEL_HSMC_NFC_SR_BUSY BIT(8)
96 #define ATMEL_HSMC_NFC_SR_WR BIT(11)
97 #define ATMEL_HSMC_NFC_SR_CSID GENMASK(14, 12)
98 #define ATMEL_HSMC_NFC_SR_XFRDONE BIT(16)
99 #define ATMEL_HSMC_NFC_SR_CMDDONE BIT(17)
100 #define ATMEL_HSMC_NFC_SR_DTOE BIT(20)
101 #define ATMEL_HSMC_NFC_SR_UNDEF BIT(21)
102 #define ATMEL_HSMC_NFC_SR_AWB BIT(22)
103 #define ATMEL_HSMC_NFC_SR_NFCASE BIT(23)
104 #define ATMEL_HSMC_NFC_SR_ERRORS (ATMEL_HSMC_NFC_SR_DTOE | \
105 ATMEL_HSMC_NFC_SR_UNDEF | \
106 ATMEL_HSMC_NFC_SR_AWB | \
107 ATMEL_HSMC_NFC_SR_NFCASE)
108 #define ATMEL_HSMC_NFC_SR_RBEDGE(x) BIT((x) + 24)
110 #define ATMEL_HSMC_NFC_ADDR 0x18
111 #define ATMEL_HSMC_NFC_BANK 0x1c
113 #define ATMEL_NFC_MAX_RB_ID 7
115 #define ATMEL_NFC_SRAM_SIZE 0x2400
117 #define ATMEL_NFC_CMD(pos, cmd) ((cmd) << (((pos) * 8) + 2))
118 #define ATMEL_NFC_VCMD2 BIT(18)
119 #define ATMEL_NFC_ACYCLE(naddrs) ((naddrs) << 19)
120 #define ATMEL_NFC_CSID(cs) ((cs) << 22)
121 #define ATMEL_NFC_DATAEN BIT(25)
122 #define ATMEL_NFC_NFCWR BIT(26)
124 #define ATMEL_NFC_MAX_ADDR_CYCLES 5
126 #define ATMEL_NAND_ALE_OFFSET BIT(21)
127 #define ATMEL_NAND_CLE_OFFSET BIT(22)
129 #define DEFAULT_TIMEOUT_MS 1000
130 #define MIN_DMA_LEN 128
132 enum atmel_nand_rb_type {
134 ATMEL_NAND_NATIVE_RB,
138 struct atmel_nand_rb {
139 enum atmel_nand_rb_type type;
141 struct gpio_desc *gpio;
146 struct atmel_nand_cs {
148 struct atmel_nand_rb rb;
149 struct gpio_desc *csgpio;
157 struct list_head node;
159 struct nand_chip base;
160 struct atmel_nand_cs *activecs;
161 struct atmel_pmecc_user *pmecc;
162 struct gpio_desc *cdgpio;
164 struct atmel_nand_cs cs[];
167 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
169 return container_of(chip, struct atmel_nand, base);
172 enum atmel_nfc_data_xfer {
175 ATMEL_NFC_WRITE_DATA,
178 struct atmel_nfc_op {
184 enum atmel_nfc_data_xfer data;
189 struct atmel_nand_controller;
190 struct atmel_nand_controller_caps;
192 struct atmel_nand_controller_ops {
193 int (*probe)(struct platform_device *pdev,
194 const struct atmel_nand_controller_caps *caps);
195 int (*remove)(struct atmel_nand_controller *nc);
196 void (*nand_init)(struct atmel_nand_controller *nc,
197 struct atmel_nand *nand);
198 int (*ecc_init)(struct atmel_nand *nand);
201 struct atmel_nand_controller_caps {
203 bool legacy_of_bindings;
206 const struct atmel_nand_controller_ops *ops;
209 struct atmel_nand_controller {
210 struct nand_hw_control base;
211 const struct atmel_nand_controller_caps *caps;
214 struct dma_chan *dmac;
215 struct atmel_pmecc *pmecc;
216 struct list_head chips;
220 static inline struct atmel_nand_controller *
221 to_nand_controller(struct nand_hw_control *ctl)
223 return container_of(ctl, struct atmel_nand_controller, base);
226 struct atmel_smc_nand_controller {
227 struct atmel_nand_controller base;
228 struct regmap *matrix;
229 unsigned int ebi_csa_offs;
232 static inline struct atmel_smc_nand_controller *
233 to_smc_nand_controller(struct nand_hw_control *ctl)
235 return container_of(to_nand_controller(ctl),
236 struct atmel_smc_nand_controller, base);
239 struct atmel_hsmc_nand_controller {
240 struct atmel_nand_controller base;
242 struct gen_pool *pool;
247 struct atmel_nfc_op op;
248 struct completion complete;
251 /* Only used when instantiating from legacy DT bindings. */
255 static inline struct atmel_hsmc_nand_controller *
256 to_hsmc_nand_controller(struct nand_hw_control *ctl)
258 return container_of(to_nand_controller(ctl),
259 struct atmel_hsmc_nand_controller, base);
262 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
264 op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
265 op->wait ^= status & op->wait;
267 return !op->wait || op->errors;
270 static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
272 struct atmel_hsmc_nand_controller *nc = data;
276 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
278 rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
279 done = atmel_nfc_op_done(&nc->op, sr);
282 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
285 complete(&nc->complete);
287 return rcvd ? IRQ_HANDLED : IRQ_NONE;
290 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
291 unsigned int timeout_ms)
296 timeout_ms = DEFAULT_TIMEOUT_MS;
301 ret = regmap_read_poll_timeout(nc->base.smc,
302 ATMEL_HSMC_NFC_SR, status,
303 atmel_nfc_op_done(&nc->op,
305 0, timeout_ms * 1000);
307 init_completion(&nc->complete);
308 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
309 nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
310 ret = wait_for_completion_timeout(&nc->complete,
311 msecs_to_jiffies(timeout_ms));
317 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
320 if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
321 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
325 if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
326 dev_err(nc->base.dev, "Access to an undefined area\n");
330 if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
331 dev_err(nc->base.dev, "Access while busy\n");
335 if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
336 dev_err(nc->base.dev, "Wrong access size\n");
343 static void atmel_nand_dma_transfer_finished(void *data)
345 struct completion *finished = data;
350 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
351 void *buf, dma_addr_t dev_dma, size_t len,
352 enum dma_data_direction dir)
354 DECLARE_COMPLETION_ONSTACK(finished);
355 dma_addr_t src_dma, dst_dma, buf_dma;
356 struct dma_async_tx_descriptor *tx;
359 buf_dma = dma_map_single(nc->dev, buf, len, dir);
360 if (dma_mapping_error(nc->dev, dev_dma)) {
362 "Failed to prepare a buffer for DMA access\n");
366 if (dir == DMA_FROM_DEVICE) {
374 tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
375 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
377 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
381 tx->callback = atmel_nand_dma_transfer_finished;
382 tx->callback_param = &finished;
384 cookie = dmaengine_submit(tx);
385 if (dma_submit_error(cookie)) {
386 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
390 dma_async_issue_pending(nc->dmac);
391 wait_for_completion(&finished);
396 dma_unmap_single(nc->dev, buf_dma, len, dir);
399 dev_dbg(nc->dev, "Fall back to CPU I/O\n");
404 static u8 atmel_nand_read_byte(struct mtd_info *mtd)
406 struct nand_chip *chip = mtd_to_nand(mtd);
407 struct atmel_nand *nand = to_atmel_nand(chip);
409 return ioread8(nand->activecs->io.virt);
412 static u16 atmel_nand_read_word(struct mtd_info *mtd)
414 struct nand_chip *chip = mtd_to_nand(mtd);
415 struct atmel_nand *nand = to_atmel_nand(chip);
417 return ioread16(nand->activecs->io.virt);
420 static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
422 struct nand_chip *chip = mtd_to_nand(mtd);
423 struct atmel_nand *nand = to_atmel_nand(chip);
425 if (chip->options & NAND_BUSWIDTH_16)
426 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
428 iowrite8(byte, nand->activecs->io.virt);
431 static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
433 struct nand_chip *chip = mtd_to_nand(mtd);
434 struct atmel_nand *nand = to_atmel_nand(chip);
435 struct atmel_nand_controller *nc;
437 nc = to_nand_controller(chip->controller);
440 * If the controller supports DMA, the buffer address is DMA-able and
441 * len is long enough to make DMA transfers profitable, let's trigger
442 * a DMA transfer. If it fails, fallback to PIO mode.
444 if (nc->dmac && virt_addr_valid(buf) &&
445 len >= MIN_DMA_LEN &&
446 !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
450 if (chip->options & NAND_BUSWIDTH_16)
451 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
453 ioread8_rep(nand->activecs->io.virt, buf, len);
456 static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
458 struct nand_chip *chip = mtd_to_nand(mtd);
459 struct atmel_nand *nand = to_atmel_nand(chip);
460 struct atmel_nand_controller *nc;
462 nc = to_nand_controller(chip->controller);
465 * If the controller supports DMA, the buffer address is DMA-able and
466 * len is long enough to make DMA transfers profitable, let's trigger
467 * a DMA transfer. If it fails, fallback to PIO mode.
469 if (nc->dmac && virt_addr_valid(buf) &&
470 len >= MIN_DMA_LEN &&
471 !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
475 if (chip->options & NAND_BUSWIDTH_16)
476 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
478 iowrite8_rep(nand->activecs->io.virt, buf, len);
481 static int atmel_nand_dev_ready(struct mtd_info *mtd)
483 struct nand_chip *chip = mtd_to_nand(mtd);
484 struct atmel_nand *nand = to_atmel_nand(chip);
486 return gpiod_get_value(nand->activecs->rb.gpio);
489 static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
491 struct nand_chip *chip = mtd_to_nand(mtd);
492 struct atmel_nand *nand = to_atmel_nand(chip);
494 if (cs < 0 || cs >= nand->numcs) {
495 nand->activecs = NULL;
496 chip->dev_ready = NULL;
500 nand->activecs = &nand->cs[cs];
502 if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
503 chip->dev_ready = atmel_nand_dev_ready;
506 static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
508 struct nand_chip *chip = mtd_to_nand(mtd);
509 struct atmel_nand *nand = to_atmel_nand(chip);
510 struct atmel_hsmc_nand_controller *nc;
513 nc = to_hsmc_nand_controller(chip->controller);
515 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
517 return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
520 static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
522 struct nand_chip *chip = mtd_to_nand(mtd);
523 struct atmel_nand *nand = to_atmel_nand(chip);
524 struct atmel_hsmc_nand_controller *nc;
526 nc = to_hsmc_nand_controller(chip->controller);
528 atmel_nand_select_chip(mtd, cs);
530 if (!nand->activecs) {
531 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
532 ATMEL_HSMC_NFC_CTRL_DIS);
536 if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
537 chip->dev_ready = atmel_hsmc_nand_dev_ready;
539 regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
540 ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
541 ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
542 ATMEL_HSMC_NFC_CFG_RSPARE |
543 ATMEL_HSMC_NFC_CFG_WSPARE,
544 ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
545 ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
546 ATMEL_HSMC_NFC_CFG_RSPARE);
547 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
548 ATMEL_HSMC_NFC_CTRL_EN);
551 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
553 u8 *addrs = nc->op.addrs;
558 nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
560 for (i = 0; i < nc->op.ncmds; i++)
561 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
563 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
564 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
566 op |= ATMEL_NFC_CSID(nc->op.cs) |
567 ATMEL_NFC_ACYCLE(nc->op.naddrs);
569 if (nc->op.ncmds > 1)
570 op |= ATMEL_NFC_VCMD2;
572 addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
575 if (nc->op.data != ATMEL_NFC_NO_DATA) {
576 op |= ATMEL_NFC_DATAEN;
577 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
579 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
580 op |= ATMEL_NFC_NFCWR;
583 /* Clear all flags. */
584 regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
586 /* Send the command. */
587 regmap_write(nc->io, op, addr);
589 ret = atmel_nfc_wait(nc, poll, 0);
591 dev_err(nc->base.dev,
592 "Failed to send NAND command (err = %d)!",
595 /* Reset the op state. */
596 memset(&nc->op, 0, sizeof(nc->op));
601 static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
604 struct nand_chip *chip = mtd_to_nand(mtd);
605 struct atmel_nand *nand = to_atmel_nand(chip);
606 struct atmel_hsmc_nand_controller *nc;
608 nc = to_hsmc_nand_controller(chip->controller);
610 if (ctrl & NAND_ALE) {
611 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
614 nc->op.addrs[nc->op.naddrs++] = dat;
615 } else if (ctrl & NAND_CLE) {
616 if (nc->op.ncmds > 1)
619 nc->op.cmds[nc->op.ncmds++] = dat;
622 if (dat == NAND_CMD_NONE) {
623 nc->op.cs = nand->activecs->id;
624 atmel_nfc_exec_op(nc, true);
628 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
631 struct nand_chip *chip = mtd_to_nand(mtd);
632 struct atmel_nand *nand = to_atmel_nand(chip);
633 struct atmel_nand_controller *nc;
635 nc = to_nand_controller(chip->controller);
637 if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) {
639 gpiod_set_value(nand->activecs->csgpio, 0);
641 gpiod_set_value(nand->activecs->csgpio, 1);
645 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
646 else if (ctrl & NAND_CLE)
647 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
650 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
653 struct mtd_info *mtd = nand_to_mtd(chip);
654 struct atmel_hsmc_nand_controller *nc;
657 nc = to_hsmc_nand_controller(chip->controller);
660 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
661 nc->sram.dma, mtd->writesize,
664 /* Falling back to CPU copy. */
666 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
669 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
673 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
676 struct mtd_info *mtd = nand_to_mtd(chip);
677 struct atmel_hsmc_nand_controller *nc;
680 nc = to_hsmc_nand_controller(chip->controller);
683 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
684 mtd->writesize, DMA_FROM_DEVICE);
686 /* Falling back to CPU copy. */
688 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
691 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
695 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
697 struct mtd_info *mtd = nand_to_mtd(chip);
698 struct atmel_hsmc_nand_controller *nc;
700 nc = to_hsmc_nand_controller(chip->controller);
703 nc->op.addrs[nc->op.naddrs++] = column;
706 * 2 address cycles for the column offset on large page NANDs.
708 if (mtd->writesize > 512)
709 nc->op.addrs[nc->op.naddrs++] = column >> 8;
713 nc->op.addrs[nc->op.naddrs++] = page;
714 nc->op.addrs[nc->op.naddrs++] = page >> 8;
716 if ((mtd->writesize > 512 && chip->chipsize > SZ_128M) ||
717 (mtd->writesize <= 512 && chip->chipsize > SZ_32M))
718 nc->op.addrs[nc->op.naddrs++] = page >> 16;
722 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
724 struct atmel_nand *nand = to_atmel_nand(chip);
725 struct atmel_nand_controller *nc;
728 nc = to_nand_controller(chip->controller);
733 ret = atmel_pmecc_enable(nand->pmecc, op);
736 "Failed to enable ECC engine (err = %d)\n", ret);
741 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
743 struct atmel_nand *nand = to_atmel_nand(chip);
746 atmel_pmecc_disable(nand->pmecc);
749 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
751 struct atmel_nand *nand = to_atmel_nand(chip);
752 struct mtd_info *mtd = nand_to_mtd(chip);
753 struct atmel_nand_controller *nc;
754 struct mtd_oob_region oobregion;
758 nc = to_nand_controller(chip->controller);
763 ret = atmel_pmecc_wait_rdy(nand->pmecc);
766 "Failed to transfer NAND page data (err = %d)\n",
771 mtd_ooblayout_ecc(mtd, 0, &oobregion);
772 eccbuf = chip->oob_poi + oobregion.offset;
774 for (i = 0; i < chip->ecc.steps; i++) {
775 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
777 eccbuf += chip->ecc.bytes;
783 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
786 struct atmel_nand *nand = to_atmel_nand(chip);
787 struct mtd_info *mtd = nand_to_mtd(chip);
788 struct atmel_nand_controller *nc;
789 struct mtd_oob_region oobregion;
790 int ret, i, max_bitflips = 0;
791 void *databuf, *eccbuf;
793 nc = to_nand_controller(chip->controller);
798 ret = atmel_pmecc_wait_rdy(nand->pmecc);
801 "Failed to read NAND page data (err = %d)\n",
806 mtd_ooblayout_ecc(mtd, 0, &oobregion);
807 eccbuf = chip->oob_poi + oobregion.offset;
810 for (i = 0; i < chip->ecc.steps; i++) {
811 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
813 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
814 ret = nand_check_erased_ecc_chunk(databuf,
822 max_bitflips = max(ret, max_bitflips);
824 mtd->ecc_stats.failed++;
826 databuf += chip->ecc.size;
827 eccbuf += chip->ecc.bytes;
833 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
834 bool oob_required, int page, bool raw)
836 struct mtd_info *mtd = nand_to_mtd(chip);
837 struct atmel_nand *nand = to_atmel_nand(chip);
840 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
844 atmel_nand_write_buf(mtd, buf, mtd->writesize);
846 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
848 atmel_pmecc_disable(nand->pmecc);
852 atmel_nand_pmecc_disable(chip, raw);
854 atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
859 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
860 struct nand_chip *chip, const u8 *buf,
861 int oob_required, int page)
863 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
866 static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
867 struct nand_chip *chip,
868 const u8 *buf, int oob_required,
871 return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
874 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
875 bool oob_required, int page, bool raw)
877 struct mtd_info *mtd = nand_to_mtd(chip);
880 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
884 atmel_nand_read_buf(mtd, buf, mtd->writesize);
885 atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
887 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
889 atmel_nand_pmecc_disable(chip, raw);
894 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
895 struct nand_chip *chip, u8 *buf,
896 int oob_required, int page)
898 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
901 static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
902 struct nand_chip *chip, u8 *buf,
903 int oob_required, int page)
905 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
908 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
909 const u8 *buf, bool oob_required,
912 struct mtd_info *mtd = nand_to_mtd(chip);
913 struct atmel_nand *nand = to_atmel_nand(chip);
914 struct atmel_hsmc_nand_controller *nc;
917 nc = to_hsmc_nand_controller(chip->controller);
919 atmel_nfc_copy_to_sram(chip, buf, false);
921 nc->op.cmds[0] = NAND_CMD_SEQIN;
923 atmel_nfc_set_op_addr(chip, page, 0x0);
924 nc->op.cs = nand->activecs->id;
925 nc->op.data = ATMEL_NFC_WRITE_DATA;
927 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
931 ret = atmel_nfc_exec_op(nc, false);
933 atmel_nand_pmecc_disable(chip, raw);
934 dev_err(nc->base.dev,
935 "Failed to transfer NAND page data (err = %d)\n",
940 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
942 atmel_nand_pmecc_disable(chip, raw);
947 atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
949 nc->op.cmds[0] = NAND_CMD_PAGEPROG;
951 nc->op.cs = nand->activecs->id;
952 ret = atmel_nfc_exec_op(nc, false);
954 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
960 static int atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd,
961 struct nand_chip *chip,
962 const u8 *buf, int oob_required,
965 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
969 static int atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd,
970 struct nand_chip *chip,
972 int oob_required, int page)
974 return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
978 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
979 bool oob_required, int page,
982 struct mtd_info *mtd = nand_to_mtd(chip);
983 struct atmel_nand *nand = to_atmel_nand(chip);
984 struct atmel_hsmc_nand_controller *nc;
987 nc = to_hsmc_nand_controller(chip->controller);
990 * Optimized read page accessors only work when the NAND R/B pin is
991 * connected to a native SoC R/B pin. If that's not the case, fallback
992 * to the non-optimized one.
994 if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
995 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
997 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
1001 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1003 if (mtd->writesize > 512)
1004 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1006 atmel_nfc_set_op_addr(chip, page, 0x0);
1007 nc->op.cs = nand->activecs->id;
1008 nc->op.data = ATMEL_NFC_READ_DATA;
1010 ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1014 ret = atmel_nfc_exec_op(nc, false);
1016 atmel_nand_pmecc_disable(chip, raw);
1017 dev_err(nc->base.dev,
1018 "Failed to load NAND page data (err = %d)\n",
1023 atmel_nfc_copy_from_sram(chip, buf, true);
1025 ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1027 atmel_nand_pmecc_disable(chip, raw);
1032 static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
1033 struct nand_chip *chip, u8 *buf,
1034 int oob_required, int page)
1036 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1040 static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
1041 struct nand_chip *chip,
1042 u8 *buf, int oob_required,
1045 return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1049 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1051 struct mtd_info *mtd = nand_to_mtd(chip);
1052 struct atmel_nand *nand = to_atmel_nand(chip);
1053 struct atmel_nand_controller *nc;
1054 struct atmel_pmecc_user_req req;
1056 nc = to_nand_controller(chip->controller);
1059 dev_err(nc->dev, "HW ECC not supported\n");
1063 if (nc->caps->legacy_of_bindings) {
1066 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1068 chip->ecc.strength = val;
1070 if (!of_property_read_u32(nc->dev->of_node,
1071 "atmel,pmecc-sector-size",
1073 chip->ecc.size = val;
1076 if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1077 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1078 else if (chip->ecc.strength)
1079 req.ecc.strength = chip->ecc.strength;
1080 else if (chip->ecc_strength_ds)
1081 req.ecc.strength = chip->ecc_strength_ds;
1083 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1086 req.ecc.sectorsize = chip->ecc.size;
1087 else if (chip->ecc_step_ds)
1088 req.ecc.sectorsize = chip->ecc_step_ds;
1090 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1092 req.pagesize = mtd->writesize;
1093 req.oobsize = mtd->oobsize;
1095 if (mtd->writesize <= 512) {
1097 req.ecc.ooboffset = 0;
1099 req.ecc.bytes = mtd->oobsize - 2;
1100 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1103 nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1104 if (IS_ERR(nand->pmecc))
1105 return PTR_ERR(nand->pmecc);
1107 chip->ecc.algo = NAND_ECC_BCH;
1108 chip->ecc.size = req.ecc.sectorsize;
1109 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1110 chip->ecc.strength = req.ecc.strength;
1112 chip->options |= NAND_NO_SUBPAGE_WRITE;
1114 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1119 static int atmel_nand_ecc_init(struct atmel_nand *nand)
1121 struct nand_chip *chip = &nand->base;
1122 struct atmel_nand_controller *nc;
1125 nc = to_nand_controller(chip->controller);
1127 switch (chip->ecc.mode) {
1131 * Nothing to do, the core will initialize everything for us.
1136 ret = atmel_nand_pmecc_init(chip);
1140 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1141 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1142 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1143 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1147 /* Other modes are not supported. */
1148 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1156 static int atmel_hsmc_nand_ecc_init(struct atmel_nand *nand)
1158 struct nand_chip *chip = &nand->base;
1161 ret = atmel_nand_ecc_init(nand);
1165 if (chip->ecc.mode != NAND_ECC_HW)
1168 /* Adjust the ECC operations for the HSMC IP. */
1169 chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1170 chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1171 chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1172 chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1173 chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
1178 static void atmel_nand_init(struct atmel_nand_controller *nc,
1179 struct atmel_nand *nand)
1181 struct nand_chip *chip = &nand->base;
1182 struct mtd_info *mtd = nand_to_mtd(chip);
1184 mtd->dev.parent = nc->dev;
1185 nand->base.controller = &nc->base;
1187 chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1188 chip->read_byte = atmel_nand_read_byte;
1189 chip->read_word = atmel_nand_read_word;
1190 chip->write_byte = atmel_nand_write_byte;
1191 chip->read_buf = atmel_nand_read_buf;
1192 chip->write_buf = atmel_nand_write_buf;
1193 chip->select_chip = atmel_nand_select_chip;
1195 /* Some NANDs require a longer delay than the default one (20us). */
1196 chip->chip_delay = 40;
1199 * Use a bounce buffer when the buffer passed by the MTD user is not
1203 chip->options |= NAND_USE_BOUNCE_BUFFER;
1205 /* Default to HW ECC if pmecc is available. */
1207 chip->ecc.mode = NAND_ECC_HW;
1210 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1211 struct atmel_nand *nand)
1213 struct nand_chip *chip = &nand->base;
1214 struct atmel_smc_nand_controller *smc_nc;
1217 atmel_nand_init(nc, nand);
1219 smc_nc = to_smc_nand_controller(chip->controller);
1220 if (!smc_nc->matrix)
1223 /* Attach the CS to the NAND Flash logic. */
1224 for (i = 0; i < nand->numcs; i++)
1225 regmap_update_bits(smc_nc->matrix, smc_nc->ebi_csa_offs,
1226 BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1229 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1230 struct atmel_nand *nand)
1232 struct nand_chip *chip = &nand->base;
1234 atmel_nand_init(nc, nand);
1236 /* Overload some methods for the HSMC controller. */
1237 chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1238 chip->select_chip = atmel_hsmc_nand_select_chip;
1241 static int atmel_nand_detect(struct atmel_nand *nand)
1243 struct nand_chip *chip = &nand->base;
1244 struct mtd_info *mtd = nand_to_mtd(chip);
1245 struct atmel_nand_controller *nc;
1248 nc = to_nand_controller(chip->controller);
1250 ret = nand_scan_ident(mtd, nand->numcs, NULL);
1252 dev_err(nc->dev, "nand_scan_ident() failed: %d\n", ret);
1257 static int atmel_nand_unregister(struct atmel_nand *nand)
1259 struct nand_chip *chip = &nand->base;
1260 struct mtd_info *mtd = nand_to_mtd(chip);
1263 ret = mtd_device_unregister(mtd);
1268 list_del(&nand->node);
1273 static int atmel_nand_register(struct atmel_nand *nand)
1275 struct nand_chip *chip = &nand->base;
1276 struct mtd_info *mtd = nand_to_mtd(chip);
1277 struct atmel_nand_controller *nc;
1280 nc = to_nand_controller(chip->controller);
1282 if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1284 * We keep the MTD name unchanged to avoid breaking platforms
1285 * where the MTD cmdline parser is used and the bootloader
1286 * has not been updated to use the new naming scheme.
1288 mtd->name = "atmel_nand";
1289 } else if (!mtd->name) {
1291 * If the new bindings are used and the bootloader has not been
1292 * updated to pass a new mtdparts parameter on the cmdline, you
1293 * should define the following property in your nand node:
1295 * label = "atmel_nand";
1297 * This way, mtd->name will be set by the core when
1298 * nand_set_flash_node() is called.
1300 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
1301 "%s:nand.%d", dev_name(nc->dev),
1304 dev_err(nc->dev, "Failed to allocate mtd->name\n");
1309 ret = nand_scan_tail(mtd);
1311 dev_err(nc->dev, "nand_scan_tail() failed: %d\n", ret);
1315 ret = mtd_device_register(mtd, NULL, 0);
1317 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1322 list_add_tail(&nand->node, &nc->chips);
1327 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1328 struct device_node *np,
1331 struct atmel_nand *nand;
1332 struct gpio_desc *gpio;
1335 numcs = of_property_count_elems_of_size(np, "reg",
1336 reg_cells * sizeof(u32));
1338 dev_err(nc->dev, "Missing or invalid reg property\n");
1339 return ERR_PTR(-EINVAL);
1342 nand = devm_kzalloc(nc->dev,
1343 sizeof(*nand) + (numcs * sizeof(*nand->cs)),
1346 dev_err(nc->dev, "Failed to allocate NAND object\n");
1347 return ERR_PTR(-ENOMEM);
1350 nand->numcs = numcs;
1352 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "det", 0,
1353 &np->fwnode, GPIOD_IN,
1355 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1357 "Failed to get detect gpio (err = %ld)\n",
1359 return ERR_CAST(gpio);
1363 nand->cdgpio = gpio;
1365 for (i = 0; i < numcs; i++) {
1366 struct resource res;
1369 ret = of_address_to_resource(np, 0, &res);
1371 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1373 return ERR_PTR(ret);
1376 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1379 dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1381 return ERR_PTR(ret);
1384 nand->cs[i].id = val;
1386 nand->cs[i].io.dma = res.start;
1387 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1388 if (IS_ERR(nand->cs[i].io.virt))
1389 return ERR_CAST(nand->cs[i].io.virt);
1391 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1392 if (val > ATMEL_NFC_MAX_RB_ID)
1393 return ERR_PTR(-EINVAL);
1395 nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1396 nand->cs[i].rb.id = val;
1398 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev,
1399 "rb", i, &np->fwnode,
1400 GPIOD_IN, "nand-rb");
1401 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1403 "Failed to get R/B gpio (err = %ld)\n",
1405 return ERR_CAST(gpio);
1408 if (!IS_ERR(gpio)) {
1409 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1410 nand->cs[i].rb.gpio = gpio;
1414 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "cs",
1418 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1420 "Failed to get CS gpio (err = %ld)\n",
1422 return ERR_CAST(gpio);
1426 nand->cs[i].csgpio = gpio;
1429 nand_set_flash_node(&nand->base, np);
1435 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1436 struct atmel_nand *nand)
1440 /* No card inserted, skip this NAND. */
1441 if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1442 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1446 nc->caps->ops->nand_init(nc, nand);
1448 ret = atmel_nand_detect(nand);
1452 ret = nc->caps->ops->ecc_init(nand);
1456 return atmel_nand_register(nand);
1460 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1462 struct atmel_nand *nand, *tmp;
1465 list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1466 ret = atmel_nand_unregister(nand);
1475 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1477 struct device *dev = nc->dev;
1478 struct platform_device *pdev = to_platform_device(dev);
1479 struct atmel_nand *nand;
1480 struct gpio_desc *gpio;
1481 struct resource *res;
1484 * Legacy bindings only allow connecting a single NAND with a unique CS
1485 * line to the controller.
1487 nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1494 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1495 nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1496 if (IS_ERR(nand->cs[0].io.virt))
1497 return PTR_ERR(nand->cs[0].io.virt);
1499 nand->cs[0].io.dma = res->start;
1502 * The old driver was hardcoding the CS id to 3 for all sama5
1503 * controllers. Since this id is only meaningful for the sama5
1504 * controller we can safely assign this id to 3 no matter the
1506 * If one wants to connect a NAND to a different CS line, he will
1507 * have to use the new bindings.
1512 gpio = devm_gpiod_get_index_optional(dev, NULL, 0, GPIOD_IN);
1514 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1516 return PTR_ERR(gpio);
1520 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1521 nand->cs[0].rb.gpio = gpio;
1525 gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1527 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1529 return PTR_ERR(gpio);
1532 nand->cs[0].csgpio = gpio;
1534 /* Card detect GPIO. */
1535 gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1538 "Failed to get detect gpio (err = %ld)\n",
1540 return PTR_ERR(gpio);
1543 nand->cdgpio = gpio;
1545 nand_set_flash_node(&nand->base, nc->dev->of_node);
1547 return atmel_nand_controller_add_nand(nc, nand);
1550 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1552 struct device_node *np, *nand_np;
1553 struct device *dev = nc->dev;
1557 /* We do not retrieve the SMC syscon when parsing old DTs. */
1558 if (nc->caps->legacy_of_bindings)
1559 return atmel_nand_controller_legacy_add_nands(nc);
1563 ret = of_property_read_u32(np, "#address-cells", &val);
1565 dev_err(dev, "missing #address-cells property\n");
1571 ret = of_property_read_u32(np, "#size-cells", &val);
1573 dev_err(dev, "missing #address-cells property\n");
1579 for_each_child_of_node(np, nand_np) {
1580 struct atmel_nand *nand;
1582 nand = atmel_nand_create(nc, nand_np, reg_cells);
1584 ret = PTR_ERR(nand);
1588 ret = atmel_nand_controller_add_nand(nc, nand);
1596 atmel_nand_controller_remove_nands(nc);
1601 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1604 dma_release_channel(nc->dmac);
1609 static const struct of_device_id atmel_matrix_of_ids[] = {
1611 .compatible = "atmel,at91sam9260-matrix",
1612 .data = (void *)AT91SAM9260_MATRIX_EBICSA,
1615 .compatible = "atmel,at91sam9261-matrix",
1616 .data = (void *)AT91SAM9261_MATRIX_EBICSA,
1619 .compatible = "atmel,at91sam9263-matrix",
1620 .data = (void *)AT91SAM9263_MATRIX_EBI0CSA,
1623 .compatible = "atmel,at91sam9rl-matrix",
1624 .data = (void *)AT91SAM9RL_MATRIX_EBICSA,
1627 .compatible = "atmel,at91sam9g45-matrix",
1628 .data = (void *)AT91SAM9G45_MATRIX_EBICSA,
1631 .compatible = "atmel,at91sam9n12-matrix",
1632 .data = (void *)AT91SAM9N12_MATRIX_EBICSA,
1635 .compatible = "atmel,at91sam9x5-matrix",
1636 .data = (void *)AT91SAM9X5_MATRIX_EBICSA,
1641 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
1642 struct platform_device *pdev,
1643 const struct atmel_nand_controller_caps *caps)
1645 struct device *dev = &pdev->dev;
1646 struct device_node *np = dev->of_node;
1649 nand_hw_control_init(&nc->base);
1650 INIT_LIST_HEAD(&nc->chips);
1654 platform_set_drvdata(pdev, nc);
1656 nc->pmecc = devm_atmel_pmecc_get(dev);
1657 if (IS_ERR(nc->pmecc)) {
1658 ret = PTR_ERR(nc->pmecc);
1659 if (ret != -EPROBE_DEFER)
1660 dev_err(dev, "Could not get PMECC object (err = %d)\n",
1665 if (nc->caps->has_dma) {
1666 dma_cap_mask_t mask;
1669 dma_cap_set(DMA_MEMCPY, mask);
1671 nc->dmac = dma_request_channel(mask, NULL, NULL);
1673 dev_err(nc->dev, "Failed to request DMA channel\n");
1676 /* We do not retrieve the SMC syscon when parsing old DTs. */
1677 if (nc->caps->legacy_of_bindings)
1680 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
1682 dev_err(dev, "Missing or invalid atmel,smc property\n");
1686 nc->smc = syscon_node_to_regmap(np);
1688 if (IS_ERR(nc->smc)) {
1689 ret = PTR_ERR(nc->smc);
1690 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
1698 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
1700 struct device *dev = nc->base.dev;
1701 const struct of_device_id *match;
1702 struct device_node *np;
1705 /* We do not retrieve the matrix syscon when parsing old DTs. */
1706 if (nc->base.caps->legacy_of_bindings)
1709 np = of_parse_phandle(dev->parent->of_node, "atmel,matrix", 0);
1713 match = of_match_node(atmel_matrix_of_ids, np);
1719 nc->matrix = syscon_node_to_regmap(np);
1721 if (IS_ERR(nc->matrix)) {
1722 ret = PTR_ERR(nc->matrix);
1723 dev_err(dev, "Could not get Matrix regmap (err = %d)\n", ret);
1727 nc->ebi_csa_offs = (unsigned int)match->data;
1730 * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
1731 * add 4 to ->ebi_csa_offs.
1733 if (of_device_is_compatible(dev->parent->of_node,
1734 "atmel,at91sam9263-ebi1"))
1735 nc->ebi_csa_offs += 4;
1741 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
1743 struct regmap_config regmap_conf = {
1749 struct device *dev = nc->base.dev;
1750 struct device_node *nand_np, *nfc_np;
1751 void __iomem *iomem;
1752 struct resource res;
1755 nand_np = dev->of_node;
1756 nfc_np = of_find_compatible_node(dev->of_node, NULL,
1757 "atmel,sama5d3-nfc");
1759 nc->clk = of_clk_get(nfc_np, 0);
1760 if (IS_ERR(nc->clk)) {
1761 ret = PTR_ERR(nc->clk);
1762 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
1767 ret = clk_prepare_enable(nc->clk);
1769 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
1774 nc->irq = of_irq_get(nand_np, 0);
1777 if (ret != -EPROBE_DEFER)
1778 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
1783 ret = of_address_to_resource(nfc_np, 0, &res);
1785 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
1790 iomem = devm_ioremap_resource(dev, &res);
1791 if (IS_ERR(iomem)) {
1792 ret = PTR_ERR(iomem);
1796 regmap_conf.name = "nfc-io";
1797 regmap_conf.max_register = resource_size(&res) - 4;
1798 nc->io = devm_regmap_init_mmio(dev, iomem, ®map_conf);
1799 if (IS_ERR(nc->io)) {
1800 ret = PTR_ERR(nc->io);
1801 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
1806 ret = of_address_to_resource(nfc_np, 1, &res);
1808 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
1813 iomem = devm_ioremap_resource(dev, &res);
1814 if (IS_ERR(iomem)) {
1815 ret = PTR_ERR(iomem);
1819 regmap_conf.name = "smc";
1820 regmap_conf.max_register = resource_size(&res) - 4;
1821 nc->base.smc = devm_regmap_init_mmio(dev, iomem, ®map_conf);
1822 if (IS_ERR(nc->base.smc)) {
1823 ret = PTR_ERR(nc->base.smc);
1824 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
1829 ret = of_address_to_resource(nfc_np, 2, &res);
1831 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
1836 nc->sram.virt = devm_ioremap_resource(dev, &res);
1837 if (IS_ERR(nc->sram.virt)) {
1838 ret = PTR_ERR(nc->sram.virt);
1842 nc->sram.dma = res.start;
1845 of_node_put(nfc_np);
1851 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
1853 struct device *dev = nc->base.dev;
1854 struct device_node *np;
1857 np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
1859 dev_err(dev, "Missing or invalid atmel,smc property\n");
1863 nc->irq = of_irq_get(np, 0);
1866 if (nc->irq != -EPROBE_DEFER)
1867 dev_err(dev, "Failed to get IRQ number (err = %d)\n",
1872 np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
1874 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
1878 nc->io = syscon_node_to_regmap(np);
1880 if (IS_ERR(nc->io)) {
1881 ret = PTR_ERR(nc->io);
1882 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
1886 nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
1887 "atmel,nfc-sram", 0);
1888 if (!nc->sram.pool) {
1889 dev_err(nc->base.dev, "Missing SRAM\n");
1893 nc->sram.virt = gen_pool_dma_alloc(nc->sram.pool,
1894 ATMEL_NFC_SRAM_SIZE,
1896 if (!nc->sram.virt) {
1897 dev_err(nc->base.dev,
1898 "Could not allocate memory from the NFC SRAM pool\n");
1906 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
1908 struct atmel_hsmc_nand_controller *hsmc_nc;
1911 ret = atmel_nand_controller_remove_nands(nc);
1915 hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
1916 if (hsmc_nc->sram.pool)
1917 gen_pool_free(hsmc_nc->sram.pool,
1918 (unsigned long)hsmc_nc->sram.virt,
1919 ATMEL_NFC_SRAM_SIZE);
1922 clk_disable_unprepare(hsmc_nc->clk);
1923 clk_put(hsmc_nc->clk);
1926 atmel_nand_controller_cleanup(nc);
1931 static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
1932 const struct atmel_nand_controller_caps *caps)
1934 struct device *dev = &pdev->dev;
1935 struct atmel_hsmc_nand_controller *nc;
1938 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
1942 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
1946 if (caps->legacy_of_bindings)
1947 ret = atmel_hsmc_nand_controller_legacy_init(nc);
1949 ret = atmel_hsmc_nand_controller_init(nc);
1954 /* Make sure all irqs are masked before registering our IRQ handler. */
1955 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
1956 ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
1957 IRQF_SHARED, "nfc", nc);
1960 "Could not get register NFC interrupt handler (err = %d)\n",
1965 /* Initial NFC configuration. */
1966 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
1967 ATMEL_HSMC_NFC_CFG_DTO_MAX);
1969 ret = atmel_nand_controller_add_nands(&nc->base);
1976 atmel_hsmc_nand_controller_remove(&nc->base);
1981 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
1982 .probe = atmel_hsmc_nand_controller_probe,
1983 .remove = atmel_hsmc_nand_controller_remove,
1984 .ecc_init = atmel_hsmc_nand_ecc_init,
1985 .nand_init = atmel_hsmc_nand_init,
1988 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
1990 .ale_offs = BIT(21),
1991 .cle_offs = BIT(22),
1992 .ops = &atmel_hsmc_nc_ops,
1995 /* Only used to parse old bindings. */
1996 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
1998 .ale_offs = BIT(21),
1999 .cle_offs = BIT(22),
2000 .ops = &atmel_hsmc_nc_ops,
2001 .legacy_of_bindings = true,
2004 static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2005 const struct atmel_nand_controller_caps *caps)
2007 struct device *dev = &pdev->dev;
2008 struct atmel_smc_nand_controller *nc;
2011 nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2015 ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2019 ret = atmel_smc_nand_controller_init(nc);
2023 return atmel_nand_controller_add_nands(&nc->base);
2027 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2031 ret = atmel_nand_controller_remove_nands(nc);
2035 atmel_nand_controller_cleanup(nc);
2040 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2041 .probe = atmel_smc_nand_controller_probe,
2042 .remove = atmel_smc_nand_controller_remove,
2043 .ecc_init = atmel_nand_ecc_init,
2044 .nand_init = atmel_smc_nand_init,
2047 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2048 .ale_offs = BIT(21),
2049 .cle_offs = BIT(22),
2050 .ops = &atmel_smc_nc_ops,
2053 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2054 .ale_offs = BIT(22),
2055 .cle_offs = BIT(21),
2056 .ops = &atmel_smc_nc_ops,
2059 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2061 .ale_offs = BIT(21),
2062 .cle_offs = BIT(22),
2063 .ops = &atmel_smc_nc_ops,
2066 /* Only used to parse old bindings. */
2067 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2068 .ale_offs = BIT(21),
2069 .cle_offs = BIT(22),
2070 .ops = &atmel_smc_nc_ops,
2071 .legacy_of_bindings = true,
2074 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2075 .ale_offs = BIT(22),
2076 .cle_offs = BIT(21),
2077 .ops = &atmel_smc_nc_ops,
2078 .legacy_of_bindings = true,
2081 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2083 .ale_offs = BIT(21),
2084 .cle_offs = BIT(22),
2085 .ops = &atmel_smc_nc_ops,
2086 .legacy_of_bindings = true,
2089 static const struct of_device_id atmel_nand_controller_of_ids[] = {
2091 .compatible = "atmel,at91rm9200-nand-controller",
2092 .data = &atmel_rm9200_nc_caps,
2095 .compatible = "atmel,at91sam9260-nand-controller",
2096 .data = &atmel_rm9200_nc_caps,
2099 .compatible = "atmel,at91sam9261-nand-controller",
2100 .data = &atmel_sam9261_nc_caps,
2103 .compatible = "atmel,at91sam9g45-nand-controller",
2104 .data = &atmel_sam9g45_nc_caps,
2107 .compatible = "atmel,sama5d3-nand-controller",
2108 .data = &atmel_sama5_nc_caps,
2110 /* Support for old/deprecated bindings: */
2112 .compatible = "atmel,at91rm9200-nand",
2113 .data = &atmel_rm9200_nand_caps,
2116 .compatible = "atmel,sama5d4-nand",
2117 .data = &atmel_rm9200_nand_caps,
2120 .compatible = "atmel,sama5d2-nand",
2121 .data = &atmel_rm9200_nand_caps,
2125 MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2127 static int atmel_nand_controller_probe(struct platform_device *pdev)
2129 const struct atmel_nand_controller_caps *caps;
2132 caps = (void *)pdev->id_entry->driver_data;
2134 caps = of_device_get_match_data(&pdev->dev);
2137 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2141 if (caps->legacy_of_bindings) {
2145 * If we are parsing legacy DT props and the DT contains a
2146 * valid NFC node, forward the request to the sama5 logic.
2148 if (of_find_compatible_node(pdev->dev.of_node, NULL,
2149 "atmel,sama5d3-nfc"))
2150 caps = &atmel_sama5_nand_caps;
2153 * Even if the compatible says we are dealing with an
2154 * at91rm9200 controller, the atmel,nand-has-dma specify that
2155 * this controller supports DMA, which means we are in fact
2156 * dealing with an at91sam9g45+ controller.
2158 if (!caps->has_dma &&
2159 of_property_read_bool(pdev->dev.of_node,
2160 "atmel,nand-has-dma"))
2161 caps = &atmel_sam9g45_nand_caps;
2164 * All SoCs except the at91sam9261 are assigning ALE to A21 and
2165 * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2166 * actually dealing with an at91sam9261 controller.
2168 of_property_read_u32(pdev->dev.of_node,
2169 "atmel,nand-addr-offset", &ale_offs);
2171 caps = &atmel_sam9261_nand_caps;
2174 return caps->ops->probe(pdev, caps);
2177 static int atmel_nand_controller_remove(struct platform_device *pdev)
2179 struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2181 return nc->caps->ops->remove(nc);
2184 static struct platform_driver atmel_nand_controller_driver = {
2186 .name = "atmel-nand-controller",
2187 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2189 .probe = atmel_nand_controller_probe,
2190 .remove = atmel_nand_controller_remove,
2192 module_platform_driver(atmel_nand_controller_driver);
2194 MODULE_LICENSE("GPL");
2195 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2196 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2197 MODULE_ALIAS("platform:atmel-nand-controller");