drivers/mtd/nand/gpmi-nand/gpmi-lib.c

   1 /*
   2  * Freescale GPMI NAND Flash Driver
   3  *
   4  * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
   5  * Copyright (C) 2008 Embedded Alley Solutions, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  20  */
  21 #include <linux/delay.h>
  22 #include <linux/clk.h>
  23 #include <linux/slab.h>
  24
  25 #include "gpmi-nand.h"
  26 #include "gpmi-regs.h"
  27 #include "bch-regs.h"
  28
  29 static struct timing_threshod timing_default_threshold = {
  30         .max_data_setup_cycles       = (BM_GPMI_TIMING0_DATA_SETUP >>
  31                                                 BP_GPMI_TIMING0_DATA_SETUP),
  32         .internal_data_setup_in_ns   = 0,
  33         .max_sample_delay_factor     = (BM_GPMI_CTRL1_RDN_DELAY >>
  34                                                 BP_GPMI_CTRL1_RDN_DELAY),
  35         .max_dll_clock_period_in_ns  = 32,
  36         .max_dll_delay_in_ns         = 16,
  37 };
  38
  39 #define MXS_SET_ADDR            0x4
  40 #define MXS_CLR_ADDR            0x8
  41 /*
  42  * Clear the bit and poll it cleared.  This is usually called with
  43  * a reset address and mask being either SFTRST(bit 31) or CLKGATE
  44  * (bit 30).
  45  */
  46 static int clear_poll_bit(void __iomem *addr, u32 mask)
  47 {
  48         int timeout = 0x400;
  49
  50         /* clear the bit */
  51         writel(mask, addr + MXS_CLR_ADDR);
  52
  53         /*
  54          * SFTRST needs 3 GPMI clocks to settle, the reference manual
  55          * recommends to wait 1us.
  56          */
  57         udelay(1);
  58
  59         /* poll the bit becoming clear */
  60         while ((readl(addr) & mask) && --timeout)
  61                 /* nothing */;
  62
  63         return !timeout;
  64 }
  65
  66 #define MODULE_CLKGATE          (1 << 30)
  67 #define MODULE_SFTRST           (1 << 31)
  68 /*
  69  * The current mxs_reset_block() will do two things:
  70  *  [1] enable the module.
  71  *  [2] reset the module.
  72  *
  73  * In most of the cases, it's ok.
  74  * But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
  75  * If you try to soft reset the BCH block, it becomes unusable until
  76  * the next hard reset. This case occurs in the NAND boot mode. When the board
  77  * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
  78  * So If the driver tries to reset the BCH again, the BCH will not work anymore.
  79  * You will see a DMA timeout in this case. The bug has been fixed
  80  * in the following chips, such as MX28.
  81  *
  82  * To avoid this bug, just add a new parameter `just_enable` for
  83  * the mxs_reset_block(), and rewrite it here.
  84  */
  85 static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
  86 {
  87         int ret;
  88         int timeout = 0x400;
  89
  90         /* clear and poll SFTRST */
  91         ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
  92         if (unlikely(ret))
  93                 goto error;
  94
  95         /* clear CLKGATE */
  96         writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
  97
  98         if (!just_enable) {
  99                 /* set SFTRST to reset the block */
 100                 writel(MODULE_SFTRST, reset_addr + MXS_SET_ADDR);
 101                 udelay(1);
 102
 103                 /* poll CLKGATE becoming set */
 104                 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout)
 105                         /* nothing */;
 106                 if (unlikely(!timeout))
 107                         goto error;
 108         }
 109
 110         /* clear and poll SFTRST */
 111         ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
 112         if (unlikely(ret))
 113                 goto error;
 114
 115         /* clear and poll CLKGATE */
 116         ret = clear_poll_bit(reset_addr, MODULE_CLKGATE);
 117         if (unlikely(ret))
 118                 goto error;
 119
 120         return 0;
 121
 122 error:
 123         pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
 124         return -ETIMEDOUT;
 125 }
 126
 127 static int __gpmi_enable_clk(struct gpmi_nand_data *this, bool v)
 128 {
 129         struct clk *clk;
 130         int ret;
 131         int i;
 132
 133         for (i = 0; i < GPMI_CLK_MAX; i++) {
 134                 clk = this->resources.clock[i];
 135                 if (!clk)
 136                         break;
 137
 138                 if (v) {
 139                         ret = clk_prepare_enable(clk);
 140                         if (ret)
 141                                 goto err_clk;
 142                 } else {
 143                         clk_disable_unprepare(clk);
 144                 }
 145         }
 146         return 0;
 147
 148 err_clk:
 149         for (; i > 0; i--)
 150                 clk_disable_unprepare(this->resources.clock[i - 1]);
 151         return ret;
 152 }
 153
 154 #define gpmi_enable_clk(x) __gpmi_enable_clk(x, true)
 155 #define gpmi_disable_clk(x) __gpmi_enable_clk(x, false)
 156
 157 int gpmi_init(struct gpmi_nand_data *this)
 158 {
 159         struct resources *r = &this->resources;
 160         int ret;
 161
 162         ret = gpmi_enable_clk(this);
 163         if (ret)
 164                 return ret;
 165         ret = gpmi_reset_block(r->gpmi_regs, false);
 166         if (ret)
 167                 goto err_out;
 168
 169         /*
 170          * Reset BCH here, too. We got failures otherwise :(
 171          * See later BCH reset for explanation of MX23 handling
 172          */
 173         ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
 174         if (ret)
 175                 goto err_out;
 176
 177
 178         /* Choose NAND mode. */
 179         writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR);
 180
 181         /* Set the IRQ polarity. */
 182         writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
 183                                 r->gpmi_regs + HW_GPMI_CTRL1_SET);
 184
 185         /* Disable Write-Protection. */
 186         writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET);
 187
 188         /* Select BCH ECC. */
 189         writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
 190
 191         /*
 192          * Decouple the chip select from dma channel. We use dma0 for all
 193          * the chips.
 194          */
 195         writel(BM_GPMI_CTRL1_DECOUPLE_CS, r->gpmi_regs + HW_GPMI_CTRL1_SET);
 196
 197         gpmi_disable_clk(this);
 198         return 0;
 199 err_out:
 200         gpmi_disable_clk(this);
 201         return ret;
 202 }
 203
 204 /* This function is very useful. It is called only when the bug occur. */
 205 void gpmi_dump_info(struct gpmi_nand_data *this)
 206 {
 207         struct resources *r = &this->resources;
 208         struct bch_geometry *geo = &this->bch_geometry;
 209         u32 reg;
 210         int i;
 211
 212         dev_err(this->dev, "Show GPMI registers :\n");
 213         for (i = 0; i <= HW_GPMI_DEBUG / 0x10 + 1; i++) {
 214                 reg = readl(r->gpmi_regs + i * 0x10);
 215                 dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
 216         }
 217
 218         /* start to print out the BCH info */
 219         dev_err(this->dev, "Show BCH registers :\n");
 220         for (i = 0; i <= HW_BCH_VERSION / 0x10 + 1; i++) {
 221                 reg = readl(r->bch_regs + i * 0x10);
 222                 dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
 223         }
 224         dev_err(this->dev, "BCH Geometry :\n"
 225                 "GF length              : %u\n"
 226                 "ECC Strength           : %u\n"
 227                 "Page Size in Bytes     : %u\n"
 228                 "Metadata Size in Bytes : %u\n"
 229                 "ECC Chunk Size in Bytes: %u\n"
 230                 "ECC Chunk Count        : %u\n"
 231                 "Payload Size in Bytes  : %u\n"
 232                 "Auxiliary Size in Bytes: %u\n"
 233                 "Auxiliary Status Offset: %u\n"
 234                 "Block Mark Byte Offset : %u\n"
 235                 "Block Mark Bit Offset  : %u\n",
 236                 geo->gf_len,
 237                 geo->ecc_strength,
 238                 geo->page_size,
 239                 geo->metadata_size,
 240                 geo->ecc_chunk_size,
 241                 geo->ecc_chunk_count,
 242                 geo->payload_size,
 243                 geo->auxiliary_size,
 244                 geo->auxiliary_status_offset,
 245                 geo->block_mark_byte_offset,
 246                 geo->block_mark_bit_offset);
 247 }
 248
 249 /* Configures the geometry for BCH.  */
 250 int bch_set_geometry(struct gpmi_nand_data *this)
 251 {
 252         struct resources *r = &this->resources;
 253         struct bch_geometry *bch_geo = &this->bch_geometry;
 254         unsigned int block_count;
 255         unsigned int block_size;
 256         unsigned int metadata_size;
 257         unsigned int ecc_strength;
 258         unsigned int page_size;
 259         unsigned int gf_len;
 260         int ret;
 261
 262         if (common_nfc_set_geometry(this))
 263                 return !0;
 264
 265         block_count   = bch_geo->ecc_chunk_count - 1;
 266         block_size    = bch_geo->ecc_chunk_size;
 267         metadata_size = bch_geo->metadata_size;
 268         ecc_strength  = bch_geo->ecc_strength >> 1;
 269         page_size     = bch_geo->page_size;
 270         gf_len        = bch_geo->gf_len;
 271
 272         ret = gpmi_enable_clk(this);
 273         if (ret)
 274                 return ret;
 275
 276         /*
 277         * Due to erratum #2847 of the MX23, the BCH cannot be soft reset on this
 278         * chip, otherwise it will lock up. So we skip resetting BCH on the MX23.
 279         * On the other hand, the MX28 needs the reset, because one case has been
 280         * seen where the BCH produced ECC errors constantly after 10000
 281         * consecutive reboots. The latter case has not been seen on the MX23
 282         * yet, still we don't know if it could happen there as well.
 283         */
 284         ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
 285         if (ret)
 286                 goto err_out;
 287
 288         /* Configure layout 0. */
 289         writel(BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)
 290                         | BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
 291                         | BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength, this)
 292                         | BF_BCH_FLASH0LAYOUT0_GF(gf_len, this)
 293                         | BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size, this),
 294                         r->bch_regs + HW_BCH_FLASH0LAYOUT0);
 295
 296         writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)
 297                         | BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength, this)
 298                         | BF_BCH_FLASH0LAYOUT1_GF(gf_len, this)
 299                         | BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size, this),
 300                         r->bch_regs + HW_BCH_FLASH0LAYOUT1);
 301
 302         /* Set *all* chip selects to use layout 0. */
 303         writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT);
 304
 305         /* Enable interrupts. */
 306         writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
 307                                 r->bch_regs + HW_BCH_CTRL_SET);
 308
 309         gpmi_disable_clk(this);
 310         return 0;
 311 err_out:
 312         gpmi_disable_clk(this);
 313         return ret;
 314 }
 315
 316 /* Converts time in nanoseconds to cycles. */
 317 static unsigned int ns_to_cycles(unsigned int time,
 318                         unsigned int period, unsigned int min)
 319 {
 320         unsigned int k;
 321
 322         k = (time + period - 1) / period;
 323         return max(k, min);
 324 }
 325
 326 #define DEF_MIN_PROP_DELAY      5
 327 #define DEF_MAX_PROP_DELAY      9
 328 /* Apply timing to current hardware conditions. */
 329 static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
 330                                         struct gpmi_nfc_hardware_timing *hw)
 331 {
 332         struct timing_threshod *nfc = &timing_default_threshold;
 333         struct resources *r = &this->resources;
 334         struct nand_chip *nand = &this->nand;
 335         struct nand_timing target = this->timing;
 336         bool improved_timing_is_available;
 337         unsigned long clock_frequency_in_hz;
 338         unsigned int clock_period_in_ns;
 339         bool dll_use_half_periods;
 340         unsigned int dll_delay_shift;
 341         unsigned int max_sample_delay_in_ns;
 342         unsigned int address_setup_in_cycles;
 343         unsigned int data_setup_in_ns;
 344         unsigned int data_setup_in_cycles;
 345         unsigned int data_hold_in_cycles;
 346         int ideal_sample_delay_in_ns;
 347         unsigned int sample_delay_factor;
 348         int tEYE;
 349         unsigned int min_prop_delay_in_ns = DEF_MIN_PROP_DELAY;
 350         unsigned int max_prop_delay_in_ns = DEF_MAX_PROP_DELAY;
 351
 352         /*
 353          * If there are multiple chips, we need to relax the timings to allow
 354          * for signal distortion due to higher capacitance.
 355          */
 356         if (nand->numchips > 2) {
 357                 target.data_setup_in_ns    += 10;
 358                 target.data_hold_in_ns     += 10;
 359                 target.address_setup_in_ns += 10;
 360         } else if (nand->numchips > 1) {
 361                 target.data_setup_in_ns    += 5;
 362                 target.data_hold_in_ns     += 5;
 363                 target.address_setup_in_ns += 5;
 364         }
 365
 366         /* Check if improved timing information is available. */
 367         improved_timing_is_available =
 368                 (target.tREA_in_ns  >= 0) &&
 369                 (target.tRLOH_in_ns >= 0) &&
 370                 (target.tRHOH_in_ns >= 0);
 371
 372         /* Inspect the clock. */
 373         nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]);
 374         clock_frequency_in_hz = nfc->clock_frequency_in_hz;
 375         clock_period_in_ns    = NSEC_PER_SEC / clock_frequency_in_hz;
 376
 377         /*
 378          * The NFC quantizes setup and hold parameters in terms of clock cycles.
 379          * Here, we quantize the setup and hold timing parameters to the
 380          * next-highest clock period to make sure we apply at least the
 381          * specified times.
 382          *
 383          * For data setup and data hold, the hardware interprets a value of zero
 384          * as the largest possible delay. This is not what's intended by a zero
 385          * in the input parameter, so we impose a minimum of one cycle.
 386          */
 387         data_setup_in_cycles    = ns_to_cycles(target.data_setup_in_ns,
 388                                                         clock_period_in_ns, 1);
 389         data_hold_in_cycles     = ns_to_cycles(target.data_hold_in_ns,
 390                                                         clock_period_in_ns, 1);
 391         address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns,
 392                                                         clock_period_in_ns, 0);
 393
 394         /*
 395          * The clock's period affects the sample delay in a number of ways:
 396          *
 397          * (1) The NFC HAL tells us the maximum clock period the sample delay
 398          *     DLL can tolerate. If the clock period is greater than half that
 399          *     maximum, we must configure the DLL to be driven by half periods.
 400          *
 401          * (2) We need to convert from an ideal sample delay, in ns, to a
 402          *     "sample delay factor," which the NFC uses. This factor depends on
 403          *     whether we're driving the DLL with full or half periods.
 404          *     Paraphrasing the reference manual:
 405          *
 406          *         AD = SDF x 0.125 x RP
 407          *
 408          * where:
 409          *
 410          *     AD   is the applied delay, in ns.
 411          *     SDF  is the sample delay factor, which is dimensionless.
 412          *     RP   is the reference period, in ns, which is a full clock period
 413          *          if the DLL is being driven by full periods, or half that if
 414          *          the DLL is being driven by half periods.
 415          *
 416          * Let's re-arrange this in a way that's more useful to us:
 417          *
 418          *                        8
 419          *         SDF  =  AD x ----
 420          *                       RP
 421          *
 422          * The reference period is either the clock period or half that, so this
 423          * is:
 424          *
 425          *                        8       AD x DDF
 426          *         SDF  =  AD x -----  =  --------
 427          *                      f x P        P
 428          *
 429          * where:
 430          *
 431          *       f  is 1 or 1/2, depending on how we're driving the DLL.
 432          *       P  is the clock period.
 433          *     DDF  is the DLL Delay Factor, a dimensionless value that
 434          *          incorporates all the constants in the conversion.
 435          *
 436          * DDF will be either 8 or 16, both of which are powers of two. We can
 437          * reduce the cost of this conversion by using bit shifts instead of
 438          * multiplication or division. Thus:
 439          *
 440          *                 AD << DDS
 441          *         SDF  =  ---------
 442          *                     P
 443          *
 444          *     or
 445          *
 446          *         AD  =  (SDF >> DDS) x P
 447          *
 448          * where:
 449          *
 450          *     DDS  is the DLL Delay Shift, the logarithm to base 2 of the DDF.
 451          */
 452         if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) {
 453                 dll_use_half_periods = true;
 454                 dll_delay_shift      = 3 + 1;
 455         } else {
 456                 dll_use_half_periods = false;
 457                 dll_delay_shift      = 3;
 458         }
 459
 460         /*
 461          * Compute the maximum sample delay the NFC allows, under current
 462          * conditions. If the clock is running too slowly, no sample delay is
 463          * possible.
 464          */
 465         if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns)
 466                 max_sample_delay_in_ns = 0;
 467         else {
 468                 /*
 469                  * Compute the delay implied by the largest sample delay factor
 470                  * the NFC allows.
 471                  */
 472                 max_sample_delay_in_ns =
 473                         (nfc->max_sample_delay_factor * clock_period_in_ns) >>
 474                                                                 dll_delay_shift;
 475
 476                 /*
 477                  * Check if the implied sample delay larger than the NFC
 478                  * actually allows.
 479                  */
 480                 if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns)
 481                         max_sample_delay_in_ns = nfc->max_dll_delay_in_ns;
 482         }
 483
 484         /*
 485          * Check if improved timing information is available. If not, we have to
 486          * use a less-sophisticated algorithm.
 487          */
 488         if (!improved_timing_is_available) {
 489                 /*
 490                  * Fold the read setup time required by the NFC into the ideal
 491                  * sample delay.
 492                  */
 493                 ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns +
 494                                                 nfc->internal_data_setup_in_ns;
 495
 496                 /*
 497                  * The ideal sample delay may be greater than the maximum
 498                  * allowed by the NFC. If so, we can trade off sample delay time
 499                  * for more data setup time.
 500                  *
 501                  * In each iteration of the following loop, we add a cycle to
 502                  * the data setup time and subtract a corresponding amount from
 503                  * the sample delay until we've satisified the constraints or
 504                  * can't do any better.
 505                  */
 506                 while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
 507                         (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
 508
 509                         data_setup_in_cycles++;
 510                         ideal_sample_delay_in_ns -= clock_period_in_ns;
 511
 512                         if (ideal_sample_delay_in_ns < 0)
 513                                 ideal_sample_delay_in_ns = 0;
 514
 515                 }
 516
 517                 /*
 518                  * Compute the sample delay factor that corresponds most closely
 519                  * to the ideal sample delay. If the result is too large for the
 520                  * NFC, use the maximum value.
 521                  *
 522                  * Notice that we use the ns_to_cycles function to compute the
 523                  * sample delay factor. We do this because the form of the
 524                  * computation is the same as that for calculating cycles.
 525                  */
 526                 sample_delay_factor =
 527                         ns_to_cycles(
 528                                 ideal_sample_delay_in_ns << dll_delay_shift,
 529                                                         clock_period_in_ns, 0);
 530
 531                 if (sample_delay_factor > nfc->max_sample_delay_factor)
 532                         sample_delay_factor = nfc->max_sample_delay_factor;
 533
 534                 /* Skip to the part where we return our results. */
 535                 goto return_results;
 536         }
 537
 538         /*
 539          * If control arrives here, we have more detailed timing information,
 540          * so we can use a better algorithm.
 541          */
 542
 543         /*
 544          * Fold the read setup time required by the NFC into the maximum
 545          * propagation delay.
 546          */
 547         max_prop_delay_in_ns += nfc->internal_data_setup_in_ns;
 548
 549         /*
 550          * Earlier, we computed the number of clock cycles required to satisfy
 551          * the data setup time. Now, we need to know the actual nanoseconds.
 552          */
 553         data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles;
 554
 555         /*
 556          * Compute tEYE, the width of the data eye when reading from the NAND
 557          * Flash. The eye width is fundamentally determined by the data setup
 558          * time, perturbed by propagation delays and some characteristics of the
 559          * NAND Flash device.
 560          *
 561          * start of the eye = max_prop_delay + tREA
 562          * end of the eye   = min_prop_delay + tRHOH + data_setup
 563          */
 564         tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns +
 565                                                         (int)data_setup_in_ns;
 566
 567         tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns;
 568
 569         /*
 570          * The eye must be open. If it's not, we can try to open it by
 571          * increasing its main forcer, the data setup time.
 572          *
 573          * In each iteration of the following loop, we increase the data setup
 574          * time by a single clock cycle. We do this until either the eye is
 575          * open or we run into NFC limits.
 576          */
 577         while ((tEYE <= 0) &&
 578                         (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
 579                 /* Give a cycle to data setup. */
 580                 data_setup_in_cycles++;
 581                 /* Synchronize the data setup time with the cycles. */
 582                 data_setup_in_ns += clock_period_in_ns;
 583                 /* Adjust tEYE accordingly. */
 584                 tEYE += clock_period_in_ns;
 585         }
 586
 587         /*
 588          * When control arrives here, the eye is open. The ideal time to sample
 589          * the data is in the center of the eye:
 590          *
 591          *     end of the eye + start of the eye
 592          *     ---------------------------------  -  data_setup
 593          *                    2
 594          *
 595          * After some algebra, this simplifies to the code immediately below.
 596          */
 597         ideal_sample_delay_in_ns =
 598                 ((int)max_prop_delay_in_ns +
 599                         (int)target.tREA_in_ns +
 600                                 (int)min_prop_delay_in_ns +
 601                                         (int)target.tRHOH_in_ns -
 602                                                 (int)data_setup_in_ns) >> 1;
 603
 604         /*
 605          * The following figure illustrates some aspects of a NAND Flash read:
 606          *
 607          *
 608          *           __                   _____________________________________
 609          * RDN         \_________________/
 610          *
 611          *                                         <---- tEYE ----->
 612          *                                        /-----------------\
 613          * Read Data ----------------------------<                   >---------
 614          *                                        \-----------------/
 615          *             ^                 ^                 ^              ^
 616          *             |                 |                 |              |
 617          *             |<--Data Setup -->|<--Delay Time -->|              |
 618          *             |                 |                 |              |
 619          *             |                 |                                |
 620          *             |                 |<--   Quantized Delay Time   -->|
 621          *             |                 |                                |
 622          *
 623          *
 624          * We have some issues we must now address:
 625          *
 626          * (1) The *ideal* sample delay time must not be negative. If it is, we
 627          *     jam it to zero.
 628          *
 629          * (2) The *ideal* sample delay time must not be greater than that
 630          *     allowed by the NFC. If it is, we can increase the data setup
 631          *     time, which will reduce the delay between the end of the data
 632          *     setup and the center of the eye. It will also make the eye
 633          *     larger, which might help with the next issue...
 634          *
 635          * (3) The *quantized* sample delay time must not fall either before the
 636          *     eye opens or after it closes (the latter is the problem
 637          *     illustrated in the above figure).
 638          */
 639
 640         /* Jam a negative ideal sample delay to zero. */
 641         if (ideal_sample_delay_in_ns < 0)
 642                 ideal_sample_delay_in_ns = 0;
 643
 644         /*
 645          * Extend the data setup as needed to reduce the ideal sample delay
 646          * below the maximum permitted by the NFC.
 647          */
 648         while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
 649                         (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
 650
 651                 /* Give a cycle to data setup. */
 652                 data_setup_in_cycles++;
 653                 /* Synchronize the data setup time with the cycles. */
 654                 data_setup_in_ns += clock_period_in_ns;
 655                 /* Adjust tEYE accordingly. */
 656                 tEYE += clock_period_in_ns;
 657
 658                 /*
 659                  * Decrease the ideal sample delay by one half cycle, to keep it
 660                  * in the middle of the eye.
 661                  */
 662                 ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
 663
 664                 /* Jam a negative ideal sample delay to zero. */
 665                 if (ideal_sample_delay_in_ns < 0)
 666                         ideal_sample_delay_in_ns = 0;
 667         }
 668
 669         /*
 670          * Compute the sample delay factor that corresponds to the ideal sample
 671          * delay. If the result is too large, then use the maximum allowed
 672          * value.
 673          *
 674          * Notice that we use the ns_to_cycles function to compute the sample
 675          * delay factor. We do this because the form of the computation is the
 676          * same as that for calculating cycles.
 677          */
 678         sample_delay_factor =
 679                 ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift,
 680                                                         clock_period_in_ns, 0);
 681
 682         if (sample_delay_factor > nfc->max_sample_delay_factor)
 683                 sample_delay_factor = nfc->max_sample_delay_factor;
 684
 685         /*
 686          * These macros conveniently encapsulate a computation we'll use to
 687          * continuously evaluate whether or not the data sample delay is inside
 688          * the eye.
 689          */
 690         #define IDEAL_DELAY  ((int) ideal_sample_delay_in_ns)
 691
 692         #define QUANTIZED_DELAY  \
 693                 ((int) ((sample_delay_factor * clock_period_in_ns) >> \
 694                                                         dll_delay_shift))
 695
 696         #define DELAY_ERROR  (abs(QUANTIZED_DELAY - IDEAL_DELAY))
 697
 698         #define SAMPLE_IS_NOT_WITHIN_THE_EYE  (DELAY_ERROR > (tEYE >> 1))
 699
 700         /*
 701          * While the quantized sample time falls outside the eye, reduce the
 702          * sample delay or extend the data setup to move the sampling point back
 703          * toward the eye. Do not allow the number of data setup cycles to
 704          * exceed the maximum allowed by the NFC.
 705          */
 706         while (SAMPLE_IS_NOT_WITHIN_THE_EYE &&
 707                         (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
 708                 /*
 709                  * If control arrives here, the quantized sample delay falls
 710                  * outside the eye. Check if it's before the eye opens, or after
 711                  * the eye closes.
 712                  */
 713                 if (QUANTIZED_DELAY > IDEAL_DELAY) {
 714                         /*
 715                          * If control arrives here, the quantized sample delay
 716                          * falls after the eye closes. Decrease the quantized
 717                          * delay time and then go back to re-evaluate.
 718                          */
 719                         if (sample_delay_factor != 0)
 720                                 sample_delay_factor--;
 721                         continue;
 722                 }
 723
 724                 /*
 725                  * If control arrives here, the quantized sample delay falls
 726                  * before the eye opens. Shift the sample point by increasing
 727                  * data setup time. This will also make the eye larger.
 728                  */
 729
 730                 /* Give a cycle to data setup. */
 731                 data_setup_in_cycles++;
 732                 /* Synchronize the data setup time with the cycles. */
 733                 data_setup_in_ns += clock_period_in_ns;
 734                 /* Adjust tEYE accordingly. */
 735                 tEYE += clock_period_in_ns;
 736
 737                 /*
 738                  * Decrease the ideal sample delay by one half cycle, to keep it
 739                  * in the middle of the eye.
 740                  */
 741                 ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
 742
 743                 /* ...and one less period for the delay time. */
 744                 ideal_sample_delay_in_ns -= clock_period_in_ns;
 745
 746                 /* Jam a negative ideal sample delay to zero. */
 747                 if (ideal_sample_delay_in_ns < 0)
 748                         ideal_sample_delay_in_ns = 0;
 749
 750                 /*
 751                  * We have a new ideal sample delay, so re-compute the quantized
 752                  * delay.
 753                  */
 754                 sample_delay_factor =
 755                         ns_to_cycles(
 756                                 ideal_sample_delay_in_ns << dll_delay_shift,
 757                                                         clock_period_in_ns, 0);
 758
 759                 if (sample_delay_factor > nfc->max_sample_delay_factor)
 760                         sample_delay_factor = nfc->max_sample_delay_factor;
 761         }
 762
 763         /* Control arrives here when we're ready to return our results. */
 764 return_results:
 765         hw->data_setup_in_cycles    = data_setup_in_cycles;
 766         hw->data_hold_in_cycles     = data_hold_in_cycles;
 767         hw->address_setup_in_cycles = address_setup_in_cycles;
 768         hw->use_half_periods        = dll_use_half_periods;
 769         hw->sample_delay_factor     = sample_delay_factor;
 770         hw->device_busy_timeout     = GPMI_DEFAULT_BUSY_TIMEOUT;
 771         hw->wrn_dly_sel             = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS;
 772
 773         /* Return success. */
 774         return 0;
 775 }
 776
 777 /*
 778  * <1> Firstly, we should know what's the GPMI-clock means.
 779  *     The GPMI-clock is the internal clock in the gpmi nand controller.
 780  *     If you set 100MHz to gpmi nand controller, the GPMI-clock's period
 781  *     is 10ns. Mark the GPMI-clock's period as GPMI-clock-period.
 782  *
 783  * <2> Secondly, we should know what's the frequency on the nand chip pins.
 784  *     The frequency on the nand chip pins is derived from the GPMI-clock.
 785  *     We can get it from the following equation:
 786  *
 787  *         F = G / (DS + DH)
 788  *
 789  *         F  : the frequency on the nand chip pins.
 790  *         G  : the GPMI clock, such as 100MHz.
 791  *         DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP
 792  *         DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD
 793  *
 794  * <3> Thirdly, when the frequency on the nand chip pins is above 33MHz,
 795  *     the nand EDO(extended Data Out) timing could be applied.
 796  *     The GPMI implements a feedback read strobe to sample the read data.
 797  *     The feedback read strobe can be delayed to support the nand EDO timing
 798  *     where the read strobe may deasserts before the read data is valid, and
 799  *     read data is valid for some time after read strobe.
 800  *
 801  *     The following figure illustrates some aspects of a NAND Flash read:
 802  *
 803  *                   |<---tREA---->|
 804  *                   |             |
 805  *                   |         |   |
 806  *                   |<--tRP-->|   |
 807  *                   |         |   |
 808  *                  __          ___|__________________________________
 809  *     RDN            \________/   |
 810  *                                 |
 811  *                                 /---------\
 812  *     Read Data    --------------<           >---------
 813  *                                 \---------/
 814  *                                |     |
 815  *                                |<-D->|
 816  *     FeedbackRDN  ________             ____________
 817  *                          \___________/
 818  *
 819  *          D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY.
 820  *
 821  *
 822  * <4> Now, we begin to describe how to compute the right RDN_DELAY.
 823  *
 824  *  4.1) From the aspect of the nand chip pins:
 825  *        Delay = (tREA + C - tRP)               {1}
 826  *
 827  *        tREA : the maximum read access time. From the ONFI nand standards,
 828  *               we know that tREA is 16ns in mode 5, tREA is 20ns is mode 4.
 829  *               Please check it in : www.onfi.org
 830  *        C    : a constant for adjust the delay. default is 4.
 831  *        tRP  : the read pulse width.
 832  *               Specified by the HW_GPMI_TIMING0:DATA_SETUP:
 833  *                    tRP = (GPMI-clock-period) * DATA_SETUP
 834  *
 835  *  4.2) From the aspect of the GPMI nand controller:
 836  *         Delay = RDN_DELAY * 0.125 * RP        {2}
 837  *
 838  *         RP   : the DLL reference period.
 839  *            if (GPMI-clock-period > DLL_THRETHOLD)
 840  *                   RP = GPMI-clock-period / 2;
 841  *            else
 842  *                   RP = GPMI-clock-period;
 843  *
 844  *            Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period
 845  *            is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD
 846  *            is 16ns, but in mx6q, we use 12ns.
 847  *
 848  *  4.3) since {1} equals {2}, we get:
 849  *
 850  *                    (tREA + 4 - tRP) * 8
 851  *         RDN_DELAY = ---------------------     {3}
 852  *                           RP
 853  *
 854  *  4.4) We only support the fastest asynchronous mode of ONFI nand.
 855  *       For some ONFI nand, the mode 4 is the fastest mode;
 856  *       while for some ONFI nand, the mode 5 is the fastest mode.
 857  *       So we only support the mode 4 and mode 5. It is no need to
 858  *       support other modes.
 859  */
 860 static void gpmi_compute_edo_timing(struct gpmi_nand_data *this,
 861                         struct gpmi_nfc_hardware_timing *hw)
 862 {
 863         struct resources *r = &this->resources;
 864         unsigned long rate = clk_get_rate(r->clock[0]);
 865         int mode = this->timing_mode;
 866         int dll_threshold = this->devdata->max_chain_delay;
 867         unsigned long delay;
 868         unsigned long clk_period;
 869         int t_rea;
 870         int c = 4;
 871         int t_rp;
 872         int rp;
 873
 874         /*
 875          * [1] for GPMI_HW_GPMI_TIMING0:
 876          *     The async mode requires 40MHz for mode 4, 50MHz for mode 5.
 877          *     The GPMI can support 100MHz at most. So if we want to
 878          *     get the 40MHz or 50MHz, we have to set DS=1, DH=1.
 879          *     Set the ADDRESS_SETUP to 0 in mode 4.
 880          */
 881         hw->data_setup_in_cycles = 1;
 882         hw->data_hold_in_cycles = 1;
 883         hw->address_setup_in_cycles = ((mode == 5) ? 1 : 0);
 884
 885         /* [2] for GPMI_HW_GPMI_TIMING1 */
 886         hw->device_busy_timeout = 0x9000;
 887
 888         /* [3] for GPMI_HW_GPMI_CTRL1 */
 889         hw->wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
 890
 891         /*
 892          * Enlarge 10 times for the numerator and denominator in {3}.
 893          * This make us to get more accurate result.
 894          */
 895         clk_period = NSEC_PER_SEC / (rate / 10);
 896         dll_threshold *= 10;
 897         t_rea = ((mode == 5) ? 16 : 20) * 10;
 898         c *= 10;
 899
 900         t_rp = clk_period * 1; /* DATA_SETUP is 1 */
 901
 902         if (clk_period > dll_threshold) {
 903                 hw->use_half_periods = 1;
 904                 rp = clk_period / 2;
 905         } else {
 906                 hw->use_half_periods = 0;
 907                 rp = clk_period;
 908         }
 909
 910         /*
 911          * Multiply the numerator with 10, we could do a round off:
 912          *      7.8 round up to 8; 7.4 round down to 7.
 913          */
 914         delay  = (((t_rea + c - t_rp) * 8) * 10) / rp;
 915         delay = (delay + 5) / 10;
 916
 917         hw->sample_delay_factor = delay;
 918 }
 919
 920 static int enable_edo_mode(struct gpmi_nand_data *this, int mode)
 921 {
 922         struct resources  *r = &this->resources;
 923         struct nand_chip *nand = &this->nand;
 924         struct mtd_info  *mtd = nand_to_mtd(nand);
 925         uint8_t *feature;
 926         unsigned long rate;
 927         int ret;
 928
 929         feature = kzalloc(ONFI_SUBFEATURE_PARAM_LEN, GFP_KERNEL);
 930         if (!feature)
 931                 return -ENOMEM;
 932
 933         nand->select_chip(mtd, 0);
 934
 935         /* [1] send SET FEATURE commond to NAND */
 936         feature[0] = mode;
 937         ret = nand->onfi_set_features(mtd, nand,
 938                                 ONFI_FEATURE_ADDR_TIMING_MODE, feature);
 939         if (ret)
 940                 goto err_out;
 941
 942         /* [2] send GET FEATURE command to double-check the timing mode */
 943         memset(feature, 0, ONFI_SUBFEATURE_PARAM_LEN);
 944         ret = nand->onfi_get_features(mtd, nand,
 945                                 ONFI_FEATURE_ADDR_TIMING_MODE, feature);
 946         if (ret || feature[0] != mode)
 947                 goto err_out;
 948
 949         nand->select_chip(mtd, -1);
 950
 951         /* [3] set the main IO clock, 100MHz for mode 5, 80MHz for mode 4. */
 952         rate = (mode == 5) ? 100000000 : 80000000;
 953         clk_set_rate(r->clock[0], rate);
 954
 955         /* Let the gpmi_begin() re-compute the timing again. */
 956         this->flags &= ~GPMI_TIMING_INIT_OK;
 957
 958         this->flags |= GPMI_ASYNC_EDO_ENABLED;
 959         this->timing_mode = mode;
 960         kfree(feature);
 961         dev_info(this->dev, "enable the asynchronous EDO mode %d\n", mode);
 962         return 0;
 963
 964 err_out:
 965         nand->select_chip(mtd, -1);
 966         kfree(feature);
 967         dev_err(this->dev, "mode:%d ,failed in set feature.\n", mode);
 968         return -EINVAL;
 969 }
 970
 971 int gpmi_extra_init(struct gpmi_nand_data *this)
 972 {
 973         struct nand_chip *chip = &this->nand;
 974
 975         /* Enable the asynchronous EDO feature. */
 976         if (GPMI_IS_MX6(this) && chip->onfi_version) {
 977                 int mode = onfi_get_async_timing_mode(chip);
 978
 979                 /* We only support the timing mode 4 and mode 5. */
 980                 if (mode & ONFI_TIMING_MODE_5)
 981                         mode = 5;
 982                 else if (mode & ONFI_TIMING_MODE_4)
 983                         mode = 4;
 984                 else
 985                         return 0;
 986
 987                 return enable_edo_mode(this, mode);
 988         }
 989         return 0;
 990 }
 991
 992 /* Begin the I/O */
 993 void gpmi_begin(struct gpmi_nand_data *this)
 994 {
 995         struct resources *r = &this->resources;
 996         void __iomem *gpmi_regs = r->gpmi_regs;
 997         unsigned int   clock_period_in_ns;
 998         uint32_t       reg;
 999         unsigned int   dll_wait_time_in_us;
1000         struct gpmi_nfc_hardware_timing  hw;
1001         int ret;
1002
1003         /* Enable the clock. */
1004         ret = gpmi_enable_clk(this);
1005         if (ret) {
1006                 dev_err(this->dev, "We failed in enable the clk\n");
1007                 goto err_out;
1008         }
1009
1010         /* Only initialize the timing once */
1011         if (this->flags & GPMI_TIMING_INIT_OK)
1012                 return;
1013         this->flags |= GPMI_TIMING_INIT_OK;
1014
1015         if (this->flags & GPMI_ASYNC_EDO_ENABLED)
1016                 gpmi_compute_edo_timing(this, &hw);
1017         else
1018                 gpmi_nfc_compute_hardware_timing(this, &hw);
1019
1020         /* [1] Set HW_GPMI_TIMING0 */
1021         reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
1022                 BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles)         |
1023                 BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles);
1024
1025         writel(reg, gpmi_regs + HW_GPMI_TIMING0);
1026
1027         /* [2] Set HW_GPMI_TIMING1 */
1028         writel(BF_GPMI_TIMING1_BUSY_TIMEOUT(hw.device_busy_timeout),
1029                 gpmi_regs + HW_GPMI_TIMING1);
1030
1031         /* [3] The following code is to set the HW_GPMI_CTRL1. */
1032
1033         /* Set the WRN_DLY_SEL */
1034         writel(BM_GPMI_CTRL1_WRN_DLY_SEL, gpmi_regs + HW_GPMI_CTRL1_CLR);
1035         writel(BF_GPMI_CTRL1_WRN_DLY_SEL(hw.wrn_dly_sel),
1036                                         gpmi_regs + HW_GPMI_CTRL1_SET);
1037
1038         /* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. */
1039         writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
1040
1041         /* Clear out the DLL control fields. */
1042         reg = BM_GPMI_CTRL1_RDN_DELAY | BM_GPMI_CTRL1_HALF_PERIOD;
1043         writel(reg, gpmi_regs + HW_GPMI_CTRL1_CLR);
1044
1045         /* If no sample delay is called for, return immediately. */
1046         if (!hw.sample_delay_factor)
1047                 return;
1048
1049         /* Set RDN_DELAY or HALF_PERIOD. */
1050         reg = ((hw.use_half_periods) ? BM_GPMI_CTRL1_HALF_PERIOD : 0)
1051                 | BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor);
1052
1053         writel(reg, gpmi_regs + HW_GPMI_CTRL1_SET);
1054
1055         /* At last, we enable the DLL. */
1056         writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
1057
1058         /*
1059          * After we enable the GPMI DLL, we have to wait 64 clock cycles before
1060          * we can use the GPMI. Calculate the amount of time we need to wait,
1061          * in microseconds.
1062          */
1063         clock_period_in_ns = NSEC_PER_SEC / clk_get_rate(r->clock[0]);
1064         dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
1065
1066         if (!dll_wait_time_in_us)
1067                 dll_wait_time_in_us = 1;
1068
1069         /* Wait for the DLL to settle. */
1070         udelay(dll_wait_time_in_us);
1071
1072 err_out:
1073         return;
1074 }
1075
1076 void gpmi_end(struct gpmi_nand_data *this)
1077 {
1078         gpmi_disable_clk(this);
1079 }
1080
1081 /* Clears a BCH interrupt. */
1082 void gpmi_clear_bch(struct gpmi_nand_data *this)
1083 {
1084         struct resources *r = &this->resources;
1085         writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
1086 }
1087
1088 /* Returns the Ready/Busy status of the given chip. */
1089 int gpmi_is_ready(struct gpmi_nand_data *this, unsigned chip)
1090 {
1091         struct resources *r = &this->resources;
1092         uint32_t mask = 0;
1093         uint32_t reg = 0;
1094
1095         if (GPMI_IS_MX23(this)) {
1096                 mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
1097                 reg = readl(r->gpmi_regs + HW_GPMI_DEBUG);
1098         } else if (GPMI_IS_MX28(this) || GPMI_IS_MX6(this)) {
1099                 /*
1100                  * In the imx6, all the ready/busy pins are bound
1101                  * together. So we only need to check chip 0.
1102                  */
1103                 if (GPMI_IS_MX6(this))
1104                         chip = 0;
1105
1106                 /* MX28 shares the same R/B register as MX6Q. */
1107                 mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip);
1108                 reg = readl(r->gpmi_regs + HW_GPMI_STAT);
1109         } else
1110                 dev_err(this->dev, "unknown arch.\n");
1111         return reg & mask;
1112 }
1113
1114 static inline void set_dma_type(struct gpmi_nand_data *this,
1115                                         enum dma_ops_type type)
1116 {
1117         this->last_dma_type = this->dma_type;
1118         this->dma_type = type;
1119 }
1120
1121 int gpmi_send_command(struct gpmi_nand_data *this)
1122 {
1123         struct dma_chan *channel = get_dma_chan(this);
1124         struct dma_async_tx_descriptor *desc;
1125         struct scatterlist *sgl;
1126         int chip = this->current_chip;
1127         u32 pio[3];
1128
1129         /* [1] send out the PIO words */
1130         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
1131                 | BM_GPMI_CTRL0_WORD_LENGTH
1132                 | BF_GPMI_CTRL0_CS(chip, this)
1133                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1134                 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
1135                 | BM_GPMI_CTRL0_ADDRESS_INCREMENT
1136                 | BF_GPMI_CTRL0_XFER_COUNT(this->command_length);
1137         pio[1] = pio[2] = 0;
1138         desc = dmaengine_prep_slave_sg(channel,
1139                                         (struct scatterlist *)pio,
1140                                         ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
1141         if (!desc)
1142                 return -EINVAL;
1143
1144         /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
1145         sgl = &this->cmd_sgl;
1146
1147         sg_init_one(sgl, this->cmd_buffer, this->command_length);
1148         dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
1149         desc = dmaengine_prep_slave_sg(channel,
1150                                 sgl, 1, DMA_MEM_TO_DEV,
1151                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1152         if (!desc)
1153                 return -EINVAL;
1154
1155         /* [3] submit the DMA */
1156         set_dma_type(this, DMA_FOR_COMMAND);
1157         return start_dma_without_bch_irq(this, desc);
1158 }
1159
1160 int gpmi_send_data(struct gpmi_nand_data *this)
1161 {
1162         struct dma_async_tx_descriptor *desc;
1163         struct dma_chan *channel = get_dma_chan(this);
1164         int chip = this->current_chip;
1165         uint32_t command_mode;
1166         uint32_t address;
1167         u32 pio[2];
1168
1169         /* [1] PIO */
1170         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
1171         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1172
1173         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1174                 | BM_GPMI_CTRL0_WORD_LENGTH
1175                 | BF_GPMI_CTRL0_CS(chip, this)
1176                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1177                 | BF_GPMI_CTRL0_ADDRESS(address)
1178                 | BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
1179         pio[1] = 0;
1180         desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
1181                                         ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
1182         if (!desc)
1183                 return -EINVAL;
1184
1185         /* [2] send DMA request */
1186         prepare_data_dma(this, DMA_TO_DEVICE);
1187         desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
1188                                         1, DMA_MEM_TO_DEV,
1189                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1190         if (!desc)
1191                 return -EINVAL;
1192
1193         /* [3] submit the DMA */
1194         set_dma_type(this, DMA_FOR_WRITE_DATA);
1195         return start_dma_without_bch_irq(this, desc);
1196 }
1197
1198 int gpmi_read_data(struct gpmi_nand_data *this)
1199 {
1200         struct dma_async_tx_descriptor *desc;
1201         struct dma_chan *channel = get_dma_chan(this);
1202         int chip = this->current_chip;
1203         u32 pio[2];
1204
1205         /* [1] : send PIO */
1206         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
1207                 | BM_GPMI_CTRL0_WORD_LENGTH
1208                 | BF_GPMI_CTRL0_CS(chip, this)
1209                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1210                 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
1211                 | BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
1212         pio[1] = 0;
1213         desc = dmaengine_prep_slave_sg(channel,
1214                                         (struct scatterlist *)pio,
1215                                         ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
1216         if (!desc)
1217                 return -EINVAL;
1218
1219         /* [2] : send DMA request */
1220         prepare_data_dma(this, DMA_FROM_DEVICE);
1221         desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
1222                                         1, DMA_DEV_TO_MEM,
1223                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1224         if (!desc)
1225                 return -EINVAL;
1226
1227         /* [3] : submit the DMA */
1228         set_dma_type(this, DMA_FOR_READ_DATA);
1229         return start_dma_without_bch_irq(this, desc);
1230 }
1231
1232 int gpmi_send_page(struct gpmi_nand_data *this,
1233                         dma_addr_t payload, dma_addr_t auxiliary)
1234 {
1235         struct bch_geometry *geo = &this->bch_geometry;
1236         uint32_t command_mode;
1237         uint32_t address;
1238         uint32_t ecc_command;
1239         uint32_t buffer_mask;
1240         struct dma_async_tx_descriptor *desc;
1241         struct dma_chan *channel = get_dma_chan(this);
1242         int chip = this->current_chip;
1243         u32 pio[6];
1244
1245         /* A DMA descriptor that does an ECC page read. */
1246         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
1247         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1248         ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
1249         buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
1250                                 BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
1251
1252         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1253                 | BM_GPMI_CTRL0_WORD_LENGTH
1254                 | BF_GPMI_CTRL0_CS(chip, this)
1255                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1256                 | BF_GPMI_CTRL0_ADDRESS(address)
1257                 | BF_GPMI_CTRL0_XFER_COUNT(0);
1258         pio[1] = 0;
1259         pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
1260                 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
1261                 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
1262         pio[3] = geo->page_size;
1263         pio[4] = payload;
1264         pio[5] = auxiliary;
1265
1266         desc = dmaengine_prep_slave_sg(channel,
1267                                         (struct scatterlist *)pio,
1268                                         ARRAY_SIZE(pio), DMA_TRANS_NONE,
1269                                         DMA_CTRL_ACK);
1270         if (!desc)
1271                 return -EINVAL;
1272
1273         set_dma_type(this, DMA_FOR_WRITE_ECC_PAGE);
1274         return start_dma_with_bch_irq(this, desc);
1275 }
1276
1277 int gpmi_read_page(struct gpmi_nand_data *this,
1278                                 dma_addr_t payload, dma_addr_t auxiliary)
1279 {
1280         struct bch_geometry *geo = &this->bch_geometry;
1281         uint32_t command_mode;
1282         uint32_t address;
1283         uint32_t ecc_command;
1284         uint32_t buffer_mask;
1285         struct dma_async_tx_descriptor *desc;
1286         struct dma_chan *channel = get_dma_chan(this);
1287         int chip = this->current_chip;
1288         u32 pio[6];
1289
1290         /* [1] Wait for the chip to report ready. */
1291         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
1292         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1293
1294         pio[0] =  BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1295                 | BM_GPMI_CTRL0_WORD_LENGTH
1296                 | BF_GPMI_CTRL0_CS(chip, this)
1297                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1298                 | BF_GPMI_CTRL0_ADDRESS(address)
1299                 | BF_GPMI_CTRL0_XFER_COUNT(0);
1300         pio[1] = 0;
1301         desc = dmaengine_prep_slave_sg(channel,
1302                                 (struct scatterlist *)pio, 2,
1303                                 DMA_TRANS_NONE, 0);
1304         if (!desc)
1305                 return -EINVAL;
1306
1307         /* [2] Enable the BCH block and read. */
1308         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
1309         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1310         ecc_command  = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
1311         buffer_mask  = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
1312                         | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
1313
1314         pio[0] =  BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1315                 | BM_GPMI_CTRL0_WORD_LENGTH
1316                 | BF_GPMI_CTRL0_CS(chip, this)
1317                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1318                 | BF_GPMI_CTRL0_ADDRESS(address)
1319                 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1320
1321         pio[1] = 0;
1322         pio[2] =  BM_GPMI_ECCCTRL_ENABLE_ECC
1323                 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
1324                 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
1325         pio[3] = geo->page_size;
1326         pio[4] = payload;
1327         pio[5] = auxiliary;
1328         desc = dmaengine_prep_slave_sg(channel,
1329                                         (struct scatterlist *)pio,
1330                                         ARRAY_SIZE(pio), DMA_TRANS_NONE,
1331                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1332         if (!desc)
1333                 return -EINVAL;
1334
1335         /* [3] Disable the BCH block */
1336         command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
1337         address      = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1338
1339         pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1340                 | BM_GPMI_CTRL0_WORD_LENGTH
1341                 | BF_GPMI_CTRL0_CS(chip, this)
1342                 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1343                 | BF_GPMI_CTRL0_ADDRESS(address)
1344                 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1345         pio[1] = 0;
1346         pio[2] = 0; /* clear GPMI_HW_GPMI_ECCCTRL, disable the BCH. */
1347         desc = dmaengine_prep_slave_sg(channel,
1348                                 (struct scatterlist *)pio, 3,
1349                                 DMA_TRANS_NONE,
1350                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1351         if (!desc)
1352                 return -EINVAL;
1353
1354         /* [4] submit the DMA */
1355         set_dma_type(this, DMA_FOR_READ_ECC_PAGE);
1356         return start_dma_with_bch_irq(this, desc);
1357 }
1358
1359 /**
1360  * gpmi_copy_bits - copy bits from one memory region to another
1361  * @dst: destination buffer
1362  * @dst_bit_off: bit offset we're starting to write at
1363  * @src: source buffer
1364  * @src_bit_off: bit offset we're starting to read from
1365  * @nbits: number of bits to copy
1366  *
1367  * This functions copies bits from one memory region to another, and is used by
1368  * the GPMI driver to copy ECC sections which are not guaranteed to be byte
1369  * aligned.
1370  *
1371  * src and dst should not overlap.
1372  *
1373  */
1374 void gpmi_copy_bits(u8 *dst, size_t dst_bit_off,
1375                     const u8 *src, size_t src_bit_off,
1376                     size_t nbits)
1377 {
1378         size_t i;
1379         size_t nbytes;
1380         u32 src_buffer = 0;
1381         size_t bits_in_src_buffer = 0;
1382
1383         if (!nbits)
1384                 return;
1385
1386         /*
1387          * Move src and dst pointers to the closest byte pointer and store bit
1388          * offsets within a byte.
1389          */
1390         src += src_bit_off / 8;
1391         src_bit_off %= 8;
1392
1393         dst += dst_bit_off / 8;
1394         dst_bit_off %= 8;
1395
1396         /*
1397          * Initialize the src_buffer value with bits available in the first
1398          * byte of data so that we end up with a byte aligned src pointer.
1399          */
1400         if (src_bit_off) {
1401                 src_buffer = src[0] >> src_bit_off;
1402                 if (nbits >= (8 - src_bit_off)) {
1403                         bits_in_src_buffer += 8 - src_bit_off;
1404                 } else {
1405                         src_buffer &= GENMASK(nbits - 1, 0);
1406                         bits_in_src_buffer += nbits;
1407                 }
1408                 nbits -= bits_in_src_buffer;
1409                 src++;
1410         }
1411
1412         /* Calculate the number of bytes that can be copied from src to dst. */
1413         nbytes = nbits / 8;
1414
1415         /* Try to align dst to a byte boundary. */
1416         if (dst_bit_off) {
1417                 if (bits_in_src_buffer < (8 - dst_bit_off) && nbytes) {
1418                         src_buffer |= src[0] << bits_in_src_buffer;
1419                         bits_in_src_buffer += 8;
1420                         src++;
1421                         nbytes--;
1422                 }
1423
1424                 if (bits_in_src_buffer >= (8 - dst_bit_off)) {
1425                         dst[0] &= GENMASK(dst_bit_off - 1, 0);
1426                         dst[0] |= src_buffer << dst_bit_off;
1427                         src_buffer >>= (8 - dst_bit_off);
1428                         bits_in_src_buffer -= (8 - dst_bit_off);
1429                         dst_bit_off = 0;
1430                         dst++;
1431                         if (bits_in_src_buffer > 7) {
1432                                 bits_in_src_buffer -= 8;
1433                                 dst[0] = src_buffer;
1434                                 dst++;
1435                                 src_buffer >>= 8;
1436                         }
1437                 }
1438         }
1439
1440         if (!bits_in_src_buffer && !dst_bit_off) {
1441                 /*
1442                  * Both src and dst pointers are byte aligned, thus we can
1443                  * just use the optimized memcpy function.
1444                  */
1445                 if (nbytes)
1446                         memcpy(dst, src, nbytes);
1447         } else {
1448                 /*
1449                  * src buffer is not byte aligned, hence we have to copy each
1450                  * src byte to the src_buffer variable before extracting a byte
1451                  * to store in dst.
1452                  */
1453                 for (i = 0; i < nbytes; i++) {
1454                         src_buffer |= src[i] << bits_in_src_buffer;
1455                         dst[i] = src_buffer;
1456                         src_buffer >>= 8;
1457                 }
1458         }
1459         /* Update dst and src pointers */
1460         dst += nbytes;
1461         src += nbytes;
1462
1463         /*
1464          * nbits is the number of remaining bits. It should not exceed 8 as
1465          * we've already copied as much bytes as possible.
1466          */
1467         nbits %= 8;
1468
1469         /*
1470          * If there's no more bits to copy to the destination and src buffer
1471          * was already byte aligned, then we're done.
1472          */
1473         if (!nbits && !bits_in_src_buffer)
1474                 return;
1475
1476         /* Copy the remaining bits to src_buffer */
1477         if (nbits)
1478                 src_buffer |= (*src & GENMASK(nbits - 1, 0)) <<
1479                               bits_in_src_buffer;
1480         bits_in_src_buffer += nbits;
1481
1482         /*
1483          * In case there were not enough bits to get a byte aligned dst buffer
1484          * prepare the src_buffer variable to match the dst organization (shift
1485          * src_buffer by dst_bit_off and retrieve the least significant bits
1486          * from dst).
1487          */
1488         if (dst_bit_off)
1489                 src_buffer = (src_buffer << dst_bit_off) |
1490                              (*dst & GENMASK(dst_bit_off - 1, 0));
1491         bits_in_src_buffer += dst_bit_off;
1492
1493         /*
1494          * Keep most significant bits from dst if we end up with an unaligned
1495          * number of bits.
1496          */
1497         nbytes = bits_in_src_buffer / 8;
1498         if (bits_in_src_buffer % 8) {
1499                 src_buffer |= (dst[nbytes] &
1500                                GENMASK(7, bits_in_src_buffer % 8)) <<
1501                               (nbytes * 8);
1502                 nbytes++;
1503         }
1504
1505         /* Copy the remaining bytes to dst */
1506         for (i = 0; i < nbytes; i++) {
1507                 dst[i] = src_buffer;
1508                 src_buffer >>= 8;
1509         }
1510 }