drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2017 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12
  13 #include <linux/stringify.h>
  14 #include <linux/kernel.h>
  15 #include <linux/timer.h>
  16 #include <linux/errno.h>
  17 #include <linux/ioport.h>
  18 #include <linux/slab.h>
  19 #include <linux/vmalloc.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/skbuff.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/bitops.h>
  27 #include <linux/io.h>
  28 #include <linux/irq.h>
  29 #include <linux/delay.h>
  30 #include <asm/byteorder.h>
  31 #include <asm/page.h>
  32 #include <linux/time.h>
  33 #include <linux/mii.h>
  34 #include <linux/if.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/rtc.h>
  37 #include <linux/bpf.h>
  38 #include <net/ip.h>
  39 #include <net/tcp.h>
  40 #include <net/udp.h>
  41 #include <net/checksum.h>
  42 #include <net/ip6_checksum.h>
  43 #include <net/udp_tunnel.h>
  44 #include <linux/workqueue.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/cache.h>
  47 #include <linux/log2.h>
  48 #include <linux/aer.h>
  49 #include <linux/bitmap.h>
  50 #include <linux/cpu_rmap.h>
  51
  52 #include "bnxt_hsi.h"
  53 #include "bnxt.h"
  54 #include "bnxt_ulp.h"
  55 #include "bnxt_sriov.h"
  56 #include "bnxt_ethtool.h"
  57 #include "bnxt_dcb.h"
  58 #include "bnxt_xdp.h"
  59
  60 #define BNXT_TX_TIMEOUT         (5 * HZ)
  61
  62 static const char version[] =
  63         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  64
  65 MODULE_LICENSE("GPL");
  66 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  67 MODULE_VERSION(DRV_MODULE_VERSION);
  68
  69 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  70 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  71 #define BNXT_RX_COPY_THRESH 256
  72
  73 #define BNXT_TX_PUSH_THRESH 164
  74
  75 enum board_idx {
  76         BCM57301,
  77         BCM57302,
  78         BCM57304,
  79         BCM57417_NPAR,
  80         BCM58700,
  81         BCM57311,
  82         BCM57312,
  83         BCM57402,
  84         BCM57404,
  85         BCM57406,
  86         BCM57402_NPAR,
  87         BCM57407,
  88         BCM57412,
  89         BCM57414,
  90         BCM57416,
  91         BCM57417,
  92         BCM57412_NPAR,
  93         BCM57314,
  94         BCM57417_SFP,
  95         BCM57416_SFP,
  96         BCM57404_NPAR,
  97         BCM57406_NPAR,
  98         BCM57407_SFP,
  99         BCM57407_NPAR,
 100         BCM57414_NPAR,
 101         BCM57416_NPAR,
 102         BCM57452,
 103         BCM57454,
 104         NETXTREME_E_VF,
 105         NETXTREME_C_VF,
 106 };
 107
 108 /* indexed by enum above */
 109 static const struct {
 110         char *name;
 111 } board_info[] = {
 112         { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
 113         { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
 114         { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 115         { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
 116         { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
 117         { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
 118         { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
 119         { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
 120         { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
 121         { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
 122         { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
 123         { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
 124         { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
 125         { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
 126         { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
 127         { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
 128         { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
 129         { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
 130         { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
 131         { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
 132         { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
 133         { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
 134         { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
 135         { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
 136         { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
 137         { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
 138         { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
 139         { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
 140         { "Broadcom NetXtreme-E Ethernet Virtual Function" },
 141         { "Broadcom NetXtreme-C Ethernet Virtual Function" },
 142 };
 143
 144 static const struct pci_device_id bnxt_pci_tbl[] = {
 145         { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
 146         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 147         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 148         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 149         { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
 150         { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
 151         { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
 152         { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
 153         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 154         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 155         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 156         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
 157         { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
 158         { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
 159         { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
 160         { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
 161         { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
 162         { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
 163         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 164         { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
 165         { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
 166         { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
 167         { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
 168         { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
 169         { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
 170         { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
 171         { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
 172         { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
 173         { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
 174         { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
 175         { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
 176         { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
 177 #ifdef CONFIG_BNXT_SRIOV
 178         { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
 179         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
 180         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
 181         { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
 182         { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
 183         { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
 184 #endif
 185         { 0 }
 186 };
 187
 188 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 189
 190 static const u16 bnxt_vf_req_snif[] = {
 191         HWRM_FUNC_CFG,
 192         HWRM_PORT_PHY_QCFG,
 193         HWRM_CFA_L2_FILTER_ALLOC,
 194 };
 195
 196 static const u16 bnxt_async_events_arr[] = {
 197         ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 198         ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 199         ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 200         ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 201         ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 202 };
 203
 204 static bool bnxt_vf_pciid(enum board_idx idx)
 205 {
 206         return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF);
 207 }
 208
 209 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 210 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 211 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 212
 213 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 214                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 215
 216 #define BNXT_CP_DB(db, raw_cons)                                        \
 217                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 218
 219 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 220                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 221
 222 const u16 bnxt_lhint_arr[] = {
 223         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 224         TX_BD_FLAGS_LHINT_512_TO_1023,
 225         TX_BD_FLAGS_LHINT_1024_TO_2047,
 226         TX_BD_FLAGS_LHINT_1024_TO_2047,
 227         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 228         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 229         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 230         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 231         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 232         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 233         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 234         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 235         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 236         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 237         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 238         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 239         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 240         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 241         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 242 };
 243
 244 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 245 {
 246         struct bnxt *bp = netdev_priv(dev);
 247         struct tx_bd *txbd;
 248         struct tx_bd_ext *txbd1;
 249         struct netdev_queue *txq;
 250         int i;
 251         dma_addr_t mapping;
 252         unsigned int length, pad = 0;
 253         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 254         u16 prod, last_frag;
 255         struct pci_dev *pdev = bp->pdev;
 256         struct bnxt_tx_ring_info *txr;
 257         struct bnxt_sw_tx_bd *tx_buf;
 258
 259         i = skb_get_queue_mapping(skb);
 260         if (unlikely(i >= bp->tx_nr_rings)) {
 261                 dev_kfree_skb_any(skb);
 262                 return NETDEV_TX_OK;
 263         }
 264
 265         txq = netdev_get_tx_queue(dev, i);
 266         txr = &bp->tx_ring[bp->tx_ring_map[i]];
 267         prod = txr->tx_prod;
 268
 269         free_size = bnxt_tx_avail(bp, txr);
 270         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 271                 netif_tx_stop_queue(txq);
 272                 return NETDEV_TX_BUSY;
 273         }
 274
 275         length = skb->len;
 276         len = skb_headlen(skb);
 277         last_frag = skb_shinfo(skb)->nr_frags;
 278
 279         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 280
 281         txbd->tx_bd_opaque = prod;
 282
 283         tx_buf = &txr->tx_buf_ring[prod];
 284         tx_buf->skb = skb;
 285         tx_buf->nr_frags = last_frag;
 286
 287         vlan_tag_flags = 0;
 288         cfa_action = 0;
 289         if (skb_vlan_tag_present(skb)) {
 290                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 291                                  skb_vlan_tag_get(skb);
 292                 /* Currently supports 8021Q, 8021AD vlan offloads
 293                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 294                  */
 295                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 296                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 297         }
 298
 299         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 300                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 301                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 302                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 303                 void *pdata = tx_push_buf->data;
 304                 u64 *end;
 305                 int j, push_len;
 306
 307                 /* Set COAL_NOW to be ready quickly for the next push */
 308                 tx_push->tx_bd_len_flags_type =
 309                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 310                                         TX_BD_TYPE_LONG_TX_BD |
 311                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 312                                         TX_BD_FLAGS_COAL_NOW |
 313                                         TX_BD_FLAGS_PACKET_END |
 314                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 315
 316                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 317                         tx_push1->tx_bd_hsize_lflags =
 318                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 319                 else
 320                         tx_push1->tx_bd_hsize_lflags = 0;
 321
 322                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 323                 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 324
 325                 end = pdata + length;
 326                 end = PTR_ALIGN(end, 8) - 1;
 327                 *end = 0;
 328
 329                 skb_copy_from_linear_data(skb, pdata, len);
 330                 pdata += len;
 331                 for (j = 0; j < last_frag; j++) {
 332                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 333                         void *fptr;
 334
 335                         fptr = skb_frag_address_safe(frag);
 336                         if (!fptr)
 337                                 goto normal_tx;
 338
 339                         memcpy(pdata, fptr, skb_frag_size(frag));
 340                         pdata += skb_frag_size(frag);
 341                 }
 342
 343                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 344                 txbd->tx_bd_haddr = txr->data_mapping;
 345                 prod = NEXT_TX(prod);
 346                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 347                 memcpy(txbd, tx_push1, sizeof(*txbd));
 348                 prod = NEXT_TX(prod);
 349                 tx_push->doorbell =
 350                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 351                 txr->tx_prod = prod;
 352
 353                 tx_buf->is_push = 1;
 354                 netdev_tx_sent_queue(txq, skb->len);
 355                 wmb();  /* Sync is_push and byte queue before pushing data */
 356
 357                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 358                 if (push_len > 16) {
 359                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 360                         __iowrite32_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 361                                          (push_len - 16) << 1);
 362                 } else {
 363                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 364                                          push_len);
 365                 }
 366
 367                 goto tx_done;
 368         }
 369
 370 normal_tx:
 371         if (length < BNXT_MIN_PKT_SIZE) {
 372                 pad = BNXT_MIN_PKT_SIZE - length;
 373                 if (skb_pad(skb, pad)) {
 374                         /* SKB already freed. */
 375                         tx_buf->skb = NULL;
 376                         return NETDEV_TX_OK;
 377                 }
 378                 length = BNXT_MIN_PKT_SIZE;
 379         }
 380
 381         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 382
 383         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 384                 dev_kfree_skb_any(skb);
 385                 tx_buf->skb = NULL;
 386                 return NETDEV_TX_OK;
 387         }
 388
 389         dma_unmap_addr_set(tx_buf, mapping, mapping);
 390         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 391                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 392
 393         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 394
 395         prod = NEXT_TX(prod);
 396         txbd1 = (struct tx_bd_ext *)
 397                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 398
 399         txbd1->tx_bd_hsize_lflags = 0;
 400         if (skb_is_gso(skb)) {
 401                 u32 hdr_len;
 402
 403                 if (skb->encapsulation)
 404                         hdr_len = skb_inner_network_offset(skb) +
 405                                 skb_inner_network_header_len(skb) +
 406                                 inner_tcp_hdrlen(skb);
 407                 else
 408                         hdr_len = skb_transport_offset(skb) +
 409                                 tcp_hdrlen(skb);
 410
 411                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 412                                         TX_BD_FLAGS_T_IPID |
 413                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 414                 length = skb_shinfo(skb)->gso_size;
 415                 txbd1->tx_bd_mss = cpu_to_le32(length);
 416                 length += hdr_len;
 417         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 418                 txbd1->tx_bd_hsize_lflags =
 419                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 420                 txbd1->tx_bd_mss = 0;
 421         }
 422
 423         length >>= 9;
 424         flags |= bnxt_lhint_arr[length];
 425         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 426
 427         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 428         txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 429         for (i = 0; i < last_frag; i++) {
 430                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 431
 432                 prod = NEXT_TX(prod);
 433                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 434
 435                 len = skb_frag_size(frag);
 436                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 437                                            DMA_TO_DEVICE);
 438
 439                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 440                         goto tx_dma_error;
 441
 442                 tx_buf = &txr->tx_buf_ring[prod];
 443                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 444
 445                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 446
 447                 flags = len << TX_BD_LEN_SHIFT;
 448                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 449         }
 450
 451         flags &= ~TX_BD_LEN;
 452         txbd->tx_bd_len_flags_type =
 453                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 454                             TX_BD_FLAGS_PACKET_END);
 455
 456         netdev_tx_sent_queue(txq, skb->len);
 457
 458         /* Sync BD data before updating doorbell */
 459         wmb();
 460
 461         prod = NEXT_TX(prod);
 462         txr->tx_prod = prod;
 463
 464         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 465         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 466
 467 tx_done:
 468
 469         mmiowb();
 470
 471         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 472                 netif_tx_stop_queue(txq);
 473
 474                 /* netif_tx_stop_queue() must be done before checking
 475                  * tx index in bnxt_tx_avail() below, because in
 476                  * bnxt_tx_int(), we update tx index before checking for
 477                  * netif_tx_queue_stopped().
 478                  */
 479                 smp_mb();
 480                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 481                         netif_tx_wake_queue(txq);
 482         }
 483         return NETDEV_TX_OK;
 484
 485 tx_dma_error:
 486         last_frag = i;
 487
 488         /* start back at beginning and unmap skb */
 489         prod = txr->tx_prod;
 490         tx_buf = &txr->tx_buf_ring[prod];
 491         tx_buf->skb = NULL;
 492         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 493                          skb_headlen(skb), PCI_DMA_TODEVICE);
 494         prod = NEXT_TX(prod);
 495
 496         /* unmap remaining mapped pages */
 497         for (i = 0; i < last_frag; i++) {
 498                 prod = NEXT_TX(prod);
 499                 tx_buf = &txr->tx_buf_ring[prod];
 500                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 501                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 502                                PCI_DMA_TODEVICE);
 503         }
 504
 505         dev_kfree_skb_any(skb);
 506         return NETDEV_TX_OK;
 507 }
 508
 509 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 510 {
 511         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 512         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
 513         u16 cons = txr->tx_cons;
 514         struct pci_dev *pdev = bp->pdev;
 515         int i;
 516         unsigned int tx_bytes = 0;
 517
 518         for (i = 0; i < nr_pkts; i++) {
 519                 struct bnxt_sw_tx_bd *tx_buf;
 520                 struct sk_buff *skb;
 521                 int j, last;
 522
 523                 tx_buf = &txr->tx_buf_ring[cons];
 524                 cons = NEXT_TX(cons);
 525                 skb = tx_buf->skb;
 526                 tx_buf->skb = NULL;
 527
 528                 if (tx_buf->is_push) {
 529                         tx_buf->is_push = 0;
 530                         goto next_tx_int;
 531                 }
 532
 533                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 534                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 535                 last = tx_buf->nr_frags;
 536
 537                 for (j = 0; j < last; j++) {
 538                         cons = NEXT_TX(cons);
 539                         tx_buf = &txr->tx_buf_ring[cons];
 540                         dma_unmap_page(
 541                                 &pdev->dev,
 542                                 dma_unmap_addr(tx_buf, mapping),
 543                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 544                                 PCI_DMA_TODEVICE);
 545                 }
 546
 547 next_tx_int:
 548                 cons = NEXT_TX(cons);
 549
 550                 tx_bytes += skb->len;
 551                 dev_kfree_skb_any(skb);
 552         }
 553
 554         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 555         txr->tx_cons = cons;
 556
 557         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 558          * before checking for netif_tx_queue_stopped().  Without the
 559          * memory barrier, there is a small possibility that bnxt_start_xmit()
 560          * will miss it and cause the queue to be stopped forever.
 561          */
 562         smp_mb();
 563
 564         if (unlikely(netif_tx_queue_stopped(txq)) &&
 565             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 566                 __netif_tx_lock(txq, smp_processor_id());
 567                 if (netif_tx_queue_stopped(txq) &&
 568                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 569                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 570                         netif_tx_wake_queue(txq);
 571                 __netif_tx_unlock(txq);
 572         }
 573 }
 574
 575 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
 576                                          gfp_t gfp)
 577 {
 578         struct device *dev = &bp->pdev->dev;
 579         struct page *page;
 580
 581         page = alloc_page(gfp);
 582         if (!page)
 583                 return NULL;
 584
 585         *mapping = dma_map_page(dev, page, 0, PAGE_SIZE, bp->rx_dir);
 586         if (dma_mapping_error(dev, *mapping)) {
 587                 __free_page(page);
 588                 return NULL;
 589         }
 590         *mapping += bp->rx_dma_offset;
 591         return page;
 592 }
 593
 594 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 595                                        gfp_t gfp)
 596 {
 597         u8 *data;
 598         struct pci_dev *pdev = bp->pdev;
 599
 600         data = kmalloc(bp->rx_buf_size, gfp);
 601         if (!data)
 602                 return NULL;
 603
 604         *mapping = dma_map_single(&pdev->dev, data + bp->rx_dma_offset,
 605                                   bp->rx_buf_use_size, bp->rx_dir);
 606
 607         if (dma_mapping_error(&pdev->dev, *mapping)) {
 608                 kfree(data);
 609                 data = NULL;
 610         }
 611         return data;
 612 }
 613
 614 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 615                        u16 prod, gfp_t gfp)
 616 {
 617         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 618         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 619         dma_addr_t mapping;
 620
 621         if (BNXT_RX_PAGE_MODE(bp)) {
 622                 struct page *page = __bnxt_alloc_rx_page(bp, &mapping, gfp);
 623
 624                 if (!page)
 625                         return -ENOMEM;
 626
 627                 rx_buf->data = page;
 628                 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
 629         } else {
 630                 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 631
 632                 if (!data)
 633                         return -ENOMEM;
 634
 635                 rx_buf->data = data;
 636                 rx_buf->data_ptr = data + bp->rx_offset;
 637         }
 638         rx_buf->mapping = mapping;
 639
 640         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 641         return 0;
 642 }
 643
 644 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
 645 {
 646         u16 prod = rxr->rx_prod;
 647         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 648         struct rx_bd *cons_bd, *prod_bd;
 649
 650         prod_rx_buf = &rxr->rx_buf_ring[prod];
 651         cons_rx_buf = &rxr->rx_buf_ring[cons];
 652
 653         prod_rx_buf->data = data;
 654         prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
 655
 656         prod_rx_buf->mapping = cons_rx_buf->mapping;
 657
 658         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 659         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 660
 661         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 662 }
 663
 664 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 665 {
 666         u16 next, max = rxr->rx_agg_bmap_size;
 667
 668         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 669         if (next >= max)
 670                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 671         return next;
 672 }
 673
 674 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 675                                      struct bnxt_rx_ring_info *rxr,
 676                                      u16 prod, gfp_t gfp)
 677 {
 678         struct rx_bd *rxbd =
 679                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 680         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 681         struct pci_dev *pdev = bp->pdev;
 682         struct page *page;
 683         dma_addr_t mapping;
 684         u16 sw_prod = rxr->rx_sw_agg_prod;
 685         unsigned int offset = 0;
 686
 687         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 688                 page = rxr->rx_page;
 689                 if (!page) {
 690                         page = alloc_page(gfp);
 691                         if (!page)
 692                                 return -ENOMEM;
 693                         rxr->rx_page = page;
 694                         rxr->rx_page_offset = 0;
 695                 }
 696                 offset = rxr->rx_page_offset;
 697                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 698                 if (rxr->rx_page_offset == PAGE_SIZE)
 699                         rxr->rx_page = NULL;
 700                 else
 701                         get_page(page);
 702         } else {
 703                 page = alloc_page(gfp);
 704                 if (!page)
 705                         return -ENOMEM;
 706         }
 707
 708         mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
 709                                PCI_DMA_FROMDEVICE);
 710         if (dma_mapping_error(&pdev->dev, mapping)) {
 711                 __free_page(page);
 712                 return -EIO;
 713         }
 714
 715         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 716                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 717
 718         __set_bit(sw_prod, rxr->rx_agg_bmap);
 719         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 720         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 721
 722         rx_agg_buf->page = page;
 723         rx_agg_buf->offset = offset;
 724         rx_agg_buf->mapping = mapping;
 725         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 726         rxbd->rx_bd_opaque = sw_prod;
 727         return 0;
 728 }
 729
 730 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 731                                    u32 agg_bufs)
 732 {
 733         struct bnxt *bp = bnapi->bp;
 734         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 735         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 736         u16 prod = rxr->rx_agg_prod;
 737         u16 sw_prod = rxr->rx_sw_agg_prod;
 738         u32 i;
 739
 740         for (i = 0; i < agg_bufs; i++) {
 741                 u16 cons;
 742                 struct rx_agg_cmp *agg;
 743                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 744                 struct rx_bd *prod_bd;
 745                 struct page *page;
 746
 747                 agg = (struct rx_agg_cmp *)
 748                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 749                 cons = agg->rx_agg_cmp_opaque;
 750                 __clear_bit(cons, rxr->rx_agg_bmap);
 751
 752                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 753                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 754
 755                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 756                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 757                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 758
 759                 /* It is possible for sw_prod to be equal to cons, so
 760                  * set cons_rx_buf->page to NULL first.
 761                  */
 762                 page = cons_rx_buf->page;
 763                 cons_rx_buf->page = NULL;
 764                 prod_rx_buf->page = page;
 765                 prod_rx_buf->offset = cons_rx_buf->offset;
 766
 767                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 768
 769                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 770
 771                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 772                 prod_bd->rx_bd_opaque = sw_prod;
 773
 774                 prod = NEXT_RX_AGG(prod);
 775                 sw_prod = NEXT_RX_AGG(sw_prod);
 776                 cp_cons = NEXT_CMP(cp_cons);
 777         }
 778         rxr->rx_agg_prod = prod;
 779         rxr->rx_sw_agg_prod = sw_prod;
 780 }
 781
 782 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
 783                                         struct bnxt_rx_ring_info *rxr,
 784                                         u16 cons, void *data, u8 *data_ptr,
 785                                         dma_addr_t dma_addr,
 786                                         unsigned int offset_and_len)
 787 {
 788         unsigned int payload = offset_and_len >> 16;
 789         unsigned int len = offset_and_len & 0xffff;
 790         struct skb_frag_struct *frag;
 791         struct page *page = data;
 792         u16 prod = rxr->rx_prod;
 793         struct sk_buff *skb;
 794         int off, err;
 795
 796         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 797         if (unlikely(err)) {
 798                 bnxt_reuse_rx_data(rxr, cons, data);
 799                 return NULL;
 800         }
 801         dma_addr -= bp->rx_dma_offset;
 802         dma_unmap_page(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir);
 803
 804         if (unlikely(!payload))
 805                 payload = eth_get_headlen(data_ptr, len);
 806
 807         skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
 808         if (!skb) {
 809                 __free_page(page);
 810                 return NULL;
 811         }
 812
 813         off = (void *)data_ptr - page_address(page);
 814         skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
 815         memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
 816                payload + NET_IP_ALIGN);
 817
 818         frag = &skb_shinfo(skb)->frags[0];
 819         skb_frag_size_sub(frag, payload);
 820         frag->page_offset += payload;
 821         skb->data_len -= payload;
 822         skb->tail += payload;
 823
 824         return skb;
 825 }
 826
 827 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 828                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 829                                    void *data, u8 *data_ptr,
 830                                    dma_addr_t dma_addr,
 831                                    unsigned int offset_and_len)
 832 {
 833         u16 prod = rxr->rx_prod;
 834         struct sk_buff *skb;
 835         int err;
 836
 837         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 838         if (unlikely(err)) {
 839                 bnxt_reuse_rx_data(rxr, cons, data);
 840                 return NULL;
 841         }
 842
 843         skb = build_skb(data, 0);
 844         dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 845                          bp->rx_dir);
 846         if (!skb) {
 847                 kfree(data);
 848                 return NULL;
 849         }
 850
 851         skb_reserve(skb, bp->rx_offset);
 852         skb_put(skb, offset_and_len & 0xffff);
 853         return skb;
 854 }
 855
 856 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 857                                      struct sk_buff *skb, u16 cp_cons,
 858                                      u32 agg_bufs)
 859 {
 860         struct pci_dev *pdev = bp->pdev;
 861         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 862         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 863         u16 prod = rxr->rx_agg_prod;
 864         u32 i;
 865
 866         for (i = 0; i < agg_bufs; i++) {
 867                 u16 cons, frag_len;
 868                 struct rx_agg_cmp *agg;
 869                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 870                 struct page *page;
 871                 dma_addr_t mapping;
 872
 873                 agg = (struct rx_agg_cmp *)
 874                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 875                 cons = agg->rx_agg_cmp_opaque;
 876                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 877                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 878
 879                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 880                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 881                                    cons_rx_buf->offset, frag_len);
 882                 __clear_bit(cons, rxr->rx_agg_bmap);
 883
 884                 /* It is possible for bnxt_alloc_rx_page() to allocate
 885                  * a sw_prod index that equals the cons index, so we
 886                  * need to clear the cons entry now.
 887                  */
 888                 mapping = cons_rx_buf->mapping;
 889                 page = cons_rx_buf->page;
 890                 cons_rx_buf->page = NULL;
 891
 892                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 893                         struct skb_shared_info *shinfo;
 894                         unsigned int nr_frags;
 895
 896                         shinfo = skb_shinfo(skb);
 897                         nr_frags = --shinfo->nr_frags;
 898                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 899
 900                         dev_kfree_skb(skb);
 901
 902                         cons_rx_buf->page = page;
 903
 904                         /* Update prod since possibly some pages have been
 905                          * allocated already.
 906                          */
 907                         rxr->rx_agg_prod = prod;
 908                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 909                         return NULL;
 910                 }
 911
 912                 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
 913                                PCI_DMA_FROMDEVICE);
 914
 915                 skb->data_len += frag_len;
 916                 skb->len += frag_len;
 917                 skb->truesize += PAGE_SIZE;
 918
 919                 prod = NEXT_RX_AGG(prod);
 920                 cp_cons = NEXT_CMP(cp_cons);
 921         }
 922         rxr->rx_agg_prod = prod;
 923         return skb;
 924 }
 925
 926 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 927                                u8 agg_bufs, u32 *raw_cons)
 928 {
 929         u16 last;
 930         struct rx_agg_cmp *agg;
 931
 932         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 933         last = RING_CMP(*raw_cons);
 934         agg = (struct rx_agg_cmp *)
 935                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 936         return RX_AGG_CMP_VALID(agg, *raw_cons);
 937 }
 938
 939 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 940                                             unsigned int len,
 941                                             dma_addr_t mapping)
 942 {
 943         struct bnxt *bp = bnapi->bp;
 944         struct pci_dev *pdev = bp->pdev;
 945         struct sk_buff *skb;
 946
 947         skb = napi_alloc_skb(&bnapi->napi, len);
 948         if (!skb)
 949                 return NULL;
 950
 951         dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
 952                                 bp->rx_dir);
 953
 954         memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
 955                len + NET_IP_ALIGN);
 956
 957         dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
 958                                    bp->rx_dir);
 959
 960         skb_put(skb, len);
 961         return skb;
 962 }
 963
 964 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
 965                            u32 *raw_cons, void *cmp)
 966 {
 967         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 968         struct rx_cmp *rxcmp = cmp;
 969         u32 tmp_raw_cons = *raw_cons;
 970         u8 cmp_type, agg_bufs = 0;
 971
 972         cmp_type = RX_CMP_TYPE(rxcmp);
 973
 974         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
 975                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
 976                             RX_CMP_AGG_BUFS) >>
 977                            RX_CMP_AGG_BUFS_SHIFT;
 978         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
 979                 struct rx_tpa_end_cmp *tpa_end = cmp;
 980
 981                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 982                             RX_TPA_END_CMP_AGG_BUFS) >>
 983                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
 984         }
 985
 986         if (agg_bufs) {
 987                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
 988                         return -EBUSY;
 989         }
 990         *raw_cons = tmp_raw_cons;
 991         return 0;
 992 }
 993
 994 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
 995 {
 996         if (!rxr->bnapi->in_reset) {
 997                 rxr->bnapi->in_reset = true;
 998                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
 999                 schedule_work(&bp->sp_task);
1000         }
1001         rxr->rx_next_cons = 0xffff;
1002 }
1003
1004 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1005                            struct rx_tpa_start_cmp *tpa_start,
1006                            struct rx_tpa_start_cmp_ext *tpa_start1)
1007 {
1008         u8 agg_id = TPA_START_AGG_ID(tpa_start);
1009         u16 cons, prod;
1010         struct bnxt_tpa_info *tpa_info;
1011         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1012         struct rx_bd *prod_bd;
1013         dma_addr_t mapping;
1014
1015         cons = tpa_start->rx_tpa_start_cmp_opaque;
1016         prod = rxr->rx_prod;
1017         cons_rx_buf = &rxr->rx_buf_ring[cons];
1018         prod_rx_buf = &rxr->rx_buf_ring[prod];
1019         tpa_info = &rxr->rx_tpa[agg_id];
1020
1021         if (unlikely(cons != rxr->rx_next_cons)) {
1022                 bnxt_sched_reset(bp, rxr);
1023                 return;
1024         }
1025
1026         prod_rx_buf->data = tpa_info->data;
1027         prod_rx_buf->data_ptr = tpa_info->data_ptr;
1028
1029         mapping = tpa_info->mapping;
1030         prod_rx_buf->mapping = mapping;
1031
1032         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1033
1034         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1035
1036         tpa_info->data = cons_rx_buf->data;
1037         tpa_info->data_ptr = cons_rx_buf->data_ptr;
1038         cons_rx_buf->data = NULL;
1039         tpa_info->mapping = cons_rx_buf->mapping;
1040
1041         tpa_info->len =
1042                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1043                                 RX_TPA_START_CMP_LEN_SHIFT;
1044         if (likely(TPA_START_HASH_VALID(tpa_start))) {
1045                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1046
1047                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1048                 tpa_info->gso_type = SKB_GSO_TCPV4;
1049                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1050                 if (hash_type == 3)
1051                         tpa_info->gso_type = SKB_GSO_TCPV6;
1052                 tpa_info->rss_hash =
1053                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1054         } else {
1055                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1056                 tpa_info->gso_type = 0;
1057                 if (netif_msg_rx_err(bp))
1058                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
1059         }
1060         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1061         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1062         tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1063
1064         rxr->rx_prod = NEXT_RX(prod);
1065         cons = NEXT_RX(cons);
1066         rxr->rx_next_cons = NEXT_RX(cons);
1067         cons_rx_buf = &rxr->rx_buf_ring[cons];
1068
1069         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1070         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1071         cons_rx_buf->data = NULL;
1072 }
1073
1074 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
1075                            u16 cp_cons, u32 agg_bufs)
1076 {
1077         if (agg_bufs)
1078                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1079 }
1080
1081 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1082                                            int payload_off, int tcp_ts,
1083                                            struct sk_buff *skb)
1084 {
1085 #ifdef CONFIG_INET
1086         struct tcphdr *th;
1087         int len, nw_off;
1088         u16 outer_ip_off, inner_ip_off, inner_mac_off;
1089         u32 hdr_info = tpa_info->hdr_info;
1090         bool loopback = false;
1091
1092         inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1093         inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1094         outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1095
1096         /* If the packet is an internal loopback packet, the offsets will
1097          * have an extra 4 bytes.
1098          */
1099         if (inner_mac_off == 4) {
1100                 loopback = true;
1101         } else if (inner_mac_off > 4) {
1102                 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1103                                             ETH_HLEN - 2));
1104
1105                 /* We only support inner iPv4/ipv6.  If we don't see the
1106                  * correct protocol ID, it must be a loopback packet where
1107                  * the offsets are off by 4.
1108                  */
1109                 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1110                         loopback = true;
1111         }
1112         if (loopback) {
1113                 /* internal loopback packet, subtract all offsets by 4 */
1114                 inner_ip_off -= 4;
1115                 inner_mac_off -= 4;
1116                 outer_ip_off -= 4;
1117         }
1118
1119         nw_off = inner_ip_off - ETH_HLEN;
1120         skb_set_network_header(skb, nw_off);
1121         if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1122                 struct ipv6hdr *iph = ipv6_hdr(skb);
1123
1124                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1125                 len = skb->len - skb_transport_offset(skb);
1126                 th = tcp_hdr(skb);
1127                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1128         } else {
1129                 struct iphdr *iph = ip_hdr(skb);
1130
1131                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1132                 len = skb->len - skb_transport_offset(skb);
1133                 th = tcp_hdr(skb);
1134                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1135         }
1136
1137         if (inner_mac_off) { /* tunnel */
1138                 struct udphdr *uh = NULL;
1139                 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1140                                             ETH_HLEN - 2));
1141
1142                 if (proto == htons(ETH_P_IP)) {
1143                         struct iphdr *iph = (struct iphdr *)skb->data;
1144
1145                         if (iph->protocol == IPPROTO_UDP)
1146                                 uh = (struct udphdr *)(iph + 1);
1147                 } else {
1148                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1149
1150                         if (iph->nexthdr == IPPROTO_UDP)
1151                                 uh = (struct udphdr *)(iph + 1);
1152                 }
1153                 if (uh) {
1154                         if (uh->check)
1155                                 skb_shinfo(skb)->gso_type |=
1156                                         SKB_GSO_UDP_TUNNEL_CSUM;
1157                         else
1158                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1159                 }
1160         }
1161 #endif
1162         return skb;
1163 }
1164
1165 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
1166 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1167
1168 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1169                                            int payload_off, int tcp_ts,
1170                                            struct sk_buff *skb)
1171 {
1172 #ifdef CONFIG_INET
1173         struct tcphdr *th;
1174         int len, nw_off, tcp_opt_len = 0;
1175
1176         if (tcp_ts)
1177                 tcp_opt_len = 12;
1178
1179         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1180                 struct iphdr *iph;
1181
1182                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1183                          ETH_HLEN;
1184                 skb_set_network_header(skb, nw_off);
1185                 iph = ip_hdr(skb);
1186                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1187                 len = skb->len - skb_transport_offset(skb);
1188                 th = tcp_hdr(skb);
1189                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1190         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1191                 struct ipv6hdr *iph;
1192
1193                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1194                          ETH_HLEN;
1195                 skb_set_network_header(skb, nw_off);
1196                 iph = ipv6_hdr(skb);
1197                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1198                 len = skb->len - skb_transport_offset(skb);
1199                 th = tcp_hdr(skb);
1200                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1201         } else {
1202                 dev_kfree_skb_any(skb);
1203                 return NULL;
1204         }
1205
1206         if (nw_off) { /* tunnel */
1207                 struct udphdr *uh = NULL;
1208
1209                 if (skb->protocol == htons(ETH_P_IP)) {
1210                         struct iphdr *iph = (struct iphdr *)skb->data;
1211
1212                         if (iph->protocol == IPPROTO_UDP)
1213                                 uh = (struct udphdr *)(iph + 1);
1214                 } else {
1215                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1216
1217                         if (iph->nexthdr == IPPROTO_UDP)
1218                                 uh = (struct udphdr *)(iph + 1);
1219                 }
1220                 if (uh) {
1221                         if (uh->check)
1222                                 skb_shinfo(skb)->gso_type |=
1223                                         SKB_GSO_UDP_TUNNEL_CSUM;
1224                         else
1225                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1226                 }
1227         }
1228 #endif
1229         return skb;
1230 }
1231
1232 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1233                                            struct bnxt_tpa_info *tpa_info,
1234                                            struct rx_tpa_end_cmp *tpa_end,
1235                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1236                                            struct sk_buff *skb)
1237 {
1238 #ifdef CONFIG_INET
1239         int payload_off;
1240         u16 segs;
1241
1242         segs = TPA_END_TPA_SEGS(tpa_end);
1243         if (segs == 1)
1244                 return skb;
1245
1246         NAPI_GRO_CB(skb)->count = segs;
1247         skb_shinfo(skb)->gso_size =
1248                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1249         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1250         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1251                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
1252                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
1253         skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1254         if (likely(skb))
1255                 tcp_gro_complete(skb);
1256 #endif
1257         return skb;
1258 }
1259
1260 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1261                                            struct bnxt_napi *bnapi,
1262                                            u32 *raw_cons,
1263                                            struct rx_tpa_end_cmp *tpa_end,
1264                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1265                                            u8 *event)
1266 {
1267         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1268         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1269         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1270         u8 *data_ptr, agg_bufs;
1271         u16 cp_cons = RING_CMP(*raw_cons);
1272         unsigned int len;
1273         struct bnxt_tpa_info *tpa_info;
1274         dma_addr_t mapping;
1275         struct sk_buff *skb;
1276         void *data;
1277
1278         if (unlikely(bnapi->in_reset)) {
1279                 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1280
1281                 if (rc < 0)
1282                         return ERR_PTR(-EBUSY);
1283                 return NULL;
1284         }
1285
1286         tpa_info = &rxr->rx_tpa[agg_id];
1287         data = tpa_info->data;
1288         data_ptr = tpa_info->data_ptr;
1289         prefetch(data_ptr);
1290         len = tpa_info->len;
1291         mapping = tpa_info->mapping;
1292
1293         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1294                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1295
1296         if (agg_bufs) {
1297                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1298                         return ERR_PTR(-EBUSY);
1299
1300                 *event |= BNXT_AGG_EVENT;
1301                 cp_cons = NEXT_CMP(cp_cons);
1302         }
1303
1304         if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1305                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1306                 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1307                             agg_bufs, (int)MAX_SKB_FRAGS);
1308                 return NULL;
1309         }
1310
1311         if (len <= bp->rx_copy_thresh) {
1312                 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1313                 if (!skb) {
1314                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1315                         return NULL;
1316                 }
1317         } else {
1318                 u8 *new_data;
1319                 dma_addr_t new_mapping;
1320
1321                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1322                 if (!new_data) {
1323                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1324                         return NULL;
1325                 }
1326
1327                 tpa_info->data = new_data;
1328                 tpa_info->data_ptr = new_data + bp->rx_offset;
1329                 tpa_info->mapping = new_mapping;
1330
1331                 skb = build_skb(data, 0);
1332                 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1333                                  bp->rx_dir);
1334
1335                 if (!skb) {
1336                         kfree(data);
1337                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1338                         return NULL;
1339                 }
1340                 skb_reserve(skb, bp->rx_offset);
1341                 skb_put(skb, len);
1342         }
1343
1344         if (agg_bufs) {
1345                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1346                 if (!skb) {
1347                         /* Page reuse already handled by bnxt_rx_pages(). */
1348                         return NULL;
1349                 }
1350         }
1351         skb->protocol = eth_type_trans(skb, bp->dev);
1352
1353         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1354                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1355
1356         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1357             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1358                 u16 vlan_proto = tpa_info->metadata >>
1359                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1360                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
1361
1362                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1363         }
1364
1365         skb_checksum_none_assert(skb);
1366         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1367                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1368                 skb->csum_level =
1369                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1370         }
1371
1372         if (TPA_END_GRO(tpa_end))
1373                 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1374
1375         return skb;
1376 }
1377
1378 /* returns the following:
1379  * 1       - 1 packet successfully received
1380  * 0       - successful TPA_START, packet not completed yet
1381  * -EBUSY  - completion ring does not have all the agg buffers yet
1382  * -ENOMEM - packet aborted due to out of memory
1383  * -EIO    - packet aborted due to hw error indicated in BD
1384  */
1385 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1386                        u8 *event)
1387 {
1388         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1389         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1390         struct net_device *dev = bp->dev;
1391         struct rx_cmp *rxcmp;
1392         struct rx_cmp_ext *rxcmp1;
1393         u32 tmp_raw_cons = *raw_cons;
1394         u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1395         struct bnxt_sw_rx_bd *rx_buf;
1396         unsigned int len;
1397         u8 *data_ptr, agg_bufs, cmp_type;
1398         dma_addr_t dma_addr;
1399         struct sk_buff *skb;
1400         void *data;
1401         int rc = 0;
1402         u32 misc;
1403
1404         rxcmp = (struct rx_cmp *)
1405                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1406
1407         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1408         cp_cons = RING_CMP(tmp_raw_cons);
1409         rxcmp1 = (struct rx_cmp_ext *)
1410                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1411
1412         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1413                 return -EBUSY;
1414
1415         cmp_type = RX_CMP_TYPE(rxcmp);
1416
1417         prod = rxr->rx_prod;
1418
1419         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1420                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1421                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1422
1423                 *event |= BNXT_RX_EVENT;
1424                 goto next_rx_no_prod;
1425
1426         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1427                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1428                                    (struct rx_tpa_end_cmp *)rxcmp,
1429                                    (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1430
1431                 if (unlikely(IS_ERR(skb)))
1432                         return -EBUSY;
1433
1434                 rc = -ENOMEM;
1435                 if (likely(skb)) {
1436                         skb_record_rx_queue(skb, bnapi->index);
1437                         napi_gro_receive(&bnapi->napi, skb);
1438                         rc = 1;
1439                 }
1440                 *event |= BNXT_RX_EVENT;
1441                 goto next_rx_no_prod;
1442         }
1443
1444         cons = rxcmp->rx_cmp_opaque;
1445         rx_buf = &rxr->rx_buf_ring[cons];
1446         data = rx_buf->data;
1447         data_ptr = rx_buf->data_ptr;
1448         if (unlikely(cons != rxr->rx_next_cons)) {
1449                 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1450
1451                 bnxt_sched_reset(bp, rxr);
1452                 return rc1;
1453         }
1454         prefetch(data_ptr);
1455
1456         misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1457         agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1458
1459         if (agg_bufs) {
1460                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1461                         return -EBUSY;
1462
1463                 cp_cons = NEXT_CMP(cp_cons);
1464                 *event |= BNXT_AGG_EVENT;
1465         }
1466         *event |= BNXT_RX_EVENT;
1467
1468         rx_buf->data = NULL;
1469         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1470                 bnxt_reuse_rx_data(rxr, cons, data);
1471                 if (agg_bufs)
1472                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1473
1474                 rc = -EIO;
1475                 goto next_rx;
1476         }
1477
1478         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1479         dma_addr = rx_buf->mapping;
1480
1481         if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1482                 rc = 1;
1483                 goto next_rx;
1484         }
1485
1486         if (len <= bp->rx_copy_thresh) {
1487                 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1488                 bnxt_reuse_rx_data(rxr, cons, data);
1489                 if (!skb) {
1490                         rc = -ENOMEM;
1491                         goto next_rx;
1492                 }
1493         } else {
1494                 u32 payload;
1495
1496                 if (rx_buf->data_ptr == data_ptr)
1497                         payload = misc & RX_CMP_PAYLOAD_OFFSET;
1498                 else
1499                         payload = 0;
1500                 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1501                                       payload | len);
1502                 if (!skb) {
1503                         rc = -ENOMEM;
1504                         goto next_rx;
1505                 }
1506         }
1507
1508         if (agg_bufs) {
1509                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1510                 if (!skb) {
1511                         rc = -ENOMEM;
1512                         goto next_rx;
1513                 }
1514         }
1515
1516         if (RX_CMP_HASH_VALID(rxcmp)) {
1517                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1518                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1519
1520                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1521                 if (hash_type != 1 && hash_type != 3)
1522                         type = PKT_HASH_TYPE_L3;
1523                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1524         }
1525
1526         skb->protocol = eth_type_trans(skb, dev);
1527
1528         if ((rxcmp1->rx_cmp_flags2 &
1529              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1530             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1531                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1532                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
1533                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1534
1535                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1536         }
1537
1538         skb_checksum_none_assert(skb);
1539         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1540                 if (dev->features & NETIF_F_RXCSUM) {
1541                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1542                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1543                 }
1544         } else {
1545                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1546                         if (dev->features & NETIF_F_RXCSUM)
1547                                 cpr->rx_l4_csum_errors++;
1548                 }
1549         }
1550
1551         skb_record_rx_queue(skb, bnapi->index);
1552         napi_gro_receive(&bnapi->napi, skb);
1553         rc = 1;
1554
1555 next_rx:
1556         rxr->rx_prod = NEXT_RX(prod);
1557         rxr->rx_next_cons = NEXT_RX(cons);
1558
1559 next_rx_no_prod:
1560         *raw_cons = tmp_raw_cons;
1561
1562         return rc;
1563 }
1564
1565 #define BNXT_GET_EVENT_PORT(data)       \
1566         ((data) &                       \
1567          ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1568
1569 static int bnxt_async_event_process(struct bnxt *bp,
1570                                     struct hwrm_async_event_cmpl *cmpl)
1571 {
1572         u16 event_id = le16_to_cpu(cmpl->event_id);
1573
1574         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1575         switch (event_id) {
1576         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1577                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1578                 struct bnxt_link_info *link_info = &bp->link_info;
1579
1580                 if (BNXT_VF(bp))
1581                         goto async_event_process_exit;
1582                 if (data1 & 0x20000) {
1583                         u16 fw_speed = link_info->force_link_speed;
1584                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1585
1586                         netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1587                                     speed);
1588                 }
1589                 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1590                 /* fall thru */
1591         }
1592         case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1593                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1594                 break;
1595         case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1596                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1597                 break;
1598         case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1599                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1600                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1601
1602                 if (BNXT_VF(bp))
1603                         break;
1604
1605                 if (bp->pf.port_id != port_id)
1606                         break;
1607
1608                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1609                 break;
1610         }
1611         case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1612                 if (BNXT_PF(bp))
1613                         goto async_event_process_exit;
1614                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1615                 break;
1616         default:
1617                 goto async_event_process_exit;
1618         }
1619         schedule_work(&bp->sp_task);
1620 async_event_process_exit:
1621         bnxt_ulp_async_events(bp, cmpl);
1622         return 0;
1623 }
1624
1625 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1626 {
1627         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1628         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1629         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1630                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1631
1632         switch (cmpl_type) {
1633         case CMPL_BASE_TYPE_HWRM_DONE:
1634                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1635                 if (seq_id == bp->hwrm_intr_seq_id)
1636                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1637                 else
1638                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1639                 break;
1640
1641         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1642                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1643
1644                 if ((vf_id < bp->pf.first_vf_id) ||
1645                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1646                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1647                                    vf_id);
1648                         return -EINVAL;
1649                 }
1650
1651                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1652                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1653                 schedule_work(&bp->sp_task);
1654                 break;
1655
1656         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1657                 bnxt_async_event_process(bp,
1658                                          (struct hwrm_async_event_cmpl *)txcmp);
1659
1660         default:
1661                 break;
1662         }
1663
1664         return 0;
1665 }
1666
1667 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1668 {
1669         struct bnxt_napi *bnapi = dev_instance;
1670         struct bnxt *bp = bnapi->bp;
1671         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1672         u32 cons = RING_CMP(cpr->cp_raw_cons);
1673
1674         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1675         napi_schedule(&bnapi->napi);
1676         return IRQ_HANDLED;
1677 }
1678
1679 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1680 {
1681         u32 raw_cons = cpr->cp_raw_cons;
1682         u16 cons = RING_CMP(raw_cons);
1683         struct tx_cmp *txcmp;
1684
1685         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1686
1687         return TX_CMP_VALID(txcmp, raw_cons);
1688 }
1689
1690 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1691 {
1692         struct bnxt_napi *bnapi = dev_instance;
1693         struct bnxt *bp = bnapi->bp;
1694         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1695         u32 cons = RING_CMP(cpr->cp_raw_cons);
1696         u32 int_status;
1697
1698         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1699
1700         if (!bnxt_has_work(bp, cpr)) {
1701                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1702                 /* return if erroneous interrupt */
1703                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1704                         return IRQ_NONE;
1705         }
1706
1707         /* disable ring IRQ */
1708         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1709
1710         /* Return here if interrupt is shared and is disabled. */
1711         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1712                 return IRQ_HANDLED;
1713
1714         napi_schedule(&bnapi->napi);
1715         return IRQ_HANDLED;
1716 }
1717
1718 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1719 {
1720         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1721         u32 raw_cons = cpr->cp_raw_cons;
1722         u32 cons;
1723         int tx_pkts = 0;
1724         int rx_pkts = 0;
1725         u8 event = 0;
1726         struct tx_cmp *txcmp;
1727
1728         while (1) {
1729                 int rc;
1730
1731                 cons = RING_CMP(raw_cons);
1732                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1733
1734                 if (!TX_CMP_VALID(txcmp, raw_cons))
1735                         break;
1736
1737                 /* The valid test of the entry must be done first before
1738                  * reading any further.
1739                  */
1740                 dma_rmb();
1741                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1742                         tx_pkts++;
1743                         /* return full budget so NAPI will complete. */
1744                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1745                                 rx_pkts = budget;
1746                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1747                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1748                         if (likely(rc >= 0))
1749                                 rx_pkts += rc;
1750                         else if (rc == -EBUSY)  /* partial completion */
1751                                 break;
1752                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1753                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1754                                     (TX_CMP_TYPE(txcmp) ==
1755                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1756                                     (TX_CMP_TYPE(txcmp) ==
1757                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1758                         bnxt_hwrm_handler(bp, txcmp);
1759                 }
1760                 raw_cons = NEXT_RAW_CMP(raw_cons);
1761
1762                 if (rx_pkts == budget)
1763                         break;
1764         }
1765
1766         if (event & BNXT_TX_EVENT) {
1767                 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
1768                 void __iomem *db = txr->tx_doorbell;
1769                 u16 prod = txr->tx_prod;
1770
1771                 /* Sync BD data before updating doorbell */
1772                 wmb();
1773
1774                 writel(DB_KEY_TX | prod, db);
1775                 writel(DB_KEY_TX | prod, db);
1776         }
1777
1778         cpr->cp_raw_cons = raw_cons;
1779         /* ACK completion ring before freeing tx ring and producing new
1780          * buffers in rx/agg rings to prevent overflowing the completion
1781          * ring.
1782          */
1783         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1784
1785         if (tx_pkts)
1786                 bnapi->tx_int(bp, bnapi, tx_pkts);
1787
1788         if (event & BNXT_RX_EVENT) {
1789                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1790
1791                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1792                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1793                 if (event & BNXT_AGG_EVENT) {
1794                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1795                                rxr->rx_agg_doorbell);
1796                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1797                                rxr->rx_agg_doorbell);
1798                 }
1799         }
1800         return rx_pkts;
1801 }
1802
1803 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
1804 {
1805         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1806         struct bnxt *bp = bnapi->bp;
1807         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1808         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1809         struct tx_cmp *txcmp;
1810         struct rx_cmp_ext *rxcmp1;
1811         u32 cp_cons, tmp_raw_cons;
1812         u32 raw_cons = cpr->cp_raw_cons;
1813         u32 rx_pkts = 0;
1814         u8 event = 0;
1815
1816         while (1) {
1817                 int rc;
1818
1819                 cp_cons = RING_CMP(raw_cons);
1820                 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1821
1822                 if (!TX_CMP_VALID(txcmp, raw_cons))
1823                         break;
1824
1825                 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1826                         tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
1827                         cp_cons = RING_CMP(tmp_raw_cons);
1828                         rxcmp1 = (struct rx_cmp_ext *)
1829                           &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1830
1831                         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1832                                 break;
1833
1834                         /* force an error to recycle the buffer */
1835                         rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1836                                 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1837
1838                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &event);
1839                         if (likely(rc == -EIO))
1840                                 rx_pkts++;
1841                         else if (rc == -EBUSY)  /* partial completion */
1842                                 break;
1843                 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
1844                                     CMPL_BASE_TYPE_HWRM_DONE)) {
1845                         bnxt_hwrm_handler(bp, txcmp);
1846                 } else {
1847                         netdev_err(bp->dev,
1848                                    "Invalid completion received on special ring\n");
1849                 }
1850                 raw_cons = NEXT_RAW_CMP(raw_cons);
1851
1852                 if (rx_pkts == budget)
1853                         break;
1854         }
1855
1856         cpr->cp_raw_cons = raw_cons;
1857         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1858         writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1859         writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1860
1861         if (event & BNXT_AGG_EVENT) {
1862                 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1863                 writel(DB_KEY_RX | rxr->rx_agg_prod, rxr->rx_agg_doorbell);
1864         }
1865
1866         if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
1867                 napi_complete_done(napi, rx_pkts);
1868                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1869         }
1870         return rx_pkts;
1871 }
1872
1873 static int bnxt_poll(struct napi_struct *napi, int budget)
1874 {
1875         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1876         struct bnxt *bp = bnapi->bp;
1877         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1878         int work_done = 0;
1879
1880         while (1) {
1881                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1882
1883                 if (work_done >= budget)
1884                         break;
1885
1886                 if (!bnxt_has_work(bp, cpr)) {
1887                         if (napi_complete_done(napi, work_done))
1888                                 BNXT_CP_DB_REARM(cpr->cp_doorbell,
1889                                                  cpr->cp_raw_cons);
1890                         break;
1891                 }
1892         }
1893         mmiowb();
1894         return work_done;
1895 }
1896
1897 static void bnxt_free_tx_skbs(struct bnxt *bp)
1898 {
1899         int i, max_idx;
1900         struct pci_dev *pdev = bp->pdev;
1901
1902         if (!bp->tx_ring)
1903                 return;
1904
1905         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1906         for (i = 0; i < bp->tx_nr_rings; i++) {
1907                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1908                 int j;
1909
1910                 for (j = 0; j < max_idx;) {
1911                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1912                         struct sk_buff *skb = tx_buf->skb;
1913                         int k, last;
1914
1915                         if (!skb) {
1916                                 j++;
1917                                 continue;
1918                         }
1919
1920                         tx_buf->skb = NULL;
1921
1922                         if (tx_buf->is_push) {
1923                                 dev_kfree_skb(skb);
1924                                 j += 2;
1925                                 continue;
1926                         }
1927
1928                         dma_unmap_single(&pdev->dev,
1929                                          dma_unmap_addr(tx_buf, mapping),
1930                                          skb_headlen(skb),
1931                                          PCI_DMA_TODEVICE);
1932
1933                         last = tx_buf->nr_frags;
1934                         j += 2;
1935                         for (k = 0; k < last; k++, j++) {
1936                                 int ring_idx = j & bp->tx_ring_mask;
1937                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1938
1939                                 tx_buf = &txr->tx_buf_ring[ring_idx];
1940                                 dma_unmap_page(
1941                                         &pdev->dev,
1942                                         dma_unmap_addr(tx_buf, mapping),
1943                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
1944                         }
1945                         dev_kfree_skb(skb);
1946                 }
1947                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1948         }
1949 }
1950
1951 static void bnxt_free_rx_skbs(struct bnxt *bp)
1952 {
1953         int i, max_idx, max_agg_idx;
1954         struct pci_dev *pdev = bp->pdev;
1955
1956         if (!bp->rx_ring)
1957                 return;
1958
1959         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1960         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1961         for (i = 0; i < bp->rx_nr_rings; i++) {
1962                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1963                 int j;
1964
1965                 if (rxr->rx_tpa) {
1966                         for (j = 0; j < MAX_TPA; j++) {
1967                                 struct bnxt_tpa_info *tpa_info =
1968                                                         &rxr->rx_tpa[j];
1969                                 u8 *data = tpa_info->data;
1970
1971                                 if (!data)
1972                                         continue;
1973
1974                                 dma_unmap_single(&pdev->dev, tpa_info->mapping,
1975                                                  bp->rx_buf_use_size,
1976                                                  bp->rx_dir);
1977
1978                                 tpa_info->data = NULL;
1979
1980                                 kfree(data);
1981                         }
1982                 }
1983
1984                 for (j = 0; j < max_idx; j++) {
1985                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1986                         dma_addr_t mapping = rx_buf->mapping;
1987                         void *data = rx_buf->data;
1988
1989                         if (!data)
1990                                 continue;
1991
1992                         rx_buf->data = NULL;
1993
1994                         if (BNXT_RX_PAGE_MODE(bp)) {
1995                                 mapping -= bp->rx_dma_offset;
1996                                 dma_unmap_page(&pdev->dev, mapping,
1997                                                PAGE_SIZE, bp->rx_dir);
1998                                 __free_page(data);
1999                         } else {
2000                                 dma_unmap_single(&pdev->dev, mapping,
2001                                                  bp->rx_buf_use_size,
2002                                                  bp->rx_dir);
2003                                 kfree(data);
2004                         }
2005                 }
2006
2007                 for (j = 0; j < max_agg_idx; j++) {
2008                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
2009                                 &rxr->rx_agg_ring[j];
2010                         struct page *page = rx_agg_buf->page;
2011
2012                         if (!page)
2013                                 continue;
2014
2015                         dma_unmap_page(&pdev->dev, rx_agg_buf->mapping,
2016                                        BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
2017
2018                         rx_agg_buf->page = NULL;
2019                         __clear_bit(j, rxr->rx_agg_bmap);
2020
2021                         __free_page(page);
2022                 }
2023                 if (rxr->rx_page) {
2024                         __free_page(rxr->rx_page);
2025                         rxr->rx_page = NULL;
2026                 }
2027         }
2028 }
2029
2030 static void bnxt_free_skbs(struct bnxt *bp)
2031 {
2032         bnxt_free_tx_skbs(bp);
2033         bnxt_free_rx_skbs(bp);
2034 }
2035
2036 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2037 {
2038         struct pci_dev *pdev = bp->pdev;
2039         int i;
2040
2041         for (i = 0; i < ring->nr_pages; i++) {
2042                 if (!ring->pg_arr[i])
2043                         continue;
2044
2045                 dma_free_coherent(&pdev->dev, ring->page_size,
2046                                   ring->pg_arr[i], ring->dma_arr[i]);
2047
2048                 ring->pg_arr[i] = NULL;
2049         }
2050         if (ring->pg_tbl) {
2051                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
2052                                   ring->pg_tbl, ring->pg_tbl_map);
2053                 ring->pg_tbl = NULL;
2054         }
2055         if (ring->vmem_size && *ring->vmem) {
2056                 vfree(*ring->vmem);
2057                 *ring->vmem = NULL;
2058         }
2059 }
2060
2061 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
2062 {
2063         int i;
2064         struct pci_dev *pdev = bp->pdev;
2065
2066         if (ring->nr_pages > 1) {
2067                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
2068                                                   ring->nr_pages * 8,
2069                                                   &ring->pg_tbl_map,
2070                                                   GFP_KERNEL);
2071                 if (!ring->pg_tbl)
2072                         return -ENOMEM;
2073         }
2074
2075         for (i = 0; i < ring->nr_pages; i++) {
2076                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2077                                                      ring->page_size,
2078                                                      &ring->dma_arr[i],
2079                                                      GFP_KERNEL);
2080                 if (!ring->pg_arr[i])
2081                         return -ENOMEM;
2082
2083                 if (ring->nr_pages > 1)
2084                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
2085         }
2086
2087         if (ring->vmem_size) {
2088                 *ring->vmem = vzalloc(ring->vmem_size);
2089                 if (!(*ring->vmem))
2090                         return -ENOMEM;
2091         }
2092         return 0;
2093 }
2094
2095 static void bnxt_free_rx_rings(struct bnxt *bp)
2096 {
2097         int i;
2098
2099         if (!bp->rx_ring)
2100                 return;
2101
2102         for (i = 0; i < bp->rx_nr_rings; i++) {
2103                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2104                 struct bnxt_ring_struct *ring;
2105
2106                 if (rxr->xdp_prog)
2107                         bpf_prog_put(rxr->xdp_prog);
2108
2109                 kfree(rxr->rx_tpa);
2110                 rxr->rx_tpa = NULL;
2111
2112                 kfree(rxr->rx_agg_bmap);
2113                 rxr->rx_agg_bmap = NULL;
2114
2115                 ring = &rxr->rx_ring_struct;
2116                 bnxt_free_ring(bp, ring);
2117
2118                 ring = &rxr->rx_agg_ring_struct;
2119                 bnxt_free_ring(bp, ring);
2120         }
2121 }
2122
2123 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2124 {
2125         int i, rc, agg_rings = 0, tpa_rings = 0;
2126
2127         if (!bp->rx_ring)
2128                 return -ENOMEM;
2129
2130         if (bp->flags & BNXT_FLAG_AGG_RINGS)
2131                 agg_rings = 1;
2132
2133         if (bp->flags & BNXT_FLAG_TPA)
2134                 tpa_rings = 1;
2135
2136         for (i = 0; i < bp->rx_nr_rings; i++) {
2137                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2138                 struct bnxt_ring_struct *ring;
2139
2140                 ring = &rxr->rx_ring_struct;
2141
2142                 rc = bnxt_alloc_ring(bp, ring);
2143                 if (rc)
2144                         return rc;
2145
2146                 if (agg_rings) {
2147                         u16 mem_size;
2148
2149                         ring = &rxr->rx_agg_ring_struct;
2150                         rc = bnxt_alloc_ring(bp, ring);
2151                         if (rc)
2152                                 return rc;
2153
2154                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2155                         mem_size = rxr->rx_agg_bmap_size / 8;
2156                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2157                         if (!rxr->rx_agg_bmap)
2158                                 return -ENOMEM;
2159
2160                         if (tpa_rings) {
2161                                 rxr->rx_tpa = kcalloc(MAX_TPA,
2162                                                 sizeof(struct bnxt_tpa_info),
2163                                                 GFP_KERNEL);
2164                                 if (!rxr->rx_tpa)
2165                                         return -ENOMEM;
2166                         }
2167                 }
2168         }
2169         return 0;
2170 }
2171
2172 static void bnxt_free_tx_rings(struct bnxt *bp)
2173 {
2174         int i;
2175         struct pci_dev *pdev = bp->pdev;
2176
2177         if (!bp->tx_ring)
2178                 return;
2179
2180         for (i = 0; i < bp->tx_nr_rings; i++) {
2181                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2182                 struct bnxt_ring_struct *ring;
2183
2184                 if (txr->tx_push) {
2185                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
2186                                           txr->tx_push, txr->tx_push_mapping);
2187                         txr->tx_push = NULL;
2188                 }
2189
2190                 ring = &txr->tx_ring_struct;
2191
2192                 bnxt_free_ring(bp, ring);
2193         }
2194 }
2195
2196 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2197 {
2198         int i, j, rc;
2199         struct pci_dev *pdev = bp->pdev;
2200
2201         bp->tx_push_size = 0;
2202         if (bp->tx_push_thresh) {
2203                 int push_size;
2204
2205                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
2206                                         bp->tx_push_thresh);
2207
2208                 if (push_size > 256) {
2209                         push_size = 0;
2210                         bp->tx_push_thresh = 0;
2211                 }
2212
2213                 bp->tx_push_size = push_size;
2214         }
2215
2216         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
2217                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2218                 struct bnxt_ring_struct *ring;
2219
2220                 ring = &txr->tx_ring_struct;
2221
2222                 rc = bnxt_alloc_ring(bp, ring);
2223                 if (rc)
2224                         return rc;
2225
2226                 if (bp->tx_push_size) {
2227                         dma_addr_t mapping;
2228
2229                         /* One pre-allocated DMA buffer to backup
2230                          * TX push operation
2231                          */
2232                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
2233                                                 bp->tx_push_size,
2234                                                 &txr->tx_push_mapping,
2235                                                 GFP_KERNEL);
2236
2237                         if (!txr->tx_push)
2238                                 return -ENOMEM;
2239
2240                         mapping = txr->tx_push_mapping +
2241                                 sizeof(struct tx_push_bd);
2242                         txr->data_mapping = cpu_to_le64(mapping);
2243
2244                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
2245                 }
2246                 ring->queue_id = bp->q_info[j].queue_id;
2247                 if (i < bp->tx_nr_rings_xdp)
2248                         continue;
2249                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
2250                         j++;
2251         }
2252         return 0;
2253 }
2254
2255 static void bnxt_free_cp_rings(struct bnxt *bp)
2256 {
2257         int i;
2258
2259         if (!bp->bnapi)
2260                 return;
2261
2262         for (i = 0; i < bp->cp_nr_rings; i++) {
2263                 struct bnxt_napi *bnapi = bp->bnapi[i];
2264                 struct bnxt_cp_ring_info *cpr;
2265                 struct bnxt_ring_struct *ring;
2266
2267                 if (!bnapi)
2268                         continue;
2269
2270                 cpr = &bnapi->cp_ring;
2271                 ring = &cpr->cp_ring_struct;
2272
2273                 bnxt_free_ring(bp, ring);
2274         }
2275 }
2276
2277 static int bnxt_alloc_cp_rings(struct bnxt *bp)
2278 {
2279         int i, rc;
2280
2281         for (i = 0; i < bp->cp_nr_rings; i++) {
2282                 struct bnxt_napi *bnapi = bp->bnapi[i];
2283                 struct bnxt_cp_ring_info *cpr;
2284                 struct bnxt_ring_struct *ring;
2285
2286                 if (!bnapi)
2287                         continue;
2288
2289                 cpr = &bnapi->cp_ring;
2290                 ring = &cpr->cp_ring_struct;
2291
2292                 rc = bnxt_alloc_ring(bp, ring);
2293                 if (rc)
2294                         return rc;
2295         }
2296         return 0;
2297 }
2298
2299 static void bnxt_init_ring_struct(struct bnxt *bp)
2300 {
2301         int i;
2302
2303         for (i = 0; i < bp->cp_nr_rings; i++) {
2304                 struct bnxt_napi *bnapi = bp->bnapi[i];
2305                 struct bnxt_cp_ring_info *cpr;
2306                 struct bnxt_rx_ring_info *rxr;
2307                 struct bnxt_tx_ring_info *txr;
2308                 struct bnxt_ring_struct *ring;
2309
2310                 if (!bnapi)
2311                         continue;
2312
2313                 cpr = &bnapi->cp_ring;
2314                 ring = &cpr->cp_ring_struct;
2315                 ring->nr_pages = bp->cp_nr_pages;
2316                 ring->page_size = HW_CMPD_RING_SIZE;
2317                 ring->pg_arr = (void **)cpr->cp_desc_ring;
2318                 ring->dma_arr = cpr->cp_desc_mapping;
2319                 ring->vmem_size = 0;
2320
2321                 rxr = bnapi->rx_ring;
2322                 if (!rxr)
2323                         goto skip_rx;
2324
2325                 ring = &rxr->rx_ring_struct;
2326                 ring->nr_pages = bp->rx_nr_pages;
2327                 ring->page_size = HW_RXBD_RING_SIZE;
2328                 ring->pg_arr = (void **)rxr->rx_desc_ring;
2329                 ring->dma_arr = rxr->rx_desc_mapping;
2330                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2331                 ring->vmem = (void **)&rxr->rx_buf_ring;
2332
2333                 ring = &rxr->rx_agg_ring_struct;
2334                 ring->nr_pages = bp->rx_agg_nr_pages;
2335                 ring->page_size = HW_RXBD_RING_SIZE;
2336                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2337                 ring->dma_arr = rxr->rx_agg_desc_mapping;
2338                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2339                 ring->vmem = (void **)&rxr->rx_agg_ring;
2340
2341 skip_rx:
2342                 txr = bnapi->tx_ring;
2343                 if (!txr)
2344                         continue;
2345
2346                 ring = &txr->tx_ring_struct;
2347                 ring->nr_pages = bp->tx_nr_pages;
2348                 ring->page_size = HW_RXBD_RING_SIZE;
2349                 ring->pg_arr = (void **)txr->tx_desc_ring;
2350                 ring->dma_arr = txr->tx_desc_mapping;
2351                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2352                 ring->vmem = (void **)&txr->tx_buf_ring;
2353         }
2354 }
2355
2356 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2357 {
2358         int i;
2359         u32 prod;
2360         struct rx_bd **rx_buf_ring;
2361
2362         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2363         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2364                 int j;
2365                 struct rx_bd *rxbd;
2366
2367                 rxbd = rx_buf_ring[i];
2368                 if (!rxbd)
2369                         continue;
2370
2371                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2372                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2373                         rxbd->rx_bd_opaque = prod;
2374                 }
2375         }
2376 }
2377
2378 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2379 {
2380         struct net_device *dev = bp->dev;
2381         struct bnxt_rx_ring_info *rxr;
2382         struct bnxt_ring_struct *ring;
2383         u32 prod, type;
2384         int i;
2385
2386         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2387                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2388
2389         if (NET_IP_ALIGN == 2)
2390                 type |= RX_BD_FLAGS_SOP;
2391
2392         rxr = &bp->rx_ring[ring_nr];
2393         ring = &rxr->rx_ring_struct;
2394         bnxt_init_rxbd_pages(ring, type);
2395
2396         if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
2397                 rxr->xdp_prog = bpf_prog_add(bp->xdp_prog, 1);
2398                 if (IS_ERR(rxr->xdp_prog)) {
2399                         int rc = PTR_ERR(rxr->xdp_prog);
2400
2401                         rxr->xdp_prog = NULL;
2402                         return rc;
2403                 }
2404         }
2405         prod = rxr->rx_prod;
2406         for (i = 0; i < bp->rx_ring_size; i++) {
2407                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2408                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2409                                     ring_nr, i, bp->rx_ring_size);
2410                         break;
2411                 }
2412                 prod = NEXT_RX(prod);
2413         }
2414         rxr->rx_prod = prod;
2415         ring->fw_ring_id = INVALID_HW_RING_ID;
2416
2417         ring = &rxr->rx_agg_ring_struct;
2418         ring->fw_ring_id = INVALID_HW_RING_ID;
2419
2420         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2421                 return 0;
2422
2423         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2424                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2425
2426         bnxt_init_rxbd_pages(ring, type);
2427
2428         prod = rxr->rx_agg_prod;
2429         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2430                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2431                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2432                                     ring_nr, i, bp->rx_ring_size);
2433                         break;
2434                 }
2435                 prod = NEXT_RX_AGG(prod);
2436         }
2437         rxr->rx_agg_prod = prod;
2438
2439         if (bp->flags & BNXT_FLAG_TPA) {
2440                 if (rxr->rx_tpa) {
2441                         u8 *data;
2442                         dma_addr_t mapping;
2443
2444                         for (i = 0; i < MAX_TPA; i++) {
2445                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2446                                                             GFP_KERNEL);
2447                                 if (!data)
2448                                         return -ENOMEM;
2449
2450                                 rxr->rx_tpa[i].data = data;
2451                                 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
2452                                 rxr->rx_tpa[i].mapping = mapping;
2453                         }
2454                 } else {
2455                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2456                         return -ENOMEM;
2457                 }
2458         }
2459
2460         return 0;
2461 }
2462
2463 static void bnxt_init_cp_rings(struct bnxt *bp)
2464 {
2465         int i;
2466
2467         for (i = 0; i < bp->cp_nr_rings; i++) {
2468                 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
2469                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
2470
2471                 ring->fw_ring_id = INVALID_HW_RING_ID;
2472         }
2473 }
2474
2475 static int bnxt_init_rx_rings(struct bnxt *bp)
2476 {
2477         int i, rc = 0;
2478
2479         if (BNXT_RX_PAGE_MODE(bp)) {
2480                 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
2481                 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
2482         } else {
2483                 bp->rx_offset = BNXT_RX_OFFSET;
2484                 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
2485         }
2486
2487         for (i = 0; i < bp->rx_nr_rings; i++) {
2488                 rc = bnxt_init_one_rx_ring(bp, i);
2489                 if (rc)
2490                         break;
2491         }
2492
2493         return rc;
2494 }
2495
2496 static int bnxt_init_tx_rings(struct bnxt *bp)
2497 {
2498         u16 i;
2499
2500         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2501                                    MAX_SKB_FRAGS + 1);
2502
2503         for (i = 0; i < bp->tx_nr_rings; i++) {
2504                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2505                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2506
2507                 ring->fw_ring_id = INVALID_HW_RING_ID;
2508         }
2509
2510         return 0;
2511 }
2512
2513 static void bnxt_free_ring_grps(struct bnxt *bp)
2514 {
2515         kfree(bp->grp_info);
2516         bp->grp_info = NULL;
2517 }
2518
2519 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2520 {
2521         int i;
2522
2523         if (irq_re_init) {
2524                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2525                                        sizeof(struct bnxt_ring_grp_info),
2526                                        GFP_KERNEL);
2527                 if (!bp->grp_info)
2528                         return -ENOMEM;
2529         }
2530         for (i = 0; i < bp->cp_nr_rings; i++) {
2531                 if (irq_re_init)
2532                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2533                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2534                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2535                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2536                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2537         }
2538         return 0;
2539 }
2540
2541 static void bnxt_free_vnics(struct bnxt *bp)
2542 {
2543         kfree(bp->vnic_info);
2544         bp->vnic_info = NULL;
2545         bp->nr_vnics = 0;
2546 }
2547
2548 static int bnxt_alloc_vnics(struct bnxt *bp)
2549 {
2550         int num_vnics = 1;
2551
2552 #ifdef CONFIG_RFS_ACCEL
2553         if (bp->flags & BNXT_FLAG_RFS)
2554                 num_vnics += bp->rx_nr_rings;
2555 #endif
2556
2557         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
2558                 num_vnics++;
2559
2560         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2561                                 GFP_KERNEL);
2562         if (!bp->vnic_info)
2563                 return -ENOMEM;
2564
2565         bp->nr_vnics = num_vnics;
2566         return 0;
2567 }
2568
2569 static void bnxt_init_vnics(struct bnxt *bp)
2570 {
2571         int i;
2572
2573         for (i = 0; i < bp->nr_vnics; i++) {
2574                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2575
2576                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2577                 vnic->fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
2578                 vnic->fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
2579                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2580
2581                 if (bp->vnic_info[i].rss_hash_key) {
2582                         if (i == 0)
2583                                 prandom_bytes(vnic->rss_hash_key,
2584                                               HW_HASH_KEY_SIZE);
2585                         else
2586                                 memcpy(vnic->rss_hash_key,
2587                                        bp->vnic_info[0].rss_hash_key,
2588                                        HW_HASH_KEY_SIZE);
2589                 }
2590         }
2591 }
2592
2593 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2594 {
2595         int pages;
2596
2597         pages = ring_size / desc_per_pg;
2598
2599         if (!pages)
2600                 return 1;
2601
2602         pages++;
2603
2604         while (pages & (pages - 1))
2605                 pages++;
2606
2607         return pages;
2608 }
2609
2610 void bnxt_set_tpa_flags(struct bnxt *bp)
2611 {
2612         bp->flags &= ~BNXT_FLAG_TPA;
2613         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
2614                 return;
2615         if (bp->dev->features & NETIF_F_LRO)
2616                 bp->flags |= BNXT_FLAG_LRO;
2617         if (bp->dev->features & NETIF_F_GRO)
2618                 bp->flags |= BNXT_FLAG_GRO;
2619 }
2620
2621 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2622  * be set on entry.
2623  */
2624 void bnxt_set_ring_params(struct bnxt *bp)
2625 {
2626         u32 ring_size, rx_size, rx_space;
2627         u32 agg_factor = 0, agg_ring_size = 0;
2628
2629         /* 8 for CRC and VLAN */
2630         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2631
2632         rx_space = rx_size + NET_SKB_PAD +
2633                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2634
2635         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2636         ring_size = bp->rx_ring_size;
2637         bp->rx_agg_ring_size = 0;
2638         bp->rx_agg_nr_pages = 0;
2639
2640         if (bp->flags & BNXT_FLAG_TPA)
2641                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2642
2643         bp->flags &= ~BNXT_FLAG_JUMBO;
2644         if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
2645                 u32 jumbo_factor;
2646
2647                 bp->flags |= BNXT_FLAG_JUMBO;
2648                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2649                 if (jumbo_factor > agg_factor)
2650                         agg_factor = jumbo_factor;
2651         }
2652         agg_ring_size = ring_size * agg_factor;
2653
2654         if (agg_ring_size) {
2655                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2656                                                         RX_DESC_CNT);
2657                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2658                         u32 tmp = agg_ring_size;
2659
2660                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2661                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2662                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2663                                     tmp, agg_ring_size);
2664                 }
2665                 bp->rx_agg_ring_size = agg_ring_size;
2666                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2667                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2668                 rx_space = rx_size + NET_SKB_PAD +
2669                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2670         }
2671
2672         bp->rx_buf_use_size = rx_size;
2673         bp->rx_buf_size = rx_space;
2674
2675         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2676         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2677
2678         ring_size = bp->tx_ring_size;
2679         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2680         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2681
2682         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2683         bp->cp_ring_size = ring_size;
2684
2685         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2686         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2687                 bp->cp_nr_pages = MAX_CP_PAGES;
2688                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2689                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2690                             ring_size, bp->cp_ring_size);
2691         }
2692         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2693         bp->cp_ring_mask = bp->cp_bit - 1;
2694 }
2695
2696 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
2697 {
2698         if (page_mode) {
2699                 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
2700                         return -EOPNOTSUPP;
2701                 bp->dev->max_mtu = BNXT_MAX_PAGE_MODE_MTU;
2702                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
2703                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
2704                 bp->dev->hw_features &= ~NETIF_F_LRO;
2705                 bp->dev->features &= ~NETIF_F_LRO;
2706                 bp->rx_dir = DMA_BIDIRECTIONAL;
2707                 bp->rx_skb_func = bnxt_rx_page_skb;
2708         } else {
2709                 bp->dev->max_mtu = BNXT_MAX_MTU;
2710                 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
2711                 bp->rx_dir = DMA_FROM_DEVICE;
2712                 bp->rx_skb_func = bnxt_rx_skb;
2713         }
2714         return 0;
2715 }
2716
2717 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2718 {
2719         int i;
2720         struct bnxt_vnic_info *vnic;
2721         struct pci_dev *pdev = bp->pdev;
2722
2723         if (!bp->vnic_info)
2724                 return;
2725
2726         for (i = 0; i < bp->nr_vnics; i++) {
2727                 vnic = &bp->vnic_info[i];
2728
2729                 kfree(vnic->fw_grp_ids);
2730                 vnic->fw_grp_ids = NULL;
2731
2732                 kfree(vnic->uc_list);
2733                 vnic->uc_list = NULL;
2734
2735                 if (vnic->mc_list) {
2736                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2737                                           vnic->mc_list, vnic->mc_list_mapping);
2738                         vnic->mc_list = NULL;
2739                 }
2740
2741                 if (vnic->rss_table) {
2742                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2743                                           vnic->rss_table,
2744                                           vnic->rss_table_dma_addr);
2745                         vnic->rss_table = NULL;
2746                 }
2747
2748                 vnic->rss_hash_key = NULL;
2749                 vnic->flags = 0;
2750         }
2751 }
2752
2753 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2754 {
2755         int i, rc = 0, size;
2756         struct bnxt_vnic_info *vnic;
2757         struct pci_dev *pdev = bp->pdev;
2758         int max_rings;
2759
2760         for (i = 0; i < bp->nr_vnics; i++) {
2761                 vnic = &bp->vnic_info[i];
2762
2763                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2764                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2765
2766                         if (mem_size > 0) {
2767                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2768                                 if (!vnic->uc_list) {
2769                                         rc = -ENOMEM;
2770                                         goto out;
2771                                 }
2772                         }
2773                 }
2774
2775                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2776                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2777                         vnic->mc_list =
2778                                 dma_alloc_coherent(&pdev->dev,
2779                                                    vnic->mc_list_size,
2780                                                    &vnic->mc_list_mapping,
2781                                                    GFP_KERNEL);
2782                         if (!vnic->mc_list) {
2783                                 rc = -ENOMEM;
2784                                 goto out;
2785                         }
2786                 }
2787
2788                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2789                         max_rings = bp->rx_nr_rings;
2790                 else
2791                         max_rings = 1;
2792
2793                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2794                 if (!vnic->fw_grp_ids) {
2795                         rc = -ENOMEM;
2796                         goto out;
2797                 }
2798
2799                 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
2800                     !(vnic->flags & BNXT_VNIC_RSS_FLAG))
2801                         continue;
2802
2803                 /* Allocate rss table and hash key */
2804                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2805                                                      &vnic->rss_table_dma_addr,
2806                                                      GFP_KERNEL);
2807                 if (!vnic->rss_table) {
2808                         rc = -ENOMEM;
2809                         goto out;
2810                 }
2811
2812                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2813
2814                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2815                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2816         }
2817         return 0;
2818
2819 out:
2820         return rc;
2821 }
2822
2823 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2824 {
2825         struct pci_dev *pdev = bp->pdev;
2826
2827         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2828                           bp->hwrm_cmd_resp_dma_addr);
2829
2830         bp->hwrm_cmd_resp_addr = NULL;
2831         if (bp->hwrm_dbg_resp_addr) {
2832                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2833                                   bp->hwrm_dbg_resp_addr,
2834                                   bp->hwrm_dbg_resp_dma_addr);
2835
2836                 bp->hwrm_dbg_resp_addr = NULL;
2837         }
2838 }
2839
2840 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2841 {
2842         struct pci_dev *pdev = bp->pdev;
2843
2844         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2845                                                    &bp->hwrm_cmd_resp_dma_addr,
2846                                                    GFP_KERNEL);
2847         if (!bp->hwrm_cmd_resp_addr)
2848                 return -ENOMEM;
2849         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2850                                                     HWRM_DBG_REG_BUF_SIZE,
2851                                                     &bp->hwrm_dbg_resp_dma_addr,
2852                                                     GFP_KERNEL);
2853         if (!bp->hwrm_dbg_resp_addr)
2854                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2855
2856         return 0;
2857 }
2858
2859 static void bnxt_free_stats(struct bnxt *bp)
2860 {
2861         u32 size, i;
2862         struct pci_dev *pdev = bp->pdev;
2863
2864         if (bp->hw_rx_port_stats) {
2865                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2866                                   bp->hw_rx_port_stats,
2867                                   bp->hw_rx_port_stats_map);
2868                 bp->hw_rx_port_stats = NULL;
2869                 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2870         }
2871
2872         if (!bp->bnapi)
2873                 return;
2874
2875         size = sizeof(struct ctx_hw_stats);
2876
2877         for (i = 0; i < bp->cp_nr_rings; i++) {
2878                 struct bnxt_napi *bnapi = bp->bnapi[i];
2879                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2880
2881                 if (cpr->hw_stats) {
2882                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2883                                           cpr->hw_stats_map);
2884                         cpr->hw_stats = NULL;
2885                 }
2886         }
2887 }
2888
2889 static int bnxt_alloc_stats(struct bnxt *bp)
2890 {
2891         u32 size, i;
2892         struct pci_dev *pdev = bp->pdev;
2893
2894         size = sizeof(struct ctx_hw_stats);
2895
2896         for (i = 0; i < bp->cp_nr_rings; i++) {
2897                 struct bnxt_napi *bnapi = bp->bnapi[i];
2898                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2899
2900                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2901                                                    &cpr->hw_stats_map,
2902                                                    GFP_KERNEL);
2903                 if (!cpr->hw_stats)
2904                         return -ENOMEM;
2905
2906                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2907         }
2908
2909         if (BNXT_PF(bp) && bp->chip_num != CHIP_NUM_58700) {
2910                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2911                                          sizeof(struct tx_port_stats) + 1024;
2912
2913                 bp->hw_rx_port_stats =
2914                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2915                                            &bp->hw_rx_port_stats_map,
2916                                            GFP_KERNEL);
2917                 if (!bp->hw_rx_port_stats)
2918                         return -ENOMEM;
2919
2920                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2921                                        512;
2922                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2923                                            sizeof(struct rx_port_stats) + 512;
2924                 bp->flags |= BNXT_FLAG_PORT_STATS;
2925         }
2926         return 0;
2927 }
2928
2929 static void bnxt_clear_ring_indices(struct bnxt *bp)
2930 {
2931         int i;
2932
2933         if (!bp->bnapi)
2934                 return;
2935
2936         for (i = 0; i < bp->cp_nr_rings; i++) {
2937                 struct bnxt_napi *bnapi = bp->bnapi[i];
2938                 struct bnxt_cp_ring_info *cpr;
2939                 struct bnxt_rx_ring_info *rxr;
2940                 struct bnxt_tx_ring_info *txr;
2941
2942                 if (!bnapi)
2943                         continue;
2944
2945                 cpr = &bnapi->cp_ring;
2946                 cpr->cp_raw_cons = 0;
2947
2948                 txr = bnapi->tx_ring;
2949                 if (txr) {
2950                         txr->tx_prod = 0;
2951                         txr->tx_cons = 0;
2952                 }
2953
2954                 rxr = bnapi->rx_ring;
2955                 if (rxr) {
2956                         rxr->rx_prod = 0;
2957                         rxr->rx_agg_prod = 0;
2958                         rxr->rx_sw_agg_prod = 0;
2959                         rxr->rx_next_cons = 0;
2960                 }
2961         }
2962 }
2963
2964 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2965 {
2966 #ifdef CONFIG_RFS_ACCEL
2967         int i;
2968
2969         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
2970          * safe to delete the hash table.
2971          */
2972         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2973                 struct hlist_head *head;
2974                 struct hlist_node *tmp;
2975                 struct bnxt_ntuple_filter *fltr;
2976
2977                 head = &bp->ntp_fltr_hash_tbl[i];
2978                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2979                         hlist_del(&fltr->hash);
2980                         kfree(fltr);
2981                 }
2982         }
2983         if (irq_reinit) {
2984                 kfree(bp->ntp_fltr_bmap);
2985                 bp->ntp_fltr_bmap = NULL;
2986         }
2987         bp->ntp_fltr_count = 0;
2988 #endif
2989 }
2990
2991 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2992 {
2993 #ifdef CONFIG_RFS_ACCEL
2994         int i, rc = 0;
2995
2996         if (!(bp->flags & BNXT_FLAG_RFS))
2997                 return 0;
2998
2999         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
3000                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
3001
3002         bp->ntp_fltr_count = 0;
3003         bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
3004                                     GFP_KERNEL);
3005
3006         if (!bp->ntp_fltr_bmap)
3007                 rc = -ENOMEM;
3008
3009         return rc;
3010 #else
3011         return 0;
3012 #endif
3013 }
3014
3015 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
3016 {
3017         bnxt_free_vnic_attributes(bp);
3018         bnxt_free_tx_rings(bp);
3019         bnxt_free_rx_rings(bp);
3020         bnxt_free_cp_rings(bp);
3021         bnxt_free_ntp_fltrs(bp, irq_re_init);
3022         if (irq_re_init) {
3023                 bnxt_free_stats(bp);
3024                 bnxt_free_ring_grps(bp);
3025                 bnxt_free_vnics(bp);
3026                 kfree(bp->tx_ring_map);
3027                 bp->tx_ring_map = NULL;
3028                 kfree(bp->tx_ring);
3029                 bp->tx_ring = NULL;
3030                 kfree(bp->rx_ring);
3031                 bp->rx_ring = NULL;
3032                 kfree(bp->bnapi);
3033                 bp->bnapi = NULL;
3034         } else {
3035                 bnxt_clear_ring_indices(bp);
3036         }
3037 }
3038
3039 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
3040 {
3041         int i, j, rc, size, arr_size;
3042         void *bnapi;
3043
3044         if (irq_re_init) {
3045                 /* Allocate bnapi mem pointer array and mem block for
3046                  * all queues
3047                  */
3048                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
3049                                 bp->cp_nr_rings);
3050                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
3051                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
3052                 if (!bnapi)
3053                         return -ENOMEM;
3054
3055                 bp->bnapi = bnapi;
3056                 bnapi += arr_size;
3057                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
3058                         bp->bnapi[i] = bnapi;
3059                         bp->bnapi[i]->index = i;
3060                         bp->bnapi[i]->bp = bp;
3061                 }
3062
3063                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
3064                                       sizeof(struct bnxt_rx_ring_info),
3065                                       GFP_KERNEL);
3066                 if (!bp->rx_ring)
3067                         return -ENOMEM;
3068
3069                 for (i = 0; i < bp->rx_nr_rings; i++) {
3070                         bp->rx_ring[i].bnapi = bp->bnapi[i];
3071                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
3072                 }
3073
3074                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
3075                                       sizeof(struct bnxt_tx_ring_info),
3076                                       GFP_KERNEL);
3077                 if (!bp->tx_ring)
3078                         return -ENOMEM;
3079
3080                 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
3081                                           GFP_KERNEL);
3082
3083                 if (!bp->tx_ring_map)
3084                         return -ENOMEM;
3085
3086                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
3087                         j = 0;
3088                 else
3089                         j = bp->rx_nr_rings;
3090
3091                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
3092                         bp->tx_ring[i].bnapi = bp->bnapi[j];
3093                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
3094                         bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
3095                         if (i >= bp->tx_nr_rings_xdp) {
3096                                 bp->tx_ring[i].txq_index = i -
3097                                         bp->tx_nr_rings_xdp;
3098                                 bp->bnapi[j]->tx_int = bnxt_tx_int;
3099                         } else {
3100                                 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
3101                                 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
3102                         }
3103                 }
3104
3105                 rc = bnxt_alloc_stats(bp);
3106                 if (rc)
3107                         goto alloc_mem_err;
3108
3109                 rc = bnxt_alloc_ntp_fltrs(bp);
3110                 if (rc)
3111                         goto alloc_mem_err;
3112
3113                 rc = bnxt_alloc_vnics(bp);
3114                 if (rc)
3115                         goto alloc_mem_err;
3116         }
3117
3118         bnxt_init_ring_struct(bp);
3119
3120         rc = bnxt_alloc_rx_rings(bp);
3121         if (rc)
3122                 goto alloc_mem_err;
3123
3124         rc = bnxt_alloc_tx_rings(bp);
3125         if (rc)
3126                 goto alloc_mem_err;
3127
3128         rc = bnxt_alloc_cp_rings(bp);
3129         if (rc)
3130                 goto alloc_mem_err;
3131
3132         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
3133                                   BNXT_VNIC_UCAST_FLAG;
3134         rc = bnxt_alloc_vnic_attributes(bp);
3135         if (rc)
3136                 goto alloc_mem_err;
3137         return 0;
3138
3139 alloc_mem_err:
3140         bnxt_free_mem(bp, true);
3141         return rc;
3142 }
3143
3144 static void bnxt_disable_int(struct bnxt *bp)
3145 {
3146         int i;
3147
3148         if (!bp->bnapi)
3149                 return;
3150
3151         for (i = 0; i < bp->cp_nr_rings; i++) {
3152                 struct bnxt_napi *bnapi = bp->bnapi[i];
3153                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3154                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3155
3156                 if (ring->fw_ring_id != INVALID_HW_RING_ID)
3157                         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3158         }
3159 }
3160
3161 static void bnxt_disable_int_sync(struct bnxt *bp)
3162 {
3163         int i;
3164
3165         atomic_inc(&bp->intr_sem);
3166
3167         bnxt_disable_int(bp);
3168         for (i = 0; i < bp->cp_nr_rings; i++)
3169                 synchronize_irq(bp->irq_tbl[i].vector);
3170 }
3171
3172 static void bnxt_enable_int(struct bnxt *bp)
3173 {
3174         int i;
3175
3176         atomic_set(&bp->intr_sem, 0);
3177         for (i = 0; i < bp->cp_nr_rings; i++) {
3178                 struct bnxt_napi *bnapi = bp->bnapi[i];
3179                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3180
3181                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
3182         }
3183 }
3184
3185 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
3186                             u16 cmpl_ring, u16 target_id)
3187 {
3188         struct input *req = request;
3189
3190         req->req_type = cpu_to_le16(req_type);
3191         req->cmpl_ring = cpu_to_le16(cmpl_ring);
3192         req->target_id = cpu_to_le16(target_id);
3193         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
3194 }
3195
3196 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
3197                                  int timeout, bool silent)
3198 {
3199         int i, intr_process, rc, tmo_count;
3200         struct input *req = msg;
3201         u32 *data = msg;
3202         __le32 *resp_len, *valid;
3203         u16 cp_ring_id, len = 0;
3204         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
3205
3206         req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
3207         memset(resp, 0, PAGE_SIZE);
3208         cp_ring_id = le16_to_cpu(req->cmpl_ring);
3209         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
3210
3211         /* Write request msg to hwrm channel */
3212         __iowrite32_copy(bp->bar0, data, msg_len / 4);
3213
3214         for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
3215                 writel(0, bp->bar0 + i);
3216
3217         /* currently supports only one outstanding message */
3218         if (intr_process)
3219                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
3220
3221         /* Ring channel doorbell */
3222         writel(1, bp->bar0 + 0x100);
3223
3224         if (!timeout)
3225                 timeout = DFLT_HWRM_CMD_TIMEOUT;
3226
3227         i = 0;
3228         tmo_count = timeout * 40;
3229         if (intr_process) {
3230                 /* Wait until hwrm response cmpl interrupt is processed */
3231                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
3232                        i++ < tmo_count) {
3233                         usleep_range(25, 40);
3234                 }
3235
3236                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
3237                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
3238                                    le16_to_cpu(req->req_type));
3239                         return -1;
3240                 }
3241         } else {
3242                 /* Check if response len is updated */
3243                 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
3244                 for (i = 0; i < tmo_count; i++) {
3245                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
3246                               HWRM_RESP_LEN_SFT;
3247                         if (len)
3248                                 break;
3249                         usleep_range(25, 40);
3250                 }
3251
3252                 if (i >= tmo_count) {
3253                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
3254                                    timeout, le16_to_cpu(req->req_type),
3255                                    le16_to_cpu(req->seq_id), len);
3256                         return -1;
3257                 }
3258
3259                 /* Last word of resp contains valid bit */
3260                 valid = bp->hwrm_cmd_resp_addr + len - 4;
3261                 for (i = 0; i < 5; i++) {
3262                         if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
3263                                 break;
3264                         udelay(1);
3265                 }
3266
3267                 if (i >= 5) {
3268                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
3269                                    timeout, le16_to_cpu(req->req_type),
3270                                    le16_to_cpu(req->seq_id), len, *valid);
3271                         return -1;
3272                 }
3273         }
3274
3275         rc = le16_to_cpu(resp->error_code);
3276         if (rc && !silent)
3277                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
3278                            le16_to_cpu(resp->req_type),
3279                            le16_to_cpu(resp->seq_id), rc);
3280         return rc;
3281 }
3282
3283 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3284 {
3285         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
3286 }
3287
3288 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
3289 {
3290         int rc;
3291
3292         mutex_lock(&bp->hwrm_cmd_lock);
3293         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
3294         mutex_unlock(&bp->hwrm_cmd_lock);
3295         return rc;
3296 }
3297
3298 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
3299                              int timeout)
3300 {
3301         int rc;
3302
3303         mutex_lock(&bp->hwrm_cmd_lock);
3304         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
3305         mutex_unlock(&bp->hwrm_cmd_lock);
3306         return rc;
3307 }
3308
3309 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
3310                                      int bmap_size)
3311 {
3312         struct hwrm_func_drv_rgtr_input req = {0};
3313         DECLARE_BITMAP(async_events_bmap, 256);
3314         u32 *events = (u32 *)async_events_bmap;
3315         int i;
3316
3317         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3318
3319         req.enables =
3320                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
3321
3322         memset(async_events_bmap, 0, sizeof(async_events_bmap));
3323         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
3324                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
3325
3326         if (bmap && bmap_size) {
3327                 for (i = 0; i < bmap_size; i++) {
3328                         if (test_bit(i, bmap))
3329                                 __set_bit(i, async_events_bmap);
3330                 }
3331         }
3332
3333         for (i = 0; i < 8; i++)
3334                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
3335
3336         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3337 }
3338
3339 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
3340 {
3341         struct hwrm_func_drv_rgtr_input req = {0};
3342
3343         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
3344
3345         req.enables =
3346                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
3347                             FUNC_DRV_RGTR_REQ_ENABLES_VER);
3348
3349         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
3350         req.ver_maj = DRV_VER_MAJ;
3351         req.ver_min = DRV_VER_MIN;
3352         req.ver_upd = DRV_VER_UPD;
3353
3354         if (BNXT_PF(bp)) {
3355                 DECLARE_BITMAP(vf_req_snif_bmap, 256);
3356                 u32 *data = (u32 *)vf_req_snif_bmap;
3357                 int i;
3358
3359                 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
3360                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
3361                         __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
3362
3363                 for (i = 0; i < 8; i++)
3364                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
3365
3366                 req.enables |=
3367                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
3368         }
3369
3370         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3371 }
3372
3373 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
3374 {
3375         struct hwrm_func_drv_unrgtr_input req = {0};
3376
3377         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
3378         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3379 }
3380
3381 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
3382 {
3383         u32 rc = 0;
3384         struct hwrm_tunnel_dst_port_free_input req = {0};
3385
3386         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
3387         req.tunnel_type = tunnel_type;
3388
3389         switch (tunnel_type) {
3390         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
3391                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
3392                 break;
3393         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
3394                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
3395                 break;
3396         default:
3397                 break;
3398         }
3399
3400         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3401         if (rc)
3402                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
3403                            rc);
3404         return rc;
3405 }
3406
3407 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
3408                                            u8 tunnel_type)
3409 {
3410         u32 rc = 0;
3411         struct hwrm_tunnel_dst_port_alloc_input req = {0};
3412         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3413
3414         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
3415
3416         req.tunnel_type = tunnel_type;
3417         req.tunnel_dst_port_val = port;
3418
3419         mutex_lock(&bp->hwrm_cmd_lock);
3420         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3421         if (rc) {
3422                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
3423                            rc);
3424                 goto err_out;
3425         }
3426
3427         switch (tunnel_type) {
3428         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
3429                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
3430                 break;
3431         case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
3432                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
3433                 break;
3434         default:
3435                 break;
3436         }
3437
3438 err_out:
3439         mutex_unlock(&bp->hwrm_cmd_lock);
3440         return rc;
3441 }
3442
3443 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
3444 {
3445         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
3446         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3447
3448         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
3449         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3450
3451         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3452         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3453         req.mask = cpu_to_le32(vnic->rx_mask);
3454         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3455 }
3456
3457 #ifdef CONFIG_RFS_ACCEL
3458 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3459                                             struct bnxt_ntuple_filter *fltr)
3460 {
3461         struct hwrm_cfa_ntuple_filter_free_input req = {0};
3462
3463         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3464         req.ntuple_filter_id = fltr->filter_id;
3465         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3466 }
3467
3468 #define BNXT_NTP_FLTR_FLAGS                                     \
3469         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
3470          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
3471          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
3472          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
3473          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
3474          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
3475          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
3476          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
3477          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
3478          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
3479          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
3480          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
3481          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
3482          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3483
3484 #define BNXT_NTP_TUNNEL_FLTR_FLAG                               \
3485                 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
3486
3487 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3488                                              struct bnxt_ntuple_filter *fltr)
3489 {
3490         int rc = 0;
3491         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3492         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3493                 bp->hwrm_cmd_resp_addr;
3494         struct flow_keys *keys = &fltr->fkeys;
3495         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3496
3497         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3498         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
3499
3500         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3501
3502         req.ethertype = htons(ETH_P_IP);
3503         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3504         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3505         req.ip_protocol = keys->basic.ip_proto;
3506
3507         if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
3508                 int i;
3509
3510                 req.ethertype = htons(ETH_P_IPV6);
3511                 req.ip_addr_type =
3512                         CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
3513                 *(struct in6_addr *)&req.src_ipaddr[0] =
3514                         keys->addrs.v6addrs.src;
3515                 *(struct in6_addr *)&req.dst_ipaddr[0] =
3516                         keys->addrs.v6addrs.dst;
3517                 for (i = 0; i < 4; i++) {
3518                         req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3519                         req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
3520                 }
3521         } else {
3522                 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3523                 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3524                 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3525                 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3526         }
3527         if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
3528                 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
3529                 req.tunnel_type =
3530                         CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
3531         }
3532
3533         req.src_port = keys->ports.src;
3534         req.src_port_mask = cpu_to_be16(0xffff);
3535         req.dst_port = keys->ports.dst;
3536         req.dst_port_mask = cpu_to_be16(0xffff);
3537
3538         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3539         mutex_lock(&bp->hwrm_cmd_lock);
3540         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3541         if (!rc)
3542                 fltr->filter_id = resp->ntuple_filter_id;
3543         mutex_unlock(&bp->hwrm_cmd_lock);
3544         return rc;
3545 }
3546 #endif
3547
3548 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3549                                      u8 *mac_addr)
3550 {
3551         u32 rc = 0;
3552         struct hwrm_cfa_l2_filter_alloc_input req = {0};
3553         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3554
3555         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3556         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
3557         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
3558                 req.flags |=
3559                         cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3560         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3561         req.enables =
3562                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3563                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3564                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3565         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3566         req.l2_addr_mask[0] = 0xff;
3567         req.l2_addr_mask[1] = 0xff;
3568         req.l2_addr_mask[2] = 0xff;
3569         req.l2_addr_mask[3] = 0xff;
3570         req.l2_addr_mask[4] = 0xff;
3571         req.l2_addr_mask[5] = 0xff;
3572
3573         mutex_lock(&bp->hwrm_cmd_lock);
3574         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3575         if (!rc)
3576                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3577                                                         resp->l2_filter_id;
3578         mutex_unlock(&bp->hwrm_cmd_lock);
3579         return rc;
3580 }
3581
3582 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3583 {
3584         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3585         int rc = 0;
3586
3587         /* Any associated ntuple filters will also be cleared by firmware. */
3588         mutex_lock(&bp->hwrm_cmd_lock);
3589         for (i = 0; i < num_of_vnics; i++) {
3590                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3591
3592                 for (j = 0; j < vnic->uc_filter_count; j++) {
3593                         struct hwrm_cfa_l2_filter_free_input req = {0};
3594
3595                         bnxt_hwrm_cmd_hdr_init(bp, &req,
3596                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
3597
3598                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
3599
3600                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3601                                                 HWRM_CMD_TIMEOUT);
3602                 }
3603                 vnic->uc_filter_count = 0;
3604         }
3605         mutex_unlock(&bp->hwrm_cmd_lock);
3606
3607         return rc;
3608 }
3609
3610 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3611 {
3612         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3613         struct hwrm_vnic_tpa_cfg_input req = {0};
3614
3615         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3616
3617         if (tpa_flags) {
3618                 u16 mss = bp->dev->mtu - 40;
3619                 u32 nsegs, n, segs = 0, flags;
3620
3621                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3622                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3623                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3624                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3625                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3626                 if (tpa_flags & BNXT_FLAG_GRO)
3627                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3628
3629                 req.flags = cpu_to_le32(flags);
3630
3631                 req.enables =
3632                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3633                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3634                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3635
3636                 /* Number of segs are log2 units, and first packet is not
3637                  * included as part of this units.
3638                  */
3639                 if (mss <= BNXT_RX_PAGE_SIZE) {
3640                         n = BNXT_RX_PAGE_SIZE / mss;
3641                         nsegs = (MAX_SKB_FRAGS - 1) * n;
3642                 } else {
3643                         n = mss / BNXT_RX_PAGE_SIZE;
3644                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
3645                                 n++;
3646                         nsegs = (MAX_SKB_FRAGS - n) / n;
3647                 }
3648
3649                 segs = ilog2(nsegs);
3650                 req.max_agg_segs = cpu_to_le16(segs);
3651                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3652
3653                 req.min_agg_len = cpu_to_le32(512);
3654         }
3655         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3656
3657         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3658 }
3659
3660 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3661 {
3662         u32 i, j, max_rings;
3663         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3664         struct hwrm_vnic_rss_cfg_input req = {0};
3665
3666         if (vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
3667                 return 0;
3668
3669         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3670         if (set_rss) {
3671                 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
3672                 if (vnic->flags & BNXT_VNIC_RSS_FLAG) {
3673                         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3674                                 max_rings = bp->rx_nr_rings - 1;
3675                         else
3676                                 max_rings = bp->rx_nr_rings;
3677                 } else {
3678                         max_rings = 1;
3679                 }
3680
3681                 /* Fill the RSS indirection table with ring group ids */
3682                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3683                         if (j == max_rings)
3684                                 j = 0;
3685                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3686                 }
3687
3688                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3689                 req.hash_key_tbl_addr =
3690                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
3691         }
3692         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3693         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3694 }
3695
3696 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3697 {
3698         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3699         struct hwrm_vnic_plcmodes_cfg_input req = {0};
3700
3701         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3702         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3703                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3704                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3705         req.enables =
3706                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3707                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3708         /* thresholds not implemented in firmware yet */
3709         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3710         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3711         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3712         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3713 }
3714
3715 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
3716                                         u16 ctx_idx)
3717 {
3718         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3719
3720         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3721         req.rss_cos_lb_ctx_id =
3722                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
3723
3724         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3725         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
3726 }
3727
3728 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3729 {
3730         int i, j;
3731
3732         for (i = 0; i < bp->nr_vnics; i++) {
3733                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3734
3735                 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
3736                         if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
3737                                 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
3738                 }
3739         }
3740         bp->rsscos_nr_ctxs = 0;
3741 }
3742
3743 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
3744 {
3745         int rc;
3746         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3747         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3748                                                 bp->hwrm_cmd_resp_addr;
3749
3750         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3751                                -1);
3752
3753         mutex_lock(&bp->hwrm_cmd_lock);
3754         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3755         if (!rc)
3756                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
3757                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
3758         mutex_unlock(&bp->hwrm_cmd_lock);
3759
3760         return rc;
3761 }
3762
3763 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3764 {
3765         unsigned int ring = 0, grp_idx;
3766         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3767         struct hwrm_vnic_cfg_input req = {0};
3768         u16 def_vlan = 0;
3769
3770         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3771
3772         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
3773         /* Only RSS support for now TBD: COS & LB */
3774         if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
3775                 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
3776                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3777                                            VNIC_CFG_REQ_ENABLES_MRU);
3778         } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
3779                 req.rss_rule =
3780                         cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
3781                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
3782                                            VNIC_CFG_REQ_ENABLES_MRU);
3783                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
3784         } else {
3785                 req.rss_rule = cpu_to_le16(0xffff);
3786         }
3787
3788         if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
3789             (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
3790                 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
3791                 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
3792         } else {
3793                 req.cos_rule = cpu_to_le16(0xffff);
3794         }
3795
3796         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3797                 ring = 0;
3798         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3799                 ring = vnic_id - 1;
3800         else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
3801                 ring = bp->rx_nr_rings - 1;
3802
3803         grp_idx = bp->rx_ring[ring].bnapi->index;
3804         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3805         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3806
3807         req.lb_rule = cpu_to_le16(0xffff);
3808         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3809                               VLAN_HLEN);
3810
3811 #ifdef CONFIG_BNXT_SRIOV
3812         if (BNXT_VF(bp))
3813                 def_vlan = bp->vf.vlan;
3814 #endif
3815         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
3816                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3817         if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
3818                 req.flags |=
3819                         cpu_to_le32(VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE);
3820
3821         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3822 }
3823
3824 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3825 {
3826         u32 rc = 0;
3827
3828         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3829                 struct hwrm_vnic_free_input req = {0};
3830
3831                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3832                 req.vnic_id =
3833                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3834
3835                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3836                 if (rc)
3837                         return rc;
3838                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3839         }
3840         return rc;
3841 }
3842
3843 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3844 {
3845         u16 i;
3846
3847         for (i = 0; i < bp->nr_vnics; i++)
3848                 bnxt_hwrm_vnic_free_one(bp, i);
3849 }
3850
3851 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3852                                 unsigned int start_rx_ring_idx,
3853                                 unsigned int nr_rings)
3854 {
3855         int rc = 0;
3856         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3857         struct hwrm_vnic_alloc_input req = {0};
3858         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3859
3860         /* map ring groups to this vnic */
3861         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3862                 grp_idx = bp->rx_ring[i].bnapi->index;
3863                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3864                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3865                                    j, nr_rings);
3866                         break;
3867                 }
3868                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3869                                         bp->grp_info[grp_idx].fw_grp_id;
3870         }
3871
3872         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[0] = INVALID_HW_RING_ID;
3873         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[1] = INVALID_HW_RING_ID;
3874         if (vnic_id == 0)
3875                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3876
3877         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3878
3879         mutex_lock(&bp->hwrm_cmd_lock);
3880         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3881         if (!rc)
3882                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3883         mutex_unlock(&bp->hwrm_cmd_lock);
3884         return rc;
3885 }
3886
3887 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
3888 {
3889         struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3890         struct hwrm_vnic_qcaps_input req = {0};
3891         int rc;
3892
3893         if (bp->hwrm_spec_code < 0x10600)
3894                 return 0;
3895
3896         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
3897         mutex_lock(&bp->hwrm_cmd_lock);
3898         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3899         if (!rc) {
3900                 if (resp->flags &
3901                     cpu_to_le32(VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
3902                         bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
3903         }
3904         mutex_unlock(&bp->hwrm_cmd_lock);
3905         return rc;
3906 }
3907
3908 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3909 {
3910         u16 i;
3911         u32 rc = 0;
3912
3913         mutex_lock(&bp->hwrm_cmd_lock);
3914         for (i = 0; i < bp->rx_nr_rings; i++) {
3915                 struct hwrm_ring_grp_alloc_input req = {0};
3916                 struct hwrm_ring_grp_alloc_output *resp =
3917                                         bp->hwrm_cmd_resp_addr;
3918                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3919
3920                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3921
3922                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3923                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3924                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3925                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3926
3927                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3928                                         HWRM_CMD_TIMEOUT);
3929                 if (rc)
3930                         break;
3931
3932                 bp->grp_info[grp_idx].fw_grp_id =
3933                         le32_to_cpu(resp->ring_group_id);
3934         }
3935         mutex_unlock(&bp->hwrm_cmd_lock);
3936         return rc;
3937 }
3938
3939 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3940 {
3941         u16 i;
3942         u32 rc = 0;
3943         struct hwrm_ring_grp_free_input req = {0};
3944
3945         if (!bp->grp_info)
3946                 return 0;
3947
3948         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3949
3950         mutex_lock(&bp->hwrm_cmd_lock);
3951         for (i = 0; i < bp->cp_nr_rings; i++) {
3952                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3953                         continue;
3954                 req.ring_group_id =
3955                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
3956
3957                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3958                                         HWRM_CMD_TIMEOUT);
3959                 if (rc)
3960                         break;
3961                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3962         }
3963         mutex_unlock(&bp->hwrm_cmd_lock);
3964         return rc;
3965 }
3966
3967 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3968                                     struct bnxt_ring_struct *ring,
3969                                     u32 ring_type, u32 map_index,
3970                                     u32 stats_ctx_id)
3971 {
3972         int rc = 0, err = 0;
3973         struct hwrm_ring_alloc_input req = {0};
3974         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3975         u16 ring_id;
3976
3977         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3978
3979         req.enables = 0;
3980         if (ring->nr_pages > 1) {
3981                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3982                 /* Page size is in log2 units */
3983                 req.page_size = BNXT_PAGE_SHIFT;
3984                 req.page_tbl_depth = 1;
3985         } else {
3986                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
3987         }
3988         req.fbo = 0;
3989         /* Association of ring index with doorbell index and MSIX number */
3990         req.logical_id = cpu_to_le16(map_index);
3991
3992         switch (ring_type) {
3993         case HWRM_RING_ALLOC_TX:
3994                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3995                 /* Association of transmit ring with completion ring */
3996                 req.cmpl_ring_id =
3997                         cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3998                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3999                 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
4000                 req.queue_id = cpu_to_le16(ring->queue_id);
4001                 break;
4002         case HWRM_RING_ALLOC_RX:
4003                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4004                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
4005                 break;
4006         case HWRM_RING_ALLOC_AGG:
4007                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
4008                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
4009                 break;
4010         case HWRM_RING_ALLOC_CMPL:
4011                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
4012                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
4013                 if (bp->flags & BNXT_FLAG_USING_MSIX)
4014                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
4015                 break;
4016         default:
4017                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
4018                            ring_type);
4019                 return -1;
4020         }
4021
4022         mutex_lock(&bp->hwrm_cmd_lock);
4023         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4024         err = le16_to_cpu(resp->error_code);
4025         ring_id = le16_to_cpu(resp->ring_id);
4026         mutex_unlock(&bp->hwrm_cmd_lock);
4027
4028         if (rc || err) {
4029                 switch (ring_type) {
4030                 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4031                         netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
4032                                    rc, err);
4033                         return -1;
4034
4035                 case RING_FREE_REQ_RING_TYPE_RX:
4036                         netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
4037                                    rc, err);
4038                         return -1;
4039
4040                 case RING_FREE_REQ_RING_TYPE_TX:
4041                         netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
4042                                    rc, err);
4043                         return -1;
4044
4045                 default:
4046                         netdev_err(bp->dev, "Invalid ring\n");
4047                         return -1;
4048                 }
4049         }
4050         ring->fw_ring_id = ring_id;
4051         return rc;
4052 }
4053
4054 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
4055 {
4056         int rc;
4057
4058         if (BNXT_PF(bp)) {
4059                 struct hwrm_func_cfg_input req = {0};
4060
4061                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4062                 req.fid = cpu_to_le16(0xffff);
4063                 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4064                 req.async_event_cr = cpu_to_le16(idx);
4065                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4066         } else {
4067                 struct hwrm_func_vf_cfg_input req = {0};
4068
4069                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
4070                 req.enables =
4071                         cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
4072                 req.async_event_cr = cpu_to_le16(idx);
4073                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4074         }
4075         return rc;
4076 }
4077
4078 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
4079 {
4080         int i, rc = 0;
4081
4082         for (i = 0; i < bp->cp_nr_rings; i++) {
4083                 struct bnxt_napi *bnapi = bp->bnapi[i];
4084                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4085                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4086
4087                 cpr->cp_doorbell = bp->bar1 + i * 0x80;
4088                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
4089                                               INVALID_STATS_CTX_ID);
4090                 if (rc)
4091                         goto err_out;
4092                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4093                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
4094
4095                 if (!i) {
4096                         rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
4097                         if (rc)
4098                                 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
4099                 }
4100         }
4101
4102         for (i = 0; i < bp->tx_nr_rings; i++) {
4103                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4104                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4105                 u32 map_idx = txr->bnapi->index;
4106                 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
4107
4108                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
4109                                               map_idx, fw_stats_ctx);
4110                 if (rc)
4111                         goto err_out;
4112                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
4113         }
4114
4115         for (i = 0; i < bp->rx_nr_rings; i++) {
4116                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4117                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4118                 u32 map_idx = rxr->bnapi->index;
4119
4120                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
4121                                               map_idx, INVALID_STATS_CTX_ID);
4122                 if (rc)
4123                         goto err_out;
4124                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
4125                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
4126                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
4127         }
4128
4129         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4130                 for (i = 0; i < bp->rx_nr_rings; i++) {
4131                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4132                         struct bnxt_ring_struct *ring =
4133                                                 &rxr->rx_agg_ring_struct;
4134                         u32 grp_idx = rxr->bnapi->index;
4135                         u32 map_idx = grp_idx + bp->rx_nr_rings;
4136
4137                         rc = hwrm_ring_alloc_send_msg(bp, ring,
4138                                                       HWRM_RING_ALLOC_AGG,
4139                                                       map_idx,
4140                                                       INVALID_STATS_CTX_ID);
4141                         if (rc)
4142                                 goto err_out;
4143
4144                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
4145                         writel(DB_KEY_RX | rxr->rx_agg_prod,
4146                                rxr->rx_agg_doorbell);
4147                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
4148                 }
4149         }
4150 err_out:
4151         return rc;
4152 }
4153
4154 static int hwrm_ring_free_send_msg(struct bnxt *bp,
4155                                    struct bnxt_ring_struct *ring,
4156                                    u32 ring_type, int cmpl_ring_id)
4157 {
4158         int rc;
4159         struct hwrm_ring_free_input req = {0};
4160         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
4161         u16 error_code;
4162
4163         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
4164         req.ring_type = ring_type;
4165         req.ring_id = cpu_to_le16(ring->fw_ring_id);
4166
4167         mutex_lock(&bp->hwrm_cmd_lock);
4168         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4169         error_code = le16_to_cpu(resp->error_code);
4170         mutex_unlock(&bp->hwrm_cmd_lock);
4171
4172         if (rc || error_code) {
4173                 switch (ring_type) {
4174                 case RING_FREE_REQ_RING_TYPE_L2_CMPL:
4175                         netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
4176                                    rc);
4177                         return rc;
4178                 case RING_FREE_REQ_RING_TYPE_RX:
4179                         netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
4180                                    rc);
4181                         return rc;
4182                 case RING_FREE_REQ_RING_TYPE_TX:
4183                         netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
4184                                    rc);
4185                         return rc;
4186                 default:
4187                         netdev_err(bp->dev, "Invalid ring\n");
4188                         return -1;
4189                 }
4190         }
4191         return 0;
4192 }
4193
4194 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
4195 {
4196         int i;
4197
4198         if (!bp->bnapi)
4199                 return;
4200
4201         for (i = 0; i < bp->tx_nr_rings; i++) {
4202                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4203                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
4204                 u32 grp_idx = txr->bnapi->index;
4205                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4206
4207                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4208                         hwrm_ring_free_send_msg(bp, ring,
4209                                                 RING_FREE_REQ_RING_TYPE_TX,
4210                                                 close_path ? cmpl_ring_id :
4211                                                 INVALID_HW_RING_ID);
4212                         ring->fw_ring_id = INVALID_HW_RING_ID;
4213                 }
4214         }
4215
4216         for (i = 0; i < bp->rx_nr_rings; i++) {
4217                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4218                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
4219                 u32 grp_idx = rxr->bnapi->index;
4220                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4221
4222                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4223                         hwrm_ring_free_send_msg(bp, ring,
4224                                                 RING_FREE_REQ_RING_TYPE_RX,
4225                                                 close_path ? cmpl_ring_id :
4226                                                 INVALID_HW_RING_ID);
4227                         ring->fw_ring_id = INVALID_HW_RING_ID;
4228                         bp->grp_info[grp_idx].rx_fw_ring_id =
4229                                 INVALID_HW_RING_ID;
4230                 }
4231         }
4232
4233         for (i = 0; i < bp->rx_nr_rings; i++) {
4234                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4235                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
4236                 u32 grp_idx = rxr->bnapi->index;
4237                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
4238
4239                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4240                         hwrm_ring_free_send_msg(bp, ring,
4241                                                 RING_FREE_REQ_RING_TYPE_RX,
4242                                                 close_path ? cmpl_ring_id :
4243                                                 INVALID_HW_RING_ID);
4244                         ring->fw_ring_id = INVALID_HW_RING_ID;
4245                         bp->grp_info[grp_idx].agg_fw_ring_id =
4246                                 INVALID_HW_RING_ID;
4247                 }
4248         }
4249
4250         /* The completion rings are about to be freed.  After that the
4251          * IRQ doorbell will not work anymore.  So we need to disable
4252          * IRQ here.
4253          */
4254         bnxt_disable_int_sync(bp);
4255
4256         for (i = 0; i < bp->cp_nr_rings; i++) {
4257                 struct bnxt_napi *bnapi = bp->bnapi[i];
4258                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4259                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4260
4261                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
4262                         hwrm_ring_free_send_msg(bp, ring,
4263                                                 RING_FREE_REQ_RING_TYPE_L2_CMPL,
4264                                                 INVALID_HW_RING_ID);
4265                         ring->fw_ring_id = INVALID_HW_RING_ID;
4266                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
4267                 }
4268         }
4269 }
4270
4271 /* Caller must hold bp->hwrm_cmd_lock */
4272 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
4273 {
4274         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4275         struct hwrm_func_qcfg_input req = {0};
4276         int rc;
4277
4278         if (bp->hwrm_spec_code < 0x10601)
4279                 return 0;
4280
4281         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4282         req.fid = cpu_to_le16(fid);
4283         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4284         if (!rc)
4285                 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
4286
4287         return rc;
4288 }
4289
4290 static int bnxt_hwrm_reserve_tx_rings(struct bnxt *bp, int *tx_rings)
4291 {
4292         struct hwrm_func_cfg_input req = {0};
4293         int rc;
4294
4295         if (bp->hwrm_spec_code < 0x10601)
4296                 return 0;
4297
4298         if (BNXT_VF(bp))
4299                 return 0;
4300
4301         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
4302         req.fid = cpu_to_le16(0xffff);
4303         req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS);
4304         req.num_tx_rings = cpu_to_le16(*tx_rings);
4305         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4306         if (rc)
4307                 return rc;
4308
4309         mutex_lock(&bp->hwrm_cmd_lock);
4310         rc = __bnxt_hwrm_get_tx_rings(bp, 0xffff, tx_rings);
4311         mutex_unlock(&bp->hwrm_cmd_lock);
4312         return rc;
4313 }
4314
4315 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
4316         u32 buf_tmrs, u16 flags,
4317         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
4318 {
4319         req->flags = cpu_to_le16(flags);
4320         req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
4321         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
4322         req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
4323         req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
4324         /* Minimum time between 2 interrupts set to buf_tmr x 2 */
4325         req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
4326         req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
4327         req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
4328 }
4329
4330 int bnxt_hwrm_set_coal(struct bnxt *bp)
4331 {
4332         int i, rc = 0;
4333         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
4334                                                            req_tx = {0}, *req;
4335         u16 max_buf, max_buf_irq;
4336         u16 buf_tmr, buf_tmr_irq;
4337         u32 flags;
4338
4339         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
4340                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4341         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
4342                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
4343
4344         /* Each rx completion (2 records) should be DMAed immediately.
4345          * DMA 1/4 of the completion buffers at a time.
4346          */
4347         max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
4348         /* max_buf must not be zero */
4349         max_buf = clamp_t(u16, max_buf, 1, 63);
4350         max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
4351         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
4352         /* buf timer set to 1/4 of interrupt timer */
4353         buf_tmr = max_t(u16, buf_tmr / 4, 1);
4354         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
4355         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4356
4357         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4358
4359         /* RING_IDLE generates more IRQs for lower latency.  Enable it only
4360          * if coal_ticks is less than 25 us.
4361          */
4362         if (bp->rx_coal_ticks < 25)
4363                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
4364
4365         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4366                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
4367
4368         /* max_buf must not be zero */
4369         max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
4370         max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
4371         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
4372         /* buf timer set to 1/4 of interrupt timer */
4373         buf_tmr = max_t(u16, buf_tmr / 4, 1);
4374         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
4375         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
4376
4377         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
4378         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
4379                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
4380
4381         mutex_lock(&bp->hwrm_cmd_lock);
4382         for (i = 0; i < bp->cp_nr_rings; i++) {
4383                 struct bnxt_napi *bnapi = bp->bnapi[i];
4384
4385                 req = &req_rx;
4386                 if (!bnapi->rx_ring)
4387                         req = &req_tx;
4388                 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
4389
4390                 rc = _hwrm_send_message(bp, req, sizeof(*req),
4391                                         HWRM_CMD_TIMEOUT);
4392                 if (rc)
4393                         break;
4394         }
4395         mutex_unlock(&bp->hwrm_cmd_lock);
4396         return rc;
4397 }
4398
4399 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
4400 {
4401         int rc = 0, i;
4402         struct hwrm_stat_ctx_free_input req = {0};
4403
4404         if (!bp->bnapi)
4405                 return 0;
4406
4407         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4408                 return 0;
4409
4410         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
4411
4412         mutex_lock(&bp->hwrm_cmd_lock);
4413         for (i = 0; i < bp->cp_nr_rings; i++) {
4414                 struct bnxt_napi *bnapi = bp->bnapi[i];
4415                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4416
4417                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
4418                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
4419
4420                         rc = _hwrm_send_message(bp, &req, sizeof(req),
4421                                                 HWRM_CMD_TIMEOUT);
4422                         if (rc)
4423                                 break;
4424
4425                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4426                 }
4427         }
4428         mutex_unlock(&bp->hwrm_cmd_lock);
4429         return rc;
4430 }
4431
4432 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
4433 {
4434         int rc = 0, i;
4435         struct hwrm_stat_ctx_alloc_input req = {0};
4436         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4437
4438         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4439                 return 0;
4440
4441         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
4442
4443         req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
4444
4445         mutex_lock(&bp->hwrm_cmd_lock);
4446         for (i = 0; i < bp->cp_nr_rings; i++) {
4447                 struct bnxt_napi *bnapi = bp->bnapi[i];
4448                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4449
4450                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
4451
4452                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4453                                         HWRM_CMD_TIMEOUT);
4454                 if (rc)
4455                         break;
4456
4457                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
4458
4459                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
4460         }
4461         mutex_unlock(&bp->hwrm_cmd_lock);
4462         return rc;
4463 }
4464
4465 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
4466 {
4467         struct hwrm_func_qcfg_input req = {0};
4468         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4469         int rc;
4470
4471         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
4472         req.fid = cpu_to_le16(0xffff);
4473         mutex_lock(&bp->hwrm_cmd_lock);
4474         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4475         if (rc)
4476                 goto func_qcfg_exit;
4477
4478 #ifdef CONFIG_BNXT_SRIOV
4479         if (BNXT_VF(bp)) {
4480                 struct bnxt_vf_info *vf = &bp->vf;
4481
4482                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
4483         }
4484 #endif
4485         if (BNXT_PF(bp)) {
4486                 u16 flags = le16_to_cpu(resp->flags);
4487
4488                 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
4489                              FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED))
4490                         bp->flags |= BNXT_FLAG_FW_LLDP_AGENT;
4491                 if (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST)
4492                         bp->flags |= BNXT_FLAG_MULTI_HOST;
4493         }
4494
4495         switch (resp->port_partition_type) {
4496         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
4497         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
4498         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
4499                 bp->port_partition_type = resp->port_partition_type;
4500                 break;
4501         }
4502
4503 func_qcfg_exit:
4504         mutex_unlock(&bp->hwrm_cmd_lock);
4505         return rc;
4506 }
4507
4508 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
4509 {
4510         int rc = 0;
4511         struct hwrm_func_qcaps_input req = {0};
4512         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4513
4514         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
4515         req.fid = cpu_to_le16(0xffff);
4516
4517         mutex_lock(&bp->hwrm_cmd_lock);
4518         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4519         if (rc)
4520                 goto hwrm_func_qcaps_exit;
4521
4522         if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED))
4523                 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
4524         if (resp->flags & cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED))
4525                 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
4526
4527         bp->tx_push_thresh = 0;
4528         if (resp->flags &
4529             cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
4530                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
4531
4532         if (BNXT_PF(bp)) {
4533                 struct bnxt_pf_info *pf = &bp->pf;
4534
4535                 pf->fw_fid = le16_to_cpu(resp->fid);
4536                 pf->port_id = le16_to_cpu(resp->port_id);
4537                 bp->dev->dev_port = pf->port_id;
4538                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
4539                 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
4540                 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4541                 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4542                 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4543                 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4544                 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4545                 if (!pf->max_hw_ring_grps)
4546                         pf->max_hw_ring_grps = pf->max_tx_rings;
4547                 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4548                 pf->max_vnics = le16_to_cpu(resp->max_vnics);
4549                 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4550                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
4551                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
4552                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
4553                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
4554                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
4555                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
4556                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
4557                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
4558                 if (resp->flags &
4559                     cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED))
4560                         bp->flags |= BNXT_FLAG_WOL_CAP;
4561         } else {
4562 #ifdef CONFIG_BNXT_SRIOV
4563                 struct bnxt_vf_info *vf = &bp->vf;
4564
4565                 vf->fw_fid = le16_to_cpu(resp->fid);
4566
4567                 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
4568                 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
4569                 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
4570                 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
4571                 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
4572                 if (!vf->max_hw_ring_grps)
4573                         vf->max_hw_ring_grps = vf->max_tx_rings;
4574                 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
4575                 vf->max_vnics = le16_to_cpu(resp->max_vnics);
4576                 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
4577
4578                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
4579                 mutex_unlock(&bp->hwrm_cmd_lock);
4580
4581                 if (is_valid_ether_addr(vf->mac_addr)) {
4582                         /* overwrite netdev dev_adr with admin VF MAC */
4583                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
4584                 } else {
4585                         eth_hw_addr_random(bp->dev);
4586                         rc = bnxt_approve_mac(bp, bp->dev->dev_addr);
4587                 }
4588                 return rc;
4589 #endif
4590         }
4591
4592 hwrm_func_qcaps_exit:
4593         mutex_unlock(&bp->hwrm_cmd_lock);
4594         return rc;
4595 }
4596
4597 static int bnxt_hwrm_func_reset(struct bnxt *bp)
4598 {
4599         struct hwrm_func_reset_input req = {0};
4600
4601         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
4602         req.enables = 0;
4603
4604         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
4605 }
4606
4607 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
4608 {
4609         int rc = 0;
4610         struct hwrm_queue_qportcfg_input req = {0};
4611         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
4612         u8 i, *qptr;
4613
4614         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
4615
4616         mutex_lock(&bp->hwrm_cmd_lock);
4617         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4618         if (rc)
4619                 goto qportcfg_exit;
4620
4621         if (!resp->max_configurable_queues) {
4622                 rc = -EINVAL;
4623                 goto qportcfg_exit;
4624         }
4625         bp->max_tc = resp->max_configurable_queues;
4626         bp->max_lltc = resp->max_configurable_lossless_queues;
4627         if (bp->max_tc > BNXT_MAX_QUEUE)
4628                 bp->max_tc = BNXT_MAX_QUEUE;
4629
4630         if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
4631                 bp->max_tc = 1;
4632
4633         if (bp->max_lltc > bp->max_tc)
4634                 bp->max_lltc = bp->max_tc;
4635
4636         qptr = &resp->queue_id0;
4637         for (i = 0; i < bp->max_tc; i++) {
4638                 bp->q_info[i].queue_id = *qptr++;
4639                 bp->q_info[i].queue_profile = *qptr++;
4640         }
4641
4642 qportcfg_exit:
4643         mutex_unlock(&bp->hwrm_cmd_lock);
4644         return rc;
4645 }
4646
4647 static int bnxt_hwrm_ver_get(struct bnxt *bp)
4648 {
4649         int rc;
4650         struct hwrm_ver_get_input req = {0};
4651         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4652
4653         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
4654         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4655         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4656         req.hwrm_intf_min = HWRM_VERSION_MINOR;
4657         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4658         mutex_lock(&bp->hwrm_cmd_lock);
4659         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4660         if (rc)
4661                 goto hwrm_ver_get_exit;
4662
4663         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4664
4665         bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4666                              resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
4667         if (resp->hwrm_intf_maj < 1) {
4668                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4669                             resp->hwrm_intf_maj, resp->hwrm_intf_min,
4670                             resp->hwrm_intf_upd);
4671                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4672         }
4673         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
4674                  resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4675                  resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4676
4677         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4678         if (!bp->hwrm_cmd_timeout)
4679                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4680
4681         if (resp->hwrm_intf_maj >= 1)
4682                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4683
4684         bp->chip_num = le16_to_cpu(resp->chip_num);
4685         if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
4686             !resp->chip_metal)
4687                 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
4688
4689 hwrm_ver_get_exit:
4690         mutex_unlock(&bp->hwrm_cmd_lock);
4691         return rc;
4692 }
4693
4694 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
4695 {
4696 #if IS_ENABLED(CONFIG_RTC_LIB)
4697         struct hwrm_fw_set_time_input req = {0};
4698         struct rtc_time tm;
4699         struct timeval tv;
4700
4701         if (bp->hwrm_spec_code < 0x10400)
4702                 return -EOPNOTSUPP;
4703
4704         do_gettimeofday(&tv);
4705         rtc_time_to_tm(tv.tv_sec, &tm);
4706         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
4707         req.year = cpu_to_le16(1900 + tm.tm_year);
4708         req.month = 1 + tm.tm_mon;
4709         req.day = tm.tm_mday;
4710         req.hour = tm.tm_hour;
4711         req.minute = tm.tm_min;
4712         req.second = tm.tm_sec;
4713         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4714 #else
4715         return -EOPNOTSUPP;
4716 #endif
4717 }
4718
4719 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4720 {
4721         int rc;
4722         struct bnxt_pf_info *pf = &bp->pf;
4723         struct hwrm_port_qstats_input req = {0};
4724
4725         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4726                 return 0;
4727
4728         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4729         req.port_id = cpu_to_le16(pf->port_id);
4730         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4731         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4732         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4733         return rc;
4734 }
4735
4736 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4737 {
4738         if (bp->vxlan_port_cnt) {
4739                 bnxt_hwrm_tunnel_dst_port_free(
4740                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4741         }
4742         bp->vxlan_port_cnt = 0;
4743         if (bp->nge_port_cnt) {
4744                 bnxt_hwrm_tunnel_dst_port_free(
4745                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4746         }
4747         bp->nge_port_cnt = 0;
4748 }
4749
4750 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4751 {
4752         int rc, i;
4753         u32 tpa_flags = 0;
4754
4755         if (set_tpa)
4756                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4757         for (i = 0; i < bp->nr_vnics; i++) {
4758                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4759                 if (rc) {
4760                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4761                                    i, rc);
4762                         return rc;
4763                 }
4764         }
4765         return 0;
4766 }
4767
4768 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4769 {
4770         int i;
4771
4772         for (i = 0; i < bp->nr_vnics; i++)
4773                 bnxt_hwrm_vnic_set_rss(bp, i, false);
4774 }
4775
4776 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4777                                     bool irq_re_init)
4778 {
4779         if (bp->vnic_info) {
4780                 bnxt_hwrm_clear_vnic_filter(bp);
4781                 /* clear all RSS setting before free vnic ctx */
4782                 bnxt_hwrm_clear_vnic_rss(bp);
4783                 bnxt_hwrm_vnic_ctx_free(bp);
4784                 /* before free the vnic, undo the vnic tpa settings */
4785                 if (bp->flags & BNXT_FLAG_TPA)
4786                         bnxt_set_tpa(bp, false);
4787                 bnxt_hwrm_vnic_free(bp);
4788         }
4789         bnxt_hwrm_ring_free(bp, close_path);
4790         bnxt_hwrm_ring_grp_free(bp);
4791         if (irq_re_init) {
4792                 bnxt_hwrm_stat_ctx_free(bp);
4793                 bnxt_hwrm_free_tunnel_ports(bp);
4794         }
4795 }
4796
4797 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4798 {
4799         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4800         int rc;
4801
4802         if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
4803                 goto skip_rss_ctx;
4804
4805         /* allocate context for vnic */
4806         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
4807         if (rc) {
4808                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4809                            vnic_id, rc);
4810                 goto vnic_setup_err;
4811         }
4812         bp->rsscos_nr_ctxs++;
4813
4814         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
4815                 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
4816                 if (rc) {
4817                         netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
4818                                    vnic_id, rc);
4819                         goto vnic_setup_err;
4820                 }
4821                 bp->rsscos_nr_ctxs++;
4822         }
4823
4824 skip_rss_ctx:
4825         /* configure default vnic, ring grp */
4826         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4827         if (rc) {
4828                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4829                            vnic_id, rc);
4830                 goto vnic_setup_err;
4831         }
4832
4833         /* Enable RSS hashing on vnic */
4834         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4835         if (rc) {
4836                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4837                            vnic_id, rc);
4838                 goto vnic_setup_err;
4839         }
4840
4841         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4842                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4843                 if (rc) {
4844                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4845                                    vnic_id, rc);
4846                 }
4847         }
4848
4849 vnic_setup_err:
4850         return rc;
4851 }
4852
4853 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4854 {
4855 #ifdef CONFIG_RFS_ACCEL
4856         int i, rc = 0;
4857
4858         for (i = 0; i < bp->rx_nr_rings; i++) {
4859                 struct bnxt_vnic_info *vnic;
4860                 u16 vnic_id = i + 1;
4861                 u16 ring_id = i;
4862
4863                 if (vnic_id >= bp->nr_vnics)
4864                         break;
4865
4866                 vnic = &bp->vnic_info[vnic_id];
4867                 vnic->flags |= BNXT_VNIC_RFS_FLAG;
4868                 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
4869                         vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
4870                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
4871                 if (rc) {
4872                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4873                                    vnic_id, rc);
4874                         break;
4875                 }
4876                 rc = bnxt_setup_vnic(bp, vnic_id);
4877                 if (rc)
4878                         break;
4879         }
4880         return rc;
4881 #else
4882         return 0;
4883 #endif
4884 }
4885
4886 /* Allow PF and VF with default VLAN to be in promiscuous mode */
4887 static bool bnxt_promisc_ok(struct bnxt *bp)
4888 {
4889 #ifdef CONFIG_BNXT_SRIOV
4890         if (BNXT_VF(bp) && !bp->vf.vlan)
4891                 return false;
4892 #endif
4893         return true;
4894 }
4895
4896 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
4897 {
4898         unsigned int rc = 0;
4899
4900         rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
4901         if (rc) {
4902                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4903                            rc);
4904                 return rc;
4905         }
4906
4907         rc = bnxt_hwrm_vnic_cfg(bp, 1);
4908         if (rc) {
4909                 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
4910                            rc);
4911                 return rc;
4912         }
4913         return rc;
4914 }
4915
4916 static int bnxt_cfg_rx_mode(struct bnxt *);
4917 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
4918
4919 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4920 {
4921         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4922         int rc = 0;
4923         unsigned int rx_nr_rings = bp->rx_nr_rings;
4924
4925         if (irq_re_init) {
4926                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4927                 if (rc) {
4928                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4929                                    rc);
4930                         goto err_out;
4931                 }
4932         }
4933
4934         rc = bnxt_hwrm_ring_alloc(bp);
4935         if (rc) {
4936                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4937                 goto err_out;
4938         }
4939
4940         rc = bnxt_hwrm_ring_grp_alloc(bp);
4941         if (rc) {
4942                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4943                 goto err_out;
4944         }
4945
4946         if (BNXT_CHIP_TYPE_NITRO_A0(bp))
4947                 rx_nr_rings--;
4948
4949         /* default vnic 0 */
4950         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
4951         if (rc) {
4952                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4953                 goto err_out;
4954         }
4955
4956         rc = bnxt_setup_vnic(bp, 0);
4957         if (rc)
4958                 goto err_out;
4959
4960         if (bp->flags & BNXT_FLAG_RFS) {
4961                 rc = bnxt_alloc_rfs_vnics(bp);
4962                 if (rc)
4963                         goto err_out;
4964         }
4965
4966         if (bp->flags & BNXT_FLAG_TPA) {
4967                 rc = bnxt_set_tpa(bp, true);
4968                 if (rc)
4969                         goto err_out;
4970         }
4971
4972         if (BNXT_VF(bp))
4973                 bnxt_update_vf_mac(bp);
4974
4975         /* Filter for default vnic 0 */
4976         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4977         if (rc) {
4978                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4979                 goto err_out;
4980         }
4981         vnic->uc_filter_count = 1;
4982
4983         vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
4984
4985         if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
4986                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4987
4988         if (bp->dev->flags & IFF_ALLMULTI) {
4989                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4990                 vnic->mc_list_count = 0;
4991         } else {
4992                 u32 mask = 0;
4993
4994                 bnxt_mc_list_updated(bp, &mask);
4995                 vnic->rx_mask |= mask;
4996         }
4997
4998         rc = bnxt_cfg_rx_mode(bp);
4999         if (rc)
5000                 goto err_out;
5001
5002         rc = bnxt_hwrm_set_coal(bp);
5003         if (rc)
5004                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
5005                                 rc);
5006
5007         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5008                 rc = bnxt_setup_nitroa0_vnic(bp);
5009                 if (rc)
5010                         netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
5011                                    rc);
5012         }
5013
5014         if (BNXT_VF(bp)) {
5015                 bnxt_hwrm_func_qcfg(bp);
5016                 netdev_update_features(bp->dev);
5017         }
5018
5019         return 0;
5020
5021 err_out:
5022         bnxt_hwrm_resource_free(bp, 0, true);
5023
5024         return rc;
5025 }
5026
5027 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
5028 {
5029         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
5030         return 0;
5031 }
5032
5033 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
5034 {
5035         bnxt_init_cp_rings(bp);
5036         bnxt_init_rx_rings(bp);
5037         bnxt_init_tx_rings(bp);
5038         bnxt_init_ring_grps(bp, irq_re_init);
5039         bnxt_init_vnics(bp);
5040
5041         return bnxt_init_chip(bp, irq_re_init);
5042 }
5043
5044 static int bnxt_set_real_num_queues(struct bnxt *bp)
5045 {
5046         int rc;
5047         struct net_device *dev = bp->dev;
5048
5049         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
5050                                           bp->tx_nr_rings_xdp);
5051         if (rc)
5052                 return rc;
5053
5054         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
5055         if (rc)
5056                 return rc;
5057
5058 #ifdef CONFIG_RFS_ACCEL
5059         if (bp->flags & BNXT_FLAG_RFS)
5060                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
5061 #endif
5062
5063         return rc;
5064 }
5065
5066 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5067                            bool shared)
5068 {
5069         int _rx = *rx, _tx = *tx;
5070
5071         if (shared) {
5072                 *rx = min_t(int, _rx, max);
5073                 *tx = min_t(int, _tx, max);
5074         } else {
5075                 if (max < 2)
5076                         return -ENOMEM;
5077
5078                 while (_rx + _tx > max) {
5079                         if (_rx > _tx && _rx > 1)
5080                                 _rx--;
5081                         else if (_tx > 1)
5082                                 _tx--;
5083                 }
5084                 *rx = _rx;
5085                 *tx = _tx;
5086         }
5087         return 0;
5088 }
5089
5090 static void bnxt_setup_msix(struct bnxt *bp)
5091 {
5092         const int len = sizeof(bp->irq_tbl[0].name);
5093         struct net_device *dev = bp->dev;
5094         int tcs, i;
5095
5096         tcs = netdev_get_num_tc(dev);
5097         if (tcs > 1) {
5098                 int i, off, count;
5099
5100                 for (i = 0; i < tcs; i++) {
5101                         count = bp->tx_nr_rings_per_tc;
5102                         off = i * count;
5103                         netdev_set_tc_queue(dev, i, count, off);
5104                 }
5105         }
5106
5107         for (i = 0; i < bp->cp_nr_rings; i++) {
5108                 char *attr;
5109
5110                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5111                         attr = "TxRx";
5112                 else if (i < bp->rx_nr_rings)
5113                         attr = "rx";
5114                 else
5115                         attr = "tx";
5116
5117                 snprintf(bp->irq_tbl[i].name, len, "%s-%s-%d", dev->name, attr,
5118                          i);
5119                 bp->irq_tbl[i].handler = bnxt_msix;
5120         }
5121 }
5122
5123 static void bnxt_setup_inta(struct bnxt *bp)
5124 {
5125         const int len = sizeof(bp->irq_tbl[0].name);
5126
5127         if (netdev_get_num_tc(bp->dev))
5128                 netdev_reset_tc(bp->dev);
5129
5130         snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
5131                  0);
5132         bp->irq_tbl[0].handler = bnxt_inta;
5133 }
5134
5135 static int bnxt_setup_int_mode(struct bnxt *bp)
5136 {
5137         int rc;
5138
5139         if (bp->flags & BNXT_FLAG_USING_MSIX)
5140                 bnxt_setup_msix(bp);
5141         else
5142                 bnxt_setup_inta(bp);
5143
5144         rc = bnxt_set_real_num_queues(bp);
5145         return rc;
5146 }
5147
5148 #ifdef CONFIG_RFS_ACCEL
5149 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
5150 {
5151 #if defined(CONFIG_BNXT_SRIOV)
5152         if (BNXT_VF(bp))
5153                 return bp->vf.max_rsscos_ctxs;
5154 #endif
5155         return bp->pf.max_rsscos_ctxs;
5156 }
5157
5158 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
5159 {
5160 #if defined(CONFIG_BNXT_SRIOV)
5161         if (BNXT_VF(bp))
5162                 return bp->vf.max_vnics;
5163 #endif
5164         return bp->pf.max_vnics;
5165 }
5166 #endif
5167
5168 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
5169 {
5170 #if defined(CONFIG_BNXT_SRIOV)
5171         if (BNXT_VF(bp))
5172                 return bp->vf.max_stat_ctxs;
5173 #endif
5174         return bp->pf.max_stat_ctxs;
5175 }
5176
5177 void bnxt_set_max_func_stat_ctxs(struct bnxt *bp, unsigned int max)
5178 {
5179 #if defined(CONFIG_BNXT_SRIOV)
5180         if (BNXT_VF(bp))
5181                 bp->vf.max_stat_ctxs = max;
5182         else
5183 #endif
5184                 bp->pf.max_stat_ctxs = max;
5185 }
5186
5187 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
5188 {
5189 #if defined(CONFIG_BNXT_SRIOV)
5190         if (BNXT_VF(bp))
5191                 return bp->vf.max_cp_rings;
5192 #endif
5193         return bp->pf.max_cp_rings;
5194 }
5195
5196 void bnxt_set_max_func_cp_rings(struct bnxt *bp, unsigned int max)
5197 {
5198 #if defined(CONFIG_BNXT_SRIOV)
5199         if (BNXT_VF(bp))
5200                 bp->vf.max_cp_rings = max;
5201         else
5202 #endif
5203                 bp->pf.max_cp_rings = max;
5204 }
5205
5206 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
5207 {
5208 #if defined(CONFIG_BNXT_SRIOV)
5209         if (BNXT_VF(bp))
5210                 return min_t(unsigned int, bp->vf.max_irqs,
5211                              bp->vf.max_cp_rings);
5212 #endif
5213         return min_t(unsigned int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5214 }
5215
5216 void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
5217 {
5218 #if defined(CONFIG_BNXT_SRIOV)
5219         if (BNXT_VF(bp))
5220                 bp->vf.max_irqs = max_irqs;
5221         else
5222 #endif
5223                 bp->pf.max_irqs = max_irqs;
5224 }
5225
5226 static int bnxt_init_msix(struct bnxt *bp)
5227 {
5228         int i, total_vecs, rc = 0, min = 1;
5229         struct msix_entry *msix_ent;
5230
5231         total_vecs = bnxt_get_max_func_irqs(bp);
5232         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
5233         if (!msix_ent)
5234                 return -ENOMEM;
5235
5236         for (i = 0; i < total_vecs; i++) {
5237                 msix_ent[i].entry = i;
5238                 msix_ent[i].vector = 0;
5239         }
5240
5241         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
5242                 min = 2;
5243
5244         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
5245         if (total_vecs < 0) {
5246                 rc = -ENODEV;
5247                 goto msix_setup_exit;
5248         }
5249
5250         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
5251         if (bp->irq_tbl) {
5252                 for (i = 0; i < total_vecs; i++)
5253                         bp->irq_tbl[i].vector = msix_ent[i].vector;
5254
5255                 bp->total_irqs = total_vecs;
5256                 /* Trim rings based upon num of vectors allocated */
5257                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
5258                                      total_vecs, min == 1);
5259                 if (rc)
5260                         goto msix_setup_exit;
5261
5262                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5263                 bp->cp_nr_rings = (min == 1) ?
5264                                   max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5265                                   bp->tx_nr_rings + bp->rx_nr_rings;
5266
5267         } else {
5268                 rc = -ENOMEM;
5269                 goto msix_setup_exit;
5270         }
5271         bp->flags |= BNXT_FLAG_USING_MSIX;
5272         kfree(msix_ent);
5273         return 0;
5274
5275 msix_setup_exit:
5276         netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
5277         kfree(bp->irq_tbl);
5278         bp->irq_tbl = NULL;
5279         pci_disable_msix(bp->pdev);
5280         kfree(msix_ent);
5281         return rc;
5282 }
5283
5284 static int bnxt_init_inta(struct bnxt *bp)
5285 {
5286         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
5287         if (!bp->irq_tbl)
5288                 return -ENOMEM;
5289
5290         bp->total_irqs = 1;
5291         bp->rx_nr_rings = 1;
5292         bp->tx_nr_rings = 1;
5293         bp->cp_nr_rings = 1;
5294         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
5295         bp->flags |= BNXT_FLAG_SHARED_RINGS;
5296         bp->irq_tbl[0].vector = bp->pdev->irq;
5297         return 0;
5298 }
5299
5300 static int bnxt_init_int_mode(struct bnxt *bp)
5301 {
5302         int rc = 0;
5303
5304         if (bp->flags & BNXT_FLAG_MSIX_CAP)
5305                 rc = bnxt_init_msix(bp);
5306
5307         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
5308                 /* fallback to INTA */
5309                 rc = bnxt_init_inta(bp);
5310         }
5311         return rc;
5312 }
5313
5314 static void bnxt_clear_int_mode(struct bnxt *bp)
5315 {
5316         if (bp->flags & BNXT_FLAG_USING_MSIX)
5317                 pci_disable_msix(bp->pdev);
5318
5319         kfree(bp->irq_tbl);
5320         bp->irq_tbl = NULL;
5321         bp->flags &= ~BNXT_FLAG_USING_MSIX;
5322 }
5323
5324 static void bnxt_free_irq(struct bnxt *bp)
5325 {
5326         struct bnxt_irq *irq;
5327         int i;
5328
5329 #ifdef CONFIG_RFS_ACCEL
5330         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
5331         bp->dev->rx_cpu_rmap = NULL;
5332 #endif
5333         if (!bp->irq_tbl)
5334                 return;
5335
5336         for (i = 0; i < bp->cp_nr_rings; i++) {
5337                 irq = &bp->irq_tbl[i];
5338                 if (irq->requested)
5339                         free_irq(irq->vector, bp->bnapi[i]);
5340                 irq->requested = 0;
5341         }
5342 }
5343
5344 static int bnxt_request_irq(struct bnxt *bp)
5345 {
5346         int i, j, rc = 0;
5347         unsigned long flags = 0;
5348 #ifdef CONFIG_RFS_ACCEL
5349         struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
5350 #endif
5351
5352         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
5353                 flags = IRQF_SHARED;
5354
5355         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
5356                 struct bnxt_irq *irq = &bp->irq_tbl[i];
5357 #ifdef CONFIG_RFS_ACCEL
5358                 if (rmap && bp->bnapi[i]->rx_ring) {
5359                         rc = irq_cpu_rmap_add(rmap, irq->vector);
5360                         if (rc)
5361                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
5362                                             j);
5363                         j++;
5364                 }
5365 #endif
5366                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5367                                  bp->bnapi[i]);
5368                 if (rc)
5369                         break;
5370
5371                 irq->requested = 1;
5372         }
5373         return rc;
5374 }
5375
5376 static void bnxt_del_napi(struct bnxt *bp)
5377 {
5378         int i;
5379
5380         if (!bp->bnapi)
5381                 return;
5382
5383         for (i = 0; i < bp->cp_nr_rings; i++) {
5384                 struct bnxt_napi *bnapi = bp->bnapi[i];
5385
5386                 napi_hash_del(&bnapi->napi);
5387                 netif_napi_del(&bnapi->napi);
5388         }
5389         /* We called napi_hash_del() before netif_napi_del(), we need
5390          * to respect an RCU grace period before freeing napi structures.
5391          */
5392         synchronize_net();
5393 }
5394
5395 static void bnxt_init_napi(struct bnxt *bp)
5396 {
5397         int i;
5398         unsigned int cp_nr_rings = bp->cp_nr_rings;
5399         struct bnxt_napi *bnapi;
5400
5401         if (bp->flags & BNXT_FLAG_USING_MSIX) {
5402                 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5403                         cp_nr_rings--;
5404                 for (i = 0; i < cp_nr_rings; i++) {
5405                         bnapi = bp->bnapi[i];
5406                         netif_napi_add(bp->dev, &bnapi->napi,
5407                                        bnxt_poll, 64);
5408                 }
5409                 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
5410                         bnapi = bp->bnapi[cp_nr_rings];
5411                         netif_napi_add(bp->dev, &bnapi->napi,
5412                                        bnxt_poll_nitroa0, 64);
5413                 }
5414         } else {
5415                 bnapi = bp->bnapi[0];
5416                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
5417         }
5418 }
5419
5420 static void bnxt_disable_napi(struct bnxt *bp)
5421 {
5422         int i;
5423
5424         if (!bp->bnapi)
5425                 return;
5426
5427         for (i = 0; i < bp->cp_nr_rings; i++)
5428                 napi_disable(&bp->bnapi[i]->napi);
5429 }
5430
5431 static void bnxt_enable_napi(struct bnxt *bp)
5432 {
5433         int i;
5434
5435         for (i = 0; i < bp->cp_nr_rings; i++) {
5436                 bp->bnapi[i]->in_reset = false;
5437                 napi_enable(&bp->bnapi[i]->napi);
5438         }
5439 }
5440
5441 void bnxt_tx_disable(struct bnxt *bp)
5442 {
5443         int i;
5444         struct bnxt_tx_ring_info *txr;
5445         struct netdev_queue *txq;
5446
5447         if (bp->tx_ring) {
5448                 for (i = 0; i < bp->tx_nr_rings; i++) {
5449                         txr = &bp->tx_ring[i];
5450                         txq = netdev_get_tx_queue(bp->dev, i);
5451                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
5452                 }
5453         }
5454         /* Stop all TX queues */
5455         netif_tx_disable(bp->dev);
5456         netif_carrier_off(bp->dev);
5457 }
5458
5459 void bnxt_tx_enable(struct bnxt *bp)
5460 {
5461         int i;
5462         struct bnxt_tx_ring_info *txr;
5463         struct netdev_queue *txq;
5464
5465         for (i = 0; i < bp->tx_nr_rings; i++) {
5466                 txr = &bp->tx_ring[i];
5467                 txq = netdev_get_tx_queue(bp->dev, i);
5468                 txr->dev_state = 0;
5469         }
5470         netif_tx_wake_all_queues(bp->dev);
5471         if (bp->link_info.link_up)
5472                 netif_carrier_on(bp->dev);
5473 }
5474
5475 static void bnxt_report_link(struct bnxt *bp)
5476 {
5477         if (bp->link_info.link_up) {
5478                 const char *duplex;
5479                 const char *flow_ctrl;
5480                 u32 speed;
5481                 u16 fec;
5482
5483                 netif_carrier_on(bp->dev);
5484                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
5485                         duplex = "full";
5486                 else
5487                         duplex = "half";
5488                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
5489                         flow_ctrl = "ON - receive & transmit";
5490                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
5491                         flow_ctrl = "ON - transmit";
5492                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
5493                         flow_ctrl = "ON - receive";
5494                 else
5495                         flow_ctrl = "none";
5496                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
5497                 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
5498                             speed, duplex, flow_ctrl);
5499                 if (bp->flags & BNXT_FLAG_EEE_CAP)
5500                         netdev_info(bp->dev, "EEE is %s\n",
5501                                     bp->eee.eee_active ? "active" :
5502                                                          "not active");
5503                 fec = bp->link_info.fec_cfg;
5504                 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
5505                         netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",
5506                                     (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
5507                                     (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :
5508                                      (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");
5509         } else {
5510                 netif_carrier_off(bp->dev);
5511                 netdev_err(bp->dev, "NIC Link is Down\n");
5512         }
5513 }
5514
5515 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
5516 {
5517         int rc = 0;
5518         struct hwrm_port_phy_qcaps_input req = {0};
5519         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5520         struct bnxt_link_info *link_info = &bp->link_info;
5521
5522         if (bp->hwrm_spec_code < 0x10201)
5523                 return 0;
5524
5525         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
5526
5527         mutex_lock(&bp->hwrm_cmd_lock);
5528         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5529         if (rc)
5530                 goto hwrm_phy_qcaps_exit;
5531
5532         if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
5533                 struct ethtool_eee *eee = &bp->eee;
5534                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
5535
5536                 bp->flags |= BNXT_FLAG_EEE_CAP;
5537                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5538                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
5539                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
5540                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
5541                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
5542         }
5543         if (resp->supported_speeds_auto_mode)
5544                 link_info->support_auto_speeds =
5545                         le16_to_cpu(resp->supported_speeds_auto_mode);
5546
5547 hwrm_phy_qcaps_exit:
5548         mutex_unlock(&bp->hwrm_cmd_lock);
5549         return rc;
5550 }
5551
5552 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
5553 {
5554         int rc = 0;
5555         struct bnxt_link_info *link_info = &bp->link_info;
5556         struct hwrm_port_phy_qcfg_input req = {0};
5557         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5558         u8 link_up = link_info->link_up;
5559         u16 diff;
5560
5561         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
5562
5563         mutex_lock(&bp->hwrm_cmd_lock);
5564         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5565         if (rc) {
5566                 mutex_unlock(&bp->hwrm_cmd_lock);
5567                 return rc;
5568         }
5569
5570         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
5571         link_info->phy_link_status = resp->link;
5572         link_info->duplex =  resp->duplex;
5573         link_info->pause = resp->pause;
5574         link_info->auto_mode = resp->auto_mode;
5575         link_info->auto_pause_setting = resp->auto_pause;
5576         link_info->lp_pause = resp->link_partner_adv_pause;
5577         link_info->force_pause_setting = resp->force_pause;
5578         link_info->duplex_setting = resp->duplex;
5579         if (link_info->phy_link_status == BNXT_LINK_LINK)
5580                 link_info->link_speed = le16_to_cpu(resp->link_speed);
5581         else
5582                 link_info->link_speed = 0;
5583         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
5584         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
5585         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
5586         link_info->lp_auto_link_speeds =
5587                 le16_to_cpu(resp->link_partner_adv_speeds);
5588         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
5589         link_info->phy_ver[0] = resp->phy_maj;
5590         link_info->phy_ver[1] = resp->phy_min;
5591         link_info->phy_ver[2] = resp->phy_bld;
5592         link_info->media_type = resp->media_type;
5593         link_info->phy_type = resp->phy_type;
5594         link_info->transceiver = resp->xcvr_pkg_type;
5595         link_info->phy_addr = resp->eee_config_phy_addr &
5596                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
5597         link_info->module_status = resp->module_status;
5598
5599         if (bp->flags & BNXT_FLAG_EEE_CAP) {
5600                 struct ethtool_eee *eee = &bp->eee;
5601                 u16 fw_speeds;
5602
5603                 eee->eee_active = 0;
5604                 if (resp->eee_config_phy_addr &
5605                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
5606                         eee->eee_active = 1;
5607                         fw_speeds = le16_to_cpu(
5608                                 resp->link_partner_adv_eee_link_speed_mask);
5609                         eee->lp_advertised =
5610                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5611                 }
5612
5613                 /* Pull initial EEE config */
5614                 if (!chng_link_state) {
5615                         if (resp->eee_config_phy_addr &
5616                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
5617                                 eee->eee_enabled = 1;
5618
5619                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
5620                         eee->advertised =
5621                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
5622
5623                         if (resp->eee_config_phy_addr &
5624                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
5625                                 __le32 tmr;
5626
5627                                 eee->tx_lpi_enabled = 1;
5628                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
5629                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
5630                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
5631                         }
5632                 }
5633         }
5634
5635         link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
5636         if (bp->hwrm_spec_code >= 0x10504)
5637                 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
5638
5639         /* TODO: need to add more logic to report VF link */
5640         if (chng_link_state) {
5641                 if (link_info->phy_link_status == BNXT_LINK_LINK)
5642                         link_info->link_up = 1;
5643                 else
5644                         link_info->link_up = 0;
5645                 if (link_up != link_info->link_up)
5646                         bnxt_report_link(bp);
5647         } else {
5648                 /* alwasy link down if not require to update link state */
5649                 link_info->link_up = 0;
5650         }
5651         mutex_unlock(&bp->hwrm_cmd_lock);
5652
5653         diff = link_info->support_auto_speeds ^ link_info->advertising;
5654         if ((link_info->support_auto_speeds | diff) !=
5655             link_info->support_auto_speeds) {
5656                 /* An advertised speed is no longer supported, so we need to
5657                  * update the advertisement settings.  Caller holds RTNL
5658                  * so we can modify link settings.
5659                  */
5660                 link_info->advertising = link_info->support_auto_speeds;
5661                 if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5662                         bnxt_hwrm_set_link_setting(bp, true, false);
5663         }
5664         return 0;
5665 }
5666
5667 static void bnxt_get_port_module_status(struct bnxt *bp)
5668 {
5669         struct bnxt_link_info *link_info = &bp->link_info;
5670         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
5671         u8 module_status;
5672
5673         if (bnxt_update_link(bp, true))
5674                 return;
5675
5676         module_status = link_info->module_status;
5677         switch (module_status) {
5678         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
5679         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
5680         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
5681                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
5682                             bp->pf.port_id);
5683                 if (bp->hwrm_spec_code >= 0x10201) {
5684                         netdev_warn(bp->dev, "Module part number %s\n",
5685                                     resp->phy_vendor_partnumber);
5686                 }
5687                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
5688                         netdev_warn(bp->dev, "TX is disabled\n");
5689                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
5690                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
5691         }
5692 }
5693
5694 static void
5695 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
5696 {
5697         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
5698                 if (bp->hwrm_spec_code >= 0x10201)
5699                         req->auto_pause =
5700                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
5701                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5702                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
5703                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5704                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
5705                 req->enables |=
5706                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5707         } else {
5708                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
5709                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
5710                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
5711                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
5712                 req->enables |=
5713                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
5714                 if (bp->hwrm_spec_code >= 0x10201) {
5715                         req->auto_pause = req->force_pause;
5716                         req->enables |= cpu_to_le32(
5717                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
5718                 }
5719         }
5720 }
5721
5722 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
5723                                       struct hwrm_port_phy_cfg_input *req)
5724 {
5725         u8 autoneg = bp->link_info.autoneg;
5726         u16 fw_link_speed = bp->link_info.req_link_speed;
5727         u16 advertising = bp->link_info.advertising;
5728
5729         if (autoneg & BNXT_AUTONEG_SPEED) {
5730                 req->auto_mode |=
5731                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
5732
5733                 req->enables |= cpu_to_le32(
5734                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
5735                 req->auto_link_speed_mask = cpu_to_le16(advertising);
5736
5737                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
5738                 req->flags |=
5739                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
5740         } else {
5741                 req->force_link_speed = cpu_to_le16(fw_link_speed);
5742                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
5743         }
5744
5745         /* tell chimp that the setting takes effect immediately */
5746         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
5747 }
5748
5749 int bnxt_hwrm_set_pause(struct bnxt *bp)
5750 {
5751         struct hwrm_port_phy_cfg_input req = {0};
5752         int rc;
5753
5754         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5755         bnxt_hwrm_set_pause_common(bp, &req);
5756
5757         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
5758             bp->link_info.force_link_chng)
5759                 bnxt_hwrm_set_link_common(bp, &req);
5760
5761         mutex_lock(&bp->hwrm_cmd_lock);
5762         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5763         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
5764                 /* since changing of pause setting doesn't trigger any link
5765                  * change event, the driver needs to update the current pause
5766                  * result upon successfully return of the phy_cfg command
5767                  */
5768                 bp->link_info.pause =
5769                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
5770                 bp->link_info.auto_pause_setting = 0;
5771                 if (!bp->link_info.force_link_chng)
5772                         bnxt_report_link(bp);
5773         }
5774         bp->link_info.force_link_chng = false;
5775         mutex_unlock(&bp->hwrm_cmd_lock);
5776         return rc;
5777 }
5778
5779 static void bnxt_hwrm_set_eee(struct bnxt *bp,
5780                               struct hwrm_port_phy_cfg_input *req)
5781 {
5782         struct ethtool_eee *eee = &bp->eee;
5783
5784         if (eee->eee_enabled) {
5785                 u16 eee_speeds;
5786                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
5787
5788                 if (eee->tx_lpi_enabled)
5789                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
5790                 else
5791                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
5792
5793                 req->flags |= cpu_to_le32(flags);
5794                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
5795                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
5796                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
5797         } else {
5798                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
5799         }
5800 }
5801
5802 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
5803 {
5804         struct hwrm_port_phy_cfg_input req = {0};
5805
5806         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5807         if (set_pause)
5808                 bnxt_hwrm_set_pause_common(bp, &req);
5809
5810         bnxt_hwrm_set_link_common(bp, &req);
5811
5812         if (set_eee)
5813                 bnxt_hwrm_set_eee(bp, &req);
5814         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5815 }
5816
5817 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
5818 {
5819         struct hwrm_port_phy_cfg_input req = {0};
5820
5821         if (!BNXT_SINGLE_PF(bp))
5822                 return 0;
5823
5824         if (pci_num_vf(bp->pdev))
5825                 return 0;
5826
5827         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
5828         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
5829         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5830 }
5831
5832 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
5833 {
5834         struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5835         struct hwrm_port_led_qcaps_input req = {0};
5836         struct bnxt_pf_info *pf = &bp->pf;
5837         int rc;
5838
5839         if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
5840                 return 0;
5841
5842         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
5843         req.port_id = cpu_to_le16(pf->port_id);
5844         mutex_lock(&bp->hwrm_cmd_lock);
5845         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5846         if (rc) {
5847                 mutex_unlock(&bp->hwrm_cmd_lock);
5848                 return rc;
5849         }
5850         if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
5851                 int i;
5852
5853                 bp->num_leds = resp->num_leds;
5854                 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
5855                                                  bp->num_leds);
5856                 for (i = 0; i < bp->num_leds; i++) {
5857                         struct bnxt_led_info *led = &bp->leds[i];
5858                         __le16 caps = led->led_state_caps;
5859
5860                         if (!led->led_group_id ||
5861                             !BNXT_LED_ALT_BLINK_CAP(caps)) {
5862                                 bp->num_leds = 0;
5863                                 break;
5864                         }
5865                 }
5866         }
5867         mutex_unlock(&bp->hwrm_cmd_lock);
5868         return 0;
5869 }
5870
5871 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
5872 {
5873         struct hwrm_wol_filter_alloc_input req = {0};
5874         struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5875         int rc;
5876
5877         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
5878         req.port_id = cpu_to_le16(bp->pf.port_id);
5879         req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
5880         req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
5881         memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
5882         mutex_lock(&bp->hwrm_cmd_lock);
5883         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5884         if (!rc)
5885                 bp->wol_filter_id = resp->wol_filter_id;
5886         mutex_unlock(&bp->hwrm_cmd_lock);
5887         return rc;
5888 }
5889
5890 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
5891 {
5892         struct hwrm_wol_filter_free_input req = {0};
5893         int rc;
5894
5895         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
5896         req.port_id = cpu_to_le16(bp->pf.port_id);
5897         req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
5898         req.wol_filter_id = bp->wol_filter_id;
5899         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5900         return rc;
5901 }
5902
5903 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
5904 {
5905         struct hwrm_wol_filter_qcfg_input req = {0};
5906         struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5907         u16 next_handle = 0;
5908         int rc;
5909
5910         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
5911         req.port_id = cpu_to_le16(bp->pf.port_id);
5912         req.handle = cpu_to_le16(handle);
5913         mutex_lock(&bp->hwrm_cmd_lock);
5914         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5915         if (!rc) {
5916                 next_handle = le16_to_cpu(resp->next_handle);
5917                 if (next_handle != 0) {
5918                         if (resp->wol_type ==
5919                             WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
5920                                 bp->wol = 1;
5921                                 bp->wol_filter_id = resp->wol_filter_id;
5922                         }
5923                 }
5924         }
5925         mutex_unlock(&bp->hwrm_cmd_lock);
5926         return next_handle;
5927 }
5928
5929 static void bnxt_get_wol_settings(struct bnxt *bp)
5930 {
5931         u16 handle = 0;
5932
5933         if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
5934                 return;
5935
5936         do {
5937                 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
5938         } while (handle && handle != 0xffff);
5939 }
5940
5941 static bool bnxt_eee_config_ok(struct bnxt *bp)
5942 {
5943         struct ethtool_eee *eee = &bp->eee;
5944         struct bnxt_link_info *link_info = &bp->link_info;
5945
5946         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
5947                 return true;
5948
5949         if (eee->eee_enabled) {
5950                 u32 advertising =
5951                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
5952
5953                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5954                         eee->eee_enabled = 0;
5955                         return false;
5956                 }
5957                 if (eee->advertised & ~advertising) {
5958                         eee->advertised = advertising & eee->supported;
5959                         return false;
5960                 }
5961         }
5962         return true;
5963 }
5964
5965 static int bnxt_update_phy_setting(struct bnxt *bp)
5966 {
5967         int rc;
5968         bool update_link = false;
5969         bool update_pause = false;
5970         bool update_eee = false;
5971         struct bnxt_link_info *link_info = &bp->link_info;
5972
5973         rc = bnxt_update_link(bp, true);
5974         if (rc) {
5975                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
5976                            rc);
5977                 return rc;
5978         }
5979         if (!BNXT_SINGLE_PF(bp))
5980                 return 0;
5981
5982         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5983             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
5984             link_info->req_flow_ctrl)
5985                 update_pause = true;
5986         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5987             link_info->force_pause_setting != link_info->req_flow_ctrl)
5988                 update_pause = true;
5989         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5990                 if (BNXT_AUTO_MODE(link_info->auto_mode))
5991                         update_link = true;
5992                 if (link_info->req_link_speed != link_info->force_link_speed)
5993                         update_link = true;
5994                 if (link_info->req_duplex != link_info->duplex_setting)
5995                         update_link = true;
5996         } else {
5997                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
5998                         update_link = true;
5999                 if (link_info->advertising != link_info->auto_link_speeds)
6000                         update_link = true;
6001         }
6002
6003         /* The last close may have shutdown the link, so need to call
6004          * PHY_CFG to bring it back up.
6005          */
6006         if (!netif_carrier_ok(bp->dev))
6007                 update_link = true;
6008
6009         if (!bnxt_eee_config_ok(bp))
6010                 update_eee = true;
6011
6012         if (update_link)
6013                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
6014         else if (update_pause)
6015                 rc = bnxt_hwrm_set_pause(bp);
6016         if (rc) {
6017                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
6018                            rc);
6019                 return rc;
6020         }
6021
6022         return rc;
6023 }
6024
6025 /* Common routine to pre-map certain register block to different GRC window.
6026  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
6027  * in PF and 3 windows in VF that can be customized to map in different
6028  * register blocks.
6029  */
6030 static void bnxt_preset_reg_win(struct bnxt *bp)
6031 {
6032         if (BNXT_PF(bp)) {
6033                 /* CAG registers map to GRC window #4 */
6034                 writel(BNXT_CAG_REG_BASE,
6035                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
6036         }
6037 }
6038
6039 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6040 {
6041         int rc = 0;
6042
6043         bnxt_preset_reg_win(bp);
6044         netif_carrier_off(bp->dev);
6045         if (irq_re_init) {
6046                 rc = bnxt_setup_int_mode(bp);
6047                 if (rc) {
6048                         netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
6049                                    rc);
6050                         return rc;
6051                 }
6052         }
6053         if ((bp->flags & BNXT_FLAG_RFS) &&
6054             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
6055                 /* disable RFS if falling back to INTA */
6056                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
6057                 bp->flags &= ~BNXT_FLAG_RFS;
6058         }
6059
6060         rc = bnxt_alloc_mem(bp, irq_re_init);
6061         if (rc) {
6062                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6063                 goto open_err_free_mem;
6064         }
6065
6066         if (irq_re_init) {
6067                 bnxt_init_napi(bp);
6068                 rc = bnxt_request_irq(bp);
6069                 if (rc) {
6070                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
6071                         goto open_err;
6072                 }
6073         }
6074
6075         bnxt_enable_napi(bp);
6076
6077         rc = bnxt_init_nic(bp, irq_re_init);
6078         if (rc) {
6079                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6080                 goto open_err;
6081         }
6082
6083         if (link_re_init) {
6084                 rc = bnxt_update_phy_setting(bp);
6085                 if (rc)
6086                         netdev_warn(bp->dev, "failed to update phy settings\n");
6087         }
6088
6089         if (irq_re_init)
6090                 udp_tunnel_get_rx_info(bp->dev);
6091
6092         set_bit(BNXT_STATE_OPEN, &bp->state);
6093         bnxt_enable_int(bp);
6094         /* Enable TX queues */
6095         bnxt_tx_enable(bp);
6096         mod_timer(&bp->timer, jiffies + bp->current_interval);
6097         /* Poll link status and check for SFP+ module status */
6098         bnxt_get_port_module_status(bp);
6099
6100         return 0;
6101
6102 open_err:
6103         bnxt_disable_napi(bp);
6104         bnxt_del_napi(bp);
6105
6106 open_err_free_mem:
6107         bnxt_free_skbs(bp);
6108         bnxt_free_irq(bp);
6109         bnxt_free_mem(bp, true);
6110         return rc;
6111 }
6112
6113 /* rtnl_lock held */
6114 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6115 {
6116         int rc = 0;
6117
6118         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
6119         if (rc) {
6120                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
6121                 dev_close(bp->dev);
6122         }
6123         return rc;
6124 }
6125
6126 /* rtnl_lock held, open the NIC half way by allocating all resources, but
6127  * NAPI, IRQ, and TX are not enabled.  This is mainly used for offline
6128  * self tests.
6129  */
6130 int bnxt_half_open_nic(struct bnxt *bp)
6131 {
6132         int rc = 0;
6133
6134         rc = bnxt_alloc_mem(bp, false);
6135         if (rc) {
6136                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
6137                 goto half_open_err;
6138         }
6139         rc = bnxt_init_nic(bp, false);
6140         if (rc) {
6141                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
6142                 goto half_open_err;
6143         }
6144         return 0;
6145
6146 half_open_err:
6147         bnxt_free_skbs(bp);
6148         bnxt_free_mem(bp, false);
6149         dev_close(bp->dev);
6150         return rc;
6151 }
6152
6153 /* rtnl_lock held, this call can only be made after a previous successful
6154  * call to bnxt_half_open_nic().
6155  */
6156 void bnxt_half_close_nic(struct bnxt *bp)
6157 {
6158         bnxt_hwrm_resource_free(bp, false, false);
6159         bnxt_free_skbs(bp);
6160         bnxt_free_mem(bp, false);
6161 }
6162
6163 static int bnxt_open(struct net_device *dev)
6164 {
6165         struct bnxt *bp = netdev_priv(dev);
6166
6167         return __bnxt_open_nic(bp, true, true);
6168 }
6169
6170 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
6171 {
6172         int rc = 0;
6173
6174 #ifdef CONFIG_BNXT_SRIOV
6175         if (bp->sriov_cfg) {
6176                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
6177                                                       !bp->sriov_cfg,
6178                                                       BNXT_SRIOV_CFG_WAIT_TMO);
6179                 if (rc)
6180                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
6181         }
6182 #endif
6183         /* Change device state to avoid TX queue wake up's */
6184         bnxt_tx_disable(bp);
6185
6186         clear_bit(BNXT_STATE_OPEN, &bp->state);
6187         smp_mb__after_atomic();
6188         while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
6189                 msleep(20);
6190
6191         /* Flush rings and and disable interrupts */
6192         bnxt_shutdown_nic(bp, irq_re_init);
6193
6194         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
6195
6196         bnxt_disable_napi(bp);
6197         del_timer_sync(&bp->timer);
6198         bnxt_free_skbs(bp);
6199
6200         if (irq_re_init) {
6201                 bnxt_free_irq(bp);
6202                 bnxt_del_napi(bp);
6203         }
6204         bnxt_free_mem(bp, irq_re_init);
6205         return rc;
6206 }
6207
6208 static int bnxt_close(struct net_device *dev)
6209 {
6210         struct bnxt *bp = netdev_priv(dev);
6211
6212         bnxt_close_nic(bp, true, true);
6213         bnxt_hwrm_shutdown_link(bp);
6214         return 0;
6215 }
6216
6217 /* rtnl_lock held */
6218 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6219 {
6220         switch (cmd) {
6221         case SIOCGMIIPHY:
6222                 /* fallthru */
6223         case SIOCGMIIREG: {
6224                 if (!netif_running(dev))
6225                         return -EAGAIN;
6226
6227                 return 0;
6228         }
6229
6230         case SIOCSMIIREG:
6231                 if (!netif_running(dev))
6232                         return -EAGAIN;
6233
6234                 return 0;
6235
6236         default:
6237                 /* do nothing */
6238                 break;
6239         }
6240         return -EOPNOTSUPP;
6241 }
6242
6243 static void
6244 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6245 {
6246         u32 i;
6247         struct bnxt *bp = netdev_priv(dev);
6248
6249         if (!bp->bnapi)
6250                 return;
6251
6252         /* TODO check if we need to synchronize with bnxt_close path */
6253         for (i = 0; i < bp->cp_nr_rings; i++) {
6254                 struct bnxt_napi *bnapi = bp->bnapi[i];
6255                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6256                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
6257
6258                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
6259                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
6260                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
6261
6262                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
6263                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
6264                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
6265
6266                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
6267                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
6268                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
6269
6270                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
6271                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
6272                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
6273
6274                 stats->rx_missed_errors +=
6275                         le64_to_cpu(hw_stats->rx_discard_pkts);
6276
6277                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
6278
6279                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
6280         }
6281
6282         if (bp->flags & BNXT_FLAG_PORT_STATS) {
6283                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
6284                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
6285
6286                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
6287                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
6288                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
6289                                           le64_to_cpu(rx->rx_ovrsz_frames) +
6290                                           le64_to_cpu(rx->rx_runt_frames);
6291                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
6292                                    le64_to_cpu(rx->rx_jbr_frames);
6293                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
6294                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
6295                 stats->tx_errors = le64_to_cpu(tx->tx_err);
6296         }
6297 }
6298
6299 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
6300 {
6301         struct net_device *dev = bp->dev;
6302         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6303         struct netdev_hw_addr *ha;
6304         u8 *haddr;
6305         int mc_count = 0;
6306         bool update = false;
6307         int off = 0;
6308
6309         netdev_for_each_mc_addr(ha, dev) {
6310                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
6311                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6312                         vnic->mc_list_count = 0;
6313                         return false;
6314                 }
6315                 haddr = ha->addr;
6316                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
6317                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
6318                         update = true;
6319                 }
6320                 off += ETH_ALEN;
6321                 mc_count++;
6322         }
6323         if (mc_count)
6324                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
6325
6326         if (mc_count != vnic->mc_list_count) {
6327                 vnic->mc_list_count = mc_count;
6328                 update = true;
6329         }
6330         return update;
6331 }
6332
6333 static bool bnxt_uc_list_updated(struct bnxt *bp)
6334 {
6335         struct net_device *dev = bp->dev;
6336         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6337         struct netdev_hw_addr *ha;
6338         int off = 0;
6339
6340         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
6341                 return true;
6342
6343         netdev_for_each_uc_addr(ha, dev) {
6344                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
6345                         return true;
6346
6347                 off += ETH_ALEN;
6348         }
6349         return false;
6350 }
6351
6352 static void bnxt_set_rx_mode(struct net_device *dev)
6353 {
6354         struct bnxt *bp = netdev_priv(dev);
6355         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6356         u32 mask = vnic->rx_mask;
6357         bool mc_update = false;
6358         bool uc_update;
6359
6360         if (!netif_running(dev))
6361                 return;
6362
6363         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
6364                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
6365                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
6366
6367         if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
6368                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6369
6370         uc_update = bnxt_uc_list_updated(bp);
6371
6372         if (dev->flags & IFF_ALLMULTI) {
6373                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
6374                 vnic->mc_list_count = 0;
6375         } else {
6376                 mc_update = bnxt_mc_list_updated(bp, &mask);
6377         }
6378
6379         if (mask != vnic->rx_mask || uc_update || mc_update) {
6380                 vnic->rx_mask = mask;
6381
6382                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
6383                 schedule_work(&bp->sp_task);
6384         }
6385 }
6386
6387 static int bnxt_cfg_rx_mode(struct bnxt *bp)
6388 {
6389         struct net_device *dev = bp->dev;
6390         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
6391         struct netdev_hw_addr *ha;
6392         int i, off = 0, rc;
6393         bool uc_update;
6394
6395         netif_addr_lock_bh(dev);
6396         uc_update = bnxt_uc_list_updated(bp);
6397         netif_addr_unlock_bh(dev);
6398
6399         if (!uc_update)
6400                 goto skip_uc;
6401
6402         mutex_lock(&bp->hwrm_cmd_lock);
6403         for (i = 1; i < vnic->uc_filter_count; i++) {
6404                 struct hwrm_cfa_l2_filter_free_input req = {0};
6405
6406                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
6407                                        -1);
6408
6409                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
6410
6411                 rc = _hwrm_send_message(bp, &req, sizeof(req),
6412                                         HWRM_CMD_TIMEOUT);
6413         }
6414         mutex_unlock(&bp->hwrm_cmd_lock);
6415
6416         vnic->uc_filter_count = 1;
6417
6418         netif_addr_lock_bh(dev);
6419         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
6420                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
6421         } else {
6422                 netdev_for_each_uc_addr(ha, dev) {
6423                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
6424                         off += ETH_ALEN;
6425                         vnic->uc_filter_count++;
6426                 }
6427         }
6428         netif_addr_unlock_bh(dev);
6429
6430         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
6431                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
6432                 if (rc) {
6433                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
6434                                    rc);
6435                         vnic->uc_filter_count = i;
6436                         return rc;
6437                 }
6438         }
6439
6440 skip_uc:
6441         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
6442         if (rc)
6443                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
6444                            rc);
6445
6446         return rc;
6447 }
6448
6449 /* If the chip and firmware supports RFS */
6450 static bool bnxt_rfs_supported(struct bnxt *bp)
6451 {
6452         if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6453                 return true;
6454         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6455                 return true;
6456         return false;
6457 }
6458
6459 /* If runtime conditions support RFS */
6460 static bool bnxt_rfs_capable(struct bnxt *bp)
6461 {
6462 #ifdef CONFIG_RFS_ACCEL
6463         int vnics, max_vnics, max_rss_ctxs;
6464
6465         if (!(bp->flags & BNXT_FLAG_MSIX_CAP))
6466                 return false;
6467
6468         vnics = 1 + bp->rx_nr_rings;
6469         max_vnics = bnxt_get_max_func_vnics(bp);
6470         max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
6471
6472         /* RSS contexts not a limiting factor */
6473         if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
6474                 max_rss_ctxs = max_vnics;
6475         if (vnics > max_vnics || vnics > max_rss_ctxs) {
6476                 netdev_warn(bp->dev,
6477                             "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
6478                             min(max_rss_ctxs - 1, max_vnics - 1));
6479                 return false;
6480         }
6481
6482         return true;
6483 #else
6484         return false;
6485 #endif
6486 }
6487
6488 static netdev_features_t bnxt_fix_features(struct net_device *dev,
6489                                            netdev_features_t features)
6490 {
6491         struct bnxt *bp = netdev_priv(dev);
6492
6493         if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
6494                 features &= ~NETIF_F_NTUPLE;
6495
6496         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
6497          * turned on or off together.
6498          */
6499         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
6500             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
6501                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
6502                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6503                                       NETIF_F_HW_VLAN_STAG_RX);
6504                 else
6505                         features |= NETIF_F_HW_VLAN_CTAG_RX |
6506                                     NETIF_F_HW_VLAN_STAG_RX;
6507         }
6508 #ifdef CONFIG_BNXT_SRIOV
6509         if (BNXT_VF(bp)) {
6510                 if (bp->vf.vlan) {
6511                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
6512                                       NETIF_F_HW_VLAN_STAG_RX);
6513                 }
6514         }
6515 #endif
6516         return features;
6517 }
6518
6519 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
6520 {
6521         struct bnxt *bp = netdev_priv(dev);
6522         u32 flags = bp->flags;
6523         u32 changes;
6524         int rc = 0;
6525         bool re_init = false;
6526         bool update_tpa = false;
6527
6528         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
6529         if ((features & NETIF_F_GRO) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
6530                 flags |= BNXT_FLAG_GRO;
6531         if (features & NETIF_F_LRO)
6532                 flags |= BNXT_FLAG_LRO;
6533
6534         if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
6535                 flags &= ~BNXT_FLAG_TPA;
6536
6537         if (features & NETIF_F_HW_VLAN_CTAG_RX)
6538                 flags |= BNXT_FLAG_STRIP_VLAN;
6539
6540         if (features & NETIF_F_NTUPLE)
6541                 flags |= BNXT_FLAG_RFS;
6542
6543         changes = flags ^ bp->flags;
6544         if (changes & BNXT_FLAG_TPA) {
6545                 update_tpa = true;
6546                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
6547                     (flags & BNXT_FLAG_TPA) == 0)
6548                         re_init = true;
6549         }
6550
6551         if (changes & ~BNXT_FLAG_TPA)
6552                 re_init = true;
6553
6554         if (flags != bp->flags) {
6555                 u32 old_flags = bp->flags;
6556
6557                 bp->flags = flags;
6558
6559                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6560                         if (update_tpa)
6561                                 bnxt_set_ring_params(bp);
6562                         return rc;
6563                 }
6564
6565                 if (re_init) {
6566                         bnxt_close_nic(bp, false, false);
6567                         if (update_tpa)
6568                                 bnxt_set_ring_params(bp);
6569
6570                         return bnxt_open_nic(bp, false, false);
6571                 }
6572                 if (update_tpa) {
6573                         rc = bnxt_set_tpa(bp,
6574                                           (flags & BNXT_FLAG_TPA) ?
6575                                           true : false);
6576                         if (rc)
6577                                 bp->flags = old_flags;
6578                 }
6579         }
6580         return rc;
6581 }
6582
6583 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
6584 {
6585         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
6586         int i = bnapi->index;
6587
6588         if (!txr)
6589                 return;
6590
6591         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
6592                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
6593                     txr->tx_cons);
6594 }
6595
6596 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
6597 {
6598         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
6599         int i = bnapi->index;
6600
6601         if (!rxr)
6602                 return;
6603
6604         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
6605                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
6606                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
6607                     rxr->rx_sw_agg_prod);
6608 }
6609
6610 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
6611 {
6612         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6613         int i = bnapi->index;
6614
6615         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
6616                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
6617 }
6618
6619 static void bnxt_dbg_dump_states(struct bnxt *bp)
6620 {
6621         int i;
6622         struct bnxt_napi *bnapi;
6623
6624         for (i = 0; i < bp->cp_nr_rings; i++) {
6625                 bnapi = bp->bnapi[i];
6626                 if (netif_msg_drv(bp)) {
6627                         bnxt_dump_tx_sw_state(bnapi);
6628                         bnxt_dump_rx_sw_state(bnapi);
6629                         bnxt_dump_cp_sw_state(bnapi);
6630                 }
6631         }
6632 }
6633
6634 static void bnxt_reset_task(struct bnxt *bp, bool silent)
6635 {
6636         if (!silent)
6637                 bnxt_dbg_dump_states(bp);
6638         if (netif_running(bp->dev)) {
6639                 int rc;
6640
6641                 if (!silent)
6642                         bnxt_ulp_stop(bp);
6643                 bnxt_close_nic(bp, false, false);
6644                 rc = bnxt_open_nic(bp, false, false);
6645                 if (!silent && !rc)
6646                         bnxt_ulp_start(bp);
6647         }
6648 }
6649
6650 static void bnxt_tx_timeout(struct net_device *dev)
6651 {
6652         struct bnxt *bp = netdev_priv(dev);
6653
6654         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
6655         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
6656         schedule_work(&bp->sp_task);
6657 }
6658
6659 #ifdef CONFIG_NET_POLL_CONTROLLER
6660 static void bnxt_poll_controller(struct net_device *dev)
6661 {
6662         struct bnxt *bp = netdev_priv(dev);
6663         int i;
6664
6665         for (i = 0; i < bp->cp_nr_rings; i++) {
6666                 struct bnxt_irq *irq = &bp->irq_tbl[i];
6667
6668                 disable_irq(irq->vector);
6669                 irq->handler(irq->vector, bp->bnapi[i]);
6670                 enable_irq(irq->vector);
6671         }
6672 }
6673 #endif
6674
6675 static void bnxt_timer(unsigned long data)
6676 {
6677         struct bnxt *bp = (struct bnxt *)data;
6678         struct net_device *dev = bp->dev;
6679
6680         if (!netif_running(dev))
6681                 return;
6682
6683         if (atomic_read(&bp->intr_sem) != 0)
6684                 goto bnxt_restart_timer;
6685
6686         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
6687                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
6688                 schedule_work(&bp->sp_task);
6689         }
6690 bnxt_restart_timer:
6691         mod_timer(&bp->timer, jiffies + bp->current_interval);
6692 }
6693
6694 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
6695 {
6696         /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
6697          * set.  If the device is being closed, bnxt_close() may be holding
6698          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
6699          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
6700          */
6701         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6702         rtnl_lock();
6703 }
6704
6705 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
6706 {
6707         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6708         rtnl_unlock();
6709 }
6710
6711 /* Only called from bnxt_sp_task() */
6712 static void bnxt_reset(struct bnxt *bp, bool silent)
6713 {
6714         bnxt_rtnl_lock_sp(bp);
6715         if (test_bit(BNXT_STATE_OPEN, &bp->state))
6716                 bnxt_reset_task(bp, silent);
6717         bnxt_rtnl_unlock_sp(bp);
6718 }
6719
6720 static void bnxt_cfg_ntp_filters(struct bnxt *);
6721
6722 static void bnxt_sp_task(struct work_struct *work)
6723 {
6724         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
6725
6726         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6727         smp_mb__after_atomic();
6728         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
6729                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6730                 return;
6731         }
6732
6733         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
6734                 bnxt_cfg_rx_mode(bp);
6735
6736         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
6737                 bnxt_cfg_ntp_filters(bp);
6738         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
6739                 bnxt_hwrm_exec_fwd_req(bp);
6740         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6741                 bnxt_hwrm_tunnel_dst_port_alloc(
6742                         bp, bp->vxlan_port,
6743                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6744         }
6745         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6746                 bnxt_hwrm_tunnel_dst_port_free(
6747                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
6748         }
6749         if (test_and_clear_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event)) {
6750                 bnxt_hwrm_tunnel_dst_port_alloc(
6751                         bp, bp->nge_port,
6752                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6753         }
6754         if (test_and_clear_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event)) {
6755                 bnxt_hwrm_tunnel_dst_port_free(
6756                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
6757         }
6758         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
6759                 bnxt_hwrm_port_qstats(bp);
6760
6761         /* These functions below will clear BNXT_STATE_IN_SP_TASK.  They
6762          * must be the last functions to be called before exiting.
6763          */
6764         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
6765                 int rc = 0;
6766
6767                 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
6768                                        &bp->sp_event))
6769                         bnxt_hwrm_phy_qcaps(bp);
6770
6771                 bnxt_rtnl_lock_sp(bp);
6772                 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6773                         rc = bnxt_update_link(bp, true);
6774                 bnxt_rtnl_unlock_sp(bp);
6775                 if (rc)
6776                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
6777                                    rc);
6778         }
6779         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
6780                 bnxt_rtnl_lock_sp(bp);
6781                 if (test_bit(BNXT_STATE_OPEN, &bp->state))
6782                         bnxt_get_port_module_status(bp);
6783                 bnxt_rtnl_unlock_sp(bp);
6784         }
6785         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
6786                 bnxt_reset(bp, false);
6787
6788         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
6789                 bnxt_reset(bp, true);
6790
6791         smp_mb__before_atomic();
6792         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
6793 }
6794
6795 /* Under rtnl_lock */
6796 int bnxt_reserve_rings(struct bnxt *bp, int tx, int rx, int tcs, int tx_xdp)
6797 {
6798         int max_rx, max_tx, tx_sets = 1;
6799         int tx_rings_needed;
6800         bool sh = true;
6801         int rc;
6802
6803         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
6804                 sh = false;
6805
6806         if (tcs)
6807                 tx_sets = tcs;
6808
6809         rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
6810         if (rc)
6811                 return rc;
6812
6813         if (max_rx < rx)
6814                 return -ENOMEM;
6815
6816         tx_rings_needed = tx * tx_sets + tx_xdp;
6817         if (max_tx < tx_rings_needed)
6818                 return -ENOMEM;
6819
6820         if (bnxt_hwrm_reserve_tx_rings(bp, &tx_rings_needed) ||
6821             tx_rings_needed < (tx * tx_sets + tx_xdp))
6822                 return -ENOMEM;
6823         return 0;
6824 }
6825
6826 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
6827 {
6828         if (bp->bar2) {
6829                 pci_iounmap(pdev, bp->bar2);
6830                 bp->bar2 = NULL;
6831         }
6832
6833         if (bp->bar1) {
6834                 pci_iounmap(pdev, bp->bar1);
6835                 bp->bar1 = NULL;
6836         }
6837
6838         if (bp->bar0) {
6839                 pci_iounmap(pdev, bp->bar0);
6840                 bp->bar0 = NULL;
6841         }
6842 }
6843
6844 static void bnxt_cleanup_pci(struct bnxt *bp)
6845 {
6846         bnxt_unmap_bars(bp, bp->pdev);
6847         pci_release_regions(bp->pdev);
6848         pci_disable_device(bp->pdev);
6849 }
6850
6851 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
6852 {
6853         int rc;
6854         struct bnxt *bp = netdev_priv(dev);
6855
6856         SET_NETDEV_DEV(dev, &pdev->dev);
6857
6858         /* enable device (incl. PCI PM wakeup), and bus-mastering */
6859         rc = pci_enable_device(pdev);
6860         if (rc) {
6861                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
6862                 goto init_err;
6863         }
6864
6865         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6866                 dev_err(&pdev->dev,
6867                         "Cannot find PCI device base address, aborting\n");
6868                 rc = -ENODEV;
6869                 goto init_err_disable;
6870         }
6871
6872         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6873         if (rc) {
6874                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
6875                 goto init_err_disable;
6876         }
6877
6878         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
6879             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
6880                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
6881                 goto init_err_disable;
6882         }
6883
6884         pci_set_master(pdev);
6885
6886         bp->dev = dev;
6887         bp->pdev = pdev;
6888
6889         bp->bar0 = pci_ioremap_bar(pdev, 0);
6890         if (!bp->bar0) {
6891                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
6892                 rc = -ENOMEM;
6893                 goto init_err_release;
6894         }
6895
6896         bp->bar1 = pci_ioremap_bar(pdev, 2);
6897         if (!bp->bar1) {
6898                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
6899                 rc = -ENOMEM;
6900                 goto init_err_release;
6901         }
6902
6903         bp->bar2 = pci_ioremap_bar(pdev, 4);
6904         if (!bp->bar2) {
6905                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
6906                 rc = -ENOMEM;
6907                 goto init_err_release;
6908         }
6909
6910         pci_enable_pcie_error_reporting(pdev);
6911
6912         INIT_WORK(&bp->sp_task, bnxt_sp_task);
6913
6914         spin_lock_init(&bp->ntp_fltr_lock);
6915
6916         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
6917         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
6918
6919         /* tick values in micro seconds */
6920         bp->rx_coal_ticks = 12;
6921         bp->rx_coal_bufs = 30;
6922         bp->rx_coal_ticks_irq = 1;
6923         bp->rx_coal_bufs_irq = 2;
6924
6925         bp->tx_coal_ticks = 25;
6926         bp->tx_coal_bufs = 30;
6927         bp->tx_coal_ticks_irq = 2;
6928         bp->tx_coal_bufs_irq = 2;
6929
6930         bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
6931
6932         init_timer(&bp->timer);
6933         bp->timer.data = (unsigned long)bp;
6934         bp->timer.function = bnxt_timer;
6935         bp->current_interval = BNXT_TIMER_INTERVAL;
6936
6937         clear_bit(BNXT_STATE_OPEN, &bp->state);
6938         return 0;
6939
6940 init_err_release:
6941         bnxt_unmap_bars(bp, pdev);
6942         pci_release_regions(pdev);
6943
6944 init_err_disable:
6945         pci_disable_device(pdev);
6946
6947 init_err:
6948         return rc;
6949 }
6950
6951 /* rtnl_lock held */
6952 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
6953 {
6954         struct sockaddr *addr = p;
6955         struct bnxt *bp = netdev_priv(dev);
6956         int rc = 0;
6957
6958         if (!is_valid_ether_addr(addr->sa_data))
6959                 return -EADDRNOTAVAIL;
6960
6961         rc = bnxt_approve_mac(bp, addr->sa_data);
6962         if (rc)
6963                 return rc;
6964
6965         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
6966                 return 0;
6967
6968         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6969         if (netif_running(dev)) {
6970                 bnxt_close_nic(bp, false, false);
6971                 rc = bnxt_open_nic(bp, false, false);
6972         }
6973
6974         return rc;
6975 }
6976
6977 /* rtnl_lock held */
6978 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
6979 {
6980         struct bnxt *bp = netdev_priv(dev);
6981
6982         if (netif_running(dev))
6983                 bnxt_close_nic(bp, false, false);
6984
6985         dev->mtu = new_mtu;
6986         bnxt_set_ring_params(bp);
6987
6988         if (netif_running(dev))
6989                 return bnxt_open_nic(bp, false, false);
6990
6991         return 0;
6992 }
6993
6994 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
6995 {
6996         struct bnxt *bp = netdev_priv(dev);
6997         bool sh = false;
6998         int rc;
6999
7000         if (tc > bp->max_tc) {
7001                 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
7002                            tc, bp->max_tc);
7003                 return -EINVAL;
7004         }
7005
7006         if (netdev_get_num_tc(dev) == tc)
7007                 return 0;
7008
7009         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
7010                 sh = true;
7011
7012         rc = bnxt_reserve_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
7013                                 tc, bp->tx_nr_rings_xdp);
7014         if (rc)
7015                 return rc;
7016
7017         /* Needs to close the device and do hw resource re-allocations */
7018         if (netif_running(bp->dev))
7019                 bnxt_close_nic(bp, true, false);
7020
7021         if (tc) {
7022                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
7023                 netdev_set_num_tc(dev, tc);
7024         } else {
7025                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7026                 netdev_reset_tc(dev);
7027         }
7028         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7029                                bp->tx_nr_rings + bp->rx_nr_rings;
7030         bp->num_stat_ctxs = bp->cp_nr_rings;
7031
7032         if (netif_running(bp->dev))
7033                 return bnxt_open_nic(bp, true, false);
7034
7035         return 0;
7036 }
7037
7038 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
7039                          struct tc_to_netdev *ntc)
7040 {
7041         if (ntc->type != TC_SETUP_MQPRIO)
7042                 return -EINVAL;
7043
7044         ntc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
7045
7046         return bnxt_setup_mq_tc(dev, ntc->mqprio->num_tc);
7047 }
7048
7049 #ifdef CONFIG_RFS_ACCEL
7050 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
7051                             struct bnxt_ntuple_filter *f2)
7052 {
7053         struct flow_keys *keys1 = &f1->fkeys;
7054         struct flow_keys *keys2 = &f2->fkeys;
7055
7056         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
7057             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
7058             keys1->ports.ports == keys2->ports.ports &&
7059             keys1->basic.ip_proto == keys2->basic.ip_proto &&
7060             keys1->basic.n_proto == keys2->basic.n_proto &&
7061             keys1->control.flags == keys2->control.flags &&
7062             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
7063             ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
7064                 return true;
7065
7066         return false;
7067 }
7068
7069 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
7070                               u16 rxq_index, u32 flow_id)
7071 {
7072         struct bnxt *bp = netdev_priv(dev);
7073         struct bnxt_ntuple_filter *fltr, *new_fltr;
7074         struct flow_keys *fkeys;
7075         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
7076         int rc = 0, idx, bit_id, l2_idx = 0;
7077         struct hlist_head *head;
7078
7079         if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
7080                 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
7081                 int off = 0, j;
7082
7083                 netif_addr_lock_bh(dev);
7084                 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
7085                         if (ether_addr_equal(eth->h_dest,
7086                                              vnic->uc_list + off)) {
7087                                 l2_idx = j + 1;
7088                                 break;
7089                         }
7090                 }
7091                 netif_addr_unlock_bh(dev);
7092                 if (!l2_idx)
7093                         return -EINVAL;
7094         }
7095         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
7096         if (!new_fltr)
7097                 return -ENOMEM;
7098
7099         fkeys = &new_fltr->fkeys;
7100         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
7101                 rc = -EPROTONOSUPPORT;
7102                 goto err_free;
7103         }
7104
7105         if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
7106              fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
7107             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
7108              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
7109                 rc = -EPROTONOSUPPORT;
7110                 goto err_free;
7111         }
7112         if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
7113             bp->hwrm_spec_code < 0x10601) {
7114                 rc = -EPROTONOSUPPORT;
7115                 goto err_free;
7116         }
7117         if ((fkeys->control.flags & FLOW_DIS_ENCAPSULATION) &&
7118             bp->hwrm_spec_code < 0x10601) {
7119                 rc = -EPROTONOSUPPORT;
7120                 goto err_free;
7121         }
7122
7123         memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
7124         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
7125
7126         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
7127         head = &bp->ntp_fltr_hash_tbl[idx];
7128         rcu_read_lock();
7129         hlist_for_each_entry_rcu(fltr, head, hash) {
7130                 if (bnxt_fltr_match(fltr, new_fltr)) {
7131                         rcu_read_unlock();
7132                         rc = 0;
7133                         goto err_free;
7134                 }
7135         }
7136         rcu_read_unlock();
7137
7138         spin_lock_bh(&bp->ntp_fltr_lock);
7139         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
7140                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
7141         if (bit_id < 0) {
7142                 spin_unlock_bh(&bp->ntp_fltr_lock);
7143                 rc = -ENOMEM;
7144                 goto err_free;
7145         }
7146
7147         new_fltr->sw_id = (u16)bit_id;
7148         new_fltr->flow_id = flow_id;
7149         new_fltr->l2_fltr_idx = l2_idx;
7150         new_fltr->rxq = rxq_index;
7151         hlist_add_head_rcu(&new_fltr->hash, head);
7152         bp->ntp_fltr_count++;
7153         spin_unlock_bh(&bp->ntp_fltr_lock);
7154
7155         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
7156         schedule_work(&bp->sp_task);
7157
7158         return new_fltr->sw_id;
7159
7160 err_free:
7161         kfree(new_fltr);
7162         return rc;
7163 }
7164
7165 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7166 {
7167         int i;
7168
7169         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
7170                 struct hlist_head *head;
7171                 struct hlist_node *tmp;
7172                 struct bnxt_ntuple_filter *fltr;
7173                 int rc;
7174
7175                 head = &bp->ntp_fltr_hash_tbl[i];
7176                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
7177                         bool del = false;
7178
7179                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
7180                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
7181                                                         fltr->flow_id,
7182                                                         fltr->sw_id)) {
7183                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
7184                                                                          fltr);
7185                                         del = true;
7186                                 }
7187                         } else {
7188                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
7189                                                                        fltr);
7190                                 if (rc)
7191                                         del = true;
7192                                 else
7193                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
7194                         }
7195
7196                         if (del) {
7197                                 spin_lock_bh(&bp->ntp_fltr_lock);
7198                                 hlist_del_rcu(&fltr->hash);
7199                                 bp->ntp_fltr_count--;
7200                                 spin_unlock_bh(&bp->ntp_fltr_lock);
7201                                 synchronize_rcu();
7202                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
7203                                 kfree(fltr);
7204                         }
7205                 }
7206         }
7207         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
7208                 netdev_info(bp->dev, "Receive PF driver unload event!");
7209 }
7210
7211 #else
7212
7213 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
7214 {
7215 }
7216
7217 #endif /* CONFIG_RFS_ACCEL */
7218
7219 static void bnxt_udp_tunnel_add(struct net_device *dev,
7220                                 struct udp_tunnel_info *ti)
7221 {
7222         struct bnxt *bp = netdev_priv(dev);
7223
7224         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7225                 return;
7226
7227         if (!netif_running(dev))
7228                 return;
7229
7230         switch (ti->type) {
7231         case UDP_TUNNEL_TYPE_VXLAN:
7232                 if (bp->vxlan_port_cnt && bp->vxlan_port != ti->port)
7233                         return;
7234
7235                 bp->vxlan_port_cnt++;
7236                 if (bp->vxlan_port_cnt == 1) {
7237                         bp->vxlan_port = ti->port;
7238                         set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
7239                         schedule_work(&bp->sp_task);
7240                 }
7241                 break;
7242         case UDP_TUNNEL_TYPE_GENEVE:
7243                 if (bp->nge_port_cnt && bp->nge_port != ti->port)
7244                         return;
7245
7246                 bp->nge_port_cnt++;
7247                 if (bp->nge_port_cnt == 1) {
7248                         bp->nge_port = ti->port;
7249                         set_bit(BNXT_GENEVE_ADD_PORT_SP_EVENT, &bp->sp_event);
7250                 }
7251                 break;
7252         default:
7253                 return;
7254         }
7255
7256         schedule_work(&bp->sp_task);
7257 }
7258
7259 static void bnxt_udp_tunnel_del(struct net_device *dev,
7260                                 struct udp_tunnel_info *ti)
7261 {
7262         struct bnxt *bp = netdev_priv(dev);
7263
7264         if (ti->sa_family != AF_INET6 && ti->sa_family != AF_INET)
7265                 return;
7266
7267         if (!netif_running(dev))
7268                 return;
7269
7270         switch (ti->type) {
7271         case UDP_TUNNEL_TYPE_VXLAN:
7272                 if (!bp->vxlan_port_cnt || bp->vxlan_port != ti->port)
7273                         return;
7274                 bp->vxlan_port_cnt--;
7275
7276                 if (bp->vxlan_port_cnt != 0)
7277                         return;
7278
7279                 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
7280                 break;
7281         case UDP_TUNNEL_TYPE_GENEVE:
7282                 if (!bp->nge_port_cnt || bp->nge_port != ti->port)
7283                         return;
7284                 bp->nge_port_cnt--;
7285
7286                 if (bp->nge_port_cnt != 0)
7287                         return;
7288
7289                 set_bit(BNXT_GENEVE_DEL_PORT_SP_EVENT, &bp->sp_event);
7290                 break;
7291         default:
7292                 return;
7293         }
7294
7295         schedule_work(&bp->sp_task);
7296 }
7297
7298 static const struct net_device_ops bnxt_netdev_ops = {
7299         .ndo_open               = bnxt_open,
7300         .ndo_start_xmit         = bnxt_start_xmit,
7301         .ndo_stop               = bnxt_close,
7302         .ndo_get_stats64        = bnxt_get_stats64,
7303         .ndo_set_rx_mode        = bnxt_set_rx_mode,
7304         .ndo_do_ioctl           = bnxt_ioctl,
7305         .ndo_validate_addr      = eth_validate_addr,
7306         .ndo_set_mac_address    = bnxt_change_mac_addr,
7307         .ndo_change_mtu         = bnxt_change_mtu,
7308         .ndo_fix_features       = bnxt_fix_features,
7309         .ndo_set_features       = bnxt_set_features,
7310         .ndo_tx_timeout         = bnxt_tx_timeout,
7311 #ifdef CONFIG_BNXT_SRIOV
7312         .ndo_get_vf_config      = bnxt_get_vf_config,
7313         .ndo_set_vf_mac         = bnxt_set_vf_mac,
7314         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
7315         .ndo_set_vf_rate        = bnxt_set_vf_bw,
7316         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
7317         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
7318 #endif
7319 #ifdef CONFIG_NET_POLL_CONTROLLER
7320         .ndo_poll_controller    = bnxt_poll_controller,
7321 #endif
7322         .ndo_setup_tc           = bnxt_setup_tc,
7323 #ifdef CONFIG_RFS_ACCEL
7324         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
7325 #endif
7326         .ndo_udp_tunnel_add     = bnxt_udp_tunnel_add,
7327         .ndo_udp_tunnel_del     = bnxt_udp_tunnel_del,
7328         .ndo_xdp                = bnxt_xdp,
7329 };
7330
7331 static void bnxt_remove_one(struct pci_dev *pdev)
7332 {
7333         struct net_device *dev = pci_get_drvdata(pdev);
7334         struct bnxt *bp = netdev_priv(dev);
7335
7336         if (BNXT_PF(bp))
7337                 bnxt_sriov_disable(bp);
7338
7339         pci_disable_pcie_error_reporting(pdev);
7340         unregister_netdev(dev);
7341         cancel_work_sync(&bp->sp_task);
7342         bp->sp_event = 0;
7343
7344         bnxt_clear_int_mode(bp);
7345         bnxt_hwrm_func_drv_unrgtr(bp);
7346         bnxt_free_hwrm_resources(bp);
7347         bnxt_ethtool_free(bp);
7348         bnxt_dcb_free(bp);
7349         kfree(bp->edev);
7350         bp->edev = NULL;
7351         if (bp->xdp_prog)
7352                 bpf_prog_put(bp->xdp_prog);
7353         bnxt_cleanup_pci(bp);
7354         free_netdev(dev);
7355 }
7356
7357 static int bnxt_probe_phy(struct bnxt *bp)
7358 {
7359         int rc = 0;
7360         struct bnxt_link_info *link_info = &bp->link_info;
7361
7362         rc = bnxt_hwrm_phy_qcaps(bp);
7363         if (rc) {
7364                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
7365                            rc);
7366                 return rc;
7367         }
7368
7369         rc = bnxt_update_link(bp, false);
7370         if (rc) {
7371                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
7372                            rc);
7373                 return rc;
7374         }
7375
7376         /* Older firmware does not have supported_auto_speeds, so assume
7377          * that all supported speeds can be autonegotiated.
7378          */
7379         if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
7380                 link_info->support_auto_speeds = link_info->support_speeds;
7381
7382         /*initialize the ethool setting copy with NVM settings */
7383         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
7384                 link_info->autoneg = BNXT_AUTONEG_SPEED;
7385                 if (bp->hwrm_spec_code >= 0x10201) {
7386                         if (link_info->auto_pause_setting &
7387                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
7388                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7389                 } else {
7390                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
7391                 }
7392                 link_info->advertising = link_info->auto_link_speeds;
7393         } else {
7394                 link_info->req_link_speed = link_info->force_link_speed;
7395                 link_info->req_duplex = link_info->duplex_setting;
7396         }
7397         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
7398                 link_info->req_flow_ctrl =
7399                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
7400         else
7401                 link_info->req_flow_ctrl = link_info->force_pause_setting;
7402         return rc;
7403 }
7404
7405 static int bnxt_get_max_irq(struct pci_dev *pdev)
7406 {
7407         u16 ctrl;
7408
7409         if (!pdev->msix_cap)
7410                 return 1;
7411
7412         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
7413         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
7414 }
7415
7416 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7417                                 int *max_cp)
7418 {
7419         int max_ring_grps = 0;
7420
7421 #ifdef CONFIG_BNXT_SRIOV
7422         if (!BNXT_PF(bp)) {
7423                 *max_tx = bp->vf.max_tx_rings;
7424                 *max_rx = bp->vf.max_rx_rings;
7425                 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
7426                 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
7427                 max_ring_grps = bp->vf.max_hw_ring_grps;
7428         } else
7429 #endif
7430         {
7431                 *max_tx = bp->pf.max_tx_rings;
7432                 *max_rx = bp->pf.max_rx_rings;
7433                 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
7434                 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
7435                 max_ring_grps = bp->pf.max_hw_ring_grps;
7436         }
7437         if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
7438                 *max_cp -= 1;
7439                 *max_rx -= 2;
7440         }
7441         if (bp->flags & BNXT_FLAG_AGG_RINGS)
7442                 *max_rx >>= 1;
7443         *max_rx = min_t(int, *max_rx, max_ring_grps);
7444 }
7445
7446 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
7447 {
7448         int rx, tx, cp;
7449
7450         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
7451         if (!rx || !tx || !cp)
7452                 return -ENOMEM;
7453
7454         *max_rx = rx;
7455         *max_tx = tx;
7456         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
7457 }
7458
7459 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
7460                                bool shared)
7461 {
7462         int rc;
7463
7464         rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7465         if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
7466                 /* Not enough rings, try disabling agg rings. */
7467                 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
7468                 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
7469                 if (rc)
7470                         return rc;
7471                 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
7472                 bp->dev->hw_features &= ~NETIF_F_LRO;
7473                 bp->dev->features &= ~NETIF_F_LRO;
7474                 bnxt_set_ring_params(bp);
7475         }
7476
7477         if (bp->flags & BNXT_FLAG_ROCE_CAP) {
7478                 int max_cp, max_stat, max_irq;
7479
7480                 /* Reserve minimum resources for RoCE */
7481                 max_cp = bnxt_get_max_func_cp_rings(bp);
7482                 max_stat = bnxt_get_max_func_stat_ctxs(bp);
7483                 max_irq = bnxt_get_max_func_irqs(bp);
7484                 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
7485                     max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
7486                     max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
7487                         return 0;
7488
7489                 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
7490                 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
7491                 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
7492                 max_cp = min_t(int, max_cp, max_irq);
7493                 max_cp = min_t(int, max_cp, max_stat);
7494                 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
7495                 if (rc)
7496                         rc = 0;
7497         }
7498         return rc;
7499 }
7500
7501 static int bnxt_set_dflt_rings(struct bnxt *bp)
7502 {
7503         int dflt_rings, max_rx_rings, max_tx_rings, rc;
7504         bool sh = true;
7505
7506         if (sh)
7507                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
7508         dflt_rings = netif_get_num_default_rss_queues();
7509         rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
7510         if (rc)
7511                 return rc;
7512         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
7513         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
7514
7515         rc = bnxt_hwrm_reserve_tx_rings(bp, &bp->tx_nr_rings_per_tc);
7516         if (rc)
7517                 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
7518
7519         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
7520         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
7521                                bp->tx_nr_rings + bp->rx_nr_rings;
7522         bp->num_stat_ctxs = bp->cp_nr_rings;
7523         if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
7524                 bp->rx_nr_rings++;
7525                 bp->cp_nr_rings++;
7526         }
7527         return rc;
7528 }
7529
7530 void bnxt_restore_pf_fw_resources(struct bnxt *bp)
7531 {
7532         ASSERT_RTNL();
7533         bnxt_hwrm_func_qcaps(bp);
7534         bnxt_subtract_ulp_resources(bp, BNXT_ROCE_ULP);
7535 }
7536
7537 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
7538 {
7539         enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
7540         enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
7541
7542         if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
7543             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
7544                 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
7545         else
7546                 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
7547                             speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
7548                             speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
7549                             speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
7550                             "Unknown", width);
7551 }
7552
7553 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7554 {
7555         static int version_printed;
7556         struct net_device *dev;
7557         struct bnxt *bp;
7558         int rc, max_irqs;
7559
7560         if (pci_is_bridge(pdev))
7561                 return -ENODEV;
7562
7563         if (version_printed++ == 0)
7564                 pr_info("%s", version);
7565
7566         max_irqs = bnxt_get_max_irq(pdev);
7567         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
7568         if (!dev)
7569                 return -ENOMEM;
7570
7571         bp = netdev_priv(dev);
7572
7573         if (bnxt_vf_pciid(ent->driver_data))
7574                 bp->flags |= BNXT_FLAG_VF;
7575
7576         if (pdev->msix_cap)
7577                 bp->flags |= BNXT_FLAG_MSIX_CAP;
7578
7579         rc = bnxt_init_board(pdev, dev);
7580         if (rc < 0)
7581                 goto init_err_free;
7582
7583         dev->netdev_ops = &bnxt_netdev_ops;
7584         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
7585         dev->ethtool_ops = &bnxt_ethtool_ops;
7586         pci_set_drvdata(pdev, dev);
7587
7588         rc = bnxt_alloc_hwrm_resources(bp);
7589         if (rc)
7590                 goto init_err_pci_clean;
7591
7592         mutex_init(&bp->hwrm_cmd_lock);
7593         rc = bnxt_hwrm_ver_get(bp);
7594         if (rc)
7595                 goto init_err_pci_clean;
7596
7597         rc = bnxt_hwrm_func_reset(bp);
7598         if (rc)
7599                 goto init_err_pci_clean;
7600
7601         bnxt_hwrm_fw_set_time(bp);
7602
7603         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7604                            NETIF_F_TSO | NETIF_F_TSO6 |
7605                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7606                            NETIF_F_GSO_IPXIP4 |
7607                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7608                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
7609                            NETIF_F_RXCSUM | NETIF_F_GRO;
7610
7611         if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
7612                 dev->hw_features |= NETIF_F_LRO;
7613
7614         dev->hw_enc_features =
7615                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
7616                         NETIF_F_TSO | NETIF_F_TSO6 |
7617                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
7618                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
7619                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
7620         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
7621                                     NETIF_F_GSO_GRE_CSUM;
7622         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
7623         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7624                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
7625         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
7626         dev->priv_flags |= IFF_UNICAST_FLT;
7627
7628         /* MTU range: 60 - 9500 */
7629         dev->min_mtu = ETH_ZLEN;
7630         dev->max_mtu = BNXT_MAX_MTU;
7631
7632         bnxt_dcb_init(bp);
7633
7634 #ifdef CONFIG_BNXT_SRIOV
7635         init_waitqueue_head(&bp->sriov_cfg_wait);
7636 #endif
7637         bp->gro_func = bnxt_gro_func_5730x;
7638         if (BNXT_CHIP_NUM_57X1X(bp->chip_num))
7639                 bp->gro_func = bnxt_gro_func_5731x;
7640
7641         rc = bnxt_hwrm_func_drv_rgtr(bp);
7642         if (rc)
7643                 goto init_err_pci_clean;
7644
7645         rc = bnxt_hwrm_func_rgtr_async_events(bp, NULL, 0);
7646         if (rc)
7647                 goto init_err_pci_clean;
7648
7649         bp->ulp_probe = bnxt_ulp_probe;
7650
7651         /* Get the MAX capabilities for this function */
7652         rc = bnxt_hwrm_func_qcaps(bp);
7653         if (rc) {
7654                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
7655                            rc);
7656                 rc = -1;
7657                 goto init_err_pci_clean;
7658         }
7659
7660         rc = bnxt_hwrm_queue_qportcfg(bp);
7661         if (rc) {
7662                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
7663                            rc);
7664                 rc = -1;
7665                 goto init_err_pci_clean;
7666         }
7667
7668         bnxt_hwrm_func_qcfg(bp);
7669         bnxt_hwrm_port_led_qcaps(bp);
7670         bnxt_ethtool_init(bp);
7671
7672         bnxt_set_rx_skb_mode(bp, false);
7673         bnxt_set_tpa_flags(bp);
7674         bnxt_set_ring_params(bp);
7675         bnxt_set_max_func_irqs(bp, max_irqs);
7676         rc = bnxt_set_dflt_rings(bp);
7677         if (rc) {
7678                 netdev_err(bp->dev, "Not enough rings available.\n");
7679                 rc = -ENOMEM;
7680                 goto init_err_pci_clean;
7681         }
7682
7683         /* Default RSS hash cfg. */
7684         bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
7685                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
7686                            VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
7687                            VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
7688         if (!BNXT_CHIP_NUM_57X0X(bp->chip_num) &&
7689             !BNXT_CHIP_TYPE_NITRO_A0(bp) &&
7690             bp->hwrm_spec_code >= 0x10501) {
7691                 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
7692                 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
7693                                     VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
7694         }
7695
7696         bnxt_hwrm_vnic_qcaps(bp);
7697         if (bnxt_rfs_supported(bp)) {
7698                 dev->hw_features |= NETIF_F_NTUPLE;
7699                 if (bnxt_rfs_capable(bp)) {
7700                         bp->flags |= BNXT_FLAG_RFS;
7701                         dev->features |= NETIF_F_NTUPLE;
7702                 }
7703         }
7704
7705         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
7706                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
7707
7708         rc = bnxt_probe_phy(bp);
7709         if (rc)
7710                 goto init_err_pci_clean;
7711
7712         rc = bnxt_init_int_mode(bp);
7713         if (rc)
7714                 goto init_err_pci_clean;
7715
7716         bnxt_get_wol_settings(bp);
7717         if (bp->flags & BNXT_FLAG_WOL_CAP)
7718                 device_set_wakeup_enable(&pdev->dev, bp->wol);
7719         else
7720                 device_set_wakeup_capable(&pdev->dev, false);
7721
7722         rc = register_netdev(dev);
7723         if (rc)
7724                 goto init_err_clr_int;
7725
7726         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
7727                     board_info[ent->driver_data].name,
7728                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
7729
7730         bnxt_parse_log_pcie_link(bp);
7731
7732         return 0;
7733
7734 init_err_clr_int:
7735         bnxt_clear_int_mode(bp);
7736
7737 init_err_pci_clean:
7738         bnxt_cleanup_pci(bp);
7739
7740 init_err_free:
7741         free_netdev(dev);
7742         return rc;
7743 }
7744
7745 static void bnxt_shutdown(struct pci_dev *pdev)
7746 {
7747         struct net_device *dev = pci_get_drvdata(pdev);
7748         struct bnxt *bp;
7749
7750         if (!dev)
7751                 return;
7752
7753         rtnl_lock();
7754         bp = netdev_priv(dev);
7755         if (!bp)
7756                 goto shutdown_exit;
7757
7758         if (netif_running(dev))
7759                 dev_close(dev);
7760
7761         if (system_state == SYSTEM_POWER_OFF) {
7762                 bnxt_clear_int_mode(bp);
7763                 pci_wake_from_d3(pdev, bp->wol);
7764                 pci_set_power_state(pdev, PCI_D3hot);
7765         }
7766
7767 shutdown_exit:
7768         rtnl_unlock();
7769 }
7770
7771 #ifdef CONFIG_PM_SLEEP
7772 static int bnxt_suspend(struct device *device)
7773 {
7774         struct pci_dev *pdev = to_pci_dev(device);
7775         struct net_device *dev = pci_get_drvdata(pdev);
7776         struct bnxt *bp = netdev_priv(dev);
7777         int rc = 0;
7778
7779         rtnl_lock();
7780         if (netif_running(dev)) {
7781                 netif_device_detach(dev);
7782                 rc = bnxt_close(dev);
7783         }
7784         bnxt_hwrm_func_drv_unrgtr(bp);
7785         rtnl_unlock();
7786         return rc;
7787 }
7788
7789 static int bnxt_resume(struct device *device)
7790 {
7791         struct pci_dev *pdev = to_pci_dev(device);
7792         struct net_device *dev = pci_get_drvdata(pdev);
7793         struct bnxt *bp = netdev_priv(dev);
7794         int rc = 0;
7795
7796         rtnl_lock();
7797         if (bnxt_hwrm_ver_get(bp) || bnxt_hwrm_func_drv_rgtr(bp)) {
7798                 rc = -ENODEV;
7799                 goto resume_exit;
7800         }
7801         rc = bnxt_hwrm_func_reset(bp);
7802         if (rc) {
7803                 rc = -EBUSY;
7804                 goto resume_exit;
7805         }
7806         bnxt_get_wol_settings(bp);
7807         if (netif_running(dev)) {
7808                 rc = bnxt_open(dev);
7809                 if (!rc)
7810                         netif_device_attach(dev);
7811         }
7812
7813 resume_exit:
7814         rtnl_unlock();
7815         return rc;
7816 }
7817
7818 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
7819 #define BNXT_PM_OPS (&bnxt_pm_ops)
7820
7821 #else
7822
7823 #define BNXT_PM_OPS NULL
7824
7825 #endif /* CONFIG_PM_SLEEP */
7826
7827 /**
7828  * bnxt_io_error_detected - called when PCI error is detected
7829  * @pdev: Pointer to PCI device
7830  * @state: The current pci connection state
7831  *
7832  * This function is called after a PCI bus error affecting
7833  * this device has been detected.
7834  */
7835 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
7836                                                pci_channel_state_t state)
7837 {
7838         struct net_device *netdev = pci_get_drvdata(pdev);
7839         struct bnxt *bp = netdev_priv(netdev);
7840
7841         netdev_info(netdev, "PCI I/O error detected\n");
7842
7843         rtnl_lock();
7844         netif_device_detach(netdev);
7845
7846         bnxt_ulp_stop(bp);
7847
7848         if (state == pci_channel_io_perm_failure) {
7849                 rtnl_unlock();
7850                 return PCI_ERS_RESULT_DISCONNECT;
7851         }
7852
7853         if (netif_running(netdev))
7854                 bnxt_close(netdev);
7855
7856         pci_disable_device(pdev);
7857         rtnl_unlock();
7858
7859         /* Request a slot slot reset. */
7860         return PCI_ERS_RESULT_NEED_RESET;
7861 }
7862
7863 /**
7864  * bnxt_io_slot_reset - called after the pci bus has been reset.
7865  * @pdev: Pointer to PCI device
7866  *
7867  * Restart the card from scratch, as if from a cold-boot.
7868  * At this point, the card has exprienced a hard reset,
7869  * followed by fixups by BIOS, and has its config space
7870  * set up identically to what it was at cold boot.
7871  */
7872 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
7873 {
7874         struct net_device *netdev = pci_get_drvdata(pdev);
7875         struct bnxt *bp = netdev_priv(netdev);
7876         int err = 0;
7877         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
7878
7879         netdev_info(bp->dev, "PCI Slot Reset\n");
7880
7881         rtnl_lock();
7882
7883         if (pci_enable_device(pdev)) {
7884                 dev_err(&pdev->dev,
7885                         "Cannot re-enable PCI device after reset.\n");
7886         } else {
7887                 pci_set_master(pdev);
7888
7889                 err = bnxt_hwrm_func_reset(bp);
7890                 if (!err && netif_running(netdev))
7891                         err = bnxt_open(netdev);
7892
7893                 if (!err) {
7894                         result = PCI_ERS_RESULT_RECOVERED;
7895                         bnxt_ulp_start(bp);
7896                 }
7897         }
7898
7899         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
7900                 dev_close(netdev);
7901
7902         rtnl_unlock();
7903
7904         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7905         if (err) {
7906                 dev_err(&pdev->dev,
7907                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
7908                          err); /* non-fatal, continue */
7909         }
7910
7911         return PCI_ERS_RESULT_RECOVERED;
7912 }
7913
7914 /**
7915  * bnxt_io_resume - called when traffic can start flowing again.
7916  * @pdev: Pointer to PCI device
7917  *
7918  * This callback is called when the error recovery driver tells
7919  * us that its OK to resume normal operation.
7920  */
7921 static void bnxt_io_resume(struct pci_dev *pdev)
7922 {
7923         struct net_device *netdev = pci_get_drvdata(pdev);
7924
7925         rtnl_lock();
7926
7927         netif_device_attach(netdev);
7928
7929         rtnl_unlock();
7930 }
7931
7932 static const struct pci_error_handlers bnxt_err_handler = {
7933         .error_detected = bnxt_io_error_detected,
7934         .slot_reset     = bnxt_io_slot_reset,
7935         .resume         = bnxt_io_resume
7936 };
7937
7938 static struct pci_driver bnxt_pci_driver = {
7939         .name           = DRV_MODULE_NAME,
7940         .id_table       = bnxt_pci_tbl,
7941         .probe          = bnxt_init_one,
7942         .remove         = bnxt_remove_one,
7943         .shutdown       = bnxt_shutdown,
7944         .driver.pm      = BNXT_PM_OPS,
7945         .err_handler    = &bnxt_err_handler,
7946 #if defined(CONFIG_BNXT_SRIOV)
7947         .sriov_configure = bnxt_sriov_configure,
7948 #endif
7949 };
7950
7951 module_pci_driver(bnxt_pci_driver);