2 * Faraday FTGMAC100 Gigabit Ethernet
4 * (C) Copyright 2009-2011 Faraday Technology
5 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
32 #include <linux/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/property.h>
38 #include "ftgmac100.h"
40 #define DRV_NAME "ftgmac100"
41 #define DRV_VERSION "0.7"
43 #define RX_QUEUE_ENTRIES 256 /* must be power of 2 */
44 #define TX_QUEUE_ENTRIES 512 /* must be power of 2 */
46 #define MAX_PKT_SIZE 1518
47 #define RX_BUF_SIZE PAGE_SIZE /* must be smaller than 0x3fff */
49 struct ftgmac100_descs {
50 struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
51 struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES];
59 struct ftgmac100_descs *descs;
60 dma_addr_t descs_dma_addr;
63 struct page *rx_pages[RX_QUEUE_ENTRIES];
64 unsigned int rx_pointer;
65 u32 rxdes0_edorr_mask;
68 unsigned int tx_clean_pointer;
69 unsigned int tx_pointer;
70 unsigned int tx_pending;
71 u32 txdes0_edotr_mask;
74 /* Component structures */
75 struct net_device *netdev;
77 struct ncsi_dev *ndev;
78 struct napi_struct napi;
79 struct work_struct reset_task;
80 struct mii_bus *mii_bus;
88 bool need_mac_restart;
91 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
92 struct ftgmac100_rxdes *rxdes, gfp_t gfp);
94 static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr)
96 iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR);
99 static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv,
102 size = FTGMAC100_RBSR_SIZE(size);
103 iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR);
106 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv,
109 iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
112 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv)
114 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
117 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
119 struct net_device *netdev = priv->netdev;
122 /* NOTE: reset clears all registers */
123 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
124 iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
125 priv->base + FTGMAC100_OFFSET_MACCR);
126 for (i = 0; i < 50; i++) {
129 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
130 if (!(maccr & FTGMAC100_MACCR_SW_RST))
136 netdev_err(netdev, "Hardware reset failed\n");
140 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
144 switch (priv->cur_speed) {
146 case 0: /* no link */
150 maccr |= FTGMAC100_MACCR_FAST_MODE;
154 maccr |= FTGMAC100_MACCR_GIGA_MODE;
157 netdev_err(priv->netdev, "Unknown speed %d !\n",
162 /* (Re)initialize the queue pointers */
163 priv->rx_pointer = 0;
164 priv->tx_clean_pointer = 0;
165 priv->tx_pointer = 0;
166 priv->tx_pending = 0;
168 /* The doc says reset twice with 10us interval */
169 if (ftgmac100_reset_mac(priv, maccr))
171 usleep_range(10, 1000);
172 return ftgmac100_reset_mac(priv, maccr);
175 static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac)
177 unsigned int maddr = mac[0] << 8 | mac[1];
178 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
180 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
181 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
184 static void ftgmac100_setup_mac(struct ftgmac100 *priv)
191 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN);
193 ether_addr_copy(priv->netdev->dev_addr, mac);
194 dev_info(priv->dev, "Read MAC address %pM from device tree\n",
199 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
200 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
202 mac[0] = (m >> 8) & 0xff;
204 mac[2] = (l >> 24) & 0xff;
205 mac[3] = (l >> 16) & 0xff;
206 mac[4] = (l >> 8) & 0xff;
209 if (is_valid_ether_addr(mac)) {
210 ether_addr_copy(priv->netdev->dev_addr, mac);
211 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
213 eth_hw_addr_random(priv->netdev);
214 dev_info(priv->dev, "Generated random MAC address %pM\n",
215 priv->netdev->dev_addr);
219 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
223 ret = eth_prepare_mac_addr_change(dev, p);
227 eth_commit_mac_addr_change(dev, p);
228 ftgmac100_set_mac(netdev_priv(dev), dev->dev_addr);
233 static void ftgmac100_init_hw(struct ftgmac100 *priv)
235 /* setup ring buffer base registers */
236 ftgmac100_set_rx_ring_base(priv,
237 priv->descs_dma_addr +
238 offsetof(struct ftgmac100_descs, rxdes));
239 ftgmac100_set_normal_prio_tx_ring_base(priv,
240 priv->descs_dma_addr +
241 offsetof(struct ftgmac100_descs, txdes));
243 ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE);
245 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC);
247 ftgmac100_set_mac(priv, priv->netdev->dev_addr);
250 static void ftgmac100_start_hw(struct ftgmac100 *priv)
252 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
254 /* Keep the original GMAC and FAST bits */
255 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
257 /* Add all the main enable bits */
258 maccr |= FTGMAC100_MACCR_TXDMA_EN |
259 FTGMAC100_MACCR_RXDMA_EN |
260 FTGMAC100_MACCR_TXMAC_EN |
261 FTGMAC100_MACCR_RXMAC_EN |
262 FTGMAC100_MACCR_CRC_APD |
263 FTGMAC100_MACCR_PHY_LINK_LEVEL |
264 FTGMAC100_MACCR_RX_RUNT |
265 FTGMAC100_MACCR_RX_BROADPKT;
267 /* Add other bits as needed */
268 if (priv->cur_duplex == DUPLEX_FULL)
269 maccr |= FTGMAC100_MACCR_FULLDUP;
272 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
275 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
277 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
280 static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes)
282 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS);
285 static bool ftgmac100_rxdes_last_segment(struct ftgmac100_rxdes *rxdes)
287 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_LRS);
290 static bool ftgmac100_rxdes_packet_ready(struct ftgmac100_rxdes *rxdes)
292 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY);
295 static void ftgmac100_rxdes_set_dma_own(const struct ftgmac100 *priv,
296 struct ftgmac100_rxdes *rxdes)
298 /* clear status bits */
299 rxdes->rxdes0 &= cpu_to_le32(priv->rxdes0_edorr_mask);
302 static bool ftgmac100_rxdes_rx_error(struct ftgmac100_rxdes *rxdes)
304 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ERR);
307 static bool ftgmac100_rxdes_crc_error(struct ftgmac100_rxdes *rxdes)
309 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_CRC_ERR);
312 static bool ftgmac100_rxdes_frame_too_long(struct ftgmac100_rxdes *rxdes)
314 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FTL);
317 static bool ftgmac100_rxdes_runt(struct ftgmac100_rxdes *rxdes)
319 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RUNT);
322 static bool ftgmac100_rxdes_odd_nibble(struct ftgmac100_rxdes *rxdes)
324 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ODD_NB);
327 static unsigned int ftgmac100_rxdes_data_length(struct ftgmac100_rxdes *rxdes)
329 return le32_to_cpu(rxdes->rxdes0) & FTGMAC100_RXDES0_VDBC;
332 static bool ftgmac100_rxdes_multicast(struct ftgmac100_rxdes *rxdes)
334 return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_MULTICAST);
337 static void ftgmac100_rxdes_set_end_of_ring(const struct ftgmac100 *priv,
338 struct ftgmac100_rxdes *rxdes)
340 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
343 static void ftgmac100_rxdes_set_dma_addr(struct ftgmac100_rxdes *rxdes,
346 rxdes->rxdes3 = cpu_to_le32(addr);
349 static dma_addr_t ftgmac100_rxdes_get_dma_addr(struct ftgmac100_rxdes *rxdes)
351 return le32_to_cpu(rxdes->rxdes3);
354 static bool ftgmac100_rxdes_is_tcp(struct ftgmac100_rxdes *rxdes)
356 return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) ==
357 cpu_to_le32(FTGMAC100_RXDES1_PROT_TCPIP);
360 static bool ftgmac100_rxdes_is_udp(struct ftgmac100_rxdes *rxdes)
362 return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) ==
363 cpu_to_le32(FTGMAC100_RXDES1_PROT_UDPIP);
366 static bool ftgmac100_rxdes_tcpcs_err(struct ftgmac100_rxdes *rxdes)
368 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR);
371 static bool ftgmac100_rxdes_udpcs_err(struct ftgmac100_rxdes *rxdes)
373 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_UDP_CHKSUM_ERR);
376 static bool ftgmac100_rxdes_ipcs_err(struct ftgmac100_rxdes *rxdes)
378 return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_IP_CHKSUM_ERR);
381 static inline struct page **ftgmac100_rxdes_page_slot(struct ftgmac100 *priv,
382 struct ftgmac100_rxdes *rxdes)
384 return &priv->rx_pages[rxdes - priv->descs->rxdes];
388 * rxdes2 is not used by hardware. We use it to keep track of page.
389 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
391 static void ftgmac100_rxdes_set_page(struct ftgmac100 *priv,
392 struct ftgmac100_rxdes *rxdes,
395 *ftgmac100_rxdes_page_slot(priv, rxdes) = page;
398 static struct page *ftgmac100_rxdes_get_page(struct ftgmac100 *priv,
399 struct ftgmac100_rxdes *rxdes)
401 return *ftgmac100_rxdes_page_slot(priv, rxdes);
404 static int ftgmac100_next_rx_pointer(int pointer)
406 return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
409 static void ftgmac100_rx_pointer_advance(struct ftgmac100 *priv)
411 priv->rx_pointer = ftgmac100_next_rx_pointer(priv->rx_pointer);
414 static struct ftgmac100_rxdes *ftgmac100_current_rxdes(struct ftgmac100 *priv)
416 return &priv->descs->rxdes[priv->rx_pointer];
419 static struct ftgmac100_rxdes *
420 ftgmac100_rx_locate_first_segment(struct ftgmac100 *priv)
422 struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
424 while (ftgmac100_rxdes_packet_ready(rxdes)) {
425 if (ftgmac100_rxdes_first_segment(rxdes))
428 ftgmac100_rxdes_set_dma_own(priv, rxdes);
429 ftgmac100_rx_pointer_advance(priv);
430 rxdes = ftgmac100_current_rxdes(priv);
436 static bool ftgmac100_rx_packet_error(struct ftgmac100 *priv,
437 struct ftgmac100_rxdes *rxdes)
439 struct net_device *netdev = priv->netdev;
442 if (unlikely(ftgmac100_rxdes_rx_error(rxdes))) {
444 netdev_info(netdev, "rx err\n");
446 netdev->stats.rx_errors++;
450 if (unlikely(ftgmac100_rxdes_crc_error(rxdes))) {
452 netdev_info(netdev, "rx crc err\n");
454 netdev->stats.rx_crc_errors++;
456 } else if (unlikely(ftgmac100_rxdes_ipcs_err(rxdes))) {
458 netdev_info(netdev, "rx IP checksum err\n");
463 if (unlikely(ftgmac100_rxdes_frame_too_long(rxdes))) {
465 netdev_info(netdev, "rx frame too long\n");
467 netdev->stats.rx_length_errors++;
469 } else if (unlikely(ftgmac100_rxdes_runt(rxdes))) {
471 netdev_info(netdev, "rx runt\n");
473 netdev->stats.rx_length_errors++;
475 } else if (unlikely(ftgmac100_rxdes_odd_nibble(rxdes))) {
477 netdev_info(netdev, "rx odd nibble\n");
479 netdev->stats.rx_length_errors++;
486 static void ftgmac100_rx_drop_packet(struct ftgmac100 *priv)
488 struct net_device *netdev = priv->netdev;
489 struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
493 netdev_dbg(netdev, "drop packet %p\n", rxdes);
496 if (ftgmac100_rxdes_last_segment(rxdes))
499 ftgmac100_rxdes_set_dma_own(priv, rxdes);
500 ftgmac100_rx_pointer_advance(priv);
501 rxdes = ftgmac100_current_rxdes(priv);
502 } while (!done && ftgmac100_rxdes_packet_ready(rxdes));
504 netdev->stats.rx_dropped++;
507 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
509 struct net_device *netdev = priv->netdev;
510 struct ftgmac100_rxdes *rxdes;
514 rxdes = ftgmac100_rx_locate_first_segment(priv);
518 if (unlikely(ftgmac100_rx_packet_error(priv, rxdes))) {
519 ftgmac100_rx_drop_packet(priv);
523 /* start processing */
524 skb = netdev_alloc_skb_ip_align(netdev, 128);
525 if (unlikely(!skb)) {
527 netdev_err(netdev, "rx skb alloc failed\n");
529 ftgmac100_rx_drop_packet(priv);
533 if (unlikely(ftgmac100_rxdes_multicast(rxdes)))
534 netdev->stats.multicast++;
537 * It seems that HW does checksum incorrectly with fragmented packets,
538 * so we are conservative here - if HW checksum error, let software do
539 * the checksum again.
541 if ((ftgmac100_rxdes_is_tcp(rxdes) && !ftgmac100_rxdes_tcpcs_err(rxdes)) ||
542 (ftgmac100_rxdes_is_udp(rxdes) && !ftgmac100_rxdes_udpcs_err(rxdes)))
543 skb->ip_summed = CHECKSUM_UNNECESSARY;
546 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
547 struct page *page = ftgmac100_rxdes_get_page(priv, rxdes);
550 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
552 size = ftgmac100_rxdes_data_length(rxdes);
553 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, 0, size);
556 skb->data_len += size;
557 skb->truesize += PAGE_SIZE;
559 if (ftgmac100_rxdes_last_segment(rxdes))
562 ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC);
564 ftgmac100_rx_pointer_advance(priv);
565 rxdes = ftgmac100_current_rxdes(priv);
568 /* Small frames are copied into linear part of skb to free one page */
569 if (skb->len <= 128) {
570 skb->truesize -= PAGE_SIZE;
571 __pskb_pull_tail(skb, skb->len);
573 /* We pull the minimum amount into linear part */
574 __pskb_pull_tail(skb, ETH_HLEN);
576 skb->protocol = eth_type_trans(skb, netdev);
578 netdev->stats.rx_packets++;
579 netdev->stats.rx_bytes += skb->len;
581 /* push packet to protocol stack */
582 napi_gro_receive(&priv->napi, skb);
588 static void ftgmac100_txdes_reset(const struct ftgmac100 *priv,
589 struct ftgmac100_txdes *txdes)
591 /* clear all except end of ring bit */
592 txdes->txdes0 &= cpu_to_le32(priv->txdes0_edotr_mask);
598 static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes)
600 return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
603 static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes)
606 * Make sure dma own bit will not be set before any other
610 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
613 static void ftgmac100_txdes_set_end_of_ring(const struct ftgmac100 *priv,
614 struct ftgmac100_txdes *txdes)
616 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
619 static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes)
621 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS);
624 static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes)
626 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS);
629 static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes,
632 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len));
635 static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes)
637 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC);
640 static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes)
642 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM);
645 static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes)
647 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM);
650 static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes)
652 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM);
655 static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes,
658 txdes->txdes3 = cpu_to_le32(addr);
661 static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes)
663 return le32_to_cpu(txdes->txdes3);
667 * txdes2 is not used by hardware. We use it to keep track of socket buffer.
668 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
670 static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes,
673 txdes->txdes2 = (unsigned int)skb;
676 static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes)
678 return (struct sk_buff *)txdes->txdes2;
681 static int ftgmac100_next_tx_pointer(int pointer)
683 return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
686 static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv)
688 priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer);
691 static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv)
693 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer);
696 static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv)
698 return &priv->descs->txdes[priv->tx_pointer];
701 static struct ftgmac100_txdes *
702 ftgmac100_current_clean_txdes(struct ftgmac100 *priv)
704 return &priv->descs->txdes[priv->tx_clean_pointer];
707 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
709 struct net_device *netdev = priv->netdev;
710 struct ftgmac100_txdes *txdes;
714 if (priv->tx_pending == 0)
717 txdes = ftgmac100_current_clean_txdes(priv);
719 if (ftgmac100_txdes_owned_by_dma(txdes))
722 skb = ftgmac100_txdes_get_skb(txdes);
723 map = ftgmac100_txdes_get_dma_addr(txdes);
725 netdev->stats.tx_packets++;
726 netdev->stats.tx_bytes += skb->len;
728 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
732 ftgmac100_txdes_reset(priv, txdes);
734 ftgmac100_tx_clean_pointer_advance(priv);
736 spin_lock(&priv->tx_lock);
738 spin_unlock(&priv->tx_lock);
739 netif_wake_queue(netdev);
744 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
746 while (ftgmac100_tx_complete_packet(priv))
750 static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb,
753 struct net_device *netdev = priv->netdev;
754 struct ftgmac100_txdes *txdes;
755 unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
757 txdes = ftgmac100_current_txdes(priv);
758 ftgmac100_tx_pointer_advance(priv);
760 /* setup TX descriptor */
761 ftgmac100_txdes_set_skb(txdes, skb);
762 ftgmac100_txdes_set_dma_addr(txdes, map);
763 ftgmac100_txdes_set_buffer_size(txdes, len);
765 ftgmac100_txdes_set_first_segment(txdes);
766 ftgmac100_txdes_set_last_segment(txdes);
767 ftgmac100_txdes_set_txint(txdes);
768 if (skb->ip_summed == CHECKSUM_PARTIAL) {
769 __be16 protocol = skb->protocol;
771 if (protocol == cpu_to_be16(ETH_P_IP)) {
772 u8 ip_proto = ip_hdr(skb)->protocol;
774 ftgmac100_txdes_set_ipcs(txdes);
775 if (ip_proto == IPPROTO_TCP)
776 ftgmac100_txdes_set_tcpcs(txdes);
777 else if (ip_proto == IPPROTO_UDP)
778 ftgmac100_txdes_set_udpcs(txdes);
782 spin_lock(&priv->tx_lock);
784 if (priv->tx_pending == TX_QUEUE_ENTRIES)
785 netif_stop_queue(netdev);
788 ftgmac100_txdes_set_dma_own(txdes);
789 spin_unlock(&priv->tx_lock);
791 ftgmac100_txdma_normal_prio_start_polling(priv);
796 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
797 struct ftgmac100_rxdes *rxdes, gfp_t gfp)
799 struct net_device *netdev = priv->netdev;
803 page = alloc_page(gfp);
806 netdev_err(netdev, "failed to allocate rx page\n");
810 map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE);
811 if (unlikely(dma_mapping_error(priv->dev, map))) {
813 netdev_err(netdev, "failed to map rx page\n");
818 ftgmac100_rxdes_set_page(priv, rxdes, page);
819 ftgmac100_rxdes_set_dma_addr(rxdes, map);
820 ftgmac100_rxdes_set_dma_own(priv, rxdes);
824 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
828 /* Free all RX buffers */
829 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
830 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
831 struct page *page = ftgmac100_rxdes_get_page(priv, rxdes);
832 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
837 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
841 /* Free all TX buffers */
842 for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
843 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i];
844 struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes);
845 dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes);
850 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
855 static void ftgmac100_free_rings(struct ftgmac100 *priv)
857 /* Free descriptors */
859 dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs),
860 priv->descs, priv->descs_dma_addr);
863 static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
865 /* Allocate descriptors */
866 priv->descs = dma_zalloc_coherent(priv->dev,
867 sizeof(struct ftgmac100_descs),
868 &priv->descs_dma_addr, GFP_KERNEL);
875 static void ftgmac100_init_rings(struct ftgmac100 *priv)
879 /* Initialize RX ring */
880 for (i = 0; i < RX_QUEUE_ENTRIES; i++)
881 priv->descs->rxdes[i].rxdes0 = 0;
882 ftgmac100_rxdes_set_end_of_ring(priv, &priv->descs->rxdes[i - 1]);
884 /* Initialize TX ring */
885 for (i = 0; i < TX_QUEUE_ENTRIES; i++)
886 priv->descs->txdes[i].txdes0 = 0;
887 ftgmac100_txdes_set_end_of_ring(priv, &priv->descs->txdes[i -1]);
890 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
894 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
895 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
897 if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL))
903 static void ftgmac100_adjust_link(struct net_device *netdev)
905 struct ftgmac100 *priv = netdev_priv(netdev);
906 struct phy_device *phydev = netdev->phydev;
909 /* We store "no link" as speed 0 */
913 new_speed = phydev->speed;
915 if (phydev->speed == priv->cur_speed &&
916 phydev->duplex == priv->cur_duplex)
919 /* Print status if we have a link or we had one and just lost it,
920 * don't print otherwise.
922 if (new_speed || priv->cur_speed)
923 phy_print_status(phydev);
925 priv->cur_speed = new_speed;
926 priv->cur_duplex = phydev->duplex;
928 /* Link is down, do nothing else */
932 /* Disable all interrupts */
933 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
935 /* Reset the adapter asynchronously */
936 schedule_work(&priv->reset_task);
939 static int ftgmac100_mii_probe(struct ftgmac100 *priv)
941 struct net_device *netdev = priv->netdev;
942 struct phy_device *phydev;
944 phydev = phy_find_first(priv->mii_bus);
946 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
950 phydev = phy_connect(netdev, phydev_name(phydev),
951 &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII);
953 if (IS_ERR(phydev)) {
954 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
955 return PTR_ERR(phydev);
961 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
963 struct net_device *netdev = bus->priv;
964 struct ftgmac100 *priv = netdev_priv(netdev);
968 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
970 /* preserve MDC cycle threshold */
971 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
973 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
974 FTGMAC100_PHYCR_REGAD(regnum) |
975 FTGMAC100_PHYCR_MIIRD;
977 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
979 for (i = 0; i < 10; i++) {
980 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
982 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
985 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
986 return FTGMAC100_PHYDATA_MIIRDATA(data);
992 netdev_err(netdev, "mdio read timed out\n");
996 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
997 int regnum, u16 value)
999 struct net_device *netdev = bus->priv;
1000 struct ftgmac100 *priv = netdev_priv(netdev);
1005 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1007 /* preserve MDC cycle threshold */
1008 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
1010 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
1011 FTGMAC100_PHYCR_REGAD(regnum) |
1012 FTGMAC100_PHYCR_MIIWR;
1014 data = FTGMAC100_PHYDATA_MIIWDATA(value);
1016 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
1017 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
1019 for (i = 0; i < 10; i++) {
1020 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
1022 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
1028 netdev_err(netdev, "mdio write timed out\n");
1032 static void ftgmac100_get_drvinfo(struct net_device *netdev,
1033 struct ethtool_drvinfo *info)
1035 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1036 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1037 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
1040 static const struct ethtool_ops ftgmac100_ethtool_ops = {
1041 .get_drvinfo = ftgmac100_get_drvinfo,
1042 .get_link = ethtool_op_get_link,
1043 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1044 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1047 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
1049 struct net_device *netdev = dev_id;
1050 struct ftgmac100 *priv = netdev_priv(netdev);
1051 unsigned int status, new_mask = FTGMAC100_INT_BAD;
1053 /* Fetch and clear interrupt bits, process abnormal ones */
1054 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
1055 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
1056 if (unlikely(status & FTGMAC100_INT_BAD)) {
1058 /* RX buffer unavailable */
1059 if (status & FTGMAC100_INT_NO_RXBUF)
1060 netdev->stats.rx_over_errors++;
1062 /* received packet lost due to RX FIFO full */
1063 if (status & FTGMAC100_INT_RPKT_LOST)
1064 netdev->stats.rx_fifo_errors++;
1066 /* sent packet lost due to excessive TX collision */
1067 if (status & FTGMAC100_INT_XPKT_LOST)
1068 netdev->stats.tx_fifo_errors++;
1070 /* AHB error -> Reset the chip */
1071 if (status & FTGMAC100_INT_AHB_ERR) {
1072 if (net_ratelimit())
1074 "AHB bus error ! Resetting chip.\n");
1075 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1076 schedule_work(&priv->reset_task);
1080 /* We may need to restart the MAC after such errors, delay
1081 * this until after we have freed some Rx buffers though
1083 priv->need_mac_restart = true;
1085 /* Disable those errors until we restart */
1086 new_mask &= ~status;
1089 /* Only enable "bad" interrupts while NAPI is on */
1090 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
1092 /* Schedule NAPI bh */
1093 napi_schedule_irqoff(&priv->napi);
1098 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1100 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1101 bool more, completed = true;
1104 ftgmac100_tx_complete(priv);
1107 more = ftgmac100_rx_packet(priv, &rx);
1108 } while (more && rx < budget);
1110 if (more && rx == budget)
1114 /* The interrupt is telling us to kick the MAC back to life
1115 * after an RX overflow
1117 if (unlikely(priv->need_mac_restart)) {
1118 ftgmac100_start_hw(priv);
1120 /* Re-enable "bad" interrupts */
1121 iowrite32(FTGMAC100_INT_BAD,
1122 priv->base + FTGMAC100_OFFSET_IER);
1125 /* Keep NAPI going if we have still packets to reclaim */
1126 if (priv->tx_pending)
1130 /* We are about to re-enable all interrupts. However
1131 * the HW has been latching RX/TX packet interrupts while
1132 * they were masked. So we clear them first, then we need
1133 * to re-check if there's something to process
1135 iowrite32(FTGMAC100_INT_RXTX,
1136 priv->base + FTGMAC100_OFFSET_ISR);
1137 if (ftgmac100_rxdes_packet_ready
1138 (ftgmac100_current_rxdes(priv)) || priv->tx_pending)
1141 /* deschedule NAPI */
1142 napi_complete(napi);
1144 /* enable all interrupts */
1145 iowrite32(FTGMAC100_INT_ALL,
1146 priv->base + FTGMAC100_OFFSET_IER);
1152 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1156 /* Re-init descriptors (adjust queue sizes) */
1157 ftgmac100_init_rings(priv);
1159 /* Realloc rx descriptors */
1160 err = ftgmac100_alloc_rx_buffers(priv);
1161 if (err && !ignore_alloc_err)
1164 /* Reinit and restart HW */
1165 ftgmac100_init_hw(priv);
1166 ftgmac100_start_hw(priv);
1168 /* Re-enable the device */
1169 napi_enable(&priv->napi);
1170 netif_start_queue(priv->netdev);
1172 /* Enable all interrupts */
1173 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1178 static void ftgmac100_reset_task(struct work_struct *work)
1180 struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1182 struct net_device *netdev = priv->netdev;
1185 netdev_dbg(netdev, "Resetting NIC...\n");
1187 /* Lock the world */
1190 mutex_lock(&netdev->phydev->lock);
1192 mutex_lock(&priv->mii_bus->mdio_lock);
1195 /* Check if the interface is still up */
1196 if (!netif_running(netdev))
1199 /* Stop the network stack */
1200 netif_trans_update(netdev);
1201 napi_disable(&priv->napi);
1202 netif_tx_disable(netdev);
1204 /* Stop and reset the MAC */
1205 ftgmac100_stop_hw(priv);
1206 err = ftgmac100_reset_and_config_mac(priv);
1208 /* Not much we can do ... it might come back... */
1209 netdev_err(netdev, "attempting to continue...\n");
1212 /* Free all rx and tx buffers */
1213 ftgmac100_free_buffers(priv);
1215 /* Setup everything again and restart chip */
1216 ftgmac100_init_all(priv, true);
1218 netdev_dbg(netdev, "Reset done !\n");
1221 mutex_unlock(&priv->mii_bus->mdio_lock);
1223 mutex_unlock(&netdev->phydev->lock);
1227 static int ftgmac100_open(struct net_device *netdev)
1229 struct ftgmac100 *priv = netdev_priv(netdev);
1232 /* Allocate ring buffers */
1233 err = ftgmac100_alloc_rings(priv);
1235 netdev_err(netdev, "Failed to allocate descriptors\n");
1239 /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1241 * Otherwise we leave it set to 0 (no link), the link
1242 * message from the PHY layer will handle setting it up to
1243 * something else if needed.
1245 if (priv->use_ncsi) {
1246 priv->cur_duplex = DUPLEX_FULL;
1247 priv->cur_speed = SPEED_100;
1249 priv->cur_duplex = 0;
1250 priv->cur_speed = 0;
1253 /* Reset the hardware */
1254 err = ftgmac100_reset_and_config_mac(priv);
1258 /* Initialize NAPI */
1259 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1261 /* Grab our interrupt */
1262 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1264 netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1268 /* Start things up */
1269 err = ftgmac100_init_all(priv, false);
1271 netdev_err(netdev, "Failed to allocate packet buffers\n");
1275 if (netdev->phydev) {
1276 /* If we have a PHY, start polling */
1277 phy_start(netdev->phydev);
1278 } else if (priv->use_ncsi) {
1279 /* If using NC-SI, set our carrier on and start the stack */
1280 netif_carrier_on(netdev);
1282 /* Start the NCSI device */
1283 err = ncsi_start_dev(priv->ndev);
1291 napi_disable(&priv->napi);
1292 netif_stop_queue(netdev);
1294 ftgmac100_free_buffers(priv);
1295 free_irq(netdev->irq, netdev);
1297 netif_napi_del(&priv->napi);
1299 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1300 ftgmac100_free_rings(priv);
1304 static int ftgmac100_stop(struct net_device *netdev)
1306 struct ftgmac100 *priv = netdev_priv(netdev);
1308 /* Note about the reset task: We are called with the rtnl lock
1309 * held, so we are synchronized against the core of the reset
1310 * task. We must not try to synchronously cancel it otherwise
1311 * we can deadlock. But since it will test for netif_running()
1312 * which has already been cleared by the net core, we don't
1313 * anything special to do.
1316 /* disable all interrupts */
1317 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1319 netif_stop_queue(netdev);
1320 napi_disable(&priv->napi);
1321 netif_napi_del(&priv->napi);
1323 phy_stop(netdev->phydev);
1324 else if (priv->use_ncsi)
1325 ncsi_stop_dev(priv->ndev);
1327 ftgmac100_stop_hw(priv);
1328 free_irq(netdev->irq, netdev);
1329 ftgmac100_free_buffers(priv);
1330 ftgmac100_free_rings(priv);
1335 static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
1336 struct net_device *netdev)
1338 struct ftgmac100 *priv = netdev_priv(netdev);
1341 if (unlikely(skb->len > MAX_PKT_SIZE)) {
1342 if (net_ratelimit())
1343 netdev_dbg(netdev, "tx packet too big\n");
1345 netdev->stats.tx_dropped++;
1347 return NETDEV_TX_OK;
1350 map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
1351 if (unlikely(dma_mapping_error(priv->dev, map))) {
1353 if (net_ratelimit())
1354 netdev_err(netdev, "map socket buffer failed\n");
1356 netdev->stats.tx_dropped++;
1358 return NETDEV_TX_OK;
1361 return ftgmac100_xmit(priv, skb, map);
1365 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1367 if (!netdev->phydev)
1370 return phy_mii_ioctl(netdev->phydev, ifr, cmd);
1373 static const struct net_device_ops ftgmac100_netdev_ops = {
1374 .ndo_open = ftgmac100_open,
1375 .ndo_stop = ftgmac100_stop,
1376 .ndo_start_xmit = ftgmac100_hard_start_xmit,
1377 .ndo_set_mac_address = ftgmac100_set_mac_addr,
1378 .ndo_validate_addr = eth_validate_addr,
1379 .ndo_do_ioctl = ftgmac100_do_ioctl,
1382 static int ftgmac100_setup_mdio(struct net_device *netdev)
1384 struct ftgmac100 *priv = netdev_priv(netdev);
1385 struct platform_device *pdev = to_platform_device(priv->dev);
1389 /* initialize mdio bus */
1390 priv->mii_bus = mdiobus_alloc();
1394 if (of_machine_is_compatible("aspeed,ast2400") ||
1395 of_machine_is_compatible("aspeed,ast2500")) {
1396 /* This driver supports the old MDIO interface */
1397 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1398 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1399 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1402 priv->mii_bus->name = "ftgmac100_mdio";
1403 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1404 pdev->name, pdev->id);
1405 priv->mii_bus->priv = priv->netdev;
1406 priv->mii_bus->read = ftgmac100_mdiobus_read;
1407 priv->mii_bus->write = ftgmac100_mdiobus_write;
1409 for (i = 0; i < PHY_MAX_ADDR; i++)
1410 priv->mii_bus->irq[i] = PHY_POLL;
1412 err = mdiobus_register(priv->mii_bus);
1414 dev_err(priv->dev, "Cannot register MDIO bus!\n");
1415 goto err_register_mdiobus;
1418 err = ftgmac100_mii_probe(priv);
1420 dev_err(priv->dev, "MII Probe failed!\n");
1427 mdiobus_unregister(priv->mii_bus);
1428 err_register_mdiobus:
1429 mdiobus_free(priv->mii_bus);
1433 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1435 struct ftgmac100 *priv = netdev_priv(netdev);
1437 if (!netdev->phydev)
1440 phy_disconnect(netdev->phydev);
1441 mdiobus_unregister(priv->mii_bus);
1442 mdiobus_free(priv->mii_bus);
1445 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1447 if (unlikely(nd->state != ncsi_dev_state_functional))
1450 netdev_info(nd->dev, "NCSI interface %s\n",
1451 nd->link_up ? "up" : "down");
1454 static int ftgmac100_probe(struct platform_device *pdev)
1456 struct resource *res;
1458 struct net_device *netdev;
1459 struct ftgmac100 *priv;
1465 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1469 irq = platform_get_irq(pdev, 0);
1473 /* setup net_device */
1474 netdev = alloc_etherdev(sizeof(*priv));
1477 goto err_alloc_etherdev;
1480 SET_NETDEV_DEV(netdev, &pdev->dev);
1482 netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1483 netdev->netdev_ops = &ftgmac100_netdev_ops;
1485 platform_set_drvdata(pdev, netdev);
1487 /* setup private data */
1488 priv = netdev_priv(netdev);
1489 priv->netdev = netdev;
1490 priv->dev = &pdev->dev;
1491 INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1493 spin_lock_init(&priv->tx_lock);
1496 priv->res = request_mem_region(res->start, resource_size(res),
1497 dev_name(&pdev->dev));
1499 dev_err(&pdev->dev, "Could not reserve memory region\n");
1504 priv->base = ioremap(res->start, resource_size(res));
1506 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1513 /* MAC address from chip or random one */
1514 ftgmac100_setup_mac(priv);
1516 if (of_machine_is_compatible("aspeed,ast2400") ||
1517 of_machine_is_compatible("aspeed,ast2500")) {
1518 priv->rxdes0_edorr_mask = BIT(30);
1519 priv->txdes0_edotr_mask = BIT(30);
1521 priv->rxdes0_edorr_mask = BIT(15);
1522 priv->txdes0_edotr_mask = BIT(15);
1525 if (pdev->dev.of_node &&
1526 of_get_property(pdev->dev.of_node, "use-ncsi", NULL)) {
1527 if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1528 dev_err(&pdev->dev, "NCSI stack not enabled\n");
1532 dev_info(&pdev->dev, "Using NCSI interface\n");
1533 priv->use_ncsi = true;
1534 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1538 priv->use_ncsi = false;
1539 err = ftgmac100_setup_mdio(netdev);
1541 goto err_setup_mdio;
1544 /* We have to disable on-chip IP checksum functionality
1545 * when NCSI is enabled on the interface. It doesn't work
1548 netdev->features = NETIF_F_IP_CSUM | NETIF_F_GRO;
1549 if (priv->use_ncsi &&
1550 of_get_property(pdev->dev.of_node, "no-hw-checksum", NULL))
1551 netdev->features &= ~NETIF_F_IP_CSUM;
1554 /* register network device */
1555 err = register_netdev(netdev);
1557 dev_err(&pdev->dev, "Failed to register netdev\n");
1558 goto err_register_netdev;
1561 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
1566 err_register_netdev:
1567 ftgmac100_destroy_mdio(netdev);
1569 iounmap(priv->base);
1571 release_resource(priv->res);
1573 netif_napi_del(&priv->napi);
1574 free_netdev(netdev);
1579 static int ftgmac100_remove(struct platform_device *pdev)
1581 struct net_device *netdev;
1582 struct ftgmac100 *priv;
1584 netdev = platform_get_drvdata(pdev);
1585 priv = netdev_priv(netdev);
1587 unregister_netdev(netdev);
1589 /* There's a small chance the reset task will have been re-queued,
1590 * during stop, make sure it's gone before we free the structure.
1592 cancel_work_sync(&priv->reset_task);
1594 ftgmac100_destroy_mdio(netdev);
1596 iounmap(priv->base);
1597 release_resource(priv->res);
1599 netif_napi_del(&priv->napi);
1600 free_netdev(netdev);
1604 static const struct of_device_id ftgmac100_of_match[] = {
1605 { .compatible = "faraday,ftgmac100" },
1608 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
1610 static struct platform_driver ftgmac100_driver = {
1611 .probe = ftgmac100_probe,
1612 .remove = ftgmac100_remove,
1615 .of_match_table = ftgmac100_of_match,
1618 module_platform_driver(ftgmac100_driver);
1620 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1621 MODULE_DESCRIPTION("FTGMAC100 driver");
1622 MODULE_LICENSE("GPL");