2 * Faraday FTGMAC100 Gigabit Ethernet
4 * (C) Copyright 2009-2011 Faraday Technology
5 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/ethtool.h>
27 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
32 #include <linux/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/property.h>
38 #include "ftgmac100.h"
40 #define DRV_NAME "ftgmac100"
41 #define DRV_VERSION "0.7"
43 #define RX_QUEUE_ENTRIES 256 /* must be power of 2 */
44 #define TX_QUEUE_ENTRIES 512 /* must be power of 2 */
46 #define MAX_PKT_SIZE 1536
47 #define RX_BUF_SIZE MAX_PKT_SIZE /* must be smaller than 0x3fff */
49 struct ftgmac100_descs {
50 struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
51 struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES];
59 struct ftgmac100_descs *descs;
60 dma_addr_t descs_dma_addr;
63 struct sk_buff *rx_skbs[RX_QUEUE_ENTRIES];
64 unsigned int rx_pointer;
65 u32 rxdes0_edorr_mask;
68 unsigned int tx_clean_pointer;
69 unsigned int tx_pointer;
70 unsigned int tx_pending;
71 u32 txdes0_edotr_mask;
74 /* Scratch page to use when rx skb alloc fails */
76 dma_addr_t rx_scratch_dma;
78 /* Component structures */
79 struct net_device *netdev;
81 struct ncsi_dev *ndev;
82 struct napi_struct napi;
83 struct work_struct reset_task;
84 struct mii_bus *mii_bus;
92 bool need_mac_restart;
95 static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr)
97 iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR);
100 static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv,
103 size = FTGMAC100_RBSR_SIZE(size);
104 iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR);
107 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv,
110 iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
113 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv)
115 iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
118 static int ftgmac100_reset_mac(struct ftgmac100 *priv, u32 maccr)
120 struct net_device *netdev = priv->netdev;
123 /* NOTE: reset clears all registers */
124 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
125 iowrite32(maccr | FTGMAC100_MACCR_SW_RST,
126 priv->base + FTGMAC100_OFFSET_MACCR);
127 for (i = 0; i < 50; i++) {
130 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
131 if (!(maccr & FTGMAC100_MACCR_SW_RST))
137 netdev_err(netdev, "Hardware reset failed\n");
141 static int ftgmac100_reset_and_config_mac(struct ftgmac100 *priv)
145 switch (priv->cur_speed) {
147 case 0: /* no link */
151 maccr |= FTGMAC100_MACCR_FAST_MODE;
155 maccr |= FTGMAC100_MACCR_GIGA_MODE;
158 netdev_err(priv->netdev, "Unknown speed %d !\n",
163 /* (Re)initialize the queue pointers */
164 priv->rx_pointer = 0;
165 priv->tx_clean_pointer = 0;
166 priv->tx_pointer = 0;
167 priv->tx_pending = 0;
169 /* The doc says reset twice with 10us interval */
170 if (ftgmac100_reset_mac(priv, maccr))
172 usleep_range(10, 1000);
173 return ftgmac100_reset_mac(priv, maccr);
176 static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac)
178 unsigned int maddr = mac[0] << 8 | mac[1];
179 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
181 iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
182 iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
185 static void ftgmac100_setup_mac(struct ftgmac100 *priv)
192 addr = device_get_mac_address(priv->dev, mac, ETH_ALEN);
194 ether_addr_copy(priv->netdev->dev_addr, mac);
195 dev_info(priv->dev, "Read MAC address %pM from device tree\n",
200 m = ioread32(priv->base + FTGMAC100_OFFSET_MAC_MADR);
201 l = ioread32(priv->base + FTGMAC100_OFFSET_MAC_LADR);
203 mac[0] = (m >> 8) & 0xff;
205 mac[2] = (l >> 24) & 0xff;
206 mac[3] = (l >> 16) & 0xff;
207 mac[4] = (l >> 8) & 0xff;
210 if (is_valid_ether_addr(mac)) {
211 ether_addr_copy(priv->netdev->dev_addr, mac);
212 dev_info(priv->dev, "Read MAC address %pM from chip\n", mac);
214 eth_hw_addr_random(priv->netdev);
215 dev_info(priv->dev, "Generated random MAC address %pM\n",
216 priv->netdev->dev_addr);
220 static int ftgmac100_set_mac_addr(struct net_device *dev, void *p)
224 ret = eth_prepare_mac_addr_change(dev, p);
228 eth_commit_mac_addr_change(dev, p);
229 ftgmac100_set_mac(netdev_priv(dev), dev->dev_addr);
234 static void ftgmac100_init_hw(struct ftgmac100 *priv)
236 /* setup ring buffer base registers */
237 ftgmac100_set_rx_ring_base(priv,
238 priv->descs_dma_addr +
239 offsetof(struct ftgmac100_descs, rxdes));
240 ftgmac100_set_normal_prio_tx_ring_base(priv,
241 priv->descs_dma_addr +
242 offsetof(struct ftgmac100_descs, txdes));
244 ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE);
246 iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC);
248 ftgmac100_set_mac(priv, priv->netdev->dev_addr);
251 static void ftgmac100_start_hw(struct ftgmac100 *priv)
253 u32 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
255 /* Keep the original GMAC and FAST bits */
256 maccr &= (FTGMAC100_MACCR_FAST_MODE | FTGMAC100_MACCR_GIGA_MODE);
258 /* Add all the main enable bits */
259 maccr |= FTGMAC100_MACCR_TXDMA_EN |
260 FTGMAC100_MACCR_RXDMA_EN |
261 FTGMAC100_MACCR_TXMAC_EN |
262 FTGMAC100_MACCR_RXMAC_EN |
263 FTGMAC100_MACCR_CRC_APD |
264 FTGMAC100_MACCR_PHY_LINK_LEVEL |
265 FTGMAC100_MACCR_RX_RUNT |
266 FTGMAC100_MACCR_RX_BROADPKT;
268 /* Add other bits as needed */
269 if (priv->cur_duplex == DUPLEX_FULL)
270 maccr |= FTGMAC100_MACCR_FULLDUP;
273 iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
276 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
278 iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
281 static int ftgmac100_alloc_rx_buf(struct ftgmac100 *priv, unsigned int entry,
282 struct ftgmac100_rxdes *rxdes, gfp_t gfp)
284 struct net_device *netdev = priv->netdev;
289 skb = netdev_alloc_skb_ip_align(netdev, RX_BUF_SIZE);
290 if (unlikely(!skb)) {
292 netdev_warn(netdev, "failed to allocate rx skb\n");
294 map = priv->rx_scratch_dma;
296 map = dma_map_single(priv->dev, skb->data, RX_BUF_SIZE,
298 if (unlikely(dma_mapping_error(priv->dev, map))) {
300 netdev_err(netdev, "failed to map rx page\n");
301 dev_kfree_skb_any(skb);
302 map = priv->rx_scratch_dma;
309 priv->rx_skbs[entry] = skb;
311 /* Store DMA address into RX desc */
312 rxdes->rxdes3 = cpu_to_le32(map);
314 /* Ensure the above is ordered vs clearing the OWN bit */
317 /* Clean status (which resets own bit) */
318 if (entry == (RX_QUEUE_ENTRIES - 1))
319 rxdes->rxdes0 = cpu_to_le32(priv->rxdes0_edorr_mask);
326 static int ftgmac100_next_rx_pointer(int pointer)
328 return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
331 static void ftgmac100_rx_packet_error(struct ftgmac100 *priv, u32 status)
333 struct net_device *netdev = priv->netdev;
335 if (status & FTGMAC100_RXDES0_RX_ERR)
336 netdev->stats.rx_errors++;
338 if (status & FTGMAC100_RXDES0_CRC_ERR)
339 netdev->stats.rx_crc_errors++;
341 if (status & (FTGMAC100_RXDES0_FTL |
342 FTGMAC100_RXDES0_RUNT |
343 FTGMAC100_RXDES0_RX_ODD_NB))
344 netdev->stats.rx_length_errors++;
347 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
349 struct net_device *netdev = priv->netdev;
350 struct ftgmac100_rxdes *rxdes;
352 unsigned int pointer, size;
353 u32 status, csum_vlan;
356 /* Grab next RX descriptor */
357 pointer = priv->rx_pointer;
358 rxdes = &priv->descs->rxdes[pointer];
360 /* Grab descriptor status */
361 status = le32_to_cpu(rxdes->rxdes0);
363 /* Do we have a packet ? */
364 if (!(status & FTGMAC100_RXDES0_RXPKT_RDY))
367 /* Order subsequent reads with the test for the ready bit */
370 /* We don't cope with fragmented RX packets */
371 if (unlikely(!(status & FTGMAC100_RXDES0_FRS) ||
372 !(status & FTGMAC100_RXDES0_LRS)))
375 /* Grab received size and csum vlan field in the descriptor */
376 size = status & FTGMAC100_RXDES0_VDBC;
377 csum_vlan = le32_to_cpu(rxdes->rxdes1);
379 /* Any error (other than csum offload) flagged ? */
380 if (unlikely(status & RXDES0_ANY_ERROR)) {
381 /* Correct for incorrect flagging of runt packets
382 * with vlan tags... Just accept a runt packet that
383 * has been flagged as vlan and whose size is at
386 if ((status & FTGMAC100_RXDES0_RUNT) &&
387 (csum_vlan & FTGMAC100_RXDES1_VLANTAG_AVAIL) &&
389 status &= ~FTGMAC100_RXDES0_RUNT;
391 /* Any error still in there ? */
392 if (status & RXDES0_ANY_ERROR) {
393 ftgmac100_rx_packet_error(priv, status);
398 /* If the packet had no skb (failed to allocate earlier)
399 * then try to allocate one and skip
401 skb = priv->rx_skbs[pointer];
402 if (!unlikely(skb)) {
403 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
407 if (unlikely(status & FTGMAC100_RXDES0_MULTICAST))
408 netdev->stats.multicast++;
410 /* If the HW found checksum errors, bounce it to software.
412 * If we didn't, we need to see if the packet was recognized
413 * by HW as one of the supported checksummed protocols before
414 * we accept the HW test results.
416 if (netdev->features & NETIF_F_RXCSUM) {
417 u32 err_bits = FTGMAC100_RXDES1_TCP_CHKSUM_ERR |
418 FTGMAC100_RXDES1_UDP_CHKSUM_ERR |
419 FTGMAC100_RXDES1_IP_CHKSUM_ERR;
420 if ((csum_vlan & err_bits) ||
421 !(csum_vlan & FTGMAC100_RXDES1_PROT_MASK))
422 skb->ip_summed = CHECKSUM_NONE;
424 skb->ip_summed = CHECKSUM_UNNECESSARY;
427 /* Transfer received size to skb */
430 /* Tear down DMA mapping, do necessary cache management */
431 map = le32_to_cpu(rxdes->rxdes3);
433 #if defined(CONFIG_ARM) && !defined(CONFIG_ARM_DMA_USE_IOMMU)
434 /* When we don't have an iommu, we can save cycles by not
435 * invalidating the cache for the part of the packet that
438 dma_unmap_single(priv->dev, map, size, DMA_FROM_DEVICE);
440 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
444 /* Resplenish rx ring */
445 ftgmac100_alloc_rx_buf(priv, pointer, rxdes, GFP_ATOMIC);
446 priv->rx_pointer = ftgmac100_next_rx_pointer(pointer);
448 skb->protocol = eth_type_trans(skb, netdev);
450 netdev->stats.rx_packets++;
451 netdev->stats.rx_bytes += size;
453 /* push packet to protocol stack */
454 if (skb->ip_summed == CHECKSUM_NONE)
455 netif_receive_skb(skb);
457 napi_gro_receive(&priv->napi, skb);
463 /* Clean rxdes0 (which resets own bit) */
464 rxdes->rxdes0 = cpu_to_le32(status & priv->rxdes0_edorr_mask);
465 priv->rx_pointer = ftgmac100_next_rx_pointer(pointer);
466 netdev->stats.rx_dropped++;
470 static void ftgmac100_txdes_reset(const struct ftgmac100 *priv,
471 struct ftgmac100_txdes *txdes)
473 /* clear all except end of ring bit */
474 txdes->txdes0 &= cpu_to_le32(priv->txdes0_edotr_mask);
480 static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes)
482 return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
485 static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes)
488 * Make sure dma own bit will not be set before any other
492 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
495 static void ftgmac100_txdes_set_end_of_ring(const struct ftgmac100 *priv,
496 struct ftgmac100_txdes *txdes)
498 txdes->txdes0 |= cpu_to_le32(priv->txdes0_edotr_mask);
501 static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes)
503 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS);
506 static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes)
508 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS);
511 static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes,
514 txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len));
517 static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes)
519 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC);
522 static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes)
524 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM);
527 static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes)
529 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM);
532 static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes)
534 txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM);
537 static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes,
540 txdes->txdes3 = cpu_to_le32(addr);
543 static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes)
545 return le32_to_cpu(txdes->txdes3);
549 * txdes2 is not used by hardware. We use it to keep track of socket buffer.
550 * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
552 static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes,
555 txdes->txdes2 = (unsigned int)skb;
558 static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes)
560 return (struct sk_buff *)txdes->txdes2;
563 static int ftgmac100_next_tx_pointer(int pointer)
565 return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
568 static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv)
570 priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer);
573 static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv)
575 priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer);
578 static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv)
580 return &priv->descs->txdes[priv->tx_pointer];
583 static struct ftgmac100_txdes *
584 ftgmac100_current_clean_txdes(struct ftgmac100 *priv)
586 return &priv->descs->txdes[priv->tx_clean_pointer];
589 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
591 struct net_device *netdev = priv->netdev;
592 struct ftgmac100_txdes *txdes;
596 if (priv->tx_pending == 0)
599 txdes = ftgmac100_current_clean_txdes(priv);
601 if (ftgmac100_txdes_owned_by_dma(txdes))
604 skb = ftgmac100_txdes_get_skb(txdes);
605 map = ftgmac100_txdes_get_dma_addr(txdes);
607 netdev->stats.tx_packets++;
608 netdev->stats.tx_bytes += skb->len;
610 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
614 ftgmac100_txdes_reset(priv, txdes);
616 ftgmac100_tx_clean_pointer_advance(priv);
618 spin_lock(&priv->tx_lock);
620 spin_unlock(&priv->tx_lock);
621 netif_wake_queue(netdev);
626 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
628 while (ftgmac100_tx_complete_packet(priv))
632 static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb,
635 struct net_device *netdev = priv->netdev;
636 struct ftgmac100_txdes *txdes;
637 unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
639 txdes = ftgmac100_current_txdes(priv);
640 ftgmac100_tx_pointer_advance(priv);
642 /* setup TX descriptor */
643 ftgmac100_txdes_set_skb(txdes, skb);
644 ftgmac100_txdes_set_dma_addr(txdes, map);
645 ftgmac100_txdes_set_buffer_size(txdes, len);
647 ftgmac100_txdes_set_first_segment(txdes);
648 ftgmac100_txdes_set_last_segment(txdes);
649 ftgmac100_txdes_set_txint(txdes);
650 if (skb->ip_summed == CHECKSUM_PARTIAL) {
651 __be16 protocol = skb->protocol;
653 if (protocol == cpu_to_be16(ETH_P_IP)) {
654 u8 ip_proto = ip_hdr(skb)->protocol;
656 ftgmac100_txdes_set_ipcs(txdes);
657 if (ip_proto == IPPROTO_TCP)
658 ftgmac100_txdes_set_tcpcs(txdes);
659 else if (ip_proto == IPPROTO_UDP)
660 ftgmac100_txdes_set_udpcs(txdes);
664 spin_lock(&priv->tx_lock);
666 if (priv->tx_pending == TX_QUEUE_ENTRIES)
667 netif_stop_queue(netdev);
670 ftgmac100_txdes_set_dma_own(txdes);
671 spin_unlock(&priv->tx_lock);
673 ftgmac100_txdma_normal_prio_start_polling(priv);
678 static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
679 struct net_device *netdev)
681 struct ftgmac100 *priv = netdev_priv(netdev);
684 if (unlikely(skb->len > MAX_PKT_SIZE)) {
686 netdev_dbg(netdev, "tx packet too big\n");
688 netdev->stats.tx_dropped++;
693 map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
694 if (unlikely(dma_mapping_error(priv->dev, map))) {
697 netdev_err(netdev, "map socket buffer failed\n");
699 netdev->stats.tx_dropped++;
704 return ftgmac100_xmit(priv, skb, map);
707 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
711 /* Free all RX buffers */
712 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
713 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
714 struct sk_buff *skb = priv->rx_skbs[i];
715 dma_addr_t map = le32_to_cpu(rxdes->rxdes3);
720 priv->rx_skbs[i] = NULL;
721 dma_unmap_single(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
722 dev_kfree_skb_any(skb);
725 /* Free all TX buffers */
726 for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
727 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i];
728 struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes);
729 dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes);
734 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
739 static void ftgmac100_free_rings(struct ftgmac100 *priv)
741 /* Free descriptors */
743 dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs),
744 priv->descs, priv->descs_dma_addr);
746 /* Free scratch packet buffer */
747 if (priv->rx_scratch)
748 dma_free_coherent(priv->dev, RX_BUF_SIZE,
749 priv->rx_scratch, priv->rx_scratch_dma);
752 static int ftgmac100_alloc_rings(struct ftgmac100 *priv)
754 /* Allocate descriptors */
755 priv->descs = dma_zalloc_coherent(priv->dev,
756 sizeof(struct ftgmac100_descs),
757 &priv->descs_dma_addr, GFP_KERNEL);
761 /* Allocate scratch packet buffer */
762 priv->rx_scratch = dma_alloc_coherent(priv->dev,
764 &priv->rx_scratch_dma,
766 if (!priv->rx_scratch)
772 static void ftgmac100_init_rings(struct ftgmac100 *priv)
774 struct ftgmac100_rxdes *rxdes;
777 /* Initialize RX ring */
778 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
779 rxdes = &priv->descs->rxdes[i];
781 rxdes->rxdes3 = cpu_to_le32(priv->rx_scratch_dma);
783 /* Mark the end of the ring */
784 rxdes->rxdes0 |= cpu_to_le32(priv->rxdes0_edorr_mask);
786 /* Initialize TX ring */
787 for (i = 0; i < TX_QUEUE_ENTRIES; i++)
788 priv->descs->txdes[i].txdes0 = 0;
789 ftgmac100_txdes_set_end_of_ring(priv, &priv->descs->txdes[i -1]);
792 static int ftgmac100_alloc_rx_buffers(struct ftgmac100 *priv)
796 for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
797 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
799 if (ftgmac100_alloc_rx_buf(priv, i, rxdes, GFP_KERNEL))
805 static void ftgmac100_adjust_link(struct net_device *netdev)
807 struct ftgmac100 *priv = netdev_priv(netdev);
808 struct phy_device *phydev = netdev->phydev;
811 /* We store "no link" as speed 0 */
815 new_speed = phydev->speed;
817 if (phydev->speed == priv->cur_speed &&
818 phydev->duplex == priv->cur_duplex)
821 /* Print status if we have a link or we had one and just lost it,
822 * don't print otherwise.
824 if (new_speed || priv->cur_speed)
825 phy_print_status(phydev);
827 priv->cur_speed = new_speed;
828 priv->cur_duplex = phydev->duplex;
830 /* Link is down, do nothing else */
834 /* Disable all interrupts */
835 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
837 /* Reset the adapter asynchronously */
838 schedule_work(&priv->reset_task);
841 static int ftgmac100_mii_probe(struct ftgmac100 *priv)
843 struct net_device *netdev = priv->netdev;
844 struct phy_device *phydev;
846 phydev = phy_find_first(priv->mii_bus);
848 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
852 phydev = phy_connect(netdev, phydev_name(phydev),
853 &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII);
855 if (IS_ERR(phydev)) {
856 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
857 return PTR_ERR(phydev);
863 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
865 struct net_device *netdev = bus->priv;
866 struct ftgmac100 *priv = netdev_priv(netdev);
870 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
872 /* preserve MDC cycle threshold */
873 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
875 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
876 FTGMAC100_PHYCR_REGAD(regnum) |
877 FTGMAC100_PHYCR_MIIRD;
879 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
881 for (i = 0; i < 10; i++) {
882 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
884 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
887 data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
888 return FTGMAC100_PHYDATA_MIIRDATA(data);
894 netdev_err(netdev, "mdio read timed out\n");
898 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
899 int regnum, u16 value)
901 struct net_device *netdev = bus->priv;
902 struct ftgmac100 *priv = netdev_priv(netdev);
907 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
909 /* preserve MDC cycle threshold */
910 phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
912 phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
913 FTGMAC100_PHYCR_REGAD(regnum) |
914 FTGMAC100_PHYCR_MIIWR;
916 data = FTGMAC100_PHYDATA_MIIWDATA(value);
918 iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
919 iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
921 for (i = 0; i < 10; i++) {
922 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
924 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
930 netdev_err(netdev, "mdio write timed out\n");
934 static void ftgmac100_get_drvinfo(struct net_device *netdev,
935 struct ethtool_drvinfo *info)
937 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
938 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
939 strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
942 static const struct ethtool_ops ftgmac100_ethtool_ops = {
943 .get_drvinfo = ftgmac100_get_drvinfo,
944 .get_link = ethtool_op_get_link,
945 .get_link_ksettings = phy_ethtool_get_link_ksettings,
946 .set_link_ksettings = phy_ethtool_set_link_ksettings,
949 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
951 struct net_device *netdev = dev_id;
952 struct ftgmac100 *priv = netdev_priv(netdev);
953 unsigned int status, new_mask = FTGMAC100_INT_BAD;
955 /* Fetch and clear interrupt bits, process abnormal ones */
956 status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
957 iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
958 if (unlikely(status & FTGMAC100_INT_BAD)) {
960 /* RX buffer unavailable */
961 if (status & FTGMAC100_INT_NO_RXBUF)
962 netdev->stats.rx_over_errors++;
964 /* received packet lost due to RX FIFO full */
965 if (status & FTGMAC100_INT_RPKT_LOST)
966 netdev->stats.rx_fifo_errors++;
968 /* sent packet lost due to excessive TX collision */
969 if (status & FTGMAC100_INT_XPKT_LOST)
970 netdev->stats.tx_fifo_errors++;
972 /* AHB error -> Reset the chip */
973 if (status & FTGMAC100_INT_AHB_ERR) {
976 "AHB bus error ! Resetting chip.\n");
977 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
978 schedule_work(&priv->reset_task);
982 /* We may need to restart the MAC after such errors, delay
983 * this until after we have freed some Rx buffers though
985 priv->need_mac_restart = true;
987 /* Disable those errors until we restart */
991 /* Only enable "bad" interrupts while NAPI is on */
992 iowrite32(new_mask, priv->base + FTGMAC100_OFFSET_IER);
994 /* Schedule NAPI bh */
995 napi_schedule_irqoff(&priv->napi);
1000 static bool ftgmac100_check_rx(struct ftgmac100 *priv)
1002 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[priv->rx_pointer];
1004 /* Do we have a packet ? */
1005 return !!(rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY));
1008 static int ftgmac100_poll(struct napi_struct *napi, int budget)
1010 struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
1011 bool more, completed = true;
1014 ftgmac100_tx_complete(priv);
1017 more = ftgmac100_rx_packet(priv, &rx);
1018 } while (more && rx < budget);
1020 if (more && rx == budget)
1024 /* The interrupt is telling us to kick the MAC back to life
1025 * after an RX overflow
1027 if (unlikely(priv->need_mac_restart)) {
1028 ftgmac100_start_hw(priv);
1030 /* Re-enable "bad" interrupts */
1031 iowrite32(FTGMAC100_INT_BAD,
1032 priv->base + FTGMAC100_OFFSET_IER);
1035 /* Keep NAPI going if we have still packets to reclaim */
1036 if (priv->tx_pending)
1040 /* We are about to re-enable all interrupts. However
1041 * the HW has been latching RX/TX packet interrupts while
1042 * they were masked. So we clear them first, then we need
1043 * to re-check if there's something to process
1045 iowrite32(FTGMAC100_INT_RXTX,
1046 priv->base + FTGMAC100_OFFSET_ISR);
1047 if (ftgmac100_check_rx(priv) || priv->tx_pending)
1050 /* deschedule NAPI */
1051 napi_complete(napi);
1053 /* enable all interrupts */
1054 iowrite32(FTGMAC100_INT_ALL,
1055 priv->base + FTGMAC100_OFFSET_IER);
1061 static int ftgmac100_init_all(struct ftgmac100 *priv, bool ignore_alloc_err)
1065 /* Re-init descriptors (adjust queue sizes) */
1066 ftgmac100_init_rings(priv);
1068 /* Realloc rx descriptors */
1069 err = ftgmac100_alloc_rx_buffers(priv);
1070 if (err && !ignore_alloc_err)
1073 /* Reinit and restart HW */
1074 ftgmac100_init_hw(priv);
1075 ftgmac100_start_hw(priv);
1077 /* Re-enable the device */
1078 napi_enable(&priv->napi);
1079 netif_start_queue(priv->netdev);
1081 /* Enable all interrupts */
1082 iowrite32(FTGMAC100_INT_ALL, priv->base + FTGMAC100_OFFSET_IER);
1087 static void ftgmac100_reset_task(struct work_struct *work)
1089 struct ftgmac100 *priv = container_of(work, struct ftgmac100,
1091 struct net_device *netdev = priv->netdev;
1094 netdev_dbg(netdev, "Resetting NIC...\n");
1096 /* Lock the world */
1099 mutex_lock(&netdev->phydev->lock);
1101 mutex_lock(&priv->mii_bus->mdio_lock);
1104 /* Check if the interface is still up */
1105 if (!netif_running(netdev))
1108 /* Stop the network stack */
1109 netif_trans_update(netdev);
1110 napi_disable(&priv->napi);
1111 netif_tx_disable(netdev);
1113 /* Stop and reset the MAC */
1114 ftgmac100_stop_hw(priv);
1115 err = ftgmac100_reset_and_config_mac(priv);
1117 /* Not much we can do ... it might come back... */
1118 netdev_err(netdev, "attempting to continue...\n");
1121 /* Free all rx and tx buffers */
1122 ftgmac100_free_buffers(priv);
1124 /* Setup everything again and restart chip */
1125 ftgmac100_init_all(priv, true);
1127 netdev_dbg(netdev, "Reset done !\n");
1130 mutex_unlock(&priv->mii_bus->mdio_lock);
1132 mutex_unlock(&netdev->phydev->lock);
1136 static int ftgmac100_open(struct net_device *netdev)
1138 struct ftgmac100 *priv = netdev_priv(netdev);
1141 /* Allocate ring buffers */
1142 err = ftgmac100_alloc_rings(priv);
1144 netdev_err(netdev, "Failed to allocate descriptors\n");
1148 /* When using NC-SI we force the speed to 100Mbit/s full duplex,
1150 * Otherwise we leave it set to 0 (no link), the link
1151 * message from the PHY layer will handle setting it up to
1152 * something else if needed.
1154 if (priv->use_ncsi) {
1155 priv->cur_duplex = DUPLEX_FULL;
1156 priv->cur_speed = SPEED_100;
1158 priv->cur_duplex = 0;
1159 priv->cur_speed = 0;
1162 /* Reset the hardware */
1163 err = ftgmac100_reset_and_config_mac(priv);
1167 /* Initialize NAPI */
1168 netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1170 /* Grab our interrupt */
1171 err = request_irq(netdev->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1173 netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
1177 /* Start things up */
1178 err = ftgmac100_init_all(priv, false);
1180 netdev_err(netdev, "Failed to allocate packet buffers\n");
1184 if (netdev->phydev) {
1185 /* If we have a PHY, start polling */
1186 phy_start(netdev->phydev);
1187 } else if (priv->use_ncsi) {
1188 /* If using NC-SI, set our carrier on and start the stack */
1189 netif_carrier_on(netdev);
1191 /* Start the NCSI device */
1192 err = ncsi_start_dev(priv->ndev);
1200 napi_disable(&priv->napi);
1201 netif_stop_queue(netdev);
1203 ftgmac100_free_buffers(priv);
1204 free_irq(netdev->irq, netdev);
1206 netif_napi_del(&priv->napi);
1208 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1209 ftgmac100_free_rings(priv);
1213 static int ftgmac100_stop(struct net_device *netdev)
1215 struct ftgmac100 *priv = netdev_priv(netdev);
1217 /* Note about the reset task: We are called with the rtnl lock
1218 * held, so we are synchronized against the core of the reset
1219 * task. We must not try to synchronously cancel it otherwise
1220 * we can deadlock. But since it will test for netif_running()
1221 * which has already been cleared by the net core, we don't
1222 * anything special to do.
1225 /* disable all interrupts */
1226 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1228 netif_stop_queue(netdev);
1229 napi_disable(&priv->napi);
1230 netif_napi_del(&priv->napi);
1232 phy_stop(netdev->phydev);
1233 else if (priv->use_ncsi)
1234 ncsi_stop_dev(priv->ndev);
1236 ftgmac100_stop_hw(priv);
1237 free_irq(netdev->irq, netdev);
1238 ftgmac100_free_buffers(priv);
1239 ftgmac100_free_rings(priv);
1245 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1247 if (!netdev->phydev)
1250 return phy_mii_ioctl(netdev->phydev, ifr, cmd);
1253 static void ftgmac100_tx_timeout(struct net_device *netdev)
1255 struct ftgmac100 *priv = netdev_priv(netdev);
1257 /* Disable all interrupts */
1258 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1260 /* Do the reset outside of interrupt context */
1261 schedule_work(&priv->reset_task);
1264 static const struct net_device_ops ftgmac100_netdev_ops = {
1265 .ndo_open = ftgmac100_open,
1266 .ndo_stop = ftgmac100_stop,
1267 .ndo_start_xmit = ftgmac100_hard_start_xmit,
1268 .ndo_set_mac_address = ftgmac100_set_mac_addr,
1269 .ndo_validate_addr = eth_validate_addr,
1270 .ndo_do_ioctl = ftgmac100_do_ioctl,
1271 .ndo_tx_timeout = ftgmac100_tx_timeout,
1274 static int ftgmac100_setup_mdio(struct net_device *netdev)
1276 struct ftgmac100 *priv = netdev_priv(netdev);
1277 struct platform_device *pdev = to_platform_device(priv->dev);
1281 /* initialize mdio bus */
1282 priv->mii_bus = mdiobus_alloc();
1286 if (of_machine_is_compatible("aspeed,ast2400") ||
1287 of_machine_is_compatible("aspeed,ast2500")) {
1288 /* This driver supports the old MDIO interface */
1289 reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR);
1290 reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
1291 iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR);
1294 priv->mii_bus->name = "ftgmac100_mdio";
1295 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1296 pdev->name, pdev->id);
1297 priv->mii_bus->priv = priv->netdev;
1298 priv->mii_bus->read = ftgmac100_mdiobus_read;
1299 priv->mii_bus->write = ftgmac100_mdiobus_write;
1301 for (i = 0; i < PHY_MAX_ADDR; i++)
1302 priv->mii_bus->irq[i] = PHY_POLL;
1304 err = mdiobus_register(priv->mii_bus);
1306 dev_err(priv->dev, "Cannot register MDIO bus!\n");
1307 goto err_register_mdiobus;
1310 err = ftgmac100_mii_probe(priv);
1312 dev_err(priv->dev, "MII Probe failed!\n");
1319 mdiobus_unregister(priv->mii_bus);
1320 err_register_mdiobus:
1321 mdiobus_free(priv->mii_bus);
1325 static void ftgmac100_destroy_mdio(struct net_device *netdev)
1327 struct ftgmac100 *priv = netdev_priv(netdev);
1329 if (!netdev->phydev)
1332 phy_disconnect(netdev->phydev);
1333 mdiobus_unregister(priv->mii_bus);
1334 mdiobus_free(priv->mii_bus);
1337 static void ftgmac100_ncsi_handler(struct ncsi_dev *nd)
1339 if (unlikely(nd->state != ncsi_dev_state_functional))
1342 netdev_info(nd->dev, "NCSI interface %s\n",
1343 nd->link_up ? "up" : "down");
1346 static int ftgmac100_probe(struct platform_device *pdev)
1348 struct resource *res;
1350 struct net_device *netdev;
1351 struct ftgmac100 *priv;
1357 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1361 irq = platform_get_irq(pdev, 0);
1365 /* setup net_device */
1366 netdev = alloc_etherdev(sizeof(*priv));
1369 goto err_alloc_etherdev;
1372 SET_NETDEV_DEV(netdev, &pdev->dev);
1374 netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1375 netdev->netdev_ops = &ftgmac100_netdev_ops;
1376 netdev->watchdog_timeo = 5 * HZ;
1378 platform_set_drvdata(pdev, netdev);
1380 /* setup private data */
1381 priv = netdev_priv(netdev);
1382 priv->netdev = netdev;
1383 priv->dev = &pdev->dev;
1384 INIT_WORK(&priv->reset_task, ftgmac100_reset_task);
1386 spin_lock_init(&priv->tx_lock);
1389 priv->res = request_mem_region(res->start, resource_size(res),
1390 dev_name(&pdev->dev));
1392 dev_err(&pdev->dev, "Could not reserve memory region\n");
1397 priv->base = ioremap(res->start, resource_size(res));
1399 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1406 /* MAC address from chip or random one */
1407 ftgmac100_setup_mac(priv);
1409 if (of_machine_is_compatible("aspeed,ast2400") ||
1410 of_machine_is_compatible("aspeed,ast2500")) {
1411 priv->rxdes0_edorr_mask = BIT(30);
1412 priv->txdes0_edotr_mask = BIT(30);
1414 priv->rxdes0_edorr_mask = BIT(15);
1415 priv->txdes0_edotr_mask = BIT(15);
1418 if (pdev->dev.of_node &&
1419 of_get_property(pdev->dev.of_node, "use-ncsi", NULL)) {
1420 if (!IS_ENABLED(CONFIG_NET_NCSI)) {
1421 dev_err(&pdev->dev, "NCSI stack not enabled\n");
1425 dev_info(&pdev->dev, "Using NCSI interface\n");
1426 priv->use_ncsi = true;
1427 priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler);
1431 priv->use_ncsi = false;
1432 err = ftgmac100_setup_mdio(netdev);
1434 goto err_setup_mdio;
1437 /* We have to disable on-chip IP checksum functionality
1438 * when NCSI is enabled on the interface. It doesn't work
1441 netdev->features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_GRO;
1442 if (priv->use_ncsi &&
1443 of_get_property(pdev->dev.of_node, "no-hw-checksum", NULL))
1444 netdev->features &= ~NETIF_F_IP_CSUM;
1447 /* register network device */
1448 err = register_netdev(netdev);
1450 dev_err(&pdev->dev, "Failed to register netdev\n");
1451 goto err_register_netdev;
1454 netdev_info(netdev, "irq %d, mapped at %p\n", netdev->irq, priv->base);
1459 err_register_netdev:
1460 ftgmac100_destroy_mdio(netdev);
1462 iounmap(priv->base);
1464 release_resource(priv->res);
1466 netif_napi_del(&priv->napi);
1467 free_netdev(netdev);
1472 static int ftgmac100_remove(struct platform_device *pdev)
1474 struct net_device *netdev;
1475 struct ftgmac100 *priv;
1477 netdev = platform_get_drvdata(pdev);
1478 priv = netdev_priv(netdev);
1480 unregister_netdev(netdev);
1482 /* There's a small chance the reset task will have been re-queued,
1483 * during stop, make sure it's gone before we free the structure.
1485 cancel_work_sync(&priv->reset_task);
1487 ftgmac100_destroy_mdio(netdev);
1489 iounmap(priv->base);
1490 release_resource(priv->res);
1492 netif_napi_del(&priv->napi);
1493 free_netdev(netdev);
1497 static const struct of_device_id ftgmac100_of_match[] = {
1498 { .compatible = "faraday,ftgmac100" },
1501 MODULE_DEVICE_TABLE(of, ftgmac100_of_match);
1503 static struct platform_driver ftgmac100_driver = {
1504 .probe = ftgmac100_probe,
1505 .remove = ftgmac100_remove,
1508 .of_match_table = ftgmac100_of_match,
1511 module_platform_driver(ftgmac100_driver);
1513 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1514 MODULE_DESCRIPTION("FTGMAC100 driver");
1515 MODULE_LICENSE("GPL");