2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_net.h>
56 #include <linux/regulator/consumer.h>
57 #include <linux/if_vlan.h>
59 #include <asm/cacheflush.h>
63 static void set_multicast_list(struct net_device *ndev);
65 #if defined(CONFIG_ARM)
66 #define FEC_ALIGNMENT 0xf
68 #define FEC_ALIGNMENT 0x3
71 #define DRIVER_NAME "fec"
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
81 /* Controller is ENET-MAC */
82 #define FEC_QUIRK_ENET_MAC (1 << 0)
83 /* Controller needs driver to swap frame */
84 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
85 /* Controller uses gasket */
86 #define FEC_QUIRK_USE_GASKET (1 << 2)
87 /* Controller has GBIT support */
88 #define FEC_QUIRK_HAS_GBIT (1 << 3)
89 /* Controller has extend desc buffer */
90 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
91 /* Controller has hardware checksum support */
92 #define FEC_QUIRK_HAS_CSUM (1 << 5)
93 /* Controller has hardware vlan support */
94 #define FEC_QUIRK_HAS_VLAN (1 << 6)
95 /* ENET IP errata ERR006358
97 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
98 * detected as not set during a prior frame transmission, then the
99 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
100 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
101 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
102 * detected as not set during a prior frame transmission, then the
103 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
104 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
105 * frames not being transmitted until there is a 0-to-1 transition on
108 #define FEC_QUIRK_ERR006358 (1 << 7)
110 static struct platform_device_id fec_devtype[] = {
112 /* keep it for coldfire */
117 .driver_data = FEC_QUIRK_USE_GASKET,
123 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
126 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
127 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
128 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
130 .name = "mvf600-fec",
131 .driver_data = FEC_QUIRK_ENET_MAC,
136 MODULE_DEVICE_TABLE(platform, fec_devtype);
139 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
140 IMX27_FEC, /* runs on i.mx27/35/51 */
146 static const struct of_device_id fec_dt_ids[] = {
147 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
148 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
149 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
150 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
151 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
154 MODULE_DEVICE_TABLE(of, fec_dt_ids);
156 static unsigned char macaddr[ETH_ALEN];
157 module_param_array(macaddr, byte, NULL, 0);
158 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
160 #if defined(CONFIG_M5272)
162 * Some hardware gets it MAC address out of local flash memory.
163 * if this is non-zero then assume it is the address to get MAC from.
165 #if defined(CONFIG_NETtel)
166 #define FEC_FLASHMAC 0xf0006006
167 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
168 #define FEC_FLASHMAC 0xf0006000
169 #elif defined(CONFIG_CANCam)
170 #define FEC_FLASHMAC 0xf0020000
171 #elif defined (CONFIG_M5272C3)
172 #define FEC_FLASHMAC (0xffe04000 + 4)
173 #elif defined(CONFIG_MOD5272)
174 #define FEC_FLASHMAC 0xffc0406b
176 #define FEC_FLASHMAC 0
178 #endif /* CONFIG_M5272 */
180 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
181 #error "FEC: descriptor ring size constants too large"
184 /* Interrupt events/masks. */
185 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
186 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
187 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
188 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
189 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
190 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
191 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
192 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
193 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
194 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
196 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
197 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
199 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
201 #define PKT_MAXBUF_SIZE 1522
202 #define PKT_MINBUF_SIZE 64
203 #define PKT_MAXBLR_SIZE 1536
205 /* FEC receive acceleration */
206 #define FEC_RACC_IPDIS (1 << 1)
207 #define FEC_RACC_PRODIS (1 << 2)
208 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
211 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
212 * size bits. Other FEC hardware does not, so we need to take that into
213 * account when setting it.
215 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
216 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
217 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
219 #define OPT_FRAME_SIZE 0
222 /* FEC MII MMFR bits definition */
223 #define FEC_MMFR_ST (1 << 30)
224 #define FEC_MMFR_OP_READ (2 << 28)
225 #define FEC_MMFR_OP_WRITE (1 << 28)
226 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
227 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
228 #define FEC_MMFR_TA (2 << 16)
229 #define FEC_MMFR_DATA(v) (v & 0xffff)
231 #define FEC_MII_TIMEOUT 30000 /* us */
233 /* Transmitter timeout */
234 #define TX_TIMEOUT (2 * HZ)
236 #define FEC_PAUSE_FLAG_AUTONEG 0x1
237 #define FEC_PAUSE_FLAG_ENABLE 0x2
241 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
243 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
245 return (struct bufdesc *)(ex + 1);
250 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
252 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
254 return (struct bufdesc *)(ex - 1);
259 static void *swap_buffer(void *bufaddr, int len)
262 unsigned int *buf = bufaddr;
264 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
265 *buf = cpu_to_be32(*buf);
271 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
273 /* Only run for packets requiring a checksum. */
274 if (skb->ip_summed != CHECKSUM_PARTIAL)
277 if (unlikely(skb_cow_head(skb, 0)))
280 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
286 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
288 struct fec_enet_private *fep = netdev_priv(ndev);
289 const struct platform_device_id *id_entry =
290 platform_get_device_id(fep->pdev);
291 struct bufdesc *bdp, *bdp_pre;
293 unsigned short status;
296 /* Fill in a Tx ring entry */
299 status = bdp->cbd_sc;
301 if (status & BD_ENET_TX_READY) {
302 /* Ooops. All transmit buffers are full. Bail out.
303 * This should not happen, since ndev->tbusy should be set.
305 netdev_err(ndev, "tx queue full!\n");
306 return NETDEV_TX_BUSY;
309 /* Protocol checksum off-load for TCP and UDP. */
310 if (fec_enet_clear_csum(skb, ndev)) {
315 /* Clear all of the status flags */
316 status &= ~BD_ENET_TX_STATS;
318 /* Set buffer length and buffer pointer */
320 bdp->cbd_datlen = skb->len;
323 * On some FEC implementations data must be aligned on
324 * 4-byte boundaries. Use bounce buffers to copy data
325 * and get it aligned. Ugh.
328 index = (struct bufdesc_ex *)bdp -
329 (struct bufdesc_ex *)fep->tx_bd_base;
331 index = bdp - fep->tx_bd_base;
333 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
334 memcpy(fep->tx_bounce[index], skb->data, skb->len);
335 bufaddr = fep->tx_bounce[index];
339 * Some design made an incorrect assumption on endian mode of
340 * the system that it's running on. As the result, driver has to
341 * swap every frame going to and coming from the controller.
343 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
344 swap_buffer(bufaddr, skb->len);
346 /* Save skb pointer */
347 fep->tx_skbuff[index] = skb;
349 /* Push the data cache so the CPM does not get stale memory
352 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
353 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
355 /* Send it on its way. Tell FEC it's ready, interrupt when done,
356 * it's the last BD of the frame, and to put the CRC on the end.
358 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
359 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
360 bdp->cbd_sc = status;
362 if (fep->bufdesc_ex) {
364 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
366 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
368 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
369 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
371 ebdp->cbd_esc = BD_ENET_TX_INT;
373 /* Enable protocol checksum flags
374 * We do not bother with the IP Checksum bits as they
375 * are done by the kernel
377 if (skb->ip_summed == CHECKSUM_PARTIAL)
378 ebdp->cbd_esc |= BD_ENET_TX_PINS;
382 bdp_pre = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
383 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
384 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
385 fep->delay_work.trig_tx = true;
386 schedule_delayed_work(&(fep->delay_work.delay_work),
387 msecs_to_jiffies(1));
390 /* If this was the last BD in the ring, start at the beginning again. */
391 if (status & BD_ENET_TX_WRAP)
392 bdp = fep->tx_bd_base;
394 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
398 if (fep->cur_tx == fep->dirty_tx)
399 netif_stop_queue(ndev);
401 /* Trigger transmission start */
402 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
404 skb_tx_timestamp(skb);
409 /* Init RX & TX buffer descriptors
411 static void fec_enet_bd_init(struct net_device *dev)
413 struct fec_enet_private *fep = netdev_priv(dev);
417 /* Initialize the receive buffer descriptors. */
418 bdp = fep->rx_bd_base;
419 for (i = 0; i < RX_RING_SIZE; i++) {
421 /* Initialize the BD for every fragment in the page. */
422 if (bdp->cbd_bufaddr)
423 bdp->cbd_sc = BD_ENET_RX_EMPTY;
426 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
429 /* Set the last buffer to wrap */
430 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
431 bdp->cbd_sc |= BD_SC_WRAP;
433 fep->cur_rx = fep->rx_bd_base;
435 /* ...and the same for transmit */
436 bdp = fep->tx_bd_base;
438 for (i = 0; i < TX_RING_SIZE; i++) {
440 /* Initialize the BD for every fragment in the page. */
442 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
443 dev_kfree_skb_any(fep->tx_skbuff[i]);
444 fep->tx_skbuff[i] = NULL;
446 bdp->cbd_bufaddr = 0;
447 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
450 /* Set the last buffer to wrap */
451 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
452 bdp->cbd_sc |= BD_SC_WRAP;
456 /* This function is called to start or restart the FEC during a link
457 * change. This only happens when switching between half and full
461 fec_restart(struct net_device *ndev, int duplex)
463 struct fec_enet_private *fep = netdev_priv(ndev);
464 const struct platform_device_id *id_entry =
465 platform_get_device_id(fep->pdev);
469 u32 rcntl = OPT_FRAME_SIZE | 0x04;
470 u32 ecntl = 0x2; /* ETHEREN */
472 if (netif_running(ndev)) {
473 netif_device_detach(ndev);
474 napi_disable(&fep->napi);
475 netif_stop_queue(ndev);
476 netif_tx_lock_bh(ndev);
479 /* Whack a reset. We should wait for this. */
480 writel(1, fep->hwp + FEC_ECNTRL);
484 * enet-mac reset will reset mac address registers too,
485 * so need to reconfigure it.
487 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
488 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
489 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
490 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
493 /* Clear any outstanding interrupt. */
494 writel(0xffc00000, fep->hwp + FEC_IEVENT);
496 /* Setup multicast filter. */
497 set_multicast_list(ndev);
499 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
500 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
503 /* Set maximum receive buffer size. */
504 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
506 fec_enet_bd_init(ndev);
508 /* Set receive and transmit descriptor base. */
509 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
511 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
512 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
514 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
515 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
518 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
519 if (fep->tx_skbuff[i]) {
520 dev_kfree_skb_any(fep->tx_skbuff[i]);
521 fep->tx_skbuff[i] = NULL;
525 /* Enable MII mode */
528 writel(0x04, fep->hwp + FEC_X_CNTRL);
532 writel(0x0, fep->hwp + FEC_X_CNTRL);
535 fep->full_duplex = duplex;
538 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
540 #if !defined(CONFIG_M5272)
541 /* set RX checksum */
542 val = readl(fep->hwp + FEC_RACC);
543 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
544 val |= FEC_RACC_OPTIONS;
546 val &= ~FEC_RACC_OPTIONS;
547 writel(val, fep->hwp + FEC_RACC);
551 * The phy interface and speed need to get configured
552 * differently on enet-mac.
554 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
555 /* Enable flow control and length check */
556 rcntl |= 0x40000000 | 0x00000020;
558 /* RGMII, RMII or MII */
559 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
561 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
566 /* 1G, 100M or 10M */
568 if (fep->phy_dev->speed == SPEED_1000)
570 else if (fep->phy_dev->speed == SPEED_100)
576 #ifdef FEC_MIIGSK_ENR
577 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
579 /* disable the gasket and wait */
580 writel(0, fep->hwp + FEC_MIIGSK_ENR);
581 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
585 * configure the gasket:
586 * RMII, 50 MHz, no loopback, no echo
587 * MII, 25 MHz, no loopback, no echo
589 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
590 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
591 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
592 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
593 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
595 /* re-enable the gasket */
596 writel(2, fep->hwp + FEC_MIIGSK_ENR);
601 #if !defined(CONFIG_M5272)
602 /* enable pause frame*/
603 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
604 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
605 fep->phy_dev && fep->phy_dev->pause)) {
606 rcntl |= FEC_ENET_FCE;
608 /* set FIFO threshold parameter to reduce overrun */
609 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
610 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
611 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
612 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
615 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
617 rcntl &= ~FEC_ENET_FCE;
619 #endif /* !defined(CONFIG_M5272) */
621 writel(rcntl, fep->hwp + FEC_R_CNTRL);
623 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
624 /* enable ENET endian swap */
626 /* enable ENET store and forward mode */
627 writel(1 << 8, fep->hwp + FEC_X_WMRK);
634 /* Enable the MIB statistic event counters */
635 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
638 /* And last, enable the transmit and receive processing */
639 writel(ecntl, fep->hwp + FEC_ECNTRL);
640 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
643 fec_ptp_start_cyclecounter(ndev);
645 /* Enable interrupts we wish to service */
646 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
648 if (netif_running(ndev)) {
649 netif_tx_unlock_bh(ndev);
650 netif_wake_queue(ndev);
651 napi_enable(&fep->napi);
652 netif_device_attach(ndev);
657 fec_stop(struct net_device *ndev)
659 struct fec_enet_private *fep = netdev_priv(ndev);
660 const struct platform_device_id *id_entry =
661 platform_get_device_id(fep->pdev);
662 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
664 /* We cannot expect a graceful transmit stop without link !!! */
666 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
668 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
669 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
672 /* Whack a reset. We should wait for this. */
673 writel(1, fep->hwp + FEC_ECNTRL);
675 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
676 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
678 /* We have to keep ENET enabled to have MII interrupt stay working */
679 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
680 writel(2, fep->hwp + FEC_ECNTRL);
681 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
687 fec_timeout(struct net_device *ndev)
689 struct fec_enet_private *fep = netdev_priv(ndev);
691 ndev->stats.tx_errors++;
693 fep->delay_work.timeout = true;
694 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
697 static void fec_enet_work(struct work_struct *work)
699 struct fec_enet_private *fep =
701 struct fec_enet_private,
702 delay_work.delay_work.work);
704 if (fep->delay_work.timeout) {
705 fep->delay_work.timeout = false;
706 fec_restart(fep->netdev, fep->full_duplex);
707 netif_wake_queue(fep->netdev);
710 if (fep->delay_work.trig_tx) {
711 fep->delay_work.trig_tx = false;
712 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
717 fec_enet_tx(struct net_device *ndev)
719 struct fec_enet_private *fep;
721 unsigned short status;
725 fep = netdev_priv(ndev);
728 /* get next bdp of dirty_tx */
729 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
730 bdp = fep->tx_bd_base;
732 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
734 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
736 /* current queue is empty */
737 if (bdp == fep->cur_tx)
741 index = (struct bufdesc_ex *)bdp -
742 (struct bufdesc_ex *)fep->tx_bd_base;
744 index = bdp - fep->tx_bd_base;
746 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
747 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
748 bdp->cbd_bufaddr = 0;
750 skb = fep->tx_skbuff[index];
752 /* Check for errors. */
753 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
754 BD_ENET_TX_RL | BD_ENET_TX_UN |
756 ndev->stats.tx_errors++;
757 if (status & BD_ENET_TX_HB) /* No heartbeat */
758 ndev->stats.tx_heartbeat_errors++;
759 if (status & BD_ENET_TX_LC) /* Late collision */
760 ndev->stats.tx_window_errors++;
761 if (status & BD_ENET_TX_RL) /* Retrans limit */
762 ndev->stats.tx_aborted_errors++;
763 if (status & BD_ENET_TX_UN) /* Underrun */
764 ndev->stats.tx_fifo_errors++;
765 if (status & BD_ENET_TX_CSL) /* Carrier lost */
766 ndev->stats.tx_carrier_errors++;
768 ndev->stats.tx_packets++;
769 ndev->stats.tx_bytes += bdp->cbd_datlen;
772 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
774 struct skb_shared_hwtstamps shhwtstamps;
776 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
778 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
779 spin_lock_irqsave(&fep->tmreg_lock, flags);
780 shhwtstamps.hwtstamp = ns_to_ktime(
781 timecounter_cyc2time(&fep->tc, ebdp->ts));
782 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
783 skb_tstamp_tx(skb, &shhwtstamps);
786 if (status & BD_ENET_TX_READY)
787 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
789 /* Deferred means some collisions occurred during transmit,
790 * but we eventually sent the packet OK.
792 if (status & BD_ENET_TX_DEF)
793 ndev->stats.collisions++;
795 /* Free the sk buffer associated with this last transmit */
796 dev_kfree_skb_any(skb);
797 fep->tx_skbuff[index] = NULL;
801 /* Update pointer to next buffer descriptor to be transmitted */
802 if (status & BD_ENET_TX_WRAP)
803 bdp = fep->tx_bd_base;
805 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
807 /* Since we have freed up a buffer, the ring is no longer full
809 if (fep->dirty_tx != fep->cur_tx) {
810 if (netif_queue_stopped(ndev))
811 netif_wake_queue(ndev);
818 /* During a receive, the cur_rx points to the current incoming buffer.
819 * When we update through the ring, if the next incoming buffer has
820 * not been given to the system, we just set the empty indicator,
821 * effectively tossing the packet.
824 fec_enet_rx(struct net_device *ndev, int budget)
826 struct fec_enet_private *fep = netdev_priv(ndev);
827 const struct platform_device_id *id_entry =
828 platform_get_device_id(fep->pdev);
830 unsigned short status;
834 int pkt_received = 0;
835 struct bufdesc_ex *ebdp = NULL;
836 bool vlan_packet_rcvd = false;
843 /* First, grab all of the stats for the incoming packet.
844 * These get messed up if we get called due to a busy condition.
848 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
850 if (pkt_received >= budget)
854 /* Since we have allocated space to hold a complete frame,
855 * the last indicator should be set.
857 if ((status & BD_ENET_RX_LAST) == 0)
858 netdev_err(ndev, "rcv is not +last\n");
861 goto rx_processing_done;
863 /* Check for errors. */
864 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
865 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
866 ndev->stats.rx_errors++;
867 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
868 /* Frame too long or too short. */
869 ndev->stats.rx_length_errors++;
871 if (status & BD_ENET_RX_NO) /* Frame alignment */
872 ndev->stats.rx_frame_errors++;
873 if (status & BD_ENET_RX_CR) /* CRC Error */
874 ndev->stats.rx_crc_errors++;
875 if (status & BD_ENET_RX_OV) /* FIFO overrun */
876 ndev->stats.rx_fifo_errors++;
879 /* Report late collisions as a frame error.
880 * On this error, the BD is closed, but we don't know what we
881 * have in the buffer. So, just drop this frame on the floor.
883 if (status & BD_ENET_RX_CL) {
884 ndev->stats.rx_errors++;
885 ndev->stats.rx_frame_errors++;
886 goto rx_processing_done;
889 /* Process the incoming frame. */
890 ndev->stats.rx_packets++;
891 pkt_len = bdp->cbd_datlen;
892 ndev->stats.rx_bytes += pkt_len;
893 data = (__u8*)__va(bdp->cbd_bufaddr);
895 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
896 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
898 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
899 swap_buffer(data, pkt_len);
901 /* Extract the enhanced buffer descriptor */
904 ebdp = (struct bufdesc_ex *)bdp;
906 /* If this is a VLAN packet remove the VLAN Tag */
907 vlan_packet_rcvd = false;
908 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
909 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
910 /* Push and remove the vlan tag */
911 struct vlan_hdr *vlan_header =
912 (struct vlan_hdr *) (data + ETH_HLEN);
913 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
914 pkt_len -= VLAN_HLEN;
916 vlan_packet_rcvd = true;
919 /* This does 16 byte alignment, exactly what we need.
920 * The packet length includes FCS, but we don't want to
921 * include that when passing upstream as it messes up
922 * bridging applications.
924 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
926 if (unlikely(!skb)) {
927 ndev->stats.rx_dropped++;
929 int payload_offset = (2 * ETH_ALEN);
930 skb_reserve(skb, NET_IP_ALIGN);
931 skb_put(skb, pkt_len - 4); /* Make room */
933 /* Extract the frame data without the VLAN header. */
934 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
935 if (vlan_packet_rcvd)
936 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
937 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
938 data + payload_offset,
939 pkt_len - 4 - (2 * ETH_ALEN));
941 skb->protocol = eth_type_trans(skb, ndev);
943 /* Get receive timestamp from the skb */
944 if (fep->hwts_rx_en && fep->bufdesc_ex) {
945 struct skb_shared_hwtstamps *shhwtstamps =
949 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
951 spin_lock_irqsave(&fep->tmreg_lock, flags);
952 shhwtstamps->hwtstamp = ns_to_ktime(
953 timecounter_cyc2time(&fep->tc, ebdp->ts));
954 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
957 if (fep->bufdesc_ex &&
958 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
959 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
961 skb->ip_summed = CHECKSUM_UNNECESSARY;
963 skb_checksum_none_assert(skb);
967 /* Handle received VLAN packets */
968 if (vlan_packet_rcvd)
969 __vlan_hwaccel_put_tag(skb,
973 if (!skb_defer_rx_timestamp(skb))
974 napi_gro_receive(&fep->napi, skb);
977 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
978 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
980 /* Clear the status flags for this buffer */
981 status &= ~BD_ENET_RX_STATS;
983 /* Mark the buffer empty */
984 status |= BD_ENET_RX_EMPTY;
985 bdp->cbd_sc = status;
987 if (fep->bufdesc_ex) {
988 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
990 ebdp->cbd_esc = BD_ENET_RX_INT;
995 /* Update BD pointer to next entry */
996 if (status & BD_ENET_RX_WRAP)
997 bdp = fep->rx_bd_base;
999 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1000 /* Doing this here will keep the FEC running while we process
1001 * incoming frames. On a heavily loaded network, we should be
1002 * able to keep up at the expense of system resources.
1004 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1008 return pkt_received;
1012 fec_enet_interrupt(int irq, void *dev_id)
1014 struct net_device *ndev = dev_id;
1015 struct fec_enet_private *fep = netdev_priv(ndev);
1017 irqreturn_t ret = IRQ_NONE;
1020 int_events = readl(fep->hwp + FEC_IEVENT);
1021 writel(int_events, fep->hwp + FEC_IEVENT);
1023 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
1026 /* Disable the RX interrupt */
1027 if (napi_schedule_prep(&fep->napi)) {
1028 writel(FEC_RX_DISABLED_IMASK,
1029 fep->hwp + FEC_IMASK);
1030 __napi_schedule(&fep->napi);
1034 if (int_events & FEC_ENET_MII) {
1036 complete(&fep->mdio_done);
1038 } while (int_events);
1043 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1045 struct net_device *ndev = napi->dev;
1046 int pkts = fec_enet_rx(ndev, budget);
1047 struct fec_enet_private *fep = netdev_priv(ndev);
1051 if (pkts < budget) {
1052 napi_complete(napi);
1053 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1058 /* ------------------------------------------------------------------------- */
1059 static void fec_get_mac(struct net_device *ndev)
1061 struct fec_enet_private *fep = netdev_priv(ndev);
1062 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1063 unsigned char *iap, tmpaddr[ETH_ALEN];
1066 * try to get mac address in following order:
1068 * 1) module parameter via kernel command line in form
1069 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1074 * 2) from device tree data
1076 if (!is_valid_ether_addr(iap)) {
1077 struct device_node *np = fep->pdev->dev.of_node;
1079 const char *mac = of_get_mac_address(np);
1081 iap = (unsigned char *) mac;
1086 * 3) from flash or fuse (via platform data)
1088 if (!is_valid_ether_addr(iap)) {
1091 iap = (unsigned char *)FEC_FLASHMAC;
1094 iap = (unsigned char *)&pdata->mac;
1099 * 4) FEC mac registers set by bootloader
1101 if (!is_valid_ether_addr(iap)) {
1102 *((unsigned long *) &tmpaddr[0]) =
1103 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
1104 *((unsigned short *) &tmpaddr[4]) =
1105 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1110 * 5) random mac address
1112 if (!is_valid_ether_addr(iap)) {
1113 /* Report it and use a random ethernet address instead */
1114 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1115 eth_hw_addr_random(ndev);
1116 netdev_info(ndev, "Using random MAC address: %pM\n",
1121 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1123 /* Adjust MAC if using macaddr */
1125 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1128 /* ------------------------------------------------------------------------- */
1133 static void fec_enet_adjust_link(struct net_device *ndev)
1135 struct fec_enet_private *fep = netdev_priv(ndev);
1136 struct phy_device *phy_dev = fep->phy_dev;
1137 int status_change = 0;
1139 /* Prevent a state halted on mii error */
1140 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1141 phy_dev->state = PHY_RESUMING;
1145 if (phy_dev->link) {
1147 fep->link = phy_dev->link;
1151 if (fep->full_duplex != phy_dev->duplex)
1154 if (phy_dev->speed != fep->speed) {
1155 fep->speed = phy_dev->speed;
1159 /* if any of the above changed restart the FEC */
1161 fec_restart(ndev, phy_dev->duplex);
1165 fep->link = phy_dev->link;
1171 phy_print_status(phy_dev);
1174 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1176 struct fec_enet_private *fep = bus->priv;
1177 unsigned long time_left;
1179 fep->mii_timeout = 0;
1180 init_completion(&fep->mdio_done);
1182 /* start a read op */
1183 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1184 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1185 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1187 /* wait for end of transfer */
1188 time_left = wait_for_completion_timeout(&fep->mdio_done,
1189 usecs_to_jiffies(FEC_MII_TIMEOUT));
1190 if (time_left == 0) {
1191 fep->mii_timeout = 1;
1192 netdev_err(fep->netdev, "MDIO read timeout\n");
1197 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1200 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1203 struct fec_enet_private *fep = bus->priv;
1204 unsigned long time_left;
1206 fep->mii_timeout = 0;
1207 init_completion(&fep->mdio_done);
1209 /* start a write op */
1210 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1211 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1212 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1213 fep->hwp + FEC_MII_DATA);
1215 /* wait for end of transfer */
1216 time_left = wait_for_completion_timeout(&fep->mdio_done,
1217 usecs_to_jiffies(FEC_MII_TIMEOUT));
1218 if (time_left == 0) {
1219 fep->mii_timeout = 1;
1220 netdev_err(fep->netdev, "MDIO write timeout\n");
1227 static int fec_enet_mdio_reset(struct mii_bus *bus)
1232 static int fec_enet_mii_probe(struct net_device *ndev)
1234 struct fec_enet_private *fep = netdev_priv(ndev);
1235 const struct platform_device_id *id_entry =
1236 platform_get_device_id(fep->pdev);
1237 struct phy_device *phy_dev = NULL;
1238 char mdio_bus_id[MII_BUS_ID_SIZE];
1239 char phy_name[MII_BUS_ID_SIZE + 3];
1241 int dev_id = fep->dev_id;
1243 fep->phy_dev = NULL;
1245 /* check for attached phy */
1246 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1247 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1249 if (fep->mii_bus->phy_map[phy_id] == NULL)
1251 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1255 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1259 if (phy_id >= PHY_MAX_ADDR) {
1260 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1261 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1265 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1266 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1267 fep->phy_interface);
1268 if (IS_ERR(phy_dev)) {
1269 netdev_err(ndev, "could not attach to PHY\n");
1270 return PTR_ERR(phy_dev);
1273 /* mask with MAC supported features */
1274 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1275 phy_dev->supported &= PHY_GBIT_FEATURES;
1276 #if !defined(CONFIG_M5272)
1277 phy_dev->supported |= SUPPORTED_Pause;
1281 phy_dev->supported &= PHY_BASIC_FEATURES;
1283 phy_dev->advertising = phy_dev->supported;
1285 fep->phy_dev = phy_dev;
1287 fep->full_duplex = 0;
1289 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1290 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1296 static int fec_enet_mii_init(struct platform_device *pdev)
1298 static struct mii_bus *fec0_mii_bus;
1299 struct net_device *ndev = platform_get_drvdata(pdev);
1300 struct fec_enet_private *fep = netdev_priv(ndev);
1301 const struct platform_device_id *id_entry =
1302 platform_get_device_id(fep->pdev);
1303 int err = -ENXIO, i;
1306 * The dual fec interfaces are not equivalent with enet-mac.
1307 * Here are the differences:
1309 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1310 * - fec0 acts as the 1588 time master while fec1 is slave
1311 * - external phys can only be configured by fec0
1313 * That is to say fec1 can not work independently. It only works
1314 * when fec0 is working. The reason behind this design is that the
1315 * second interface is added primarily for Switch mode.
1317 * Because of the last point above, both phys are attached on fec0
1318 * mdio interface in board design, and need to be configured by
1321 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1322 /* fec1 uses fec0 mii_bus */
1323 if (mii_cnt && fec0_mii_bus) {
1324 fep->mii_bus = fec0_mii_bus;
1331 fep->mii_timeout = 0;
1334 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1336 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1337 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1338 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1341 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1342 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1344 fep->phy_speed <<= 1;
1345 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1347 fep->mii_bus = mdiobus_alloc();
1348 if (fep->mii_bus == NULL) {
1353 fep->mii_bus->name = "fec_enet_mii_bus";
1354 fep->mii_bus->read = fec_enet_mdio_read;
1355 fep->mii_bus->write = fec_enet_mdio_write;
1356 fep->mii_bus->reset = fec_enet_mdio_reset;
1357 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1358 pdev->name, fep->dev_id + 1);
1359 fep->mii_bus->priv = fep;
1360 fep->mii_bus->parent = &pdev->dev;
1362 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1363 if (!fep->mii_bus->irq) {
1365 goto err_out_free_mdiobus;
1368 for (i = 0; i < PHY_MAX_ADDR; i++)
1369 fep->mii_bus->irq[i] = PHY_POLL;
1371 if (mdiobus_register(fep->mii_bus))
1372 goto err_out_free_mdio_irq;
1376 /* save fec0 mii_bus */
1377 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1378 fec0_mii_bus = fep->mii_bus;
1382 err_out_free_mdio_irq:
1383 kfree(fep->mii_bus->irq);
1384 err_out_free_mdiobus:
1385 mdiobus_free(fep->mii_bus);
1390 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1392 if (--mii_cnt == 0) {
1393 mdiobus_unregister(fep->mii_bus);
1394 kfree(fep->mii_bus->irq);
1395 mdiobus_free(fep->mii_bus);
1399 static int fec_enet_get_settings(struct net_device *ndev,
1400 struct ethtool_cmd *cmd)
1402 struct fec_enet_private *fep = netdev_priv(ndev);
1403 struct phy_device *phydev = fep->phy_dev;
1408 return phy_ethtool_gset(phydev, cmd);
1411 static int fec_enet_set_settings(struct net_device *ndev,
1412 struct ethtool_cmd *cmd)
1414 struct fec_enet_private *fep = netdev_priv(ndev);
1415 struct phy_device *phydev = fep->phy_dev;
1420 return phy_ethtool_sset(phydev, cmd);
1423 static void fec_enet_get_drvinfo(struct net_device *ndev,
1424 struct ethtool_drvinfo *info)
1426 struct fec_enet_private *fep = netdev_priv(ndev);
1428 strlcpy(info->driver, fep->pdev->dev.driver->name,
1429 sizeof(info->driver));
1430 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1431 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1434 static int fec_enet_get_ts_info(struct net_device *ndev,
1435 struct ethtool_ts_info *info)
1437 struct fec_enet_private *fep = netdev_priv(ndev);
1439 if (fep->bufdesc_ex) {
1441 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1442 SOF_TIMESTAMPING_RX_SOFTWARE |
1443 SOF_TIMESTAMPING_SOFTWARE |
1444 SOF_TIMESTAMPING_TX_HARDWARE |
1445 SOF_TIMESTAMPING_RX_HARDWARE |
1446 SOF_TIMESTAMPING_RAW_HARDWARE;
1448 info->phc_index = ptp_clock_index(fep->ptp_clock);
1450 info->phc_index = -1;
1452 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1453 (1 << HWTSTAMP_TX_ON);
1455 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1456 (1 << HWTSTAMP_FILTER_ALL);
1459 return ethtool_op_get_ts_info(ndev, info);
1463 #if !defined(CONFIG_M5272)
1465 static void fec_enet_get_pauseparam(struct net_device *ndev,
1466 struct ethtool_pauseparam *pause)
1468 struct fec_enet_private *fep = netdev_priv(ndev);
1470 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1471 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1472 pause->rx_pause = pause->tx_pause;
1475 static int fec_enet_set_pauseparam(struct net_device *ndev,
1476 struct ethtool_pauseparam *pause)
1478 struct fec_enet_private *fep = netdev_priv(ndev);
1480 if (pause->tx_pause != pause->rx_pause) {
1482 "hardware only support enable/disable both tx and rx");
1486 fep->pause_flag = 0;
1488 /* tx pause must be same as rx pause */
1489 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1490 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1492 if (pause->rx_pause || pause->autoneg) {
1493 fep->phy_dev->supported |= ADVERTISED_Pause;
1494 fep->phy_dev->advertising |= ADVERTISED_Pause;
1496 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1497 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1500 if (pause->autoneg) {
1501 if (netif_running(ndev))
1503 phy_start_aneg(fep->phy_dev);
1505 if (netif_running(ndev))
1506 fec_restart(ndev, 0);
1511 static const struct fec_stat {
1512 char name[ETH_GSTRING_LEN];
1516 { "tx_dropped", RMON_T_DROP },
1517 { "tx_packets", RMON_T_PACKETS },
1518 { "tx_broadcast", RMON_T_BC_PKT },
1519 { "tx_multicast", RMON_T_MC_PKT },
1520 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1521 { "tx_undersize", RMON_T_UNDERSIZE },
1522 { "tx_oversize", RMON_T_OVERSIZE },
1523 { "tx_fragment", RMON_T_FRAG },
1524 { "tx_jabber", RMON_T_JAB },
1525 { "tx_collision", RMON_T_COL },
1526 { "tx_64byte", RMON_T_P64 },
1527 { "tx_65to127byte", RMON_T_P65TO127 },
1528 { "tx_128to255byte", RMON_T_P128TO255 },
1529 { "tx_256to511byte", RMON_T_P256TO511 },
1530 { "tx_512to1023byte", RMON_T_P512TO1023 },
1531 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1532 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1533 { "tx_octets", RMON_T_OCTETS },
1536 { "IEEE_tx_drop", IEEE_T_DROP },
1537 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1538 { "IEEE_tx_1col", IEEE_T_1COL },
1539 { "IEEE_tx_mcol", IEEE_T_MCOL },
1540 { "IEEE_tx_def", IEEE_T_DEF },
1541 { "IEEE_tx_lcol", IEEE_T_LCOL },
1542 { "IEEE_tx_excol", IEEE_T_EXCOL },
1543 { "IEEE_tx_macerr", IEEE_T_MACERR },
1544 { "IEEE_tx_cserr", IEEE_T_CSERR },
1545 { "IEEE_tx_sqe", IEEE_T_SQE },
1546 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1547 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1550 { "rx_packets", RMON_R_PACKETS },
1551 { "rx_broadcast", RMON_R_BC_PKT },
1552 { "rx_multicast", RMON_R_MC_PKT },
1553 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1554 { "rx_undersize", RMON_R_UNDERSIZE },
1555 { "rx_oversize", RMON_R_OVERSIZE },
1556 { "rx_fragment", RMON_R_FRAG },
1557 { "rx_jabber", RMON_R_JAB },
1558 { "rx_64byte", RMON_R_P64 },
1559 { "rx_65to127byte", RMON_R_P65TO127 },
1560 { "rx_128to255byte", RMON_R_P128TO255 },
1561 { "rx_256to511byte", RMON_R_P256TO511 },
1562 { "rx_512to1023byte", RMON_R_P512TO1023 },
1563 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1564 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1565 { "rx_octets", RMON_R_OCTETS },
1568 { "IEEE_rx_drop", IEEE_R_DROP },
1569 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1570 { "IEEE_rx_crc", IEEE_R_CRC },
1571 { "IEEE_rx_align", IEEE_R_ALIGN },
1572 { "IEEE_rx_macerr", IEEE_R_MACERR },
1573 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1574 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1577 static void fec_enet_get_ethtool_stats(struct net_device *dev,
1578 struct ethtool_stats *stats, u64 *data)
1580 struct fec_enet_private *fep = netdev_priv(dev);
1583 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1584 data[i] = readl(fep->hwp + fec_stats[i].offset);
1587 static void fec_enet_get_strings(struct net_device *netdev,
1588 u32 stringset, u8 *data)
1591 switch (stringset) {
1593 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1594 memcpy(data + i * ETH_GSTRING_LEN,
1595 fec_stats[i].name, ETH_GSTRING_LEN);
1600 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
1604 return ARRAY_SIZE(fec_stats);
1609 #endif /* !defined(CONFIG_M5272) */
1611 static int fec_enet_nway_reset(struct net_device *dev)
1613 struct fec_enet_private *fep = netdev_priv(dev);
1614 struct phy_device *phydev = fep->phy_dev;
1619 return genphy_restart_aneg(phydev);
1622 static const struct ethtool_ops fec_enet_ethtool_ops = {
1623 #if !defined(CONFIG_M5272)
1624 .get_pauseparam = fec_enet_get_pauseparam,
1625 .set_pauseparam = fec_enet_set_pauseparam,
1627 .get_settings = fec_enet_get_settings,
1628 .set_settings = fec_enet_set_settings,
1629 .get_drvinfo = fec_enet_get_drvinfo,
1630 .get_link = ethtool_op_get_link,
1631 .get_ts_info = fec_enet_get_ts_info,
1632 .nway_reset = fec_enet_nway_reset,
1633 #ifndef CONFIG_M5272
1634 .get_ethtool_stats = fec_enet_get_ethtool_stats,
1635 .get_strings = fec_enet_get_strings,
1636 .get_sset_count = fec_enet_get_sset_count,
1640 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1642 struct fec_enet_private *fep = netdev_priv(ndev);
1643 struct phy_device *phydev = fep->phy_dev;
1645 if (!netif_running(ndev))
1651 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1652 return fec_ptp_ioctl(ndev, rq, cmd);
1654 return phy_mii_ioctl(phydev, rq, cmd);
1657 static void fec_enet_free_buffers(struct net_device *ndev)
1659 struct fec_enet_private *fep = netdev_priv(ndev);
1661 struct sk_buff *skb;
1662 struct bufdesc *bdp;
1664 bdp = fep->rx_bd_base;
1665 for (i = 0; i < RX_RING_SIZE; i++) {
1666 skb = fep->rx_skbuff[i];
1668 if (bdp->cbd_bufaddr)
1669 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1670 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1673 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1676 bdp = fep->tx_bd_base;
1677 for (i = 0; i < TX_RING_SIZE; i++)
1678 kfree(fep->tx_bounce[i]);
1681 static int fec_enet_alloc_buffers(struct net_device *ndev)
1683 struct fec_enet_private *fep = netdev_priv(ndev);
1685 struct sk_buff *skb;
1686 struct bufdesc *bdp;
1688 bdp = fep->rx_bd_base;
1689 for (i = 0; i < RX_RING_SIZE; i++) {
1690 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1692 fec_enet_free_buffers(ndev);
1695 fep->rx_skbuff[i] = skb;
1697 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1698 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1699 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1701 if (fep->bufdesc_ex) {
1702 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1703 ebdp->cbd_esc = BD_ENET_RX_INT;
1706 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1709 /* Set the last buffer to wrap. */
1710 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1711 bdp->cbd_sc |= BD_SC_WRAP;
1713 bdp = fep->tx_bd_base;
1714 for (i = 0; i < TX_RING_SIZE; i++) {
1715 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1718 bdp->cbd_bufaddr = 0;
1720 if (fep->bufdesc_ex) {
1721 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1722 ebdp->cbd_esc = BD_ENET_TX_INT;
1725 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1728 /* Set the last buffer to wrap. */
1729 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1730 bdp->cbd_sc |= BD_SC_WRAP;
1736 fec_enet_open(struct net_device *ndev)
1738 struct fec_enet_private *fep = netdev_priv(ndev);
1741 napi_enable(&fep->napi);
1743 /* I should reset the ring buffers here, but I don't yet know
1744 * a simple way to do that.
1747 ret = fec_enet_alloc_buffers(ndev);
1751 /* Probe and connect to PHY when open the interface */
1752 ret = fec_enet_mii_probe(ndev);
1754 fec_enet_free_buffers(ndev);
1757 phy_start(fep->phy_dev);
1758 netif_start_queue(ndev);
1764 fec_enet_close(struct net_device *ndev)
1766 struct fec_enet_private *fep = netdev_priv(ndev);
1768 /* Don't know what to do yet. */
1769 napi_disable(&fep->napi);
1771 netif_stop_queue(ndev);
1775 phy_stop(fep->phy_dev);
1776 phy_disconnect(fep->phy_dev);
1779 fec_enet_free_buffers(ndev);
1784 /* Set or clear the multicast filter for this adaptor.
1785 * Skeleton taken from sunlance driver.
1786 * The CPM Ethernet implementation allows Multicast as well as individual
1787 * MAC address filtering. Some of the drivers check to make sure it is
1788 * a group multicast address, and discard those that are not. I guess I
1789 * will do the same for now, but just remove the test if you want
1790 * individual filtering as well (do the upper net layers want or support
1791 * this kind of feature?).
1794 #define HASH_BITS 6 /* #bits in hash */
1795 #define CRC32_POLY 0xEDB88320
1797 static void set_multicast_list(struct net_device *ndev)
1799 struct fec_enet_private *fep = netdev_priv(ndev);
1800 struct netdev_hw_addr *ha;
1801 unsigned int i, bit, data, crc, tmp;
1804 if (ndev->flags & IFF_PROMISC) {
1805 tmp = readl(fep->hwp + FEC_R_CNTRL);
1807 writel(tmp, fep->hwp + FEC_R_CNTRL);
1811 tmp = readl(fep->hwp + FEC_R_CNTRL);
1813 writel(tmp, fep->hwp + FEC_R_CNTRL);
1815 if (ndev->flags & IFF_ALLMULTI) {
1816 /* Catch all multicast addresses, so set the
1819 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1820 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1825 /* Clear filter and add the addresses in hash register
1827 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1828 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1830 netdev_for_each_mc_addr(ha, ndev) {
1831 /* calculate crc32 value of mac address */
1834 for (i = 0; i < ndev->addr_len; i++) {
1836 for (bit = 0; bit < 8; bit++, data >>= 1) {
1838 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1842 /* only upper 6 bits (HASH_BITS) are used
1843 * which point to specific bit in he hash registers
1845 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1848 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1849 tmp |= 1 << (hash - 32);
1850 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1852 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1854 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1859 /* Set a MAC change in hardware. */
1861 fec_set_mac_address(struct net_device *ndev, void *p)
1863 struct fec_enet_private *fep = netdev_priv(ndev);
1864 struct sockaddr *addr = p;
1866 if (!is_valid_ether_addr(addr->sa_data))
1867 return -EADDRNOTAVAIL;
1869 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1871 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1872 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1873 fep->hwp + FEC_ADDR_LOW);
1874 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1875 fep->hwp + FEC_ADDR_HIGH);
1879 #ifdef CONFIG_NET_POLL_CONTROLLER
1881 * fec_poll_controller - FEC Poll controller function
1882 * @dev: The FEC network adapter
1884 * Polled functionality used by netconsole and others in non interrupt mode
1887 static void fec_poll_controller(struct net_device *dev)
1890 struct fec_enet_private *fep = netdev_priv(dev);
1892 for (i = 0; i < FEC_IRQ_NUM; i++) {
1893 if (fep->irq[i] > 0) {
1894 disable_irq(fep->irq[i]);
1895 fec_enet_interrupt(fep->irq[i], dev);
1896 enable_irq(fep->irq[i]);
1902 static int fec_set_features(struct net_device *netdev,
1903 netdev_features_t features)
1905 struct fec_enet_private *fep = netdev_priv(netdev);
1906 netdev_features_t changed = features ^ netdev->features;
1908 netdev->features = features;
1910 /* Receive checksum has been changed */
1911 if (changed & NETIF_F_RXCSUM) {
1912 if (features & NETIF_F_RXCSUM)
1913 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1915 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
1917 if (netif_running(netdev)) {
1919 fec_restart(netdev, fep->phy_dev->duplex);
1920 netif_wake_queue(netdev);
1922 fec_restart(netdev, fep->phy_dev->duplex);
1929 static const struct net_device_ops fec_netdev_ops = {
1930 .ndo_open = fec_enet_open,
1931 .ndo_stop = fec_enet_close,
1932 .ndo_start_xmit = fec_enet_start_xmit,
1933 .ndo_set_rx_mode = set_multicast_list,
1934 .ndo_change_mtu = eth_change_mtu,
1935 .ndo_validate_addr = eth_validate_addr,
1936 .ndo_tx_timeout = fec_timeout,
1937 .ndo_set_mac_address = fec_set_mac_address,
1938 .ndo_do_ioctl = fec_enet_ioctl,
1939 #ifdef CONFIG_NET_POLL_CONTROLLER
1940 .ndo_poll_controller = fec_poll_controller,
1942 .ndo_set_features = fec_set_features,
1946 * XXX: We need to clean up on failure exits here.
1949 static int fec_enet_init(struct net_device *ndev)
1951 struct fec_enet_private *fep = netdev_priv(ndev);
1952 const struct platform_device_id *id_entry =
1953 platform_get_device_id(fep->pdev);
1954 struct bufdesc *cbd_base;
1956 /* Allocate memory for buffer descriptors. */
1957 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1962 memset(cbd_base, 0, PAGE_SIZE);
1966 /* Get the Ethernet address */
1969 /* Set receive and transmit descriptor base. */
1970 fep->rx_bd_base = cbd_base;
1971 if (fep->bufdesc_ex)
1972 fep->tx_bd_base = (struct bufdesc *)
1973 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
1975 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1977 /* The FEC Ethernet specific entries in the device structure */
1978 ndev->watchdog_timeo = TX_TIMEOUT;
1979 ndev->netdev_ops = &fec_netdev_ops;
1980 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1982 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
1983 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
1985 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) {
1986 /* enable hw VLAN support */
1987 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1988 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1991 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
1992 /* enable hw accelerator */
1993 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
1995 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
1997 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2000 fec_restart(ndev, 0);
2006 static void fec_reset_phy(struct platform_device *pdev)
2010 struct device_node *np = pdev->dev.of_node;
2015 of_property_read_u32(np, "phy-reset-duration", &msec);
2016 /* A sane reset duration should not be longer than 1s */
2020 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
2021 if (!gpio_is_valid(phy_reset))
2024 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2025 GPIOF_OUT_INIT_LOW, "phy-reset");
2027 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
2031 gpio_set_value(phy_reset, 1);
2033 #else /* CONFIG_OF */
2034 static void fec_reset_phy(struct platform_device *pdev)
2037 * In case of platform probe, the reset has been done
2041 #endif /* CONFIG_OF */
2044 fec_probe(struct platform_device *pdev)
2046 struct fec_enet_private *fep;
2047 struct fec_platform_data *pdata;
2048 struct net_device *ndev;
2049 int i, irq, ret = 0;
2051 const struct of_device_id *of_id;
2054 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2056 pdev->id_entry = of_id->data;
2058 /* Init network device */
2059 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
2063 SET_NETDEV_DEV(ndev, &pdev->dev);
2065 /* setup board info structure */
2066 fep = netdev_priv(ndev);
2068 #if !defined(CONFIG_M5272)
2069 /* default enable pause frame auto negotiation */
2070 if (pdev->id_entry &&
2071 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2072 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
2075 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2076 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2077 if (IS_ERR(fep->hwp)) {
2078 ret = PTR_ERR(fep->hwp);
2079 goto failed_ioremap;
2083 fep->dev_id = dev_id++;
2085 fep->bufdesc_ex = 0;
2087 platform_set_drvdata(pdev, ndev);
2089 ret = of_get_phy_mode(pdev->dev.of_node);
2091 pdata = dev_get_platdata(&pdev->dev);
2093 fep->phy_interface = pdata->phy;
2095 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2097 fep->phy_interface = ret;
2100 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2101 if (IS_ERR(fep->clk_ipg)) {
2102 ret = PTR_ERR(fep->clk_ipg);
2106 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2107 if (IS_ERR(fep->clk_ahb)) {
2108 ret = PTR_ERR(fep->clk_ahb);
2112 /* enet_out is optional, depends on board */
2113 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2114 if (IS_ERR(fep->clk_enet_out))
2115 fep->clk_enet_out = NULL;
2117 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
2119 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
2120 if (IS_ERR(fep->clk_ptp)) {
2121 fep->clk_ptp = NULL;
2122 fep->bufdesc_ex = 0;
2125 ret = clk_prepare_enable(fep->clk_ahb);
2129 ret = clk_prepare_enable(fep->clk_ipg);
2131 goto failed_clk_ipg;
2133 if (fep->clk_enet_out) {
2134 ret = clk_prepare_enable(fep->clk_enet_out);
2136 goto failed_clk_enet_out;
2140 ret = clk_prepare_enable(fep->clk_ptp);
2142 goto failed_clk_ptp;
2145 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2146 if (!IS_ERR(fep->reg_phy)) {
2147 ret = regulator_enable(fep->reg_phy);
2150 "Failed to enable phy regulator: %d\n", ret);
2151 goto failed_regulator;
2154 fep->reg_phy = NULL;
2157 fec_reset_phy(pdev);
2159 if (fep->bufdesc_ex)
2162 ret = fec_enet_init(ndev);
2166 for (i = 0; i < FEC_IRQ_NUM; i++) {
2167 irq = platform_get_irq(pdev, i);
2174 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
2175 IRQF_DISABLED, pdev->name, ndev);
2180 ret = fec_enet_mii_init(pdev);
2182 goto failed_mii_init;
2184 /* Carrier starts down, phylib will bring it up */
2185 netif_carrier_off(ndev);
2187 ret = register_netdev(ndev);
2189 goto failed_register;
2191 if (fep->bufdesc_ex && fep->ptp_clock)
2192 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2194 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2198 fec_enet_mii_remove(fep);
2203 regulator_disable(fep->reg_phy);
2206 clk_disable_unprepare(fep->clk_ptp);
2208 if (fep->clk_enet_out)
2209 clk_disable_unprepare(fep->clk_enet_out);
2210 failed_clk_enet_out:
2211 clk_disable_unprepare(fep->clk_ipg);
2213 clk_disable_unprepare(fep->clk_ahb);
2222 fec_drv_remove(struct platform_device *pdev)
2224 struct net_device *ndev = platform_get_drvdata(pdev);
2225 struct fec_enet_private *fep = netdev_priv(ndev);
2227 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2228 unregister_netdev(ndev);
2229 fec_enet_mii_remove(fep);
2230 del_timer_sync(&fep->time_keep);
2232 regulator_disable(fep->reg_phy);
2234 clk_disable_unprepare(fep->clk_ptp);
2236 ptp_clock_unregister(fep->ptp_clock);
2237 if (fep->clk_enet_out)
2238 clk_disable_unprepare(fep->clk_enet_out);
2239 clk_disable_unprepare(fep->clk_ipg);
2240 clk_disable_unprepare(fep->clk_ahb);
2246 #ifdef CONFIG_PM_SLEEP
2248 fec_suspend(struct device *dev)
2250 struct net_device *ndev = dev_get_drvdata(dev);
2251 struct fec_enet_private *fep = netdev_priv(ndev);
2253 if (netif_running(ndev)) {
2255 netif_device_detach(ndev);
2258 clk_disable_unprepare(fep->clk_ptp);
2259 if (fep->clk_enet_out)
2260 clk_disable_unprepare(fep->clk_enet_out);
2261 clk_disable_unprepare(fep->clk_ipg);
2262 clk_disable_unprepare(fep->clk_ahb);
2265 regulator_disable(fep->reg_phy);
2271 fec_resume(struct device *dev)
2273 struct net_device *ndev = dev_get_drvdata(dev);
2274 struct fec_enet_private *fep = netdev_priv(ndev);
2278 ret = regulator_enable(fep->reg_phy);
2283 ret = clk_prepare_enable(fep->clk_ahb);
2285 goto failed_clk_ahb;
2287 ret = clk_prepare_enable(fep->clk_ipg);
2289 goto failed_clk_ipg;
2291 if (fep->clk_enet_out) {
2292 ret = clk_prepare_enable(fep->clk_enet_out);
2294 goto failed_clk_enet_out;
2298 ret = clk_prepare_enable(fep->clk_ptp);
2300 goto failed_clk_ptp;
2303 if (netif_running(ndev)) {
2304 fec_restart(ndev, fep->full_duplex);
2305 netif_device_attach(ndev);
2311 if (fep->clk_enet_out)
2312 clk_disable_unprepare(fep->clk_enet_out);
2313 failed_clk_enet_out:
2314 clk_disable_unprepare(fep->clk_ipg);
2316 clk_disable_unprepare(fep->clk_ahb);
2319 regulator_disable(fep->reg_phy);
2322 #endif /* CONFIG_PM_SLEEP */
2324 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2326 static struct platform_driver fec_driver = {
2328 .name = DRIVER_NAME,
2329 .owner = THIS_MODULE,
2331 .of_match_table = fec_dt_ids,
2333 .id_table = fec_devtype,
2335 .remove = fec_drv_remove,
2338 module_platform_driver(fec_driver);
2340 MODULE_ALIAS("platform:"DRIVER_NAME);
2341 MODULE_LICENSE("GPL");