drivers/net/ethernet/mellanox/mlx4/en_rx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <net/busy_poll.h>
  35 #include <linux/bpf.h>
  36 #include <linux/bpf_trace.h>
  37 #include <linux/mlx4/cq.h>
  38 #include <linux/slab.h>
  39 #include <linux/mlx4/qp.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/rculist.h>
  42 #include <linux/if_ether.h>
  43 #include <linux/if_vlan.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/irq.h>
  46
  47 #if IS_ENABLED(CONFIG_IPV6)
  48 #include <net/ip6_checksum.h>
  49 #endif
  50
  51 #include "mlx4_en.h"
  52
  53 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
  54                             struct mlx4_en_rx_alloc *page_alloc,
  55                             const struct mlx4_en_frag_info *frag_info,
  56                             gfp_t _gfp)
  57 {
  58         int order;
  59         struct page *page;
  60         dma_addr_t dma;
  61
  62         for (order = priv->rx_page_order; ;) {
  63                 gfp_t gfp = _gfp;
  64
  65                 if (order)
  66                         gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC;
  67                 page = alloc_pages(gfp, order);
  68                 if (likely(page))
  69                         break;
  70                 if (--order < 0 ||
  71                     ((PAGE_SIZE << order) < frag_info->frag_size))
  72                         return -ENOMEM;
  73         }
  74         dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
  75                            priv->dma_dir);
  76         if (unlikely(dma_mapping_error(priv->ddev, dma))) {
  77                 put_page(page);
  78                 return -ENOMEM;
  79         }
  80         page_alloc->page_size = PAGE_SIZE << order;
  81         page_alloc->page = page;
  82         page_alloc->dma = dma;
  83         page_alloc->page_offset = 0;
  84         /* Not doing get_page() for each frag is a big win
  85          * on asymetric workloads. Note we can not use atomic_set().
  86          */
  87         page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1);
  88         return 0;
  89 }
  90
  91 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
  92                                struct mlx4_en_rx_desc *rx_desc,
  93                                struct mlx4_en_rx_alloc *frags,
  94                                struct mlx4_en_rx_alloc *ring_alloc,
  95                                gfp_t gfp)
  96 {
  97         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
  98         const struct mlx4_en_frag_info *frag_info;
  99         struct page *page;
 100         int i;
 101
 102         for (i = 0; i < priv->num_frags; i++) {
 103                 frag_info = &priv->frag_info[i];
 104                 page_alloc[i] = ring_alloc[i];
 105                 page_alloc[i].page_offset += frag_info->frag_stride;
 106
 107                 if (page_alloc[i].page_offset + frag_info->frag_stride <=
 108                     ring_alloc[i].page_size)
 109                         continue;
 110
 111                 if (unlikely(mlx4_alloc_pages(priv, &page_alloc[i],
 112                                               frag_info, gfp)))
 113                         goto out;
 114         }
 115
 116         for (i = 0; i < priv->num_frags; i++) {
 117                 frags[i] = ring_alloc[i];
 118                 frags[i].page_offset += priv->frag_info[i].rx_headroom;
 119                 rx_desc->data[i].addr = cpu_to_be64(frags[i].dma +
 120                                                     frags[i].page_offset);
 121                 ring_alloc[i] = page_alloc[i];
 122         }
 123
 124         return 0;
 125
 126 out:
 127         while (i--) {
 128                 if (page_alloc[i].page != ring_alloc[i].page) {
 129                         dma_unmap_page(priv->ddev, page_alloc[i].dma,
 130                                 page_alloc[i].page_size,
 131                                 priv->dma_dir);
 132                         page = page_alloc[i].page;
 133                         /* Revert changes done by mlx4_alloc_pages */
 134                         page_ref_sub(page, page_alloc[i].page_size /
 135                                            priv->frag_info[i].frag_stride - 1);
 136                         put_page(page);
 137                 }
 138         }
 139         return -ENOMEM;
 140 }
 141
 142 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
 143                               struct mlx4_en_rx_alloc *frags,
 144                               int i)
 145 {
 146         const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 147         u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
 148
 149
 150         if (next_frag_end > frags[i].page_size)
 151                 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
 152                                priv->dma_dir);
 153
 154         if (frags[i].page)
 155                 put_page(frags[i].page);
 156 }
 157
 158 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
 159                                   struct mlx4_en_rx_ring *ring)
 160 {
 161         int i;
 162         struct mlx4_en_rx_alloc *page_alloc;
 163
 164         for (i = 0; i < priv->num_frags; i++) {
 165                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 166
 167                 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
 168                                      frag_info, GFP_KERNEL | __GFP_COLD))
 169                         goto out;
 170
 171                 en_dbg(DRV, priv, "  frag %d allocator: - size:%d frags:%d\n",
 172                        i, ring->page_alloc[i].page_size,
 173                        page_ref_count(ring->page_alloc[i].page));
 174         }
 175         return 0;
 176
 177 out:
 178         while (i--) {
 179                 struct page *page;
 180
 181                 page_alloc = &ring->page_alloc[i];
 182                 dma_unmap_page(priv->ddev, page_alloc->dma,
 183                                page_alloc->page_size,
 184                                priv->dma_dir);
 185                 page = page_alloc->page;
 186                 /* Revert changes done by mlx4_alloc_pages */
 187                 page_ref_sub(page, page_alloc->page_size /
 188                                    priv->frag_info[i].frag_stride - 1);
 189                 put_page(page);
 190                 page_alloc->page = NULL;
 191         }
 192         return -ENOMEM;
 193 }
 194
 195 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
 196                                       struct mlx4_en_rx_ring *ring)
 197 {
 198         struct mlx4_en_rx_alloc *page_alloc;
 199         int i;
 200
 201         for (i = 0; i < priv->num_frags; i++) {
 202                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 203
 204                 page_alloc = &ring->page_alloc[i];
 205                 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
 206                        i, page_count(page_alloc->page));
 207
 208                 dma_unmap_page(priv->ddev, page_alloc->dma,
 209                                 page_alloc->page_size, priv->dma_dir);
 210                 while (page_alloc->page_offset + frag_info->frag_stride <
 211                        page_alloc->page_size) {
 212                         put_page(page_alloc->page);
 213                         page_alloc->page_offset += frag_info->frag_stride;
 214                 }
 215                 page_alloc->page = NULL;
 216         }
 217 }
 218
 219 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
 220                                  struct mlx4_en_rx_ring *ring, int index)
 221 {
 222         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
 223         int possible_frags;
 224         int i;
 225
 226         /* Set size and memtype fields */
 227         for (i = 0; i < priv->num_frags; i++) {
 228                 rx_desc->data[i].byte_count =
 229                         cpu_to_be32(priv->frag_info[i].frag_size);
 230                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
 231         }
 232
 233         /* If the number of used fragments does not fill up the ring stride,
 234          * remaining (unused) fragments must be padded with null address/size
 235          * and a special memory key */
 236         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
 237         for (i = priv->num_frags; i < possible_frags; i++) {
 238                 rx_desc->data[i].byte_count = 0;
 239                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
 240                 rx_desc->data[i].addr = 0;
 241         }
 242 }
 243
 244 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 245                                    struct mlx4_en_rx_ring *ring, int index,
 246                                    gfp_t gfp)
 247 {
 248         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
 249         struct mlx4_en_rx_alloc *frags = ring->rx_info +
 250                                         (index << priv->log_rx_info);
 251
 252         if (ring->page_cache.index > 0) {
 253                 frags[0] = ring->page_cache.buf[--ring->page_cache.index];
 254                 rx_desc->data[0].addr = cpu_to_be64(frags[0].dma +
 255                                                     frags[0].page_offset);
 256                 return 0;
 257         }
 258
 259         return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
 260 }
 261
 262 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
 263 {
 264         return ring->prod == ring->cons;
 265 }
 266
 267 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 268 {
 269         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 270 }
 271
 272 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
 273                                  struct mlx4_en_rx_ring *ring,
 274                                  int index)
 275 {
 276         struct mlx4_en_rx_alloc *frags;
 277         int nr;
 278
 279         frags = ring->rx_info + (index << priv->log_rx_info);
 280         for (nr = 0; nr < priv->num_frags; nr++) {
 281                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
 282                 mlx4_en_free_frag(priv, frags, nr);
 283         }
 284 }
 285
 286 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 287 {
 288         struct mlx4_en_rx_ring *ring;
 289         int ring_ind;
 290         int buf_ind;
 291         int new_size;
 292
 293         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 294                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 295                         ring = priv->rx_ring[ring_ind];
 296
 297                         if (mlx4_en_prepare_rx_desc(priv, ring,
 298                                                     ring->actual_size,
 299                                                     GFP_KERNEL | __GFP_COLD)) {
 300                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
 301                                         en_err(priv, "Failed to allocate enough rx buffers\n");
 302                                         return -ENOMEM;
 303                                 } else {
 304                                         new_size = rounddown_pow_of_two(ring->actual_size);
 305                                         en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
 306                                                 ring->actual_size, new_size);
 307                                         goto reduce_rings;
 308                                 }
 309                         }
 310                         ring->actual_size++;
 311                         ring->prod++;
 312                 }
 313         }
 314         return 0;
 315
 316 reduce_rings:
 317         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 318                 ring = priv->rx_ring[ring_ind];
 319                 while (ring->actual_size > new_size) {
 320                         ring->actual_size--;
 321                         ring->prod--;
 322                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
 323                 }
 324         }
 325
 326         return 0;
 327 }
 328
 329 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 330                                 struct mlx4_en_rx_ring *ring)
 331 {
 332         int index;
 333
 334         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 335                ring->cons, ring->prod);
 336
 337         /* Unmap and free Rx buffers */
 338         while (!mlx4_en_is_ring_empty(ring)) {
 339                 index = ring->cons & ring->size_mask;
 340                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 341                 mlx4_en_free_rx_desc(priv, ring, index);
 342                 ++ring->cons;
 343         }
 344 }
 345
 346 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
 347 {
 348         int i;
 349         int num_of_eqs;
 350         int num_rx_rings;
 351         struct mlx4_dev *dev = mdev->dev;
 352
 353         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
 354                 num_of_eqs = max_t(int, MIN_RX_RINGS,
 355                                    min_t(int,
 356                                          mlx4_get_eqs_per_port(mdev->dev, i),
 357                                          DEF_RX_RINGS));
 358
 359                 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
 360                         min_t(int, num_of_eqs,
 361                               netif_get_num_default_rss_queues());
 362                 mdev->profile.prof[i].rx_ring_num =
 363                         rounddown_pow_of_two(num_rx_rings);
 364         }
 365 }
 366
 367 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 368                            struct mlx4_en_rx_ring **pring,
 369                            u32 size, u16 stride, int node)
 370 {
 371         struct mlx4_en_dev *mdev = priv->mdev;
 372         struct mlx4_en_rx_ring *ring;
 373         int err = -ENOMEM;
 374         int tmp;
 375
 376         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
 377         if (!ring) {
 378                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 379                 if (!ring) {
 380                         en_err(priv, "Failed to allocate RX ring structure\n");
 381                         return -ENOMEM;
 382                 }
 383         }
 384
 385         ring->prod = 0;
 386         ring->cons = 0;
 387         ring->size = size;
 388         ring->size_mask = size - 1;
 389         ring->stride = stride;
 390         ring->log_stride = ffs(ring->stride) - 1;
 391         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 392
 393         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
 394                                         sizeof(struct mlx4_en_rx_alloc));
 395         ring->rx_info = vmalloc_node(tmp, node);
 396         if (!ring->rx_info) {
 397                 ring->rx_info = vmalloc(tmp);
 398                 if (!ring->rx_info) {
 399                         err = -ENOMEM;
 400                         goto err_ring;
 401                 }
 402         }
 403
 404         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
 405                  ring->rx_info, tmp);
 406
 407         /* Allocate HW buffers on provided NUMA node */
 408         set_dev_node(&mdev->dev->persist->pdev->dev, node);
 409         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 410         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
 411         if (err)
 412                 goto err_info;
 413
 414         ring->buf = ring->wqres.buf.direct.buf;
 415
 416         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
 417
 418         *pring = ring;
 419         return 0;
 420
 421 err_info:
 422         vfree(ring->rx_info);
 423         ring->rx_info = NULL;
 424 err_ring:
 425         kfree(ring);
 426         *pring = NULL;
 427
 428         return err;
 429 }
 430
 431 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 432 {
 433         struct mlx4_en_rx_ring *ring;
 434         int i;
 435         int ring_ind;
 436         int err;
 437         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 438                                         DS_SIZE * priv->num_frags);
 439
 440         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 441                 ring = priv->rx_ring[ring_ind];
 442
 443                 ring->prod = 0;
 444                 ring->cons = 0;
 445                 ring->actual_size = 0;
 446                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
 447
 448                 ring->stride = stride;
 449                 if (ring->stride <= TXBB_SIZE) {
 450                         /* Stamp first unused send wqe */
 451                         __be32 *ptr = (__be32 *)ring->buf;
 452                         __be32 stamp = cpu_to_be32(1 << STAMP_SHIFT);
 453                         *ptr = stamp;
 454                         /* Move pointer to start of rx section */
 455                         ring->buf += TXBB_SIZE;
 456                 }
 457
 458                 ring->log_stride = ffs(ring->stride) - 1;
 459                 ring->buf_size = ring->size * ring->stride;
 460
 461                 memset(ring->buf, 0, ring->buf_size);
 462                 mlx4_en_update_rx_prod_db(ring);
 463
 464                 /* Initialize all descriptors */
 465                 for (i = 0; i < ring->size; i++)
 466                         mlx4_en_init_rx_desc(priv, ring, i);
 467
 468                 /* Initialize page allocators */
 469                 err = mlx4_en_init_allocator(priv, ring);
 470                 if (err) {
 471                         en_err(priv, "Failed initializing ring allocator\n");
 472                         if (ring->stride <= TXBB_SIZE)
 473                                 ring->buf -= TXBB_SIZE;
 474                         ring_ind--;
 475                         goto err_allocator;
 476                 }
 477         }
 478         err = mlx4_en_fill_rx_buffers(priv);
 479         if (err)
 480                 goto err_buffers;
 481
 482         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 483                 ring = priv->rx_ring[ring_ind];
 484
 485                 ring->size_mask = ring->actual_size - 1;
 486                 mlx4_en_update_rx_prod_db(ring);
 487         }
 488
 489         return 0;
 490
 491 err_buffers:
 492         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 493                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
 494
 495         ring_ind = priv->rx_ring_num - 1;
 496 err_allocator:
 497         while (ring_ind >= 0) {
 498                 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
 499                         priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
 500                 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
 501                 ring_ind--;
 502         }
 503         return err;
 504 }
 505
 506 /* We recover from out of memory by scheduling our napi poll
 507  * function (mlx4_en_process_cq), which tries to allocate
 508  * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
 509  */
 510 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
 511 {
 512         int ring;
 513
 514         if (!priv->port_up)
 515                 return;
 516
 517         for (ring = 0; ring < priv->rx_ring_num; ring++) {
 518                 if (mlx4_en_is_ring_empty(priv->rx_ring[ring])) {
 519                         local_bh_disable();
 520                         napi_reschedule(&priv->rx_cq[ring]->napi);
 521                         local_bh_enable();
 522                 }
 523         }
 524 }
 525
 526 /* When the rx ring is running in page-per-packet mode, a released frame can go
 527  * directly into a small cache, to avoid unmapping or touching the page
 528  * allocator. In bpf prog performance scenarios, buffers are either forwarded
 529  * or dropped, never converted to skbs, so every page can come directly from
 530  * this cache when it is sized to be a multiple of the napi budget.
 531  */
 532 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
 533                         struct mlx4_en_rx_alloc *frame)
 534 {
 535         struct mlx4_en_page_cache *cache = &ring->page_cache;
 536
 537         if (cache->index >= MLX4_EN_CACHE_SIZE)
 538                 return false;
 539
 540         cache->buf[cache->index++] = *frame;
 541         return true;
 542 }
 543
 544 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 545                              struct mlx4_en_rx_ring **pring,
 546                              u32 size, u16 stride)
 547 {
 548         struct mlx4_en_dev *mdev = priv->mdev;
 549         struct mlx4_en_rx_ring *ring = *pring;
 550         struct bpf_prog *old_prog;
 551
 552         old_prog = rcu_dereference_protected(
 553                                         ring->xdp_prog,
 554                                         lockdep_is_held(&mdev->state_lock));
 555         if (old_prog)
 556                 bpf_prog_put(old_prog);
 557         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 558         vfree(ring->rx_info);
 559         ring->rx_info = NULL;
 560         kfree(ring);
 561         *pring = NULL;
 562 }
 563
 564 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 565                                 struct mlx4_en_rx_ring *ring)
 566 {
 567         int i;
 568
 569         for (i = 0; i < ring->page_cache.index; i++) {
 570                 struct mlx4_en_rx_alloc *frame = &ring->page_cache.buf[i];
 571
 572                 dma_unmap_page(priv->ddev, frame->dma, frame->page_size,
 573                                priv->dma_dir);
 574                 put_page(frame->page);
 575         }
 576         ring->page_cache.index = 0;
 577         mlx4_en_free_rx_buf(priv, ring);
 578         if (ring->stride <= TXBB_SIZE)
 579                 ring->buf -= TXBB_SIZE;
 580         mlx4_en_destroy_allocator(priv, ring);
 581 }
 582
 583
 584 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
 585                                     struct mlx4_en_rx_desc *rx_desc,
 586                                     struct mlx4_en_rx_alloc *frags,
 587                                     struct sk_buff *skb,
 588                                     int length)
 589 {
 590         struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
 591         struct mlx4_en_frag_info *frag_info = priv->frag_info;
 592         int nr, frag_size;
 593         dma_addr_t dma;
 594
 595         /* Collect used fragments while replacing them in the HW descriptors */
 596         for (nr = 0;;) {
 597                 frag_size = min_t(int, length, frag_info->frag_size);
 598
 599                 if (unlikely(!frags[nr].page))
 600                         goto fail;
 601
 602                 dma = be64_to_cpu(rx_desc->data[nr].addr);
 603                 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
 604                                         DMA_FROM_DEVICE);
 605
 606                 __skb_fill_page_desc(skb, nr, frags[nr].page,
 607                                      frags[nr].page_offset,
 608                                      frag_size);
 609
 610                 skb->truesize += frag_info->frag_stride;
 611                 frags[nr].page = NULL;
 612                 nr++;
 613                 length -= frag_size;
 614                 if (!length)
 615                         break;
 616                 frag_info++;
 617         }
 618         return nr;
 619
 620 fail:
 621         while (nr > 0) {
 622                 nr--;
 623                 __skb_frag_unref(&skb_frags_rx[nr]);
 624         }
 625         return 0;
 626 }
 627
 628
 629 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
 630                                       struct mlx4_en_rx_desc *rx_desc,
 631                                       struct mlx4_en_rx_alloc *frags,
 632                                       unsigned int length)
 633 {
 634         struct sk_buff *skb;
 635         void *va;
 636         int used_frags;
 637         dma_addr_t dma;
 638
 639         skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
 640         if (unlikely(!skb)) {
 641                 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
 642                 return NULL;
 643         }
 644         skb_reserve(skb, NET_IP_ALIGN);
 645         skb->len = length;
 646
 647         /* Get pointer to first fragment so we could copy the headers into the
 648          * (linear part of the) skb */
 649         va = page_address(frags[0].page) + frags[0].page_offset;
 650
 651         if (length <= SMALL_PACKET_SIZE) {
 652                 /* We are copying all relevant data to the skb - temporarily
 653                  * sync buffers for the copy */
 654                 dma = be64_to_cpu(rx_desc->data[0].addr);
 655                 dma_sync_single_for_cpu(priv->ddev, dma, length,
 656                                         DMA_FROM_DEVICE);
 657                 skb_copy_to_linear_data(skb, va, length);
 658                 skb->tail += length;
 659         } else {
 660                 unsigned int pull_len;
 661
 662                 /* Move relevant fragments to skb */
 663                 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
 664                                                         skb, length);
 665                 if (unlikely(!used_frags)) {
 666                         kfree_skb(skb);
 667                         return NULL;
 668                 }
 669                 skb_shinfo(skb)->nr_frags = used_frags;
 670
 671                 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
 672                 /* Copy headers into the skb linear buffer */
 673                 memcpy(skb->data, va, pull_len);
 674                 skb->tail += pull_len;
 675
 676                 /* Skip headers in first fragment */
 677                 skb_shinfo(skb)->frags[0].page_offset += pull_len;
 678
 679                 /* Adjust size of first fragment */
 680                 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
 681                 skb->data_len = length - pull_len;
 682         }
 683         return skb;
 684 }
 685
 686 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
 687 {
 688         int i;
 689         int offset = ETH_HLEN;
 690
 691         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
 692                 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
 693                         goto out_loopback;
 694         }
 695         /* Loopback found */
 696         priv->loopback_ok = 1;
 697
 698 out_loopback:
 699         dev_kfree_skb_any(skb);
 700 }
 701
 702 static bool mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
 703                                       struct mlx4_en_rx_ring *ring)
 704 {
 705         u32 missing = ring->actual_size - (ring->prod - ring->cons);
 706
 707         /* Try to batch allocations, but not too much. */
 708         if (missing < 8)
 709                 return false;
 710         do {
 711                 if (mlx4_en_prepare_rx_desc(priv, ring,
 712                                             ring->prod & ring->size_mask,
 713                                             GFP_ATOMIC | __GFP_COLD |
 714                                             __GFP_MEMALLOC))
 715                         break;
 716                 ring->prod++;
 717         } while (--missing);
 718
 719         return true;
 720 }
 721
 722 /* When hardware doesn't strip the vlan, we need to calculate the checksum
 723  * over it and add it to the hardware's checksum calculation
 724  */
 725 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
 726                                          struct vlan_hdr *vlanh)
 727 {
 728         return csum_add(hw_checksum, *(__wsum *)vlanh);
 729 }
 730
 731 /* Although the stack expects checksum which doesn't include the pseudo
 732  * header, the HW adds it. To address that, we are subtracting the pseudo
 733  * header checksum from the checksum value provided by the HW.
 734  */
 735 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
 736                                 struct iphdr *iph)
 737 {
 738         __u16 length_for_csum = 0;
 739         __wsum csum_pseudo_header = 0;
 740
 741         length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
 742         csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
 743                                                 length_for_csum, iph->protocol, 0);
 744         skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
 745 }
 746
 747 #if IS_ENABLED(CONFIG_IPV6)
 748 /* In IPv6 packets, besides subtracting the pseudo header checksum,
 749  * we also compute/add the IP header checksum which
 750  * is not added by the HW.
 751  */
 752 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
 753                                struct ipv6hdr *ipv6h)
 754 {
 755         __wsum csum_pseudo_hdr = 0;
 756
 757         if (unlikely(ipv6h->nexthdr == IPPROTO_FRAGMENT ||
 758                      ipv6h->nexthdr == IPPROTO_HOPOPTS))
 759                 return -1;
 760         hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr));
 761
 762         csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
 763                                        sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
 764         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
 765         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
 766
 767         skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
 768         skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
 769         return 0;
 770 }
 771 #endif
 772 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
 773                       netdev_features_t dev_features)
 774 {
 775         __wsum hw_checksum = 0;
 776
 777         void *hdr = (u8 *)va + sizeof(struct ethhdr);
 778
 779         hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
 780
 781         if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
 782             !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
 783                 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
 784                 hdr += sizeof(struct vlan_hdr);
 785         }
 786
 787         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
 788                 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
 789 #if IS_ENABLED(CONFIG_IPV6)
 790         else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
 791                 if (unlikely(get_fixed_ipv6_csum(hw_checksum, skb, hdr)))
 792                         return -1;
 793 #endif
 794         return 0;
 795 }
 796
 797 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 798 {
 799         struct mlx4_en_priv *priv = netdev_priv(dev);
 800         struct mlx4_en_dev *mdev = priv->mdev;
 801         struct mlx4_cqe *cqe;
 802         struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
 803         struct mlx4_en_rx_alloc *frags;
 804         struct mlx4_en_rx_desc *rx_desc;
 805         struct bpf_prog *xdp_prog;
 806         int doorbell_pending;
 807         struct sk_buff *skb;
 808         int index;
 809         int nr;
 810         unsigned int length;
 811         int polled = 0;
 812         int ip_summed;
 813         int factor = priv->cqe_factor;
 814         u64 timestamp;
 815         bool l2_tunnel;
 816
 817         if (unlikely(!priv->port_up))
 818                 return 0;
 819
 820         if (unlikely(budget <= 0))
 821                 return polled;
 822
 823         /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */
 824         rcu_read_lock();
 825         xdp_prog = rcu_dereference(ring->xdp_prog);
 826         doorbell_pending = 0;
 827
 828         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 829          * descriptor offset can be deduced from the CQE index instead of
 830          * reading 'cqe->index' */
 831         index = cq->mcq.cons_index & ring->size_mask;
 832         cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 833
 834         /* Process all completed CQEs */
 835         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 836                     cq->mcq.cons_index & cq->size)) {
 837
 838                 frags = ring->rx_info + (index << priv->log_rx_info);
 839                 rx_desc = ring->buf + (index << ring->log_stride);
 840
 841                 /*
 842                  * make sure we read the CQE after we read the ownership bit
 843                  */
 844                 dma_rmb();
 845
 846                 /* Drop packet on bad receive or bad checksum */
 847                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 848                                                 MLX4_CQE_OPCODE_ERROR)) {
 849                         en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
 850                                ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
 851                                ((struct mlx4_err_cqe *)cqe)->syndrome);
 852                         goto next;
 853                 }
 854                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 855                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 856                         goto next;
 857                 }
 858
 859                 /* Check if we need to drop the packet if SRIOV is not enabled
 860                  * and not performing the selftest or flb disabled
 861                  */
 862                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
 863                         struct ethhdr *ethh;
 864                         dma_addr_t dma;
 865                         /* Get pointer to first fragment since we haven't
 866                          * skb yet and cast it to ethhdr struct
 867                          */
 868                         dma = be64_to_cpu(rx_desc->data[0].addr);
 869                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
 870                                                 DMA_FROM_DEVICE);
 871                         ethh = (struct ethhdr *)(page_address(frags[0].page) +
 872                                                  frags[0].page_offset);
 873
 874                         if (is_multicast_ether_addr(ethh->h_dest)) {
 875                                 struct mlx4_mac_entry *entry;
 876                                 struct hlist_head *bucket;
 877                                 unsigned int mac_hash;
 878
 879                                 /* Drop the packet, since HW loopback-ed it */
 880                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
 881                                 bucket = &priv->mac_hash[mac_hash];
 882                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
 883                                         if (ether_addr_equal_64bits(entry->mac,
 884                                                                     ethh->h_source))
 885                                                 goto next;
 886                                 }
 887                         }
 888                 }
 889
 890                 /*
 891                  * Packet is OK - process it.
 892                  */
 893                 length = be32_to_cpu(cqe->byte_cnt);
 894                 length -= ring->fcs_del;
 895                 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
 896                         (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
 897
 898                 /* A bpf program gets first chance to drop the packet. It may
 899                  * read bytes but not past the end of the frag.
 900                  */
 901                 if (xdp_prog) {
 902                         struct xdp_buff xdp;
 903                         dma_addr_t dma;
 904                         void *orig_data;
 905                         u32 act;
 906
 907                         dma = be64_to_cpu(rx_desc->data[0].addr);
 908                         dma_sync_single_for_cpu(priv->ddev, dma,
 909                                                 priv->frag_info[0].frag_size,
 910                                                 DMA_FROM_DEVICE);
 911
 912                         xdp.data_hard_start = page_address(frags[0].page);
 913                         xdp.data = xdp.data_hard_start + frags[0].page_offset;
 914                         xdp.data_end = xdp.data + length;
 915                         orig_data = xdp.data;
 916
 917                         act = bpf_prog_run_xdp(xdp_prog, &xdp);
 918
 919                         if (xdp.data != orig_data) {
 920                                 length = xdp.data_end - xdp.data;
 921                                 frags[0].page_offset = xdp.data -
 922                                         xdp.data_hard_start;
 923                         }
 924
 925                         switch (act) {
 926                         case XDP_PASS:
 927                                 break;
 928                         case XDP_TX:
 929                                 if (likely(!mlx4_en_xmit_frame(ring, frags, dev,
 930                                                         length, cq->ring,
 931                                                         &doorbell_pending)))
 932                                         goto consumed;
 933                                 trace_xdp_exception(dev, xdp_prog, act);
 934                                 goto xdp_drop_no_cnt; /* Drop on xmit failure */
 935                         default:
 936                                 bpf_warn_invalid_xdp_action(act);
 937                         case XDP_ABORTED:
 938                                 trace_xdp_exception(dev, xdp_prog, act);
 939                         case XDP_DROP:
 940                                 ring->xdp_drop++;
 941 xdp_drop_no_cnt:
 942                                 if (likely(mlx4_en_rx_recycle(ring, frags)))
 943                                         goto consumed;
 944                                 goto next;
 945                         }
 946                 }
 947
 948                 ring->bytes += length;
 949                 ring->packets++;
 950
 951                 if (likely(dev->features & NETIF_F_RXCSUM)) {
 952                         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
 953                                                       MLX4_CQE_STATUS_UDP)) {
 954                                 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 955                                     cqe->checksum == cpu_to_be16(0xffff)) {
 956                                         ip_summed = CHECKSUM_UNNECESSARY;
 957                                         ring->csum_ok++;
 958                                 } else {
 959                                         ip_summed = CHECKSUM_NONE;
 960                                         ring->csum_none++;
 961                                 }
 962                         } else {
 963                                 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
 964                                     (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 965                                                                MLX4_CQE_STATUS_IPV6))) {
 966                                         ip_summed = CHECKSUM_COMPLETE;
 967                                         ring->csum_complete++;
 968                                 } else {
 969                                         ip_summed = CHECKSUM_NONE;
 970                                         ring->csum_none++;
 971                                 }
 972                         }
 973                 } else {
 974                         ip_summed = CHECKSUM_NONE;
 975                         ring->csum_none++;
 976                 }
 977
 978                 /* This packet is eligible for GRO if it is:
 979                  * - DIX Ethernet (type interpretation)
 980                  * - TCP/IP (v4)
 981                  * - without IP options
 982                  * - not an IP fragment
 983                  */
 984                 if (dev->features & NETIF_F_GRO) {
 985                         struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
 986                         if (!gro_skb)
 987                                 goto next;
 988
 989                         nr = mlx4_en_complete_rx_desc(priv,
 990                                 rx_desc, frags, gro_skb,
 991                                 length);
 992                         if (!nr)
 993                                 goto next;
 994
 995                         if (ip_summed == CHECKSUM_COMPLETE) {
 996                                 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
 997                                 if (check_csum(cqe, gro_skb, va,
 998                                                dev->features)) {
 999                                         ip_summed = CHECKSUM_NONE;
1000                                         ring->csum_none++;
1001                                         ring->csum_complete--;
1002                                 }
1003                         }
1004
1005                         skb_shinfo(gro_skb)->nr_frags = nr;
1006                         gro_skb->len = length;
1007                         gro_skb->data_len = length;
1008                         gro_skb->ip_summed = ip_summed;
1009
1010                         if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
1011                                 gro_skb->csum_level = 1;
1012
1013                         if ((cqe->vlan_my_qpn &
1014                             cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
1015                             (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1016                                 u16 vid = be16_to_cpu(cqe->sl_vid);
1017
1018                                 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
1019                         } else if ((be32_to_cpu(cqe->vlan_my_qpn) &
1020                                   MLX4_CQE_SVLAN_PRESENT_MASK) &&
1021                                  (dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
1022                                 __vlan_hwaccel_put_tag(gro_skb,
1023                                                        htons(ETH_P_8021AD),
1024                                                        be16_to_cpu(cqe->sl_vid));
1025                         }
1026
1027                         if (dev->features & NETIF_F_RXHASH)
1028                                 skb_set_hash(gro_skb,
1029                                              be32_to_cpu(cqe->immed_rss_invalid),
1030                                              (ip_summed == CHECKSUM_UNNECESSARY) ?
1031                                                 PKT_HASH_TYPE_L4 :
1032                                                 PKT_HASH_TYPE_L3);
1033
1034                         skb_record_rx_queue(gro_skb, cq->ring);
1035
1036                         if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1037                                 timestamp = mlx4_en_get_cqe_ts(cqe);
1038                                 mlx4_en_fill_hwtstamps(mdev,
1039                                                        skb_hwtstamps(gro_skb),
1040                                                        timestamp);
1041                         }
1042
1043                         napi_gro_frags(&cq->napi);
1044                         goto next;
1045                 }
1046
1047                 /* GRO not possible, complete processing here */
1048                 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
1049                 if (unlikely(!skb)) {
1050                         ring->dropped++;
1051                         goto next;
1052                 }
1053
1054                 if (unlikely(priv->validate_loopback)) {
1055                         validate_loopback(priv, skb);
1056                         goto next;
1057                 }
1058
1059                 if (ip_summed == CHECKSUM_COMPLETE) {
1060                         if (check_csum(cqe, skb, skb->data, dev->features)) {
1061                                 ip_summed = CHECKSUM_NONE;
1062                                 ring->csum_complete--;
1063                                 ring->csum_none++;
1064                         }
1065                 }
1066
1067                 skb->ip_summed = ip_summed;
1068                 skb->protocol = eth_type_trans(skb, dev);
1069                 skb_record_rx_queue(skb, cq->ring);
1070
1071                 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
1072                         skb->csum_level = 1;
1073
1074                 if (dev->features & NETIF_F_RXHASH)
1075                         skb_set_hash(skb,
1076                                      be32_to_cpu(cqe->immed_rss_invalid),
1077                                      (ip_summed == CHECKSUM_UNNECESSARY) ?
1078                                         PKT_HASH_TYPE_L4 :
1079                                         PKT_HASH_TYPE_L3);
1080
1081                 if ((be32_to_cpu(cqe->vlan_my_qpn) &
1082                     MLX4_CQE_CVLAN_PRESENT_MASK) &&
1083                     (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
1084                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
1085                 else if ((be32_to_cpu(cqe->vlan_my_qpn) &
1086                           MLX4_CQE_SVLAN_PRESENT_MASK) &&
1087                          (dev->features & NETIF_F_HW_VLAN_STAG_RX))
1088                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
1089                                                be16_to_cpu(cqe->sl_vid));
1090
1091                 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1092                         timestamp = mlx4_en_get_cqe_ts(cqe);
1093                         mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
1094                                                timestamp);
1095                 }
1096
1097                 napi_gro_receive(&cq->napi, skb);
1098 next:
1099                 for (nr = 0; nr < priv->num_frags; nr++)
1100                         mlx4_en_free_frag(priv, frags, nr);
1101
1102 consumed:
1103                 ++cq->mcq.cons_index;
1104                 index = (cq->mcq.cons_index) & ring->size_mask;
1105                 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
1106                 if (++polled == budget)
1107                         goto out;
1108         }
1109
1110 out:
1111         rcu_read_unlock();
1112
1113         if (polled) {
1114                 if (doorbell_pending)
1115                         mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq->ring]);
1116
1117                 mlx4_cq_set_ci(&cq->mcq);
1118                 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1119                 ring->cons = cq->mcq.cons_index;
1120         }
1121         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
1122
1123         if (mlx4_en_refill_rx_buffers(priv, ring))
1124                 mlx4_en_update_rx_prod_db(ring);
1125
1126         return polled;
1127 }
1128
1129
1130 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1131 {
1132         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1133         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1134
1135         if (likely(priv->port_up))
1136                 napi_schedule_irqoff(&cq->napi);
1137         else
1138                 mlx4_en_arm_cq(priv, cq);
1139 }
1140
1141 /* Rx CQ polling - called by NAPI */
1142 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1143 {
1144         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1145         struct net_device *dev = cq->dev;
1146         struct mlx4_en_priv *priv = netdev_priv(dev);
1147         int done;
1148
1149         done = mlx4_en_process_rx_cq(dev, cq, budget);
1150
1151         /* If we used up all the quota - we're probably not done yet... */
1152         if (done == budget) {
1153                 const struct cpumask *aff;
1154                 struct irq_data *idata;
1155                 int cpu_curr;
1156
1157                 INC_PERF_COUNTER(priv->pstats.napi_quota);
1158
1159                 cpu_curr = smp_processor_id();
1160                 idata = irq_desc_get_irq_data(cq->irq_desc);
1161                 aff = irq_data_get_affinity_mask(idata);
1162
1163                 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1164                         return budget;
1165
1166                 /* Current cpu is not according to smp_irq_affinity -
1167                  * probably affinity changed. Need to stop this NAPI
1168                  * poll, and restart it on the right CPU.
1169                  * Try to avoid returning a too small value (like 0),
1170                  * to not fool net_rx_action() and its netdev_budget
1171                  */
1172                 if (done)
1173                         done--;
1174         }
1175         /* Done for now */
1176         if (napi_complete_done(napi, done))
1177                 mlx4_en_arm_cq(priv, cq);
1178         return done;
1179 }
1180
1181 static const int frag_sizes[] = {
1182         FRAG_SZ0,
1183         FRAG_SZ1,
1184         FRAG_SZ2,
1185         FRAG_SZ3
1186 };
1187
1188 void mlx4_en_calc_rx_buf(struct net_device *dev)
1189 {
1190         struct mlx4_en_priv *priv = netdev_priv(dev);
1191         int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu);
1192         int i = 0;
1193
1194         /* bpf requires buffers to be set up as 1 packet per page.
1195          * This only works when num_frags == 1.
1196          */
1197         if (priv->tx_ring_num[TX_XDP]) {
1198                 priv->rx_page_order = 0;
1199                 priv->frag_info[0].frag_size = eff_mtu;
1200                 /* This will gain efficient xdp frame recycling at the
1201                  * expense of more costly truesize accounting
1202                  */
1203                 priv->frag_info[0].frag_stride = PAGE_SIZE;
1204                 priv->dma_dir = PCI_DMA_BIDIRECTIONAL;
1205                 priv->frag_info[0].rx_headroom = XDP_PACKET_HEADROOM;
1206                 i = 1;
1207         } else {
1208                 int buf_size = 0;
1209
1210                 while (buf_size < eff_mtu) {
1211                         priv->frag_info[i].frag_size =
1212                                 (eff_mtu > buf_size + frag_sizes[i]) ?
1213                                         frag_sizes[i] : eff_mtu - buf_size;
1214                         priv->frag_info[i].frag_stride =
1215                                 ALIGN(priv->frag_info[i].frag_size,
1216                                       SMP_CACHE_BYTES);
1217                         priv->frag_info[i].rx_headroom = 0;
1218                         buf_size += priv->frag_info[i].frag_size;
1219                         i++;
1220                 }
1221                 priv->rx_page_order = MLX4_EN_ALLOC_PREFER_ORDER;
1222                 priv->dma_dir = PCI_DMA_FROMDEVICE;
1223         }
1224
1225         priv->num_frags = i;
1226         priv->rx_skb_size = eff_mtu;
1227         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1228
1229         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1230                eff_mtu, priv->num_frags);
1231         for (i = 0; i < priv->num_frags; i++) {
1232                 en_err(priv,
1233                        "  frag:%d - size:%d stride:%d\n",
1234                        i,
1235                        priv->frag_info[i].frag_size,
1236                        priv->frag_info[i].frag_stride);
1237         }
1238 }
1239
1240 /* RSS related functions */
1241
1242 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1243                                  struct mlx4_en_rx_ring *ring,
1244                                  enum mlx4_qp_state *state,
1245                                  struct mlx4_qp *qp)
1246 {
1247         struct mlx4_en_dev *mdev = priv->mdev;
1248         struct mlx4_qp_context *context;
1249         int err = 0;
1250
1251         context = kmalloc(sizeof(*context), GFP_KERNEL);
1252         if (!context)
1253                 return -ENOMEM;
1254
1255         err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1256         if (err) {
1257                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1258                 goto out;
1259         }
1260         qp->event = mlx4_en_sqp_event;
1261
1262         memset(context, 0, sizeof *context);
1263         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1264                                 qpn, ring->cqn, -1, context);
1265         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1266
1267         /* Cancel FCS removal if FW allows */
1268         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1269                 context->param3 |= cpu_to_be32(1 << 29);
1270                 if (priv->dev->features & NETIF_F_RXFCS)
1271                         ring->fcs_del = 0;
1272                 else
1273                         ring->fcs_del = ETH_FCS_LEN;
1274         } else
1275                 ring->fcs_del = 0;
1276
1277         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1278         if (err) {
1279                 mlx4_qp_remove(mdev->dev, qp);
1280                 mlx4_qp_free(mdev->dev, qp);
1281         }
1282         mlx4_en_update_rx_prod_db(ring);
1283 out:
1284         kfree(context);
1285         return err;
1286 }
1287
1288 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1289 {
1290         int err;
1291         u32 qpn;
1292
1293         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1294                                     MLX4_RESERVE_A0_QP);
1295         if (err) {
1296                 en_err(priv, "Failed reserving drop qpn\n");
1297                 return err;
1298         }
1299         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1300         if (err) {
1301                 en_err(priv, "Failed allocating drop qp\n");
1302                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1303                 return err;
1304         }
1305
1306         return 0;
1307 }
1308
1309 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1310 {
1311         u32 qpn;
1312
1313         qpn = priv->drop_qp.qpn;
1314         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1315         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1316         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1317 }
1318
1319 /* Allocate rx qp's and configure them according to rss map */
1320 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1321 {
1322         struct mlx4_en_dev *mdev = priv->mdev;
1323         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1324         struct mlx4_qp_context context;
1325         struct mlx4_rss_context *rss_context;
1326         int rss_rings;
1327         void *ptr;
1328         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1329                         MLX4_RSS_TCP_IPV6);
1330         int i, qpn;
1331         int err = 0;
1332         int good_qps = 0;
1333
1334         en_dbg(DRV, priv, "Configuring rss steering\n");
1335         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1336                                     priv->rx_ring_num,
1337                                     &rss_map->base_qpn, 0);
1338         if (err) {
1339                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1340                 return err;
1341         }
1342
1343         for (i = 0; i < priv->rx_ring_num; i++) {
1344                 qpn = rss_map->base_qpn + i;
1345                 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1346                                             &rss_map->state[i],
1347                                             &rss_map->qps[i]);
1348                 if (err)
1349                         goto rss_err;
1350
1351                 ++good_qps;
1352         }
1353
1354         /* Configure RSS indirection qp */
1355         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1356         if (err) {
1357                 en_err(priv, "Failed to allocate RSS indirection QP\n");
1358                 goto rss_err;
1359         }
1360         rss_map->indir_qp.event = mlx4_en_sqp_event;
1361         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1362                                 priv->rx_ring[0]->cqn, -1, &context);
1363
1364         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1365                 rss_rings = priv->rx_ring_num;
1366         else
1367                 rss_rings = priv->prof->rss_rings;
1368
1369         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1370                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1371         rss_context = ptr;
1372         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1373                                             (rss_map->base_qpn));
1374         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1375         if (priv->mdev->profile.udp_rss) {
1376                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1377                 rss_context->base_qpn_udp = rss_context->default_qpn;
1378         }
1379
1380         if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1381                 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1382                 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1383         }
1384
1385         rss_context->flags = rss_mask;
1386         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1387         if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1388                 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1389         } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1390                 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1391                 memcpy(rss_context->rss_key, priv->rss_key,
1392                        MLX4_EN_RSS_KEY_SIZE);
1393         } else {
1394                 en_err(priv, "Unknown RSS hash function requested\n");
1395                 err = -EINVAL;
1396                 goto indir_err;
1397         }
1398         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1399                                &rss_map->indir_qp, &rss_map->indir_state);
1400         if (err)
1401                 goto indir_err;
1402
1403         return 0;
1404
1405 indir_err:
1406         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1407                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1408         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1409         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1410 rss_err:
1411         for (i = 0; i < good_qps; i++) {
1412                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1413                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1414                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1415                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1416         }
1417         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1418         return err;
1419 }
1420
1421 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1422 {
1423         struct mlx4_en_dev *mdev = priv->mdev;
1424         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1425         int i;
1426
1427         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1428                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1429         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1430         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1431
1432         for (i = 0; i < priv->rx_ring_num; i++) {
1433                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1434                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1435                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1436                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1437         }
1438         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1439 }