2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
47 #include <linux/mlx4/device.h>
48 #include <linux/mlx4/driver.h>
49 #include <linux/mlx4/doorbell.h>
50 #include <linux/mlx4/cmd.h>
52 #define DRV_NAME "mlx4_core"
53 #define PFX DRV_NAME ": "
54 #define DRV_VERSION "2.2-1"
55 #define DRV_RELDATE "Feb, 2014"
57 #define MLX4_FS_UDP_UC_EN (1 << 1)
58 #define MLX4_FS_TCP_UC_EN (1 << 2)
59 #define MLX4_FS_NUM_OF_L2_ADDR 8
60 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61 #define MLX4_FS_NUM_MCG (1 << 17)
63 #define INIT_HCA_TPT_MW_ENABLE (1 << 7)
67 #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
68 #define MLX4_RATELIMIT_DEFAULT 0xffff
70 struct mlx4_set_port_prio2tc_context {
74 struct mlx4_port_scheduler_tc_cfg_be {
77 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
81 struct mlx4_set_port_scheduler_context {
82 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
86 MLX4_HCR_BASE = 0x80680,
87 MLX4_HCR_SIZE = 0x0001c,
88 MLX4_CLR_INT_SIZE = 0x00008,
89 MLX4_SLAVE_COMM_BASE = 0x0,
90 MLX4_COMM_PAGESIZE = 0x1000,
91 MLX4_CLOCK_SIZE = 0x00008
95 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
96 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
97 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
98 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
99 MLX4_MTT_ENTRY_PER_SEG = 8,
103 MLX4_NUM_PDS = 1 << 15
107 MLX4_CMPT_TYPE_QP = 0,
108 MLX4_CMPT_TYPE_SRQ = 1,
109 MLX4_CMPT_TYPE_CQ = 2,
110 MLX4_CMPT_TYPE_EQ = 3,
115 MLX4_CMPT_SHIFT = 24,
116 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
119 enum mlx4_mpt_state {
120 MLX4_MPT_DISABLED = 0,
125 #define MLX4_COMM_TIME 10000
131 MLX4_COMM_CMD_VHCR_EN,
132 MLX4_COMM_CMD_VHCR_POST,
133 MLX4_COMM_CMD_FLR = 254
137 MLX4_VF_SMI_DISABLED,
141 /*The flag indicates that the slave should delay the RESET cmd*/
142 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
143 /*indicates how many retries will be done if we are in the middle of FLR*/
144 #define NUM_OF_RESET_RETRIES 10
145 #define SLEEP_TIME_IN_RESET (2 * 1000)
158 MLX4_NUM_OF_RESOURCE_TYPE
161 enum mlx4_alloc_mode {
163 RES_OP_RESERVE_AND_MAP,
167 enum mlx4_res_tracker_free_type {
169 RES_TR_FREE_SLAVES_ONLY,
170 RES_TR_FREE_STRUCTS_ONLY,
174 *Virtual HCR structures.
175 * mlx4_vhcr is the sw representation, in machine endianess
177 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
178 * to FW to go through communication channel.
179 * It is big endian, and has the same structure as the physical HCR
180 * used by command interface
193 struct mlx4_vhcr_cmd {
204 struct mlx4_cmd_info {
209 bool encode_slave_id;
210 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
211 struct mlx4_cmd_mailbox *inbox);
212 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
213 struct mlx4_cmd_mailbox *inbox,
214 struct mlx4_cmd_mailbox *outbox,
215 struct mlx4_cmd_info *cmd);
218 #ifdef CONFIG_MLX4_DEBUG
219 extern int mlx4_debug_level;
220 #else /* CONFIG_MLX4_DEBUG */
221 #define mlx4_debug_level (0)
222 #endif /* CONFIG_MLX4_DEBUG */
224 #define mlx4_dbg(mdev, format, arg...) \
226 if (mlx4_debug_level) \
227 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
230 #define mlx4_err(mdev, format, arg...) \
231 dev_err(&mdev->pdev->dev, format, ##arg)
232 #define mlx4_info(mdev, format, arg...) \
233 dev_info(&mdev->pdev->dev, format, ##arg)
234 #define mlx4_warn(mdev, format, arg...) \
235 dev_warn(&mdev->pdev->dev, format, ##arg)
237 extern int mlx4_log_num_mgm_entry_size;
238 extern int log_mtts_per_seg;
240 #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
241 #define ALL_SLAVES 0xff
251 unsigned long *table;
255 unsigned long **bits;
256 unsigned int *num_free;
263 struct mlx4_icm_table {
271 struct mlx4_icm **icm;
274 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
275 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
276 #define MLX4_MPT_FLAG_MIO (1 << 17)
277 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
278 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
279 #define MLX4_MPT_FLAG_REGION (1 << 8)
281 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
282 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
283 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
285 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
287 #define MLX4_MPT_STATUS_SW 0xF0
288 #define MLX4_MPT_STATUS_HW 0x00
291 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
293 struct mlx4_mpt_entry {
307 __be32 first_byte_offset;
311 * Must be packed because start is 64 bits but only aligned to 32 bits.
313 struct mlx4_eq_context {
327 __be32 mtt_base_addr_l;
329 __be32 consumer_index;
330 __be32 producer_index;
334 struct mlx4_cq_context {
338 __be32 logsize_usrpage;
346 __be32 mtt_base_addr_l;
347 __be32 last_notified_index;
348 __be32 solicit_producer_index;
349 __be32 consumer_index;
350 __be32 producer_index;
355 struct mlx4_srq_context {
356 __be32 state_logsize_srqn;
360 __be32 pg_offset_cqn;
365 __be32 mtt_base_addr_l;
367 __be16 limit_watermark;
376 struct mlx4_dev *dev;
377 void __iomem *doorbell;
383 struct mlx4_buf_list *page_list;
387 struct mlx4_slave_eqe {
393 struct mlx4_slave_event_eq_info {
398 struct mlx4_profile {
413 struct mlx4_icm *fw_icm;
414 struct mlx4_icm *aux_icm;
429 MLX4_MCAST_CONFIG = 0,
430 MLX4_MCAST_DISABLE = 1,
431 MLX4_MCAST_ENABLE = 2,
434 #define VLAN_FLTR_SIZE 128
436 struct mlx4_vlan_fltr {
437 __be32 entry[VLAN_FLTR_SIZE];
440 struct mlx4_mcast_entry {
441 struct list_head list;
445 struct mlx4_promisc_qp {
446 struct list_head list;
450 struct mlx4_steer_index {
451 struct list_head list;
453 struct list_head duplicates;
456 #define MLX4_EVENT_TYPES_NUM 64
458 struct mlx4_slave_state {
466 u16 mtu[MLX4_MAX_PORTS + 1];
467 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
468 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
469 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
470 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
471 /* event type to eq number lookup */
472 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
476 /*initialized via the kzalloc*/
477 u8 is_slave_going_down;
479 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
482 #define MLX4_VGT 4095
485 struct mlx4_vport_state {
494 struct mlx4_vf_admin_state {
495 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
496 u8 enable_smi[MLX4_MAX_PORTS + 1];
499 struct mlx4_vport_oper_state {
500 struct mlx4_vport_state state;
505 struct mlx4_vf_oper_state {
506 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
507 u8 smi_enabled[MLX4_MAX_PORTS + 1];
512 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
515 struct resource_allocator {
516 spinlock_t alloc_lock; /* protect quotas */
519 int res_port_rsvd[MLX4_MAX_PORTS];
523 int res_port_free[MLX4_MAX_PORTS];
530 struct mlx4_resource_tracker {
532 /* tree for each resources */
533 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
534 /* num_of_slave's lists, one per slave */
535 struct slave_list *slave_list;
536 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
539 #define SLAVE_EVENT_EQ_SIZE 128
540 struct mlx4_slave_event_eq {
544 spinlock_t event_lock;
545 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
548 struct mlx4_master_qp0_state {
549 int proxy_qp0_active;
554 struct mlx4_mfunc_master_ctx {
555 struct mlx4_slave_state *slave_state;
556 struct mlx4_vf_admin_state *vf_admin;
557 struct mlx4_vf_oper_state *vf_oper;
558 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
559 int init_port_ref[MLX4_MAX_PORTS + 1];
560 u16 max_mtu[MLX4_MAX_PORTS + 1];
561 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
562 struct mlx4_resource_tracker res_tracker;
563 struct workqueue_struct *comm_wq;
564 struct work_struct comm_work;
565 struct work_struct slave_event_work;
566 struct work_struct slave_flr_event_work;
567 spinlock_t slave_state_lock;
568 __be32 comm_arm_bit_vector[4];
569 struct mlx4_eqe cmd_eqe;
570 struct mlx4_slave_event_eq slave_eq;
571 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
575 struct mlx4_comm __iomem *comm;
576 struct mlx4_vhcr_cmd *vhcr;
579 struct mlx4_mfunc_master_ctx master;
582 #define MGM_QPN_MASK 0x00FFFFFF
583 #define MGM_BLCK_LB_BIT 30
586 __be32 next_gid_index;
587 __be32 members_count;
590 __be32 qp[MLX4_MAX_QP_PER_MGM];
594 struct pci_pool *pool;
596 struct mutex hcr_mutex;
597 struct mutex slave_cmd_mutex;
598 struct semaphore poll_sem;
599 struct semaphore event_sem;
601 spinlock_t context_lock;
603 struct mlx4_cmd_context *context;
611 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
612 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
613 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
615 struct mlx4_vf_immed_vlan_work {
616 struct work_struct work;
617 struct mlx4_priv *priv;
629 struct mlx4_uar_table {
630 struct mlx4_bitmap bitmap;
633 struct mlx4_mr_table {
634 struct mlx4_bitmap mpt_bitmap;
635 struct mlx4_buddy mtt_buddy;
638 struct mlx4_icm_table mtt_table;
639 struct mlx4_icm_table dmpt_table;
642 struct mlx4_cq_table {
643 struct mlx4_bitmap bitmap;
645 struct radix_tree_root tree;
646 struct mlx4_icm_table table;
647 struct mlx4_icm_table cmpt_table;
650 struct mlx4_eq_table {
651 struct mlx4_bitmap bitmap;
653 void __iomem *clr_int;
654 void __iomem **uar_map;
657 struct mlx4_icm_table table;
658 struct mlx4_icm_table cmpt_table;
663 struct mlx4_srq_table {
664 struct mlx4_bitmap bitmap;
666 struct radix_tree_root tree;
667 struct mlx4_icm_table table;
668 struct mlx4_icm_table cmpt_table;
671 struct mlx4_qp_table {
672 struct mlx4_bitmap bitmap;
676 struct mlx4_icm_table qp_table;
677 struct mlx4_icm_table auxc_table;
678 struct mlx4_icm_table altc_table;
679 struct mlx4_icm_table rdmarc_table;
680 struct mlx4_icm_table cmpt_table;
683 struct mlx4_mcg_table {
685 struct mlx4_bitmap bitmap;
686 struct mlx4_icm_table table;
689 struct mlx4_catas_err {
691 struct timer_list timer;
692 struct list_head list;
695 #define MLX4_MAX_MAC_NUM 128
696 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
698 struct mlx4_mac_table {
699 __be64 entries[MLX4_MAX_MAC_NUM];
700 int refs[MLX4_MAX_MAC_NUM];
706 #define MLX4_ROCE_GID_ENTRY_SIZE 16
708 struct mlx4_roce_gid_entry {
709 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
712 struct mlx4_roce_gid_table {
713 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS];
717 #define MLX4_MAX_VLAN_NUM 128
718 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
720 struct mlx4_vlan_table {
721 __be32 entries[MLX4_MAX_VLAN_NUM];
722 int refs[MLX4_MAX_VLAN_NUM];
728 #define SET_PORT_GEN_ALL_VALID 0x7
729 #define SET_PORT_PROMISC_SHIFT 31
730 #define SET_PORT_MC_PROMISC_SHIFT 30
733 MCAST_DIRECT_ONLY = 0,
739 struct mlx4_set_port_general_context {
752 struct mlx4_set_port_rqp_calc_context {
770 struct mlx4_port_info {
771 struct mlx4_dev *dev;
774 struct device_attribute port_attr;
775 enum mlx4_port_type tmp_type;
776 char dev_mtu_name[16];
777 struct device_attribute port_mtu_attr;
778 struct mlx4_mac_table mac_table;
779 struct mlx4_vlan_table vlan_table;
780 struct mlx4_roce_gid_table gid_table;
785 struct mlx4_dev *dev;
786 u8 do_sense_port[MLX4_MAX_PORTS + 1];
787 u8 sense_allowed[MLX4_MAX_PORTS + 1];
788 struct delayed_work sense_poll;
791 struct mlx4_msix_ctl {
793 struct mutex pool_lock;
797 struct list_head promisc_qps[MLX4_NUM_STEERS];
798 struct list_head steer_entries[MLX4_NUM_STEERS];
802 MLX4_PCI_DEV_IS_VF = 1 << 0,
803 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
814 struct list_head dev_list;
815 struct list_head ctx_list;
821 struct list_head pgdir_list;
822 struct mutex pgdir_mutex;
826 struct mlx4_mfunc mfunc;
828 struct mlx4_bitmap pd_bitmap;
829 struct mlx4_bitmap xrcd_bitmap;
830 struct mlx4_uar_table uar_table;
831 struct mlx4_mr_table mr_table;
832 struct mlx4_cq_table cq_table;
833 struct mlx4_eq_table eq_table;
834 struct mlx4_srq_table srq_table;
835 struct mlx4_qp_table qp_table;
836 struct mlx4_mcg_table mcg_table;
837 struct mlx4_bitmap counters_bitmap;
839 struct mlx4_catas_err catas_err;
841 void __iomem *clr_base;
843 struct mlx4_uar driver_uar;
845 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
846 struct mlx4_sense sense;
847 struct mutex port_mutex;
848 struct mlx4_msix_ctl msix_ctl;
849 struct mlx4_steer *steer;
850 struct list_head bf_list;
851 struct mutex bf_mutex;
852 struct io_mapping *bf_mapping;
853 void __iomem *clock_mapping;
856 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
857 __be64 slave_node_guids[MLX4_MFUNC_MAX];
859 atomic_t opreq_count;
860 struct work_struct opreq_task;
863 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
865 return container_of(dev, struct mlx4_priv, dev);
868 #define MLX4_SENSE_RANGE (HZ * 3)
870 extern struct workqueue_struct *mlx4_wq;
872 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
873 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
874 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
875 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
877 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
878 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
879 u32 reserved_bot, u32 resetrved_top);
880 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
882 int mlx4_reset(struct mlx4_dev *dev);
884 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
885 void mlx4_free_eq_table(struct mlx4_dev *dev);
887 int mlx4_init_pd_table(struct mlx4_dev *dev);
888 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
889 int mlx4_init_uar_table(struct mlx4_dev *dev);
890 int mlx4_init_mr_table(struct mlx4_dev *dev);
891 int mlx4_init_eq_table(struct mlx4_dev *dev);
892 int mlx4_init_cq_table(struct mlx4_dev *dev);
893 int mlx4_init_qp_table(struct mlx4_dev *dev);
894 int mlx4_init_srq_table(struct mlx4_dev *dev);
895 int mlx4_init_mcg_table(struct mlx4_dev *dev);
897 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
898 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
899 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
900 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
901 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
902 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
903 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
904 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
905 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
906 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp);
907 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
908 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
909 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
910 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
911 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
912 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
913 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
914 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp);
915 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
916 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
917 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
919 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
920 struct mlx4_vhcr *vhcr,
921 struct mlx4_cmd_mailbox *inbox,
922 struct mlx4_cmd_mailbox *outbox,
923 struct mlx4_cmd_info *cmd);
924 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
925 struct mlx4_vhcr *vhcr,
926 struct mlx4_cmd_mailbox *inbox,
927 struct mlx4_cmd_mailbox *outbox,
928 struct mlx4_cmd_info *cmd);
929 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
930 struct mlx4_vhcr *vhcr,
931 struct mlx4_cmd_mailbox *inbox,
932 struct mlx4_cmd_mailbox *outbox,
933 struct mlx4_cmd_info *cmd);
934 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
935 struct mlx4_vhcr *vhcr,
936 struct mlx4_cmd_mailbox *inbox,
937 struct mlx4_cmd_mailbox *outbox,
938 struct mlx4_cmd_info *cmd);
939 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
940 struct mlx4_vhcr *vhcr,
941 struct mlx4_cmd_mailbox *inbox,
942 struct mlx4_cmd_mailbox *outbox,
943 struct mlx4_cmd_info *cmd);
944 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
945 struct mlx4_vhcr *vhcr,
946 struct mlx4_cmd_mailbox *inbox,
947 struct mlx4_cmd_mailbox *outbox,
948 struct mlx4_cmd_info *cmd);
949 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
950 struct mlx4_vhcr *vhcr,
951 struct mlx4_cmd_mailbox *inbox,
952 struct mlx4_cmd_mailbox *outbox,
953 struct mlx4_cmd_info *cmd);
954 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
956 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
957 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
958 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
959 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
960 int start_index, int npages, u64 *page_list);
961 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
962 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
963 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
964 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
966 void mlx4_start_catas_poll(struct mlx4_dev *dev);
967 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
968 void mlx4_catas_init(void);
969 int mlx4_restart_one(struct pci_dev *pdev);
970 int mlx4_register_device(struct mlx4_dev *dev);
971 void mlx4_unregister_device(struct mlx4_dev *dev);
972 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
973 unsigned long param);
976 struct mlx4_init_hca_param;
978 u64 mlx4_make_profile(struct mlx4_dev *dev,
979 struct mlx4_profile *request,
980 struct mlx4_dev_cap *dev_cap,
981 struct mlx4_init_hca_param *init_hca);
982 void mlx4_master_comm_channel(struct work_struct *work);
983 void mlx4_gen_slave_eqe(struct work_struct *work);
984 void mlx4_master_handle_slave_flr(struct work_struct *work);
986 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
987 struct mlx4_vhcr *vhcr,
988 struct mlx4_cmd_mailbox *inbox,
989 struct mlx4_cmd_mailbox *outbox,
990 struct mlx4_cmd_info *cmd);
991 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
992 struct mlx4_vhcr *vhcr,
993 struct mlx4_cmd_mailbox *inbox,
994 struct mlx4_cmd_mailbox *outbox,
995 struct mlx4_cmd_info *cmd);
996 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
997 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
998 struct mlx4_cmd_mailbox *outbox,
999 struct mlx4_cmd_info *cmd);
1000 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1001 struct mlx4_vhcr *vhcr,
1002 struct mlx4_cmd_mailbox *inbox,
1003 struct mlx4_cmd_mailbox *outbox,
1004 struct mlx4_cmd_info *cmd);
1005 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1006 struct mlx4_vhcr *vhcr,
1007 struct mlx4_cmd_mailbox *inbox,
1008 struct mlx4_cmd_mailbox *outbox,
1009 struct mlx4_cmd_info *cmd);
1010 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1011 struct mlx4_vhcr *vhcr,
1012 struct mlx4_cmd_mailbox *inbox,
1013 struct mlx4_cmd_mailbox *outbox,
1014 struct mlx4_cmd_info *cmd);
1015 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1016 struct mlx4_vhcr *vhcr,
1017 struct mlx4_cmd_mailbox *inbox,
1018 struct mlx4_cmd_mailbox *outbox,
1019 struct mlx4_cmd_info *cmd);
1020 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1021 struct mlx4_vhcr *vhcr,
1022 struct mlx4_cmd_mailbox *inbox,
1023 struct mlx4_cmd_mailbox *outbox,
1024 struct mlx4_cmd_info *cmd);
1025 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1026 struct mlx4_vhcr *vhcr,
1027 struct mlx4_cmd_mailbox *inbox,
1028 struct mlx4_cmd_mailbox *outbox,
1029 struct mlx4_cmd_info *cmd);
1030 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1031 struct mlx4_vhcr *vhcr,
1032 struct mlx4_cmd_mailbox *inbox,
1033 struct mlx4_cmd_mailbox *outbox,
1034 struct mlx4_cmd_info *cmd);
1035 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1036 struct mlx4_vhcr *vhcr,
1037 struct mlx4_cmd_mailbox *inbox,
1038 struct mlx4_cmd_mailbox *outbox,
1039 struct mlx4_cmd_info *cmd);
1040 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1041 struct mlx4_vhcr *vhcr,
1042 struct mlx4_cmd_mailbox *inbox,
1043 struct mlx4_cmd_mailbox *outbox,
1044 struct mlx4_cmd_info *cmd);
1045 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1046 struct mlx4_vhcr *vhcr,
1047 struct mlx4_cmd_mailbox *inbox,
1048 struct mlx4_cmd_mailbox *outbox,
1049 struct mlx4_cmd_info *cmd);
1050 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1051 struct mlx4_vhcr *vhcr,
1052 struct mlx4_cmd_mailbox *inbox,
1053 struct mlx4_cmd_mailbox *outbox,
1054 struct mlx4_cmd_info *cmd);
1055 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1056 struct mlx4_vhcr *vhcr,
1057 struct mlx4_cmd_mailbox *inbox,
1058 struct mlx4_cmd_mailbox *outbox,
1059 struct mlx4_cmd_info *cmd);
1060 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1061 struct mlx4_vhcr *vhcr,
1062 struct mlx4_cmd_mailbox *inbox,
1063 struct mlx4_cmd_mailbox *outbox,
1064 struct mlx4_cmd_info *cmd);
1065 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1066 struct mlx4_vhcr *vhcr,
1067 struct mlx4_cmd_mailbox *inbox,
1068 struct mlx4_cmd_mailbox *outbox,
1069 struct mlx4_cmd_info *cmd);
1070 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1071 struct mlx4_vhcr *vhcr,
1072 struct mlx4_cmd_mailbox *inbox,
1073 struct mlx4_cmd_mailbox *outbox,
1074 struct mlx4_cmd_info *cmd);
1075 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1076 struct mlx4_vhcr *vhcr,
1077 struct mlx4_cmd_mailbox *inbox,
1078 struct mlx4_cmd_mailbox *outbox,
1079 struct mlx4_cmd_info *cmd);
1080 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1081 struct mlx4_vhcr *vhcr,
1082 struct mlx4_cmd_mailbox *inbox,
1083 struct mlx4_cmd_mailbox *outbox,
1084 struct mlx4_cmd_info *cmd);
1085 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1086 struct mlx4_vhcr *vhcr,
1087 struct mlx4_cmd_mailbox *inbox,
1088 struct mlx4_cmd_mailbox *outbox,
1089 struct mlx4_cmd_info *cmd);
1090 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1091 struct mlx4_vhcr *vhcr,
1092 struct mlx4_cmd_mailbox *inbox,
1093 struct mlx4_cmd_mailbox *outbox,
1094 struct mlx4_cmd_info *cmd);
1095 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1096 struct mlx4_vhcr *vhcr,
1097 struct mlx4_cmd_mailbox *inbox,
1098 struct mlx4_cmd_mailbox *outbox,
1099 struct mlx4_cmd_info *cmd);
1100 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1101 struct mlx4_vhcr *vhcr,
1102 struct mlx4_cmd_mailbox *inbox,
1103 struct mlx4_cmd_mailbox *outbox,
1104 struct mlx4_cmd_info *cmd);
1105 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1106 struct mlx4_vhcr *vhcr,
1107 struct mlx4_cmd_mailbox *inbox,
1108 struct mlx4_cmd_mailbox *outbox,
1109 struct mlx4_cmd_info *cmd);
1110 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1111 struct mlx4_vhcr *vhcr,
1112 struct mlx4_cmd_mailbox *inbox,
1113 struct mlx4_cmd_mailbox *outbox,
1114 struct mlx4_cmd_info *cmd);
1115 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1116 struct mlx4_vhcr *vhcr,
1117 struct mlx4_cmd_mailbox *inbox,
1118 struct mlx4_cmd_mailbox *outbox,
1119 struct mlx4_cmd_info *cmd);
1121 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1123 int mlx4_cmd_init(struct mlx4_dev *dev);
1124 void mlx4_cmd_cleanup(struct mlx4_dev *dev);
1125 int mlx4_multi_func_init(struct mlx4_dev *dev);
1126 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1127 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1128 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1129 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1131 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1132 unsigned long timeout);
1134 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1135 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1137 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1139 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1141 void mlx4_handle_catas_err(struct mlx4_dev *dev);
1143 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1144 enum mlx4_port_type *type);
1145 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1146 enum mlx4_port_type *stype,
1147 enum mlx4_port_type *defaults);
1148 void mlx4_start_sense(struct mlx4_dev *dev);
1149 void mlx4_stop_sense(struct mlx4_dev *dev);
1150 void mlx4_sense_init(struct mlx4_dev *dev);
1151 int mlx4_check_port_params(struct mlx4_dev *dev,
1152 enum mlx4_port_type *port_type);
1153 int mlx4_change_port_types(struct mlx4_dev *dev,
1154 enum mlx4_port_type *port_types);
1156 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1157 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1158 void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1159 struct mlx4_roce_gid_table *table);
1160 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1161 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1163 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1164 /* resource tracker functions*/
1165 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1166 enum mlx4_resource resource_type,
1167 u64 resource_id, int *slave);
1168 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1169 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1170 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1172 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1173 enum mlx4_res_tracker_free_type type);
1175 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1176 struct mlx4_vhcr *vhcr,
1177 struct mlx4_cmd_mailbox *inbox,
1178 struct mlx4_cmd_mailbox *outbox,
1179 struct mlx4_cmd_info *cmd);
1180 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1181 struct mlx4_vhcr *vhcr,
1182 struct mlx4_cmd_mailbox *inbox,
1183 struct mlx4_cmd_mailbox *outbox,
1184 struct mlx4_cmd_info *cmd);
1185 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1186 struct mlx4_vhcr *vhcr,
1187 struct mlx4_cmd_mailbox *inbox,
1188 struct mlx4_cmd_mailbox *outbox,
1189 struct mlx4_cmd_info *cmd);
1190 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1191 struct mlx4_vhcr *vhcr,
1192 struct mlx4_cmd_mailbox *inbox,
1193 struct mlx4_cmd_mailbox *outbox,
1194 struct mlx4_cmd_info *cmd);
1195 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1196 struct mlx4_vhcr *vhcr,
1197 struct mlx4_cmd_mailbox *inbox,
1198 struct mlx4_cmd_mailbox *outbox,
1199 struct mlx4_cmd_info *cmd);
1200 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1201 struct mlx4_vhcr *vhcr,
1202 struct mlx4_cmd_mailbox *inbox,
1203 struct mlx4_cmd_mailbox *outbox,
1204 struct mlx4_cmd_info *cmd);
1205 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1207 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1208 int *gid_tbl_len, int *pkey_tbl_len);
1210 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1211 struct mlx4_vhcr *vhcr,
1212 struct mlx4_cmd_mailbox *inbox,
1213 struct mlx4_cmd_mailbox *outbox,
1214 struct mlx4_cmd_info *cmd);
1216 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1217 struct mlx4_vhcr *vhcr,
1218 struct mlx4_cmd_mailbox *inbox,
1219 struct mlx4_cmd_mailbox *outbox,
1220 struct mlx4_cmd_info *cmd);
1222 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1223 struct mlx4_vhcr *vhcr,
1224 struct mlx4_cmd_mailbox *inbox,
1225 struct mlx4_cmd_mailbox *outbox,
1226 struct mlx4_cmd_info *cmd);
1227 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1228 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1229 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1230 int block_mcast_loopback, enum mlx4_protocol prot,
1231 enum mlx4_steer_type steer);
1232 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1233 u8 gid[16], u8 port,
1234 int block_mcast_loopback,
1235 enum mlx4_protocol prot, u64 *reg_id);
1236 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1237 struct mlx4_vhcr *vhcr,
1238 struct mlx4_cmd_mailbox *inbox,
1239 struct mlx4_cmd_mailbox *outbox,
1240 struct mlx4_cmd_info *cmd);
1241 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1242 struct mlx4_vhcr *vhcr,
1243 struct mlx4_cmd_mailbox *inbox,
1244 struct mlx4_cmd_mailbox *outbox,
1245 struct mlx4_cmd_info *cmd);
1246 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1247 int port, void *buf);
1248 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1249 struct mlx4_cmd_mailbox *outbox);
1250 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1251 struct mlx4_vhcr *vhcr,
1252 struct mlx4_cmd_mailbox *inbox,
1253 struct mlx4_cmd_mailbox *outbox,
1254 struct mlx4_cmd_info *cmd);
1255 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1256 struct mlx4_vhcr *vhcr,
1257 struct mlx4_cmd_mailbox *inbox,
1258 struct mlx4_cmd_mailbox *outbox,
1259 struct mlx4_cmd_info *cmd);
1260 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1261 struct mlx4_vhcr *vhcr,
1262 struct mlx4_cmd_mailbox *inbox,
1263 struct mlx4_cmd_mailbox *outbox,
1264 struct mlx4_cmd_info *cmd);
1265 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1266 struct mlx4_vhcr *vhcr,
1267 struct mlx4_cmd_mailbox *inbox,
1268 struct mlx4_cmd_mailbox *outbox,
1269 struct mlx4_cmd_info *cmd);
1270 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1271 struct mlx4_vhcr *vhcr,
1272 struct mlx4_cmd_mailbox *inbox,
1273 struct mlx4_cmd_mailbox *outbox,
1274 struct mlx4_cmd_info *cmd);
1276 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1277 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1279 static inline void set_param_l(u64 *arg, u32 val)
1281 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1284 static inline void set_param_h(u64 *arg, u32 val)
1286 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1289 static inline u32 get_param_l(u64 *arg)
1291 return (u32) (*arg & 0xffffffff);
1294 static inline u32 get_param_h(u64 *arg)
1296 return (u32)(*arg >> 32);
1299 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1301 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1304 #define NOT_MASKED_PD_BITS 17
1306 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1308 void mlx4_init_quotas(struct mlx4_dev *dev);
1310 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1311 /* Returns the VF index of slave */
1312 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);