2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #include <linux/net_tstamp.h>
44 #ifdef CONFIG_MLX4_EN_DCB
45 #include <linux/dcbnl.h>
47 #include <linux/cpu_rmap.h>
48 #include <linux/ptp_clock_kernel.h>
50 #include <linux/mlx4/device.h>
51 #include <linux/mlx4/qp.h>
52 #include <linux/mlx4/cq.h>
53 #include <linux/mlx4/srq.h>
54 #include <linux/mlx4/doorbell.h>
55 #include <linux/mlx4/cmd.h>
58 #include "mlx4_stats.h"
60 #define DRV_NAME "mlx4_en"
61 #define DRV_VERSION "2.2-1"
62 #define DRV_RELDATE "Feb 2014"
64 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
71 #define MLX4_EN_PAGE_SHIFT 12
72 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
73 #define DEF_RX_RINGS 16
74 #define MAX_RX_RINGS 128
75 #define MIN_RX_RINGS 4
77 #define HEADROOM (2048 / TXBB_SIZE + 1)
78 #define STAMP_STRIDE 64
79 #define STAMP_DWORDS (STAMP_STRIDE / 4)
80 #define STAMP_SHIFT 31
81 #define STAMP_VAL 0x7fffffff
82 #define STATS_DELAY (HZ / 4)
83 #define SERVICE_TASK_DELAY (HZ / 4)
84 #define MAX_NUM_OF_FS_RULES 256
86 #define MLX4_EN_FILTER_HASH_SHIFT 4
87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
90 #define MAX_DESC_SIZE 512
91 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
94 * OS related constants and tunables
97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
98 #define MLX4_EN_PRIV_FLAGS_PHV 2
100 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
102 /* Use the maximum between 16384 and a single page */
103 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
105 #define MLX4_EN_ALLOC_PREFER_ORDER min_t(int, get_order(32768), \
106 PAGE_ALLOC_COSTLY_ORDER)
108 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU
109 * and 4K allocations) */
111 FRAG_SZ0 = 1536 - NET_IP_ALIGN,
114 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
116 #define MLX4_EN_MAX_RX_FRAGS 4
118 /* Maximum ring sizes */
119 #define MLX4_EN_MAX_TX_SIZE 8192
120 #define MLX4_EN_MAX_RX_SIZE 8192
122 /* Minimum ring size for our page-allocation scheme to work */
123 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
124 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
126 #define MLX4_EN_SMALL_PKT_SIZE 64
127 #define MLX4_EN_MIN_TX_RING_P_UP 1
128 #define MLX4_EN_MAX_TX_RING_P_UP 32
129 #define MLX4_EN_NUM_UP 8
130 #define MLX4_EN_DEF_TX_RING_SIZE 512
131 #define MLX4_EN_DEF_RX_RING_SIZE 1024
132 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
135 #define MLX4_EN_DEFAULT_TX_WORK 256
136 #define MLX4_EN_DOORBELL_BUDGET 8
138 /* Target number of packets to coalesce with interrupt moderation */
139 #define MLX4_EN_RX_COAL_TARGET 44
140 #define MLX4_EN_RX_COAL_TIME 0x10
142 #define MLX4_EN_TX_COAL_PKTS 16
143 #define MLX4_EN_TX_COAL_TIME 0x10
145 #define MLX4_EN_RX_RATE_LOW 400000
146 #define MLX4_EN_RX_COAL_TIME_LOW 0
147 #define MLX4_EN_RX_RATE_HIGH 450000
148 #define MLX4_EN_RX_COAL_TIME_HIGH 128
149 #define MLX4_EN_RX_SIZE_THRESH 1024
150 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
151 #define MLX4_EN_SAMPLE_INTERVAL 0
152 #define MLX4_EN_AVG_PKT_SMALL 256
154 #define MLX4_EN_AUTO_CONF 0xffff
156 #define MLX4_EN_DEF_RX_PAUSE 1
157 #define MLX4_EN_DEF_TX_PAUSE 1
159 /* Interval between successive polls in the Tx routine when polling is used
160 instead of interrupts (in per-core Tx rings) - should be power of 2 */
161 #define MLX4_EN_TX_POLL_MODER 16
162 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
164 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
165 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
166 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
168 #define MLX4_EN_MIN_MTU 46
169 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
170 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
172 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
173 #define ETH_BCAST 0xffffffffffffULL
175 #define MLX4_EN_LOOPBACK_RETRIES 5
176 #define MLX4_EN_LOOPBACK_TIMEOUT 100
178 #ifdef MLX4_EN_PERF_STAT
179 /* Number of samples to 'average' */
181 #define AVG_FACTOR 1024
183 #define INC_PERF_COUNTER(cnt) (++(cnt))
184 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
185 #define AVG_PERF_COUNTER(cnt, sample) \
186 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
187 #define GET_PERF_COUNTER(cnt) (cnt)
188 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
192 #define INC_PERF_COUNTER(cnt) do {} while (0)
193 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
194 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
195 #define GET_PERF_COUNTER(cnt) (0)
196 #define GET_AVG_PERF_COUNTER(cnt) (0)
197 #endif /* MLX4_EN_PERF_STAT */
199 /* Constants for TX flow */
201 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
211 /* keep tx types first */
214 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)
222 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
223 #define XNOR(x, y) (!(x) == !(y))
226 struct mlx4_en_tx_info {
240 } ____cacheline_aligned_in_smp;
243 #define MLX4_EN_BIT_DESC_OWN 0x80000000
244 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
245 #define MLX4_EN_MEMTYPE_PAD 0x100
246 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
249 struct mlx4_en_tx_desc {
250 struct mlx4_wqe_ctrl_seg ctrl;
252 struct mlx4_wqe_data_seg data; /* at least one data segment */
253 struct mlx4_wqe_lso_seg lso;
254 struct mlx4_wqe_inline_seg inl;
258 #define MLX4_EN_USE_SRQ 0x01000000
260 #define MLX4_EN_CX3_LOW_ID 0x1000
261 #define MLX4_EN_CX3_HIGH_ID 0x1005
263 struct mlx4_en_rx_alloc {
270 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
272 struct mlx4_en_page_cache {
277 } buf[MLX4_EN_CACHE_SIZE];
282 struct mlx4_en_tx_ring {
283 /* cache line used and dirtied in tx completion
284 * (mlx4_en_free_tx_buf())
288 unsigned long wake_queue;
289 struct netdev_queue *tx_queue;
290 u32 (*free_tx_desc)(struct mlx4_en_priv *priv,
291 struct mlx4_en_tx_ring *ring,
293 u64 timestamp, int napi_mode);
294 struct mlx4_en_rx_ring *recycle_ring;
296 /* cache line used and dirtied in mlx4_en_xmit() */
297 u32 prod ____cacheline_aligned_in_smp;
298 unsigned int tx_dropped;
300 unsigned long packets;
301 unsigned long tx_csum;
302 unsigned long tso_packets;
303 unsigned long xmit_more;
306 /* Following part should be mostly read */
309 u32 size; /* number of TXBBs */
314 struct mlx4_en_tx_info *tx_info;
322 /* Not used in fast path
323 * Only queue_stopped might be used if BQL is not properly working.
325 unsigned long queue_stopped;
326 struct mlx4_hwq_resources sp_wqres;
327 struct mlx4_qp sp_qp;
328 struct mlx4_qp_context sp_context;
329 cpumask_t sp_affinity_mask;
330 enum mlx4_qp_state sp_qp_state;
332 u16 sp_cqn; /* index of port CQ associated with this ring */
333 } ____cacheline_aligned_in_smp;
335 struct mlx4_en_rx_desc {
336 /* actual number of entries depends on rx ring stride */
337 struct mlx4_wqe_data_seg data[0];
340 struct mlx4_en_rx_ring {
341 struct mlx4_hwq_resources wqres;
342 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
343 u32 size ; /* number of Rx descs*/
348 u16 cqn; /* index of port CQ associated with this ring */
355 struct bpf_prog __rcu *xdp_prog;
356 struct mlx4_en_page_cache page_cache;
358 unsigned long packets;
359 unsigned long csum_ok;
360 unsigned long csum_none;
361 unsigned long csum_complete;
362 unsigned long xdp_drop;
363 unsigned long xdp_tx;
364 unsigned long xdp_tx_full;
365 unsigned long dropped;
366 int hwtstamp_rx_filter;
367 cpumask_var_t affinity_mask;
372 struct mlx4_hwq_resources wqres;
374 struct net_device *dev;
375 struct napi_struct napi;
382 struct mlx4_cqe *buf;
383 #define MLX4_EN_OPCODE_ERROR 0x1e
385 struct irq_desc *irq_desc;
388 struct mlx4_en_port_profile {
390 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
394 u8 num_tx_rings_p_up;
401 struct hwtstamp_config hwtstamp_config;
404 struct mlx4_en_profile {
410 u8 num_tx_rings_p_up;
411 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
415 struct mlx4_dev *dev;
416 struct pci_dev *pdev;
417 struct mutex state_lock;
418 struct net_device *pndev[MLX4_MAX_PORTS + 1];
419 struct net_device *upper[MLX4_MAX_PORTS + 1];
422 struct mlx4_en_profile profile;
424 struct workqueue_struct *workqueue;
425 struct device *dma_device;
426 void __iomem *uar_map;
427 struct mlx4_uar priv_uar;
431 u8 mac_removed[MLX4_MAX_PORTS + 1];
433 struct cyclecounter cycles;
434 seqlock_t clock_lock;
435 struct timecounter clock;
436 unsigned long last_overflow_check;
437 struct ptp_clock *ptp_clock;
438 struct ptp_clock_info ptp_clock_info;
439 struct notifier_block nb;
443 struct mlx4_en_rss_map {
445 struct mlx4_qp qps[MAX_RX_RINGS];
446 enum mlx4_qp_state state[MAX_RX_RINGS];
447 struct mlx4_qp indir_qp;
448 enum mlx4_qp_state indir_state;
451 enum mlx4_en_port_flag {
452 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
453 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
456 struct mlx4_en_port_state {
463 enum mlx4_en_mclist_act {
469 struct mlx4_en_mc_list {
470 struct list_head list;
471 enum mlx4_en_mclist_act action;
477 struct mlx4_en_frag_info {
482 #ifdef CONFIG_MLX4_EN_DCB
483 /* Minimal TC BW - setting to 0 will block traffic */
484 #define MLX4_EN_BW_MIN 1
485 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
487 #define MLX4_EN_TC_ETS 7
496 struct mlx4_en_cee_config {
498 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP];
502 struct ethtool_flow_id {
503 struct list_head list;
504 struct ethtool_rx_flow_spec flow_spec;
509 MLX4_EN_FLAG_PROMISC = (1 << 0),
510 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
511 /* whether we need to enable hardware loopback by putting dmac
514 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
515 /* whether we need to drop packets that hardware loopback-ed */
516 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
517 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
518 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5),
519 #ifdef CONFIG_MLX4_EN_DCB
520 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6),
524 #define PORT_BEACON_MAX_LIMIT (65535)
525 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
526 #define MLX4_EN_MAC_HASH_IDX 5
528 struct mlx4_en_stats_bitmap {
529 DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
530 struct mutex mutex; /* for mutual access to stats bitmap */
533 struct mlx4_en_priv {
534 struct mlx4_en_dev *mdev;
535 struct mlx4_en_port_profile *prof;
536 struct net_device *dev;
537 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
538 struct mlx4_en_port_state port_state;
539 spinlock_t stats_lock;
540 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
541 /* To allow rules removal while port is going down */
542 struct list_head ethtool_list;
544 unsigned long last_moder_packets[MAX_RX_RINGS];
545 unsigned long last_moder_tx_packets;
546 unsigned long last_moder_bytes[MAX_RX_RINGS];
547 unsigned long last_moder_jiffies;
548 int last_moder_time[MAX_RX_RINGS];
558 u16 adaptive_rx_coal;
561 u32 validate_loopback;
563 struct mlx4_hwq_resources res;
571 unsigned char current_mac[ETH_ALEN + 2];
578 struct mlx4_en_rss_map rss_map;
581 u8 num_tx_rings_p_up;
583 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
586 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
593 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];
594 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
595 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];
596 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
597 struct mlx4_qp drop_qp;
598 struct work_struct rx_mode_task;
599 struct work_struct watchdog_task;
600 struct work_struct linkstate_task;
601 struct delayed_work stats_task;
602 struct delayed_work service_task;
603 struct work_struct vxlan_add_task;
604 struct work_struct vxlan_del_task;
605 struct mlx4_en_perf_stats pstats;
606 struct mlx4_en_pkt_stats pkstats;
607 struct mlx4_en_counter_stats pf_stats;
608 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
609 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
610 struct mlx4_en_flow_stats_rx rx_flowstats;
611 struct mlx4_en_flow_stats_tx tx_flowstats;
612 struct mlx4_en_port_stats port_stats;
613 struct mlx4_en_xdp_stats xdp_stats;
614 struct mlx4_en_stats_bitmap stats_bitmap;
615 struct list_head mc_list;
616 struct list_head curr_list;
618 struct mlx4_en_stat_out_mbox hw_stats;
622 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
623 struct hwtstamp_config hwtstamp_config;
626 #ifdef CONFIG_MLX4_EN_DCB
627 #define MLX4_EN_DCB_ENABLED 0x3
629 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
630 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
631 struct mlx4_en_cee_config cee_config;
634 #ifdef CONFIG_RFS_ACCEL
635 spinlock_t filters_lock;
637 struct list_head filters;
638 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
644 u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
649 MLX4_EN_WOL_MAGIC = (1ULL << 61),
650 MLX4_EN_WOL_ENABLED = (1ULL << 62),
653 struct mlx4_mac_entry {
654 struct hlist_node hlist;
655 unsigned char mac[ETH_ALEN + 2];
660 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
662 return buf + idx * cqe_sz;
665 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
667 void mlx4_en_init_ptys2ethtool_map(void);
668 void mlx4_en_update_loopback_state(struct net_device *dev,
669 netdev_features_t features);
671 void mlx4_en_destroy_netdev(struct net_device *dev);
672 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
673 struct mlx4_en_port_profile *prof);
675 int mlx4_en_start_port(struct net_device *dev);
676 void mlx4_en_stop_port(struct net_device *dev, int detach);
678 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
679 struct mlx4_en_stats_bitmap *stats_bitmap,
680 u8 rx_ppp, u8 rx_pause,
681 u8 tx_ppp, u8 tx_pause);
683 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
684 struct mlx4_en_priv *tmp,
685 struct mlx4_en_port_profile *prof,
686 bool carry_xdp_prog);
687 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
688 struct mlx4_en_priv *tmp);
690 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
691 int entries, int ring, enum cq_type mode, int node);
692 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
693 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
695 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
696 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
697 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
699 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
700 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
701 void *accel_priv, select_queue_fallback_t fallback);
702 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
703 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
704 struct mlx4_en_rx_alloc *frame,
705 struct net_device *dev, unsigned int length,
706 int tx_ind, int *doorbell_pending);
707 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
708 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
709 struct mlx4_en_rx_alloc *frame);
711 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
712 struct mlx4_en_tx_ring **pring,
713 u32 size, u16 stride,
714 int node, int queue_index);
715 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
716 struct mlx4_en_tx_ring **pring);
717 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
718 struct mlx4_en_tx_ring *ring,
719 int cq, int user_prio);
720 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
721 struct mlx4_en_tx_ring *ring);
722 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
723 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
724 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
725 struct mlx4_en_rx_ring **pring,
726 u32 size, u16 stride, int node);
727 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
728 struct mlx4_en_rx_ring **pring,
729 u32 size, u16 stride);
730 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
731 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
732 struct mlx4_en_rx_ring *ring);
733 int mlx4_en_process_rx_cq(struct net_device *dev,
734 struct mlx4_en_cq *cq,
736 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
737 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
738 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
739 struct mlx4_en_tx_ring *ring,
740 int index, u8 owner, u64 timestamp,
742 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
743 struct mlx4_en_tx_ring *ring,
744 int index, u8 owner, u64 timestamp,
746 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
747 int is_tx, int rss, int qpn, int cqn, int user_prio,
748 struct mlx4_qp_context *context);
749 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
750 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
752 void mlx4_en_calc_rx_buf(struct net_device *dev);
753 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
754 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
755 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
756 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
757 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
758 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
760 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
761 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
763 void mlx4_en_fold_software_stats(struct net_device *dev);
764 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
765 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
767 #ifdef CONFIG_MLX4_EN_DCB
768 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
769 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
772 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
774 #ifdef CONFIG_RFS_ACCEL
775 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
778 #define MLX4_EN_NUM_SELF_TEST 5
779 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
780 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
782 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
783 ((dev->features & feature) ^ (new_features & feature))
785 int mlx4_en_reset_config(struct net_device *dev,
786 struct hwtstamp_config ts_config,
787 netdev_features_t new_features);
788 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
789 struct mlx4_en_stats_bitmap *stats_bitmap,
790 u8 rx_ppp, u8 rx_pause,
791 u8 tx_ppp, u8 tx_pause);
792 int mlx4_en_netdev_event(struct notifier_block *this,
793 unsigned long event, void *ptr);
796 * Functions for time stamping
798 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
799 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
800 struct skb_shared_hwtstamps *hwts,
802 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
803 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
807 extern const struct ethtool_ops mlx4_en_ethtool_ops;
812 * printk / logging functions
816 void en_print(const char *level, const struct mlx4_en_priv *priv,
817 const char *format, ...);
819 #define en_dbg(mlevel, priv, format, ...) \
821 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \
822 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \
824 #define en_warn(priv, format, ...) \
825 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
826 #define en_err(priv, format, ...) \
827 en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
828 #define en_info(priv, format, ...) \
829 en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
831 #define mlx4_err(mdev, format, ...) \
832 pr_err(DRV_NAME " %s: " format, \
833 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
834 #define mlx4_info(mdev, format, ...) \
835 pr_info(DRV_NAME " %s: " format, \
836 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
837 #define mlx4_warn(mdev, format, ...) \
838 pr_warn(DRV_NAME " %s: " format, \
839 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)