2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
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21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
42 struct mlx5e_rq_param {
43 u32 rqc[MLX5_ST_SZ_DW(rqc)];
44 struct mlx5_wq_param wq;
47 struct mlx5e_sq_param {
48 u32 sqc[MLX5_ST_SZ_DW(sqc)];
49 struct mlx5_wq_param wq;
54 struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
60 struct mlx5e_channel_param {
61 struct mlx5e_rq_param rq;
62 struct mlx5e_sq_param sq;
63 struct mlx5e_sq_param icosq;
64 struct mlx5e_cq_param rx_cq;
65 struct mlx5e_cq_param tx_cq;
66 struct mlx5e_cq_param icosq_cq;
69 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
71 struct mlx5_core_dev *mdev = priv->mdev;
74 port_state = mlx5_query_vport_state(mdev,
75 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
77 if (port_state == VPORT_STATE_UP)
78 netif_carrier_on(priv->netdev);
80 netif_carrier_off(priv->netdev);
83 static void mlx5e_update_carrier_work(struct work_struct *work)
85 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
88 mutex_lock(&priv->state_lock);
89 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
90 mlx5e_update_carrier(priv);
91 mutex_unlock(&priv->state_lock);
94 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
96 struct mlx5e_sw_stats *s = &priv->stats.sw;
97 struct mlx5e_rq_stats *rq_stats;
98 struct mlx5e_sq_stats *sq_stats;
99 u64 tx_offload_none = 0;
102 memset(s, 0, sizeof(*s));
103 for (i = 0; i < priv->params.num_channels; i++) {
104 rq_stats = &priv->channel[i]->rq.stats;
106 s->rx_packets += rq_stats->packets;
107 s->rx_bytes += rq_stats->bytes;
108 s->rx_lro_packets += rq_stats->lro_packets;
109 s->rx_lro_bytes += rq_stats->lro_bytes;
110 s->rx_csum_none += rq_stats->csum_none;
111 s->rx_csum_complete += rq_stats->csum_complete;
112 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
113 s->rx_wqe_err += rq_stats->wqe_err;
114 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
115 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
116 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
117 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
118 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
120 for (j = 0; j < priv->params.num_tc; j++) {
121 sq_stats = &priv->channel[i]->sq[j].stats;
123 s->tx_packets += sq_stats->packets;
124 s->tx_bytes += sq_stats->bytes;
125 s->tx_tso_packets += sq_stats->tso_packets;
126 s->tx_tso_bytes += sq_stats->tso_bytes;
127 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
128 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
129 s->tx_queue_stopped += sq_stats->stopped;
130 s->tx_queue_wake += sq_stats->wake;
131 s->tx_queue_dropped += sq_stats->dropped;
132 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
133 tx_offload_none += sq_stats->csum_none;
137 /* Update calculated offload counters */
138 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
139 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
141 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
142 priv->stats.pport.phy_counters,
143 counter_set.phys_layer_cntrs.link_down_events);
146 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
148 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
149 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
150 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
151 struct mlx5_core_dev *mdev = priv->mdev;
153 memset(in, 0, sizeof(in));
155 MLX5_SET(query_vport_counter_in, in, opcode,
156 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
157 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
158 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
160 memset(out, 0, outlen);
162 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
165 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
167 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
168 struct mlx5_core_dev *mdev = priv->mdev;
169 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
174 in = mlx5_vzalloc(sz);
178 MLX5_SET(ppcnt_reg, in, local_port, 1);
180 out = pstats->IEEE_802_3_counters;
181 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
182 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
184 out = pstats->RFC_2863_counters;
185 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
186 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
188 out = pstats->RFC_2819_counters;
189 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
190 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
192 out = pstats->phy_counters;
193 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
194 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
196 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
197 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
198 out = pstats->per_prio_counters[prio];
199 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
200 mlx5_core_access_reg(mdev, in, sz, out, sz,
201 MLX5_REG_PPCNT, 0, 0);
208 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
210 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
212 if (!priv->q_counter)
215 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
216 &qcnt->rx_out_of_buffer);
219 void mlx5e_update_stats(struct mlx5e_priv *priv)
221 mlx5e_update_q_counter(priv);
222 mlx5e_update_vport_counters(priv);
223 mlx5e_update_pport_counters(priv);
224 mlx5e_update_sw_counters(priv);
227 static void mlx5e_update_stats_work(struct work_struct *work)
229 struct delayed_work *dwork = to_delayed_work(work);
230 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
232 mutex_lock(&priv->state_lock);
233 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
234 mlx5e_update_stats(priv);
235 queue_delayed_work(priv->wq, dwork,
236 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
238 mutex_unlock(&priv->state_lock);
241 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
242 enum mlx5_dev_event event, unsigned long param)
244 struct mlx5e_priv *priv = vpriv;
246 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
250 case MLX5_DEV_EVENT_PORT_UP:
251 case MLX5_DEV_EVENT_PORT_DOWN:
252 queue_work(priv->wq, &priv->update_carrier_work);
260 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
262 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
265 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
267 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
268 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
271 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
272 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
274 static int mlx5e_create_rq(struct mlx5e_channel *c,
275 struct mlx5e_rq_param *param,
278 struct mlx5e_priv *priv = c->priv;
279 struct mlx5_core_dev *mdev = priv->mdev;
280 void *rqc = param->rqc;
281 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
287 param->wq.db_numa_node = cpu_to_node(c->cpu);
289 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
294 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
296 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
298 switch (priv->params.rq_wq_type) {
299 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
300 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
301 GFP_KERNEL, cpu_to_node(c->cpu));
304 goto err_rq_wq_destroy;
306 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
307 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
309 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
310 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
311 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
312 byte_count = rq->wqe_sz;
314 default: /* MLX5_WQ_TYPE_LINKED_LIST */
315 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
316 cpu_to_node(c->cpu));
319 goto err_rq_wq_destroy;
321 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
322 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
324 rq->wqe_sz = (priv->params.lro_en) ?
325 priv->params.lro_wqe_sz :
326 MLX5E_SW2HW_MTU(priv->netdev->mtu);
327 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
328 byte_count = rq->wqe_sz;
329 byte_count |= MLX5_HW_START_PADDING;
332 for (i = 0; i < wq_sz; i++) {
333 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
335 wqe->data.byte_count = cpu_to_be32(byte_count);
338 rq->wq_type = priv->params.rq_wq_type;
340 rq->netdev = c->netdev;
341 rq->tstamp = &priv->tstamp;
345 rq->mkey_be = c->mkey_be;
346 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
351 mlx5_wq_destroy(&rq->wq_ctrl);
356 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
358 switch (rq->wq_type) {
359 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
362 default: /* MLX5_WQ_TYPE_LINKED_LIST */
366 mlx5_wq_destroy(&rq->wq_ctrl);
369 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
371 struct mlx5e_priv *priv = rq->priv;
372 struct mlx5_core_dev *mdev = priv->mdev;
380 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
381 sizeof(u64) * rq->wq_ctrl.buf.npages;
382 in = mlx5_vzalloc(inlen);
386 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
387 wq = MLX5_ADDR_OF(rqc, rqc, wq);
389 memcpy(rqc, param->rqc, sizeof(param->rqc));
391 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
392 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
393 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
394 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
395 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
396 MLX5_ADAPTER_PAGE_SHIFT);
397 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
399 mlx5_fill_page_array(&rq->wq_ctrl.buf,
400 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
402 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
409 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
412 struct mlx5e_channel *c = rq->channel;
413 struct mlx5e_priv *priv = c->priv;
414 struct mlx5_core_dev *mdev = priv->mdev;
421 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
422 in = mlx5_vzalloc(inlen);
426 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
428 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
429 MLX5_SET(rqc, rqc, state, next_state);
431 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
438 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
440 struct mlx5e_channel *c = rq->channel;
441 struct mlx5e_priv *priv = c->priv;
442 struct mlx5_core_dev *mdev = priv->mdev;
449 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
450 in = mlx5_vzalloc(inlen);
454 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
456 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
457 MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
458 MLX5_SET(rqc, rqc, vsd, vsd);
459 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
461 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
468 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
470 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
473 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
475 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
476 struct mlx5e_channel *c = rq->channel;
477 struct mlx5e_priv *priv = c->priv;
478 struct mlx5_wq_ll *wq = &rq->wq;
480 while (time_before(jiffies, exp_time)) {
481 if (wq->cur_sz >= priv->params.min_rx_wqes)
490 static int mlx5e_open_rq(struct mlx5e_channel *c,
491 struct mlx5e_rq_param *param,
494 struct mlx5e_sq *sq = &c->icosq;
495 u16 pi = sq->pc & sq->wq.sz_m1;
498 err = mlx5e_create_rq(c, param, rq);
502 err = mlx5e_enable_rq(rq, param);
506 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
510 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
512 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
513 sq->ico_wqe_info[pi].num_wqebbs = 1;
514 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
519 mlx5e_disable_rq(rq);
521 mlx5e_destroy_rq(rq);
526 static void mlx5e_close_rq(struct mlx5e_rq *rq)
528 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
529 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
531 mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
532 while (!mlx5_wq_ll_is_empty(&rq->wq))
535 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
536 napi_synchronize(&rq->channel->napi);
538 mlx5e_disable_rq(rq);
539 mlx5e_destroy_rq(rq);
542 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
549 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
551 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
552 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
554 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
555 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
557 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
560 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
561 mlx5e_free_sq_db(sq);
565 sq->dma_fifo_mask = df_sz - 1;
570 static int mlx5e_create_sq(struct mlx5e_channel *c,
572 struct mlx5e_sq_param *param,
575 struct mlx5e_priv *priv = c->priv;
576 struct mlx5_core_dev *mdev = priv->mdev;
578 void *sqc = param->sqc;
579 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
582 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
586 param->wq.db_numa_node = cpu_to_node(c->cpu);
588 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
591 goto err_unmap_free_uar;
593 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
594 if (sq->uar.bf_map) {
595 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
596 sq->uar_map = sq->uar.bf_map;
598 sq->uar_map = sq->uar.map;
600 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
601 sq->max_inline = param->max_inline;
603 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
605 goto err_sq_wq_destroy;
608 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
610 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
613 cpu_to_node(c->cpu));
614 if (!sq->ico_wqe_info) {
621 txq_ix = c->ix + tc * priv->params.num_channels;
622 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
623 priv->txq_to_sq_map[txq_ix] = sq;
627 sq->tstamp = &priv->tstamp;
628 sq->mkey_be = c->mkey_be;
631 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
632 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
637 mlx5e_free_sq_db(sq);
640 mlx5_wq_destroy(&sq->wq_ctrl);
643 mlx5_unmap_free_uar(mdev, &sq->uar);
648 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
650 struct mlx5e_channel *c = sq->channel;
651 struct mlx5e_priv *priv = c->priv;
653 kfree(sq->ico_wqe_info);
654 mlx5e_free_sq_db(sq);
655 mlx5_wq_destroy(&sq->wq_ctrl);
656 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
659 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
661 struct mlx5e_channel *c = sq->channel;
662 struct mlx5e_priv *priv = c->priv;
663 struct mlx5_core_dev *mdev = priv->mdev;
671 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
672 sizeof(u64) * sq->wq_ctrl.buf.npages;
673 in = mlx5_vzalloc(inlen);
677 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
678 wq = MLX5_ADDR_OF(sqc, sqc, wq);
680 memcpy(sqc, param->sqc, sizeof(param->sqc));
682 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
683 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
684 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
685 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
686 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
688 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
689 MLX5_SET(wq, wq, uar_page, sq->uar.index);
690 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
691 MLX5_ADAPTER_PAGE_SHIFT);
692 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
694 mlx5_fill_page_array(&sq->wq_ctrl.buf,
695 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
697 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
704 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
706 struct mlx5e_channel *c = sq->channel;
707 struct mlx5e_priv *priv = c->priv;
708 struct mlx5_core_dev *mdev = priv->mdev;
715 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
716 in = mlx5_vzalloc(inlen);
720 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
722 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
723 MLX5_SET(sqc, sqc, state, next_state);
725 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
732 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
734 struct mlx5e_channel *c = sq->channel;
735 struct mlx5e_priv *priv = c->priv;
736 struct mlx5_core_dev *mdev = priv->mdev;
738 mlx5_core_destroy_sq(mdev, sq->sqn);
741 static int mlx5e_open_sq(struct mlx5e_channel *c,
743 struct mlx5e_sq_param *param,
748 err = mlx5e_create_sq(c, tc, param, sq);
752 err = mlx5e_enable_sq(sq, param);
756 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
761 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
762 netdev_tx_reset_queue(sq->txq);
763 netif_tx_start_queue(sq->txq);
769 mlx5e_disable_sq(sq);
771 mlx5e_destroy_sq(sq);
776 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
778 __netif_tx_lock_bh(txq);
779 netif_tx_stop_queue(txq);
780 __netif_tx_unlock_bh(txq);
783 static void mlx5e_close_sq(struct mlx5e_sq *sq)
786 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
787 /* prevent netif_tx_wake_queue */
788 napi_synchronize(&sq->channel->napi);
789 netif_tx_disable_queue(sq->txq);
791 /* ensure hw is notified of all pending wqes */
792 if (mlx5e_sq_has_room_for(sq, 1))
793 mlx5e_send_nop(sq, true);
795 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
798 while (sq->cc != sq->pc) /* wait till sq is empty */
801 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
802 napi_synchronize(&sq->channel->napi);
804 mlx5e_disable_sq(sq);
805 mlx5e_destroy_sq(sq);
808 static int mlx5e_create_cq(struct mlx5e_channel *c,
809 struct mlx5e_cq_param *param,
812 struct mlx5e_priv *priv = c->priv;
813 struct mlx5_core_dev *mdev = priv->mdev;
814 struct mlx5_core_cq *mcq = &cq->mcq;
820 param->wq.buf_numa_node = cpu_to_node(c->cpu);
821 param->wq.db_numa_node = cpu_to_node(c->cpu);
822 param->eq_ix = c->ix;
824 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
829 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
834 mcq->set_ci_db = cq->wq_ctrl.db.db;
835 mcq->arm_db = cq->wq_ctrl.db.db + 1;
838 mcq->vector = param->eq_ix;
839 mcq->comp = mlx5e_completion_event;
840 mcq->event = mlx5e_cq_error_event;
842 mcq->uar = &priv->cq_uar;
844 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
845 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
856 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
858 mlx5_wq_destroy(&cq->wq_ctrl);
861 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
863 struct mlx5e_priv *priv = cq->priv;
864 struct mlx5_core_dev *mdev = priv->mdev;
865 struct mlx5_core_cq *mcq = &cq->mcq;
870 unsigned int irqn_not_used;
874 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
875 sizeof(u64) * cq->wq_ctrl.buf.npages;
876 in = mlx5_vzalloc(inlen);
880 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
882 memcpy(cqc, param->cqc, sizeof(param->cqc));
884 mlx5_fill_page_array(&cq->wq_ctrl.buf,
885 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
887 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
889 MLX5_SET(cqc, cqc, c_eqn, eqn);
890 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
891 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
892 MLX5_ADAPTER_PAGE_SHIFT);
893 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
895 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
907 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
909 struct mlx5e_priv *priv = cq->priv;
910 struct mlx5_core_dev *mdev = priv->mdev;
912 mlx5_core_destroy_cq(mdev, &cq->mcq);
915 static int mlx5e_open_cq(struct mlx5e_channel *c,
916 struct mlx5e_cq_param *param,
918 u16 moderation_usecs,
919 u16 moderation_frames)
922 struct mlx5e_priv *priv = c->priv;
923 struct mlx5_core_dev *mdev = priv->mdev;
925 err = mlx5e_create_cq(c, param, cq);
929 err = mlx5e_enable_cq(cq, param);
933 if (MLX5_CAP_GEN(mdev, cq_moderation))
934 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
940 mlx5e_destroy_cq(cq);
945 static void mlx5e_close_cq(struct mlx5e_cq *cq)
947 mlx5e_disable_cq(cq);
948 mlx5e_destroy_cq(cq);
951 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
953 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
956 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
957 struct mlx5e_channel_param *cparam)
959 struct mlx5e_priv *priv = c->priv;
963 for (tc = 0; tc < c->num_tc; tc++) {
964 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
965 priv->params.tx_cq_moderation_usec,
966 priv->params.tx_cq_moderation_pkts);
968 goto err_close_tx_cqs;
974 for (tc--; tc >= 0; tc--)
975 mlx5e_close_cq(&c->sq[tc].cq);
980 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
984 for (tc = 0; tc < c->num_tc; tc++)
985 mlx5e_close_cq(&c->sq[tc].cq);
988 static int mlx5e_open_sqs(struct mlx5e_channel *c,
989 struct mlx5e_channel_param *cparam)
994 for (tc = 0; tc < c->num_tc; tc++) {
995 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1003 for (tc--; tc >= 0; tc--)
1004 mlx5e_close_sq(&c->sq[tc]);
1009 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1013 for (tc = 0; tc < c->num_tc; tc++)
1014 mlx5e_close_sq(&c->sq[tc]);
1017 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1021 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1022 priv->channeltc_to_txq_map[ix][i] =
1023 ix + i * priv->params.num_channels;
1026 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1027 struct mlx5e_channel_param *cparam,
1028 struct mlx5e_channel **cp)
1030 struct net_device *netdev = priv->netdev;
1031 int cpu = mlx5e_get_cpu(priv, ix);
1032 struct mlx5e_channel *c;
1035 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1042 c->pdev = &priv->mdev->pdev->dev;
1043 c->netdev = priv->netdev;
1044 c->mkey_be = cpu_to_be32(priv->mkey.key);
1045 c->num_tc = priv->params.num_tc;
1047 mlx5e_build_channeltc_to_txq_map(priv, ix);
1049 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1051 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1055 err = mlx5e_open_tx_cqs(c, cparam);
1057 goto err_close_icosq_cq;
1059 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1060 priv->params.rx_cq_moderation_usec,
1061 priv->params.rx_cq_moderation_pkts);
1063 goto err_close_tx_cqs;
1065 napi_enable(&c->napi);
1067 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1069 goto err_disable_napi;
1071 err = mlx5e_open_sqs(c, cparam);
1073 goto err_close_icosq;
1075 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1079 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1088 mlx5e_close_sq(&c->icosq);
1091 napi_disable(&c->napi);
1092 mlx5e_close_cq(&c->rq.cq);
1095 mlx5e_close_tx_cqs(c);
1098 mlx5e_close_cq(&c->icosq.cq);
1101 netif_napi_del(&c->napi);
1102 napi_hash_del(&c->napi);
1108 static void mlx5e_close_channel(struct mlx5e_channel *c)
1110 mlx5e_close_rq(&c->rq);
1112 mlx5e_close_sq(&c->icosq);
1113 napi_disable(&c->napi);
1114 mlx5e_close_cq(&c->rq.cq);
1115 mlx5e_close_tx_cqs(c);
1116 mlx5e_close_cq(&c->icosq.cq);
1117 netif_napi_del(&c->napi);
1119 napi_hash_del(&c->napi);
1125 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1126 struct mlx5e_rq_param *param)
1128 void *rqc = param->rqc;
1129 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1131 switch (priv->params.rq_wq_type) {
1132 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1133 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1134 priv->params.mpwqe_log_num_strides - 9);
1135 MLX5_SET(wq, wq, log_wqe_stride_size,
1136 priv->params.mpwqe_log_stride_sz - 6);
1137 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1139 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1140 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1143 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1144 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1145 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1146 MLX5_SET(wq, wq, pd, priv->pdn);
1147 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1149 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1150 param->wq.linear = 1;
1153 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1155 void *rqc = param->rqc;
1156 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1158 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1159 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1162 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1163 struct mlx5e_sq_param *param)
1165 void *sqc = param->sqc;
1166 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1168 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1169 MLX5_SET(wq, wq, pd, priv->pdn);
1171 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1174 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1175 struct mlx5e_sq_param *param)
1177 void *sqc = param->sqc;
1178 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1180 mlx5e_build_sq_param_common(priv, param);
1181 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1183 param->max_inline = priv->params.tx_max_inline;
1186 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1187 struct mlx5e_cq_param *param)
1189 void *cqc = param->cqc;
1191 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1194 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1195 struct mlx5e_cq_param *param)
1197 void *cqc = param->cqc;
1200 switch (priv->params.rq_wq_type) {
1201 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1202 log_cq_size = priv->params.log_rq_size +
1203 priv->params.mpwqe_log_num_strides;
1205 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1206 log_cq_size = priv->params.log_rq_size;
1209 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1210 if (priv->params.rx_cqe_compress) {
1211 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1212 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1215 mlx5e_build_common_cq_param(priv, param);
1218 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1219 struct mlx5e_cq_param *param)
1221 void *cqc = param->cqc;
1223 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1225 mlx5e_build_common_cq_param(priv, param);
1228 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1229 struct mlx5e_cq_param *param,
1232 void *cqc = param->cqc;
1234 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1236 mlx5e_build_common_cq_param(priv, param);
1239 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1240 struct mlx5e_sq_param *param,
1243 void *sqc = param->sqc;
1244 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1246 mlx5e_build_sq_param_common(priv, param);
1248 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1249 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1251 param->icosq = true;
1254 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1256 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1258 mlx5e_build_rq_param(priv, &cparam->rq);
1259 mlx5e_build_sq_param(priv, &cparam->sq);
1260 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1261 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1262 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1263 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1266 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1268 struct mlx5e_channel_param *cparam;
1269 int nch = priv->params.num_channels;
1274 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1277 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1278 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1280 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1282 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1283 goto err_free_txq_to_sq_map;
1285 mlx5e_build_channel_param(priv, cparam);
1287 for (i = 0; i < nch; i++) {
1288 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1290 goto err_close_channels;
1293 for (j = 0; j < nch; j++) {
1294 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1296 goto err_close_channels;
1303 for (i--; i >= 0; i--)
1304 mlx5e_close_channel(priv->channel[i]);
1306 err_free_txq_to_sq_map:
1307 kfree(priv->txq_to_sq_map);
1308 kfree(priv->channel);
1314 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1318 for (i = 0; i < priv->params.num_channels; i++)
1319 mlx5e_close_channel(priv->channel[i]);
1321 kfree(priv->txq_to_sq_map);
1322 kfree(priv->channel);
1325 static int mlx5e_rx_hash_fn(int hfunc)
1327 return (hfunc == ETH_RSS_HASH_TOP) ?
1328 MLX5_RX_HASH_FN_TOEPLITZ :
1329 MLX5_RX_HASH_FN_INVERTED_XOR8;
1332 static int mlx5e_bits_invert(unsigned long a, int size)
1337 for (i = 0; i < size; i++)
1338 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1343 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1347 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1351 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1352 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1354 ix = priv->params.indirection_rqt[ix];
1355 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1356 priv->channel[ix]->rq.rqn :
1358 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1362 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1365 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1366 priv->channel[ix]->rq.rqn :
1369 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1372 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
1374 struct mlx5_core_dev *mdev = priv->mdev;
1380 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1381 in = mlx5_vzalloc(inlen);
1385 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1387 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1388 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1390 if (sz > 1) /* RSS */
1391 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1393 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1395 err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
1401 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1403 mlx5_core_destroy_rqt(priv->mdev, rqtn);
1406 static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1408 int nch = mlx5e_get_max_num_channels(priv->mdev);
1414 rqtn = &priv->indir_rqtn;
1415 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1420 for (ix = 0; ix < nch; ix++) {
1421 rqtn = &priv->direct_tir[ix].rqtn;
1422 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1424 goto err_destroy_rqts;
1430 for (ix--; ix >= 0; ix--)
1431 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1433 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1438 static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1440 int nch = mlx5e_get_max_num_channels(priv->mdev);
1443 for (i = 0; i < nch; i++)
1444 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1446 mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1449 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1451 struct mlx5_core_dev *mdev = priv->mdev;
1457 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1458 in = mlx5_vzalloc(inlen);
1462 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1464 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1465 if (sz > 1) /* RSS */
1466 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1468 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1470 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1472 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1479 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1484 rqtn = priv->indir_rqtn;
1485 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1486 for (ix = 0; ix < priv->params.num_channels; ix++) {
1487 rqtn = priv->direct_tir[ix].rqtn;
1488 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1492 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1494 if (!priv->params.lro_en)
1497 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1499 MLX5_SET(tirc, tirc, lro_enable_mask,
1500 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1501 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1502 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1503 (priv->params.lro_wqe_sz -
1504 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1505 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1506 MLX5_CAP_ETH(priv->mdev,
1507 lro_timer_supported_periods[2]));
1510 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1512 MLX5_SET(tirc, tirc, rx_hash_fn,
1513 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1514 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1515 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1516 rx_hash_toeplitz_key);
1517 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1518 rx_hash_toeplitz_key);
1520 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1521 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1525 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1527 struct mlx5_core_dev *mdev = priv->mdev;
1536 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1537 in = mlx5_vzalloc(inlen);
1541 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1542 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1544 mlx5e_build_tir_ctx_lro(tirc, priv);
1546 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1547 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1553 for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1554 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1566 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1573 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1574 in = mlx5_vzalloc(inlen);
1578 MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1580 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1581 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1587 for (i = 0; i < priv->params.num_channels; i++) {
1588 err = mlx5_core_modify_tir(priv->mdev,
1589 priv->direct_tir[i].tirn, in,
1600 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1602 struct mlx5_core_dev *mdev = priv->mdev;
1603 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1606 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1610 /* Update vport context MTU */
1611 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1615 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1617 struct mlx5_core_dev *mdev = priv->mdev;
1621 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1622 if (err || !hw_mtu) /* fallback to port oper mtu */
1623 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1625 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1628 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1630 struct mlx5e_priv *priv = netdev_priv(netdev);
1634 err = mlx5e_set_mtu(priv, netdev->mtu);
1638 mlx5e_query_mtu(priv, &mtu);
1639 if (mtu != netdev->mtu)
1640 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1641 __func__, mtu, netdev->mtu);
1647 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1649 struct mlx5e_priv *priv = netdev_priv(netdev);
1650 int nch = priv->params.num_channels;
1651 int ntc = priv->params.num_tc;
1654 netdev_reset_tc(netdev);
1659 netdev_set_num_tc(netdev, ntc);
1661 for (tc = 0; tc < ntc; tc++)
1662 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1665 int mlx5e_open_locked(struct net_device *netdev)
1667 struct mlx5e_priv *priv = netdev_priv(netdev);
1671 set_bit(MLX5E_STATE_OPENED, &priv->state);
1673 mlx5e_netdev_set_tcs(netdev);
1675 num_txqs = priv->params.num_channels * priv->params.num_tc;
1676 netif_set_real_num_tx_queues(netdev, num_txqs);
1677 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1679 err = mlx5e_set_dev_port_mtu(netdev);
1681 goto err_clear_state_opened_flag;
1683 err = mlx5e_open_channels(priv);
1685 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1687 goto err_clear_state_opened_flag;
1690 err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1692 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1694 goto err_close_channels;
1697 mlx5e_redirect_rqts(priv);
1698 mlx5e_update_carrier(priv);
1699 mlx5e_timestamp_init(priv);
1700 #ifdef CONFIG_RFS_ACCEL
1701 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1704 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1709 mlx5e_close_channels(priv);
1710 err_clear_state_opened_flag:
1711 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1715 static int mlx5e_open(struct net_device *netdev)
1717 struct mlx5e_priv *priv = netdev_priv(netdev);
1720 mutex_lock(&priv->state_lock);
1721 err = mlx5e_open_locked(netdev);
1722 mutex_unlock(&priv->state_lock);
1727 int mlx5e_close_locked(struct net_device *netdev)
1729 struct mlx5e_priv *priv = netdev_priv(netdev);
1731 /* May already be CLOSED in case a previous configuration operation
1732 * (e.g RX/TX queue size change) that involves close&open failed.
1734 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1737 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1739 mlx5e_timestamp_cleanup(priv);
1740 netif_carrier_off(priv->netdev);
1741 mlx5e_redirect_rqts(priv);
1742 mlx5e_close_channels(priv);
1747 static int mlx5e_close(struct net_device *netdev)
1749 struct mlx5e_priv *priv = netdev_priv(netdev);
1752 mutex_lock(&priv->state_lock);
1753 err = mlx5e_close_locked(netdev);
1754 mutex_unlock(&priv->state_lock);
1759 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1760 struct mlx5e_rq *rq,
1761 struct mlx5e_rq_param *param)
1763 struct mlx5_core_dev *mdev = priv->mdev;
1764 void *rqc = param->rqc;
1765 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1768 param->wq.db_numa_node = param->wq.buf_numa_node;
1770 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1780 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1781 struct mlx5e_cq *cq,
1782 struct mlx5e_cq_param *param)
1784 struct mlx5_core_dev *mdev = priv->mdev;
1785 struct mlx5_core_cq *mcq = &cq->mcq;
1790 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1795 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1798 mcq->set_ci_db = cq->wq_ctrl.db.db;
1799 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1800 *mcq->set_ci_db = 0;
1802 mcq->vector = param->eq_ix;
1803 mcq->comp = mlx5e_completion_event;
1804 mcq->event = mlx5e_cq_error_event;
1806 mcq->uar = &priv->cq_uar;
1813 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1815 struct mlx5e_cq_param cq_param;
1816 struct mlx5e_rq_param rq_param;
1817 struct mlx5e_rq *rq = &priv->drop_rq;
1818 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1821 memset(&cq_param, 0, sizeof(cq_param));
1822 memset(&rq_param, 0, sizeof(rq_param));
1823 mlx5e_build_drop_rq_param(&rq_param);
1825 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1829 err = mlx5e_enable_cq(cq, &cq_param);
1831 goto err_destroy_cq;
1833 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1835 goto err_disable_cq;
1837 err = mlx5e_enable_rq(rq, &rq_param);
1839 goto err_destroy_rq;
1844 mlx5e_destroy_rq(&priv->drop_rq);
1847 mlx5e_disable_cq(&priv->drop_rq.cq);
1850 mlx5e_destroy_cq(&priv->drop_rq.cq);
1855 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1857 mlx5e_disable_rq(&priv->drop_rq);
1858 mlx5e_destroy_rq(&priv->drop_rq);
1859 mlx5e_disable_cq(&priv->drop_rq.cq);
1860 mlx5e_destroy_cq(&priv->drop_rq.cq);
1863 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1865 struct mlx5_core_dev *mdev = priv->mdev;
1866 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1867 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1869 memset(in, 0, sizeof(in));
1871 MLX5_SET(tisc, tisc, prio, tc << 1);
1872 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1874 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1877 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1879 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1882 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1887 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1888 err = mlx5e_create_tis(priv, tc);
1890 goto err_close_tises;
1896 for (tc--; tc >= 0; tc--)
1897 mlx5e_destroy_tis(priv, tc);
1902 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1906 for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1907 mlx5e_destroy_tis(priv, tc);
1910 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1911 enum mlx5e_traffic_types tt)
1913 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1915 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1917 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1918 MLX5_HASH_FIELD_SEL_DST_IP)
1920 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1921 MLX5_HASH_FIELD_SEL_DST_IP |\
1922 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1923 MLX5_HASH_FIELD_SEL_L4_DPORT)
1925 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1926 MLX5_HASH_FIELD_SEL_DST_IP |\
1927 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1929 mlx5e_build_tir_ctx_lro(tirc, priv);
1931 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1932 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
1933 mlx5e_build_tir_ctx_hash(tirc, priv);
1936 case MLX5E_TT_IPV4_TCP:
1937 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1938 MLX5_L3_PROT_TYPE_IPV4);
1939 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1940 MLX5_L4_PROT_TYPE_TCP);
1941 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1942 MLX5_HASH_IP_L4PORTS);
1945 case MLX5E_TT_IPV6_TCP:
1946 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1947 MLX5_L3_PROT_TYPE_IPV6);
1948 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1949 MLX5_L4_PROT_TYPE_TCP);
1950 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1951 MLX5_HASH_IP_L4PORTS);
1954 case MLX5E_TT_IPV4_UDP:
1955 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1956 MLX5_L3_PROT_TYPE_IPV4);
1957 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1958 MLX5_L4_PROT_TYPE_UDP);
1959 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1960 MLX5_HASH_IP_L4PORTS);
1963 case MLX5E_TT_IPV6_UDP:
1964 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1965 MLX5_L3_PROT_TYPE_IPV6);
1966 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1967 MLX5_L4_PROT_TYPE_UDP);
1968 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1969 MLX5_HASH_IP_L4PORTS);
1972 case MLX5E_TT_IPV4_IPSEC_AH:
1973 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1974 MLX5_L3_PROT_TYPE_IPV4);
1975 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1976 MLX5_HASH_IP_IPSEC_SPI);
1979 case MLX5E_TT_IPV6_IPSEC_AH:
1980 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1981 MLX5_L3_PROT_TYPE_IPV6);
1982 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1983 MLX5_HASH_IP_IPSEC_SPI);
1986 case MLX5E_TT_IPV4_IPSEC_ESP:
1987 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1988 MLX5_L3_PROT_TYPE_IPV4);
1989 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1990 MLX5_HASH_IP_IPSEC_SPI);
1993 case MLX5E_TT_IPV6_IPSEC_ESP:
1994 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1995 MLX5_L3_PROT_TYPE_IPV6);
1996 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1997 MLX5_HASH_IP_IPSEC_SPI);
2001 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2002 MLX5_L3_PROT_TYPE_IPV4);
2003 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2008 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2009 MLX5_L3_PROT_TYPE_IPV6);
2010 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2015 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2019 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2022 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2024 mlx5e_build_tir_ctx_lro(tirc, priv);
2026 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2027 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2028 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2031 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2033 int nch = mlx5e_get_max_num_channels(priv->mdev);
2042 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2043 in = mlx5_vzalloc(inlen);
2048 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2049 memset(in, 0, inlen);
2050 tirn = &priv->indir_tirn[tt];
2051 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2052 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2053 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2055 goto err_destroy_tirs;
2059 for (ix = 0; ix < nch; ix++) {
2060 memset(in, 0, inlen);
2061 tirn = &priv->direct_tir[ix].tirn;
2062 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2063 mlx5e_build_direct_tir_ctx(priv, tirc,
2064 priv->direct_tir[ix].rqtn);
2065 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2067 goto err_destroy_ch_tirs;
2074 err_destroy_ch_tirs:
2075 for (ix--; ix >= 0; ix--)
2076 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2079 for (tt--; tt >= 0; tt--)
2080 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2087 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
2089 int nch = mlx5e_get_max_num_channels(priv->mdev);
2092 for (i = 0; i < nch; i++)
2093 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2095 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2096 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
2099 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2104 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2107 for (i = 0; i < priv->params.num_channels; i++) {
2108 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2116 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2118 struct mlx5e_priv *priv = netdev_priv(netdev);
2122 if (tc && tc != MLX5E_MAX_NUM_TC)
2125 mutex_lock(&priv->state_lock);
2127 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2129 mlx5e_close_locked(priv->netdev);
2131 priv->params.num_tc = tc ? tc : 1;
2134 err = mlx5e_open_locked(priv->netdev);
2136 mutex_unlock(&priv->state_lock);
2141 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2142 __be16 proto, struct tc_to_netdev *tc)
2144 struct mlx5e_priv *priv = netdev_priv(dev);
2146 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2150 case TC_SETUP_CLSFLOWER:
2151 switch (tc->cls_flower->command) {
2152 case TC_CLSFLOWER_REPLACE:
2153 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2154 case TC_CLSFLOWER_DESTROY:
2155 return mlx5e_delete_flower(priv, tc->cls_flower);
2156 case TC_CLSFLOWER_STATS:
2157 return mlx5e_stats_flower(priv, tc->cls_flower);
2164 if (tc->type != TC_SETUP_MQPRIO)
2167 return mlx5e_setup_tc(dev, tc->tc);
2170 static struct rtnl_link_stats64 *
2171 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2173 struct mlx5e_priv *priv = netdev_priv(dev);
2174 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2175 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2176 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2178 stats->rx_packets = sstats->rx_packets;
2179 stats->rx_bytes = sstats->rx_bytes;
2180 stats->tx_packets = sstats->tx_packets;
2181 stats->tx_bytes = sstats->tx_bytes;
2183 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2184 stats->tx_dropped = sstats->tx_queue_dropped;
2186 stats->rx_length_errors =
2187 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2188 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2189 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2190 stats->rx_crc_errors =
2191 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2192 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2193 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2194 stats->tx_carrier_errors =
2195 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2196 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2197 stats->rx_frame_errors;
2198 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2200 /* vport multicast also counts packets that are dropped due to steering
2201 * or rx out of buffer
2204 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2209 static void mlx5e_set_rx_mode(struct net_device *dev)
2211 struct mlx5e_priv *priv = netdev_priv(dev);
2213 queue_work(priv->wq, &priv->set_rx_mode_work);
2216 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2218 struct mlx5e_priv *priv = netdev_priv(netdev);
2219 struct sockaddr *saddr = addr;
2221 if (!is_valid_ether_addr(saddr->sa_data))
2222 return -EADDRNOTAVAIL;
2224 netif_addr_lock_bh(netdev);
2225 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2226 netif_addr_unlock_bh(netdev);
2228 queue_work(priv->wq, &priv->set_rx_mode_work);
2233 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2236 netdev->features |= feature; \
2238 netdev->features &= ~feature; \
2241 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2243 static int set_feature_lro(struct net_device *netdev, bool enable)
2245 struct mlx5e_priv *priv = netdev_priv(netdev);
2246 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2249 mutex_lock(&priv->state_lock);
2251 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2252 mlx5e_close_locked(priv->netdev);
2254 priv->params.lro_en = enable;
2255 err = mlx5e_modify_tirs_lro(priv);
2257 netdev_err(netdev, "lro modify failed, %d\n", err);
2258 priv->params.lro_en = !enable;
2261 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2262 mlx5e_open_locked(priv->netdev);
2264 mutex_unlock(&priv->state_lock);
2269 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2271 struct mlx5e_priv *priv = netdev_priv(netdev);
2274 mlx5e_enable_vlan_filter(priv);
2276 mlx5e_disable_vlan_filter(priv);
2281 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2283 struct mlx5e_priv *priv = netdev_priv(netdev);
2285 if (!enable && mlx5e_tc_num_filters(priv)) {
2287 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2294 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2296 struct mlx5e_priv *priv = netdev_priv(netdev);
2297 struct mlx5_core_dev *mdev = priv->mdev;
2299 return mlx5_set_port_fcs(mdev, !enable);
2302 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2304 struct mlx5e_priv *priv = netdev_priv(netdev);
2307 mutex_lock(&priv->state_lock);
2309 priv->params.vlan_strip_disable = !enable;
2310 err = mlx5e_modify_rqs_vsd(priv, !enable);
2312 priv->params.vlan_strip_disable = enable;
2314 mutex_unlock(&priv->state_lock);
2319 #ifdef CONFIG_RFS_ACCEL
2320 static int set_feature_arfs(struct net_device *netdev, bool enable)
2322 struct mlx5e_priv *priv = netdev_priv(netdev);
2326 err = mlx5e_arfs_enable(priv);
2328 err = mlx5e_arfs_disable(priv);
2334 static int mlx5e_handle_feature(struct net_device *netdev,
2335 netdev_features_t wanted_features,
2336 netdev_features_t feature,
2337 mlx5e_feature_handler feature_handler)
2339 netdev_features_t changes = wanted_features ^ netdev->features;
2340 bool enable = !!(wanted_features & feature);
2343 if (!(changes & feature))
2346 err = feature_handler(netdev, enable);
2348 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2349 enable ? "Enable" : "Disable", feature, err);
2353 MLX5E_SET_FEATURE(netdev, feature, enable);
2357 static int mlx5e_set_features(struct net_device *netdev,
2358 netdev_features_t features)
2362 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2364 err |= mlx5e_handle_feature(netdev, features,
2365 NETIF_F_HW_VLAN_CTAG_FILTER,
2366 set_feature_vlan_filter);
2367 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2368 set_feature_tc_num_filters);
2369 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2370 set_feature_rx_all);
2371 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2372 set_feature_rx_vlan);
2373 #ifdef CONFIG_RFS_ACCEL
2374 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2378 return err ? -EINVAL : 0;
2381 #define MXL5_HW_MIN_MTU 64
2382 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2384 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2386 struct mlx5e_priv *priv = netdev_priv(netdev);
2387 struct mlx5_core_dev *mdev = priv->mdev;
2393 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2395 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2396 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2398 if (new_mtu > max_mtu || new_mtu < min_mtu) {
2400 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2401 __func__, new_mtu, min_mtu, max_mtu);
2405 mutex_lock(&priv->state_lock);
2407 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2409 mlx5e_close_locked(netdev);
2411 netdev->mtu = new_mtu;
2414 err = mlx5e_open_locked(netdev);
2416 mutex_unlock(&priv->state_lock);
2421 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2425 return mlx5e_hwstamp_set(dev, ifr);
2427 return mlx5e_hwstamp_get(dev, ifr);
2433 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2435 struct mlx5e_priv *priv = netdev_priv(dev);
2436 struct mlx5_core_dev *mdev = priv->mdev;
2438 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2441 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2443 struct mlx5e_priv *priv = netdev_priv(dev);
2444 struct mlx5_core_dev *mdev = priv->mdev;
2446 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2450 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2452 struct mlx5e_priv *priv = netdev_priv(dev);
2453 struct mlx5_core_dev *mdev = priv->mdev;
2455 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2458 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2460 struct mlx5e_priv *priv = netdev_priv(dev);
2461 struct mlx5_core_dev *mdev = priv->mdev;
2463 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2465 static int mlx5_vport_link2ifla(u8 esw_link)
2468 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2469 return IFLA_VF_LINK_STATE_DISABLE;
2470 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2471 return IFLA_VF_LINK_STATE_ENABLE;
2473 return IFLA_VF_LINK_STATE_AUTO;
2476 static int mlx5_ifla_link2vport(u8 ifla_link)
2478 switch (ifla_link) {
2479 case IFLA_VF_LINK_STATE_DISABLE:
2480 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2481 case IFLA_VF_LINK_STATE_ENABLE:
2482 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2484 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2487 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2490 struct mlx5e_priv *priv = netdev_priv(dev);
2491 struct mlx5_core_dev *mdev = priv->mdev;
2493 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2494 mlx5_ifla_link2vport(link_state));
2497 static int mlx5e_get_vf_config(struct net_device *dev,
2498 int vf, struct ifla_vf_info *ivi)
2500 struct mlx5e_priv *priv = netdev_priv(dev);
2501 struct mlx5_core_dev *mdev = priv->mdev;
2504 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2507 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2511 static int mlx5e_get_vf_stats(struct net_device *dev,
2512 int vf, struct ifla_vf_stats *vf_stats)
2514 struct mlx5e_priv *priv = netdev_priv(dev);
2515 struct mlx5_core_dev *mdev = priv->mdev;
2517 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2521 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2522 sa_family_t sa_family, __be16 port)
2524 struct mlx5e_priv *priv = netdev_priv(netdev);
2526 if (!mlx5e_vxlan_allowed(priv->mdev))
2529 mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1);
2532 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2533 sa_family_t sa_family, __be16 port)
2535 struct mlx5e_priv *priv = netdev_priv(netdev);
2537 if (!mlx5e_vxlan_allowed(priv->mdev))
2540 mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0);
2543 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2544 struct sk_buff *skb,
2545 netdev_features_t features)
2547 struct udphdr *udph;
2551 switch (vlan_get_protocol(skb)) {
2552 case htons(ETH_P_IP):
2553 proto = ip_hdr(skb)->protocol;
2555 case htons(ETH_P_IPV6):
2556 proto = ipv6_hdr(skb)->nexthdr;
2562 if (proto == IPPROTO_UDP) {
2563 udph = udp_hdr(skb);
2564 port = be16_to_cpu(udph->dest);
2567 /* Verify if UDP port is being offloaded by HW */
2568 if (port && mlx5e_vxlan_lookup_port(priv, port))
2572 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2573 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2576 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2577 struct net_device *netdev,
2578 netdev_features_t features)
2580 struct mlx5e_priv *priv = netdev_priv(netdev);
2582 features = vlan_features_check(skb, features);
2583 features = vxlan_features_check(skb, features);
2585 /* Validate if the tunneled packet is being offloaded by HW */
2586 if (skb->encapsulation &&
2587 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2588 return mlx5e_vxlan_features_check(priv, skb, features);
2593 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2594 .ndo_open = mlx5e_open,
2595 .ndo_stop = mlx5e_close,
2596 .ndo_start_xmit = mlx5e_xmit,
2597 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2598 .ndo_select_queue = mlx5e_select_queue,
2599 .ndo_get_stats64 = mlx5e_get_stats,
2600 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2601 .ndo_set_mac_address = mlx5e_set_mac,
2602 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2603 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2604 .ndo_set_features = mlx5e_set_features,
2605 .ndo_change_mtu = mlx5e_change_mtu,
2606 .ndo_do_ioctl = mlx5e_ioctl,
2607 #ifdef CONFIG_RFS_ACCEL
2608 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2612 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2613 .ndo_open = mlx5e_open,
2614 .ndo_stop = mlx5e_close,
2615 .ndo_start_xmit = mlx5e_xmit,
2616 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2617 .ndo_select_queue = mlx5e_select_queue,
2618 .ndo_get_stats64 = mlx5e_get_stats,
2619 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2620 .ndo_set_mac_address = mlx5e_set_mac,
2621 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2622 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2623 .ndo_set_features = mlx5e_set_features,
2624 .ndo_change_mtu = mlx5e_change_mtu,
2625 .ndo_do_ioctl = mlx5e_ioctl,
2626 .ndo_add_vxlan_port = mlx5e_add_vxlan_port,
2627 .ndo_del_vxlan_port = mlx5e_del_vxlan_port,
2628 .ndo_features_check = mlx5e_features_check,
2629 #ifdef CONFIG_RFS_ACCEL
2630 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2632 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2633 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
2634 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
2635 .ndo_set_vf_trust = mlx5e_set_vf_trust,
2636 .ndo_get_vf_config = mlx5e_get_vf_config,
2637 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2638 .ndo_get_vf_stats = mlx5e_get_vf_stats,
2641 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2643 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2645 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2646 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2647 !MLX5_CAP_ETH(mdev, csum_cap) ||
2648 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2649 !MLX5_CAP_ETH(mdev, vlan_cap) ||
2650 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2651 MLX5_CAP_FLOWTABLE(mdev,
2652 flow_table_properties_nic_receive.max_ft_level)
2654 mlx5_core_warn(mdev,
2655 "Not creating net device, some required device capabilities are missing\n");
2658 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2659 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2660 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2661 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2666 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2668 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2670 return bf_buf_size -
2671 sizeof(struct mlx5e_tx_wqe) +
2672 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2675 #ifdef CONFIG_MLX5_CORE_EN_DCB
2676 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2680 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2681 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2682 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2683 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2684 priv->params.ets.prio_tc[i] = i;
2687 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2688 priv->params.ets.prio_tc[0] = 1;
2689 priv->params.ets.prio_tc[1] = 0;
2693 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2694 u32 *indirection_rqt, int len,
2697 int node = mdev->priv.numa_node;
2698 int node_num_of_cores;
2702 node = first_online_node;
2704 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2706 if (node_num_of_cores)
2707 num_channels = min_t(int, num_channels, node_num_of_cores);
2709 for (i = 0; i < len; i++)
2710 indirection_rqt[i] = i % num_channels;
2713 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2715 return MLX5_CAP_GEN(mdev, striding_rq) &&
2716 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2717 MLX5_CAP_ETH(mdev, reg_umr_sq);
2720 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2722 enum pcie_link_width width;
2723 enum pci_bus_speed speed;
2726 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2730 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2734 case PCIE_SPEED_2_5GT:
2735 *pci_bw = 2500 * width;
2737 case PCIE_SPEED_5_0GT:
2738 *pci_bw = 5000 * width;
2740 case PCIE_SPEED_8_0GT:
2741 *pci_bw = 8000 * width;
2750 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2752 return (link_speed && pci_bw &&
2753 (pci_bw < 40000) && (pci_bw < link_speed));
2756 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2757 struct net_device *netdev,
2760 struct mlx5e_priv *priv = netdev_priv(netdev);
2764 priv->params.log_sq_size =
2765 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2766 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2767 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2768 MLX5_WQ_TYPE_LINKED_LIST;
2770 /* set CQE compression */
2771 priv->params.rx_cqe_compress_admin = false;
2772 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
2773 MLX5_CAP_GEN(mdev, vport_group_manager)) {
2774 mlx5e_get_max_linkspeed(mdev, &link_speed);
2775 mlx5e_get_pci_bw(mdev, &pci_bw);
2776 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
2777 link_speed, pci_bw);
2778 priv->params.rx_cqe_compress_admin =
2779 cqe_compress_heuristic(link_speed, pci_bw);
2782 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
2784 switch (priv->params.rq_wq_type) {
2785 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2786 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2787 priv->params.mpwqe_log_stride_sz =
2788 priv->params.rx_cqe_compress ?
2789 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
2790 MLX5_MPWRQ_LOG_STRIDE_SIZE;
2791 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
2792 priv->params.mpwqe_log_stride_sz;
2793 priv->params.lro_en = true;
2795 default: /* MLX5_WQ_TYPE_LINKED_LIST */
2796 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2799 mlx5_core_info(mdev,
2800 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
2801 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
2802 BIT(priv->params.log_rq_size),
2803 BIT(priv->params.mpwqe_log_stride_sz),
2804 priv->params.rx_cqe_compress_admin);
2806 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2807 BIT(priv->params.log_rq_size));
2808 priv->params.rx_cq_moderation_usec =
2809 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2810 priv->params.rx_cq_moderation_pkts =
2811 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2812 priv->params.tx_cq_moderation_usec =
2813 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2814 priv->params.tx_cq_moderation_pkts =
2815 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2816 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
2817 priv->params.num_tc = 1;
2818 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
2820 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2821 sizeof(priv->params.toeplitz_hash_key));
2823 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2824 MLX5E_INDIR_RQT_SIZE, num_channels);
2826 priv->params.lro_wqe_sz =
2827 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2830 priv->netdev = netdev;
2831 priv->params.num_channels = num_channels;
2833 #ifdef CONFIG_MLX5_CORE_EN_DCB
2834 mlx5e_ets_init(priv);
2837 mutex_init(&priv->state_lock);
2839 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2840 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2841 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2844 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2846 struct mlx5e_priv *priv = netdev_priv(netdev);
2848 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2849 if (is_zero_ether_addr(netdev->dev_addr) &&
2850 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2851 eth_hw_addr_random(netdev);
2852 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2856 static void mlx5e_build_netdev(struct net_device *netdev)
2858 struct mlx5e_priv *priv = netdev_priv(netdev);
2859 struct mlx5_core_dev *mdev = priv->mdev;
2863 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2865 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2866 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2867 #ifdef CONFIG_MLX5_CORE_EN_DCB
2868 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2871 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2874 netdev->watchdog_timeo = 15 * HZ;
2876 netdev->ethtool_ops = &mlx5e_ethtool_ops;
2878 netdev->vlan_features |= NETIF_F_SG;
2879 netdev->vlan_features |= NETIF_F_IP_CSUM;
2880 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
2881 netdev->vlan_features |= NETIF_F_GRO;
2882 netdev->vlan_features |= NETIF_F_TSO;
2883 netdev->vlan_features |= NETIF_F_TSO6;
2884 netdev->vlan_features |= NETIF_F_RXCSUM;
2885 netdev->vlan_features |= NETIF_F_RXHASH;
2887 if (!!MLX5_CAP_ETH(mdev, lro_cap))
2888 netdev->vlan_features |= NETIF_F_LRO;
2890 netdev->hw_features = netdev->vlan_features;
2891 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
2892 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2893 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2895 if (mlx5e_vxlan_allowed(mdev)) {
2896 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
2897 NETIF_F_GSO_UDP_TUNNEL_CSUM |
2898 NETIF_F_GSO_PARTIAL;
2899 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2900 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
2901 netdev->hw_enc_features |= NETIF_F_TSO;
2902 netdev->hw_enc_features |= NETIF_F_TSO6;
2903 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2904 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
2905 NETIF_F_GSO_PARTIAL;
2906 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
2909 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2912 netdev->hw_features |= NETIF_F_RXALL;
2914 netdev->features = netdev->hw_features;
2915 if (!priv->params.lro_en)
2916 netdev->features &= ~NETIF_F_LRO;
2919 netdev->features &= ~NETIF_F_RXALL;
2921 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2922 if (FT_CAP(flow_modify_en) &&
2923 FT_CAP(modify_root) &&
2924 FT_CAP(identified_miss_table_mode) &&
2925 FT_CAP(flow_table_modify)) {
2926 netdev->hw_features |= NETIF_F_HW_TC;
2927 #ifdef CONFIG_RFS_ACCEL
2928 netdev->hw_features |= NETIF_F_NTUPLE;
2932 netdev->features |= NETIF_F_HIGHDMA;
2934 netdev->priv_flags |= IFF_UNICAST_FLT;
2936 mlx5e_set_netdev_dev_addr(netdev);
2939 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2940 struct mlx5_core_mkey *mkey)
2942 struct mlx5_core_dev *mdev = priv->mdev;
2943 struct mlx5_create_mkey_mbox_in *in;
2946 in = mlx5_vzalloc(sizeof(*in));
2950 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2951 MLX5_PERM_LOCAL_READ |
2952 MLX5_ACCESS_MODE_PA;
2953 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2954 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2956 err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2964 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2966 struct mlx5_core_dev *mdev = priv->mdev;
2969 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2971 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2972 priv->q_counter = 0;
2976 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2978 if (!priv->q_counter)
2981 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2984 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2986 struct mlx5_core_dev *mdev = priv->mdev;
2987 struct mlx5_create_mkey_mbox_in *in;
2988 struct mlx5_mkey_seg *mkc;
2989 int inlen = sizeof(*in);
2991 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2994 in = mlx5_vzalloc(inlen);
2999 mkc->status = MLX5_MKEY_STATUS_FREE;
3000 mkc->flags = MLX5_PERM_UMR_EN |
3001 MLX5_PERM_LOCAL_READ |
3002 MLX5_PERM_LOCAL_WRITE |
3003 MLX5_ACCESS_MODE_MTT;
3005 mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3006 mkc->flags_pd = cpu_to_be32(priv->pdn);
3007 mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3008 mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
3009 mkc->log2_page_size = PAGE_SHIFT;
3011 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3019 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
3021 struct net_device *netdev;
3022 struct mlx5e_priv *priv;
3023 int nch = mlx5e_get_max_num_channels(mdev);
3026 if (mlx5e_check_required_hca_cap(mdev))
3029 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3030 nch * MLX5E_MAX_NUM_TC,
3033 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3037 mlx5e_build_netdev_priv(mdev, netdev, nch);
3038 mlx5e_build_netdev(netdev);
3040 netif_carrier_off(netdev);
3042 priv = netdev_priv(netdev);
3044 priv->wq = create_singlethread_workqueue("mlx5e");
3046 goto err_free_netdev;
3048 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
3050 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
3051 goto err_destroy_wq;
3054 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3056 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
3057 goto err_unmap_free_uar;
3060 err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3062 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3063 goto err_dealloc_pd;
3066 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
3068 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3069 goto err_dealloc_transport_domain;
3072 err = mlx5e_create_umr_mkey(priv);
3074 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3075 goto err_destroy_mkey;
3078 err = mlx5e_create_tises(priv);
3080 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
3081 goto err_destroy_umr_mkey;
3084 err = mlx5e_open_drop_rq(priv);
3086 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3087 goto err_destroy_tises;
3090 err = mlx5e_create_rqts(priv);
3092 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
3093 goto err_close_drop_rq;
3096 err = mlx5e_create_tirs(priv);
3098 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
3099 goto err_destroy_rqts;
3102 err = mlx5e_create_flow_steering(priv);
3104 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3105 goto err_destroy_tirs;
3108 mlx5e_create_q_counter(priv);
3110 mlx5e_init_l2_addr(priv);
3112 mlx5e_vxlan_init(priv);
3114 err = mlx5e_tc_init(priv);
3116 goto err_dealloc_q_counters;
3118 #ifdef CONFIG_MLX5_CORE_EN_DCB
3119 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3122 err = register_netdev(netdev);
3124 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3125 goto err_tc_cleanup;
3128 if (mlx5e_vxlan_allowed(mdev)) {
3130 vxlan_get_rx_port(netdev);
3134 mlx5e_enable_async_events(priv);
3135 queue_work(priv->wq, &priv->set_rx_mode_work);
3140 mlx5e_tc_cleanup(priv);
3142 err_dealloc_q_counters:
3143 mlx5e_destroy_q_counter(priv);
3144 mlx5e_destroy_flow_steering(priv);
3147 mlx5e_destroy_tirs(priv);
3150 mlx5e_destroy_rqts(priv);
3153 mlx5e_close_drop_rq(priv);
3156 mlx5e_destroy_tises(priv);
3158 err_destroy_umr_mkey:
3159 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3162 mlx5_core_destroy_mkey(mdev, &priv->mkey);
3164 err_dealloc_transport_domain:
3165 mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3168 mlx5_core_dealloc_pd(mdev, priv->pdn);
3171 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3174 destroy_workqueue(priv->wq);
3177 free_netdev(netdev);
3182 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3184 struct mlx5e_priv *priv = vpriv;
3185 struct net_device *netdev = priv->netdev;
3187 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3189 queue_work(priv->wq, &priv->set_rx_mode_work);
3190 mlx5e_disable_async_events(priv);
3191 flush_workqueue(priv->wq);
3192 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3193 netif_device_detach(netdev);
3194 mlx5e_close(netdev);
3196 unregister_netdev(netdev);
3199 mlx5e_tc_cleanup(priv);
3200 mlx5e_vxlan_cleanup(priv);
3201 mlx5e_destroy_q_counter(priv);
3202 mlx5e_destroy_flow_steering(priv);
3203 mlx5e_destroy_tirs(priv);
3204 mlx5e_destroy_rqts(priv);
3205 mlx5e_close_drop_rq(priv);
3206 mlx5e_destroy_tises(priv);
3207 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3208 mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
3209 mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
3210 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3211 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3212 cancel_delayed_work_sync(&priv->update_stats_work);
3213 destroy_workqueue(priv->wq);
3215 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3216 free_netdev(netdev);
3219 static void *mlx5e_get_netdev(void *vpriv)
3221 struct mlx5e_priv *priv = vpriv;
3223 return priv->netdev;
3226 static struct mlx5_interface mlx5e_interface = {
3227 .add = mlx5e_create_netdev,
3228 .remove = mlx5e_destroy_netdev,
3229 .event = mlx5e_async_event,
3230 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3231 .get_dev = mlx5e_get_netdev,
3234 void mlx5e_init(void)
3236 mlx5_register_interface(&mlx5e_interface);
3239 void mlx5e_cleanup(void)
3241 mlx5_unregister_interface(&mlx5e_interface);