drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 struct mlx5e_rq_param {
  43         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  44         struct mlx5_wq_param       wq;
  45 };
  46
  47 struct mlx5e_sq_param {
  48         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  49         struct mlx5_wq_param       wq;
  50         u16                        max_inline;
  51         bool                       icosq;
  52 };
  53
  54 struct mlx5e_cq_param {
  55         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  56         struct mlx5_wq_param       wq;
  57         u16                        eq_ix;
  58 };
  59
  60 struct mlx5e_channel_param {
  61         struct mlx5e_rq_param      rq;
  62         struct mlx5e_sq_param      sq;
  63         struct mlx5e_sq_param      icosq;
  64         struct mlx5e_cq_param      rx_cq;
  65         struct mlx5e_cq_param      tx_cq;
  66         struct mlx5e_cq_param      icosq_cq;
  67 };
  68
  69 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  70 {
  71         struct mlx5_core_dev *mdev = priv->mdev;
  72         u8 port_state;
  73
  74         port_state = mlx5_query_vport_state(mdev,
  75                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  76
  77         if (port_state == VPORT_STATE_UP)
  78                 netif_carrier_on(priv->netdev);
  79         else
  80                 netif_carrier_off(priv->netdev);
  81 }
  82
  83 static void mlx5e_update_carrier_work(struct work_struct *work)
  84 {
  85         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  86                                                update_carrier_work);
  87
  88         mutex_lock(&priv->state_lock);
  89         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  90                 mlx5e_update_carrier(priv);
  91         mutex_unlock(&priv->state_lock);
  92 }
  93
  94 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
  95 {
  96         struct mlx5e_sw_stats *s = &priv->stats.sw;
  97         struct mlx5e_rq_stats *rq_stats;
  98         struct mlx5e_sq_stats *sq_stats;
  99         u64 tx_offload_none = 0;
 100         int i, j;
 101
 102         memset(s, 0, sizeof(*s));
 103         for (i = 0; i < priv->params.num_channels; i++) {
 104                 rq_stats = &priv->channel[i]->rq.stats;
 105
 106                 s->rx_packets   += rq_stats->packets;
 107                 s->rx_bytes     += rq_stats->bytes;
 108                 s->rx_lro_packets += rq_stats->lro_packets;
 109                 s->rx_lro_bytes += rq_stats->lro_bytes;
 110                 s->rx_csum_none += rq_stats->csum_none;
 111                 s->rx_csum_complete += rq_stats->csum_complete;
 112                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 113                 s->rx_wqe_err   += rq_stats->wqe_err;
 114                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 115                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
 116                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 117                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 118                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 119
 120                 for (j = 0; j < priv->params.num_tc; j++) {
 121                         sq_stats = &priv->channel[i]->sq[j].stats;
 122
 123                         s->tx_packets           += sq_stats->packets;
 124                         s->tx_bytes             += sq_stats->bytes;
 125                         s->tx_tso_packets       += sq_stats->tso_packets;
 126                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 127                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 128                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 129                         s->tx_queue_stopped     += sq_stats->stopped;
 130                         s->tx_queue_wake        += sq_stats->wake;
 131                         s->tx_queue_dropped     += sq_stats->dropped;
 132                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 133                         tx_offload_none         += sq_stats->csum_none;
 134                 }
 135         }
 136
 137         /* Update calculated offload counters */
 138         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 139         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 140
 141         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 142                                 priv->stats.pport.phy_counters,
 143                                 counter_set.phys_layer_cntrs.link_down_events);
 144 }
 145
 146 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 147 {
 148         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 149         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 150         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 151         struct mlx5_core_dev *mdev = priv->mdev;
 152
 153         memset(in, 0, sizeof(in));
 154
 155         MLX5_SET(query_vport_counter_in, in, opcode,
 156                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 157         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 158         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 159
 160         memset(out, 0, outlen);
 161
 162         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 163 }
 164
 165 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 166 {
 167         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 168         struct mlx5_core_dev *mdev = priv->mdev;
 169         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 170         int prio;
 171         void *out;
 172         u32 *in;
 173
 174         in = mlx5_vzalloc(sz);
 175         if (!in)
 176                 goto free_out;
 177
 178         MLX5_SET(ppcnt_reg, in, local_port, 1);
 179
 180         out = pstats->IEEE_802_3_counters;
 181         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 182         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 183
 184         out = pstats->RFC_2863_counters;
 185         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 186         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 187
 188         out = pstats->RFC_2819_counters;
 189         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 190         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 191
 192         out = pstats->phy_counters;
 193         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 194         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 195
 196         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 197         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 198                 out = pstats->per_prio_counters[prio];
 199                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 200                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 201                                      MLX5_REG_PPCNT, 0, 0);
 202         }
 203
 204 free_out:
 205         kvfree(in);
 206 }
 207
 208 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 209 {
 210         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 211
 212         if (!priv->q_counter)
 213                 return;
 214
 215         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 216                                       &qcnt->rx_out_of_buffer);
 217 }
 218
 219 void mlx5e_update_stats(struct mlx5e_priv *priv)
 220 {
 221         mlx5e_update_q_counter(priv);
 222         mlx5e_update_vport_counters(priv);
 223         mlx5e_update_pport_counters(priv);
 224         mlx5e_update_sw_counters(priv);
 225 }
 226
 227 static void mlx5e_update_stats_work(struct work_struct *work)
 228 {
 229         struct delayed_work *dwork = to_delayed_work(work);
 230         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 231                                                update_stats_work);
 232         mutex_lock(&priv->state_lock);
 233         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 234                 mlx5e_update_stats(priv);
 235                 queue_delayed_work(priv->wq, dwork,
 236                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 237         }
 238         mutex_unlock(&priv->state_lock);
 239 }
 240
 241 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 242                               enum mlx5_dev_event event, unsigned long param)
 243 {
 244         struct mlx5e_priv *priv = vpriv;
 245
 246         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 247                 return;
 248
 249         switch (event) {
 250         case MLX5_DEV_EVENT_PORT_UP:
 251         case MLX5_DEV_EVENT_PORT_DOWN:
 252                 queue_work(priv->wq, &priv->update_carrier_work);
 253                 break;
 254
 255         default:
 256                 break;
 257         }
 258 }
 259
 260 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 261 {
 262         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 263 }
 264
 265 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 266 {
 267         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 268         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 269 }
 270
 271 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 272 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 273
 274 static int mlx5e_create_rq(struct mlx5e_channel *c,
 275                            struct mlx5e_rq_param *param,
 276                            struct mlx5e_rq *rq)
 277 {
 278         struct mlx5e_priv *priv = c->priv;
 279         struct mlx5_core_dev *mdev = priv->mdev;
 280         void *rqc = param->rqc;
 281         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 282         u32 byte_count;
 283         int wq_sz;
 284         int err;
 285         int i;
 286
 287         param->wq.db_numa_node = cpu_to_node(c->cpu);
 288
 289         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 290                                 &rq->wq_ctrl);
 291         if (err)
 292                 return err;
 293
 294         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 295
 296         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 297
 298         switch (priv->params.rq_wq_type) {
 299         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 300                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 301                                             GFP_KERNEL, cpu_to_node(c->cpu));
 302                 if (!rq->wqe_info) {
 303                         err = -ENOMEM;
 304                         goto err_rq_wq_destroy;
 305                 }
 306                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 307                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 308
 309                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 310                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 311                 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 312                 byte_count = rq->wqe_sz;
 313                 break;
 314         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 315                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 316                                        cpu_to_node(c->cpu));
 317                 if (!rq->skb) {
 318                         err = -ENOMEM;
 319                         goto err_rq_wq_destroy;
 320                 }
 321                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 322                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 323
 324                 rq->wqe_sz = (priv->params.lro_en) ?
 325                                 priv->params.lro_wqe_sz :
 326                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 327                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 328                 byte_count = rq->wqe_sz;
 329                 byte_count |= MLX5_HW_START_PADDING;
 330         }
 331
 332         for (i = 0; i < wq_sz; i++) {
 333                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 334
 335                 wqe->data.byte_count = cpu_to_be32(byte_count);
 336         }
 337
 338         rq->wq_type = priv->params.rq_wq_type;
 339         rq->pdev    = c->pdev;
 340         rq->netdev  = c->netdev;
 341         rq->tstamp  = &priv->tstamp;
 342         rq->channel = c;
 343         rq->ix      = c->ix;
 344         rq->priv    = c->priv;
 345         rq->mkey_be = c->mkey_be;
 346         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 347
 348         return 0;
 349
 350 err_rq_wq_destroy:
 351         mlx5_wq_destroy(&rq->wq_ctrl);
 352
 353         return err;
 354 }
 355
 356 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 357 {
 358         switch (rq->wq_type) {
 359         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 360                 kfree(rq->wqe_info);
 361                 break;
 362         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 363                 kfree(rq->skb);
 364         }
 365
 366         mlx5_wq_destroy(&rq->wq_ctrl);
 367 }
 368
 369 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 370 {
 371         struct mlx5e_priv *priv = rq->priv;
 372         struct mlx5_core_dev *mdev = priv->mdev;
 373
 374         void *in;
 375         void *rqc;
 376         void *wq;
 377         int inlen;
 378         int err;
 379
 380         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 381                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 382         in = mlx5_vzalloc(inlen);
 383         if (!in)
 384                 return -ENOMEM;
 385
 386         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 387         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 388
 389         memcpy(rqc, param->rqc, sizeof(param->rqc));
 390
 391         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 392         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 393         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 394         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 395         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 396                                                 MLX5_ADAPTER_PAGE_SHIFT);
 397         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 398
 399         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 400                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 401
 402         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 403
 404         kvfree(in);
 405
 406         return err;
 407 }
 408
 409 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 410                                  int next_state)
 411 {
 412         struct mlx5e_channel *c = rq->channel;
 413         struct mlx5e_priv *priv = c->priv;
 414         struct mlx5_core_dev *mdev = priv->mdev;
 415
 416         void *in;
 417         void *rqc;
 418         int inlen;
 419         int err;
 420
 421         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 422         in = mlx5_vzalloc(inlen);
 423         if (!in)
 424                 return -ENOMEM;
 425
 426         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 427
 428         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 429         MLX5_SET(rqc, rqc, state, next_state);
 430
 431         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 432
 433         kvfree(in);
 434
 435         return err;
 436 }
 437
 438 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 439 {
 440         struct mlx5e_channel *c = rq->channel;
 441         struct mlx5e_priv *priv = c->priv;
 442         struct mlx5_core_dev *mdev = priv->mdev;
 443
 444         void *in;
 445         void *rqc;
 446         int inlen;
 447         int err;
 448
 449         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 450         in = mlx5_vzalloc(inlen);
 451         if (!in)
 452                 return -ENOMEM;
 453
 454         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 455
 456         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 457         MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
 458         MLX5_SET(rqc, rqc, vsd, vsd);
 459         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 460
 461         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 462
 463         kvfree(in);
 464
 465         return err;
 466 }
 467
 468 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 469 {
 470         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 471 }
 472
 473 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 474 {
 475         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 476         struct mlx5e_channel *c = rq->channel;
 477         struct mlx5e_priv *priv = c->priv;
 478         struct mlx5_wq_ll *wq = &rq->wq;
 479
 480         while (time_before(jiffies, exp_time)) {
 481                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 482                         return 0;
 483
 484                 msleep(20);
 485         }
 486
 487         return -ETIMEDOUT;
 488 }
 489
 490 static int mlx5e_open_rq(struct mlx5e_channel *c,
 491                          struct mlx5e_rq_param *param,
 492                          struct mlx5e_rq *rq)
 493 {
 494         struct mlx5e_sq *sq = &c->icosq;
 495         u16 pi = sq->pc & sq->wq.sz_m1;
 496         int err;
 497
 498         err = mlx5e_create_rq(c, param, rq);
 499         if (err)
 500                 return err;
 501
 502         err = mlx5e_enable_rq(rq, param);
 503         if (err)
 504                 goto err_destroy_rq;
 505
 506         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 507         if (err)
 508                 goto err_disable_rq;
 509
 510         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 511
 512         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 513         sq->ico_wqe_info[pi].num_wqebbs = 1;
 514         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 515
 516         return 0;
 517
 518 err_disable_rq:
 519         mlx5e_disable_rq(rq);
 520 err_destroy_rq:
 521         mlx5e_destroy_rq(rq);
 522
 523         return err;
 524 }
 525
 526 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 527 {
 528         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 529         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 530
 531         mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 532         while (!mlx5_wq_ll_is_empty(&rq->wq))
 533                 msleep(20);
 534
 535         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 536         napi_synchronize(&rq->channel->napi);
 537
 538         mlx5e_disable_rq(rq);
 539         mlx5e_destroy_rq(rq);
 540 }
 541
 542 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 543 {
 544         kfree(sq->wqe_info);
 545         kfree(sq->dma_fifo);
 546         kfree(sq->skb);
 547 }
 548
 549 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 550 {
 551         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 552         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 553
 554         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 555         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 556                                     numa);
 557         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 558                                     numa);
 559
 560         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 561                 mlx5e_free_sq_db(sq);
 562                 return -ENOMEM;
 563         }
 564
 565         sq->dma_fifo_mask = df_sz - 1;
 566
 567         return 0;
 568 }
 569
 570 static int mlx5e_create_sq(struct mlx5e_channel *c,
 571                            int tc,
 572                            struct mlx5e_sq_param *param,
 573                            struct mlx5e_sq *sq)
 574 {
 575         struct mlx5e_priv *priv = c->priv;
 576         struct mlx5_core_dev *mdev = priv->mdev;
 577
 578         void *sqc = param->sqc;
 579         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 580         int err;
 581
 582         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 583         if (err)
 584                 return err;
 585
 586         param->wq.db_numa_node = cpu_to_node(c->cpu);
 587
 588         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 589                                  &sq->wq_ctrl);
 590         if (err)
 591                 goto err_unmap_free_uar;
 592
 593         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 594         if (sq->uar.bf_map) {
 595                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 596                 sq->uar_map = sq->uar.bf_map;
 597         } else {
 598                 sq->uar_map = sq->uar.map;
 599         }
 600         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 601         sq->max_inline  = param->max_inline;
 602
 603         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 604         if (err)
 605                 goto err_sq_wq_destroy;
 606
 607         if (param->icosq) {
 608                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 609
 610                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 611                                                 wq_sz,
 612                                                 GFP_KERNEL,
 613                                                 cpu_to_node(c->cpu));
 614                 if (!sq->ico_wqe_info) {
 615                         err = -ENOMEM;
 616                         goto err_free_sq_db;
 617                 }
 618         } else {
 619                 int txq_ix;
 620
 621                 txq_ix = c->ix + tc * priv->params.num_channels;
 622                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 623                 priv->txq_to_sq_map[txq_ix] = sq;
 624         }
 625
 626         sq->pdev      = c->pdev;
 627         sq->tstamp    = &priv->tstamp;
 628         sq->mkey_be   = c->mkey_be;
 629         sq->channel   = c;
 630         sq->tc        = tc;
 631         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 632         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 633
 634         return 0;
 635
 636 err_free_sq_db:
 637         mlx5e_free_sq_db(sq);
 638
 639 err_sq_wq_destroy:
 640         mlx5_wq_destroy(&sq->wq_ctrl);
 641
 642 err_unmap_free_uar:
 643         mlx5_unmap_free_uar(mdev, &sq->uar);
 644
 645         return err;
 646 }
 647
 648 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 649 {
 650         struct mlx5e_channel *c = sq->channel;
 651         struct mlx5e_priv *priv = c->priv;
 652
 653         kfree(sq->ico_wqe_info);
 654         mlx5e_free_sq_db(sq);
 655         mlx5_wq_destroy(&sq->wq_ctrl);
 656         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 657 }
 658
 659 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 660 {
 661         struct mlx5e_channel *c = sq->channel;
 662         struct mlx5e_priv *priv = c->priv;
 663         struct mlx5_core_dev *mdev = priv->mdev;
 664
 665         void *in;
 666         void *sqc;
 667         void *wq;
 668         int inlen;
 669         int err;
 670
 671         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 672                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 673         in = mlx5_vzalloc(inlen);
 674         if (!in)
 675                 return -ENOMEM;
 676
 677         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 678         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 679
 680         memcpy(sqc, param->sqc, sizeof(param->sqc));
 681
 682         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 683         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 684         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 685         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 686         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 687
 688         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 689         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 690         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 691                                           MLX5_ADAPTER_PAGE_SHIFT);
 692         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 693
 694         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 695                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 696
 697         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 698
 699         kvfree(in);
 700
 701         return err;
 702 }
 703
 704 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 705 {
 706         struct mlx5e_channel *c = sq->channel;
 707         struct mlx5e_priv *priv = c->priv;
 708         struct mlx5_core_dev *mdev = priv->mdev;
 709
 710         void *in;
 711         void *sqc;
 712         int inlen;
 713         int err;
 714
 715         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 716         in = mlx5_vzalloc(inlen);
 717         if (!in)
 718                 return -ENOMEM;
 719
 720         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 721
 722         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 723         MLX5_SET(sqc, sqc, state, next_state);
 724
 725         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 726
 727         kvfree(in);
 728
 729         return err;
 730 }
 731
 732 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 733 {
 734         struct mlx5e_channel *c = sq->channel;
 735         struct mlx5e_priv *priv = c->priv;
 736         struct mlx5_core_dev *mdev = priv->mdev;
 737
 738         mlx5_core_destroy_sq(mdev, sq->sqn);
 739 }
 740
 741 static int mlx5e_open_sq(struct mlx5e_channel *c,
 742                          int tc,
 743                          struct mlx5e_sq_param *param,
 744                          struct mlx5e_sq *sq)
 745 {
 746         int err;
 747
 748         err = mlx5e_create_sq(c, tc, param, sq);
 749         if (err)
 750                 return err;
 751
 752         err = mlx5e_enable_sq(sq, param);
 753         if (err)
 754                 goto err_destroy_sq;
 755
 756         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 757         if (err)
 758                 goto err_disable_sq;
 759
 760         if (sq->txq) {
 761                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 762                 netdev_tx_reset_queue(sq->txq);
 763                 netif_tx_start_queue(sq->txq);
 764         }
 765
 766         return 0;
 767
 768 err_disable_sq:
 769         mlx5e_disable_sq(sq);
 770 err_destroy_sq:
 771         mlx5e_destroy_sq(sq);
 772
 773         return err;
 774 }
 775
 776 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 777 {
 778         __netif_tx_lock_bh(txq);
 779         netif_tx_stop_queue(txq);
 780         __netif_tx_unlock_bh(txq);
 781 }
 782
 783 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 784 {
 785         if (sq->txq) {
 786                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 787                 /* prevent netif_tx_wake_queue */
 788                 napi_synchronize(&sq->channel->napi);
 789                 netif_tx_disable_queue(sq->txq);
 790
 791                 /* ensure hw is notified of all pending wqes */
 792                 if (mlx5e_sq_has_room_for(sq, 1))
 793                         mlx5e_send_nop(sq, true);
 794
 795                 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 796         }
 797
 798         while (sq->cc != sq->pc) /* wait till sq is empty */
 799                 msleep(20);
 800
 801         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 802         napi_synchronize(&sq->channel->napi);
 803
 804         mlx5e_disable_sq(sq);
 805         mlx5e_destroy_sq(sq);
 806 }
 807
 808 static int mlx5e_create_cq(struct mlx5e_channel *c,
 809                            struct mlx5e_cq_param *param,
 810                            struct mlx5e_cq *cq)
 811 {
 812         struct mlx5e_priv *priv = c->priv;
 813         struct mlx5_core_dev *mdev = priv->mdev;
 814         struct mlx5_core_cq *mcq = &cq->mcq;
 815         int eqn_not_used;
 816         unsigned int irqn;
 817         int err;
 818         u32 i;
 819
 820         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 821         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 822         param->eq_ix   = c->ix;
 823
 824         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 825                                &cq->wq_ctrl);
 826         if (err)
 827                 return err;
 828
 829         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 830
 831         cq->napi        = &c->napi;
 832
 833         mcq->cqe_sz     = 64;
 834         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 835         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 836         *mcq->set_ci_db = 0;
 837         *mcq->arm_db    = 0;
 838         mcq->vector     = param->eq_ix;
 839         mcq->comp       = mlx5e_completion_event;
 840         mcq->event      = mlx5e_cq_error_event;
 841         mcq->irqn       = irqn;
 842         mcq->uar        = &priv->cq_uar;
 843
 844         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 845                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 846
 847                 cqe->op_own = 0xf1;
 848         }
 849
 850         cq->channel = c;
 851         cq->priv = priv;
 852
 853         return 0;
 854 }
 855
 856 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 857 {
 858         mlx5_wq_destroy(&cq->wq_ctrl);
 859 }
 860
 861 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 862 {
 863         struct mlx5e_priv *priv = cq->priv;
 864         struct mlx5_core_dev *mdev = priv->mdev;
 865         struct mlx5_core_cq *mcq = &cq->mcq;
 866
 867         void *in;
 868         void *cqc;
 869         int inlen;
 870         unsigned int irqn_not_used;
 871         int eqn;
 872         int err;
 873
 874         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 875                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 876         in = mlx5_vzalloc(inlen);
 877         if (!in)
 878                 return -ENOMEM;
 879
 880         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 881
 882         memcpy(cqc, param->cqc, sizeof(param->cqc));
 883
 884         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 885                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 886
 887         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 888
 889         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 890         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 891         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 892                                             MLX5_ADAPTER_PAGE_SHIFT);
 893         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 894
 895         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 896
 897         kvfree(in);
 898
 899         if (err)
 900                 return err;
 901
 902         mlx5e_cq_arm(cq);
 903
 904         return 0;
 905 }
 906
 907 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 908 {
 909         struct mlx5e_priv *priv = cq->priv;
 910         struct mlx5_core_dev *mdev = priv->mdev;
 911
 912         mlx5_core_destroy_cq(mdev, &cq->mcq);
 913 }
 914
 915 static int mlx5e_open_cq(struct mlx5e_channel *c,
 916                          struct mlx5e_cq_param *param,
 917                          struct mlx5e_cq *cq,
 918                          u16 moderation_usecs,
 919                          u16 moderation_frames)
 920 {
 921         int err;
 922         struct mlx5e_priv *priv = c->priv;
 923         struct mlx5_core_dev *mdev = priv->mdev;
 924
 925         err = mlx5e_create_cq(c, param, cq);
 926         if (err)
 927                 return err;
 928
 929         err = mlx5e_enable_cq(cq, param);
 930         if (err)
 931                 goto err_destroy_cq;
 932
 933         if (MLX5_CAP_GEN(mdev, cq_moderation))
 934                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 935                                                moderation_usecs,
 936                                                moderation_frames);
 937         return 0;
 938
 939 err_destroy_cq:
 940         mlx5e_destroy_cq(cq);
 941
 942         return err;
 943 }
 944
 945 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 946 {
 947         mlx5e_disable_cq(cq);
 948         mlx5e_destroy_cq(cq);
 949 }
 950
 951 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 952 {
 953         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 954 }
 955
 956 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 957                              struct mlx5e_channel_param *cparam)
 958 {
 959         struct mlx5e_priv *priv = c->priv;
 960         int err;
 961         int tc;
 962
 963         for (tc = 0; tc < c->num_tc; tc++) {
 964                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 965                                     priv->params.tx_cq_moderation_usec,
 966                                     priv->params.tx_cq_moderation_pkts);
 967                 if (err)
 968                         goto err_close_tx_cqs;
 969         }
 970
 971         return 0;
 972
 973 err_close_tx_cqs:
 974         for (tc--; tc >= 0; tc--)
 975                 mlx5e_close_cq(&c->sq[tc].cq);
 976
 977         return err;
 978 }
 979
 980 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 981 {
 982         int tc;
 983
 984         for (tc = 0; tc < c->num_tc; tc++)
 985                 mlx5e_close_cq(&c->sq[tc].cq);
 986 }
 987
 988 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 989                           struct mlx5e_channel_param *cparam)
 990 {
 991         int err;
 992         int tc;
 993
 994         for (tc = 0; tc < c->num_tc; tc++) {
 995                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 996                 if (err)
 997                         goto err_close_sqs;
 998         }
 999
1000         return 0;
1001
1002 err_close_sqs:
1003         for (tc--; tc >= 0; tc--)
1004                 mlx5e_close_sq(&c->sq[tc]);
1005
1006         return err;
1007 }
1008
1009 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1010 {
1011         int tc;
1012
1013         for (tc = 0; tc < c->num_tc; tc++)
1014                 mlx5e_close_sq(&c->sq[tc]);
1015 }
1016
1017 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1018 {
1019         int i;
1020
1021         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1022                 priv->channeltc_to_txq_map[ix][i] =
1023                         ix + i * priv->params.num_channels;
1024 }
1025
1026 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1027                               struct mlx5e_channel_param *cparam,
1028                               struct mlx5e_channel **cp)
1029 {
1030         struct net_device *netdev = priv->netdev;
1031         int cpu = mlx5e_get_cpu(priv, ix);
1032         struct mlx5e_channel *c;
1033         int err;
1034
1035         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1036         if (!c)
1037                 return -ENOMEM;
1038
1039         c->priv     = priv;
1040         c->ix       = ix;
1041         c->cpu      = cpu;
1042         c->pdev     = &priv->mdev->pdev->dev;
1043         c->netdev   = priv->netdev;
1044         c->mkey_be  = cpu_to_be32(priv->mkey.key);
1045         c->num_tc   = priv->params.num_tc;
1046
1047         mlx5e_build_channeltc_to_txq_map(priv, ix);
1048
1049         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1050
1051         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1052         if (err)
1053                 goto err_napi_del;
1054
1055         err = mlx5e_open_tx_cqs(c, cparam);
1056         if (err)
1057                 goto err_close_icosq_cq;
1058
1059         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1060                             priv->params.rx_cq_moderation_usec,
1061                             priv->params.rx_cq_moderation_pkts);
1062         if (err)
1063                 goto err_close_tx_cqs;
1064
1065         napi_enable(&c->napi);
1066
1067         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1068         if (err)
1069                 goto err_disable_napi;
1070
1071         err = mlx5e_open_sqs(c, cparam);
1072         if (err)
1073                 goto err_close_icosq;
1074
1075         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1076         if (err)
1077                 goto err_close_sqs;
1078
1079         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1080         *cp = c;
1081
1082         return 0;
1083
1084 err_close_sqs:
1085         mlx5e_close_sqs(c);
1086
1087 err_close_icosq:
1088         mlx5e_close_sq(&c->icosq);
1089
1090 err_disable_napi:
1091         napi_disable(&c->napi);
1092         mlx5e_close_cq(&c->rq.cq);
1093
1094 err_close_tx_cqs:
1095         mlx5e_close_tx_cqs(c);
1096
1097 err_close_icosq_cq:
1098         mlx5e_close_cq(&c->icosq.cq);
1099
1100 err_napi_del:
1101         netif_napi_del(&c->napi);
1102         napi_hash_del(&c->napi);
1103         kfree(c);
1104
1105         return err;
1106 }
1107
1108 static void mlx5e_close_channel(struct mlx5e_channel *c)
1109 {
1110         mlx5e_close_rq(&c->rq);
1111         mlx5e_close_sqs(c);
1112         mlx5e_close_sq(&c->icosq);
1113         napi_disable(&c->napi);
1114         mlx5e_close_cq(&c->rq.cq);
1115         mlx5e_close_tx_cqs(c);
1116         mlx5e_close_cq(&c->icosq.cq);
1117         netif_napi_del(&c->napi);
1118
1119         napi_hash_del(&c->napi);
1120         synchronize_rcu();
1121
1122         kfree(c);
1123 }
1124
1125 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1126                                  struct mlx5e_rq_param *param)
1127 {
1128         void *rqc = param->rqc;
1129         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1130
1131         switch (priv->params.rq_wq_type) {
1132         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1133                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1134                          priv->params.mpwqe_log_num_strides - 9);
1135                 MLX5_SET(wq, wq, log_wqe_stride_size,
1136                          priv->params.mpwqe_log_stride_sz - 6);
1137                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1138                 break;
1139         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1140                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1141         }
1142
1143         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1144         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1145         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1146         MLX5_SET(wq, wq, pd,               priv->pdn);
1147         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1148
1149         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1150         param->wq.linear = 1;
1151 }
1152
1153 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1154 {
1155         void *rqc = param->rqc;
1156         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1157
1158         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1159         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1160 }
1161
1162 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1163                                         struct mlx5e_sq_param *param)
1164 {
1165         void *sqc = param->sqc;
1166         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1167
1168         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1169         MLX5_SET(wq, wq, pd,            priv->pdn);
1170
1171         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1172 }
1173
1174 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1175                                  struct mlx5e_sq_param *param)
1176 {
1177         void *sqc = param->sqc;
1178         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1179
1180         mlx5e_build_sq_param_common(priv, param);
1181         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1182
1183         param->max_inline = priv->params.tx_max_inline;
1184 }
1185
1186 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1187                                         struct mlx5e_cq_param *param)
1188 {
1189         void *cqc = param->cqc;
1190
1191         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1192 }
1193
1194 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1195                                     struct mlx5e_cq_param *param)
1196 {
1197         void *cqc = param->cqc;
1198         u8 log_cq_size;
1199
1200         switch (priv->params.rq_wq_type) {
1201         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1202                 log_cq_size = priv->params.log_rq_size +
1203                         priv->params.mpwqe_log_num_strides;
1204                 break;
1205         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1206                 log_cq_size = priv->params.log_rq_size;
1207         }
1208
1209         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1210         if (priv->params.rx_cqe_compress) {
1211                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1212                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1213         }
1214
1215         mlx5e_build_common_cq_param(priv, param);
1216 }
1217
1218 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1219                                     struct mlx5e_cq_param *param)
1220 {
1221         void *cqc = param->cqc;
1222
1223         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1224
1225         mlx5e_build_common_cq_param(priv, param);
1226 }
1227
1228 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1229                                      struct mlx5e_cq_param *param,
1230                                      u8 log_wq_size)
1231 {
1232         void *cqc = param->cqc;
1233
1234         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1235
1236         mlx5e_build_common_cq_param(priv, param);
1237 }
1238
1239 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1240                                     struct mlx5e_sq_param *param,
1241                                     u8 log_wq_size)
1242 {
1243         void *sqc = param->sqc;
1244         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1245
1246         mlx5e_build_sq_param_common(priv, param);
1247
1248         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1249         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1250
1251         param->icosq = true;
1252 }
1253
1254 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1255 {
1256         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1257
1258         mlx5e_build_rq_param(priv, &cparam->rq);
1259         mlx5e_build_sq_param(priv, &cparam->sq);
1260         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1261         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1262         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1263         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1264 }
1265
1266 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1267 {
1268         struct mlx5e_channel_param *cparam;
1269         int nch = priv->params.num_channels;
1270         int err = -ENOMEM;
1271         int i;
1272         int j;
1273
1274         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1275                                 GFP_KERNEL);
1276
1277         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1278                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1279
1280         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1281
1282         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1283                 goto err_free_txq_to_sq_map;
1284
1285         mlx5e_build_channel_param(priv, cparam);
1286
1287         for (i = 0; i < nch; i++) {
1288                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1289                 if (err)
1290                         goto err_close_channels;
1291         }
1292
1293         for (j = 0; j < nch; j++) {
1294                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1295                 if (err)
1296                         goto err_close_channels;
1297         }
1298
1299         kfree(cparam);
1300         return 0;
1301
1302 err_close_channels:
1303         for (i--; i >= 0; i--)
1304                 mlx5e_close_channel(priv->channel[i]);
1305
1306 err_free_txq_to_sq_map:
1307         kfree(priv->txq_to_sq_map);
1308         kfree(priv->channel);
1309         kfree(cparam);
1310
1311         return err;
1312 }
1313
1314 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1315 {
1316         int i;
1317
1318         for (i = 0; i < priv->params.num_channels; i++)
1319                 mlx5e_close_channel(priv->channel[i]);
1320
1321         kfree(priv->txq_to_sq_map);
1322         kfree(priv->channel);
1323 }
1324
1325 static int mlx5e_rx_hash_fn(int hfunc)
1326 {
1327         return (hfunc == ETH_RSS_HASH_TOP) ?
1328                MLX5_RX_HASH_FN_TOEPLITZ :
1329                MLX5_RX_HASH_FN_INVERTED_XOR8;
1330 }
1331
1332 static int mlx5e_bits_invert(unsigned long a, int size)
1333 {
1334         int inv = 0;
1335         int i;
1336
1337         for (i = 0; i < size; i++)
1338                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1339
1340         return inv;
1341 }
1342
1343 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1344 {
1345         int i;
1346
1347         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1348                 int ix = i;
1349                 u32 rqn;
1350
1351                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1352                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1353
1354                 ix = priv->params.indirection_rqt[ix];
1355                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1356                                 priv->channel[ix]->rq.rqn :
1357                                 priv->drop_rq.rqn;
1358                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1359         }
1360 }
1361
1362 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1363                                       int ix)
1364 {
1365         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1366                         priv->channel[ix]->rq.rqn :
1367                         priv->drop_rq.rqn;
1368
1369         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1370 }
1371
1372 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
1373 {
1374         struct mlx5_core_dev *mdev = priv->mdev;
1375         void *rqtc;
1376         int inlen;
1377         int err;
1378         u32 *in;
1379
1380         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1381         in = mlx5_vzalloc(inlen);
1382         if (!in)
1383                 return -ENOMEM;
1384
1385         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1386
1387         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1388         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1389
1390         if (sz > 1) /* RSS */
1391                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1392         else
1393                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1394
1395         err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
1396
1397         kvfree(in);
1398         return err;
1399 }
1400
1401 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1402 {
1403         mlx5_core_destroy_rqt(priv->mdev, rqtn);
1404 }
1405
1406 static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1407 {
1408         int nch = mlx5e_get_max_num_channels(priv->mdev);
1409         u32 *rqtn;
1410         int err;
1411         int ix;
1412
1413         /* Indirect RQT */
1414         rqtn = &priv->indir_rqtn;
1415         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1416         if (err)
1417                 return err;
1418
1419         /* Direct RQTs */
1420         for (ix = 0; ix < nch; ix++) {
1421                 rqtn = &priv->direct_tir[ix].rqtn;
1422                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1423                 if (err)
1424                         goto err_destroy_rqts;
1425         }
1426
1427         return 0;
1428
1429 err_destroy_rqts:
1430         for (ix--; ix >= 0; ix--)
1431                 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1432
1433         mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1434
1435         return err;
1436 }
1437
1438 static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1439 {
1440         int nch = mlx5e_get_max_num_channels(priv->mdev);
1441         int i;
1442
1443         for (i = 0; i < nch; i++)
1444                 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1445
1446         mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1447 }
1448
1449 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1450 {
1451         struct mlx5_core_dev *mdev = priv->mdev;
1452         void *rqtc;
1453         int inlen;
1454         u32 *in;
1455         int err;
1456
1457         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1458         in = mlx5_vzalloc(inlen);
1459         if (!in)
1460                 return -ENOMEM;
1461
1462         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1463
1464         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1465         if (sz > 1) /* RSS */
1466                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1467         else
1468                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1469
1470         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1471
1472         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1473
1474         kvfree(in);
1475
1476         return err;
1477 }
1478
1479 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1480 {
1481         u32 rqtn;
1482         int ix;
1483
1484         rqtn = priv->indir_rqtn;
1485         mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1486         for (ix = 0; ix < priv->params.num_channels; ix++) {
1487                 rqtn = priv->direct_tir[ix].rqtn;
1488                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1489         }
1490 }
1491
1492 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1493 {
1494         if (!priv->params.lro_en)
1495                 return;
1496
1497 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1498
1499         MLX5_SET(tirc, tirc, lro_enable_mask,
1500                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1501                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1502         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1503                  (priv->params.lro_wqe_sz -
1504                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1505         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1506                  MLX5_CAP_ETH(priv->mdev,
1507                               lro_timer_supported_periods[2]));
1508 }
1509
1510 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1511 {
1512         MLX5_SET(tirc, tirc, rx_hash_fn,
1513                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1514         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1515                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1516                                              rx_hash_toeplitz_key);
1517                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1518                                                rx_hash_toeplitz_key);
1519
1520                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1521                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1522         }
1523 }
1524
1525 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1526 {
1527         struct mlx5_core_dev *mdev = priv->mdev;
1528
1529         void *in;
1530         void *tirc;
1531         int inlen;
1532         int err;
1533         int tt;
1534         int ix;
1535
1536         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1537         in = mlx5_vzalloc(inlen);
1538         if (!in)
1539                 return -ENOMEM;
1540
1541         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1542         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1543
1544         mlx5e_build_tir_ctx_lro(tirc, priv);
1545
1546         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1547                 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1548                                            inlen);
1549                 if (err)
1550                         goto free_in;
1551         }
1552
1553         for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1554                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1555                                            in, inlen);
1556                 if (err)
1557                         goto free_in;
1558         }
1559
1560 free_in:
1561         kvfree(in);
1562
1563         return err;
1564 }
1565
1566 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1567 {
1568         void *in;
1569         int inlen;
1570         int err;
1571         int i;
1572
1573         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1574         in = mlx5_vzalloc(inlen);
1575         if (!in)
1576                 return -ENOMEM;
1577
1578         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1579
1580         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1581                 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1582                                            inlen);
1583                 if (err)
1584                         return err;
1585         }
1586
1587         for (i = 0; i < priv->params.num_channels; i++) {
1588                 err = mlx5_core_modify_tir(priv->mdev,
1589                                            priv->direct_tir[i].tirn, in,
1590                                            inlen);
1591                 if (err)
1592                         return err;
1593         }
1594
1595         kvfree(in);
1596
1597         return 0;
1598 }
1599
1600 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1601 {
1602         struct mlx5_core_dev *mdev = priv->mdev;
1603         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1604         int err;
1605
1606         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1607         if (err)
1608                 return err;
1609
1610         /* Update vport context MTU */
1611         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1612         return 0;
1613 }
1614
1615 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1616 {
1617         struct mlx5_core_dev *mdev = priv->mdev;
1618         u16 hw_mtu = 0;
1619         int err;
1620
1621         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1622         if (err || !hw_mtu) /* fallback to port oper mtu */
1623                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1624
1625         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1626 }
1627
1628 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1629 {
1630         struct mlx5e_priv *priv = netdev_priv(netdev);
1631         u16 mtu;
1632         int err;
1633
1634         err = mlx5e_set_mtu(priv, netdev->mtu);
1635         if (err)
1636                 return err;
1637
1638         mlx5e_query_mtu(priv, &mtu);
1639         if (mtu != netdev->mtu)
1640                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1641                             __func__, mtu, netdev->mtu);
1642
1643         netdev->mtu = mtu;
1644         return 0;
1645 }
1646
1647 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1648 {
1649         struct mlx5e_priv *priv = netdev_priv(netdev);
1650         int nch = priv->params.num_channels;
1651         int ntc = priv->params.num_tc;
1652         int tc;
1653
1654         netdev_reset_tc(netdev);
1655
1656         if (ntc == 1)
1657                 return;
1658
1659         netdev_set_num_tc(netdev, ntc);
1660
1661         for (tc = 0; tc < ntc; tc++)
1662                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1663 }
1664
1665 int mlx5e_open_locked(struct net_device *netdev)
1666 {
1667         struct mlx5e_priv *priv = netdev_priv(netdev);
1668         int num_txqs;
1669         int err;
1670
1671         set_bit(MLX5E_STATE_OPENED, &priv->state);
1672
1673         mlx5e_netdev_set_tcs(netdev);
1674
1675         num_txqs = priv->params.num_channels * priv->params.num_tc;
1676         netif_set_real_num_tx_queues(netdev, num_txqs);
1677         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1678
1679         err = mlx5e_set_dev_port_mtu(netdev);
1680         if (err)
1681                 goto err_clear_state_opened_flag;
1682
1683         err = mlx5e_open_channels(priv);
1684         if (err) {
1685                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1686                            __func__, err);
1687                 goto err_clear_state_opened_flag;
1688         }
1689
1690         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1691         if (err) {
1692                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1693                            __func__, err);
1694                 goto err_close_channels;
1695         }
1696
1697         mlx5e_redirect_rqts(priv);
1698         mlx5e_update_carrier(priv);
1699         mlx5e_timestamp_init(priv);
1700 #ifdef CONFIG_RFS_ACCEL
1701         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1702 #endif
1703
1704         queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1705
1706         return 0;
1707
1708 err_close_channels:
1709         mlx5e_close_channels(priv);
1710 err_clear_state_opened_flag:
1711         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1712         return err;
1713 }
1714
1715 static int mlx5e_open(struct net_device *netdev)
1716 {
1717         struct mlx5e_priv *priv = netdev_priv(netdev);
1718         int err;
1719
1720         mutex_lock(&priv->state_lock);
1721         err = mlx5e_open_locked(netdev);
1722         mutex_unlock(&priv->state_lock);
1723
1724         return err;
1725 }
1726
1727 int mlx5e_close_locked(struct net_device *netdev)
1728 {
1729         struct mlx5e_priv *priv = netdev_priv(netdev);
1730
1731         /* May already be CLOSED in case a previous configuration operation
1732          * (e.g RX/TX queue size change) that involves close&open failed.
1733          */
1734         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1735                 return 0;
1736
1737         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1738
1739         mlx5e_timestamp_cleanup(priv);
1740         netif_carrier_off(priv->netdev);
1741         mlx5e_redirect_rqts(priv);
1742         mlx5e_close_channels(priv);
1743
1744         return 0;
1745 }
1746
1747 static int mlx5e_close(struct net_device *netdev)
1748 {
1749         struct mlx5e_priv *priv = netdev_priv(netdev);
1750         int err;
1751
1752         mutex_lock(&priv->state_lock);
1753         err = mlx5e_close_locked(netdev);
1754         mutex_unlock(&priv->state_lock);
1755
1756         return err;
1757 }
1758
1759 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1760                                 struct mlx5e_rq *rq,
1761                                 struct mlx5e_rq_param *param)
1762 {
1763         struct mlx5_core_dev *mdev = priv->mdev;
1764         void *rqc = param->rqc;
1765         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1766         int err;
1767
1768         param->wq.db_numa_node = param->wq.buf_numa_node;
1769
1770         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1771                                 &rq->wq_ctrl);
1772         if (err)
1773                 return err;
1774
1775         rq->priv = priv;
1776
1777         return 0;
1778 }
1779
1780 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1781                                 struct mlx5e_cq *cq,
1782                                 struct mlx5e_cq_param *param)
1783 {
1784         struct mlx5_core_dev *mdev = priv->mdev;
1785         struct mlx5_core_cq *mcq = &cq->mcq;
1786         int eqn_not_used;
1787         unsigned int irqn;
1788         int err;
1789
1790         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1791                                &cq->wq_ctrl);
1792         if (err)
1793                 return err;
1794
1795         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1796
1797         mcq->cqe_sz     = 64;
1798         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1799         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1800         *mcq->set_ci_db = 0;
1801         *mcq->arm_db    = 0;
1802         mcq->vector     = param->eq_ix;
1803         mcq->comp       = mlx5e_completion_event;
1804         mcq->event      = mlx5e_cq_error_event;
1805         mcq->irqn       = irqn;
1806         mcq->uar        = &priv->cq_uar;
1807
1808         cq->priv = priv;
1809
1810         return 0;
1811 }
1812
1813 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1814 {
1815         struct mlx5e_cq_param cq_param;
1816         struct mlx5e_rq_param rq_param;
1817         struct mlx5e_rq *rq = &priv->drop_rq;
1818         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1819         int err;
1820
1821         memset(&cq_param, 0, sizeof(cq_param));
1822         memset(&rq_param, 0, sizeof(rq_param));
1823         mlx5e_build_drop_rq_param(&rq_param);
1824
1825         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1826         if (err)
1827                 return err;
1828
1829         err = mlx5e_enable_cq(cq, &cq_param);
1830         if (err)
1831                 goto err_destroy_cq;
1832
1833         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1834         if (err)
1835                 goto err_disable_cq;
1836
1837         err = mlx5e_enable_rq(rq, &rq_param);
1838         if (err)
1839                 goto err_destroy_rq;
1840
1841         return 0;
1842
1843 err_destroy_rq:
1844         mlx5e_destroy_rq(&priv->drop_rq);
1845
1846 err_disable_cq:
1847         mlx5e_disable_cq(&priv->drop_rq.cq);
1848
1849 err_destroy_cq:
1850         mlx5e_destroy_cq(&priv->drop_rq.cq);
1851
1852         return err;
1853 }
1854
1855 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1856 {
1857         mlx5e_disable_rq(&priv->drop_rq);
1858         mlx5e_destroy_rq(&priv->drop_rq);
1859         mlx5e_disable_cq(&priv->drop_rq.cq);
1860         mlx5e_destroy_cq(&priv->drop_rq.cq);
1861 }
1862
1863 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1864 {
1865         struct mlx5_core_dev *mdev = priv->mdev;
1866         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1867         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1868
1869         memset(in, 0, sizeof(in));
1870
1871         MLX5_SET(tisc, tisc, prio, tc << 1);
1872         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1873
1874         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1875 }
1876
1877 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1878 {
1879         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1880 }
1881
1882 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1883 {
1884         int err;
1885         int tc;
1886
1887         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1888                 err = mlx5e_create_tis(priv, tc);
1889                 if (err)
1890                         goto err_close_tises;
1891         }
1892
1893         return 0;
1894
1895 err_close_tises:
1896         for (tc--; tc >= 0; tc--)
1897                 mlx5e_destroy_tis(priv, tc);
1898
1899         return err;
1900 }
1901
1902 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1903 {
1904         int tc;
1905
1906         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1907                 mlx5e_destroy_tis(priv, tc);
1908 }
1909
1910 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1911                                       enum mlx5e_traffic_types tt)
1912 {
1913         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1914
1915         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1916
1917 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1918                                  MLX5_HASH_FIELD_SEL_DST_IP)
1919
1920 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1921                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1922                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1923                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1924
1925 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1926                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1927                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1928
1929         mlx5e_build_tir_ctx_lro(tirc, priv);
1930
1931         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1932         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
1933         mlx5e_build_tir_ctx_hash(tirc, priv);
1934
1935         switch (tt) {
1936         case MLX5E_TT_IPV4_TCP:
1937                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1938                          MLX5_L3_PROT_TYPE_IPV4);
1939                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1940                          MLX5_L4_PROT_TYPE_TCP);
1941                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1942                          MLX5_HASH_IP_L4PORTS);
1943                 break;
1944
1945         case MLX5E_TT_IPV6_TCP:
1946                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1947                          MLX5_L3_PROT_TYPE_IPV6);
1948                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1949                          MLX5_L4_PROT_TYPE_TCP);
1950                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1951                          MLX5_HASH_IP_L4PORTS);
1952                 break;
1953
1954         case MLX5E_TT_IPV4_UDP:
1955                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1956                          MLX5_L3_PROT_TYPE_IPV4);
1957                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1958                          MLX5_L4_PROT_TYPE_UDP);
1959                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1960                          MLX5_HASH_IP_L4PORTS);
1961                 break;
1962
1963         case MLX5E_TT_IPV6_UDP:
1964                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1965                          MLX5_L3_PROT_TYPE_IPV6);
1966                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1967                          MLX5_L4_PROT_TYPE_UDP);
1968                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1969                          MLX5_HASH_IP_L4PORTS);
1970                 break;
1971
1972         case MLX5E_TT_IPV4_IPSEC_AH:
1973                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1974                          MLX5_L3_PROT_TYPE_IPV4);
1975                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1976                          MLX5_HASH_IP_IPSEC_SPI);
1977                 break;
1978
1979         case MLX5E_TT_IPV6_IPSEC_AH:
1980                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1981                          MLX5_L3_PROT_TYPE_IPV6);
1982                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1983                          MLX5_HASH_IP_IPSEC_SPI);
1984                 break;
1985
1986         case MLX5E_TT_IPV4_IPSEC_ESP:
1987                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1988                          MLX5_L3_PROT_TYPE_IPV4);
1989                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1990                          MLX5_HASH_IP_IPSEC_SPI);
1991                 break;
1992
1993         case MLX5E_TT_IPV6_IPSEC_ESP:
1994                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1995                          MLX5_L3_PROT_TYPE_IPV6);
1996                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1997                          MLX5_HASH_IP_IPSEC_SPI);
1998                 break;
1999
2000         case MLX5E_TT_IPV4:
2001                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2002                          MLX5_L3_PROT_TYPE_IPV4);
2003                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2004                          MLX5_HASH_IP);
2005                 break;
2006
2007         case MLX5E_TT_IPV6:
2008                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2009                          MLX5_L3_PROT_TYPE_IPV6);
2010                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2011                          MLX5_HASH_IP);
2012                 break;
2013         default:
2014                 WARN_ONCE(true,
2015                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2016         }
2017 }
2018
2019 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2020                                        u32 rqtn)
2021 {
2022         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2023
2024         mlx5e_build_tir_ctx_lro(tirc, priv);
2025
2026         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2027         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2028         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2029 }
2030
2031 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2032 {
2033         int nch = mlx5e_get_max_num_channels(priv->mdev);
2034         void *tirc;
2035         int inlen;
2036         u32 *tirn;
2037         int err;
2038         u32 *in;
2039         int ix;
2040         int tt;
2041
2042         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2043         in = mlx5_vzalloc(inlen);
2044         if (!in)
2045                 return -ENOMEM;
2046
2047         /* indirect tirs */
2048         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2049                 memset(in, 0, inlen);
2050                 tirn = &priv->indir_tirn[tt];
2051                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2052                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2053                 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2054                 if (err)
2055                         goto err_destroy_tirs;
2056         }
2057
2058         /* direct tirs */
2059         for (ix = 0; ix < nch; ix++) {
2060                 memset(in, 0, inlen);
2061                 tirn = &priv->direct_tir[ix].tirn;
2062                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2063                 mlx5e_build_direct_tir_ctx(priv, tirc,
2064                                            priv->direct_tir[ix].rqtn);
2065                 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2066                 if (err)
2067                         goto err_destroy_ch_tirs;
2068         }
2069
2070         kvfree(in);
2071
2072         return 0;
2073
2074 err_destroy_ch_tirs:
2075         for (ix--; ix >= 0; ix--)
2076                 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2077
2078 err_destroy_tirs:
2079         for (tt--; tt >= 0; tt--)
2080                 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2081
2082         kvfree(in);
2083
2084         return err;
2085 }
2086
2087 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
2088 {
2089         int nch = mlx5e_get_max_num_channels(priv->mdev);
2090         int i;
2091
2092         for (i = 0; i < nch; i++)
2093                 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2094
2095         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2096                 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
2097 }
2098
2099 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2100 {
2101         int err = 0;
2102         int i;
2103
2104         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2105                 return 0;
2106
2107         for (i = 0; i < priv->params.num_channels; i++) {
2108                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2109                 if (err)
2110                         return err;
2111         }
2112
2113         return 0;
2114 }
2115
2116 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2117 {
2118         struct mlx5e_priv *priv = netdev_priv(netdev);
2119         bool was_opened;
2120         int err = 0;
2121
2122         if (tc && tc != MLX5E_MAX_NUM_TC)
2123                 return -EINVAL;
2124
2125         mutex_lock(&priv->state_lock);
2126
2127         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2128         if (was_opened)
2129                 mlx5e_close_locked(priv->netdev);
2130
2131         priv->params.num_tc = tc ? tc : 1;
2132
2133         if (was_opened)
2134                 err = mlx5e_open_locked(priv->netdev);
2135
2136         mutex_unlock(&priv->state_lock);
2137
2138         return err;
2139 }
2140
2141 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2142                               __be16 proto, struct tc_to_netdev *tc)
2143 {
2144         struct mlx5e_priv *priv = netdev_priv(dev);
2145
2146         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2147                 goto mqprio;
2148
2149         switch (tc->type) {
2150         case TC_SETUP_CLSFLOWER:
2151                 switch (tc->cls_flower->command) {
2152                 case TC_CLSFLOWER_REPLACE:
2153                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2154                 case TC_CLSFLOWER_DESTROY:
2155                         return mlx5e_delete_flower(priv, tc->cls_flower);
2156                 case TC_CLSFLOWER_STATS:
2157                         return mlx5e_stats_flower(priv, tc->cls_flower);
2158                 }
2159         default:
2160                 return -EOPNOTSUPP;
2161         }
2162
2163 mqprio:
2164         if (tc->type != TC_SETUP_MQPRIO)
2165                 return -EINVAL;
2166
2167         return mlx5e_setup_tc(dev, tc->tc);
2168 }
2169
2170 static struct rtnl_link_stats64 *
2171 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2172 {
2173         struct mlx5e_priv *priv = netdev_priv(dev);
2174         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2175         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2176         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2177
2178         stats->rx_packets = sstats->rx_packets;
2179         stats->rx_bytes   = sstats->rx_bytes;
2180         stats->tx_packets = sstats->tx_packets;
2181         stats->tx_bytes   = sstats->tx_bytes;
2182
2183         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2184         stats->tx_dropped = sstats->tx_queue_dropped;
2185
2186         stats->rx_length_errors =
2187                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2188                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2189                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2190         stats->rx_crc_errors =
2191                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2192         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2193         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2194         stats->tx_carrier_errors =
2195                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2196         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2197                            stats->rx_frame_errors;
2198         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2199
2200         /* vport multicast also counts packets that are dropped due to steering
2201          * or rx out of buffer
2202          */
2203         stats->multicast =
2204                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2205
2206         return stats;
2207 }
2208
2209 static void mlx5e_set_rx_mode(struct net_device *dev)
2210 {
2211         struct mlx5e_priv *priv = netdev_priv(dev);
2212
2213         queue_work(priv->wq, &priv->set_rx_mode_work);
2214 }
2215
2216 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2217 {
2218         struct mlx5e_priv *priv = netdev_priv(netdev);
2219         struct sockaddr *saddr = addr;
2220
2221         if (!is_valid_ether_addr(saddr->sa_data))
2222                 return -EADDRNOTAVAIL;
2223
2224         netif_addr_lock_bh(netdev);
2225         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2226         netif_addr_unlock_bh(netdev);
2227
2228         queue_work(priv->wq, &priv->set_rx_mode_work);
2229
2230         return 0;
2231 }
2232
2233 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2234         do {                                            \
2235                 if (enable)                             \
2236                         netdev->features |= feature;    \
2237                 else                                    \
2238                         netdev->features &= ~feature;   \
2239         } while (0)
2240
2241 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2242
2243 static int set_feature_lro(struct net_device *netdev, bool enable)
2244 {
2245         struct mlx5e_priv *priv = netdev_priv(netdev);
2246         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2247         int err;
2248
2249         mutex_lock(&priv->state_lock);
2250
2251         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2252                 mlx5e_close_locked(priv->netdev);
2253
2254         priv->params.lro_en = enable;
2255         err = mlx5e_modify_tirs_lro(priv);
2256         if (err) {
2257                 netdev_err(netdev, "lro modify failed, %d\n", err);
2258                 priv->params.lro_en = !enable;
2259         }
2260
2261         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2262                 mlx5e_open_locked(priv->netdev);
2263
2264         mutex_unlock(&priv->state_lock);
2265
2266         return err;
2267 }
2268
2269 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2270 {
2271         struct mlx5e_priv *priv = netdev_priv(netdev);
2272
2273         if (enable)
2274                 mlx5e_enable_vlan_filter(priv);
2275         else
2276                 mlx5e_disable_vlan_filter(priv);
2277
2278         return 0;
2279 }
2280
2281 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2282 {
2283         struct mlx5e_priv *priv = netdev_priv(netdev);
2284
2285         if (!enable && mlx5e_tc_num_filters(priv)) {
2286                 netdev_err(netdev,
2287                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2288                 return -EINVAL;
2289         }
2290
2291         return 0;
2292 }
2293
2294 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2295 {
2296         struct mlx5e_priv *priv = netdev_priv(netdev);
2297         struct mlx5_core_dev *mdev = priv->mdev;
2298
2299         return mlx5_set_port_fcs(mdev, !enable);
2300 }
2301
2302 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2303 {
2304         struct mlx5e_priv *priv = netdev_priv(netdev);
2305         int err;
2306
2307         mutex_lock(&priv->state_lock);
2308
2309         priv->params.vlan_strip_disable = !enable;
2310         err = mlx5e_modify_rqs_vsd(priv, !enable);
2311         if (err)
2312                 priv->params.vlan_strip_disable = enable;
2313
2314         mutex_unlock(&priv->state_lock);
2315
2316         return err;
2317 }
2318
2319 #ifdef CONFIG_RFS_ACCEL
2320 static int set_feature_arfs(struct net_device *netdev, bool enable)
2321 {
2322         struct mlx5e_priv *priv = netdev_priv(netdev);
2323         int err;
2324
2325         if (enable)
2326                 err = mlx5e_arfs_enable(priv);
2327         else
2328                 err = mlx5e_arfs_disable(priv);
2329
2330         return err;
2331 }
2332 #endif
2333
2334 static int mlx5e_handle_feature(struct net_device *netdev,
2335                                 netdev_features_t wanted_features,
2336                                 netdev_features_t feature,
2337                                 mlx5e_feature_handler feature_handler)
2338 {
2339         netdev_features_t changes = wanted_features ^ netdev->features;
2340         bool enable = !!(wanted_features & feature);
2341         int err;
2342
2343         if (!(changes & feature))
2344                 return 0;
2345
2346         err = feature_handler(netdev, enable);
2347         if (err) {
2348                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2349                            enable ? "Enable" : "Disable", feature, err);
2350                 return err;
2351         }
2352
2353         MLX5E_SET_FEATURE(netdev, feature, enable);
2354         return 0;
2355 }
2356
2357 static int mlx5e_set_features(struct net_device *netdev,
2358                               netdev_features_t features)
2359 {
2360         int err;
2361
2362         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2363                                     set_feature_lro);
2364         err |= mlx5e_handle_feature(netdev, features,
2365                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2366                                     set_feature_vlan_filter);
2367         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2368                                     set_feature_tc_num_filters);
2369         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2370                                     set_feature_rx_all);
2371         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2372                                     set_feature_rx_vlan);
2373 #ifdef CONFIG_RFS_ACCEL
2374         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2375                                     set_feature_arfs);
2376 #endif
2377
2378         return err ? -EINVAL : 0;
2379 }
2380
2381 #define MXL5_HW_MIN_MTU 64
2382 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2383
2384 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2385 {
2386         struct mlx5e_priv *priv = netdev_priv(netdev);
2387         struct mlx5_core_dev *mdev = priv->mdev;
2388         bool was_opened;
2389         u16 max_mtu;
2390         u16 min_mtu;
2391         int err = 0;
2392
2393         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2394
2395         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2396         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2397
2398         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2399                 netdev_err(netdev,
2400                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2401                            __func__, new_mtu, min_mtu, max_mtu);
2402                 return -EINVAL;
2403         }
2404
2405         mutex_lock(&priv->state_lock);
2406
2407         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2408         if (was_opened)
2409                 mlx5e_close_locked(netdev);
2410
2411         netdev->mtu = new_mtu;
2412
2413         if (was_opened)
2414                 err = mlx5e_open_locked(netdev);
2415
2416         mutex_unlock(&priv->state_lock);
2417
2418         return err;
2419 }
2420
2421 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2422 {
2423         switch (cmd) {
2424         case SIOCSHWTSTAMP:
2425                 return mlx5e_hwstamp_set(dev, ifr);
2426         case SIOCGHWTSTAMP:
2427                 return mlx5e_hwstamp_get(dev, ifr);
2428         default:
2429                 return -EOPNOTSUPP;
2430         }
2431 }
2432
2433 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2434 {
2435         struct mlx5e_priv *priv = netdev_priv(dev);
2436         struct mlx5_core_dev *mdev = priv->mdev;
2437
2438         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2439 }
2440
2441 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2442 {
2443         struct mlx5e_priv *priv = netdev_priv(dev);
2444         struct mlx5_core_dev *mdev = priv->mdev;
2445
2446         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2447                                            vlan, qos);
2448 }
2449
2450 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2451 {
2452         struct mlx5e_priv *priv = netdev_priv(dev);
2453         struct mlx5_core_dev *mdev = priv->mdev;
2454
2455         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2456 }
2457
2458 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2459 {
2460         struct mlx5e_priv *priv = netdev_priv(dev);
2461         struct mlx5_core_dev *mdev = priv->mdev;
2462
2463         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2464 }
2465 static int mlx5_vport_link2ifla(u8 esw_link)
2466 {
2467         switch (esw_link) {
2468         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2469                 return IFLA_VF_LINK_STATE_DISABLE;
2470         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2471                 return IFLA_VF_LINK_STATE_ENABLE;
2472         }
2473         return IFLA_VF_LINK_STATE_AUTO;
2474 }
2475
2476 static int mlx5_ifla_link2vport(u8 ifla_link)
2477 {
2478         switch (ifla_link) {
2479         case IFLA_VF_LINK_STATE_DISABLE:
2480                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2481         case IFLA_VF_LINK_STATE_ENABLE:
2482                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2483         }
2484         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2485 }
2486
2487 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2488                                    int link_state)
2489 {
2490         struct mlx5e_priv *priv = netdev_priv(dev);
2491         struct mlx5_core_dev *mdev = priv->mdev;
2492
2493         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2494                                             mlx5_ifla_link2vport(link_state));
2495 }
2496
2497 static int mlx5e_get_vf_config(struct net_device *dev,
2498                                int vf, struct ifla_vf_info *ivi)
2499 {
2500         struct mlx5e_priv *priv = netdev_priv(dev);
2501         struct mlx5_core_dev *mdev = priv->mdev;
2502         int err;
2503
2504         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2505         if (err)
2506                 return err;
2507         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2508         return 0;
2509 }
2510
2511 static int mlx5e_get_vf_stats(struct net_device *dev,
2512                               int vf, struct ifla_vf_stats *vf_stats)
2513 {
2514         struct mlx5e_priv *priv = netdev_priv(dev);
2515         struct mlx5_core_dev *mdev = priv->mdev;
2516
2517         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2518                                             vf_stats);
2519 }
2520
2521 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2522                                  sa_family_t sa_family, __be16 port)
2523 {
2524         struct mlx5e_priv *priv = netdev_priv(netdev);
2525
2526         if (!mlx5e_vxlan_allowed(priv->mdev))
2527                 return;
2528
2529         mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1);
2530 }
2531
2532 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2533                                  sa_family_t sa_family, __be16 port)
2534 {
2535         struct mlx5e_priv *priv = netdev_priv(netdev);
2536
2537         if (!mlx5e_vxlan_allowed(priv->mdev))
2538                 return;
2539
2540         mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0);
2541 }
2542
2543 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2544                                                     struct sk_buff *skb,
2545                                                     netdev_features_t features)
2546 {
2547         struct udphdr *udph;
2548         u16 proto;
2549         u16 port = 0;
2550
2551         switch (vlan_get_protocol(skb)) {
2552         case htons(ETH_P_IP):
2553                 proto = ip_hdr(skb)->protocol;
2554                 break;
2555         case htons(ETH_P_IPV6):
2556                 proto = ipv6_hdr(skb)->nexthdr;
2557                 break;
2558         default:
2559                 goto out;
2560         }
2561
2562         if (proto == IPPROTO_UDP) {
2563                 udph = udp_hdr(skb);
2564                 port = be16_to_cpu(udph->dest);
2565         }
2566
2567         /* Verify if UDP port is being offloaded by HW */
2568         if (port && mlx5e_vxlan_lookup_port(priv, port))
2569                 return features;
2570
2571 out:
2572         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2573         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2574 }
2575
2576 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2577                                               struct net_device *netdev,
2578                                               netdev_features_t features)
2579 {
2580         struct mlx5e_priv *priv = netdev_priv(netdev);
2581
2582         features = vlan_features_check(skb, features);
2583         features = vxlan_features_check(skb, features);
2584
2585         /* Validate if the tunneled packet is being offloaded by HW */
2586         if (skb->encapsulation &&
2587             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2588                 return mlx5e_vxlan_features_check(priv, skb, features);
2589
2590         return features;
2591 }
2592
2593 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2594         .ndo_open                = mlx5e_open,
2595         .ndo_stop                = mlx5e_close,
2596         .ndo_start_xmit          = mlx5e_xmit,
2597         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2598         .ndo_select_queue        = mlx5e_select_queue,
2599         .ndo_get_stats64         = mlx5e_get_stats,
2600         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2601         .ndo_set_mac_address     = mlx5e_set_mac,
2602         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2603         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2604         .ndo_set_features        = mlx5e_set_features,
2605         .ndo_change_mtu          = mlx5e_change_mtu,
2606         .ndo_do_ioctl            = mlx5e_ioctl,
2607 #ifdef CONFIG_RFS_ACCEL
2608         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2609 #endif
2610 };
2611
2612 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2613         .ndo_open                = mlx5e_open,
2614         .ndo_stop                = mlx5e_close,
2615         .ndo_start_xmit          = mlx5e_xmit,
2616         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2617         .ndo_select_queue        = mlx5e_select_queue,
2618         .ndo_get_stats64         = mlx5e_get_stats,
2619         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2620         .ndo_set_mac_address     = mlx5e_set_mac,
2621         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2622         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2623         .ndo_set_features        = mlx5e_set_features,
2624         .ndo_change_mtu          = mlx5e_change_mtu,
2625         .ndo_do_ioctl            = mlx5e_ioctl,
2626         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2627         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2628         .ndo_features_check      = mlx5e_features_check,
2629 #ifdef CONFIG_RFS_ACCEL
2630         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2631 #endif
2632         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2633         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2634         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
2635         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
2636         .ndo_get_vf_config       = mlx5e_get_vf_config,
2637         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2638         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2639 };
2640
2641 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2642 {
2643         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2644                 return -ENOTSUPP;
2645         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2646             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2647             !MLX5_CAP_ETH(mdev, csum_cap) ||
2648             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2649             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2650             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2651             MLX5_CAP_FLOWTABLE(mdev,
2652                                flow_table_properties_nic_receive.max_ft_level)
2653                                < 3) {
2654                 mlx5_core_warn(mdev,
2655                                "Not creating net device, some required device capabilities are missing\n");
2656                 return -ENOTSUPP;
2657         }
2658         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2659                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2660         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2661                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2662
2663         return 0;
2664 }
2665
2666 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2667 {
2668         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2669
2670         return bf_buf_size -
2671                sizeof(struct mlx5e_tx_wqe) +
2672                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2673 }
2674
2675 #ifdef CONFIG_MLX5_CORE_EN_DCB
2676 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2677 {
2678         int i;
2679
2680         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2681         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2682                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2683                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2684                 priv->params.ets.prio_tc[i] = i;
2685         }
2686
2687         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2688         priv->params.ets.prio_tc[0] = 1;
2689         priv->params.ets.prio_tc[1] = 0;
2690 }
2691 #endif
2692
2693 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2694                                    u32 *indirection_rqt, int len,
2695                                    int num_channels)
2696 {
2697         int node = mdev->priv.numa_node;
2698         int node_num_of_cores;
2699         int i;
2700
2701         if (node == -1)
2702                 node = first_online_node;
2703
2704         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2705
2706         if (node_num_of_cores)
2707                 num_channels = min_t(int, num_channels, node_num_of_cores);
2708
2709         for (i = 0; i < len; i++)
2710                 indirection_rqt[i] = i % num_channels;
2711 }
2712
2713 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2714 {
2715         return MLX5_CAP_GEN(mdev, striding_rq) &&
2716                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2717                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2718 }
2719
2720 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2721 {
2722         enum pcie_link_width width;
2723         enum pci_bus_speed speed;
2724         int err = 0;
2725
2726         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2727         if (err)
2728                 return err;
2729
2730         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2731                 return -EINVAL;
2732
2733         switch (speed) {
2734         case PCIE_SPEED_2_5GT:
2735                 *pci_bw = 2500 * width;
2736                 break;
2737         case PCIE_SPEED_5_0GT:
2738                 *pci_bw = 5000 * width;
2739                 break;
2740         case PCIE_SPEED_8_0GT:
2741                 *pci_bw = 8000 * width;
2742                 break;
2743         default:
2744                 return -EINVAL;
2745         }
2746
2747         return 0;
2748 }
2749
2750 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2751 {
2752         return (link_speed && pci_bw &&
2753                 (pci_bw < 40000) && (pci_bw < link_speed));
2754 }
2755
2756 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2757                                     struct net_device *netdev,
2758                                     int num_channels)
2759 {
2760         struct mlx5e_priv *priv = netdev_priv(netdev);
2761         u32 link_speed = 0;
2762         u32 pci_bw = 0;
2763
2764         priv->params.log_sq_size           =
2765                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2766         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2767                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2768                 MLX5_WQ_TYPE_LINKED_LIST;
2769
2770         /* set CQE compression */
2771         priv->params.rx_cqe_compress_admin = false;
2772         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
2773             MLX5_CAP_GEN(mdev, vport_group_manager)) {
2774                 mlx5e_get_max_linkspeed(mdev, &link_speed);
2775                 mlx5e_get_pci_bw(mdev, &pci_bw);
2776                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
2777                               link_speed, pci_bw);
2778                 priv->params.rx_cqe_compress_admin =
2779                         cqe_compress_heuristic(link_speed, pci_bw);
2780         }
2781
2782         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
2783
2784         switch (priv->params.rq_wq_type) {
2785         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2786                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2787                 priv->params.mpwqe_log_stride_sz =
2788                         priv->params.rx_cqe_compress ?
2789                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
2790                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
2791                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
2792                         priv->params.mpwqe_log_stride_sz;
2793                 priv->params.lro_en = true;
2794                 break;
2795         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2796                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2797         }
2798
2799         mlx5_core_info(mdev,
2800                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
2801                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
2802                        BIT(priv->params.log_rq_size),
2803                        BIT(priv->params.mpwqe_log_stride_sz),
2804                        priv->params.rx_cqe_compress_admin);
2805
2806         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2807                                             BIT(priv->params.log_rq_size));
2808         priv->params.rx_cq_moderation_usec =
2809                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2810         priv->params.rx_cq_moderation_pkts =
2811                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2812         priv->params.tx_cq_moderation_usec =
2813                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2814         priv->params.tx_cq_moderation_pkts =
2815                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2816         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2817         priv->params.num_tc                = 1;
2818         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2819
2820         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2821                             sizeof(priv->params.toeplitz_hash_key));
2822
2823         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2824                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2825
2826         priv->params.lro_wqe_sz            =
2827                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2828
2829         priv->mdev                         = mdev;
2830         priv->netdev                       = netdev;
2831         priv->params.num_channels          = num_channels;
2832
2833 #ifdef CONFIG_MLX5_CORE_EN_DCB
2834         mlx5e_ets_init(priv);
2835 #endif
2836
2837         mutex_init(&priv->state_lock);
2838
2839         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2840         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2841         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2842 }
2843
2844 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2845 {
2846         struct mlx5e_priv *priv = netdev_priv(netdev);
2847
2848         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2849         if (is_zero_ether_addr(netdev->dev_addr) &&
2850             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2851                 eth_hw_addr_random(netdev);
2852                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2853         }
2854 }
2855
2856 static void mlx5e_build_netdev(struct net_device *netdev)
2857 {
2858         struct mlx5e_priv *priv = netdev_priv(netdev);
2859         struct mlx5_core_dev *mdev = priv->mdev;
2860         bool fcs_supported;
2861         bool fcs_enabled;
2862
2863         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2864
2865         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2866                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2867 #ifdef CONFIG_MLX5_CORE_EN_DCB
2868                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2869 #endif
2870         } else {
2871                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2872         }
2873
2874         netdev->watchdog_timeo    = 15 * HZ;
2875
2876         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2877
2878         netdev->vlan_features    |= NETIF_F_SG;
2879         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2880         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2881         netdev->vlan_features    |= NETIF_F_GRO;
2882         netdev->vlan_features    |= NETIF_F_TSO;
2883         netdev->vlan_features    |= NETIF_F_TSO6;
2884         netdev->vlan_features    |= NETIF_F_RXCSUM;
2885         netdev->vlan_features    |= NETIF_F_RXHASH;
2886
2887         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2888                 netdev->vlan_features    |= NETIF_F_LRO;
2889
2890         netdev->hw_features       = netdev->vlan_features;
2891         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2892         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2893         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2894
2895         if (mlx5e_vxlan_allowed(mdev)) {
2896                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
2897                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
2898                                            NETIF_F_GSO_PARTIAL;
2899                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2900                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
2901                 netdev->hw_enc_features |= NETIF_F_TSO;
2902                 netdev->hw_enc_features |= NETIF_F_TSO6;
2903                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2904                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
2905                                            NETIF_F_GSO_PARTIAL;
2906                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
2907         }
2908
2909         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2910
2911         if (fcs_supported)
2912                 netdev->hw_features |= NETIF_F_RXALL;
2913
2914         netdev->features          = netdev->hw_features;
2915         if (!priv->params.lro_en)
2916                 netdev->features  &= ~NETIF_F_LRO;
2917
2918         if (fcs_enabled)
2919                 netdev->features  &= ~NETIF_F_RXALL;
2920
2921 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2922         if (FT_CAP(flow_modify_en) &&
2923             FT_CAP(modify_root) &&
2924             FT_CAP(identified_miss_table_mode) &&
2925             FT_CAP(flow_table_modify)) {
2926                 netdev->hw_features      |= NETIF_F_HW_TC;
2927 #ifdef CONFIG_RFS_ACCEL
2928                 netdev->hw_features      |= NETIF_F_NTUPLE;
2929 #endif
2930         }
2931
2932         netdev->features         |= NETIF_F_HIGHDMA;
2933
2934         netdev->priv_flags       |= IFF_UNICAST_FLT;
2935
2936         mlx5e_set_netdev_dev_addr(netdev);
2937 }
2938
2939 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2940                              struct mlx5_core_mkey *mkey)
2941 {
2942         struct mlx5_core_dev *mdev = priv->mdev;
2943         struct mlx5_create_mkey_mbox_in *in;
2944         int err;
2945
2946         in = mlx5_vzalloc(sizeof(*in));
2947         if (!in)
2948                 return -ENOMEM;
2949
2950         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2951                         MLX5_PERM_LOCAL_READ  |
2952                         MLX5_ACCESS_MODE_PA;
2953         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2954         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2955
2956         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2957                                     NULL);
2958
2959         kvfree(in);
2960
2961         return err;
2962 }
2963
2964 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2965 {
2966         struct mlx5_core_dev *mdev = priv->mdev;
2967         int err;
2968
2969         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2970         if (err) {
2971                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2972                 priv->q_counter = 0;
2973         }
2974 }
2975
2976 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2977 {
2978         if (!priv->q_counter)
2979                 return;
2980
2981         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2982 }
2983
2984 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2985 {
2986         struct mlx5_core_dev *mdev = priv->mdev;
2987         struct mlx5_create_mkey_mbox_in *in;
2988         struct mlx5_mkey_seg *mkc;
2989         int inlen = sizeof(*in);
2990         u64 npages =
2991                 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2992         int err;
2993
2994         in = mlx5_vzalloc(inlen);
2995         if (!in)
2996                 return -ENOMEM;
2997
2998         mkc = &in->seg;
2999         mkc->status = MLX5_MKEY_STATUS_FREE;
3000         mkc->flags = MLX5_PERM_UMR_EN |
3001                      MLX5_PERM_LOCAL_READ |
3002                      MLX5_PERM_LOCAL_WRITE |
3003                      MLX5_ACCESS_MODE_MTT;
3004
3005         mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3006         mkc->flags_pd = cpu_to_be32(priv->pdn);
3007         mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3008         mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
3009         mkc->log2_page_size = PAGE_SHIFT;
3010
3011         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3012                                     NULL, NULL);
3013
3014         kvfree(in);
3015
3016         return err;
3017 }
3018
3019 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
3020 {
3021         struct net_device *netdev;
3022         struct mlx5e_priv *priv;
3023         int nch = mlx5e_get_max_num_channels(mdev);
3024         int err;
3025
3026         if (mlx5e_check_required_hca_cap(mdev))
3027                 return NULL;
3028
3029         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3030                                     nch * MLX5E_MAX_NUM_TC,
3031                                     nch);
3032         if (!netdev) {
3033                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3034                 return NULL;
3035         }
3036
3037         mlx5e_build_netdev_priv(mdev, netdev, nch);
3038         mlx5e_build_netdev(netdev);
3039
3040         netif_carrier_off(netdev);
3041
3042         priv = netdev_priv(netdev);
3043
3044         priv->wq = create_singlethread_workqueue("mlx5e");
3045         if (!priv->wq)
3046                 goto err_free_netdev;
3047
3048         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
3049         if (err) {
3050                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
3051                 goto err_destroy_wq;
3052         }
3053
3054         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3055         if (err) {
3056                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
3057                 goto err_unmap_free_uar;
3058         }
3059
3060         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3061         if (err) {
3062                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3063                 goto err_dealloc_pd;
3064         }
3065
3066         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
3067         if (err) {
3068                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3069                 goto err_dealloc_transport_domain;
3070         }
3071
3072         err = mlx5e_create_umr_mkey(priv);
3073         if (err) {
3074                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3075                 goto err_destroy_mkey;
3076         }
3077
3078         err = mlx5e_create_tises(priv);
3079         if (err) {
3080                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
3081                 goto err_destroy_umr_mkey;
3082         }
3083
3084         err = mlx5e_open_drop_rq(priv);
3085         if (err) {
3086                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3087                 goto err_destroy_tises;
3088         }
3089
3090         err = mlx5e_create_rqts(priv);
3091         if (err) {
3092                 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
3093                 goto err_close_drop_rq;
3094         }
3095
3096         err = mlx5e_create_tirs(priv);
3097         if (err) {
3098                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
3099                 goto err_destroy_rqts;
3100         }
3101
3102         err = mlx5e_create_flow_steering(priv);
3103         if (err) {
3104                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3105                 goto err_destroy_tirs;
3106         }
3107
3108         mlx5e_create_q_counter(priv);
3109
3110         mlx5e_init_l2_addr(priv);
3111
3112         mlx5e_vxlan_init(priv);
3113
3114         err = mlx5e_tc_init(priv);
3115         if (err)
3116                 goto err_dealloc_q_counters;
3117
3118 #ifdef CONFIG_MLX5_CORE_EN_DCB
3119         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3120 #endif
3121
3122         err = register_netdev(netdev);
3123         if (err) {
3124                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3125                 goto err_tc_cleanup;
3126         }
3127
3128         if (mlx5e_vxlan_allowed(mdev)) {
3129                 rtnl_lock();
3130                 vxlan_get_rx_port(netdev);
3131                 rtnl_unlock();
3132         }
3133
3134         mlx5e_enable_async_events(priv);
3135         queue_work(priv->wq, &priv->set_rx_mode_work);
3136
3137         return priv;
3138
3139 err_tc_cleanup:
3140         mlx5e_tc_cleanup(priv);
3141
3142 err_dealloc_q_counters:
3143         mlx5e_destroy_q_counter(priv);
3144         mlx5e_destroy_flow_steering(priv);
3145
3146 err_destroy_tirs:
3147         mlx5e_destroy_tirs(priv);
3148
3149 err_destroy_rqts:
3150         mlx5e_destroy_rqts(priv);
3151
3152 err_close_drop_rq:
3153         mlx5e_close_drop_rq(priv);
3154
3155 err_destroy_tises:
3156         mlx5e_destroy_tises(priv);
3157
3158 err_destroy_umr_mkey:
3159         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3160
3161 err_destroy_mkey:
3162         mlx5_core_destroy_mkey(mdev, &priv->mkey);
3163
3164 err_dealloc_transport_domain:
3165         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3166
3167 err_dealloc_pd:
3168         mlx5_core_dealloc_pd(mdev, priv->pdn);
3169
3170 err_unmap_free_uar:
3171         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3172
3173 err_destroy_wq:
3174         destroy_workqueue(priv->wq);
3175
3176 err_free_netdev:
3177         free_netdev(netdev);
3178
3179         return NULL;
3180 }
3181
3182 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3183 {
3184         struct mlx5e_priv *priv = vpriv;
3185         struct net_device *netdev = priv->netdev;
3186
3187         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3188
3189         queue_work(priv->wq, &priv->set_rx_mode_work);
3190         mlx5e_disable_async_events(priv);
3191         flush_workqueue(priv->wq);
3192         if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3193                 netif_device_detach(netdev);
3194                 mlx5e_close(netdev);
3195         } else {
3196                 unregister_netdev(netdev);
3197         }
3198
3199         mlx5e_tc_cleanup(priv);
3200         mlx5e_vxlan_cleanup(priv);
3201         mlx5e_destroy_q_counter(priv);
3202         mlx5e_destroy_flow_steering(priv);
3203         mlx5e_destroy_tirs(priv);
3204         mlx5e_destroy_rqts(priv);
3205         mlx5e_close_drop_rq(priv);
3206         mlx5e_destroy_tises(priv);
3207         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3208         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
3209         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
3210         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3211         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3212         cancel_delayed_work_sync(&priv->update_stats_work);
3213         destroy_workqueue(priv->wq);
3214
3215         if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3216                 free_netdev(netdev);
3217 }
3218
3219 static void *mlx5e_get_netdev(void *vpriv)
3220 {
3221         struct mlx5e_priv *priv = vpriv;
3222
3223         return priv->netdev;
3224 }
3225
3226 static struct mlx5_interface mlx5e_interface = {
3227         .add       = mlx5e_create_netdev,
3228         .remove    = mlx5e_destroy_netdev,
3229         .event     = mlx5e_async_event,
3230         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3231         .get_dev   = mlx5e_get_netdev,
3232 };
3233
3234 void mlx5e_init(void)
3235 {
3236         mlx5_register_interface(&mlx5e_interface);
3237 }
3238
3239 void mlx5e_cleanup(void)
3240 {
3241         mlx5_unregister_interface(&mlx5e_interface);
3242 }