drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 struct mlx5e_rq_param {
  43         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  44         struct mlx5_wq_param       wq;
  45 };
  46
  47 struct mlx5e_sq_param {
  48         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  49         struct mlx5_wq_param       wq;
  50         u16                        max_inline;
  51         bool                       icosq;
  52 };
  53
  54 struct mlx5e_cq_param {
  55         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  56         struct mlx5_wq_param       wq;
  57         u16                        eq_ix;
  58 };
  59
  60 struct mlx5e_channel_param {
  61         struct mlx5e_rq_param      rq;
  62         struct mlx5e_sq_param      sq;
  63         struct mlx5e_sq_param      icosq;
  64         struct mlx5e_cq_param      rx_cq;
  65         struct mlx5e_cq_param      tx_cq;
  66         struct mlx5e_cq_param      icosq_cq;
  67 };
  68
  69 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  70 {
  71         struct mlx5_core_dev *mdev = priv->mdev;
  72         u8 port_state;
  73
  74         port_state = mlx5_query_vport_state(mdev,
  75                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  76
  77         if (port_state == VPORT_STATE_UP)
  78                 netif_carrier_on(priv->netdev);
  79         else
  80                 netif_carrier_off(priv->netdev);
  81 }
  82
  83 static void mlx5e_update_carrier_work(struct work_struct *work)
  84 {
  85         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  86                                                update_carrier_work);
  87
  88         mutex_lock(&priv->state_lock);
  89         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  90                 mlx5e_update_carrier(priv);
  91         mutex_unlock(&priv->state_lock);
  92 }
  93
  94 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
  95 {
  96         struct mlx5e_sw_stats *s = &priv->stats.sw;
  97         struct mlx5e_rq_stats *rq_stats;
  98         struct mlx5e_sq_stats *sq_stats;
  99         u64 tx_offload_none = 0;
 100         int i, j;
 101
 102         memset(s, 0, sizeof(*s));
 103         for (i = 0; i < priv->params.num_channels; i++) {
 104                 rq_stats = &priv->channel[i]->rq.stats;
 105
 106                 s->rx_packets   += rq_stats->packets;
 107                 s->rx_bytes     += rq_stats->bytes;
 108                 s->lro_packets  += rq_stats->lro_packets;
 109                 s->lro_bytes    += rq_stats->lro_bytes;
 110                 s->rx_csum_none += rq_stats->csum_none;
 111                 s->rx_csum_sw   += rq_stats->csum_sw;
 112                 s->rx_csum_inner += rq_stats->csum_inner;
 113                 s->rx_wqe_err   += rq_stats->wqe_err;
 114                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 115                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
 116                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 117                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 118                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 119
 120                 for (j = 0; j < priv->params.num_tc; j++) {
 121                         sq_stats = &priv->channel[i]->sq[j].stats;
 122
 123                         s->tx_packets           += sq_stats->packets;
 124                         s->tx_bytes             += sq_stats->bytes;
 125                         s->tso_packets          += sq_stats->tso_packets;
 126                         s->tso_bytes            += sq_stats->tso_bytes;
 127                         s->tso_inner_packets    += sq_stats->tso_inner_packets;
 128                         s->tso_inner_bytes      += sq_stats->tso_inner_bytes;
 129                         s->tx_queue_stopped     += sq_stats->stopped;
 130                         s->tx_queue_wake        += sq_stats->wake;
 131                         s->tx_queue_dropped     += sq_stats->dropped;
 132                         s->tx_csum_inner        += sq_stats->csum_offload_inner;
 133                         tx_offload_none         += sq_stats->csum_offload_none;
 134                 }
 135         }
 136
 137         /* Update calculated offload counters */
 138         s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
 139         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 140                              s->rx_csum_sw;
 141
 142         s->link_down_events = MLX5_GET(ppcnt_reg,
 143                                 priv->stats.pport.phy_counters,
 144                                 counter_set.phys_layer_cntrs.link_down_events);
 145 }
 146
 147 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 148 {
 149         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 150         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 151         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 152         struct mlx5_core_dev *mdev = priv->mdev;
 153
 154         memset(in, 0, sizeof(in));
 155
 156         MLX5_SET(query_vport_counter_in, in, opcode,
 157                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 158         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 159         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 160
 161         memset(out, 0, outlen);
 162
 163         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 164 }
 165
 166 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 167 {
 168         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 169         struct mlx5_core_dev *mdev = priv->mdev;
 170         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 171         int prio;
 172         void *out;
 173         u32 *in;
 174
 175         in = mlx5_vzalloc(sz);
 176         if (!in)
 177                 goto free_out;
 178
 179         MLX5_SET(ppcnt_reg, in, local_port, 1);
 180
 181         out = pstats->IEEE_802_3_counters;
 182         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 183         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 184
 185         out = pstats->RFC_2863_counters;
 186         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 187         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 188
 189         out = pstats->RFC_2819_counters;
 190         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 191         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 192
 193         out = pstats->phy_counters;
 194         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 195         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 196
 197         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 198         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 199                 out = pstats->per_prio_counters[prio];
 200                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 201                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 202                                      MLX5_REG_PPCNT, 0, 0);
 203         }
 204
 205 free_out:
 206         kvfree(in);
 207 }
 208
 209 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 210 {
 211         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 212
 213         if (!priv->q_counter)
 214                 return;
 215
 216         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 217                                       &qcnt->rx_out_of_buffer);
 218 }
 219
 220 void mlx5e_update_stats(struct mlx5e_priv *priv)
 221 {
 222         mlx5e_update_q_counter(priv);
 223         mlx5e_update_vport_counters(priv);
 224         mlx5e_update_pport_counters(priv);
 225         mlx5e_update_sw_counters(priv);
 226 }
 227
 228 static void mlx5e_update_stats_work(struct work_struct *work)
 229 {
 230         struct delayed_work *dwork = to_delayed_work(work);
 231         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 232                                                update_stats_work);
 233         mutex_lock(&priv->state_lock);
 234         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 235                 mlx5e_update_stats(priv);
 236                 queue_delayed_work(priv->wq, dwork,
 237                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 238         }
 239         mutex_unlock(&priv->state_lock);
 240 }
 241
 242 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 243                               enum mlx5_dev_event event, unsigned long param)
 244 {
 245         struct mlx5e_priv *priv = vpriv;
 246
 247         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 248                 return;
 249
 250         switch (event) {
 251         case MLX5_DEV_EVENT_PORT_UP:
 252         case MLX5_DEV_EVENT_PORT_DOWN:
 253                 queue_work(priv->wq, &priv->update_carrier_work);
 254                 break;
 255
 256         default:
 257                 break;
 258         }
 259 }
 260
 261 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 262 {
 263         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 264 }
 265
 266 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 267 {
 268         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 269         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 270 }
 271
 272 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 273 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 274
 275 static int mlx5e_create_rq(struct mlx5e_channel *c,
 276                            struct mlx5e_rq_param *param,
 277                            struct mlx5e_rq *rq)
 278 {
 279         struct mlx5e_priv *priv = c->priv;
 280         struct mlx5_core_dev *mdev = priv->mdev;
 281         void *rqc = param->rqc;
 282         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 283         u32 byte_count;
 284         int wq_sz;
 285         int err;
 286         int i;
 287
 288         param->wq.db_numa_node = cpu_to_node(c->cpu);
 289
 290         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 291                                 &rq->wq_ctrl);
 292         if (err)
 293                 return err;
 294
 295         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 296
 297         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 298
 299         switch (priv->params.rq_wq_type) {
 300         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 301                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 302                                             GFP_KERNEL, cpu_to_node(c->cpu));
 303                 if (!rq->wqe_info) {
 304                         err = -ENOMEM;
 305                         goto err_rq_wq_destroy;
 306                 }
 307                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 308                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 309
 310                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 311                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 312                 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 313                 byte_count = rq->wqe_sz;
 314                 break;
 315         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 316                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 317                                        cpu_to_node(c->cpu));
 318                 if (!rq->skb) {
 319                         err = -ENOMEM;
 320                         goto err_rq_wq_destroy;
 321                 }
 322                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 323                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 324
 325                 rq->wqe_sz = (priv->params.lro_en) ?
 326                                 priv->params.lro_wqe_sz :
 327                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 328                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 329                 byte_count = rq->wqe_sz;
 330                 byte_count |= MLX5_HW_START_PADDING;
 331         }
 332
 333         for (i = 0; i < wq_sz; i++) {
 334                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 335
 336                 wqe->data.byte_count = cpu_to_be32(byte_count);
 337         }
 338
 339         rq->wq_type = priv->params.rq_wq_type;
 340         rq->pdev    = c->pdev;
 341         rq->netdev  = c->netdev;
 342         rq->tstamp  = &priv->tstamp;
 343         rq->channel = c;
 344         rq->ix      = c->ix;
 345         rq->priv    = c->priv;
 346         rq->mkey_be = c->mkey_be;
 347         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 348
 349         return 0;
 350
 351 err_rq_wq_destroy:
 352         mlx5_wq_destroy(&rq->wq_ctrl);
 353
 354         return err;
 355 }
 356
 357 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 358 {
 359         switch (rq->wq_type) {
 360         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 361                 kfree(rq->wqe_info);
 362                 break;
 363         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 364                 kfree(rq->skb);
 365         }
 366
 367         mlx5_wq_destroy(&rq->wq_ctrl);
 368 }
 369
 370 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 371 {
 372         struct mlx5e_priv *priv = rq->priv;
 373         struct mlx5_core_dev *mdev = priv->mdev;
 374
 375         void *in;
 376         void *rqc;
 377         void *wq;
 378         int inlen;
 379         int err;
 380
 381         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 382                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 383         in = mlx5_vzalloc(inlen);
 384         if (!in)
 385                 return -ENOMEM;
 386
 387         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 388         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 389
 390         memcpy(rqc, param->rqc, sizeof(param->rqc));
 391
 392         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 393         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 394         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 395         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 396         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 397                                                 MLX5_ADAPTER_PAGE_SHIFT);
 398         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 399
 400         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 401                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 402
 403         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 404
 405         kvfree(in);
 406
 407         return err;
 408 }
 409
 410 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 411                                  int next_state)
 412 {
 413         struct mlx5e_channel *c = rq->channel;
 414         struct mlx5e_priv *priv = c->priv;
 415         struct mlx5_core_dev *mdev = priv->mdev;
 416
 417         void *in;
 418         void *rqc;
 419         int inlen;
 420         int err;
 421
 422         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 423         in = mlx5_vzalloc(inlen);
 424         if (!in)
 425                 return -ENOMEM;
 426
 427         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 428
 429         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 430         MLX5_SET(rqc, rqc, state, next_state);
 431
 432         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 433
 434         kvfree(in);
 435
 436         return err;
 437 }
 438
 439 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 440 {
 441         struct mlx5e_channel *c = rq->channel;
 442         struct mlx5e_priv *priv = c->priv;
 443         struct mlx5_core_dev *mdev = priv->mdev;
 444
 445         void *in;
 446         void *rqc;
 447         int inlen;
 448         int err;
 449
 450         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 451         in = mlx5_vzalloc(inlen);
 452         if (!in)
 453                 return -ENOMEM;
 454
 455         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 456
 457         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 458         MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
 459         MLX5_SET(rqc, rqc, vsd, vsd);
 460         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 461
 462         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 463
 464         kvfree(in);
 465
 466         return err;
 467 }
 468
 469 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 470 {
 471         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 472 }
 473
 474 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 475 {
 476         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 477         struct mlx5e_channel *c = rq->channel;
 478         struct mlx5e_priv *priv = c->priv;
 479         struct mlx5_wq_ll *wq = &rq->wq;
 480
 481         while (time_before(jiffies, exp_time)) {
 482                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 483                         return 0;
 484
 485                 msleep(20);
 486         }
 487
 488         return -ETIMEDOUT;
 489 }
 490
 491 static int mlx5e_open_rq(struct mlx5e_channel *c,
 492                          struct mlx5e_rq_param *param,
 493                          struct mlx5e_rq *rq)
 494 {
 495         struct mlx5e_sq *sq = &c->icosq;
 496         u16 pi = sq->pc & sq->wq.sz_m1;
 497         int err;
 498
 499         err = mlx5e_create_rq(c, param, rq);
 500         if (err)
 501                 return err;
 502
 503         err = mlx5e_enable_rq(rq, param);
 504         if (err)
 505                 goto err_destroy_rq;
 506
 507         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 508         if (err)
 509                 goto err_disable_rq;
 510
 511         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 512
 513         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 514         sq->ico_wqe_info[pi].num_wqebbs = 1;
 515         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 516
 517         return 0;
 518
 519 err_disable_rq:
 520         mlx5e_disable_rq(rq);
 521 err_destroy_rq:
 522         mlx5e_destroy_rq(rq);
 523
 524         return err;
 525 }
 526
 527 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 528 {
 529         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 530         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 531
 532         mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 533         while (!mlx5_wq_ll_is_empty(&rq->wq))
 534                 msleep(20);
 535
 536         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 537         napi_synchronize(&rq->channel->napi);
 538
 539         mlx5e_disable_rq(rq);
 540         mlx5e_destroy_rq(rq);
 541 }
 542
 543 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 544 {
 545         kfree(sq->wqe_info);
 546         kfree(sq->dma_fifo);
 547         kfree(sq->skb);
 548 }
 549
 550 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 551 {
 552         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 553         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 554
 555         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 556         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 557                                     numa);
 558         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 559                                     numa);
 560
 561         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 562                 mlx5e_free_sq_db(sq);
 563                 return -ENOMEM;
 564         }
 565
 566         sq->dma_fifo_mask = df_sz - 1;
 567
 568         return 0;
 569 }
 570
 571 static int mlx5e_create_sq(struct mlx5e_channel *c,
 572                            int tc,
 573                            struct mlx5e_sq_param *param,
 574                            struct mlx5e_sq *sq)
 575 {
 576         struct mlx5e_priv *priv = c->priv;
 577         struct mlx5_core_dev *mdev = priv->mdev;
 578
 579         void *sqc = param->sqc;
 580         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 581         int err;
 582
 583         err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
 584         if (err)
 585                 return err;
 586
 587         param->wq.db_numa_node = cpu_to_node(c->cpu);
 588
 589         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 590                                  &sq->wq_ctrl);
 591         if (err)
 592                 goto err_unmap_free_uar;
 593
 594         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 595         if (sq->uar.bf_map) {
 596                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 597                 sq->uar_map = sq->uar.bf_map;
 598         } else {
 599                 sq->uar_map = sq->uar.map;
 600         }
 601         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 602         sq->max_inline  = param->max_inline;
 603
 604         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 605         if (err)
 606                 goto err_sq_wq_destroy;
 607
 608         if (param->icosq) {
 609                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 610
 611                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 612                                                 wq_sz,
 613                                                 GFP_KERNEL,
 614                                                 cpu_to_node(c->cpu));
 615                 if (!sq->ico_wqe_info) {
 616                         err = -ENOMEM;
 617                         goto err_free_sq_db;
 618                 }
 619         } else {
 620                 int txq_ix;
 621
 622                 txq_ix = c->ix + tc * priv->params.num_channels;
 623                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 624                 priv->txq_to_sq_map[txq_ix] = sq;
 625         }
 626
 627         sq->pdev      = c->pdev;
 628         sq->tstamp    = &priv->tstamp;
 629         sq->mkey_be   = c->mkey_be;
 630         sq->channel   = c;
 631         sq->tc        = tc;
 632         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 633         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 634
 635         return 0;
 636
 637 err_free_sq_db:
 638         mlx5e_free_sq_db(sq);
 639
 640 err_sq_wq_destroy:
 641         mlx5_wq_destroy(&sq->wq_ctrl);
 642
 643 err_unmap_free_uar:
 644         mlx5_unmap_free_uar(mdev, &sq->uar);
 645
 646         return err;
 647 }
 648
 649 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 650 {
 651         struct mlx5e_channel *c = sq->channel;
 652         struct mlx5e_priv *priv = c->priv;
 653
 654         kfree(sq->ico_wqe_info);
 655         mlx5e_free_sq_db(sq);
 656         mlx5_wq_destroy(&sq->wq_ctrl);
 657         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 658 }
 659
 660 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 661 {
 662         struct mlx5e_channel *c = sq->channel;
 663         struct mlx5e_priv *priv = c->priv;
 664         struct mlx5_core_dev *mdev = priv->mdev;
 665
 666         void *in;
 667         void *sqc;
 668         void *wq;
 669         int inlen;
 670         int err;
 671
 672         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 673                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 674         in = mlx5_vzalloc(inlen);
 675         if (!in)
 676                 return -ENOMEM;
 677
 678         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 679         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 680
 681         memcpy(sqc, param->sqc, sizeof(param->sqc));
 682
 683         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 684         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 685         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 686         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 687         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 688
 689         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 690         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 691         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 692                                           MLX5_ADAPTER_PAGE_SHIFT);
 693         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 694
 695         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 696                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 697
 698         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 699
 700         kvfree(in);
 701
 702         return err;
 703 }
 704
 705 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 706 {
 707         struct mlx5e_channel *c = sq->channel;
 708         struct mlx5e_priv *priv = c->priv;
 709         struct mlx5_core_dev *mdev = priv->mdev;
 710
 711         void *in;
 712         void *sqc;
 713         int inlen;
 714         int err;
 715
 716         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 717         in = mlx5_vzalloc(inlen);
 718         if (!in)
 719                 return -ENOMEM;
 720
 721         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 722
 723         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 724         MLX5_SET(sqc, sqc, state, next_state);
 725
 726         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 727
 728         kvfree(in);
 729
 730         return err;
 731 }
 732
 733 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 734 {
 735         struct mlx5e_channel *c = sq->channel;
 736         struct mlx5e_priv *priv = c->priv;
 737         struct mlx5_core_dev *mdev = priv->mdev;
 738
 739         mlx5_core_destroy_sq(mdev, sq->sqn);
 740 }
 741
 742 static int mlx5e_open_sq(struct mlx5e_channel *c,
 743                          int tc,
 744                          struct mlx5e_sq_param *param,
 745                          struct mlx5e_sq *sq)
 746 {
 747         int err;
 748
 749         err = mlx5e_create_sq(c, tc, param, sq);
 750         if (err)
 751                 return err;
 752
 753         err = mlx5e_enable_sq(sq, param);
 754         if (err)
 755                 goto err_destroy_sq;
 756
 757         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 758         if (err)
 759                 goto err_disable_sq;
 760
 761         if (sq->txq) {
 762                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 763                 netdev_tx_reset_queue(sq->txq);
 764                 netif_tx_start_queue(sq->txq);
 765         }
 766
 767         return 0;
 768
 769 err_disable_sq:
 770         mlx5e_disable_sq(sq);
 771 err_destroy_sq:
 772         mlx5e_destroy_sq(sq);
 773
 774         return err;
 775 }
 776
 777 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 778 {
 779         __netif_tx_lock_bh(txq);
 780         netif_tx_stop_queue(txq);
 781         __netif_tx_unlock_bh(txq);
 782 }
 783
 784 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 785 {
 786         if (sq->txq) {
 787                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 788                 /* prevent netif_tx_wake_queue */
 789                 napi_synchronize(&sq->channel->napi);
 790                 netif_tx_disable_queue(sq->txq);
 791
 792                 /* ensure hw is notified of all pending wqes */
 793                 if (mlx5e_sq_has_room_for(sq, 1))
 794                         mlx5e_send_nop(sq, true);
 795
 796                 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 797         }
 798
 799         while (sq->cc != sq->pc) /* wait till sq is empty */
 800                 msleep(20);
 801
 802         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 803         napi_synchronize(&sq->channel->napi);
 804
 805         mlx5e_disable_sq(sq);
 806         mlx5e_destroy_sq(sq);
 807 }
 808
 809 static int mlx5e_create_cq(struct mlx5e_channel *c,
 810                            struct mlx5e_cq_param *param,
 811                            struct mlx5e_cq *cq)
 812 {
 813         struct mlx5e_priv *priv = c->priv;
 814         struct mlx5_core_dev *mdev = priv->mdev;
 815         struct mlx5_core_cq *mcq = &cq->mcq;
 816         int eqn_not_used;
 817         unsigned int irqn;
 818         int err;
 819         u32 i;
 820
 821         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 822         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 823         param->eq_ix   = c->ix;
 824
 825         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 826                                &cq->wq_ctrl);
 827         if (err)
 828                 return err;
 829
 830         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 831
 832         cq->napi        = &c->napi;
 833
 834         mcq->cqe_sz     = 64;
 835         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 836         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 837         *mcq->set_ci_db = 0;
 838         *mcq->arm_db    = 0;
 839         mcq->vector     = param->eq_ix;
 840         mcq->comp       = mlx5e_completion_event;
 841         mcq->event      = mlx5e_cq_error_event;
 842         mcq->irqn       = irqn;
 843         mcq->uar        = &priv->cq_uar;
 844
 845         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 846                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 847
 848                 cqe->op_own = 0xf1;
 849         }
 850
 851         cq->channel = c;
 852         cq->priv = priv;
 853
 854         return 0;
 855 }
 856
 857 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 858 {
 859         mlx5_wq_destroy(&cq->wq_ctrl);
 860 }
 861
 862 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 863 {
 864         struct mlx5e_priv *priv = cq->priv;
 865         struct mlx5_core_dev *mdev = priv->mdev;
 866         struct mlx5_core_cq *mcq = &cq->mcq;
 867
 868         void *in;
 869         void *cqc;
 870         int inlen;
 871         unsigned int irqn_not_used;
 872         int eqn;
 873         int err;
 874
 875         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 876                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 877         in = mlx5_vzalloc(inlen);
 878         if (!in)
 879                 return -ENOMEM;
 880
 881         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 882
 883         memcpy(cqc, param->cqc, sizeof(param->cqc));
 884
 885         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 886                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 887
 888         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 889
 890         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 891         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 892         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 893                                             MLX5_ADAPTER_PAGE_SHIFT);
 894         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 895
 896         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 897
 898         kvfree(in);
 899
 900         if (err)
 901                 return err;
 902
 903         mlx5e_cq_arm(cq);
 904
 905         return 0;
 906 }
 907
 908 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 909 {
 910         struct mlx5e_priv *priv = cq->priv;
 911         struct mlx5_core_dev *mdev = priv->mdev;
 912
 913         mlx5_core_destroy_cq(mdev, &cq->mcq);
 914 }
 915
 916 static int mlx5e_open_cq(struct mlx5e_channel *c,
 917                          struct mlx5e_cq_param *param,
 918                          struct mlx5e_cq *cq,
 919                          u16 moderation_usecs,
 920                          u16 moderation_frames)
 921 {
 922         int err;
 923         struct mlx5e_priv *priv = c->priv;
 924         struct mlx5_core_dev *mdev = priv->mdev;
 925
 926         err = mlx5e_create_cq(c, param, cq);
 927         if (err)
 928                 return err;
 929
 930         err = mlx5e_enable_cq(cq, param);
 931         if (err)
 932                 goto err_destroy_cq;
 933
 934         if (MLX5_CAP_GEN(mdev, cq_moderation))
 935                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 936                                                moderation_usecs,
 937                                                moderation_frames);
 938         return 0;
 939
 940 err_destroy_cq:
 941         mlx5e_destroy_cq(cq);
 942
 943         return err;
 944 }
 945
 946 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 947 {
 948         mlx5e_disable_cq(cq);
 949         mlx5e_destroy_cq(cq);
 950 }
 951
 952 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 953 {
 954         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 955 }
 956
 957 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 958                              struct mlx5e_channel_param *cparam)
 959 {
 960         struct mlx5e_priv *priv = c->priv;
 961         int err;
 962         int tc;
 963
 964         for (tc = 0; tc < c->num_tc; tc++) {
 965                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 966                                     priv->params.tx_cq_moderation_usec,
 967                                     priv->params.tx_cq_moderation_pkts);
 968                 if (err)
 969                         goto err_close_tx_cqs;
 970         }
 971
 972         return 0;
 973
 974 err_close_tx_cqs:
 975         for (tc--; tc >= 0; tc--)
 976                 mlx5e_close_cq(&c->sq[tc].cq);
 977
 978         return err;
 979 }
 980
 981 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 982 {
 983         int tc;
 984
 985         for (tc = 0; tc < c->num_tc; tc++)
 986                 mlx5e_close_cq(&c->sq[tc].cq);
 987 }
 988
 989 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 990                           struct mlx5e_channel_param *cparam)
 991 {
 992         int err;
 993         int tc;
 994
 995         for (tc = 0; tc < c->num_tc; tc++) {
 996                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 997                 if (err)
 998                         goto err_close_sqs;
 999         }
1000
1001         return 0;
1002
1003 err_close_sqs:
1004         for (tc--; tc >= 0; tc--)
1005                 mlx5e_close_sq(&c->sq[tc]);
1006
1007         return err;
1008 }
1009
1010 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1011 {
1012         int tc;
1013
1014         for (tc = 0; tc < c->num_tc; tc++)
1015                 mlx5e_close_sq(&c->sq[tc]);
1016 }
1017
1018 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1019 {
1020         int i;
1021
1022         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1023                 priv->channeltc_to_txq_map[ix][i] =
1024                         ix + i * priv->params.num_channels;
1025 }
1026
1027 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1028                               struct mlx5e_channel_param *cparam,
1029                               struct mlx5e_channel **cp)
1030 {
1031         struct net_device *netdev = priv->netdev;
1032         int cpu = mlx5e_get_cpu(priv, ix);
1033         struct mlx5e_channel *c;
1034         int err;
1035
1036         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1037         if (!c)
1038                 return -ENOMEM;
1039
1040         c->priv     = priv;
1041         c->ix       = ix;
1042         c->cpu      = cpu;
1043         c->pdev     = &priv->mdev->pdev->dev;
1044         c->netdev   = priv->netdev;
1045         c->mkey_be  = cpu_to_be32(priv->mkey.key);
1046         c->num_tc   = priv->params.num_tc;
1047
1048         mlx5e_build_channeltc_to_txq_map(priv, ix);
1049
1050         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1051
1052         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1053         if (err)
1054                 goto err_napi_del;
1055
1056         err = mlx5e_open_tx_cqs(c, cparam);
1057         if (err)
1058                 goto err_close_icosq_cq;
1059
1060         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1061                             priv->params.rx_cq_moderation_usec,
1062                             priv->params.rx_cq_moderation_pkts);
1063         if (err)
1064                 goto err_close_tx_cqs;
1065
1066         napi_enable(&c->napi);
1067
1068         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1069         if (err)
1070                 goto err_disable_napi;
1071
1072         err = mlx5e_open_sqs(c, cparam);
1073         if (err)
1074                 goto err_close_icosq;
1075
1076         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1077         if (err)
1078                 goto err_close_sqs;
1079
1080         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1081         *cp = c;
1082
1083         return 0;
1084
1085 err_close_sqs:
1086         mlx5e_close_sqs(c);
1087
1088 err_close_icosq:
1089         mlx5e_close_sq(&c->icosq);
1090
1091 err_disable_napi:
1092         napi_disable(&c->napi);
1093         mlx5e_close_cq(&c->rq.cq);
1094
1095 err_close_tx_cqs:
1096         mlx5e_close_tx_cqs(c);
1097
1098 err_close_icosq_cq:
1099         mlx5e_close_cq(&c->icosq.cq);
1100
1101 err_napi_del:
1102         netif_napi_del(&c->napi);
1103         napi_hash_del(&c->napi);
1104         kfree(c);
1105
1106         return err;
1107 }
1108
1109 static void mlx5e_close_channel(struct mlx5e_channel *c)
1110 {
1111         mlx5e_close_rq(&c->rq);
1112         mlx5e_close_sqs(c);
1113         mlx5e_close_sq(&c->icosq);
1114         napi_disable(&c->napi);
1115         mlx5e_close_cq(&c->rq.cq);
1116         mlx5e_close_tx_cqs(c);
1117         mlx5e_close_cq(&c->icosq.cq);
1118         netif_napi_del(&c->napi);
1119
1120         napi_hash_del(&c->napi);
1121         synchronize_rcu();
1122
1123         kfree(c);
1124 }
1125
1126 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1127                                  struct mlx5e_rq_param *param)
1128 {
1129         void *rqc = param->rqc;
1130         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1131
1132         switch (priv->params.rq_wq_type) {
1133         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1134                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1135                          priv->params.mpwqe_log_num_strides - 9);
1136                 MLX5_SET(wq, wq, log_wqe_stride_size,
1137                          priv->params.mpwqe_log_stride_sz - 6);
1138                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1139                 break;
1140         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1141                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1142         }
1143
1144         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1145         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1146         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1147         MLX5_SET(wq, wq, pd,               priv->pdn);
1148         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1149
1150         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1151         param->wq.linear = 1;
1152 }
1153
1154 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1155 {
1156         void *rqc = param->rqc;
1157         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1158
1159         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1160         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1161 }
1162
1163 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1164                                         struct mlx5e_sq_param *param)
1165 {
1166         void *sqc = param->sqc;
1167         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1168
1169         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1170         MLX5_SET(wq, wq, pd,            priv->pdn);
1171
1172         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1173 }
1174
1175 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1176                                  struct mlx5e_sq_param *param)
1177 {
1178         void *sqc = param->sqc;
1179         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1180
1181         mlx5e_build_sq_param_common(priv, param);
1182         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1183
1184         param->max_inline = priv->params.tx_max_inline;
1185 }
1186
1187 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1188                                         struct mlx5e_cq_param *param)
1189 {
1190         void *cqc = param->cqc;
1191
1192         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1193 }
1194
1195 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1196                                     struct mlx5e_cq_param *param)
1197 {
1198         void *cqc = param->cqc;
1199         u8 log_cq_size;
1200
1201         switch (priv->params.rq_wq_type) {
1202         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1203                 log_cq_size = priv->params.log_rq_size +
1204                         priv->params.mpwqe_log_num_strides;
1205                 break;
1206         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1207                 log_cq_size = priv->params.log_rq_size;
1208         }
1209
1210         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1211         if (priv->params.rx_cqe_compress) {
1212                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1213                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1214         }
1215
1216         mlx5e_build_common_cq_param(priv, param);
1217 }
1218
1219 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1220                                     struct mlx5e_cq_param *param)
1221 {
1222         void *cqc = param->cqc;
1223
1224         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1225
1226         mlx5e_build_common_cq_param(priv, param);
1227 }
1228
1229 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1230                                      struct mlx5e_cq_param *param,
1231                                      u8 log_wq_size)
1232 {
1233         void *cqc = param->cqc;
1234
1235         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1236
1237         mlx5e_build_common_cq_param(priv, param);
1238 }
1239
1240 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1241                                     struct mlx5e_sq_param *param,
1242                                     u8 log_wq_size)
1243 {
1244         void *sqc = param->sqc;
1245         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1246
1247         mlx5e_build_sq_param_common(priv, param);
1248
1249         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1250         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1251
1252         param->icosq = true;
1253 }
1254
1255 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1256 {
1257         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1258
1259         mlx5e_build_rq_param(priv, &cparam->rq);
1260         mlx5e_build_sq_param(priv, &cparam->sq);
1261         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1262         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1263         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1264         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1265 }
1266
1267 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1268 {
1269         struct mlx5e_channel_param *cparam;
1270         int nch = priv->params.num_channels;
1271         int err = -ENOMEM;
1272         int i;
1273         int j;
1274
1275         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1276                                 GFP_KERNEL);
1277
1278         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1279                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1280
1281         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1282
1283         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1284                 goto err_free_txq_to_sq_map;
1285
1286         mlx5e_build_channel_param(priv, cparam);
1287
1288         for (i = 0; i < nch; i++) {
1289                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1290                 if (err)
1291                         goto err_close_channels;
1292         }
1293
1294         for (j = 0; j < nch; j++) {
1295                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1296                 if (err)
1297                         goto err_close_channels;
1298         }
1299
1300         kfree(cparam);
1301         return 0;
1302
1303 err_close_channels:
1304         for (i--; i >= 0; i--)
1305                 mlx5e_close_channel(priv->channel[i]);
1306
1307 err_free_txq_to_sq_map:
1308         kfree(priv->txq_to_sq_map);
1309         kfree(priv->channel);
1310         kfree(cparam);
1311
1312         return err;
1313 }
1314
1315 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1316 {
1317         int i;
1318
1319         for (i = 0; i < priv->params.num_channels; i++)
1320                 mlx5e_close_channel(priv->channel[i]);
1321
1322         kfree(priv->txq_to_sq_map);
1323         kfree(priv->channel);
1324 }
1325
1326 static int mlx5e_rx_hash_fn(int hfunc)
1327 {
1328         return (hfunc == ETH_RSS_HASH_TOP) ?
1329                MLX5_RX_HASH_FN_TOEPLITZ :
1330                MLX5_RX_HASH_FN_INVERTED_XOR8;
1331 }
1332
1333 static int mlx5e_bits_invert(unsigned long a, int size)
1334 {
1335         int inv = 0;
1336         int i;
1337
1338         for (i = 0; i < size; i++)
1339                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1340
1341         return inv;
1342 }
1343
1344 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1345 {
1346         int i;
1347
1348         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1349                 int ix = i;
1350                 u32 rqn;
1351
1352                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1353                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1354
1355                 ix = priv->params.indirection_rqt[ix];
1356                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1357                                 priv->channel[ix]->rq.rqn :
1358                                 priv->drop_rq.rqn;
1359                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1360         }
1361 }
1362
1363 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1364                                       int ix)
1365 {
1366         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1367                         priv->channel[ix]->rq.rqn :
1368                         priv->drop_rq.rqn;
1369
1370         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1371 }
1372
1373 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
1374 {
1375         struct mlx5_core_dev *mdev = priv->mdev;
1376         void *rqtc;
1377         int inlen;
1378         int err;
1379         u32 *in;
1380
1381         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1382         in = mlx5_vzalloc(inlen);
1383         if (!in)
1384                 return -ENOMEM;
1385
1386         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1387
1388         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1389         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1390
1391         if (sz > 1) /* RSS */
1392                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1393         else
1394                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1395
1396         err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
1397
1398         kvfree(in);
1399         return err;
1400 }
1401
1402 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1403 {
1404         mlx5_core_destroy_rqt(priv->mdev, rqtn);
1405 }
1406
1407 static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1408 {
1409         int nch = mlx5e_get_max_num_channels(priv->mdev);
1410         u32 *rqtn;
1411         int err;
1412         int ix;
1413
1414         /* Indirect RQT */
1415         rqtn = &priv->indir_rqtn;
1416         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1417         if (err)
1418                 return err;
1419
1420         /* Direct RQTs */
1421         for (ix = 0; ix < nch; ix++) {
1422                 rqtn = &priv->direct_tir[ix].rqtn;
1423                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1424                 if (err)
1425                         goto err_destroy_rqts;
1426         }
1427
1428         return 0;
1429
1430 err_destroy_rqts:
1431         for (ix--; ix >= 0; ix--)
1432                 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1433
1434         mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1435
1436         return err;
1437 }
1438
1439 static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1440 {
1441         int nch = mlx5e_get_max_num_channels(priv->mdev);
1442         int i;
1443
1444         for (i = 0; i < nch; i++)
1445                 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1446
1447         mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1448 }
1449
1450 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1451 {
1452         struct mlx5_core_dev *mdev = priv->mdev;
1453         void *rqtc;
1454         int inlen;
1455         u32 *in;
1456         int err;
1457
1458         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1459         in = mlx5_vzalloc(inlen);
1460         if (!in)
1461                 return -ENOMEM;
1462
1463         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1464
1465         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1466         if (sz > 1) /* RSS */
1467                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1468         else
1469                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1470
1471         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1472
1473         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1474
1475         kvfree(in);
1476
1477         return err;
1478 }
1479
1480 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1481 {
1482         u32 rqtn;
1483         int ix;
1484
1485         rqtn = priv->indir_rqtn;
1486         mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1487         for (ix = 0; ix < priv->params.num_channels; ix++) {
1488                 rqtn = priv->direct_tir[ix].rqtn;
1489                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1490         }
1491 }
1492
1493 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1494 {
1495         if (!priv->params.lro_en)
1496                 return;
1497
1498 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1499
1500         MLX5_SET(tirc, tirc, lro_enable_mask,
1501                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1502                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1503         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1504                  (priv->params.lro_wqe_sz -
1505                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1506         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1507                  MLX5_CAP_ETH(priv->mdev,
1508                               lro_timer_supported_periods[2]));
1509 }
1510
1511 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1512 {
1513         MLX5_SET(tirc, tirc, rx_hash_fn,
1514                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1515         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1516                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1517                                              rx_hash_toeplitz_key);
1518                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1519                                                rx_hash_toeplitz_key);
1520
1521                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1522                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1523         }
1524 }
1525
1526 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1527 {
1528         struct mlx5_core_dev *mdev = priv->mdev;
1529
1530         void *in;
1531         void *tirc;
1532         int inlen;
1533         int err;
1534         int tt;
1535         int ix;
1536
1537         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1538         in = mlx5_vzalloc(inlen);
1539         if (!in)
1540                 return -ENOMEM;
1541
1542         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1543         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1544
1545         mlx5e_build_tir_ctx_lro(tirc, priv);
1546
1547         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1548                 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1549                                            inlen);
1550                 if (err)
1551                         goto free_in;
1552         }
1553
1554         for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1555                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1556                                            in, inlen);
1557                 if (err)
1558                         goto free_in;
1559         }
1560
1561 free_in:
1562         kvfree(in);
1563
1564         return err;
1565 }
1566
1567 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1568 {
1569         void *in;
1570         int inlen;
1571         int err;
1572         int i;
1573
1574         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1575         in = mlx5_vzalloc(inlen);
1576         if (!in)
1577                 return -ENOMEM;
1578
1579         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1580
1581         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1582                 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1583                                            inlen);
1584                 if (err)
1585                         return err;
1586         }
1587
1588         for (i = 0; i < priv->params.num_channels; i++) {
1589                 err = mlx5_core_modify_tir(priv->mdev,
1590                                            priv->direct_tir[i].tirn, in,
1591                                            inlen);
1592                 if (err)
1593                         return err;
1594         }
1595
1596         kvfree(in);
1597
1598         return 0;
1599 }
1600
1601 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1602 {
1603         struct mlx5_core_dev *mdev = priv->mdev;
1604         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1605         int err;
1606
1607         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1608         if (err)
1609                 return err;
1610
1611         /* Update vport context MTU */
1612         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1613         return 0;
1614 }
1615
1616 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1617 {
1618         struct mlx5_core_dev *mdev = priv->mdev;
1619         u16 hw_mtu = 0;
1620         int err;
1621
1622         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1623         if (err || !hw_mtu) /* fallback to port oper mtu */
1624                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1625
1626         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1627 }
1628
1629 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1630 {
1631         struct mlx5e_priv *priv = netdev_priv(netdev);
1632         u16 mtu;
1633         int err;
1634
1635         err = mlx5e_set_mtu(priv, netdev->mtu);
1636         if (err)
1637                 return err;
1638
1639         mlx5e_query_mtu(priv, &mtu);
1640         if (mtu != netdev->mtu)
1641                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1642                             __func__, mtu, netdev->mtu);
1643
1644         netdev->mtu = mtu;
1645         return 0;
1646 }
1647
1648 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1649 {
1650         struct mlx5e_priv *priv = netdev_priv(netdev);
1651         int nch = priv->params.num_channels;
1652         int ntc = priv->params.num_tc;
1653         int tc;
1654
1655         netdev_reset_tc(netdev);
1656
1657         if (ntc == 1)
1658                 return;
1659
1660         netdev_set_num_tc(netdev, ntc);
1661
1662         for (tc = 0; tc < ntc; tc++)
1663                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1664 }
1665
1666 int mlx5e_open_locked(struct net_device *netdev)
1667 {
1668         struct mlx5e_priv *priv = netdev_priv(netdev);
1669         int num_txqs;
1670         int err;
1671
1672         set_bit(MLX5E_STATE_OPENED, &priv->state);
1673
1674         mlx5e_netdev_set_tcs(netdev);
1675
1676         num_txqs = priv->params.num_channels * priv->params.num_tc;
1677         netif_set_real_num_tx_queues(netdev, num_txqs);
1678         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1679
1680         err = mlx5e_set_dev_port_mtu(netdev);
1681         if (err)
1682                 goto err_clear_state_opened_flag;
1683
1684         err = mlx5e_open_channels(priv);
1685         if (err) {
1686                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1687                            __func__, err);
1688                 goto err_clear_state_opened_flag;
1689         }
1690
1691         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1692         if (err) {
1693                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1694                            __func__, err);
1695                 goto err_close_channels;
1696         }
1697
1698         mlx5e_redirect_rqts(priv);
1699         mlx5e_update_carrier(priv);
1700         mlx5e_timestamp_init(priv);
1701 #ifdef CONFIG_RFS_ACCEL
1702         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1703 #endif
1704
1705         queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1706
1707         return 0;
1708
1709 err_close_channels:
1710         mlx5e_close_channels(priv);
1711 err_clear_state_opened_flag:
1712         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1713         return err;
1714 }
1715
1716 static int mlx5e_open(struct net_device *netdev)
1717 {
1718         struct mlx5e_priv *priv = netdev_priv(netdev);
1719         int err;
1720
1721         mutex_lock(&priv->state_lock);
1722         err = mlx5e_open_locked(netdev);
1723         mutex_unlock(&priv->state_lock);
1724
1725         return err;
1726 }
1727
1728 int mlx5e_close_locked(struct net_device *netdev)
1729 {
1730         struct mlx5e_priv *priv = netdev_priv(netdev);
1731
1732         /* May already be CLOSED in case a previous configuration operation
1733          * (e.g RX/TX queue size change) that involves close&open failed.
1734          */
1735         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1736                 return 0;
1737
1738         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1739
1740         mlx5e_timestamp_cleanup(priv);
1741         netif_carrier_off(priv->netdev);
1742         mlx5e_redirect_rqts(priv);
1743         mlx5e_close_channels(priv);
1744
1745         return 0;
1746 }
1747
1748 static int mlx5e_close(struct net_device *netdev)
1749 {
1750         struct mlx5e_priv *priv = netdev_priv(netdev);
1751         int err;
1752
1753         mutex_lock(&priv->state_lock);
1754         err = mlx5e_close_locked(netdev);
1755         mutex_unlock(&priv->state_lock);
1756
1757         return err;
1758 }
1759
1760 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1761                                 struct mlx5e_rq *rq,
1762                                 struct mlx5e_rq_param *param)
1763 {
1764         struct mlx5_core_dev *mdev = priv->mdev;
1765         void *rqc = param->rqc;
1766         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1767         int err;
1768
1769         param->wq.db_numa_node = param->wq.buf_numa_node;
1770
1771         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1772                                 &rq->wq_ctrl);
1773         if (err)
1774                 return err;
1775
1776         rq->priv = priv;
1777
1778         return 0;
1779 }
1780
1781 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1782                                 struct mlx5e_cq *cq,
1783                                 struct mlx5e_cq_param *param)
1784 {
1785         struct mlx5_core_dev *mdev = priv->mdev;
1786         struct mlx5_core_cq *mcq = &cq->mcq;
1787         int eqn_not_used;
1788         unsigned int irqn;
1789         int err;
1790
1791         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1792                                &cq->wq_ctrl);
1793         if (err)
1794                 return err;
1795
1796         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1797
1798         mcq->cqe_sz     = 64;
1799         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1800         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1801         *mcq->set_ci_db = 0;
1802         *mcq->arm_db    = 0;
1803         mcq->vector     = param->eq_ix;
1804         mcq->comp       = mlx5e_completion_event;
1805         mcq->event      = mlx5e_cq_error_event;
1806         mcq->irqn       = irqn;
1807         mcq->uar        = &priv->cq_uar;
1808
1809         cq->priv = priv;
1810
1811         return 0;
1812 }
1813
1814 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1815 {
1816         struct mlx5e_cq_param cq_param;
1817         struct mlx5e_rq_param rq_param;
1818         struct mlx5e_rq *rq = &priv->drop_rq;
1819         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1820         int err;
1821
1822         memset(&cq_param, 0, sizeof(cq_param));
1823         memset(&rq_param, 0, sizeof(rq_param));
1824         mlx5e_build_drop_rq_param(&rq_param);
1825
1826         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1827         if (err)
1828                 return err;
1829
1830         err = mlx5e_enable_cq(cq, &cq_param);
1831         if (err)
1832                 goto err_destroy_cq;
1833
1834         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1835         if (err)
1836                 goto err_disable_cq;
1837
1838         err = mlx5e_enable_rq(rq, &rq_param);
1839         if (err)
1840                 goto err_destroy_rq;
1841
1842         return 0;
1843
1844 err_destroy_rq:
1845         mlx5e_destroy_rq(&priv->drop_rq);
1846
1847 err_disable_cq:
1848         mlx5e_disable_cq(&priv->drop_rq.cq);
1849
1850 err_destroy_cq:
1851         mlx5e_destroy_cq(&priv->drop_rq.cq);
1852
1853         return err;
1854 }
1855
1856 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1857 {
1858         mlx5e_disable_rq(&priv->drop_rq);
1859         mlx5e_destroy_rq(&priv->drop_rq);
1860         mlx5e_disable_cq(&priv->drop_rq.cq);
1861         mlx5e_destroy_cq(&priv->drop_rq.cq);
1862 }
1863
1864 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1865 {
1866         struct mlx5_core_dev *mdev = priv->mdev;
1867         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1868         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1869
1870         memset(in, 0, sizeof(in));
1871
1872         MLX5_SET(tisc, tisc, prio, tc << 1);
1873         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1874
1875         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1876 }
1877
1878 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1879 {
1880         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1881 }
1882
1883 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1884 {
1885         int err;
1886         int tc;
1887
1888         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1889                 err = mlx5e_create_tis(priv, tc);
1890                 if (err)
1891                         goto err_close_tises;
1892         }
1893
1894         return 0;
1895
1896 err_close_tises:
1897         for (tc--; tc >= 0; tc--)
1898                 mlx5e_destroy_tis(priv, tc);
1899
1900         return err;
1901 }
1902
1903 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1904 {
1905         int tc;
1906
1907         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1908                 mlx5e_destroy_tis(priv, tc);
1909 }
1910
1911 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1912                                       enum mlx5e_traffic_types tt)
1913 {
1914         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1915
1916         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1917
1918 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1919                                  MLX5_HASH_FIELD_SEL_DST_IP)
1920
1921 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1922                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1923                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1924                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1925
1926 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1927                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1928                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1929
1930         mlx5e_build_tir_ctx_lro(tirc, priv);
1931
1932         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1933         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
1934         mlx5e_build_tir_ctx_hash(tirc, priv);
1935
1936         switch (tt) {
1937         case MLX5E_TT_IPV4_TCP:
1938                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1939                          MLX5_L3_PROT_TYPE_IPV4);
1940                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1941                          MLX5_L4_PROT_TYPE_TCP);
1942                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1943                          MLX5_HASH_IP_L4PORTS);
1944                 break;
1945
1946         case MLX5E_TT_IPV6_TCP:
1947                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1948                          MLX5_L3_PROT_TYPE_IPV6);
1949                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1950                          MLX5_L4_PROT_TYPE_TCP);
1951                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1952                          MLX5_HASH_IP_L4PORTS);
1953                 break;
1954
1955         case MLX5E_TT_IPV4_UDP:
1956                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1957                          MLX5_L3_PROT_TYPE_IPV4);
1958                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1959                          MLX5_L4_PROT_TYPE_UDP);
1960                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1961                          MLX5_HASH_IP_L4PORTS);
1962                 break;
1963
1964         case MLX5E_TT_IPV6_UDP:
1965                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1966                          MLX5_L3_PROT_TYPE_IPV6);
1967                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1968                          MLX5_L4_PROT_TYPE_UDP);
1969                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1970                          MLX5_HASH_IP_L4PORTS);
1971                 break;
1972
1973         case MLX5E_TT_IPV4_IPSEC_AH:
1974                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1975                          MLX5_L3_PROT_TYPE_IPV4);
1976                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1977                          MLX5_HASH_IP_IPSEC_SPI);
1978                 break;
1979
1980         case MLX5E_TT_IPV6_IPSEC_AH:
1981                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1982                          MLX5_L3_PROT_TYPE_IPV6);
1983                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1984                          MLX5_HASH_IP_IPSEC_SPI);
1985                 break;
1986
1987         case MLX5E_TT_IPV4_IPSEC_ESP:
1988                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1989                          MLX5_L3_PROT_TYPE_IPV4);
1990                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1991                          MLX5_HASH_IP_IPSEC_SPI);
1992                 break;
1993
1994         case MLX5E_TT_IPV6_IPSEC_ESP:
1995                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1996                          MLX5_L3_PROT_TYPE_IPV6);
1997                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1998                          MLX5_HASH_IP_IPSEC_SPI);
1999                 break;
2000
2001         case MLX5E_TT_IPV4:
2002                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2003                          MLX5_L3_PROT_TYPE_IPV4);
2004                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2005                          MLX5_HASH_IP);
2006                 break;
2007
2008         case MLX5E_TT_IPV6:
2009                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2010                          MLX5_L3_PROT_TYPE_IPV6);
2011                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2012                          MLX5_HASH_IP);
2013                 break;
2014         default:
2015                 WARN_ONCE(true,
2016                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2017         }
2018 }
2019
2020 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2021                                        u32 rqtn)
2022 {
2023         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2024
2025         mlx5e_build_tir_ctx_lro(tirc, priv);
2026
2027         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2028         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2029         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2030 }
2031
2032 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2033 {
2034         int nch = mlx5e_get_max_num_channels(priv->mdev);
2035         void *tirc;
2036         int inlen;
2037         u32 *tirn;
2038         int err;
2039         u32 *in;
2040         int ix;
2041         int tt;
2042
2043         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2044         in = mlx5_vzalloc(inlen);
2045         if (!in)
2046                 return -ENOMEM;
2047
2048         /* indirect tirs */
2049         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2050                 memset(in, 0, inlen);
2051                 tirn = &priv->indir_tirn[tt];
2052                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2053                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2054                 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2055                 if (err)
2056                         goto err_destroy_tirs;
2057         }
2058
2059         /* direct tirs */
2060         for (ix = 0; ix < nch; ix++) {
2061                 memset(in, 0, inlen);
2062                 tirn = &priv->direct_tir[ix].tirn;
2063                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2064                 mlx5e_build_direct_tir_ctx(priv, tirc,
2065                                            priv->direct_tir[ix].rqtn);
2066                 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2067                 if (err)
2068                         goto err_destroy_ch_tirs;
2069         }
2070
2071         kvfree(in);
2072
2073         return 0;
2074
2075 err_destroy_ch_tirs:
2076         for (ix--; ix >= 0; ix--)
2077                 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2078
2079 err_destroy_tirs:
2080         for (tt--; tt >= 0; tt--)
2081                 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2082
2083         kvfree(in);
2084
2085         return err;
2086 }
2087
2088 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
2089 {
2090         int nch = mlx5e_get_max_num_channels(priv->mdev);
2091         int i;
2092
2093         for (i = 0; i < nch; i++)
2094                 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2095
2096         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2097                 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
2098 }
2099
2100 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2101 {
2102         int err = 0;
2103         int i;
2104
2105         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2106                 return 0;
2107
2108         for (i = 0; i < priv->params.num_channels; i++) {
2109                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2110                 if (err)
2111                         return err;
2112         }
2113
2114         return 0;
2115 }
2116
2117 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2118 {
2119         struct mlx5e_priv *priv = netdev_priv(netdev);
2120         bool was_opened;
2121         int err = 0;
2122
2123         if (tc && tc != MLX5E_MAX_NUM_TC)
2124                 return -EINVAL;
2125
2126         mutex_lock(&priv->state_lock);
2127
2128         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2129         if (was_opened)
2130                 mlx5e_close_locked(priv->netdev);
2131
2132         priv->params.num_tc = tc ? tc : 1;
2133
2134         if (was_opened)
2135                 err = mlx5e_open_locked(priv->netdev);
2136
2137         mutex_unlock(&priv->state_lock);
2138
2139         return err;
2140 }
2141
2142 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2143                               __be16 proto, struct tc_to_netdev *tc)
2144 {
2145         struct mlx5e_priv *priv = netdev_priv(dev);
2146
2147         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2148                 goto mqprio;
2149
2150         switch (tc->type) {
2151         case TC_SETUP_CLSFLOWER:
2152                 switch (tc->cls_flower->command) {
2153                 case TC_CLSFLOWER_REPLACE:
2154                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2155                 case TC_CLSFLOWER_DESTROY:
2156                         return mlx5e_delete_flower(priv, tc->cls_flower);
2157                 case TC_CLSFLOWER_STATS:
2158                         return mlx5e_stats_flower(priv, tc->cls_flower);
2159                 }
2160         default:
2161                 return -EOPNOTSUPP;
2162         }
2163
2164 mqprio:
2165         if (tc->type != TC_SETUP_MQPRIO)
2166                 return -EINVAL;
2167
2168         return mlx5e_setup_tc(dev, tc->tc);
2169 }
2170
2171 static struct rtnl_link_stats64 *
2172 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2173 {
2174         struct mlx5e_priv *priv = netdev_priv(dev);
2175         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2176         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2177         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2178
2179         stats->rx_packets = sstats->rx_packets;
2180         stats->rx_bytes   = sstats->rx_bytes;
2181         stats->tx_packets = sstats->tx_packets;
2182         stats->tx_bytes   = sstats->tx_bytes;
2183
2184         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2185         stats->tx_dropped = sstats->tx_queue_dropped;
2186
2187         stats->rx_length_errors =
2188                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2189                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2190                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2191         stats->rx_crc_errors =
2192                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2193         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2194         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2195         stats->tx_carrier_errors =
2196                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2197         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2198                            stats->rx_frame_errors;
2199         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2200
2201         /* vport multicast also counts packets that are dropped due to steering
2202          * or rx out of buffer
2203          */
2204         stats->multicast =
2205                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2206
2207         return stats;
2208 }
2209
2210 static void mlx5e_set_rx_mode(struct net_device *dev)
2211 {
2212         struct mlx5e_priv *priv = netdev_priv(dev);
2213
2214         queue_work(priv->wq, &priv->set_rx_mode_work);
2215 }
2216
2217 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2218 {
2219         struct mlx5e_priv *priv = netdev_priv(netdev);
2220         struct sockaddr *saddr = addr;
2221
2222         if (!is_valid_ether_addr(saddr->sa_data))
2223                 return -EADDRNOTAVAIL;
2224
2225         netif_addr_lock_bh(netdev);
2226         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2227         netif_addr_unlock_bh(netdev);
2228
2229         queue_work(priv->wq, &priv->set_rx_mode_work);
2230
2231         return 0;
2232 }
2233
2234 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2235         do {                                            \
2236                 if (enable)                             \
2237                         netdev->features |= feature;    \
2238                 else                                    \
2239                         netdev->features &= ~feature;   \
2240         } while (0)
2241
2242 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2243
2244 static int set_feature_lro(struct net_device *netdev, bool enable)
2245 {
2246         struct mlx5e_priv *priv = netdev_priv(netdev);
2247         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2248         int err;
2249
2250         mutex_lock(&priv->state_lock);
2251
2252         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2253                 mlx5e_close_locked(priv->netdev);
2254
2255         priv->params.lro_en = enable;
2256         err = mlx5e_modify_tirs_lro(priv);
2257         if (err) {
2258                 netdev_err(netdev, "lro modify failed, %d\n", err);
2259                 priv->params.lro_en = !enable;
2260         }
2261
2262         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2263                 mlx5e_open_locked(priv->netdev);
2264
2265         mutex_unlock(&priv->state_lock);
2266
2267         return err;
2268 }
2269
2270 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2271 {
2272         struct mlx5e_priv *priv = netdev_priv(netdev);
2273
2274         if (enable)
2275                 mlx5e_enable_vlan_filter(priv);
2276         else
2277                 mlx5e_disable_vlan_filter(priv);
2278
2279         return 0;
2280 }
2281
2282 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2283 {
2284         struct mlx5e_priv *priv = netdev_priv(netdev);
2285
2286         if (!enable && mlx5e_tc_num_filters(priv)) {
2287                 netdev_err(netdev,
2288                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2289                 return -EINVAL;
2290         }
2291
2292         return 0;
2293 }
2294
2295 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2296 {
2297         struct mlx5e_priv *priv = netdev_priv(netdev);
2298         struct mlx5_core_dev *mdev = priv->mdev;
2299
2300         return mlx5_set_port_fcs(mdev, !enable);
2301 }
2302
2303 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2304 {
2305         struct mlx5e_priv *priv = netdev_priv(netdev);
2306         int err;
2307
2308         mutex_lock(&priv->state_lock);
2309
2310         priv->params.vlan_strip_disable = !enable;
2311         err = mlx5e_modify_rqs_vsd(priv, !enable);
2312         if (err)
2313                 priv->params.vlan_strip_disable = enable;
2314
2315         mutex_unlock(&priv->state_lock);
2316
2317         return err;
2318 }
2319
2320 #ifdef CONFIG_RFS_ACCEL
2321 static int set_feature_arfs(struct net_device *netdev, bool enable)
2322 {
2323         struct mlx5e_priv *priv = netdev_priv(netdev);
2324         int err;
2325
2326         if (enable)
2327                 err = mlx5e_arfs_enable(priv);
2328         else
2329                 err = mlx5e_arfs_disable(priv);
2330
2331         return err;
2332 }
2333 #endif
2334
2335 static int mlx5e_handle_feature(struct net_device *netdev,
2336                                 netdev_features_t wanted_features,
2337                                 netdev_features_t feature,
2338                                 mlx5e_feature_handler feature_handler)
2339 {
2340         netdev_features_t changes = wanted_features ^ netdev->features;
2341         bool enable = !!(wanted_features & feature);
2342         int err;
2343
2344         if (!(changes & feature))
2345                 return 0;
2346
2347         err = feature_handler(netdev, enable);
2348         if (err) {
2349                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2350                            enable ? "Enable" : "Disable", feature, err);
2351                 return err;
2352         }
2353
2354         MLX5E_SET_FEATURE(netdev, feature, enable);
2355         return 0;
2356 }
2357
2358 static int mlx5e_set_features(struct net_device *netdev,
2359                               netdev_features_t features)
2360 {
2361         int err;
2362
2363         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2364                                     set_feature_lro);
2365         err |= mlx5e_handle_feature(netdev, features,
2366                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2367                                     set_feature_vlan_filter);
2368         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2369                                     set_feature_tc_num_filters);
2370         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2371                                     set_feature_rx_all);
2372         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2373                                     set_feature_rx_vlan);
2374 #ifdef CONFIG_RFS_ACCEL
2375         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2376                                     set_feature_arfs);
2377 #endif
2378
2379         return err ? -EINVAL : 0;
2380 }
2381
2382 #define MXL5_HW_MIN_MTU 64
2383 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2384
2385 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2386 {
2387         struct mlx5e_priv *priv = netdev_priv(netdev);
2388         struct mlx5_core_dev *mdev = priv->mdev;
2389         bool was_opened;
2390         u16 max_mtu;
2391         u16 min_mtu;
2392         int err = 0;
2393
2394         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2395
2396         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2397         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2398
2399         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2400                 netdev_err(netdev,
2401                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2402                            __func__, new_mtu, min_mtu, max_mtu);
2403                 return -EINVAL;
2404         }
2405
2406         mutex_lock(&priv->state_lock);
2407
2408         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2409         if (was_opened)
2410                 mlx5e_close_locked(netdev);
2411
2412         netdev->mtu = new_mtu;
2413
2414         if (was_opened)
2415                 err = mlx5e_open_locked(netdev);
2416
2417         mutex_unlock(&priv->state_lock);
2418
2419         return err;
2420 }
2421
2422 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2423 {
2424         switch (cmd) {
2425         case SIOCSHWTSTAMP:
2426                 return mlx5e_hwstamp_set(dev, ifr);
2427         case SIOCGHWTSTAMP:
2428                 return mlx5e_hwstamp_get(dev, ifr);
2429         default:
2430                 return -EOPNOTSUPP;
2431         }
2432 }
2433
2434 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2435 {
2436         struct mlx5e_priv *priv = netdev_priv(dev);
2437         struct mlx5_core_dev *mdev = priv->mdev;
2438
2439         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2440 }
2441
2442 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2443 {
2444         struct mlx5e_priv *priv = netdev_priv(dev);
2445         struct mlx5_core_dev *mdev = priv->mdev;
2446
2447         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2448                                            vlan, qos);
2449 }
2450
2451 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2452 {
2453         struct mlx5e_priv *priv = netdev_priv(dev);
2454         struct mlx5_core_dev *mdev = priv->mdev;
2455
2456         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2457 }
2458
2459 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2460 {
2461         struct mlx5e_priv *priv = netdev_priv(dev);
2462         struct mlx5_core_dev *mdev = priv->mdev;
2463
2464         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2465 }
2466 static int mlx5_vport_link2ifla(u8 esw_link)
2467 {
2468         switch (esw_link) {
2469         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2470                 return IFLA_VF_LINK_STATE_DISABLE;
2471         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2472                 return IFLA_VF_LINK_STATE_ENABLE;
2473         }
2474         return IFLA_VF_LINK_STATE_AUTO;
2475 }
2476
2477 static int mlx5_ifla_link2vport(u8 ifla_link)
2478 {
2479         switch (ifla_link) {
2480         case IFLA_VF_LINK_STATE_DISABLE:
2481                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2482         case IFLA_VF_LINK_STATE_ENABLE:
2483                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2484         }
2485         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2486 }
2487
2488 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2489                                    int link_state)
2490 {
2491         struct mlx5e_priv *priv = netdev_priv(dev);
2492         struct mlx5_core_dev *mdev = priv->mdev;
2493
2494         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2495                                             mlx5_ifla_link2vport(link_state));
2496 }
2497
2498 static int mlx5e_get_vf_config(struct net_device *dev,
2499                                int vf, struct ifla_vf_info *ivi)
2500 {
2501         struct mlx5e_priv *priv = netdev_priv(dev);
2502         struct mlx5_core_dev *mdev = priv->mdev;
2503         int err;
2504
2505         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2506         if (err)
2507                 return err;
2508         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2509         return 0;
2510 }
2511
2512 static int mlx5e_get_vf_stats(struct net_device *dev,
2513                               int vf, struct ifla_vf_stats *vf_stats)
2514 {
2515         struct mlx5e_priv *priv = netdev_priv(dev);
2516         struct mlx5_core_dev *mdev = priv->mdev;
2517
2518         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2519                                             vf_stats);
2520 }
2521
2522 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2523                                  sa_family_t sa_family, __be16 port)
2524 {
2525         struct mlx5e_priv *priv = netdev_priv(netdev);
2526
2527         if (!mlx5e_vxlan_allowed(priv->mdev))
2528                 return;
2529
2530         mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1);
2531 }
2532
2533 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2534                                  sa_family_t sa_family, __be16 port)
2535 {
2536         struct mlx5e_priv *priv = netdev_priv(netdev);
2537
2538         if (!mlx5e_vxlan_allowed(priv->mdev))
2539                 return;
2540
2541         mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0);
2542 }
2543
2544 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2545                                                     struct sk_buff *skb,
2546                                                     netdev_features_t features)
2547 {
2548         struct udphdr *udph;
2549         u16 proto;
2550         u16 port = 0;
2551
2552         switch (vlan_get_protocol(skb)) {
2553         case htons(ETH_P_IP):
2554                 proto = ip_hdr(skb)->protocol;
2555                 break;
2556         case htons(ETH_P_IPV6):
2557                 proto = ipv6_hdr(skb)->nexthdr;
2558                 break;
2559         default:
2560                 goto out;
2561         }
2562
2563         if (proto == IPPROTO_UDP) {
2564                 udph = udp_hdr(skb);
2565                 port = be16_to_cpu(udph->dest);
2566         }
2567
2568         /* Verify if UDP port is being offloaded by HW */
2569         if (port && mlx5e_vxlan_lookup_port(priv, port))
2570                 return features;
2571
2572 out:
2573         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2574         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2575 }
2576
2577 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2578                                               struct net_device *netdev,
2579                                               netdev_features_t features)
2580 {
2581         struct mlx5e_priv *priv = netdev_priv(netdev);
2582
2583         features = vlan_features_check(skb, features);
2584         features = vxlan_features_check(skb, features);
2585
2586         /* Validate if the tunneled packet is being offloaded by HW */
2587         if (skb->encapsulation &&
2588             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2589                 return mlx5e_vxlan_features_check(priv, skb, features);
2590
2591         return features;
2592 }
2593
2594 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2595         .ndo_open                = mlx5e_open,
2596         .ndo_stop                = mlx5e_close,
2597         .ndo_start_xmit          = mlx5e_xmit,
2598         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2599         .ndo_select_queue        = mlx5e_select_queue,
2600         .ndo_get_stats64         = mlx5e_get_stats,
2601         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2602         .ndo_set_mac_address     = mlx5e_set_mac,
2603         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2604         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2605         .ndo_set_features        = mlx5e_set_features,
2606         .ndo_change_mtu          = mlx5e_change_mtu,
2607         .ndo_do_ioctl            = mlx5e_ioctl,
2608 #ifdef CONFIG_RFS_ACCEL
2609         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2610 #endif
2611 };
2612
2613 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2614         .ndo_open                = mlx5e_open,
2615         .ndo_stop                = mlx5e_close,
2616         .ndo_start_xmit          = mlx5e_xmit,
2617         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2618         .ndo_select_queue        = mlx5e_select_queue,
2619         .ndo_get_stats64         = mlx5e_get_stats,
2620         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2621         .ndo_set_mac_address     = mlx5e_set_mac,
2622         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2623         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2624         .ndo_set_features        = mlx5e_set_features,
2625         .ndo_change_mtu          = mlx5e_change_mtu,
2626         .ndo_do_ioctl            = mlx5e_ioctl,
2627         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2628         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2629         .ndo_features_check      = mlx5e_features_check,
2630 #ifdef CONFIG_RFS_ACCEL
2631         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2632 #endif
2633         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2634         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2635         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
2636         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
2637         .ndo_get_vf_config       = mlx5e_get_vf_config,
2638         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2639         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2640 };
2641
2642 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2643 {
2644         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2645                 return -ENOTSUPP;
2646         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2647             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2648             !MLX5_CAP_ETH(mdev, csum_cap) ||
2649             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2650             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2651             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2652             MLX5_CAP_FLOWTABLE(mdev,
2653                                flow_table_properties_nic_receive.max_ft_level)
2654                                < 3) {
2655                 mlx5_core_warn(mdev,
2656                                "Not creating net device, some required device capabilities are missing\n");
2657                 return -ENOTSUPP;
2658         }
2659         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2660                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2661         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2662                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2663
2664         return 0;
2665 }
2666
2667 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2668 {
2669         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2670
2671         return bf_buf_size -
2672                sizeof(struct mlx5e_tx_wqe) +
2673                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2674 }
2675
2676 #ifdef CONFIG_MLX5_CORE_EN_DCB
2677 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2678 {
2679         int i;
2680
2681         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2682         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2683                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2684                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2685                 priv->params.ets.prio_tc[i] = i;
2686         }
2687
2688         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2689         priv->params.ets.prio_tc[0] = 1;
2690         priv->params.ets.prio_tc[1] = 0;
2691 }
2692 #endif
2693
2694 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2695                                    u32 *indirection_rqt, int len,
2696                                    int num_channels)
2697 {
2698         int node = mdev->priv.numa_node;
2699         int node_num_of_cores;
2700         int i;
2701
2702         if (node == -1)
2703                 node = first_online_node;
2704
2705         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2706
2707         if (node_num_of_cores)
2708                 num_channels = min_t(int, num_channels, node_num_of_cores);
2709
2710         for (i = 0; i < len; i++)
2711                 indirection_rqt[i] = i % num_channels;
2712 }
2713
2714 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2715 {
2716         return MLX5_CAP_GEN(mdev, striding_rq) &&
2717                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2718                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2719 }
2720
2721 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2722 {
2723         enum pcie_link_width width;
2724         enum pci_bus_speed speed;
2725         int err = 0;
2726
2727         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2728         if (err)
2729                 return err;
2730
2731         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2732                 return -EINVAL;
2733
2734         switch (speed) {
2735         case PCIE_SPEED_2_5GT:
2736                 *pci_bw = 2500 * width;
2737                 break;
2738         case PCIE_SPEED_5_0GT:
2739                 *pci_bw = 5000 * width;
2740                 break;
2741         case PCIE_SPEED_8_0GT:
2742                 *pci_bw = 8000 * width;
2743                 break;
2744         default:
2745                 return -EINVAL;
2746         }
2747
2748         return 0;
2749 }
2750
2751 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2752 {
2753         return (link_speed && pci_bw &&
2754                 (pci_bw < 40000) && (pci_bw < link_speed));
2755 }
2756
2757 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2758                                     struct net_device *netdev,
2759                                     int num_channels)
2760 {
2761         struct mlx5e_priv *priv = netdev_priv(netdev);
2762         u32 link_speed = 0;
2763         u32 pci_bw = 0;
2764
2765         priv->params.log_sq_size           =
2766                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2767         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2768                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2769                 MLX5_WQ_TYPE_LINKED_LIST;
2770
2771         /* set CQE compression */
2772         priv->params.rx_cqe_compress_admin = false;
2773         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
2774             MLX5_CAP_GEN(mdev, vport_group_manager)) {
2775                 mlx5e_get_max_linkspeed(mdev, &link_speed);
2776                 mlx5e_get_pci_bw(mdev, &pci_bw);
2777                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
2778                               link_speed, pci_bw);
2779                 priv->params.rx_cqe_compress_admin =
2780                         cqe_compress_heuristic(link_speed, pci_bw);
2781         }
2782
2783         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
2784
2785         switch (priv->params.rq_wq_type) {
2786         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2787                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2788                 priv->params.mpwqe_log_stride_sz =
2789                         priv->params.rx_cqe_compress ?
2790                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
2791                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
2792                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
2793                         priv->params.mpwqe_log_stride_sz;
2794                 priv->params.lro_en = true;
2795                 break;
2796         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2797                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2798         }
2799
2800         mlx5_core_info(mdev,
2801                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
2802                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
2803                        BIT(priv->params.log_rq_size),
2804                        BIT(priv->params.mpwqe_log_stride_sz),
2805                        priv->params.rx_cqe_compress_admin);
2806
2807         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2808                                             BIT(priv->params.log_rq_size));
2809         priv->params.rx_cq_moderation_usec =
2810                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2811         priv->params.rx_cq_moderation_pkts =
2812                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2813         priv->params.tx_cq_moderation_usec =
2814                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2815         priv->params.tx_cq_moderation_pkts =
2816                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2817         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2818         priv->params.num_tc                = 1;
2819         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2820
2821         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2822                             sizeof(priv->params.toeplitz_hash_key));
2823
2824         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2825                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2826
2827         priv->params.lro_wqe_sz            =
2828                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2829
2830         priv->mdev                         = mdev;
2831         priv->netdev                       = netdev;
2832         priv->params.num_channels          = num_channels;
2833
2834 #ifdef CONFIG_MLX5_CORE_EN_DCB
2835         mlx5e_ets_init(priv);
2836 #endif
2837
2838         mutex_init(&priv->state_lock);
2839
2840         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2841         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2842         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2843 }
2844
2845 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2846 {
2847         struct mlx5e_priv *priv = netdev_priv(netdev);
2848
2849         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2850         if (is_zero_ether_addr(netdev->dev_addr) &&
2851             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2852                 eth_hw_addr_random(netdev);
2853                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2854         }
2855 }
2856
2857 static void mlx5e_build_netdev(struct net_device *netdev)
2858 {
2859         struct mlx5e_priv *priv = netdev_priv(netdev);
2860         struct mlx5_core_dev *mdev = priv->mdev;
2861         bool fcs_supported;
2862         bool fcs_enabled;
2863
2864         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2865
2866         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2867                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2868 #ifdef CONFIG_MLX5_CORE_EN_DCB
2869                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2870 #endif
2871         } else {
2872                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2873         }
2874
2875         netdev->watchdog_timeo    = 15 * HZ;
2876
2877         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2878
2879         netdev->vlan_features    |= NETIF_F_SG;
2880         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2881         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2882         netdev->vlan_features    |= NETIF_F_GRO;
2883         netdev->vlan_features    |= NETIF_F_TSO;
2884         netdev->vlan_features    |= NETIF_F_TSO6;
2885         netdev->vlan_features    |= NETIF_F_RXCSUM;
2886         netdev->vlan_features    |= NETIF_F_RXHASH;
2887
2888         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2889                 netdev->vlan_features    |= NETIF_F_LRO;
2890
2891         netdev->hw_features       = netdev->vlan_features;
2892         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2893         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2894         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2895
2896         if (mlx5e_vxlan_allowed(mdev)) {
2897                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
2898                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
2899                                            NETIF_F_GSO_PARTIAL;
2900                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2901                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
2902                 netdev->hw_enc_features |= NETIF_F_TSO;
2903                 netdev->hw_enc_features |= NETIF_F_TSO6;
2904                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2905                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
2906                                            NETIF_F_GSO_PARTIAL;
2907                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
2908         }
2909
2910         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2911
2912         if (fcs_supported)
2913                 netdev->hw_features |= NETIF_F_RXALL;
2914
2915         netdev->features          = netdev->hw_features;
2916         if (!priv->params.lro_en)
2917                 netdev->features  &= ~NETIF_F_LRO;
2918
2919         if (fcs_enabled)
2920                 netdev->features  &= ~NETIF_F_RXALL;
2921
2922 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2923         if (FT_CAP(flow_modify_en) &&
2924             FT_CAP(modify_root) &&
2925             FT_CAP(identified_miss_table_mode) &&
2926             FT_CAP(flow_table_modify)) {
2927                 netdev->hw_features      |= NETIF_F_HW_TC;
2928 #ifdef CONFIG_RFS_ACCEL
2929                 netdev->hw_features      |= NETIF_F_NTUPLE;
2930 #endif
2931         }
2932
2933         netdev->features         |= NETIF_F_HIGHDMA;
2934
2935         netdev->priv_flags       |= IFF_UNICAST_FLT;
2936
2937         mlx5e_set_netdev_dev_addr(netdev);
2938 }
2939
2940 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2941                              struct mlx5_core_mkey *mkey)
2942 {
2943         struct mlx5_core_dev *mdev = priv->mdev;
2944         struct mlx5_create_mkey_mbox_in *in;
2945         int err;
2946
2947         in = mlx5_vzalloc(sizeof(*in));
2948         if (!in)
2949                 return -ENOMEM;
2950
2951         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2952                         MLX5_PERM_LOCAL_READ  |
2953                         MLX5_ACCESS_MODE_PA;
2954         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2955         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2956
2957         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2958                                     NULL);
2959
2960         kvfree(in);
2961
2962         return err;
2963 }
2964
2965 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2966 {
2967         struct mlx5_core_dev *mdev = priv->mdev;
2968         int err;
2969
2970         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2971         if (err) {
2972                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2973                 priv->q_counter = 0;
2974         }
2975 }
2976
2977 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2978 {
2979         if (!priv->q_counter)
2980                 return;
2981
2982         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2983 }
2984
2985 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2986 {
2987         struct mlx5_core_dev *mdev = priv->mdev;
2988         struct mlx5_create_mkey_mbox_in *in;
2989         struct mlx5_mkey_seg *mkc;
2990         int inlen = sizeof(*in);
2991         u64 npages =
2992                 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2993         int err;
2994
2995         in = mlx5_vzalloc(inlen);
2996         if (!in)
2997                 return -ENOMEM;
2998
2999         mkc = &in->seg;
3000         mkc->status = MLX5_MKEY_STATUS_FREE;
3001         mkc->flags = MLX5_PERM_UMR_EN |
3002                      MLX5_PERM_LOCAL_READ |
3003                      MLX5_PERM_LOCAL_WRITE |
3004                      MLX5_ACCESS_MODE_MTT;
3005
3006         mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3007         mkc->flags_pd = cpu_to_be32(priv->pdn);
3008         mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3009         mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
3010         mkc->log2_page_size = PAGE_SHIFT;
3011
3012         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3013                                     NULL, NULL);
3014
3015         kvfree(in);
3016
3017         return err;
3018 }
3019
3020 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
3021 {
3022         struct net_device *netdev;
3023         struct mlx5e_priv *priv;
3024         int nch = mlx5e_get_max_num_channels(mdev);
3025         int err;
3026
3027         if (mlx5e_check_required_hca_cap(mdev))
3028                 return NULL;
3029
3030         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3031                                     nch * MLX5E_MAX_NUM_TC,
3032                                     nch);
3033         if (!netdev) {
3034                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3035                 return NULL;
3036         }
3037
3038         mlx5e_build_netdev_priv(mdev, netdev, nch);
3039         mlx5e_build_netdev(netdev);
3040
3041         netif_carrier_off(netdev);
3042
3043         priv = netdev_priv(netdev);
3044
3045         priv->wq = create_singlethread_workqueue("mlx5e");
3046         if (!priv->wq)
3047                 goto err_free_netdev;
3048
3049         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
3050         if (err) {
3051                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
3052                 goto err_destroy_wq;
3053         }
3054
3055         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3056         if (err) {
3057                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
3058                 goto err_unmap_free_uar;
3059         }
3060
3061         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3062         if (err) {
3063                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3064                 goto err_dealloc_pd;
3065         }
3066
3067         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
3068         if (err) {
3069                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3070                 goto err_dealloc_transport_domain;
3071         }
3072
3073         err = mlx5e_create_umr_mkey(priv);
3074         if (err) {
3075                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3076                 goto err_destroy_mkey;
3077         }
3078
3079         err = mlx5e_create_tises(priv);
3080         if (err) {
3081                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
3082                 goto err_destroy_umr_mkey;
3083         }
3084
3085         err = mlx5e_open_drop_rq(priv);
3086         if (err) {
3087                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3088                 goto err_destroy_tises;
3089         }
3090
3091         err = mlx5e_create_rqts(priv);
3092         if (err) {
3093                 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
3094                 goto err_close_drop_rq;
3095         }
3096
3097         err = mlx5e_create_tirs(priv);
3098         if (err) {
3099                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
3100                 goto err_destroy_rqts;
3101         }
3102
3103         err = mlx5e_create_flow_steering(priv);
3104         if (err) {
3105                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3106                 goto err_destroy_tirs;
3107         }
3108
3109         mlx5e_create_q_counter(priv);
3110
3111         mlx5e_init_l2_addr(priv);
3112
3113         mlx5e_vxlan_init(priv);
3114
3115         err = mlx5e_tc_init(priv);
3116         if (err)
3117                 goto err_dealloc_q_counters;
3118
3119 #ifdef CONFIG_MLX5_CORE_EN_DCB
3120         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3121 #endif
3122
3123         err = register_netdev(netdev);
3124         if (err) {
3125                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3126                 goto err_tc_cleanup;
3127         }
3128
3129         if (mlx5e_vxlan_allowed(mdev)) {
3130                 rtnl_lock();
3131                 vxlan_get_rx_port(netdev);
3132                 rtnl_unlock();
3133         }
3134
3135         mlx5e_enable_async_events(priv);
3136         queue_work(priv->wq, &priv->set_rx_mode_work);
3137
3138         return priv;
3139
3140 err_tc_cleanup:
3141         mlx5e_tc_cleanup(priv);
3142
3143 err_dealloc_q_counters:
3144         mlx5e_destroy_q_counter(priv);
3145         mlx5e_destroy_flow_steering(priv);
3146
3147 err_destroy_tirs:
3148         mlx5e_destroy_tirs(priv);
3149
3150 err_destroy_rqts:
3151         mlx5e_destroy_rqts(priv);
3152
3153 err_close_drop_rq:
3154         mlx5e_close_drop_rq(priv);
3155
3156 err_destroy_tises:
3157         mlx5e_destroy_tises(priv);
3158
3159 err_destroy_umr_mkey:
3160         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3161
3162 err_destroy_mkey:
3163         mlx5_core_destroy_mkey(mdev, &priv->mkey);
3164
3165 err_dealloc_transport_domain:
3166         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3167
3168 err_dealloc_pd:
3169         mlx5_core_dealloc_pd(mdev, priv->pdn);
3170
3171 err_unmap_free_uar:
3172         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3173
3174 err_destroy_wq:
3175         destroy_workqueue(priv->wq);
3176
3177 err_free_netdev:
3178         free_netdev(netdev);
3179
3180         return NULL;
3181 }
3182
3183 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3184 {
3185         struct mlx5e_priv *priv = vpriv;
3186         struct net_device *netdev = priv->netdev;
3187
3188         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3189
3190         queue_work(priv->wq, &priv->set_rx_mode_work);
3191         mlx5e_disable_async_events(priv);
3192         flush_workqueue(priv->wq);
3193         if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3194                 netif_device_detach(netdev);
3195                 mlx5e_close(netdev);
3196         } else {
3197                 unregister_netdev(netdev);
3198         }
3199
3200         mlx5e_tc_cleanup(priv);
3201         mlx5e_vxlan_cleanup(priv);
3202         mlx5e_destroy_q_counter(priv);
3203         mlx5e_destroy_flow_steering(priv);
3204         mlx5e_destroy_tirs(priv);
3205         mlx5e_destroy_rqts(priv);
3206         mlx5e_close_drop_rq(priv);
3207         mlx5e_destroy_tises(priv);
3208         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3209         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
3210         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
3211         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3212         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3213         cancel_delayed_work_sync(&priv->update_stats_work);
3214         destroy_workqueue(priv->wq);
3215
3216         if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3217                 free_netdev(netdev);
3218 }
3219
3220 static void *mlx5e_get_netdev(void *vpriv)
3221 {
3222         struct mlx5e_priv *priv = vpriv;
3223
3224         return priv->netdev;
3225 }
3226
3227 static struct mlx5_interface mlx5e_interface = {
3228         .add       = mlx5e_create_netdev,
3229         .remove    = mlx5e_destroy_netdev,
3230         .event     = mlx5e_async_event,
3231         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3232         .get_dev   = mlx5e_get_netdev,
3233 };
3234
3235 void mlx5e_init(void)
3236 {
3237         mlx5_register_interface(&mlx5e_interface);
3238 }
3239
3240 void mlx5e_cleanup(void)
3241 {
3242         mlx5_unregister_interface(&mlx5e_interface);
3243 }