2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 #ifndef _MLXSW_SPECTRUM_H
38 #define _MLXSW_SPECTRUM_H
40 #include <linux/types.h>
41 #include <linux/netdevice.h>
42 #include <linux/bitops.h>
43 #include <linux/if_vlan.h>
44 #include <linux/list.h>
45 #include <linux/dcbnl.h>
46 #include <linux/in6.h>
47 #include <net/switchdev.h>
52 #define MLXSW_SP_VFID_BASE VLAN_N_VID
53 #define MLXSW_SP_VFID_MAX 6656 /* Bridged VLAN interfaces */
55 #define MLXSW_SP_RFID_BASE 15360
56 #define MLXSW_SP_RIF_MAX 800
58 #define MLXSW_SP_LAG_MAX 64
59 #define MLXSW_SP_PORT_PER_LAG_MAX 16
61 #define MLXSW_SP_MID_MAX 7000
63 #define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
65 #define MLXSW_SP_LPM_TREE_MIN 2 /* trees 0 and 1 are reserved */
66 #define MLXSW_SP_LPM_TREE_MAX 22
67 #define MLXSW_SP_LPM_TREE_COUNT (MLXSW_SP_LPM_TREE_MAX - MLXSW_SP_LPM_TREE_MIN)
69 #define MLXSW_SP_VIRTUAL_ROUTER_MAX 256
71 #define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
73 #define MLXSW_SP_BYTES_PER_CELL 96
75 #define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
76 #define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL)
78 /* Maximum delay buffer needed in case of PAUSE frames, in cells.
79 * Assumes 100m cable and maximum MTU.
81 #define MLXSW_SP_PAUSE_DELAY 612
83 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
85 static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay)
87 delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE));
88 return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu);
93 struct mlxsw_sp_upper {
94 struct net_device *dev;
95 unsigned int ref_count;
99 void (*leave)(struct mlxsw_sp_port *mlxsw_sp_vport);
100 struct list_head list;
101 unsigned int ref_count;
102 struct net_device *dev;
103 struct mlxsw_sp_rif *r;
107 struct mlxsw_sp_rif {
108 struct net_device *dev;
109 unsigned int ref_count;
110 struct mlxsw_sp_fid *f;
111 unsigned char addr[ETH_ALEN];
116 struct mlxsw_sp_mid {
117 struct list_head list;
118 unsigned char addr[ETH_ALEN];
121 unsigned int ref_count;
124 static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
126 return MLXSW_SP_VFID_BASE + vfid;
129 static inline u16 mlxsw_sp_fid_to_vfid(u16 fid)
131 return fid - MLXSW_SP_VFID_BASE;
134 static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
136 return fid >= MLXSW_SP_VFID_BASE && fid < MLXSW_SP_RFID_BASE;
139 static inline bool mlxsw_sp_fid_is_rfid(u16 fid)
141 return fid >= MLXSW_SP_RFID_BASE;
144 static inline u16 mlxsw_sp_rif_sp_to_fid(u16 rif)
146 return MLXSW_SP_RFID_BASE + rif;
149 struct mlxsw_sp_sb_pr {
150 enum mlxsw_reg_sbpr_mode mode;
154 struct mlxsw_cp_sb_occ {
159 struct mlxsw_sp_sb_cm {
163 struct mlxsw_cp_sb_occ occ;
166 struct mlxsw_sp_sb_pm {
169 struct mlxsw_cp_sb_occ occ;
172 #define MLXSW_SP_SB_POOL_COUNT 4
173 #define MLXSW_SP_SB_TC_COUNT 8
176 struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT];
178 struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT];
179 struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT];
180 } ports[MLXSW_PORT_MAX_PORTS];
183 #define MLXSW_SP_PREFIX_COUNT (sizeof(struct in6_addr) * BITS_PER_BYTE)
185 struct mlxsw_sp_prefix_usage {
186 DECLARE_BITMAP(b, MLXSW_SP_PREFIX_COUNT);
189 enum mlxsw_sp_l3proto {
190 MLXSW_SP_L3_PROTO_IPV4,
191 MLXSW_SP_L3_PROTO_IPV6,
194 struct mlxsw_sp_lpm_tree {
196 unsigned int ref_count;
197 enum mlxsw_sp_l3proto proto;
198 struct mlxsw_sp_prefix_usage prefix_usage;
204 u16 id; /* virtual router ID */
206 enum mlxsw_sp_l3proto proto;
207 u32 tb_id; /* kernel fib table id */
208 struct mlxsw_sp_lpm_tree *lpm_tree;
209 struct mlxsw_sp_fib *fib;
212 struct mlxsw_sp_router {
213 struct mlxsw_sp_lpm_tree lpm_trees[MLXSW_SP_LPM_TREE_COUNT];
214 struct mlxsw_sp_vr vrs[MLXSW_SP_VIRTUAL_ROUTER_MAX];
219 struct list_head list;
220 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_MAX);
223 struct list_head list;
224 DECLARE_BITMAP(mapped, MLXSW_SP_MID_MAX);
226 struct list_head fids; /* VLAN-aware bridge FIDs */
227 struct mlxsw_sp_rif *rifs[MLXSW_SP_RIF_MAX];
228 struct mlxsw_sp_port **ports;
229 struct mlxsw_core *core;
230 const struct mlxsw_bus_info *bus_info;
231 unsigned char base_mac[ETH_ALEN];
233 struct delayed_work dw;
234 #define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
235 unsigned int interval; /* ms */
237 #define MLXSW_SP_MIN_AGEING_TIME 10
238 #define MLXSW_SP_MAX_AGEING_TIME 1000000
239 #define MLXSW_SP_DEFAULT_AGEING_TIME 300
241 struct mlxsw_sp_upper master_bridge;
242 struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];
243 u8 port_to_module[MLXSW_PORT_MAX_PORTS];
244 struct mlxsw_sp_sb sb;
245 struct mlxsw_sp_router router;
248 static inline struct mlxsw_sp_upper *
249 mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
251 return &mlxsw_sp->lags[lag_id];
254 struct mlxsw_sp_port_pcpu_stats {
259 struct u64_stats_sync syncp;
263 struct mlxsw_sp_port {
264 struct mlxsw_core_port core_port; /* must be first */
265 struct net_device *dev;
266 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
267 struct mlxsw_sp *mlxsw_sp;
279 struct list_head list;
280 struct mlxsw_sp_fid *f;
288 struct ieee_ets *ets;
289 struct ieee_maxrate *maxrate;
290 struct ieee_pfc *pfc;
297 /* 802.1Q bridge VLANs */
298 unsigned long *active_vlans;
299 unsigned long *untagged_vlans;
300 /* VLAN interfaces */
301 struct list_head vports_list;
304 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev);
305 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port);
308 mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port)
310 return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause;
313 static inline struct mlxsw_sp_port *
314 mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
316 struct mlxsw_sp_port *mlxsw_sp_port;
319 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
321 mlxsw_sp_port = mlxsw_sp->ports[local_port];
322 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
326 mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
328 return mlxsw_sp_vport->vport.vid;
332 mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
334 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_port);
339 static inline void mlxsw_sp_vport_fid_set(struct mlxsw_sp_port *mlxsw_sp_vport,
340 struct mlxsw_sp_fid *f)
342 mlxsw_sp_vport->vport.f = f;
345 static inline struct mlxsw_sp_fid *
346 mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
348 return mlxsw_sp_vport->vport.f;
351 static inline struct net_device *
352 mlxsw_sp_vport_br_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
354 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
356 return f ? f->dev : NULL;
359 static inline struct mlxsw_sp_port *
360 mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
362 struct mlxsw_sp_port *mlxsw_sp_vport;
364 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
366 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
367 return mlxsw_sp_vport;
373 static inline struct mlxsw_sp_port *
374 mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
377 struct mlxsw_sp_port *mlxsw_sp_vport;
379 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
381 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
383 if (f && f->fid == fid)
384 return mlxsw_sp_vport;
390 static inline struct mlxsw_sp_rif *
391 mlxsw_sp_rif_find_by_dev(const struct mlxsw_sp *mlxsw_sp,
392 const struct net_device *dev)
396 for (i = 0; i < MLXSW_SP_RIF_MAX; i++)
397 if (mlxsw_sp->rifs[i] && mlxsw_sp->rifs[i]->dev == dev)
398 return mlxsw_sp->rifs[i];
403 enum mlxsw_sp_flood_table {
404 MLXSW_SP_FLOOD_TABLE_UC,
405 MLXSW_SP_FLOOD_TABLE_BM,
408 int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
409 void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp);
410 int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
411 int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
412 unsigned int sb_index, u16 pool_index,
413 struct devlink_sb_pool_info *pool_info);
414 int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
415 unsigned int sb_index, u16 pool_index, u32 size,
416 enum devlink_sb_threshold_type threshold_type);
417 int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
418 unsigned int sb_index, u16 pool_index,
420 int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
421 unsigned int sb_index, u16 pool_index,
423 int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
424 unsigned int sb_index, u16 tc_index,
425 enum devlink_sb_pool_type pool_type,
426 u16 *p_pool_index, u32 *p_threshold);
427 int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
428 unsigned int sb_index, u16 tc_index,
429 enum devlink_sb_pool_type pool_type,
430 u16 pool_index, u32 threshold);
431 int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
432 unsigned int sb_index);
433 int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
434 unsigned int sb_index);
435 int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
436 unsigned int sb_index, u16 pool_index,
437 u32 *p_cur, u32 *p_max);
438 int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
439 unsigned int sb_index, u16 tc_index,
440 enum devlink_sb_pool_type pool_type,
441 u32 *p_cur, u32 *p_max);
443 int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
444 void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
445 int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
446 void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
447 void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
448 int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
449 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
451 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
452 u16 vid_end, bool is_member, bool untagged);
453 int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
455 int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
457 void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port);
458 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid);
459 int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid);
460 int mlxsw_sp_rif_fdb_op(struct mlxsw_sp *mlxsw_sp, const char *mac, u16 fid,
462 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
463 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
464 bool dwrr, u8 dwrr_weight);
465 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
466 u8 switch_prio, u8 tclass);
467 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
468 u8 *prio_tc, bool pause_en,
469 struct ieee_pfc *my_pfc);
470 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
471 enum mlxsw_reg_qeec_hr hr, u8 index,
472 u8 next_index, u32 maxrate);
474 #ifdef CONFIG_MLXSW_SPECTRUM_DCB
476 int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port);
477 void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port);
481 static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
486 static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
491 int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp);
492 void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp);
493 int mlxsw_sp_router_fib4_add(struct mlxsw_sp_port *mlxsw_sp_port,
494 const struct switchdev_obj_ipv4_fib *fib4,
495 struct switchdev_trans *trans);
496 int mlxsw_sp_router_fib4_del(struct mlxsw_sp_port *mlxsw_sp_port,
497 const struct switchdev_obj_ipv4_fib *fib4);