drivers/net/ethernet/mellanox/mlxsw/switchx2.c

   1 /*
   2  * drivers/net/ethernet/mellanox/mlxsw/switchx2.c
   3  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
   5  * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
   6  * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. Neither the names of the copyright holders nor the names of its
  17  *    contributors may be used to endorse or promote products derived from
  18  *    this software without specific prior written permission.
  19  *
  20  * Alternatively, this software may be distributed under the terms of the
  21  * GNU General Public License ("GPL") version 2 as published by the Free
  22  * Software Foundation.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  27  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  28  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  32  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  34  * POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/types.h>
  40 #include <linux/netdevice.h>
  41 #include <linux/etherdevice.h>
  42 #include <linux/slab.h>
  43 #include <linux/device.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/if_vlan.h>
  46 #include <net/switchdev.h>
  47 #include <generated/utsrelease.h>
  48
  49 #include "core.h"
  50 #include "reg.h"
  51 #include "port.h"
  52 #include "trap.h"
  53 #include "txheader.h"
  54
  55 static const char mlxsw_sx_driver_name[] = "mlxsw_switchx2";
  56 static const char mlxsw_sx_driver_version[] = "1.0";
  57
  58 struct mlxsw_sx_port;
  59
  60 struct mlxsw_sx {
  61         struct mlxsw_sx_port **ports;
  62         struct mlxsw_core *core;
  63         const struct mlxsw_bus_info *bus_info;
  64         u8 hw_id[ETH_ALEN];
  65 };
  66
  67 struct mlxsw_sx_port_pcpu_stats {
  68         u64                     rx_packets;
  69         u64                     rx_bytes;
  70         u64                     tx_packets;
  71         u64                     tx_bytes;
  72         struct u64_stats_sync   syncp;
  73         u32                     tx_dropped;
  74 };
  75
  76 struct mlxsw_sx_port {
  77         struct mlxsw_core_port core_port; /* must be first */
  78         struct net_device *dev;
  79         struct mlxsw_sx_port_pcpu_stats __percpu *pcpu_stats;
  80         struct mlxsw_sx *mlxsw_sx;
  81         u8 local_port;
  82 };
  83
  84 /* tx_hdr_version
  85  * Tx header version.
  86  * Must be set to 0.
  87  */
  88 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
  89
  90 /* tx_hdr_ctl
  91  * Packet control type.
  92  * 0 - Ethernet control (e.g. EMADs, LACP)
  93  * 1 - Ethernet data
  94  */
  95 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
  96
  97 /* tx_hdr_proto
  98  * Packet protocol type. Must be set to 1 (Ethernet).
  99  */
 100 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
 101
 102 /* tx_hdr_etclass
 103  * Egress TClass to be used on the egress device on the egress port.
 104  * The MSB is specified in the 'ctclass3' field.
 105  * Range is 0-15, where 15 is the highest priority.
 106  */
 107 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 18, 3);
 108
 109 /* tx_hdr_swid
 110  * Switch partition ID.
 111  */
 112 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
 113
 114 /* tx_hdr_port_mid
 115  * Destination local port for unicast packets.
 116  * Destination multicast ID for multicast packets.
 117  *
 118  * Control packets are directed to a specific egress port, while data
 119  * packets are transmitted through the CPU port (0) into the switch partition,
 120  * where forwarding rules are applied.
 121  */
 122 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
 123
 124 /* tx_hdr_ctclass3
 125  * See field 'etclass'.
 126  */
 127 MLXSW_ITEM32(tx, hdr, ctclass3, 0x04, 14, 1);
 128
 129 /* tx_hdr_rdq
 130  * RDQ for control packets sent to remote CPU.
 131  * Must be set to 0x1F for EMADs, otherwise 0.
 132  */
 133 MLXSW_ITEM32(tx, hdr, rdq, 0x04, 9, 5);
 134
 135 /* tx_hdr_cpu_sig
 136  * Signature control for packets going to CPU. Must be set to 0.
 137  */
 138 MLXSW_ITEM32(tx, hdr, cpu_sig, 0x04, 0, 9);
 139
 140 /* tx_hdr_sig
 141  * Stacking protocl signature. Must be set to 0xE0E0.
 142  */
 143 MLXSW_ITEM32(tx, hdr, sig, 0x0C, 16, 16);
 144
 145 /* tx_hdr_stclass
 146  * Stacking TClass.
 147  */
 148 MLXSW_ITEM32(tx, hdr, stclass, 0x0C, 13, 3);
 149
 150 /* tx_hdr_emad
 151  * EMAD bit. Must be set for EMADs.
 152  */
 153 MLXSW_ITEM32(tx, hdr, emad, 0x0C, 5, 1);
 154
 155 /* tx_hdr_type
 156  * 0 - Data packets
 157  * 6 - Control packets
 158  */
 159 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
 160
 161 static void mlxsw_sx_txhdr_construct(struct sk_buff *skb,
 162                                      const struct mlxsw_tx_info *tx_info)
 163 {
 164         char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
 165         bool is_emad = tx_info->is_emad;
 166
 167         memset(txhdr, 0, MLXSW_TXHDR_LEN);
 168
 169         /* We currently set default values for the egress tclass (QoS). */
 170         mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_0);
 171         mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
 172         mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
 173         mlxsw_tx_hdr_etclass_set(txhdr, is_emad ? MLXSW_TXHDR_ETCLASS_6 :
 174                                                   MLXSW_TXHDR_ETCLASS_5);
 175         mlxsw_tx_hdr_swid_set(txhdr, 0);
 176         mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
 177         mlxsw_tx_hdr_ctclass3_set(txhdr, MLXSW_TXHDR_CTCLASS3);
 178         mlxsw_tx_hdr_rdq_set(txhdr, is_emad ? MLXSW_TXHDR_RDQ_EMAD :
 179                                               MLXSW_TXHDR_RDQ_OTHER);
 180         mlxsw_tx_hdr_cpu_sig_set(txhdr, MLXSW_TXHDR_CPU_SIG);
 181         mlxsw_tx_hdr_sig_set(txhdr, MLXSW_TXHDR_SIG);
 182         mlxsw_tx_hdr_stclass_set(txhdr, MLXSW_TXHDR_STCLASS_NONE);
 183         mlxsw_tx_hdr_emad_set(txhdr, is_emad ? MLXSW_TXHDR_EMAD :
 184                                                MLXSW_TXHDR_NOT_EMAD);
 185         mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
 186 }
 187
 188 static int mlxsw_sx_port_admin_status_set(struct mlxsw_sx_port *mlxsw_sx_port,
 189                                           bool is_up)
 190 {
 191         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 192         char paos_pl[MLXSW_REG_PAOS_LEN];
 193
 194         mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port,
 195                             is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
 196                             MLXSW_PORT_ADMIN_STATUS_DOWN);
 197         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
 198 }
 199
 200 static int mlxsw_sx_port_oper_status_get(struct mlxsw_sx_port *mlxsw_sx_port,
 201                                          bool *p_is_up)
 202 {
 203         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 204         char paos_pl[MLXSW_REG_PAOS_LEN];
 205         u8 oper_status;
 206         int err;
 207
 208         mlxsw_reg_paos_pack(paos_pl, mlxsw_sx_port->local_port, 0);
 209         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(paos), paos_pl);
 210         if (err)
 211                 return err;
 212         oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
 213         *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
 214         return 0;
 215 }
 216
 217 static int mlxsw_sx_port_mtu_set(struct mlxsw_sx_port *mlxsw_sx_port, u16 mtu)
 218 {
 219         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 220         char pmtu_pl[MLXSW_REG_PMTU_LEN];
 221         int max_mtu;
 222         int err;
 223
 224         mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
 225         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, 0);
 226         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
 227         if (err)
 228                 return err;
 229         max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
 230
 231         if (mtu > max_mtu)
 232                 return -EINVAL;
 233
 234         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sx_port->local_port, mtu);
 235         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pmtu), pmtu_pl);
 236 }
 237
 238 static int mlxsw_sx_port_swid_set(struct mlxsw_sx_port *mlxsw_sx_port, u8 swid)
 239 {
 240         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 241         char pspa_pl[MLXSW_REG_PSPA_LEN];
 242
 243         mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sx_port->local_port);
 244         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(pspa), pspa_pl);
 245 }
 246
 247 static int
 248 mlxsw_sx_port_system_port_mapping_set(struct mlxsw_sx_port *mlxsw_sx_port)
 249 {
 250         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 251         char sspr_pl[MLXSW_REG_SSPR_LEN];
 252
 253         mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sx_port->local_port);
 254         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sspr), sspr_pl);
 255 }
 256
 257 static int mlxsw_sx_port_module_check(struct mlxsw_sx_port *mlxsw_sx_port,
 258                                       bool *p_usable)
 259 {
 260         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 261         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 262         int err;
 263
 264         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sx_port->local_port);
 265         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(pmlp), pmlp_pl);
 266         if (err)
 267                 return err;
 268         *p_usable = mlxsw_reg_pmlp_width_get(pmlp_pl) ? true : false;
 269         return 0;
 270 }
 271
 272 static int mlxsw_sx_port_open(struct net_device *dev)
 273 {
 274         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 275         int err;
 276
 277         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
 278         if (err)
 279                 return err;
 280         netif_start_queue(dev);
 281         return 0;
 282 }
 283
 284 static int mlxsw_sx_port_stop(struct net_device *dev)
 285 {
 286         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 287
 288         netif_stop_queue(dev);
 289         return mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
 290 }
 291
 292 static netdev_tx_t mlxsw_sx_port_xmit(struct sk_buff *skb,
 293                                       struct net_device *dev)
 294 {
 295         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 296         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 297         struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
 298         const struct mlxsw_tx_info tx_info = {
 299                 .local_port = mlxsw_sx_port->local_port,
 300                 .is_emad = false,
 301         };
 302         u64 len;
 303         int err;
 304
 305         if (mlxsw_core_skb_transmit_busy(mlxsw_sx->core, &tx_info))
 306                 return NETDEV_TX_BUSY;
 307
 308         if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
 309                 struct sk_buff *skb_orig = skb;
 310
 311                 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
 312                 if (!skb) {
 313                         this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
 314                         dev_kfree_skb_any(skb_orig);
 315                         return NETDEV_TX_OK;
 316                 }
 317         }
 318         mlxsw_sx_txhdr_construct(skb, &tx_info);
 319         /* TX header is consumed by HW on the way so we shouldn't count its
 320          * bytes as being sent.
 321          */
 322         len = skb->len - MLXSW_TXHDR_LEN;
 323         /* Due to a race we might fail here because of a full queue. In that
 324          * unlikely case we simply drop the packet.
 325          */
 326         err = mlxsw_core_skb_transmit(mlxsw_sx->core, skb, &tx_info);
 327
 328         if (!err) {
 329                 pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
 330                 u64_stats_update_begin(&pcpu_stats->syncp);
 331                 pcpu_stats->tx_packets++;
 332                 pcpu_stats->tx_bytes += len;
 333                 u64_stats_update_end(&pcpu_stats->syncp);
 334         } else {
 335                 this_cpu_inc(mlxsw_sx_port->pcpu_stats->tx_dropped);
 336                 dev_kfree_skb_any(skb);
 337         }
 338         return NETDEV_TX_OK;
 339 }
 340
 341 static int mlxsw_sx_port_change_mtu(struct net_device *dev, int mtu)
 342 {
 343         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 344         int err;
 345
 346         err = mlxsw_sx_port_mtu_set(mlxsw_sx_port, mtu);
 347         if (err)
 348                 return err;
 349         dev->mtu = mtu;
 350         return 0;
 351 }
 352
 353 static struct rtnl_link_stats64 *
 354 mlxsw_sx_port_get_stats64(struct net_device *dev,
 355                           struct rtnl_link_stats64 *stats)
 356 {
 357         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 358         struct mlxsw_sx_port_pcpu_stats *p;
 359         u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
 360         u32 tx_dropped = 0;
 361         unsigned int start;
 362         int i;
 363
 364         for_each_possible_cpu(i) {
 365                 p = per_cpu_ptr(mlxsw_sx_port->pcpu_stats, i);
 366                 do {
 367                         start = u64_stats_fetch_begin_irq(&p->syncp);
 368                         rx_packets      = p->rx_packets;
 369                         rx_bytes        = p->rx_bytes;
 370                         tx_packets      = p->tx_packets;
 371                         tx_bytes        = p->tx_bytes;
 372                 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
 373
 374                 stats->rx_packets       += rx_packets;
 375                 stats->rx_bytes         += rx_bytes;
 376                 stats->tx_packets       += tx_packets;
 377                 stats->tx_bytes         += tx_bytes;
 378                 /* tx_dropped is u32, updated without syncp protection. */
 379                 tx_dropped      += p->tx_dropped;
 380         }
 381         stats->tx_dropped       = tx_dropped;
 382         return stats;
 383 }
 384
 385 static const struct net_device_ops mlxsw_sx_port_netdev_ops = {
 386         .ndo_open               = mlxsw_sx_port_open,
 387         .ndo_stop               = mlxsw_sx_port_stop,
 388         .ndo_start_xmit         = mlxsw_sx_port_xmit,
 389         .ndo_change_mtu         = mlxsw_sx_port_change_mtu,
 390         .ndo_get_stats64        = mlxsw_sx_port_get_stats64,
 391 };
 392
 393 static void mlxsw_sx_port_get_drvinfo(struct net_device *dev,
 394                                       struct ethtool_drvinfo *drvinfo)
 395 {
 396         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 397         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 398
 399         strlcpy(drvinfo->driver, mlxsw_sx_driver_name, sizeof(drvinfo->driver));
 400         strlcpy(drvinfo->version, mlxsw_sx_driver_version,
 401                 sizeof(drvinfo->version));
 402         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
 403                  "%d.%d.%d",
 404                  mlxsw_sx->bus_info->fw_rev.major,
 405                  mlxsw_sx->bus_info->fw_rev.minor,
 406                  mlxsw_sx->bus_info->fw_rev.subminor);
 407         strlcpy(drvinfo->bus_info, mlxsw_sx->bus_info->device_name,
 408                 sizeof(drvinfo->bus_info));
 409 }
 410
 411 struct mlxsw_sx_port_hw_stats {
 412         char str[ETH_GSTRING_LEN];
 413         u64 (*getter)(char *payload);
 414 };
 415
 416 static const struct mlxsw_sx_port_hw_stats mlxsw_sx_port_hw_stats[] = {
 417         {
 418                 .str = "a_frames_transmitted_ok",
 419                 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
 420         },
 421         {
 422                 .str = "a_frames_received_ok",
 423                 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
 424         },
 425         {
 426                 .str = "a_frame_check_sequence_errors",
 427                 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
 428         },
 429         {
 430                 .str = "a_alignment_errors",
 431                 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
 432         },
 433         {
 434                 .str = "a_octets_transmitted_ok",
 435                 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
 436         },
 437         {
 438                 .str = "a_octets_received_ok",
 439                 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
 440         },
 441         {
 442                 .str = "a_multicast_frames_xmitted_ok",
 443                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
 444         },
 445         {
 446                 .str = "a_broadcast_frames_xmitted_ok",
 447                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
 448         },
 449         {
 450                 .str = "a_multicast_frames_received_ok",
 451                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
 452         },
 453         {
 454                 .str = "a_broadcast_frames_received_ok",
 455                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
 456         },
 457         {
 458                 .str = "a_in_range_length_errors",
 459                 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
 460         },
 461         {
 462                 .str = "a_out_of_range_length_field",
 463                 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
 464         },
 465         {
 466                 .str = "a_frame_too_long_errors",
 467                 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
 468         },
 469         {
 470                 .str = "a_symbol_error_during_carrier",
 471                 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
 472         },
 473         {
 474                 .str = "a_mac_control_frames_transmitted",
 475                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
 476         },
 477         {
 478                 .str = "a_mac_control_frames_received",
 479                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
 480         },
 481         {
 482                 .str = "a_unsupported_opcodes_received",
 483                 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
 484         },
 485         {
 486                 .str = "a_pause_mac_ctrl_frames_received",
 487                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
 488         },
 489         {
 490                 .str = "a_pause_mac_ctrl_frames_xmitted",
 491                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
 492         },
 493 };
 494
 495 #define MLXSW_SX_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sx_port_hw_stats)
 496
 497 static void mlxsw_sx_port_get_strings(struct net_device *dev,
 498                                       u32 stringset, u8 *data)
 499 {
 500         u8 *p = data;
 501         int i;
 502
 503         switch (stringset) {
 504         case ETH_SS_STATS:
 505                 for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++) {
 506                         memcpy(p, mlxsw_sx_port_hw_stats[i].str,
 507                                ETH_GSTRING_LEN);
 508                         p += ETH_GSTRING_LEN;
 509                 }
 510                 break;
 511         }
 512 }
 513
 514 static void mlxsw_sx_port_get_stats(struct net_device *dev,
 515                                     struct ethtool_stats *stats, u64 *data)
 516 {
 517         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 518         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 519         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
 520         int i;
 521         int err;
 522
 523         mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sx_port->local_port,
 524                              MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
 525         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppcnt), ppcnt_pl);
 526         for (i = 0; i < MLXSW_SX_PORT_HW_STATS_LEN; i++)
 527                 data[i] = !err ? mlxsw_sx_port_hw_stats[i].getter(ppcnt_pl) : 0;
 528 }
 529
 530 static int mlxsw_sx_port_get_sset_count(struct net_device *dev, int sset)
 531 {
 532         switch (sset) {
 533         case ETH_SS_STATS:
 534                 return MLXSW_SX_PORT_HW_STATS_LEN;
 535         default:
 536                 return -EOPNOTSUPP;
 537         }
 538 }
 539
 540 struct mlxsw_sx_port_link_mode {
 541         u32 mask;
 542         u32 supported;
 543         u32 advertised;
 544         u32 speed;
 545 };
 546
 547 static const struct mlxsw_sx_port_link_mode mlxsw_sx_port_link_mode[] = {
 548         {
 549                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
 550                 .supported      = SUPPORTED_100baseT_Full,
 551                 .advertised     = ADVERTISED_100baseT_Full,
 552                 .speed          = 100,
 553         },
 554         {
 555                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
 556                 .speed          = 100,
 557         },
 558         {
 559                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
 560                                   MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
 561                 .supported      = SUPPORTED_1000baseKX_Full,
 562                 .advertised     = ADVERTISED_1000baseKX_Full,
 563                 .speed          = 1000,
 564         },
 565         {
 566                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
 567                 .supported      = SUPPORTED_10000baseT_Full,
 568                 .advertised     = ADVERTISED_10000baseT_Full,
 569                 .speed          = 10000,
 570         },
 571         {
 572                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
 573                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
 574                 .supported      = SUPPORTED_10000baseKX4_Full,
 575                 .advertised     = ADVERTISED_10000baseKX4_Full,
 576                 .speed          = 10000,
 577         },
 578         {
 579                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
 580                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
 581                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
 582                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
 583                 .supported      = SUPPORTED_10000baseKR_Full,
 584                 .advertised     = ADVERTISED_10000baseKR_Full,
 585                 .speed          = 10000,
 586         },
 587         {
 588                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
 589                 .supported      = SUPPORTED_20000baseKR2_Full,
 590                 .advertised     = ADVERTISED_20000baseKR2_Full,
 591                 .speed          = 20000,
 592         },
 593         {
 594                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
 595                 .supported      = SUPPORTED_40000baseCR4_Full,
 596                 .advertised     = ADVERTISED_40000baseCR4_Full,
 597                 .speed          = 40000,
 598         },
 599         {
 600                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
 601                 .supported      = SUPPORTED_40000baseKR4_Full,
 602                 .advertised     = ADVERTISED_40000baseKR4_Full,
 603                 .speed          = 40000,
 604         },
 605         {
 606                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
 607                 .supported      = SUPPORTED_40000baseSR4_Full,
 608                 .advertised     = ADVERTISED_40000baseSR4_Full,
 609                 .speed          = 40000,
 610         },
 611         {
 612                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
 613                 .supported      = SUPPORTED_40000baseLR4_Full,
 614                 .advertised     = ADVERTISED_40000baseLR4_Full,
 615                 .speed          = 40000,
 616         },
 617         {
 618                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
 619                                   MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
 620                                   MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
 621                 .speed          = 25000,
 622         },
 623         {
 624                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
 625                                   MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
 626                                   MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
 627                 .speed          = 50000,
 628         },
 629         {
 630                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
 631                 .supported      = SUPPORTED_56000baseKR4_Full,
 632                 .advertised     = ADVERTISED_56000baseKR4_Full,
 633                 .speed          = 56000,
 634         },
 635         {
 636                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
 637                                   MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
 638                                   MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
 639                                   MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
 640                 .speed          = 100000,
 641         },
 642 };
 643
 644 #define MLXSW_SX_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sx_port_link_mode)
 645
 646 static u32 mlxsw_sx_from_ptys_supported_port(u32 ptys_eth_proto)
 647 {
 648         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
 649                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
 650                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
 651                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
 652                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
 653                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
 654                 return SUPPORTED_FIBRE;
 655
 656         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
 657                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
 658                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
 659                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
 660                               MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
 661                 return SUPPORTED_Backplane;
 662         return 0;
 663 }
 664
 665 static u32 mlxsw_sx_from_ptys_supported_link(u32 ptys_eth_proto)
 666 {
 667         u32 modes = 0;
 668         int i;
 669
 670         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 671                 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
 672                         modes |= mlxsw_sx_port_link_mode[i].supported;
 673         }
 674         return modes;
 675 }
 676
 677 static u32 mlxsw_sx_from_ptys_advert_link(u32 ptys_eth_proto)
 678 {
 679         u32 modes = 0;
 680         int i;
 681
 682         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 683                 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask)
 684                         modes |= mlxsw_sx_port_link_mode[i].advertised;
 685         }
 686         return modes;
 687 }
 688
 689 static void mlxsw_sx_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
 690                                             struct ethtool_cmd *cmd)
 691 {
 692         u32 speed = SPEED_UNKNOWN;
 693         u8 duplex = DUPLEX_UNKNOWN;
 694         int i;
 695
 696         if (!carrier_ok)
 697                 goto out;
 698
 699         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 700                 if (ptys_eth_proto & mlxsw_sx_port_link_mode[i].mask) {
 701                         speed = mlxsw_sx_port_link_mode[i].speed;
 702                         duplex = DUPLEX_FULL;
 703                         break;
 704                 }
 705         }
 706 out:
 707         ethtool_cmd_speed_set(cmd, speed);
 708         cmd->duplex = duplex;
 709 }
 710
 711 static u8 mlxsw_sx_port_connector_port(u32 ptys_eth_proto)
 712 {
 713         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
 714                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
 715                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
 716                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
 717                 return PORT_FIBRE;
 718
 719         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
 720                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
 721                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
 722                 return PORT_DA;
 723
 724         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
 725                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
 726                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
 727                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
 728                 return PORT_NONE;
 729
 730         return PORT_OTHER;
 731 }
 732
 733 static int mlxsw_sx_port_get_settings(struct net_device *dev,
 734                                       struct ethtool_cmd *cmd)
 735 {
 736         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 737         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 738         char ptys_pl[MLXSW_REG_PTYS_LEN];
 739         u32 eth_proto_cap;
 740         u32 eth_proto_admin;
 741         u32 eth_proto_oper;
 742         int err;
 743
 744         mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
 745         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 746         if (err) {
 747                 netdev_err(dev, "Failed to get proto");
 748                 return err;
 749         }
 750         mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
 751                               &eth_proto_admin, &eth_proto_oper);
 752
 753         cmd->supported = mlxsw_sx_from_ptys_supported_port(eth_proto_cap) |
 754                          mlxsw_sx_from_ptys_supported_link(eth_proto_cap) |
 755                          SUPPORTED_Pause | SUPPORTED_Asym_Pause;
 756         cmd->advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_admin);
 757         mlxsw_sx_from_ptys_speed_duplex(netif_carrier_ok(dev),
 758                                         eth_proto_oper, cmd);
 759
 760         eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
 761         cmd->port = mlxsw_sx_port_connector_port(eth_proto_oper);
 762         cmd->lp_advertising = mlxsw_sx_from_ptys_advert_link(eth_proto_oper);
 763
 764         cmd->transceiver = XCVR_INTERNAL;
 765         return 0;
 766 }
 767
 768 static u32 mlxsw_sx_to_ptys_advert_link(u32 advertising)
 769 {
 770         u32 ptys_proto = 0;
 771         int i;
 772
 773         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 774                 if (advertising & mlxsw_sx_port_link_mode[i].advertised)
 775                         ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
 776         }
 777         return ptys_proto;
 778 }
 779
 780 static u32 mlxsw_sx_to_ptys_speed(u32 speed)
 781 {
 782         u32 ptys_proto = 0;
 783         int i;
 784
 785         for (i = 0; i < MLXSW_SX_PORT_LINK_MODE_LEN; i++) {
 786                 if (speed == mlxsw_sx_port_link_mode[i].speed)
 787                         ptys_proto |= mlxsw_sx_port_link_mode[i].mask;
 788         }
 789         return ptys_proto;
 790 }
 791
 792 static int mlxsw_sx_port_set_settings(struct net_device *dev,
 793                                       struct ethtool_cmd *cmd)
 794 {
 795         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 796         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 797         char ptys_pl[MLXSW_REG_PTYS_LEN];
 798         u32 speed;
 799         u32 eth_proto_new;
 800         u32 eth_proto_cap;
 801         u32 eth_proto_admin;
 802         bool is_up;
 803         int err;
 804
 805         speed = ethtool_cmd_speed(cmd);
 806
 807         eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
 808                 mlxsw_sx_to_ptys_advert_link(cmd->advertising) :
 809                 mlxsw_sx_to_ptys_speed(speed);
 810
 811         mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, 0);
 812         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 813         if (err) {
 814                 netdev_err(dev, "Failed to get proto");
 815                 return err;
 816         }
 817         mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
 818
 819         eth_proto_new = eth_proto_new & eth_proto_cap;
 820         if (!eth_proto_new) {
 821                 netdev_err(dev, "Not supported proto admin requested");
 822                 return -EINVAL;
 823         }
 824         if (eth_proto_new == eth_proto_admin)
 825                 return 0;
 826
 827         mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, eth_proto_new);
 828         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 829         if (err) {
 830                 netdev_err(dev, "Failed to set proto admin");
 831                 return err;
 832         }
 833
 834         err = mlxsw_sx_port_oper_status_get(mlxsw_sx_port, &is_up);
 835         if (err) {
 836                 netdev_err(dev, "Failed to get oper status");
 837                 return err;
 838         }
 839         if (!is_up)
 840                 return 0;
 841
 842         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
 843         if (err) {
 844                 netdev_err(dev, "Failed to set admin status");
 845                 return err;
 846         }
 847
 848         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, true);
 849         if (err) {
 850                 netdev_err(dev, "Failed to set admin status");
 851                 return err;
 852         }
 853
 854         return 0;
 855 }
 856
 857 static const struct ethtool_ops mlxsw_sx_port_ethtool_ops = {
 858         .get_drvinfo            = mlxsw_sx_port_get_drvinfo,
 859         .get_link               = ethtool_op_get_link,
 860         .get_strings            = mlxsw_sx_port_get_strings,
 861         .get_ethtool_stats      = mlxsw_sx_port_get_stats,
 862         .get_sset_count         = mlxsw_sx_port_get_sset_count,
 863         .get_settings           = mlxsw_sx_port_get_settings,
 864         .set_settings           = mlxsw_sx_port_set_settings,
 865 };
 866
 867 static int mlxsw_sx_port_attr_get(struct net_device *dev,
 868                                   struct switchdev_attr *attr)
 869 {
 870         struct mlxsw_sx_port *mlxsw_sx_port = netdev_priv(dev);
 871         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 872
 873         switch (attr->id) {
 874         case SWITCHDEV_ATTR_ID_PORT_PARENT_ID:
 875                 attr->u.ppid.id_len = sizeof(mlxsw_sx->hw_id);
 876                 memcpy(&attr->u.ppid.id, &mlxsw_sx->hw_id, attr->u.ppid.id_len);
 877                 break;
 878         default:
 879                 return -EOPNOTSUPP;
 880         }
 881
 882         return 0;
 883 }
 884
 885 static const struct switchdev_ops mlxsw_sx_port_switchdev_ops = {
 886         .switchdev_port_attr_get        = mlxsw_sx_port_attr_get,
 887 };
 888
 889 static int mlxsw_sx_hw_id_get(struct mlxsw_sx *mlxsw_sx)
 890 {
 891         char spad_pl[MLXSW_REG_SPAD_LEN];
 892         int err;
 893
 894         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(spad), spad_pl);
 895         if (err)
 896                 return err;
 897         mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sx->hw_id);
 898         return 0;
 899 }
 900
 901 static int mlxsw_sx_port_dev_addr_get(struct mlxsw_sx_port *mlxsw_sx_port)
 902 {
 903         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 904         struct net_device *dev = mlxsw_sx_port->dev;
 905         char ppad_pl[MLXSW_REG_PPAD_LEN];
 906         int err;
 907
 908         mlxsw_reg_ppad_pack(ppad_pl, false, 0);
 909         err = mlxsw_reg_query(mlxsw_sx->core, MLXSW_REG(ppad), ppad_pl);
 910         if (err)
 911                 return err;
 912         mlxsw_reg_ppad_mac_memcpy_from(ppad_pl, dev->dev_addr);
 913         /* The last byte value in base mac address is guaranteed
 914          * to be such it does not overflow when adding local_port
 915          * value.
 916          */
 917         dev->dev_addr[ETH_ALEN - 1] += mlxsw_sx_port->local_port;
 918         return 0;
 919 }
 920
 921 static int mlxsw_sx_port_stp_state_set(struct mlxsw_sx_port *mlxsw_sx_port,
 922                                        u16 vid, enum mlxsw_reg_spms_state state)
 923 {
 924         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 925         char *spms_pl;
 926         int err;
 927
 928         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
 929         if (!spms_pl)
 930                 return -ENOMEM;
 931         mlxsw_reg_spms_pack(spms_pl, mlxsw_sx_port->local_port);
 932         mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
 933         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spms), spms_pl);
 934         kfree(spms_pl);
 935         return err;
 936 }
 937
 938 static int mlxsw_sx_port_speed_set(struct mlxsw_sx_port *mlxsw_sx_port,
 939                                    u32 speed)
 940 {
 941         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 942         char ptys_pl[MLXSW_REG_PTYS_LEN];
 943
 944         mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sx_port->local_port, speed);
 945         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(ptys), ptys_pl);
 946 }
 947
 948 static int
 949 mlxsw_sx_port_mac_learning_mode_set(struct mlxsw_sx_port *mlxsw_sx_port,
 950                                     enum mlxsw_reg_spmlr_learn_mode mode)
 951 {
 952         struct mlxsw_sx *mlxsw_sx = mlxsw_sx_port->mlxsw_sx;
 953         char spmlr_pl[MLXSW_REG_SPMLR_LEN];
 954
 955         mlxsw_reg_spmlr_pack(spmlr_pl, mlxsw_sx_port->local_port, mode);
 956         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(spmlr), spmlr_pl);
 957 }
 958
 959 static int mlxsw_sx_port_create(struct mlxsw_sx *mlxsw_sx, u8 local_port)
 960 {
 961         struct mlxsw_sx_port *mlxsw_sx_port;
 962         struct net_device *dev;
 963         bool usable;
 964         int err;
 965
 966         dev = alloc_etherdev(sizeof(struct mlxsw_sx_port));
 967         if (!dev)
 968                 return -ENOMEM;
 969         mlxsw_sx_port = netdev_priv(dev);
 970         mlxsw_sx_port->dev = dev;
 971         mlxsw_sx_port->mlxsw_sx = mlxsw_sx;
 972         mlxsw_sx_port->local_port = local_port;
 973
 974         mlxsw_sx_port->pcpu_stats =
 975                 netdev_alloc_pcpu_stats(struct mlxsw_sx_port_pcpu_stats);
 976         if (!mlxsw_sx_port->pcpu_stats) {
 977                 err = -ENOMEM;
 978                 goto err_alloc_stats;
 979         }
 980
 981         dev->netdev_ops = &mlxsw_sx_port_netdev_ops;
 982         dev->ethtool_ops = &mlxsw_sx_port_ethtool_ops;
 983         dev->switchdev_ops = &mlxsw_sx_port_switchdev_ops;
 984
 985         err = mlxsw_sx_port_dev_addr_get(mlxsw_sx_port);
 986         if (err) {
 987                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Unable to get port mac address\n",
 988                         mlxsw_sx_port->local_port);
 989                 goto err_dev_addr_get;
 990         }
 991
 992         netif_carrier_off(dev);
 993
 994         dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
 995                          NETIF_F_VLAN_CHALLENGED;
 996
 997         /* Each packet needs to have a Tx header (metadata) on top all other
 998          * headers.
 999          */
1000         dev->hard_header_len += MLXSW_TXHDR_LEN;
1001
1002         err = mlxsw_sx_port_module_check(mlxsw_sx_port, &usable);
1003         if (err) {
1004                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to check module\n",
1005                         mlxsw_sx_port->local_port);
1006                 goto err_port_module_check;
1007         }
1008
1009         if (!usable) {
1010                 dev_dbg(mlxsw_sx->bus_info->dev, "Port %d: Not usable, skipping initialization\n",
1011                         mlxsw_sx_port->local_port);
1012                 goto port_not_usable;
1013         }
1014
1015         err = mlxsw_sx_port_system_port_mapping_set(mlxsw_sx_port);
1016         if (err) {
1017                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1018                         mlxsw_sx_port->local_port);
1019                 goto err_port_system_port_mapping_set;
1020         }
1021
1022         err = mlxsw_sx_port_swid_set(mlxsw_sx_port, 0);
1023         if (err) {
1024                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set SWID\n",
1025                         mlxsw_sx_port->local_port);
1026                 goto err_port_swid_set;
1027         }
1028
1029         err = mlxsw_sx_port_speed_set(mlxsw_sx_port,
1030                                       MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4);
1031         if (err) {
1032                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set speed\n",
1033                         mlxsw_sx_port->local_port);
1034                 goto err_port_speed_set;
1035         }
1036
1037         err = mlxsw_sx_port_mtu_set(mlxsw_sx_port, ETH_DATA_LEN);
1038         if (err) {
1039                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MTU\n",
1040                         mlxsw_sx_port->local_port);
1041                 goto err_port_mtu_set;
1042         }
1043
1044         err = mlxsw_sx_port_admin_status_set(mlxsw_sx_port, false);
1045         if (err)
1046                 goto err_port_admin_status_set;
1047
1048         err = mlxsw_sx_port_stp_state_set(mlxsw_sx_port,
1049                                           MLXSW_PORT_DEFAULT_VID,
1050                                           MLXSW_REG_SPMS_STATE_FORWARDING);
1051         if (err) {
1052                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set STP state\n",
1053                         mlxsw_sx_port->local_port);
1054                 goto err_port_stp_state_set;
1055         }
1056
1057         err = mlxsw_sx_port_mac_learning_mode_set(mlxsw_sx_port,
1058                                                   MLXSW_REG_SPMLR_LEARN_MODE_DISABLE);
1059         if (err) {
1060                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to set MAC learning mode\n",
1061                         mlxsw_sx_port->local_port);
1062                 goto err_port_mac_learning_mode_set;
1063         }
1064
1065         err = register_netdev(dev);
1066         if (err) {
1067                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to register netdev\n",
1068                         mlxsw_sx_port->local_port);
1069                 goto err_register_netdev;
1070         }
1071
1072         err = mlxsw_core_port_init(mlxsw_sx->core, &mlxsw_sx_port->core_port,
1073                                    mlxsw_sx_port->local_port, dev, false, 0);
1074         if (err) {
1075                 dev_err(mlxsw_sx->bus_info->dev, "Port %d: Failed to init core port\n",
1076                         mlxsw_sx_port->local_port);
1077                 goto err_core_port_init;
1078         }
1079
1080         mlxsw_sx->ports[local_port] = mlxsw_sx_port;
1081         return 0;
1082
1083 err_core_port_init:
1084         unregister_netdev(dev);
1085 err_register_netdev:
1086 err_port_mac_learning_mode_set:
1087 err_port_stp_state_set:
1088 err_port_admin_status_set:
1089 err_port_mtu_set:
1090 err_port_speed_set:
1091 err_port_swid_set:
1092 err_port_system_port_mapping_set:
1093 port_not_usable:
1094 err_port_module_check:
1095 err_dev_addr_get:
1096         free_percpu(mlxsw_sx_port->pcpu_stats);
1097 err_alloc_stats:
1098         free_netdev(dev);
1099         return err;
1100 }
1101
1102 static void mlxsw_sx_port_remove(struct mlxsw_sx *mlxsw_sx, u8 local_port)
1103 {
1104         struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1105
1106         if (!mlxsw_sx_port)
1107                 return;
1108         mlxsw_core_port_fini(&mlxsw_sx_port->core_port);
1109         unregister_netdev(mlxsw_sx_port->dev); /* This calls ndo_stop */
1110         mlxsw_sx_port_swid_set(mlxsw_sx_port, MLXSW_PORT_SWID_DISABLED_PORT);
1111         free_percpu(mlxsw_sx_port->pcpu_stats);
1112         free_netdev(mlxsw_sx_port->dev);
1113 }
1114
1115 static void mlxsw_sx_ports_remove(struct mlxsw_sx *mlxsw_sx)
1116 {
1117         int i;
1118
1119         for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1120                 mlxsw_sx_port_remove(mlxsw_sx, i);
1121         kfree(mlxsw_sx->ports);
1122 }
1123
1124 static int mlxsw_sx_ports_create(struct mlxsw_sx *mlxsw_sx)
1125 {
1126         size_t alloc_size;
1127         int i;
1128         int err;
1129
1130         alloc_size = sizeof(struct mlxsw_sx_port *) * MLXSW_PORT_MAX_PORTS;
1131         mlxsw_sx->ports = kzalloc(alloc_size, GFP_KERNEL);
1132         if (!mlxsw_sx->ports)
1133                 return -ENOMEM;
1134
1135         for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
1136                 err = mlxsw_sx_port_create(mlxsw_sx, i);
1137                 if (err)
1138                         goto err_port_create;
1139         }
1140         return 0;
1141
1142 err_port_create:
1143         for (i--; i >= 1; i--)
1144                 mlxsw_sx_port_remove(mlxsw_sx, i);
1145         kfree(mlxsw_sx->ports);
1146         return err;
1147 }
1148
1149 static void mlxsw_sx_pude_event_func(const struct mlxsw_reg_info *reg,
1150                                      char *pude_pl, void *priv)
1151 {
1152         struct mlxsw_sx *mlxsw_sx = priv;
1153         struct mlxsw_sx_port *mlxsw_sx_port;
1154         enum mlxsw_reg_pude_oper_status status;
1155         u8 local_port;
1156
1157         local_port = mlxsw_reg_pude_local_port_get(pude_pl);
1158         mlxsw_sx_port = mlxsw_sx->ports[local_port];
1159         if (!mlxsw_sx_port) {
1160                 dev_warn(mlxsw_sx->bus_info->dev, "Port %d: Link event received for non-existent port\n",
1161                          local_port);
1162                 return;
1163         }
1164
1165         status = mlxsw_reg_pude_oper_status_get(pude_pl);
1166         if (status == MLXSW_PORT_OPER_STATUS_UP) {
1167                 netdev_info(mlxsw_sx_port->dev, "link up\n");
1168                 netif_carrier_on(mlxsw_sx_port->dev);
1169         } else {
1170                 netdev_info(mlxsw_sx_port->dev, "link down\n");
1171                 netif_carrier_off(mlxsw_sx_port->dev);
1172         }
1173 }
1174
1175 static struct mlxsw_event_listener mlxsw_sx_pude_event = {
1176         .func = mlxsw_sx_pude_event_func,
1177         .trap_id = MLXSW_TRAP_ID_PUDE,
1178 };
1179
1180 static int mlxsw_sx_event_register(struct mlxsw_sx *mlxsw_sx,
1181                                    enum mlxsw_event_trap_id trap_id)
1182 {
1183         struct mlxsw_event_listener *el;
1184         char hpkt_pl[MLXSW_REG_HPKT_LEN];
1185         int err;
1186
1187         switch (trap_id) {
1188         case MLXSW_TRAP_ID_PUDE:
1189                 el = &mlxsw_sx_pude_event;
1190                 break;
1191         }
1192         err = mlxsw_core_event_listener_register(mlxsw_sx->core, el, mlxsw_sx);
1193         if (err)
1194                 return err;
1195
1196         mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
1197         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1198         if (err)
1199                 goto err_event_trap_set;
1200
1201         return 0;
1202
1203 err_event_trap_set:
1204         mlxsw_core_event_listener_unregister(mlxsw_sx->core, el, mlxsw_sx);
1205         return err;
1206 }
1207
1208 static void mlxsw_sx_event_unregister(struct mlxsw_sx *mlxsw_sx,
1209                                       enum mlxsw_event_trap_id trap_id)
1210 {
1211         struct mlxsw_event_listener *el;
1212
1213         switch (trap_id) {
1214         case MLXSW_TRAP_ID_PUDE:
1215                 el = &mlxsw_sx_pude_event;
1216                 break;
1217         }
1218         mlxsw_core_event_listener_unregister(mlxsw_sx->core, el, mlxsw_sx);
1219 }
1220
1221 static void mlxsw_sx_rx_listener_func(struct sk_buff *skb, u8 local_port,
1222                                       void *priv)
1223 {
1224         struct mlxsw_sx *mlxsw_sx = priv;
1225         struct mlxsw_sx_port *mlxsw_sx_port = mlxsw_sx->ports[local_port];
1226         struct mlxsw_sx_port_pcpu_stats *pcpu_stats;
1227
1228         if (unlikely(!mlxsw_sx_port)) {
1229                 dev_warn_ratelimited(mlxsw_sx->bus_info->dev, "Port %d: skb received for non-existent port\n",
1230                                      local_port);
1231                 return;
1232         }
1233
1234         skb->dev = mlxsw_sx_port->dev;
1235
1236         pcpu_stats = this_cpu_ptr(mlxsw_sx_port->pcpu_stats);
1237         u64_stats_update_begin(&pcpu_stats->syncp);
1238         pcpu_stats->rx_packets++;
1239         pcpu_stats->rx_bytes += skb->len;
1240         u64_stats_update_end(&pcpu_stats->syncp);
1241
1242         skb->protocol = eth_type_trans(skb, skb->dev);
1243         netif_receive_skb(skb);
1244 }
1245
1246 static const struct mlxsw_rx_listener mlxsw_sx_rx_listener[] = {
1247         {
1248                 .func = mlxsw_sx_rx_listener_func,
1249                 .local_port = MLXSW_PORT_DONT_CARE,
1250                 .trap_id = MLXSW_TRAP_ID_FDB_MC,
1251         },
1252         /* Traps for specific L2 packet types, not trapped as FDB MC */
1253         {
1254                 .func = mlxsw_sx_rx_listener_func,
1255                 .local_port = MLXSW_PORT_DONT_CARE,
1256                 .trap_id = MLXSW_TRAP_ID_STP,
1257         },
1258         {
1259                 .func = mlxsw_sx_rx_listener_func,
1260                 .local_port = MLXSW_PORT_DONT_CARE,
1261                 .trap_id = MLXSW_TRAP_ID_LACP,
1262         },
1263         {
1264                 .func = mlxsw_sx_rx_listener_func,
1265                 .local_port = MLXSW_PORT_DONT_CARE,
1266                 .trap_id = MLXSW_TRAP_ID_EAPOL,
1267         },
1268         {
1269                 .func = mlxsw_sx_rx_listener_func,
1270                 .local_port = MLXSW_PORT_DONT_CARE,
1271                 .trap_id = MLXSW_TRAP_ID_LLDP,
1272         },
1273         {
1274                 .func = mlxsw_sx_rx_listener_func,
1275                 .local_port = MLXSW_PORT_DONT_CARE,
1276                 .trap_id = MLXSW_TRAP_ID_MMRP,
1277         },
1278         {
1279                 .func = mlxsw_sx_rx_listener_func,
1280                 .local_port = MLXSW_PORT_DONT_CARE,
1281                 .trap_id = MLXSW_TRAP_ID_MVRP,
1282         },
1283         {
1284                 .func = mlxsw_sx_rx_listener_func,
1285                 .local_port = MLXSW_PORT_DONT_CARE,
1286                 .trap_id = MLXSW_TRAP_ID_RPVST,
1287         },
1288         {
1289                 .func = mlxsw_sx_rx_listener_func,
1290                 .local_port = MLXSW_PORT_DONT_CARE,
1291                 .trap_id = MLXSW_TRAP_ID_DHCP,
1292         },
1293         {
1294                 .func = mlxsw_sx_rx_listener_func,
1295                 .local_port = MLXSW_PORT_DONT_CARE,
1296                 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
1297         },
1298         {
1299                 .func = mlxsw_sx_rx_listener_func,
1300                 .local_port = MLXSW_PORT_DONT_CARE,
1301                 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
1302         },
1303         {
1304                 .func = mlxsw_sx_rx_listener_func,
1305                 .local_port = MLXSW_PORT_DONT_CARE,
1306                 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
1307         },
1308         {
1309                 .func = mlxsw_sx_rx_listener_func,
1310                 .local_port = MLXSW_PORT_DONT_CARE,
1311                 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
1312         },
1313         {
1314                 .func = mlxsw_sx_rx_listener_func,
1315                 .local_port = MLXSW_PORT_DONT_CARE,
1316                 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
1317         },
1318 };
1319
1320 static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1321 {
1322         char htgt_pl[MLXSW_REG_HTGT_LEN];
1323         char hpkt_pl[MLXSW_REG_HPKT_LEN];
1324         int i;
1325         int err;
1326
1327         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
1328         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1329         if (err)
1330                 return err;
1331
1332         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
1333         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1334         if (err)
1335                 return err;
1336
1337         for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1338                 err = mlxsw_core_rx_listener_register(mlxsw_sx->core,
1339                                                       &mlxsw_sx_rx_listener[i],
1340                                                       mlxsw_sx);
1341                 if (err)
1342                         goto err_rx_listener_register;
1343
1344                 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
1345                                     mlxsw_sx_rx_listener[i].trap_id);
1346                 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1347                 if (err)
1348                         goto err_rx_trap_set;
1349         }
1350         return 0;
1351
1352 err_rx_trap_set:
1353         mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1354                                           &mlxsw_sx_rx_listener[i],
1355                                           mlxsw_sx);
1356 err_rx_listener_register:
1357         for (i--; i >= 0; i--) {
1358                 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1359                                     mlxsw_sx_rx_listener[i].trap_id);
1360                 mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1361
1362                 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1363                                                   &mlxsw_sx_rx_listener[i],
1364                                                   mlxsw_sx);
1365         }
1366         return err;
1367 }
1368
1369 static void mlxsw_sx_traps_fini(struct mlxsw_sx *mlxsw_sx)
1370 {
1371         char hpkt_pl[MLXSW_REG_HPKT_LEN];
1372         int i;
1373
1374         for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1375                 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD,
1376                                     mlxsw_sx_rx_listener[i].trap_id);
1377                 mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(hpkt), hpkt_pl);
1378
1379                 mlxsw_core_rx_listener_unregister(mlxsw_sx->core,
1380                                                   &mlxsw_sx_rx_listener[i],
1381                                                   mlxsw_sx);
1382         }
1383 }
1384
1385 static int mlxsw_sx_flood_init(struct mlxsw_sx *mlxsw_sx)
1386 {
1387         char sfgc_pl[MLXSW_REG_SFGC_LEN];
1388         char sgcr_pl[MLXSW_REG_SGCR_LEN];
1389         char *sftr_pl;
1390         int err;
1391
1392         /* Configure a flooding table, which includes only CPU port. */
1393         sftr_pl = kmalloc(MLXSW_REG_SFTR_LEN, GFP_KERNEL);
1394         if (!sftr_pl)
1395                 return -ENOMEM;
1396         mlxsw_reg_sftr_pack(sftr_pl, 0, 0, MLXSW_REG_SFGC_TABLE_TYPE_SINGLE, 0,
1397                             MLXSW_PORT_CPU_PORT, true);
1398         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sftr), sftr_pl);
1399         kfree(sftr_pl);
1400         if (err)
1401                 return err;
1402
1403         /* Flood different packet types using the flooding table. */
1404         mlxsw_reg_sfgc_pack(sfgc_pl,
1405                             MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
1406                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1407                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1408                             0);
1409         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1410         if (err)
1411                 return err;
1412
1413         mlxsw_reg_sfgc_pack(sfgc_pl,
1414                             MLXSW_REG_SFGC_TYPE_BROADCAST,
1415                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1416                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1417                             0);
1418         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1419         if (err)
1420                 return err;
1421
1422         mlxsw_reg_sfgc_pack(sfgc_pl,
1423                             MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
1424                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1425                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1426                             0);
1427         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1428         if (err)
1429                 return err;
1430
1431         mlxsw_reg_sfgc_pack(sfgc_pl,
1432                             MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
1433                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1434                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1435                             0);
1436         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1437         if (err)
1438                 return err;
1439
1440         mlxsw_reg_sfgc_pack(sfgc_pl,
1441                             MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
1442                             MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID,
1443                             MLXSW_REG_SFGC_TABLE_TYPE_SINGLE,
1444                             0);
1445         err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sfgc), sfgc_pl);
1446         if (err)
1447                 return err;
1448
1449         mlxsw_reg_sgcr_pack(sgcr_pl, true);
1450         return mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(sgcr), sgcr_pl);
1451 }
1452
1453 static int mlxsw_sx_init(struct mlxsw_core *mlxsw_core,
1454                          const struct mlxsw_bus_info *mlxsw_bus_info)
1455 {
1456         struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1457         int err;
1458
1459         mlxsw_sx->core = mlxsw_core;
1460         mlxsw_sx->bus_info = mlxsw_bus_info;
1461
1462         err = mlxsw_sx_hw_id_get(mlxsw_sx);
1463         if (err) {
1464                 dev_err(mlxsw_sx->bus_info->dev, "Failed to get switch HW ID\n");
1465                 return err;
1466         }
1467
1468         err = mlxsw_sx_ports_create(mlxsw_sx);
1469         if (err) {
1470                 dev_err(mlxsw_sx->bus_info->dev, "Failed to create ports\n");
1471                 return err;
1472         }
1473
1474         err = mlxsw_sx_event_register(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1475         if (err) {
1476                 dev_err(mlxsw_sx->bus_info->dev, "Failed to register for PUDE events\n");
1477                 goto err_event_register;
1478         }
1479
1480         err = mlxsw_sx_traps_init(mlxsw_sx);
1481         if (err) {
1482                 dev_err(mlxsw_sx->bus_info->dev, "Failed to set traps for RX\n");
1483                 goto err_rx_listener_register;
1484         }
1485
1486         err = mlxsw_sx_flood_init(mlxsw_sx);
1487         if (err) {
1488                 dev_err(mlxsw_sx->bus_info->dev, "Failed to initialize flood tables\n");
1489                 goto err_flood_init;
1490         }
1491
1492         return 0;
1493
1494 err_flood_init:
1495         mlxsw_sx_traps_fini(mlxsw_sx);
1496 err_rx_listener_register:
1497         mlxsw_sx_event_unregister(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1498 err_event_register:
1499         mlxsw_sx_ports_remove(mlxsw_sx);
1500         return err;
1501 }
1502
1503 static void mlxsw_sx_fini(struct mlxsw_core *mlxsw_core)
1504 {
1505         struct mlxsw_sx *mlxsw_sx = mlxsw_core_driver_priv(mlxsw_core);
1506
1507         mlxsw_sx_traps_fini(mlxsw_sx);
1508         mlxsw_sx_event_unregister(mlxsw_sx, MLXSW_TRAP_ID_PUDE);
1509         mlxsw_sx_ports_remove(mlxsw_sx);
1510 }
1511
1512 static struct mlxsw_config_profile mlxsw_sx_config_profile = {
1513         .used_max_vepa_channels         = 1,
1514         .max_vepa_channels              = 0,
1515         .used_max_lag                   = 1,
1516         .max_lag                        = 64,
1517         .used_max_port_per_lag          = 1,
1518         .max_port_per_lag               = 16,
1519         .used_max_mid                   = 1,
1520         .max_mid                        = 7000,
1521         .used_max_pgt                   = 1,
1522         .max_pgt                        = 0,
1523         .used_max_system_port           = 1,
1524         .max_system_port                = 48000,
1525         .used_max_vlan_groups           = 1,
1526         .max_vlan_groups                = 127,
1527         .used_max_regions               = 1,
1528         .max_regions                    = 400,
1529         .used_flood_tables              = 1,
1530         .max_flood_tables               = 2,
1531         .max_vid_flood_tables           = 1,
1532         .used_flood_mode                = 1,
1533         .flood_mode                     = 3,
1534         .used_max_ib_mc                 = 1,
1535         .max_ib_mc                      = 0,
1536         .used_max_pkey                  = 1,
1537         .max_pkey                       = 0,
1538         .swid_config                    = {
1539                 {
1540                         .used_type      = 1,
1541                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
1542                 }
1543         },
1544 };
1545
1546 static struct mlxsw_driver mlxsw_sx_driver = {
1547         .kind                   = MLXSW_DEVICE_KIND_SWITCHX2,
1548         .owner                  = THIS_MODULE,
1549         .priv_size              = sizeof(struct mlxsw_sx),
1550         .init                   = mlxsw_sx_init,
1551         .fini                   = mlxsw_sx_fini,
1552         .txhdr_construct        = mlxsw_sx_txhdr_construct,
1553         .txhdr_len              = MLXSW_TXHDR_LEN,
1554         .profile                = &mlxsw_sx_config_profile,
1555 };
1556
1557 static int __init mlxsw_sx_module_init(void)
1558 {
1559         return mlxsw_core_driver_register(&mlxsw_sx_driver);
1560 }
1561
1562 static void __exit mlxsw_sx_module_exit(void)
1563 {
1564         mlxsw_core_driver_unregister(&mlxsw_sx_driver);
1565 }
1566
1567 module_init(mlxsw_sx_module_init);
1568 module_exit(mlxsw_sx_module_exit);
1569
1570 MODULE_LICENSE("Dual BSD/GPL");
1571 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
1572 MODULE_DESCRIPTION("Mellanox SwitchX-2 driver");
1573 MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SWITCHX2);