2 * Texas Instruments Ethernet Switch Driver
4 * Copyright (C) 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
39 #include <linux/pinctrl/consumer.h>
44 #include "davinci_cpdma.h"
46 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
55 #define cpsw_info(priv, type, format, ...) \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
61 #define cpsw_err(priv, type, format, ...) \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
67 #define cpsw_dbg(priv, type, format, ...) \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
73 #define cpsw_notice(priv, type, format, ...) \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
79 #define ALE_ALL_PORTS 0x7
81 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
85 #define CPSW_VERSION_1 0x19010a
86 #define CPSW_VERSION_2 0x19010c
87 #define CPSW_VERSION_3 0x19010f
88 #define CPSW_VERSION_4 0x190112
90 #define HOST_PORT_NUM 0
91 #define SLIVER_SIZE 0x40
93 #define CPSW1_HOST_PORT_OFFSET 0x028
94 #define CPSW1_SLAVE_OFFSET 0x050
95 #define CPSW1_SLAVE_SIZE 0x040
96 #define CPSW1_CPDMA_OFFSET 0x100
97 #define CPSW1_STATERAM_OFFSET 0x200
98 #define CPSW1_HW_STATS 0x400
99 #define CPSW1_CPTS_OFFSET 0x500
100 #define CPSW1_ALE_OFFSET 0x600
101 #define CPSW1_SLIVER_OFFSET 0x700
103 #define CPSW2_HOST_PORT_OFFSET 0x108
104 #define CPSW2_SLAVE_OFFSET 0x200
105 #define CPSW2_SLAVE_SIZE 0x100
106 #define CPSW2_CPDMA_OFFSET 0x800
107 #define CPSW2_HW_STATS 0x900
108 #define CPSW2_STATERAM_OFFSET 0xa00
109 #define CPSW2_CPTS_OFFSET 0xc00
110 #define CPSW2_ALE_OFFSET 0xd00
111 #define CPSW2_SLIVER_OFFSET 0xd80
112 #define CPSW2_BD_OFFSET 0x2000
114 #define CPDMA_RXTHRESH 0x0c0
115 #define CPDMA_RXFREE 0x0e0
116 #define CPDMA_TXHDP 0x00
117 #define CPDMA_RXHDP 0x20
118 #define CPDMA_TXCP 0x40
119 #define CPDMA_RXCP 0x60
121 #define CPSW_POLL_WEIGHT 64
122 #define CPSW_MIN_PACKET_SIZE 60
123 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
125 #define RX_PRIORITY_MAPPING 0x76543210
126 #define TX_PRIORITY_MAPPING 0x33221100
127 #define CPDMA_TX_PRIORITY_MAP 0x01234567
129 #define CPSW_VLAN_AWARE BIT(1)
130 #define CPSW_ALE_VLAN_AWARE 1
132 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
136 #define CPSW_INTPACEEN (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT 63
139 #define CPSW_CMINTMIN_CNT 2
140 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
143 #define cpsw_slave_index(cpsw, priv) \
144 ((cpsw->data.dual_emac) ? priv->emac_port : \
145 cpsw->data.active_slave)
147 #define CPSW_MAX_QUEUES 8
149 static int debug_level;
150 module_param(debug_level, int, 0);
151 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
153 static int ale_ageout = 10;
154 module_param(ale_ageout, int, 0);
155 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
157 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
158 module_param(rx_packet_max, int, 0);
159 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
161 struct cpsw_wr_regs {
181 struct cpsw_ss_regs {
198 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
199 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
200 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
201 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
202 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
203 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
204 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
205 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
208 #define CPSW2_CONTROL 0x00 /* Control Register */
209 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
210 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
211 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
212 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
213 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
214 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
216 /* CPSW_PORT_V1 and V2 */
217 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
218 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
219 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
221 /* CPSW_PORT_V2 only */
222 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
223 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
224 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
225 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
226 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
227 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
228 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
229 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
231 /* Bit definitions for the CPSW2_CONTROL register */
232 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
233 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
234 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
235 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
236 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
237 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
238 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
239 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
240 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
241 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
242 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
243 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
244 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
245 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
246 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
247 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
248 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
250 #define CTRL_V2_TS_BITS \
251 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
252 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
254 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
255 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
256 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
259 #define CTRL_V3_TS_BITS \
260 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
261 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
264 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
265 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
266 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
268 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
269 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
270 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
271 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
272 #define TS_MSG_TYPE_EN_MASK (0xffff)
274 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
275 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
277 /* Bit definitions for the CPSW1_TS_CTL register */
278 #define CPSW_V1_TS_RX_EN BIT(0)
279 #define CPSW_V1_TS_TX_EN BIT(4)
280 #define CPSW_V1_MSG_TYPE_OFS 16
282 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
283 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
285 struct cpsw_host_regs {
291 u32 cpdma_tx_pri_map;
292 u32 cpdma_rx_chan_map;
295 struct cpsw_sliver_regs {
308 struct cpsw_hw_stats {
310 u32 rxbroadcastframes;
311 u32 rxmulticastframes;
314 u32 rxaligncodeerrors;
315 u32 rxoversizedframes;
317 u32 rxundersizedframes;
322 u32 txbroadcastframes;
323 u32 txmulticastframes;
325 u32 txdeferredframes;
326 u32 txcollisionframes;
327 u32 txsinglecollframes;
328 u32 txmultcollframes;
329 u32 txexcessivecollisions;
330 u32 txlatecollisions;
332 u32 txcarriersenseerrors;
335 u32 octetframes65t127;
336 u32 octetframes128t255;
337 u32 octetframes256t511;
338 u32 octetframes512t1023;
339 u32 octetframes1024tup;
348 struct cpsw_sliver_regs __iomem *sliver;
351 struct cpsw_slave_data *data;
352 struct phy_device *phy;
353 struct net_device *ndev;
358 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
360 return __raw_readl(slave->regs + offset);
363 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
365 __raw_writel(val, slave->regs + offset);
369 struct cpdma_chan *ch;
375 struct cpsw_platform_data data;
376 struct napi_struct napi_rx;
377 struct napi_struct napi_tx;
378 struct cpsw_ss_regs __iomem *regs;
379 struct cpsw_wr_regs __iomem *wr_regs;
380 u8 __iomem *hw_stats;
381 struct cpsw_host_regs __iomem *host_port_regs;
386 struct cpsw_slave *slaves;
387 struct cpdma_ctlr *dma;
388 struct cpsw_vector txv[CPSW_MAX_QUEUES];
389 struct cpsw_vector rxv[CPSW_MAX_QUEUES];
390 struct cpsw_ale *ale;
392 bool rx_irq_disabled;
393 bool tx_irq_disabled;
394 u32 irqs_table[IRQ_NUM];
396 int rx_ch_num, tx_ch_num;
401 struct net_device *ndev;
404 u8 mac_addr[ETH_ALEN];
408 struct cpsw_common *cpsw;
412 char stat_string[ETH_GSTRING_LEN];
424 #define CPSW_STAT(m) CPSW_STATS, \
425 sizeof(((struct cpsw_hw_stats *)0)->m), \
426 offsetof(struct cpsw_hw_stats, m)
427 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
428 sizeof(((struct cpdma_chan_stats *)0)->m), \
429 offsetof(struct cpdma_chan_stats, m)
430 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
431 sizeof(((struct cpdma_chan_stats *)0)->m), \
432 offsetof(struct cpdma_chan_stats, m)
434 static const struct cpsw_stats cpsw_gstrings_stats[] = {
435 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
436 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
437 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
438 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
439 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
440 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
441 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
442 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
443 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
444 { "Rx Fragments", CPSW_STAT(rxfragments) },
445 { "Rx Octets", CPSW_STAT(rxoctets) },
446 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
447 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
448 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
449 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
450 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
451 { "Collisions", CPSW_STAT(txcollisionframes) },
452 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
453 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
454 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
455 { "Late Collisions", CPSW_STAT(txlatecollisions) },
456 { "Tx Underrun", CPSW_STAT(txunderrun) },
457 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
458 { "Tx Octets", CPSW_STAT(txoctets) },
459 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
460 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
461 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
462 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
463 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
464 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
465 { "Net Octets", CPSW_STAT(netoctets) },
466 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
467 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
468 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
471 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
472 { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
473 { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
474 { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
475 { "misqueued", CPDMA_RX_STAT(misqueued) },
476 { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
477 { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
478 { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
479 { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
480 { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
481 { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
482 { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
483 { "requeue", CPDMA_RX_STAT(requeue) },
484 { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
487 #define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats)
488 #define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats)
490 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
491 #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
492 #define for_each_slave(priv, func, arg...) \
494 struct cpsw_slave *slave; \
495 struct cpsw_common *cpsw = (priv)->cpsw; \
497 if (cpsw->data.dual_emac) \
498 (func)((cpsw)->slaves + priv->emac_port, ##arg);\
500 for (n = cpsw->data.slaves, \
501 slave = cpsw->slaves; \
503 (func)(slave++, ##arg); \
506 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb) \
508 if (!cpsw->data.dual_emac) \
510 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
511 ndev = cpsw->slaves[0].ndev; \
513 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
514 ndev = cpsw->slaves[1].ndev; \
518 #define cpsw_add_mcast(cpsw, priv, addr) \
520 if (cpsw->data.dual_emac) { \
521 struct cpsw_slave *slave = cpsw->slaves + \
523 int slave_port = cpsw_get_slave_port( \
525 cpsw_ale_add_mcast(cpsw->ale, addr, \
526 1 << slave_port | ALE_PORT_HOST, \
527 ALE_VLAN, slave->port_vlan, 0); \
529 cpsw_ale_add_mcast(cpsw->ale, addr, \
535 static inline int cpsw_get_slave_port(u32 slave_num)
537 return slave_num + 1;
540 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
542 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
543 struct cpsw_ale *ale = cpsw->ale;
546 if (cpsw->data.dual_emac) {
549 /* Enabling promiscuous mode for one interface will be
550 * common for both the interface as the interface shares
551 * the same hardware resource.
553 for (i = 0; i < cpsw->data.slaves; i++)
554 if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
557 if (!enable && flag) {
559 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
564 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
566 dev_dbg(&ndev->dev, "promiscuity enabled\n");
569 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
570 dev_dbg(&ndev->dev, "promiscuity disabled\n");
574 unsigned long timeout = jiffies + HZ;
576 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
577 for (i = 0; i <= cpsw->data.slaves; i++) {
578 cpsw_ale_control_set(ale, i,
579 ALE_PORT_NOLEARN, 1);
580 cpsw_ale_control_set(ale, i,
581 ALE_PORT_NO_SA_UPDATE, 1);
584 /* Clear All Untouched entries */
585 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
588 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
590 } while (time_after(timeout, jiffies));
591 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
593 /* Clear all mcast from ALE */
594 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
596 /* Flood All Unicast Packets to Host port */
597 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
598 dev_dbg(&ndev->dev, "promiscuity enabled\n");
600 /* Don't Flood All Unicast Packets to Host port */
601 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
603 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
604 for (i = 0; i <= cpsw->data.slaves; i++) {
605 cpsw_ale_control_set(ale, i,
606 ALE_PORT_NOLEARN, 0);
607 cpsw_ale_control_set(ale, i,
608 ALE_PORT_NO_SA_UPDATE, 0);
610 dev_dbg(&ndev->dev, "promiscuity disabled\n");
615 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
617 struct cpsw_priv *priv = netdev_priv(ndev);
618 struct cpsw_common *cpsw = priv->cpsw;
621 if (cpsw->data.dual_emac)
622 vid = cpsw->slaves[priv->emac_port].port_vlan;
624 vid = cpsw->data.default_vlan;
626 if (ndev->flags & IFF_PROMISC) {
627 /* Enable promiscuous mode */
628 cpsw_set_promiscious(ndev, true);
629 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
632 /* Disable promiscuous mode */
633 cpsw_set_promiscious(ndev, false);
636 /* Restore allmulti on vlans if necessary */
637 cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
639 /* Clear all mcast from ALE */
640 cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
642 if (!netdev_mc_empty(ndev)) {
643 struct netdev_hw_addr *ha;
645 /* program multicast address list into ALE register */
646 netdev_for_each_mc_addr(ha, ndev) {
647 cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
652 static void cpsw_intr_enable(struct cpsw_common *cpsw)
654 __raw_writel(0xFF, &cpsw->wr_regs->tx_en);
655 __raw_writel(0xFF, &cpsw->wr_regs->rx_en);
657 cpdma_ctlr_int_ctrl(cpsw->dma, true);
661 static void cpsw_intr_disable(struct cpsw_common *cpsw)
663 __raw_writel(0, &cpsw->wr_regs->tx_en);
664 __raw_writel(0, &cpsw->wr_regs->rx_en);
666 cpdma_ctlr_int_ctrl(cpsw->dma, false);
670 static void cpsw_tx_handler(void *token, int len, int status)
672 struct netdev_queue *txq;
673 struct sk_buff *skb = token;
674 struct net_device *ndev = skb->dev;
675 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
677 /* Check whether the queue is stopped due to stalled tx dma, if the
678 * queue is stopped then start the queue as we have free desc for tx
680 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
681 if (unlikely(netif_tx_queue_stopped(txq)))
682 netif_tx_wake_queue(txq);
684 cpts_tx_timestamp(cpsw->cpts, skb);
685 ndev->stats.tx_packets++;
686 ndev->stats.tx_bytes += len;
687 dev_kfree_skb_any(skb);
690 static void cpsw_rx_handler(void *token, int len, int status)
692 struct cpdma_chan *ch;
693 struct sk_buff *skb = token;
694 struct sk_buff *new_skb;
695 struct net_device *ndev = skb->dev;
697 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
699 cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
701 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
702 bool ndev_status = false;
703 struct cpsw_slave *slave = cpsw->slaves;
706 if (cpsw->data.dual_emac) {
707 /* In dual emac mode check for all interfaces */
708 for (n = cpsw->data.slaves; n; n--, slave++)
709 if (netif_running(slave->ndev))
713 if (ndev_status && (status >= 0)) {
714 /* The packet received is for the interface which
715 * is already down and the other interface is up
716 * and running, instead of freeing which results
717 * in reducing of the number of rx descriptor in
718 * DMA engine, requeue skb back to cpdma.
724 /* the interface is going down, skbs are purged */
725 dev_kfree_skb_any(skb);
729 new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
731 skb_copy_queue_mapping(new_skb, skb);
733 cpts_rx_timestamp(cpsw->cpts, skb);
734 skb->protocol = eth_type_trans(skb, ndev);
735 netif_receive_skb(skb);
736 ndev->stats.rx_bytes += len;
737 ndev->stats.rx_packets++;
738 kmemleak_not_leak(new_skb);
740 ndev->stats.rx_dropped++;
745 if (netif_dormant(ndev)) {
746 dev_kfree_skb_any(new_skb);
750 ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
751 ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
752 skb_tailroom(new_skb), 0);
753 if (WARN_ON(ret < 0))
754 dev_kfree_skb_any(new_skb);
757 static void cpsw_split_res(struct net_device *ndev)
759 struct cpsw_priv *priv = netdev_priv(ndev);
760 u32 consumed_rate = 0, bigest_rate = 0;
761 struct cpsw_common *cpsw = priv->cpsw;
762 struct cpsw_vector *txv = cpsw->txv;
763 int i, ch_weight, rlim_ch_num = 0;
764 int budget, bigest_rate_ch = 0;
765 u32 ch_rate, max_rate;
768 for (i = 0; i < cpsw->tx_ch_num; i++) {
769 ch_rate = cpdma_chan_get_rate(txv[i].ch);
774 consumed_rate += ch_rate;
777 if (cpsw->tx_ch_num == rlim_ch_num) {
778 max_rate = consumed_rate;
779 } else if (!rlim_ch_num) {
780 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
782 max_rate = consumed_rate;
784 max_rate = cpsw->speed * 1000;
786 /* if max_rate is less then expected due to reduced link speed,
787 * split proportionally according next potential max speed
789 if (max_rate < consumed_rate)
792 if (max_rate < consumed_rate)
795 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
796 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
797 (cpsw->tx_ch_num - rlim_ch_num);
798 bigest_rate = (max_rate - consumed_rate) /
799 (cpsw->tx_ch_num - rlim_ch_num);
802 /* split tx weight/budget */
803 budget = CPSW_POLL_WEIGHT;
804 for (i = 0; i < cpsw->tx_ch_num; i++) {
805 ch_rate = cpdma_chan_get_rate(txv[i].ch);
807 txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
810 if (ch_rate > bigest_rate) {
812 bigest_rate = ch_rate;
815 ch_weight = (ch_rate * 100) / max_rate;
818 cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
820 txv[i].budget = ch_budget;
823 cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
826 budget -= txv[i].budget;
830 txv[bigest_rate_ch].budget += budget;
832 /* split rx budget */
833 budget = CPSW_POLL_WEIGHT;
834 ch_budget = budget / cpsw->rx_ch_num;
835 for (i = 0; i < cpsw->rx_ch_num; i++) {
836 cpsw->rxv[i].budget = ch_budget;
841 cpsw->rxv[0].budget += budget;
844 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
846 struct cpsw_common *cpsw = dev_id;
848 writel(0, &cpsw->wr_regs->tx_en);
849 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
851 if (cpsw->quirk_irq) {
852 disable_irq_nosync(cpsw->irqs_table[1]);
853 cpsw->tx_irq_disabled = true;
856 napi_schedule(&cpsw->napi_tx);
860 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
862 struct cpsw_common *cpsw = dev_id;
864 cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
865 writel(0, &cpsw->wr_regs->rx_en);
867 if (cpsw->quirk_irq) {
868 disable_irq_nosync(cpsw->irqs_table[0]);
869 cpsw->rx_irq_disabled = true;
872 napi_schedule(&cpsw->napi_rx);
876 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
879 int num_tx, cur_budget, ch;
880 struct cpsw_common *cpsw = napi_to_cpsw(napi_tx);
881 struct cpsw_vector *txv;
883 /* process every unprocessed channel */
884 ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
885 for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
886 if (!(ch_map & 0x01))
889 txv = &cpsw->txv[ch];
890 if (unlikely(txv->budget > budget - num_tx))
891 cur_budget = budget - num_tx;
893 cur_budget = txv->budget;
895 num_tx += cpdma_chan_process(txv->ch, cur_budget);
896 if (num_tx >= budget)
900 if (num_tx < budget) {
901 napi_complete(napi_tx);
902 writel(0xff, &cpsw->wr_regs->tx_en);
903 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
904 cpsw->tx_irq_disabled = false;
905 enable_irq(cpsw->irqs_table[1]);
912 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
915 int num_rx, cur_budget, ch;
916 struct cpsw_common *cpsw = napi_to_cpsw(napi_rx);
917 struct cpsw_vector *rxv;
919 /* process every unprocessed channel */
920 ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
921 for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
922 if (!(ch_map & 0x01))
925 rxv = &cpsw->rxv[ch];
926 if (unlikely(rxv->budget > budget - num_rx))
927 cur_budget = budget - num_rx;
929 cur_budget = rxv->budget;
931 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
932 if (num_rx >= budget)
936 if (num_rx < budget) {
937 napi_complete(napi_rx);
938 writel(0xff, &cpsw->wr_regs->rx_en);
939 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
940 cpsw->rx_irq_disabled = false;
941 enable_irq(cpsw->irqs_table[0]);
948 static inline void soft_reset(const char *module, void __iomem *reg)
950 unsigned long timeout = jiffies + HZ;
952 __raw_writel(1, reg);
955 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
957 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
960 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
961 ((mac)[2] << 16) | ((mac)[3] << 24))
962 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
964 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
965 struct cpsw_priv *priv)
967 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
968 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
971 static void _cpsw_adjust_link(struct cpsw_slave *slave,
972 struct cpsw_priv *priv, bool *link)
974 struct phy_device *phy = slave->phy;
977 struct cpsw_common *cpsw = priv->cpsw;
982 slave_port = cpsw_get_slave_port(slave->slave_num);
985 mac_control = cpsw->data.mac_control;
987 /* enable forwarding */
988 cpsw_ale_control_set(cpsw->ale, slave_port,
989 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
991 if (phy->speed == 1000)
992 mac_control |= BIT(7); /* GIGABITEN */
994 mac_control |= BIT(0); /* FULLDUPLEXEN */
996 /* set speed_in input in case RMII mode is used in 100Mbps */
997 if (phy->speed == 100)
998 mac_control |= BIT(15);
999 else if (phy->speed == 10)
1000 mac_control |= BIT(18); /* In Band mode */
1003 mac_control |= BIT(3);
1006 mac_control |= BIT(4);
1011 /* disable forwarding */
1012 cpsw_ale_control_set(cpsw->ale, slave_port,
1013 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1016 if (mac_control != slave->mac_control) {
1017 phy_print_status(phy);
1018 __raw_writel(mac_control, &slave->sliver->mac_control);
1021 slave->mac_control = mac_control;
1024 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1028 for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1029 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1030 speed += cpsw->slaves[i].phy->speed;
1035 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1040 /* re-split resources only in case speed was changed */
1041 speed = cpsw_get_common_speed(cpsw);
1042 if (speed == cpsw->speed || !speed)
1045 cpsw->speed = speed;
1047 for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1048 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1055 /* cases not dependent on speed */
1056 if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1062 static void cpsw_adjust_link(struct net_device *ndev)
1064 struct cpsw_priv *priv = netdev_priv(ndev);
1065 struct cpsw_common *cpsw = priv->cpsw;
1068 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1071 if (cpsw_need_resplit(cpsw))
1072 cpsw_split_res(ndev);
1074 netif_carrier_on(ndev);
1075 if (netif_running(ndev))
1076 netif_tx_wake_all_queues(ndev);
1078 netif_carrier_off(ndev);
1079 netif_tx_stop_all_queues(ndev);
1083 static int cpsw_get_coalesce(struct net_device *ndev,
1084 struct ethtool_coalesce *coal)
1086 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1088 coal->rx_coalesce_usecs = cpsw->coal_intvl;
1092 static int cpsw_set_coalesce(struct net_device *ndev,
1093 struct ethtool_coalesce *coal)
1095 struct cpsw_priv *priv = netdev_priv(ndev);
1097 u32 num_interrupts = 0;
1101 struct cpsw_common *cpsw = priv->cpsw;
1103 coal_intvl = coal->rx_coalesce_usecs;
1105 int_ctrl = readl(&cpsw->wr_regs->int_control);
1106 prescale = cpsw->bus_freq_mhz * 4;
1108 if (!coal->rx_coalesce_usecs) {
1109 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1113 if (coal_intvl < CPSW_CMINTMIN_INTVL)
1114 coal_intvl = CPSW_CMINTMIN_INTVL;
1116 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1117 /* Interrupt pacer works with 4us Pulse, we can
1118 * throttle further by dilating the 4us pulse.
1120 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1122 if (addnl_dvdr > 1) {
1123 prescale *= addnl_dvdr;
1124 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1125 coal_intvl = (CPSW_CMINTMAX_INTVL
1129 coal_intvl = CPSW_CMINTMAX_INTVL;
1133 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1134 writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1135 writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1137 int_ctrl |= CPSW_INTPACEEN;
1138 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1139 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1142 writel(int_ctrl, &cpsw->wr_regs->int_control);
1144 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1145 cpsw->coal_intvl = coal_intvl;
1150 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1152 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1156 return (CPSW_STATS_COMMON_LEN +
1157 (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1164 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1170 ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1171 for (i = 0; i < ch_stats_len; i++) {
1172 line = i % CPSW_STATS_CH_LEN;
1173 snprintf(*p, ETH_GSTRING_LEN,
1174 "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1175 i / CPSW_STATS_CH_LEN,
1176 cpsw_gstrings_ch_stats[line].stat_string);
1177 *p += ETH_GSTRING_LEN;
1181 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1183 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1187 switch (stringset) {
1189 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1190 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1192 p += ETH_GSTRING_LEN;
1195 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1196 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1201 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1202 struct ethtool_stats *stats, u64 *data)
1205 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1206 struct cpdma_chan_stats ch_stats;
1209 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1210 for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1211 data[l] = readl(cpsw->hw_stats +
1212 cpsw_gstrings_stats[l].stat_offset);
1214 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1215 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1216 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1217 p = (u8 *)&ch_stats +
1218 cpsw_gstrings_ch_stats[i].stat_offset;
1219 data[l] = *(u32 *)p;
1223 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1224 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1225 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1226 p = (u8 *)&ch_stats +
1227 cpsw_gstrings_ch_stats[i].stat_offset;
1228 data[l] = *(u32 *)p;
1233 static int cpsw_common_res_usage_state(struct cpsw_common *cpsw)
1236 u32 usage_count = 0;
1238 if (!cpsw->data.dual_emac)
1241 for (i = 0; i < cpsw->data.slaves; i++)
1242 if (cpsw->slaves[i].open_stat)
1248 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1249 struct sk_buff *skb,
1250 struct cpdma_chan *txch)
1252 struct cpsw_common *cpsw = priv->cpsw;
1254 return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1255 priv->emac_port + cpsw->data.dual_emac);
1258 static inline void cpsw_add_dual_emac_def_ale_entries(
1259 struct cpsw_priv *priv, struct cpsw_slave *slave,
1262 struct cpsw_common *cpsw = priv->cpsw;
1263 u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1265 if (cpsw->version == CPSW_VERSION_1)
1266 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1268 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1269 cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1270 port_mask, port_mask, 0);
1271 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1272 port_mask, ALE_VLAN, slave->port_vlan, 0);
1273 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1274 HOST_PORT_NUM, ALE_VLAN |
1275 ALE_SECURE, slave->port_vlan);
1278 static void soft_reset_slave(struct cpsw_slave *slave)
1282 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1283 soft_reset(name, &slave->sliver->soft_reset);
1286 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1289 struct cpsw_common *cpsw = priv->cpsw;
1291 soft_reset_slave(slave);
1293 /* setup priority mapping */
1294 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1296 switch (cpsw->version) {
1297 case CPSW_VERSION_1:
1298 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1300 case CPSW_VERSION_2:
1301 case CPSW_VERSION_3:
1302 case CPSW_VERSION_4:
1303 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1307 /* setup max packet size, and mac address */
1308 __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1309 cpsw_set_slave_mac(slave, priv);
1311 slave->mac_control = 0; /* no link yet */
1313 slave_port = cpsw_get_slave_port(slave->slave_num);
1315 if (cpsw->data.dual_emac)
1316 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1318 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1319 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1321 if (slave->data->phy_node) {
1322 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1323 &cpsw_adjust_link, 0, slave->data->phy_if);
1325 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1326 slave->data->phy_node->full_name,
1331 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1332 &cpsw_adjust_link, slave->data->phy_if);
1333 if (IS_ERR(slave->phy)) {
1335 "phy \"%s\" not found on slave %d, err %ld\n",
1336 slave->data->phy_id, slave->slave_num,
1337 PTR_ERR(slave->phy));
1343 phy_attached_info(slave->phy);
1345 phy_start(slave->phy);
1347 /* Configure GMII_SEL register */
1348 cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1351 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1353 struct cpsw_common *cpsw = priv->cpsw;
1354 const int vlan = cpsw->data.default_vlan;
1357 int unreg_mcast_mask;
1359 reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1362 writel(vlan, &cpsw->host_port_regs->port_vlan);
1364 for (i = 0; i < cpsw->data.slaves; i++)
1365 slave_write(cpsw->slaves + i, vlan, reg);
1367 if (priv->ndev->flags & IFF_ALLMULTI)
1368 unreg_mcast_mask = ALE_ALL_PORTS;
1370 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1372 cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1373 ALE_ALL_PORTS, ALE_ALL_PORTS,
1377 static void cpsw_init_host_port(struct cpsw_priv *priv)
1381 struct cpsw_common *cpsw = priv->cpsw;
1383 /* soft reset the controller and initialize ale */
1384 soft_reset("cpsw", &cpsw->regs->soft_reset);
1385 cpsw_ale_start(cpsw->ale);
1387 /* switch to vlan unaware mode */
1388 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1389 CPSW_ALE_VLAN_AWARE);
1390 control_reg = readl(&cpsw->regs->control);
1391 control_reg |= CPSW_VLAN_AWARE;
1392 writel(control_reg, &cpsw->regs->control);
1393 fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1394 CPSW_FIFO_NORMAL_MODE;
1395 writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1397 /* setup host port priority mapping */
1398 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1399 &cpsw->host_port_regs->cpdma_tx_pri_map);
1400 __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1402 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1403 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1405 if (!cpsw->data.dual_emac) {
1406 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1408 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1409 ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1413 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1415 struct cpsw_common *cpsw = priv->cpsw;
1416 struct sk_buff *skb;
1420 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1421 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1422 for (i = 0; i < ch_buf_num; i++) {
1423 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1424 cpsw->rx_packet_max,
1427 cpsw_err(priv, ifup, "cannot allocate skb\n");
1431 skb_set_queue_mapping(skb, ch);
1432 ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1433 skb->data, skb_tailroom(skb),
1436 cpsw_err(priv, ifup,
1437 "cannot submit skb to channel %d rx, error %d\n",
1442 kmemleak_not_leak(skb);
1445 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1452 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1456 slave_port = cpsw_get_slave_port(slave->slave_num);
1460 phy_stop(slave->phy);
1461 phy_disconnect(slave->phy);
1463 cpsw_ale_control_set(cpsw->ale, slave_port,
1464 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1465 soft_reset_slave(slave);
1468 static int cpsw_ndo_open(struct net_device *ndev)
1470 struct cpsw_priv *priv = netdev_priv(ndev);
1471 struct cpsw_common *cpsw = priv->cpsw;
1475 ret = pm_runtime_get_sync(cpsw->dev);
1477 pm_runtime_put_noidle(cpsw->dev);
1481 if (!cpsw_common_res_usage_state(cpsw))
1482 cpsw_intr_disable(cpsw);
1483 netif_carrier_off(ndev);
1485 /* Notify the stack of the actual queue counts. */
1486 ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1488 dev_err(priv->dev, "cannot set real number of tx queues\n");
1492 ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1494 dev_err(priv->dev, "cannot set real number of rx queues\n");
1498 reg = cpsw->version;
1500 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1501 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1502 CPSW_RTL_VERSION(reg));
1504 /* initialize host and slave ports */
1505 if (!cpsw_common_res_usage_state(cpsw))
1506 cpsw_init_host_port(priv);
1507 for_each_slave(priv, cpsw_slave_open, priv);
1509 /* Add default VLAN */
1510 if (!cpsw->data.dual_emac)
1511 cpsw_add_default_vlan(priv);
1513 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1514 ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1516 if (!cpsw_common_res_usage_state(cpsw)) {
1517 /* disable priority elevation */
1518 __raw_writel(0, &cpsw->regs->ptype);
1520 /* enable statistics collection only on all ports */
1521 __raw_writel(0x7, &cpsw->regs->stat_port_en);
1523 /* Enable internal fifo flow control */
1524 writel(0x7, &cpsw->regs->flow_control);
1526 napi_enable(&cpsw->napi_rx);
1527 napi_enable(&cpsw->napi_tx);
1529 if (cpsw->tx_irq_disabled) {
1530 cpsw->tx_irq_disabled = false;
1531 enable_irq(cpsw->irqs_table[1]);
1534 if (cpsw->rx_irq_disabled) {
1535 cpsw->rx_irq_disabled = false;
1536 enable_irq(cpsw->irqs_table[0]);
1539 ret = cpsw_fill_rx_channels(priv);
1543 if (cpts_register(cpsw->cpts))
1544 dev_err(priv->dev, "error registering cpts device\n");
1548 /* Enable Interrupt pacing if configured */
1549 if (cpsw->coal_intvl != 0) {
1550 struct ethtool_coalesce coal;
1552 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1553 cpsw_set_coalesce(ndev, &coal);
1556 cpdma_ctlr_start(cpsw->dma);
1557 cpsw_intr_enable(cpsw);
1559 if (cpsw->data.dual_emac)
1560 cpsw->slaves[priv->emac_port].open_stat = true;
1565 cpdma_ctlr_stop(cpsw->dma);
1566 for_each_slave(priv, cpsw_slave_stop, cpsw);
1567 pm_runtime_put_sync(cpsw->dev);
1568 netif_carrier_off(priv->ndev);
1572 static int cpsw_ndo_stop(struct net_device *ndev)
1574 struct cpsw_priv *priv = netdev_priv(ndev);
1575 struct cpsw_common *cpsw = priv->cpsw;
1577 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1578 netif_tx_stop_all_queues(priv->ndev);
1579 netif_carrier_off(priv->ndev);
1581 if (cpsw_common_res_usage_state(cpsw) <= 1) {
1582 napi_disable(&cpsw->napi_rx);
1583 napi_disable(&cpsw->napi_tx);
1584 cpts_unregister(cpsw->cpts);
1585 cpsw_intr_disable(cpsw);
1586 cpdma_ctlr_stop(cpsw->dma);
1587 cpsw_ale_stop(cpsw->ale);
1589 for_each_slave(priv, cpsw_slave_stop, cpsw);
1591 if (cpsw_need_resplit(cpsw))
1592 cpsw_split_res(ndev);
1594 pm_runtime_put_sync(cpsw->dev);
1595 if (cpsw->data.dual_emac)
1596 cpsw->slaves[priv->emac_port].open_stat = false;
1600 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1601 struct net_device *ndev)
1603 struct cpsw_priv *priv = netdev_priv(ndev);
1604 struct cpsw_common *cpsw = priv->cpsw;
1605 struct netdev_queue *txq;
1606 struct cpdma_chan *txch;
1609 netif_trans_update(ndev);
1611 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1612 cpsw_err(priv, tx_err, "packet pad failed\n");
1613 ndev->stats.tx_dropped++;
1614 return NETDEV_TX_OK;
1617 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1618 cpts_is_tx_enabled(cpsw->cpts))
1619 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1621 skb_tx_timestamp(skb);
1623 q_idx = skb_get_queue_mapping(skb);
1624 if (q_idx >= cpsw->tx_ch_num)
1625 q_idx = q_idx % cpsw->tx_ch_num;
1627 txch = cpsw->txv[q_idx].ch;
1628 ret = cpsw_tx_packet_submit(priv, skb, txch);
1629 if (unlikely(ret != 0)) {
1630 cpsw_err(priv, tx_err, "desc submit failed\n");
1634 /* If there is no more tx desc left free then we need to
1635 * tell the kernel to stop sending us tx frames.
1637 if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1638 txq = netdev_get_tx_queue(ndev, q_idx);
1639 netif_tx_stop_queue(txq);
1642 return NETDEV_TX_OK;
1644 ndev->stats.tx_dropped++;
1645 txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
1646 netif_tx_stop_queue(txq);
1647 return NETDEV_TX_BUSY;
1650 #if IS_ENABLED(CONFIG_TI_CPTS)
1652 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1654 struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1657 if (!cpts_is_tx_enabled(cpsw->cpts) &&
1658 !cpts_is_rx_enabled(cpsw->cpts)) {
1659 slave_write(slave, 0, CPSW1_TS_CTL);
1663 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1664 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1666 if (cpts_is_tx_enabled(cpsw->cpts))
1667 ts_en |= CPSW_V1_TS_TX_EN;
1669 if (cpts_is_rx_enabled(cpsw->cpts))
1670 ts_en |= CPSW_V1_TS_RX_EN;
1672 slave_write(slave, ts_en, CPSW1_TS_CTL);
1673 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1676 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1678 struct cpsw_slave *slave;
1679 struct cpsw_common *cpsw = priv->cpsw;
1682 slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1684 ctrl = slave_read(slave, CPSW2_CONTROL);
1685 switch (cpsw->version) {
1686 case CPSW_VERSION_2:
1687 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1689 if (cpts_is_tx_enabled(cpsw->cpts))
1690 ctrl |= CTRL_V2_TX_TS_BITS;
1692 if (cpts_is_rx_enabled(cpsw->cpts))
1693 ctrl |= CTRL_V2_RX_TS_BITS;
1695 case CPSW_VERSION_3:
1697 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1699 if (cpts_is_tx_enabled(cpsw->cpts))
1700 ctrl |= CTRL_V3_TX_TS_BITS;
1702 if (cpts_is_rx_enabled(cpsw->cpts))
1703 ctrl |= CTRL_V3_RX_TS_BITS;
1707 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1709 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1710 slave_write(slave, ctrl, CPSW2_CONTROL);
1711 __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
1714 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1716 struct cpsw_priv *priv = netdev_priv(dev);
1717 struct hwtstamp_config cfg;
1718 struct cpsw_common *cpsw = priv->cpsw;
1719 struct cpts *cpts = cpsw->cpts;
1721 if (cpsw->version != CPSW_VERSION_1 &&
1722 cpsw->version != CPSW_VERSION_2 &&
1723 cpsw->version != CPSW_VERSION_3)
1726 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1729 /* reserved for future extensions */
1733 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1736 switch (cfg.rx_filter) {
1737 case HWTSTAMP_FILTER_NONE:
1738 cpts_rx_enable(cpts, 0);
1740 case HWTSTAMP_FILTER_ALL:
1741 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1742 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1743 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1745 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1746 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1747 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1748 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1749 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1750 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1751 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1752 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1753 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1754 cpts_rx_enable(cpts, 1);
1755 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1761 cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
1763 switch (cpsw->version) {
1764 case CPSW_VERSION_1:
1765 cpsw_hwtstamp_v1(cpsw);
1767 case CPSW_VERSION_2:
1768 case CPSW_VERSION_3:
1769 cpsw_hwtstamp_v2(priv);
1775 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1778 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1780 struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1781 struct cpts *cpts = cpsw->cpts;
1782 struct hwtstamp_config cfg;
1784 if (cpsw->version != CPSW_VERSION_1 &&
1785 cpsw->version != CPSW_VERSION_2 &&
1786 cpsw->version != CPSW_VERSION_3)
1790 cfg.tx_type = cpts_is_tx_enabled(cpts) ?
1791 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1792 cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
1793 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1795 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1798 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1803 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1807 #endif /*CONFIG_TI_CPTS*/
1809 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1811 struct cpsw_priv *priv = netdev_priv(dev);
1812 struct cpsw_common *cpsw = priv->cpsw;
1813 int slave_no = cpsw_slave_index(cpsw, priv);
1815 if (!netif_running(dev))
1820 return cpsw_hwtstamp_set(dev, req);
1822 return cpsw_hwtstamp_get(dev, req);
1825 if (!cpsw->slaves[slave_no].phy)
1827 return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1830 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1832 struct cpsw_priv *priv = netdev_priv(ndev);
1833 struct cpsw_common *cpsw = priv->cpsw;
1836 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1837 ndev->stats.tx_errors++;
1838 cpsw_intr_disable(cpsw);
1839 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1840 cpdma_chan_stop(cpsw->txv[ch].ch);
1841 cpdma_chan_start(cpsw->txv[ch].ch);
1844 cpsw_intr_enable(cpsw);
1847 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1849 struct cpsw_priv *priv = netdev_priv(ndev);
1850 struct sockaddr *addr = (struct sockaddr *)p;
1851 struct cpsw_common *cpsw = priv->cpsw;
1856 if (!is_valid_ether_addr(addr->sa_data))
1857 return -EADDRNOTAVAIL;
1859 ret = pm_runtime_get_sync(cpsw->dev);
1861 pm_runtime_put_noidle(cpsw->dev);
1865 if (cpsw->data.dual_emac) {
1866 vid = cpsw->slaves[priv->emac_port].port_vlan;
1870 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1872 cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1875 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1876 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1877 for_each_slave(priv, cpsw_set_slave_mac, priv);
1879 pm_runtime_put(cpsw->dev);
1884 #ifdef CONFIG_NET_POLL_CONTROLLER
1885 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1887 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1889 cpsw_intr_disable(cpsw);
1890 cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1891 cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1892 cpsw_intr_enable(cpsw);
1896 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1900 int unreg_mcast_mask = 0;
1902 struct cpsw_common *cpsw = priv->cpsw;
1904 if (cpsw->data.dual_emac) {
1905 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1907 if (priv->ndev->flags & IFF_ALLMULTI)
1908 unreg_mcast_mask = port_mask;
1910 port_mask = ALE_ALL_PORTS;
1912 if (priv->ndev->flags & IFF_ALLMULTI)
1913 unreg_mcast_mask = ALE_ALL_PORTS;
1915 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1918 ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
1923 ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1924 HOST_PORT_NUM, ALE_VLAN, vid);
1928 ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1929 port_mask, ALE_VLAN, vid, 0);
1931 goto clean_vlan_ucast;
1935 cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1936 HOST_PORT_NUM, ALE_VLAN, vid);
1938 cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1942 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1943 __be16 proto, u16 vid)
1945 struct cpsw_priv *priv = netdev_priv(ndev);
1946 struct cpsw_common *cpsw = priv->cpsw;
1949 if (vid == cpsw->data.default_vlan)
1952 ret = pm_runtime_get_sync(cpsw->dev);
1954 pm_runtime_put_noidle(cpsw->dev);
1958 if (cpsw->data.dual_emac) {
1959 /* In dual EMAC, reserved VLAN id should not be used for
1960 * creating VLAN interfaces as this can break the dual
1961 * EMAC port separation
1965 for (i = 0; i < cpsw->data.slaves; i++) {
1966 if (vid == cpsw->slaves[i].port_vlan)
1971 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1972 ret = cpsw_add_vlan_ale_entry(priv, vid);
1974 pm_runtime_put(cpsw->dev);
1978 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1979 __be16 proto, u16 vid)
1981 struct cpsw_priv *priv = netdev_priv(ndev);
1982 struct cpsw_common *cpsw = priv->cpsw;
1985 if (vid == cpsw->data.default_vlan)
1988 ret = pm_runtime_get_sync(cpsw->dev);
1990 pm_runtime_put_noidle(cpsw->dev);
1994 if (cpsw->data.dual_emac) {
1997 for (i = 0; i < cpsw->data.slaves; i++) {
1998 if (vid == cpsw->slaves[i].port_vlan)
2003 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2004 ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2008 ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2009 HOST_PORT_NUM, ALE_VLAN, vid);
2013 ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2015 pm_runtime_put(cpsw->dev);
2019 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2021 struct cpsw_priv *priv = netdev_priv(ndev);
2022 struct cpsw_common *cpsw = priv->cpsw;
2023 struct cpsw_slave *slave;
2028 ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2029 if (ch_rate == rate)
2032 ch_rate = rate * 1000;
2033 min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2034 if ((ch_rate < min_rate && ch_rate)) {
2035 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2040 if (rate > cpsw->speed) {
2041 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2045 ret = pm_runtime_get_sync(cpsw->dev);
2047 pm_runtime_put_noidle(cpsw->dev);
2051 ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2052 pm_runtime_put(cpsw->dev);
2057 /* update rates for slaves tx queues */
2058 for (i = 0; i < cpsw->data.slaves; i++) {
2059 slave = &cpsw->slaves[i];
2063 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2066 cpsw_split_res(ndev);
2070 static const struct net_device_ops cpsw_netdev_ops = {
2071 .ndo_open = cpsw_ndo_open,
2072 .ndo_stop = cpsw_ndo_stop,
2073 .ndo_start_xmit = cpsw_ndo_start_xmit,
2074 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
2075 .ndo_do_ioctl = cpsw_ndo_ioctl,
2076 .ndo_validate_addr = eth_validate_addr,
2077 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
2078 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
2079 .ndo_set_tx_maxrate = cpsw_ndo_set_tx_maxrate,
2080 #ifdef CONFIG_NET_POLL_CONTROLLER
2081 .ndo_poll_controller = cpsw_ndo_poll_controller,
2083 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
2084 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
2087 static int cpsw_get_regs_len(struct net_device *ndev)
2089 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2091 return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2094 static void cpsw_get_regs(struct net_device *ndev,
2095 struct ethtool_regs *regs, void *p)
2098 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2100 /* update CPSW IP version */
2101 regs->version = cpsw->version;
2103 cpsw_ale_dump(cpsw->ale, reg);
2106 static void cpsw_get_drvinfo(struct net_device *ndev,
2107 struct ethtool_drvinfo *info)
2109 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2110 struct platform_device *pdev = to_platform_device(cpsw->dev);
2112 strlcpy(info->driver, "cpsw", sizeof(info->driver));
2113 strlcpy(info->version, "1.0", sizeof(info->version));
2114 strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2117 static u32 cpsw_get_msglevel(struct net_device *ndev)
2119 struct cpsw_priv *priv = netdev_priv(ndev);
2120 return priv->msg_enable;
2123 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2125 struct cpsw_priv *priv = netdev_priv(ndev);
2126 priv->msg_enable = value;
2129 #if IS_ENABLED(CONFIG_TI_CPTS)
2130 static int cpsw_get_ts_info(struct net_device *ndev,
2131 struct ethtool_ts_info *info)
2133 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2135 info->so_timestamping =
2136 SOF_TIMESTAMPING_TX_HARDWARE |
2137 SOF_TIMESTAMPING_TX_SOFTWARE |
2138 SOF_TIMESTAMPING_RX_HARDWARE |
2139 SOF_TIMESTAMPING_RX_SOFTWARE |
2140 SOF_TIMESTAMPING_SOFTWARE |
2141 SOF_TIMESTAMPING_RAW_HARDWARE;
2142 info->phc_index = cpsw->cpts->phc_index;
2144 (1 << HWTSTAMP_TX_OFF) |
2145 (1 << HWTSTAMP_TX_ON);
2147 (1 << HWTSTAMP_FILTER_NONE) |
2148 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2152 static int cpsw_get_ts_info(struct net_device *ndev,
2153 struct ethtool_ts_info *info)
2155 info->so_timestamping =
2156 SOF_TIMESTAMPING_TX_SOFTWARE |
2157 SOF_TIMESTAMPING_RX_SOFTWARE |
2158 SOF_TIMESTAMPING_SOFTWARE;
2159 info->phc_index = -1;
2161 info->rx_filters = 0;
2166 static int cpsw_get_link_ksettings(struct net_device *ndev,
2167 struct ethtool_link_ksettings *ecmd)
2169 struct cpsw_priv *priv = netdev_priv(ndev);
2170 struct cpsw_common *cpsw = priv->cpsw;
2171 int slave_no = cpsw_slave_index(cpsw, priv);
2173 if (cpsw->slaves[slave_no].phy)
2174 return phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy,
2180 static int cpsw_set_link_ksettings(struct net_device *ndev,
2181 const struct ethtool_link_ksettings *ecmd)
2183 struct cpsw_priv *priv = netdev_priv(ndev);
2184 struct cpsw_common *cpsw = priv->cpsw;
2185 int slave_no = cpsw_slave_index(cpsw, priv);
2187 if (cpsw->slaves[slave_no].phy)
2188 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2194 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2196 struct cpsw_priv *priv = netdev_priv(ndev);
2197 struct cpsw_common *cpsw = priv->cpsw;
2198 int slave_no = cpsw_slave_index(cpsw, priv);
2203 if (cpsw->slaves[slave_no].phy)
2204 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2207 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2209 struct cpsw_priv *priv = netdev_priv(ndev);
2210 struct cpsw_common *cpsw = priv->cpsw;
2211 int slave_no = cpsw_slave_index(cpsw, priv);
2213 if (cpsw->slaves[slave_no].phy)
2214 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2219 static void cpsw_get_pauseparam(struct net_device *ndev,
2220 struct ethtool_pauseparam *pause)
2222 struct cpsw_priv *priv = netdev_priv(ndev);
2224 pause->autoneg = AUTONEG_DISABLE;
2225 pause->rx_pause = priv->rx_pause ? true : false;
2226 pause->tx_pause = priv->tx_pause ? true : false;
2229 static int cpsw_set_pauseparam(struct net_device *ndev,
2230 struct ethtool_pauseparam *pause)
2232 struct cpsw_priv *priv = netdev_priv(ndev);
2235 priv->rx_pause = pause->rx_pause ? true : false;
2236 priv->tx_pause = pause->tx_pause ? true : false;
2238 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2242 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2244 struct cpsw_priv *priv = netdev_priv(ndev);
2245 struct cpsw_common *cpsw = priv->cpsw;
2248 ret = pm_runtime_get_sync(cpsw->dev);
2250 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2251 pm_runtime_put_noidle(cpsw->dev);
2257 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2259 struct cpsw_priv *priv = netdev_priv(ndev);
2262 ret = pm_runtime_put(priv->cpsw->dev);
2264 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2267 static void cpsw_get_channels(struct net_device *ndev,
2268 struct ethtool_channels *ch)
2270 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2272 ch->max_combined = 0;
2273 ch->max_rx = CPSW_MAX_QUEUES;
2274 ch->max_tx = CPSW_MAX_QUEUES;
2276 ch->other_count = 0;
2277 ch->rx_count = cpsw->rx_ch_num;
2278 ch->tx_count = cpsw->tx_ch_num;
2279 ch->combined_count = 0;
2282 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2283 struct ethtool_channels *ch)
2285 if (ch->combined_count)
2288 /* verify we have at least one channel in each direction */
2289 if (!ch->rx_count || !ch->tx_count)
2292 if (ch->rx_count > cpsw->data.channels ||
2293 ch->tx_count > cpsw->data.channels)
2299 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2301 int (*poll)(struct napi_struct *, int);
2302 struct cpsw_common *cpsw = priv->cpsw;
2303 void (*handler)(void *, int, int);
2304 struct netdev_queue *queue;
2305 struct cpsw_vector *vec;
2309 ch = &cpsw->rx_ch_num;
2311 handler = cpsw_rx_handler;
2312 poll = cpsw_rx_poll;
2314 ch = &cpsw->tx_ch_num;
2316 handler = cpsw_tx_handler;
2317 poll = cpsw_tx_poll;
2320 while (*ch < ch_num) {
2321 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2322 queue = netdev_get_tx_queue(priv->ndev, *ch);
2323 queue->tx_maxrate = 0;
2325 if (IS_ERR(vec[*ch].ch))
2326 return PTR_ERR(vec[*ch].ch);
2331 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2332 (rx ? "rx" : "tx"));
2336 while (*ch > ch_num) {
2339 ret = cpdma_chan_destroy(vec[*ch].ch);
2343 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2344 (rx ? "rx" : "tx"));
2350 static int cpsw_update_channels(struct cpsw_priv *priv,
2351 struct ethtool_channels *ch)
2355 ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2359 ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2366 static int cpsw_set_channels(struct net_device *ndev,
2367 struct ethtool_channels *chs)
2369 struct cpsw_priv *priv = netdev_priv(ndev);
2370 struct cpsw_common *cpsw = priv->cpsw;
2371 struct cpsw_slave *slave;
2374 ret = cpsw_check_ch_settings(cpsw, chs);
2378 /* Disable NAPI scheduling */
2379 cpsw_intr_disable(cpsw);
2381 /* Stop all transmit queues for every network device.
2382 * Disable re-using rx descriptors with dormant_on.
2384 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2385 if (!(slave->ndev && netif_running(slave->ndev)))
2388 netif_tx_stop_all_queues(slave->ndev);
2389 netif_dormant_on(slave->ndev);
2392 /* Handle rest of tx packets and stop cpdma channels */
2393 cpdma_ctlr_stop(cpsw->dma);
2394 ret = cpsw_update_channels(priv, chs);
2398 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2399 if (!(slave->ndev && netif_running(slave->ndev)))
2402 /* Inform stack about new count of queues */
2403 ret = netif_set_real_num_tx_queues(slave->ndev,
2406 dev_err(priv->dev, "cannot set real number of tx queues\n");
2410 ret = netif_set_real_num_rx_queues(slave->ndev,
2413 dev_err(priv->dev, "cannot set real number of rx queues\n");
2417 /* Enable rx packets handling */
2418 netif_dormant_off(slave->ndev);
2421 if (cpsw_common_res_usage_state(cpsw)) {
2422 ret = cpsw_fill_rx_channels(priv);
2426 cpsw_split_res(ndev);
2428 /* After this receive is started */
2429 cpdma_ctlr_start(cpsw->dma);
2430 cpsw_intr_enable(cpsw);
2433 /* Resume transmit for every affected interface */
2434 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2435 if (!(slave->ndev && netif_running(slave->ndev)))
2437 netif_tx_start_all_queues(slave->ndev);
2441 dev_err(priv->dev, "cannot update channels number, closing device\n");
2446 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2448 struct cpsw_priv *priv = netdev_priv(ndev);
2449 struct cpsw_common *cpsw = priv->cpsw;
2450 int slave_no = cpsw_slave_index(cpsw, priv);
2452 if (cpsw->slaves[slave_no].phy)
2453 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2458 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2460 struct cpsw_priv *priv = netdev_priv(ndev);
2461 struct cpsw_common *cpsw = priv->cpsw;
2462 int slave_no = cpsw_slave_index(cpsw, priv);
2464 if (cpsw->slaves[slave_no].phy)
2465 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2470 static int cpsw_nway_reset(struct net_device *ndev)
2472 struct cpsw_priv *priv = netdev_priv(ndev);
2473 struct cpsw_common *cpsw = priv->cpsw;
2474 int slave_no = cpsw_slave_index(cpsw, priv);
2476 if (cpsw->slaves[slave_no].phy)
2477 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2482 static const struct ethtool_ops cpsw_ethtool_ops = {
2483 .get_drvinfo = cpsw_get_drvinfo,
2484 .get_msglevel = cpsw_get_msglevel,
2485 .set_msglevel = cpsw_set_msglevel,
2486 .get_link = ethtool_op_get_link,
2487 .get_ts_info = cpsw_get_ts_info,
2488 .get_coalesce = cpsw_get_coalesce,
2489 .set_coalesce = cpsw_set_coalesce,
2490 .get_sset_count = cpsw_get_sset_count,
2491 .get_strings = cpsw_get_strings,
2492 .get_ethtool_stats = cpsw_get_ethtool_stats,
2493 .get_pauseparam = cpsw_get_pauseparam,
2494 .set_pauseparam = cpsw_set_pauseparam,
2495 .get_wol = cpsw_get_wol,
2496 .set_wol = cpsw_set_wol,
2497 .get_regs_len = cpsw_get_regs_len,
2498 .get_regs = cpsw_get_regs,
2499 .begin = cpsw_ethtool_op_begin,
2500 .complete = cpsw_ethtool_op_complete,
2501 .get_channels = cpsw_get_channels,
2502 .set_channels = cpsw_set_channels,
2503 .get_link_ksettings = cpsw_get_link_ksettings,
2504 .set_link_ksettings = cpsw_set_link_ksettings,
2505 .get_eee = cpsw_get_eee,
2506 .set_eee = cpsw_set_eee,
2507 .nway_reset = cpsw_nway_reset,
2510 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2511 u32 slave_reg_ofs, u32 sliver_reg_ofs)
2513 void __iomem *regs = cpsw->regs;
2514 int slave_num = slave->slave_num;
2515 struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num;
2518 slave->regs = regs + slave_reg_ofs;
2519 slave->sliver = regs + sliver_reg_ofs;
2520 slave->port_vlan = data->dual_emac_res_vlan;
2523 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2524 struct platform_device *pdev)
2526 struct device_node *node = pdev->dev.of_node;
2527 struct device_node *slave_node;
2534 if (of_property_read_u32(node, "slaves", &prop)) {
2535 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2538 data->slaves = prop;
2540 if (of_property_read_u32(node, "active_slave", &prop)) {
2541 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2544 data->active_slave = prop;
2546 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2547 * sizeof(struct cpsw_slave_data),
2549 if (!data->slave_data)
2552 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2553 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2556 data->channels = prop;
2558 if (of_property_read_u32(node, "ale_entries", &prop)) {
2559 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2562 data->ale_entries = prop;
2564 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2565 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2568 data->bd_ram_size = prop;
2570 if (of_property_read_u32(node, "mac_control", &prop)) {
2571 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2574 data->mac_control = prop;
2576 if (of_property_read_bool(node, "dual_emac"))
2577 data->dual_emac = 1;
2580 * Populate all the child nodes here...
2582 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2583 /* We do not want to force this, as in some cases may not have child */
2585 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2587 for_each_available_child_of_node(node, slave_node) {
2588 struct cpsw_slave_data *slave_data = data->slave_data + i;
2589 const void *mac_addr = NULL;
2593 /* This is no slave child node, continue */
2594 if (strcmp(slave_node->name, "slave"))
2597 slave_data->phy_node = of_parse_phandle(slave_node,
2599 parp = of_get_property(slave_node, "phy_id", &lenp);
2600 if (slave_data->phy_node) {
2602 "slave[%d] using phy-handle=\"%s\"\n",
2603 i, slave_data->phy_node->full_name);
2604 } else if (of_phy_is_fixed_link(slave_node)) {
2605 /* In the case of a fixed PHY, the DT node associated
2606 * to the PHY is the Ethernet MAC DT node.
2608 ret = of_phy_register_fixed_link(slave_node);
2610 if (ret != -EPROBE_DEFER)
2611 dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2614 slave_data->phy_node = of_node_get(slave_node);
2617 struct device_node *mdio_node;
2618 struct platform_device *mdio;
2620 if (lenp != (sizeof(__be32) * 2)) {
2621 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2624 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2625 phyid = be32_to_cpup(parp+1);
2626 mdio = of_find_device_by_node(mdio_node);
2627 of_node_put(mdio_node);
2629 dev_err(&pdev->dev, "Missing mdio platform device\n");
2632 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2633 PHY_ID_FMT, mdio->name, phyid);
2634 put_device(&mdio->dev);
2637 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2641 slave_data->phy_if = of_get_phy_mode(slave_node);
2642 if (slave_data->phy_if < 0) {
2643 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2645 return slave_data->phy_if;
2649 mac_addr = of_get_mac_address(slave_node);
2651 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2653 ret = ti_cm_get_macid(&pdev->dev, i,
2654 slave_data->mac_addr);
2658 if (data->dual_emac) {
2659 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2661 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2662 slave_data->dual_emac_res_vlan = i+1;
2663 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2664 slave_data->dual_emac_res_vlan, i);
2666 slave_data->dual_emac_res_vlan = prop;
2671 if (i == data->slaves)
2678 static void cpsw_remove_dt(struct platform_device *pdev)
2680 struct net_device *ndev = platform_get_drvdata(pdev);
2681 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2682 struct cpsw_platform_data *data = &cpsw->data;
2683 struct device_node *node = pdev->dev.of_node;
2684 struct device_node *slave_node;
2687 for_each_available_child_of_node(node, slave_node) {
2688 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2690 if (strcmp(slave_node->name, "slave"))
2693 if (of_phy_is_fixed_link(slave_node))
2694 of_phy_deregister_fixed_link(slave_node);
2696 of_node_put(slave_data->phy_node);
2699 if (i == data->slaves)
2703 of_platform_depopulate(&pdev->dev);
2706 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2708 struct cpsw_common *cpsw = priv->cpsw;
2709 struct cpsw_platform_data *data = &cpsw->data;
2710 struct net_device *ndev;
2711 struct cpsw_priv *priv_sl2;
2714 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2716 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2720 priv_sl2 = netdev_priv(ndev);
2721 priv_sl2->cpsw = cpsw;
2722 priv_sl2->ndev = ndev;
2723 priv_sl2->dev = &ndev->dev;
2724 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2726 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2727 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2729 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2730 priv_sl2->mac_addr);
2732 random_ether_addr(priv_sl2->mac_addr);
2733 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2734 priv_sl2->mac_addr);
2736 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2738 priv_sl2->emac_port = 1;
2739 cpsw->slaves[1].ndev = ndev;
2740 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2742 ndev->netdev_ops = &cpsw_netdev_ops;
2743 ndev->ethtool_ops = &cpsw_ethtool_ops;
2745 /* register the network device */
2746 SET_NETDEV_DEV(ndev, cpsw->dev);
2747 ret = register_netdev(ndev);
2749 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2757 #define CPSW_QUIRK_IRQ BIT(0)
2759 static struct platform_device_id cpsw_devtype[] = {
2761 /* keep it for existing comaptibles */
2763 .driver_data = CPSW_QUIRK_IRQ,
2765 .name = "am335x-cpsw",
2766 .driver_data = CPSW_QUIRK_IRQ,
2768 .name = "am4372-cpsw",
2771 .name = "dra7-cpsw",
2777 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2786 static const struct of_device_id cpsw_of_mtable[] = {
2787 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2788 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2789 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2790 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2793 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2795 static int cpsw_probe(struct platform_device *pdev)
2798 struct cpsw_platform_data *data;
2799 struct net_device *ndev;
2800 struct cpsw_priv *priv;
2801 struct cpdma_params dma_params;
2802 struct cpsw_ale_params ale_params;
2803 void __iomem *ss_regs;
2804 void __iomem *cpts_regs;
2805 struct resource *res, *ss_res;
2806 const struct of_device_id *of_id;
2807 struct gpio_descs *mode;
2808 u32 slave_offset, sliver_offset, slave_size;
2809 struct cpsw_common *cpsw;
2813 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2817 cpsw->dev = &pdev->dev;
2819 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2821 dev_err(&pdev->dev, "error allocating net_device\n");
2825 platform_set_drvdata(pdev, ndev);
2826 priv = netdev_priv(ndev);
2829 priv->dev = &ndev->dev;
2830 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2831 cpsw->rx_packet_max = max(rx_packet_max, 128);
2833 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2835 ret = PTR_ERR(mode);
2836 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2837 goto clean_ndev_ret;
2841 * This may be required here for child devices.
2843 pm_runtime_enable(&pdev->dev);
2845 /* Select default pin state */
2846 pinctrl_pm_select_default_state(&pdev->dev);
2848 /* Need to enable clocks with runtime PM api to access module
2851 ret = pm_runtime_get_sync(&pdev->dev);
2853 pm_runtime_put_noidle(&pdev->dev);
2854 goto clean_runtime_disable_ret;
2857 ret = cpsw_probe_dt(&cpsw->data, pdev);
2862 cpsw->rx_ch_num = 1;
2863 cpsw->tx_ch_num = 1;
2865 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2866 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2867 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2869 eth_random_addr(priv->mac_addr);
2870 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2873 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2875 cpsw->slaves = devm_kzalloc(&pdev->dev,
2876 sizeof(struct cpsw_slave) * data->slaves,
2878 if (!cpsw->slaves) {
2882 for (i = 0; i < data->slaves; i++)
2883 cpsw->slaves[i].slave_num = i;
2885 cpsw->slaves[0].ndev = ndev;
2886 priv->emac_port = 0;
2888 clk = devm_clk_get(&pdev->dev, "fck");
2890 dev_err(priv->dev, "fck is not found\n");
2894 cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2896 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2897 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2898 if (IS_ERR(ss_regs)) {
2899 ret = PTR_ERR(ss_regs);
2902 cpsw->regs = ss_regs;
2904 cpsw->version = readl(&cpsw->regs->id_ver);
2906 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2907 cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2908 if (IS_ERR(cpsw->wr_regs)) {
2909 ret = PTR_ERR(cpsw->wr_regs);
2913 memset(&dma_params, 0, sizeof(dma_params));
2914 memset(&ale_params, 0, sizeof(ale_params));
2916 switch (cpsw->version) {
2917 case CPSW_VERSION_1:
2918 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2919 cpts_regs = ss_regs + CPSW1_CPTS_OFFSET;
2920 cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
2921 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2922 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2923 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2924 slave_offset = CPSW1_SLAVE_OFFSET;
2925 slave_size = CPSW1_SLAVE_SIZE;
2926 sliver_offset = CPSW1_SLIVER_OFFSET;
2927 dma_params.desc_mem_phys = 0;
2929 case CPSW_VERSION_2:
2930 case CPSW_VERSION_3:
2931 case CPSW_VERSION_4:
2932 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2933 cpts_regs = ss_regs + CPSW2_CPTS_OFFSET;
2934 cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
2935 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2936 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2937 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2938 slave_offset = CPSW2_SLAVE_OFFSET;
2939 slave_size = CPSW2_SLAVE_SIZE;
2940 sliver_offset = CPSW2_SLIVER_OFFSET;
2941 dma_params.desc_mem_phys =
2942 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2945 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
2949 for (i = 0; i < cpsw->data.slaves; i++) {
2950 struct cpsw_slave *slave = &cpsw->slaves[i];
2952 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
2953 slave_offset += slave_size;
2954 sliver_offset += SLIVER_SIZE;
2957 dma_params.dev = &pdev->dev;
2958 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2959 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2960 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2961 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2962 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
2964 dma_params.num_chan = data->channels;
2965 dma_params.has_soft_reset = true;
2966 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2967 dma_params.desc_mem_size = data->bd_ram_size;
2968 dma_params.desc_align = 16;
2969 dma_params.has_ext_regs = true;
2970 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
2971 dma_params.bus_freq_mhz = cpsw->bus_freq_mhz;
2973 cpsw->dma = cpdma_ctlr_create(&dma_params);
2975 dev_err(priv->dev, "error initializing dma\n");
2980 cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
2981 cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
2982 if (WARN_ON(!cpsw->rxv[0].ch || !cpsw->txv[0].ch)) {
2983 dev_err(priv->dev, "error initializing dma channels\n");
2988 ale_params.dev = &ndev->dev;
2989 ale_params.ale_ageout = ale_ageout;
2990 ale_params.ale_entries = data->ale_entries;
2991 ale_params.ale_ports = data->slaves;
2993 cpsw->ale = cpsw_ale_create(&ale_params);
2995 dev_err(priv->dev, "error initializing ale engine\n");
3000 cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3001 if (IS_ERR(cpsw->cpts)) {
3002 ret = PTR_ERR(cpsw->cpts);
3006 ndev->irq = platform_get_irq(pdev, 1);
3007 if (ndev->irq < 0) {
3008 dev_err(priv->dev, "error getting irq resource\n");
3013 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
3015 pdev->id_entry = of_id->data;
3016 if (pdev->id_entry->driver_data)
3017 cpsw->quirk_irq = true;
3020 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3021 * MISC IRQs which are always kept disabled with this driver so
3022 * we will not request them.
3024 * If anyone wants to implement support for those, make sure to
3025 * first request and append them to irqs_table array.
3029 irq = platform_get_irq(pdev, 1);
3035 cpsw->irqs_table[0] = irq;
3036 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3037 0, dev_name(&pdev->dev), cpsw);
3039 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3044 irq = platform_get_irq(pdev, 2);
3050 cpsw->irqs_table[1] = irq;
3051 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3052 0, dev_name(&pdev->dev), cpsw);
3054 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3058 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3060 ndev->netdev_ops = &cpsw_netdev_ops;
3061 ndev->ethtool_ops = &cpsw_ethtool_ops;
3062 netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
3063 netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
3064 cpsw_split_res(ndev);
3066 /* register the network device */
3067 SET_NETDEV_DEV(ndev, &pdev->dev);
3068 ret = register_netdev(ndev);
3070 dev_err(priv->dev, "error registering net device\n");
3075 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
3076 &ss_res->start, ndev->irq);
3078 if (cpsw->data.dual_emac) {
3079 ret = cpsw_probe_dual_emac(priv);
3081 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3082 goto clean_unregister_netdev_ret;
3086 pm_runtime_put(&pdev->dev);
3090 clean_unregister_netdev_ret:
3091 unregister_netdev(ndev);
3093 cpsw_ale_destroy(cpsw->ale);
3095 cpdma_ctlr_destroy(cpsw->dma);
3097 cpsw_remove_dt(pdev);
3098 pm_runtime_put_sync(&pdev->dev);
3099 clean_runtime_disable_ret:
3100 pm_runtime_disable(&pdev->dev);
3102 free_netdev(priv->ndev);
3106 static int cpsw_remove(struct platform_device *pdev)
3108 struct net_device *ndev = platform_get_drvdata(pdev);
3109 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3112 ret = pm_runtime_get_sync(&pdev->dev);
3114 pm_runtime_put_noidle(&pdev->dev);
3118 if (cpsw->data.dual_emac)
3119 unregister_netdev(cpsw->slaves[1].ndev);
3120 unregister_netdev(ndev);
3122 cpts_release(cpsw->cpts);
3123 cpsw_ale_destroy(cpsw->ale);
3124 cpdma_ctlr_destroy(cpsw->dma);
3125 cpsw_remove_dt(pdev);
3126 pm_runtime_put_sync(&pdev->dev);
3127 pm_runtime_disable(&pdev->dev);
3128 if (cpsw->data.dual_emac)
3129 free_netdev(cpsw->slaves[1].ndev);
3134 #ifdef CONFIG_PM_SLEEP
3135 static int cpsw_suspend(struct device *dev)
3137 struct platform_device *pdev = to_platform_device(dev);
3138 struct net_device *ndev = platform_get_drvdata(pdev);
3139 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3141 if (cpsw->data.dual_emac) {
3144 for (i = 0; i < cpsw->data.slaves; i++) {
3145 if (netif_running(cpsw->slaves[i].ndev))
3146 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3149 if (netif_running(ndev))
3150 cpsw_ndo_stop(ndev);
3153 /* Select sleep pin state */
3154 pinctrl_pm_select_sleep_state(dev);
3159 static int cpsw_resume(struct device *dev)
3161 struct platform_device *pdev = to_platform_device(dev);
3162 struct net_device *ndev = platform_get_drvdata(pdev);
3163 struct cpsw_common *cpsw = netdev_priv(ndev);
3165 /* Select default pin state */
3166 pinctrl_pm_select_default_state(dev);
3168 /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3170 if (cpsw->data.dual_emac) {
3173 for (i = 0; i < cpsw->data.slaves; i++) {
3174 if (netif_running(cpsw->slaves[i].ndev))
3175 cpsw_ndo_open(cpsw->slaves[i].ndev);
3178 if (netif_running(ndev))
3179 cpsw_ndo_open(ndev);
3187 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3189 static struct platform_driver cpsw_driver = {
3193 .of_match_table = cpsw_of_mtable,
3195 .probe = cpsw_probe,
3196 .remove = cpsw_remove,
3199 module_platform_driver(cpsw_driver);
3201 MODULE_LICENSE("GPL");
3202 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3203 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3204 MODULE_DESCRIPTION("TI CPSW Ethernet driver");