2 * Copyright (c) 2004-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/module.h>
19 #include <linux/mmc/card.h>
20 #include <linux/mmc/mmc.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/sdio_func.h>
23 #include <linux/mmc/sdio_ids.h>
24 #include <linux/mmc/sdio.h>
25 #include <linux/mmc/sd.h>
34 struct sdio_func *func;
36 /* protects access to bus_req_freeq */
40 struct list_head bus_req_freeq;
42 /* available bus requests */
43 struct bus_request bus_req[BUS_REQUEST_MAX_NUM];
49 /* protects access to dma_buffer */
50 struct mutex dma_buffer_mutex;
52 /* scatter request list head */
53 struct list_head scat_req;
55 atomic_t irq_handling;
56 wait_queue_head_t irq_wq;
58 /* protects access to scat_req */
64 const struct sdio_device_id *id;
65 struct work_struct wr_async_work;
66 struct list_head wr_asyncq;
68 /* protects access to wr_asyncq */
69 spinlock_t wr_async_lock;
72 #define CMD53_ARG_READ 0
73 #define CMD53_ARG_WRITE 1
74 #define CMD53_ARG_BLOCK_BASIS 1
75 #define CMD53_ARG_FIXED_ADDRESS 0
76 #define CMD53_ARG_INCR_ADDRESS 1
78 static inline struct ath6kl_sdio *ath6kl_sdio_priv(struct ath6kl *ar)
84 * Macro to check if DMA buffer is WORD-aligned and DMA-able.
85 * Most host controllers assume the buffer is DMA'able and will
86 * bug-check otherwise (i.e. buffers on the stack). virt_addr_valid
87 * check fails on stack memory.
89 static inline bool buf_needs_bounce(u8 *buf)
91 return ((unsigned long) buf & 0x3) || !virt_addr_valid(buf);
94 static void ath6kl_sdio_set_mbox_info(struct ath6kl *ar)
96 struct ath6kl_mbox_info *mbox_info = &ar->mbox_info;
98 /* EP1 has an extended range */
99 mbox_info->htc_addr = HIF_MBOX_BASE_ADDR;
100 mbox_info->htc_ext_addr = HIF_MBOX0_EXT_BASE_ADDR;
101 mbox_info->htc_ext_sz = HIF_MBOX0_EXT_WIDTH;
102 mbox_info->block_size = HIF_MBOX_BLOCK_SIZE;
103 mbox_info->gmbox_addr = HIF_GMBOX_BASE_ADDR;
104 mbox_info->gmbox_sz = HIF_GMBOX_WIDTH;
107 static inline void ath6kl_sdio_set_cmd53_arg(u32 *arg, u8 rw, u8 func,
108 u8 mode, u8 opcode, u32 addr,
111 *arg = (((rw & 1) << 31) |
112 ((func & 0x7) << 28) |
114 ((opcode & 1) << 26) |
115 ((addr & 0x1FFFF) << 9) |
119 static inline void ath6kl_sdio_set_cmd52_arg(u32 *arg, u8 write, u8 raw,
120 unsigned int address,
125 *arg = ((write & 1) << 31) |
126 ((func & 0x7) << 28) |
129 ((address & 0x1FFFF) << 9) |
134 static int ath6kl_sdio_func0_cmd52_wr_byte(struct mmc_card *card,
135 unsigned int address,
138 struct mmc_command io_cmd;
140 memset(&io_cmd, 0, sizeof(io_cmd));
141 ath6kl_sdio_set_cmd52_arg(&io_cmd.arg, 1, 0, address, byte);
142 io_cmd.opcode = SD_IO_RW_DIRECT;
143 io_cmd.flags = MMC_RSP_R5 | MMC_CMD_AC;
145 return mmc_wait_for_cmd(card->host, &io_cmd, 0);
148 static int ath6kl_sdio_io(struct sdio_func *func, u32 request, u32 addr,
153 sdio_claim_host(func);
155 if (request & HIF_WRITE) {
156 /* FIXME: looks like ugly workaround for something */
157 if (addr >= HIF_MBOX_BASE_ADDR &&
158 addr <= HIF_MBOX_END_ADDR)
159 addr += (HIF_MBOX_WIDTH - len);
161 /* FIXME: this also looks like ugly workaround */
162 if (addr == HIF_MBOX0_EXT_BASE_ADDR)
163 addr += HIF_MBOX0_EXT_WIDTH - len;
165 if (request & HIF_FIXED_ADDRESS)
166 ret = sdio_writesb(func, addr, buf, len);
168 ret = sdio_memcpy_toio(func, addr, buf, len);
170 if (request & HIF_FIXED_ADDRESS)
171 ret = sdio_readsb(func, buf, addr, len);
173 ret = sdio_memcpy_fromio(func, buf, addr, len);
176 sdio_release_host(func);
178 ath6kl_dbg(ATH6KL_DBG_SDIO, "%s addr 0x%x%s buf 0x%p len %d\n",
179 request & HIF_WRITE ? "wr" : "rd", addr,
180 request & HIF_FIXED_ADDRESS ? " (fixed)" : "", buf, len);
181 ath6kl_dbg_dump(ATH6KL_DBG_SDIO_DUMP, NULL, "sdio ", buf, len);
183 trace_ath6kl_sdio(addr, request, buf, len);
188 static struct bus_request *ath6kl_sdio_alloc_busreq(struct ath6kl_sdio *ar_sdio)
190 struct bus_request *bus_req;
192 spin_lock_bh(&ar_sdio->lock);
194 if (list_empty(&ar_sdio->bus_req_freeq)) {
195 spin_unlock_bh(&ar_sdio->lock);
199 bus_req = list_first_entry(&ar_sdio->bus_req_freeq,
200 struct bus_request, list);
201 list_del(&bus_req->list);
203 spin_unlock_bh(&ar_sdio->lock);
204 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n",
210 static void ath6kl_sdio_free_bus_req(struct ath6kl_sdio *ar_sdio,
211 struct bus_request *bus_req)
213 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%s: bus request 0x%p\n",
216 spin_lock_bh(&ar_sdio->lock);
217 list_add_tail(&bus_req->list, &ar_sdio->bus_req_freeq);
218 spin_unlock_bh(&ar_sdio->lock);
221 static void ath6kl_sdio_setup_scat_data(struct hif_scatter_req *scat_req,
222 struct mmc_data *data)
224 struct scatterlist *sg;
227 data->blksz = HIF_MBOX_BLOCK_SIZE;
228 data->blocks = scat_req->len / HIF_MBOX_BLOCK_SIZE;
230 ath6kl_dbg(ATH6KL_DBG_SCATTER,
231 "hif-scatter: (%s) addr: 0x%X, (block len: %d, block count: %d) , (tot:%d,sg:%d)\n",
232 (scat_req->req & HIF_WRITE) ? "WR" : "RD", scat_req->addr,
233 data->blksz, data->blocks, scat_req->len,
234 scat_req->scat_entries);
236 data->flags = (scat_req->req & HIF_WRITE) ? MMC_DATA_WRITE :
239 /* fill SG entries */
240 sg = scat_req->sgentries;
241 sg_init_table(sg, scat_req->scat_entries);
243 /* assemble SG list */
244 for (i = 0; i < scat_req->scat_entries; i++, sg++) {
245 ath6kl_dbg(ATH6KL_DBG_SCATTER, "%d: addr:0x%p, len:%d\n",
246 i, scat_req->scat_list[i].buf,
247 scat_req->scat_list[i].len);
249 sg_set_buf(sg, scat_req->scat_list[i].buf,
250 scat_req->scat_list[i].len);
253 /* set scatter-gather table for request */
254 data->sg = scat_req->sgentries;
255 data->sg_len = scat_req->scat_entries;
258 static int ath6kl_sdio_scat_rw(struct ath6kl_sdio *ar_sdio,
259 struct bus_request *req)
261 struct mmc_request mmc_req;
262 struct mmc_command cmd;
263 struct mmc_data data;
264 struct hif_scatter_req *scat_req;
268 scat_req = req->scat_req;
270 if (scat_req->virt_scat) {
272 if (scat_req->req & HIF_BLOCK_BASIS)
273 len = round_down(len, HIF_MBOX_BLOCK_SIZE);
275 status = ath6kl_sdio_io(ar_sdio->func, scat_req->req,
276 scat_req->addr, scat_req->virt_dma_buf,
281 memset(&mmc_req, 0, sizeof(struct mmc_request));
282 memset(&cmd, 0, sizeof(struct mmc_command));
283 memset(&data, 0, sizeof(struct mmc_data));
285 ath6kl_sdio_setup_scat_data(scat_req, &data);
287 opcode = (scat_req->req & HIF_FIXED_ADDRESS) ?
288 CMD53_ARG_FIXED_ADDRESS : CMD53_ARG_INCR_ADDRESS;
290 rw = (scat_req->req & HIF_WRITE) ? CMD53_ARG_WRITE : CMD53_ARG_READ;
292 /* Fixup the address so that the last byte will fall on MBOX EOM */
293 if (scat_req->req & HIF_WRITE) {
294 if (scat_req->addr == HIF_MBOX_BASE_ADDR)
295 scat_req->addr += HIF_MBOX_WIDTH - scat_req->len;
297 /* Uses extended address range */
298 scat_req->addr += HIF_MBOX0_EXT_WIDTH - scat_req->len;
301 /* set command argument */
302 ath6kl_sdio_set_cmd53_arg(&cmd.arg, rw, ar_sdio->func->num,
303 CMD53_ARG_BLOCK_BASIS, opcode, scat_req->addr,
306 cmd.opcode = SD_IO_RW_EXTENDED;
307 cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
310 mmc_req.data = &data;
312 sdio_claim_host(ar_sdio->func);
314 mmc_set_data_timeout(&data, ar_sdio->func->card);
316 trace_ath6kl_sdio_scat(scat_req->addr,
319 scat_req->scat_entries,
320 scat_req->scat_list);
322 /* synchronous call to process request */
323 mmc_wait_for_req(ar_sdio->func->card->host, &mmc_req);
325 sdio_release_host(ar_sdio->func);
327 status = cmd.error ? cmd.error : data.error;
330 scat_req->status = status;
332 if (scat_req->status)
333 ath6kl_err("Scatter write request failed:%d\n",
336 if (scat_req->req & HIF_ASYNCHRONOUS)
337 scat_req->complete(ar_sdio->ar->htc_target, scat_req);
342 static int ath6kl_sdio_alloc_prep_scat_req(struct ath6kl_sdio *ar_sdio,
343 int n_scat_entry, int n_scat_req,
346 struct hif_scatter_req *s_req;
347 struct bus_request *bus_req;
348 int i, scat_req_sz, scat_list_sz, size;
351 scat_list_sz = (n_scat_entry - 1) * sizeof(struct hif_scatter_item);
352 scat_req_sz = sizeof(*s_req) + scat_list_sz;
355 size = sizeof(struct scatterlist) * n_scat_entry;
357 size = 2 * L1_CACHE_BYTES +
358 ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER;
360 for (i = 0; i < n_scat_req; i++) {
361 /* allocate the scatter request */
362 s_req = kzalloc(scat_req_sz, GFP_KERNEL);
367 virt_buf = kzalloc(size, GFP_KERNEL);
373 s_req->virt_dma_buf =
374 (u8 *)L1_CACHE_ALIGN((unsigned long)virt_buf);
376 /* allocate sglist */
377 s_req->sgentries = kzalloc(size, GFP_KERNEL);
379 if (!s_req->sgentries) {
385 /* allocate a bus request for this scatter request */
386 bus_req = ath6kl_sdio_alloc_busreq(ar_sdio);
388 kfree(s_req->sgentries);
389 kfree(s_req->virt_dma_buf);
394 /* assign the scatter request to this bus request */
395 bus_req->scat_req = s_req;
396 s_req->busrequest = bus_req;
398 s_req->virt_scat = virt_scat;
400 /* add it to the scatter pool */
401 hif_scatter_req_add(ar_sdio->ar, s_req);
407 static int ath6kl_sdio_read_write_sync(struct ath6kl *ar, u32 addr, u8 *buf,
408 u32 len, u32 request)
410 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
413 bool bounced = false;
415 if (request & HIF_BLOCK_BASIS)
416 len = round_down(len, HIF_MBOX_BLOCK_SIZE);
418 if (buf_needs_bounce(buf)) {
419 if (!ar_sdio->dma_buffer)
421 mutex_lock(&ar_sdio->dma_buffer_mutex);
422 tbuf = ar_sdio->dma_buffer;
424 if (request & HIF_WRITE)
425 memcpy(tbuf, buf, len);
431 ret = ath6kl_sdio_io(ar_sdio->func, request, addr, tbuf, len);
432 if ((request & HIF_READ) && bounced)
433 memcpy(buf, tbuf, len);
436 mutex_unlock(&ar_sdio->dma_buffer_mutex);
441 static void __ath6kl_sdio_write_async(struct ath6kl_sdio *ar_sdio,
442 struct bus_request *req)
445 ath6kl_sdio_scat_rw(ar_sdio, req);
450 status = ath6kl_sdio_read_write_sync(ar_sdio->ar, req->address,
451 req->buffer, req->length,
453 context = req->packet;
454 ath6kl_sdio_free_bus_req(ar_sdio, req);
455 ath6kl_hif_rw_comp_handler(context, status);
459 static void ath6kl_sdio_write_async_work(struct work_struct *work)
461 struct ath6kl_sdio *ar_sdio;
462 struct bus_request *req, *tmp_req;
464 ar_sdio = container_of(work, struct ath6kl_sdio, wr_async_work);
466 spin_lock_bh(&ar_sdio->wr_async_lock);
467 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
468 list_del(&req->list);
469 spin_unlock_bh(&ar_sdio->wr_async_lock);
470 __ath6kl_sdio_write_async(ar_sdio, req);
471 spin_lock_bh(&ar_sdio->wr_async_lock);
473 spin_unlock_bh(&ar_sdio->wr_async_lock);
476 static void ath6kl_sdio_irq_handler(struct sdio_func *func)
479 struct ath6kl_sdio *ar_sdio;
481 ath6kl_dbg(ATH6KL_DBG_SDIO, "irq\n");
483 ar_sdio = sdio_get_drvdata(func);
484 atomic_set(&ar_sdio->irq_handling, 1);
486 * Release the host during interrups so we can pick it back up when
487 * we process commands.
489 sdio_release_host(ar_sdio->func);
491 status = ath6kl_hif_intr_bh_handler(ar_sdio->ar);
492 sdio_claim_host(ar_sdio->func);
494 atomic_set(&ar_sdio->irq_handling, 0);
495 wake_up(&ar_sdio->irq_wq);
497 WARN_ON(status && status != -ECANCELED);
500 static int ath6kl_sdio_power_on(struct ath6kl *ar)
502 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
503 struct sdio_func *func = ar_sdio->func;
506 if (!ar_sdio->is_disabled)
509 ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power on\n");
511 sdio_claim_host(func);
513 ret = sdio_enable_func(func);
515 ath6kl_err("Unable to enable sdio func: %d)\n", ret);
516 sdio_release_host(func);
520 sdio_release_host(func);
523 * Wait for hardware to initialise. It should take a lot less than
524 * 10 ms but let's be conservative here.
528 ar_sdio->is_disabled = false;
533 static int ath6kl_sdio_power_off(struct ath6kl *ar)
535 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
538 if (ar_sdio->is_disabled)
541 ath6kl_dbg(ATH6KL_DBG_BOOT, "sdio power off\n");
543 /* Disable the card */
544 sdio_claim_host(ar_sdio->func);
545 ret = sdio_disable_func(ar_sdio->func);
546 sdio_release_host(ar_sdio->func);
551 ar_sdio->is_disabled = true;
556 static int ath6kl_sdio_write_async(struct ath6kl *ar, u32 address, u8 *buffer,
557 u32 length, u32 request,
558 struct htc_packet *packet)
560 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
561 struct bus_request *bus_req;
563 bus_req = ath6kl_sdio_alloc_busreq(ar_sdio);
565 if (WARN_ON_ONCE(!bus_req))
568 bus_req->address = address;
569 bus_req->buffer = buffer;
570 bus_req->length = length;
571 bus_req->request = request;
572 bus_req->packet = packet;
574 spin_lock_bh(&ar_sdio->wr_async_lock);
575 list_add_tail(&bus_req->list, &ar_sdio->wr_asyncq);
576 spin_unlock_bh(&ar_sdio->wr_async_lock);
577 queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work);
582 static void ath6kl_sdio_irq_enable(struct ath6kl *ar)
584 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
587 sdio_claim_host(ar_sdio->func);
589 /* Register the isr */
590 ret = sdio_claim_irq(ar_sdio->func, ath6kl_sdio_irq_handler);
592 ath6kl_err("Failed to claim sdio irq: %d\n", ret);
594 sdio_release_host(ar_sdio->func);
597 static bool ath6kl_sdio_is_on_irq(struct ath6kl *ar)
599 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
601 return !atomic_read(&ar_sdio->irq_handling);
604 static void ath6kl_sdio_irq_disable(struct ath6kl *ar)
606 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
609 sdio_claim_host(ar_sdio->func);
611 if (atomic_read(&ar_sdio->irq_handling)) {
612 sdio_release_host(ar_sdio->func);
614 ret = wait_event_interruptible(ar_sdio->irq_wq,
615 ath6kl_sdio_is_on_irq(ar));
619 sdio_claim_host(ar_sdio->func);
622 ret = sdio_release_irq(ar_sdio->func);
624 ath6kl_err("Failed to release sdio irq: %d\n", ret);
626 sdio_release_host(ar_sdio->func);
629 static struct hif_scatter_req *ath6kl_sdio_scatter_req_get(struct ath6kl *ar)
631 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
632 struct hif_scatter_req *node = NULL;
634 spin_lock_bh(&ar_sdio->scat_lock);
636 if (!list_empty(&ar_sdio->scat_req)) {
637 node = list_first_entry(&ar_sdio->scat_req,
638 struct hif_scatter_req, list);
639 list_del(&node->list);
641 node->scat_q_depth = get_queue_depth(&ar_sdio->scat_req);
644 spin_unlock_bh(&ar_sdio->scat_lock);
649 static void ath6kl_sdio_scatter_req_add(struct ath6kl *ar,
650 struct hif_scatter_req *s_req)
652 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
654 spin_lock_bh(&ar_sdio->scat_lock);
656 list_add_tail(&s_req->list, &ar_sdio->scat_req);
658 spin_unlock_bh(&ar_sdio->scat_lock);
662 /* scatter gather read write request */
663 static int ath6kl_sdio_async_rw_scatter(struct ath6kl *ar,
664 struct hif_scatter_req *scat_req)
666 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
667 u32 request = scat_req->req;
673 ath6kl_dbg(ATH6KL_DBG_SCATTER,
674 "hif-scatter: total len: %d scatter entries: %d\n",
675 scat_req->len, scat_req->scat_entries);
677 if (request & HIF_SYNCHRONOUS)
678 status = ath6kl_sdio_scat_rw(ar_sdio, scat_req->busrequest);
680 spin_lock_bh(&ar_sdio->wr_async_lock);
681 list_add_tail(&scat_req->busrequest->list, &ar_sdio->wr_asyncq);
682 spin_unlock_bh(&ar_sdio->wr_async_lock);
683 queue_work(ar->ath6kl_wq, &ar_sdio->wr_async_work);
689 /* clean up scatter support */
690 static void ath6kl_sdio_cleanup_scatter(struct ath6kl *ar)
692 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
693 struct hif_scatter_req *s_req, *tmp_req;
695 /* empty the free list */
696 spin_lock_bh(&ar_sdio->scat_lock);
697 list_for_each_entry_safe(s_req, tmp_req, &ar_sdio->scat_req, list) {
698 list_del(&s_req->list);
699 spin_unlock_bh(&ar_sdio->scat_lock);
702 * FIXME: should we also call completion handler with
703 * ath6kl_hif_rw_comp_handler() with status -ECANCELED so
704 * that the packet is properly freed?
706 if (s_req->busrequest)
707 ath6kl_sdio_free_bus_req(ar_sdio, s_req->busrequest);
708 kfree(s_req->virt_dma_buf);
709 kfree(s_req->sgentries);
712 spin_lock_bh(&ar_sdio->scat_lock);
714 spin_unlock_bh(&ar_sdio->scat_lock);
717 /* setup of HIF scatter resources */
718 static int ath6kl_sdio_enable_scatter(struct ath6kl *ar)
720 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
721 struct htc_target *target = ar->htc_target;
723 bool virt_scat = false;
725 if (ar_sdio->scatter_enabled)
728 ar_sdio->scatter_enabled = true;
730 /* check if host supports scatter and it meets our requirements */
731 if (ar_sdio->func->card->host->max_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
732 ath6kl_err("host only supports scatter of :%d entries, need: %d\n",
733 ar_sdio->func->card->host->max_segs,
734 MAX_SCATTER_ENTRIES_PER_REQ);
739 ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio,
740 MAX_SCATTER_ENTRIES_PER_REQ,
741 MAX_SCATTER_REQUESTS, virt_scat);
744 ath6kl_dbg(ATH6KL_DBG_BOOT,
745 "hif-scatter enabled requests %d entries %d\n",
746 MAX_SCATTER_REQUESTS,
747 MAX_SCATTER_ENTRIES_PER_REQ);
749 target->max_scat_entries = MAX_SCATTER_ENTRIES_PER_REQ;
750 target->max_xfer_szper_scatreq =
751 MAX_SCATTER_REQ_TRANSFER_SIZE;
753 ath6kl_sdio_cleanup_scatter(ar);
754 ath6kl_warn("hif scatter resource setup failed, trying virtual scatter method\n");
758 if (virt_scat || ret) {
759 ret = ath6kl_sdio_alloc_prep_scat_req(ar_sdio,
760 ATH6KL_SCATTER_ENTRIES_PER_REQ,
761 ATH6KL_SCATTER_REQS, virt_scat);
764 ath6kl_err("failed to alloc virtual scatter resources !\n");
765 ath6kl_sdio_cleanup_scatter(ar);
769 ath6kl_dbg(ATH6KL_DBG_BOOT,
770 "virtual scatter enabled requests %d entries %d\n",
771 ATH6KL_SCATTER_REQS, ATH6KL_SCATTER_ENTRIES_PER_REQ);
773 target->max_scat_entries = ATH6KL_SCATTER_ENTRIES_PER_REQ;
774 target->max_xfer_szper_scatreq =
775 ATH6KL_MAX_TRANSFER_SIZE_PER_SCATTER;
781 static int ath6kl_sdio_config(struct ath6kl *ar)
783 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
784 struct sdio_func *func = ar_sdio->func;
787 sdio_claim_host(func);
789 if ((ar_sdio->id->device & MANUFACTURER_ID_ATH6KL_BASE_MASK) >=
790 MANUFACTURER_ID_AR6003_BASE) {
791 /* enable 4-bit ASYNC interrupt on AR6003 or later */
792 ret = ath6kl_sdio_func0_cmd52_wr_byte(func->card,
793 CCCR_SDIO_IRQ_MODE_REG,
794 SDIO_IRQ_MODE_ASYNC_4BIT_IRQ);
796 ath6kl_err("Failed to enable 4-bit async irq mode %d\n",
801 ath6kl_dbg(ATH6KL_DBG_BOOT, "4-bit async irq mode enabled\n");
804 /* give us some time to enable, in ms */
805 func->enable_timeout = 100;
807 ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
809 ath6kl_err("Set sdio block size %d failed: %d)\n",
810 HIF_MBOX_BLOCK_SIZE, ret);
815 sdio_release_host(func);
820 static int ath6kl_set_sdio_pm_caps(struct ath6kl *ar)
822 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
823 struct sdio_func *func = ar_sdio->func;
827 flags = sdio_get_host_pm_caps(func);
829 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio suspend pm_caps 0x%x\n", flags);
831 if (!(flags & MMC_PM_WAKE_SDIO_IRQ) ||
832 !(flags & MMC_PM_KEEP_POWER))
835 ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
837 ath6kl_err("set sdio keep pwr flag failed: %d\n", ret);
841 /* sdio irq wakes up host */
842 ret = sdio_set_host_pm_flags(func, MMC_PM_WAKE_SDIO_IRQ);
844 ath6kl_err("set sdio wake irq flag failed: %d\n", ret);
849 static int ath6kl_sdio_suspend(struct ath6kl *ar, struct cfg80211_wowlan *wow)
851 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
852 struct sdio_func *func = ar_sdio->func;
854 bool try_deepsleep = false;
857 if (ar->suspend_mode == WLAN_POWER_STATE_WOW ||
858 (!ar->suspend_mode && wow)) {
860 ret = ath6kl_set_sdio_pm_caps(ar);
864 ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_WOW, wow);
865 if (ret && ret != -ENOTCONN)
866 ath6kl_err("wow suspend failed: %d\n", ret);
869 (!ar->wow_suspend_mode ||
870 ar->wow_suspend_mode == WLAN_POWER_STATE_DEEP_SLEEP))
871 try_deepsleep = true;
873 ar->wow_suspend_mode == WLAN_POWER_STATE_CUT_PWR)
879 if (ar->suspend_mode == WLAN_POWER_STATE_DEEP_SLEEP ||
880 !ar->suspend_mode || try_deepsleep) {
882 flags = sdio_get_host_pm_caps(func);
883 if (!(flags & MMC_PM_KEEP_POWER))
886 ret = sdio_set_host_pm_flags(func, MMC_PM_KEEP_POWER);
891 * Workaround to support Deep Sleep with MSM, set the host pm
892 * flag as MMC_PM_WAKE_SDIO_IRQ to allow SDCC deiver to disable
893 * the sdc2_clock and internally allows MSM to enter
894 * TCXO shutdown properly.
896 if ((flags & MMC_PM_WAKE_SDIO_IRQ)) {
897 ret = sdio_set_host_pm_flags(func,
898 MMC_PM_WAKE_SDIO_IRQ);
903 ret = ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_DEEPSLEEP,
912 if (func->card && func->card->host)
913 func->card->host->pm_flags &= ~MMC_PM_KEEP_POWER;
915 return ath6kl_cfg80211_suspend(ar, ATH6KL_CFG_SUSPEND_CUTPOWER, NULL);
918 static int ath6kl_sdio_resume(struct ath6kl *ar)
921 case ATH6KL_STATE_OFF:
922 case ATH6KL_STATE_CUTPOWER:
923 ath6kl_dbg(ATH6KL_DBG_SUSPEND,
924 "sdio resume configuring sdio\n");
926 /* need to set sdio settings after power is cut from sdio */
927 ath6kl_sdio_config(ar);
930 case ATH6KL_STATE_ON:
933 case ATH6KL_STATE_DEEPSLEEP:
936 case ATH6KL_STATE_WOW:
939 case ATH6KL_STATE_SUSPENDING:
942 case ATH6KL_STATE_RESUMING:
945 case ATH6KL_STATE_RECOVERY:
949 ath6kl_cfg80211_resume(ar);
954 /* set the window address register (using 4-byte register access ). */
955 static int ath6kl_set_addrwin_reg(struct ath6kl *ar, u32 reg_addr, u32 addr)
962 * Write bytes 1,2,3 of the register to set the upper address bytes,
963 * the LSB is written last to initiate the access cycle
966 for (i = 1; i <= 3; i++) {
968 * Fill the buffer with the address byte value we want to
971 memset(addr_val, ((u8 *)&addr)[i], 4);
974 * Hit each byte of the register address with a 4-byte
975 * write operation to the same address, this is a harmless
978 status = ath6kl_sdio_read_write_sync(ar, reg_addr + i, addr_val,
979 4, HIF_WR_SYNC_BYTE_FIX);
985 ath6kl_err("%s: failed to write initial bytes of 0x%x to window reg: 0x%X\n",
986 __func__, addr, reg_addr);
991 * Write the address register again, this time write the whole
992 * 4-byte value. The effect here is that the LSB write causes the
993 * cycle to start, the extra 3 byte write to bytes 1,2,3 has no
994 * effect since we are writing the same values again
996 status = ath6kl_sdio_read_write_sync(ar, reg_addr, (u8 *)(&addr),
997 4, HIF_WR_SYNC_BYTE_INC);
1000 ath6kl_err("%s: failed to write 0x%x to window reg: 0x%X\n",
1001 __func__, addr, reg_addr);
1008 static int ath6kl_sdio_diag_read32(struct ath6kl *ar, u32 address, u32 *data)
1012 /* set window register to start read cycle */
1013 status = ath6kl_set_addrwin_reg(ar, WINDOW_READ_ADDR_ADDRESS,
1020 status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS,
1021 (u8 *)data, sizeof(u32), HIF_RD_SYNC_BYTE_INC);
1023 ath6kl_err("%s: failed to read from window data addr\n",
1031 static int ath6kl_sdio_diag_write32(struct ath6kl *ar, u32 address,
1035 u32 val = (__force u32) data;
1037 /* set write data */
1038 status = ath6kl_sdio_read_write_sync(ar, WINDOW_DATA_ADDRESS,
1039 (u8 *) &val, sizeof(u32), HIF_WR_SYNC_BYTE_INC);
1041 ath6kl_err("%s: failed to write 0x%x to window data addr\n",
1046 /* set window register, which starts the write cycle */
1047 return ath6kl_set_addrwin_reg(ar, WINDOW_WRITE_ADDR_ADDRESS,
1051 static int ath6kl_sdio_bmi_credits(struct ath6kl *ar)
1054 unsigned long timeout;
1057 ar->bmi.cmd_credits = 0;
1059 /* Read the counter register to get the command credits */
1060 addr = COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
1062 timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT);
1063 while (time_before(jiffies, timeout) && !ar->bmi.cmd_credits) {
1066 * Hit the credit counter with a 4-byte access, the first byte
1067 * read will hit the counter and cause a decrement, while the
1068 * remaining 3 bytes has no effect. The rationale behind this
1069 * is to make all HIF accesses 4-byte aligned.
1071 ret = ath6kl_sdio_read_write_sync(ar, addr,
1072 (u8 *)&ar->bmi.cmd_credits, 4,
1073 HIF_RD_SYNC_BYTE_INC);
1075 ath6kl_err("Unable to decrement the command credit count register: %d\n",
1080 /* The counter is only 8 bits.
1081 * Ignore anything in the upper 3 bytes
1083 ar->bmi.cmd_credits &= 0xFF;
1086 if (!ar->bmi.cmd_credits) {
1087 ath6kl_err("bmi communication timeout\n");
1094 static int ath6kl_bmi_get_rx_lkahd(struct ath6kl *ar)
1096 unsigned long timeout;
1100 timeout = jiffies + msecs_to_jiffies(BMI_COMMUNICATION_TIMEOUT);
1101 while ((time_before(jiffies, timeout)) && !rx_word) {
1102 ret = ath6kl_sdio_read_write_sync(ar,
1103 RX_LOOKAHEAD_VALID_ADDRESS,
1104 (u8 *)&rx_word, sizeof(rx_word),
1105 HIF_RD_SYNC_BYTE_INC);
1107 ath6kl_err("unable to read RX_LOOKAHEAD_VALID\n");
1111 /* all we really want is one bit */
1112 rx_word &= (1 << ENDPOINT1);
1116 ath6kl_err("bmi_recv_buf FIFO empty\n");
1123 static int ath6kl_sdio_bmi_write(struct ath6kl *ar, u8 *buf, u32 len)
1128 ret = ath6kl_sdio_bmi_credits(ar);
1132 addr = ar->mbox_info.htc_addr;
1134 ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len,
1135 HIF_WR_SYNC_BYTE_INC);
1137 ath6kl_err("unable to send the bmi data to the device\n");
1144 static int ath6kl_sdio_bmi_read(struct ath6kl *ar, u8 *buf, u32 len)
1150 * During normal bootup, small reads may be required.
1151 * Rather than issue an HIF Read and then wait as the Target
1152 * adds successive bytes to the FIFO, we wait here until
1153 * we know that response data is available.
1155 * This allows us to cleanly timeout on an unexpected
1156 * Target failure rather than risk problems at the HIF level.
1157 * In particular, this avoids SDIO timeouts and possibly garbage
1158 * data on some host controllers. And on an interconnect
1159 * such as Compact Flash (as well as some SDIO masters) which
1160 * does not provide any indication on data timeout, it avoids
1161 * a potential hang or garbage response.
1163 * Synchronization is more difficult for reads larger than the
1164 * size of the MBOX FIFO (128B), because the Target is unable
1165 * to push the 129th byte of data until AFTER the Host posts an
1166 * HIF Read and removes some FIFO data. So for large reads the
1167 * Host proceeds to post an HIF Read BEFORE all the data is
1168 * actually available to read. Fortunately, large BMI reads do
1169 * not occur in practice -- they're supported for debug/development.
1171 * So Host/Target BMI synchronization is divided into these cases:
1172 * CASE 1: length < 4
1175 * CASE 2: 4 <= length <= 128
1176 * Wait for first 4 bytes to be in FIFO
1177 * If CONSERVATIVE_BMI_READ is enabled, also wait for
1178 * a BMI command credit, which indicates that the ENTIRE
1179 * response is available in the the FIFO
1181 * CASE 3: length > 128
1182 * Wait for the first 4 bytes to be in FIFO
1184 * For most uses, a small timeout should be sufficient and we will
1185 * usually see a response quickly; but there may be some unusual
1186 * (debug) cases of BMI_EXECUTE where we want an larger timeout.
1187 * For now, we use an unbounded busy loop while waiting for
1190 * If BMI_EXECUTE ever needs to support longer-latency execution,
1191 * especially in production, this code needs to be enhanced to sleep
1192 * and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently
1193 * a function of Host processor speed.
1195 if (len >= 4) { /* NB: Currently, always true */
1196 ret = ath6kl_bmi_get_rx_lkahd(ar);
1201 addr = ar->mbox_info.htc_addr;
1202 ret = ath6kl_sdio_read_write_sync(ar, addr, buf, len,
1203 HIF_RD_SYNC_BYTE_INC);
1205 ath6kl_err("Unable to read the bmi data from the device: %d\n",
1213 static void ath6kl_sdio_stop(struct ath6kl *ar)
1215 struct ath6kl_sdio *ar_sdio = ath6kl_sdio_priv(ar);
1216 struct bus_request *req, *tmp_req;
1219 /* FIXME: make sure that wq is not queued again */
1221 cancel_work_sync(&ar_sdio->wr_async_work);
1223 spin_lock_bh(&ar_sdio->wr_async_lock);
1225 list_for_each_entry_safe(req, tmp_req, &ar_sdio->wr_asyncq, list) {
1226 list_del(&req->list);
1228 if (req->scat_req) {
1229 /* this is a scatter gather request */
1230 req->scat_req->status = -ECANCELED;
1231 req->scat_req->complete(ar_sdio->ar->htc_target,
1234 context = req->packet;
1235 ath6kl_sdio_free_bus_req(ar_sdio, req);
1236 ath6kl_hif_rw_comp_handler(context, -ECANCELED);
1240 spin_unlock_bh(&ar_sdio->wr_async_lock);
1242 WARN_ON(get_queue_depth(&ar_sdio->scat_req) != 4);
1245 static const struct ath6kl_hif_ops ath6kl_sdio_ops = {
1246 .read_write_sync = ath6kl_sdio_read_write_sync,
1247 .write_async = ath6kl_sdio_write_async,
1248 .irq_enable = ath6kl_sdio_irq_enable,
1249 .irq_disable = ath6kl_sdio_irq_disable,
1250 .scatter_req_get = ath6kl_sdio_scatter_req_get,
1251 .scatter_req_add = ath6kl_sdio_scatter_req_add,
1252 .enable_scatter = ath6kl_sdio_enable_scatter,
1253 .scat_req_rw = ath6kl_sdio_async_rw_scatter,
1254 .cleanup_scatter = ath6kl_sdio_cleanup_scatter,
1255 .suspend = ath6kl_sdio_suspend,
1256 .resume = ath6kl_sdio_resume,
1257 .diag_read32 = ath6kl_sdio_diag_read32,
1258 .diag_write32 = ath6kl_sdio_diag_write32,
1259 .bmi_read = ath6kl_sdio_bmi_read,
1260 .bmi_write = ath6kl_sdio_bmi_write,
1261 .power_on = ath6kl_sdio_power_on,
1262 .power_off = ath6kl_sdio_power_off,
1263 .stop = ath6kl_sdio_stop,
1266 #ifdef CONFIG_PM_SLEEP
1269 * Empty handlers so that mmc subsystem doesn't remove us entirely during
1270 * suspend. We instead follow cfg80211 suspend/resume handlers.
1272 static int ath6kl_sdio_pm_suspend(struct device *device)
1274 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm suspend\n");
1279 static int ath6kl_sdio_pm_resume(struct device *device)
1281 ath6kl_dbg(ATH6KL_DBG_SUSPEND, "sdio pm resume\n");
1286 static SIMPLE_DEV_PM_OPS(ath6kl_sdio_pm_ops, ath6kl_sdio_pm_suspend,
1287 ath6kl_sdio_pm_resume);
1289 #define ATH6KL_SDIO_PM_OPS (&ath6kl_sdio_pm_ops)
1293 #define ATH6KL_SDIO_PM_OPS NULL
1295 #endif /* CONFIG_PM_SLEEP */
1297 static int ath6kl_sdio_probe(struct sdio_func *func,
1298 const struct sdio_device_id *id)
1301 struct ath6kl_sdio *ar_sdio;
1305 ath6kl_dbg(ATH6KL_DBG_BOOT,
1306 "sdio new func %d vendor 0x%x device 0x%x block 0x%x/0x%x\n",
1307 func->num, func->vendor, func->device,
1308 func->max_blksize, func->cur_blksize);
1310 ar_sdio = kzalloc(sizeof(struct ath6kl_sdio), GFP_KERNEL);
1314 ar_sdio->dma_buffer = kzalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL);
1315 if (!ar_sdio->dma_buffer) {
1320 ar_sdio->func = func;
1321 sdio_set_drvdata(func, ar_sdio);
1324 ar_sdio->is_disabled = true;
1326 spin_lock_init(&ar_sdio->lock);
1327 spin_lock_init(&ar_sdio->scat_lock);
1328 spin_lock_init(&ar_sdio->wr_async_lock);
1329 mutex_init(&ar_sdio->dma_buffer_mutex);
1331 INIT_LIST_HEAD(&ar_sdio->scat_req);
1332 INIT_LIST_HEAD(&ar_sdio->bus_req_freeq);
1333 INIT_LIST_HEAD(&ar_sdio->wr_asyncq);
1335 INIT_WORK(&ar_sdio->wr_async_work, ath6kl_sdio_write_async_work);
1337 init_waitqueue_head(&ar_sdio->irq_wq);
1339 for (count = 0; count < BUS_REQUEST_MAX_NUM; count++)
1340 ath6kl_sdio_free_bus_req(ar_sdio, &ar_sdio->bus_req[count]);
1342 ar = ath6kl_core_create(&ar_sdio->func->dev);
1344 ath6kl_err("Failed to alloc ath6kl core\n");
1350 ar->hif_type = ATH6KL_HIF_TYPE_SDIO;
1351 ar->hif_priv = ar_sdio;
1352 ar->hif_ops = &ath6kl_sdio_ops;
1353 ar->bmi.max_data_size = 256;
1355 ath6kl_sdio_set_mbox_info(ar);
1357 ret = ath6kl_sdio_config(ar);
1359 ath6kl_err("Failed to config sdio: %d\n", ret);
1360 goto err_core_alloc;
1363 ret = ath6kl_core_init(ar, ATH6KL_HTC_TYPE_MBOX);
1365 ath6kl_err("Failed to init ath6kl core\n");
1366 goto err_core_alloc;
1372 ath6kl_core_destroy(ar_sdio->ar);
1374 kfree(ar_sdio->dma_buffer);
1381 static void ath6kl_sdio_remove(struct sdio_func *func)
1383 struct ath6kl_sdio *ar_sdio;
1385 ath6kl_dbg(ATH6KL_DBG_BOOT,
1386 "sdio removed func %d vendor 0x%x device 0x%x\n",
1387 func->num, func->vendor, func->device);
1389 ar_sdio = sdio_get_drvdata(func);
1391 ath6kl_stop_txrx(ar_sdio->ar);
1392 cancel_work_sync(&ar_sdio->wr_async_work);
1394 ath6kl_core_cleanup(ar_sdio->ar);
1395 ath6kl_core_destroy(ar_sdio->ar);
1397 kfree(ar_sdio->dma_buffer);
1401 static const struct sdio_device_id ath6kl_sdio_devices[] = {
1402 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0))},
1403 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))},
1404 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x0))},
1405 {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x1))},
1409 MODULE_DEVICE_TABLE(sdio, ath6kl_sdio_devices);
1411 static struct sdio_driver ath6kl_sdio_driver = {
1412 .name = "ath6kl_sdio",
1413 .id_table = ath6kl_sdio_devices,
1414 .probe = ath6kl_sdio_probe,
1415 .remove = ath6kl_sdio_remove,
1416 .drv.pm = ATH6KL_SDIO_PM_OPS,
1419 static int __init ath6kl_sdio_init(void)
1423 ret = sdio_register_driver(&ath6kl_sdio_driver);
1425 ath6kl_err("sdio driver registration failed: %d\n", ret);
1430 static void __exit ath6kl_sdio_exit(void)
1432 sdio_unregister_driver(&ath6kl_sdio_driver);
1435 module_init(ath6kl_sdio_init);
1436 module_exit(ath6kl_sdio_exit);
1438 MODULE_AUTHOR("Atheros Communications, Inc.");
1439 MODULE_DESCRIPTION("Driver support for Atheros AR600x SDIO devices");
1440 MODULE_LICENSE("Dual BSD/GPL");
1442 MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_OTP_FILE);
1443 MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_FIRMWARE_FILE);
1444 MODULE_FIRMWARE(AR6003_HW_2_0_FW_DIR "/" AR6003_HW_2_0_PATCH_FILE);
1445 MODULE_FIRMWARE(AR6003_HW_2_0_BOARD_DATA_FILE);
1446 MODULE_FIRMWARE(AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE);
1447 MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_OTP_FILE);
1448 MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_FIRMWARE_FILE);
1449 MODULE_FIRMWARE(AR6003_HW_2_1_1_FW_DIR "/" AR6003_HW_2_1_1_PATCH_FILE);
1450 MODULE_FIRMWARE(AR6003_HW_2_1_1_BOARD_DATA_FILE);
1451 MODULE_FIRMWARE(AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE);
1452 MODULE_FIRMWARE(AR6004_HW_1_0_FW_DIR "/" AR6004_HW_1_0_FIRMWARE_FILE);
1453 MODULE_FIRMWARE(AR6004_HW_1_0_BOARD_DATA_FILE);
1454 MODULE_FIRMWARE(AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE);
1455 MODULE_FIRMWARE(AR6004_HW_1_1_FW_DIR "/" AR6004_HW_1_1_FIRMWARE_FILE);
1456 MODULE_FIRMWARE(AR6004_HW_1_1_BOARD_DATA_FILE);
1457 MODULE_FIRMWARE(AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE);
1458 MODULE_FIRMWARE(AR6004_HW_1_2_FW_DIR "/" AR6004_HW_1_2_FIRMWARE_FILE);
1459 MODULE_FIRMWARE(AR6004_HW_1_2_BOARD_DATA_FILE);
1460 MODULE_FIRMWARE(AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE);
1461 MODULE_FIRMWARE(AR6004_HW_1_3_FW_DIR "/" AR6004_HW_1_3_FIRMWARE_FILE);
1462 MODULE_FIRMWARE(AR6004_HW_1_3_BOARD_DATA_FILE);
1463 MODULE_FIRMWARE(AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE);