1 /******************************************************************************
3 * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *****************************************************************************/
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/skbuff.h>
33 #include <linux/netdevice.h>
34 #include <linux/wireless.h>
35 #include <net/mac80211.h>
36 #include <linux/etherdevice.h>
37 #include <asm/unaligned.h>
39 #include "iwl-eeprom.h"
44 #include "iwl-helpers.h"
45 #include "iwl-agn-led.h"
46 #include "iwl-5000-hw.h"
47 #include "iwl-6000-hw.h"
49 /* Highest firmware API version supported */
50 #define IWL5000_UCODE_API_MAX 2
51 #define IWL5150_UCODE_API_MAX 2
53 /* Lowest firmware API version supported */
54 #define IWL5000_UCODE_API_MIN 1
55 #define IWL5150_UCODE_API_MIN 1
57 #define IWL5000_FW_PRE "iwlwifi-5000-"
58 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
59 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
61 #define IWL5150_FW_PRE "iwlwifi-5150-"
62 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
63 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
65 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
75 int iwl5000_apm_init(struct iwl_priv *priv)
79 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
80 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
82 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
83 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
84 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
86 /* Set FH wait threshold to maximum (HW error during stress W/A) */
87 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
89 /* enable HAP INTA to move device L1a -> L0s */
90 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
91 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
93 if (priv->cfg->need_pll_cfg)
94 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
96 /* set "initialization complete" bit to move adapter
97 * D0U* --> D0A* state */
98 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
100 /* wait for clock stabilization */
101 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
102 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
103 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
105 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
110 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
114 /* disable L1-Active */
115 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
116 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
121 int iwl5000_apm_reset(struct iwl_priv *priv)
125 iwl_apm_stop_master(priv);
127 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
132 /* FIXME: put here L1A -L0S w/a */
134 if (priv->cfg->need_pll_cfg)
135 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
137 /* set "initialization complete" bit to move adapter
138 * D0U* --> D0A* state */
139 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
141 /* wait for clock stabilization */
142 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
143 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
144 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
146 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
151 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
155 /* disable L1-Active */
156 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
157 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
164 /* NIC configuration for 5000 series */
165 void iwl5000_nic_config(struct iwl_priv *priv)
171 spin_lock_irqsave(&priv->lock, flags);
173 lctl = iwl_pcie_link_ctl(priv);
176 /* L1-ASPM is enabled by BIOS */
177 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
178 /* L1-APSM enabled: disable L0S */
179 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
181 /* L1-ASPM disabled: enable L0S */
182 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
184 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
186 /* write radio config values to register */
187 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
188 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
189 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
190 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
191 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
193 /* set CSR_HW_CONFIG_REG for uCode use */
194 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
195 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
196 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
198 /* W/A : NIC is stuck in a reset state after Early PCIe power off
199 * (PCIe power is lost before PERST# is asserted),
200 * causing ME FW to lose ownership and not being able to obtain it back.
202 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
203 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
204 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
207 spin_unlock_irqrestore(&priv->lock, flags);
214 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
218 if ((address & INDIRECT_ADDRESS) == 0)
221 switch (address & INDIRECT_TYPE_MSK) {
223 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
225 case INDIRECT_GENERAL:
226 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
228 case INDIRECT_REGULATORY:
229 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
231 case INDIRECT_CALIBRATION:
232 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
234 case INDIRECT_PROCESS_ADJST:
235 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
237 case INDIRECT_OTHERS:
238 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
241 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
242 address & INDIRECT_TYPE_MSK);
246 /* translate the offset from words to byte */
247 return (address & ADDRESS_MSK) + (offset << 1);
250 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
252 struct iwl_eeprom_calib_hdr {
258 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
259 EEPROM_5000_CALIB_ALL);
264 static void iwl5000_gain_computation(struct iwl_priv *priv,
265 u32 average_noise[NUM_RX_CHAINS],
266 u16 min_average_noise_antenna_i,
267 u32 min_average_noise,
272 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
275 * Find Gain Code for the chains based on "default chain"
277 for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
278 if ((data->disconn_array[i])) {
279 data->delta_gain_code[i] = 0;
282 delta_g = (1000 * ((s32)average_noise[0] -
283 (s32)average_noise[i])) / 1500;
284 /* bound gain by 2 bits value max, 3rd bit is sign */
285 data->delta_gain_code[i] =
286 min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
289 /* set negative sign */
290 data->delta_gain_code[i] |= (1 << 2);
293 IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d ANT_C = %d\n",
294 data->delta_gain_code[1], data->delta_gain_code[2]);
296 if (!data->radio_write) {
297 struct iwl_calib_chain_noise_gain_cmd cmd;
299 memset(&cmd, 0, sizeof(cmd));
301 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
302 cmd.hdr.first_group = 0;
303 cmd.hdr.groups_num = 1;
304 cmd.hdr.data_valid = 1;
305 cmd.delta_gain_1 = data->delta_gain_code[1];
306 cmd.delta_gain_2 = data->delta_gain_code[2];
307 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
308 sizeof(cmd), &cmd, NULL);
310 data->radio_write = 1;
311 data->state = IWL_CHAIN_NOISE_CALIBRATED;
314 data->chain_noise_a = 0;
315 data->chain_noise_b = 0;
316 data->chain_noise_c = 0;
317 data->chain_signal_a = 0;
318 data->chain_signal_b = 0;
319 data->chain_signal_c = 0;
320 data->beacon_count = 0;
323 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
325 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
328 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
329 struct iwl_calib_chain_noise_reset_cmd cmd;
330 memset(&cmd, 0, sizeof(cmd));
332 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
333 cmd.hdr.first_group = 0;
334 cmd.hdr.groups_num = 1;
335 cmd.hdr.data_valid = 1;
336 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
340 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
341 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
342 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
346 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
349 if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
350 (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
351 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
353 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
356 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
358 .max_nrg_cck = 0, /* not used, set to 0 */
359 .auto_corr_min_ofdm = 90,
360 .auto_corr_min_ofdm_mrc = 170,
361 .auto_corr_min_ofdm_x1 = 120,
362 .auto_corr_min_ofdm_mrc_x1 = 240,
364 .auto_corr_max_ofdm = 120,
365 .auto_corr_max_ofdm_mrc = 210,
366 .auto_corr_max_ofdm_x1 = 155,
367 .auto_corr_max_ofdm_mrc_x1 = 290,
369 .auto_corr_min_cck = 125,
370 .auto_corr_max_cck = 200,
371 .auto_corr_min_cck_mrc = 170,
372 .auto_corr_max_cck_mrc = 400,
377 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
379 .max_nrg_cck = 0, /* not used, set to 0 */
380 .auto_corr_min_ofdm = 90,
381 .auto_corr_min_ofdm_mrc = 170,
382 .auto_corr_min_ofdm_x1 = 105,
383 .auto_corr_min_ofdm_mrc_x1 = 220,
385 .auto_corr_max_ofdm = 120,
386 .auto_corr_max_ofdm_mrc = 210,
387 /* max = min for performance bug in 5150 DSP */
388 .auto_corr_max_ofdm_x1 = 105,
389 .auto_corr_max_ofdm_mrc_x1 = 220,
391 .auto_corr_min_cck = 125,
392 .auto_corr_max_cck = 200,
393 .auto_corr_min_cck_mrc = 170,
394 .auto_corr_max_cck_mrc = 400,
399 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
402 u32 address = eeprom_indirect_address(priv, offset);
403 BUG_ON(address >= priv->cfg->eeprom_size);
404 return &priv->eeprom[address];
407 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
409 const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
410 s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
411 iwl_temp_calib_to_offset(priv);
413 priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
416 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
419 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
425 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
427 struct iwl_calib_xtal_freq_cmd cmd;
428 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
430 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
431 cmd.hdr.first_group = 0;
432 cmd.hdr.groups_num = 1;
433 cmd.hdr.data_valid = 1;
434 cmd.cap_pin1 = (u8)xtal_calib[0];
435 cmd.cap_pin2 = (u8)xtal_calib[1];
436 return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
437 (u8 *)&cmd, sizeof(cmd));
440 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
442 struct iwl_calib_cfg_cmd calib_cfg_cmd;
443 struct iwl_host_cmd cmd = {
444 .id = CALIBRATION_CFG_CMD,
445 .len = sizeof(struct iwl_calib_cfg_cmd),
446 .data = &calib_cfg_cmd,
449 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
450 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
451 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
452 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
453 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
455 return iwl_send_cmd(priv, &cmd);
458 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
459 struct iwl_rx_mem_buffer *rxb)
461 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
462 struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
463 int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
466 /* reduce the size of the length field itself */
469 /* Define the order in which the results will be sent to the runtime
470 * uCode. iwl_send_calib_results sends them in a row according to their
471 * index. We sort them here */
472 switch (hdr->op_code) {
473 case IWL_PHY_CALIBRATE_DC_CMD:
474 index = IWL_CALIB_DC;
476 case IWL_PHY_CALIBRATE_LO_CMD:
477 index = IWL_CALIB_LO;
479 case IWL_PHY_CALIBRATE_TX_IQ_CMD:
480 index = IWL_CALIB_TX_IQ;
482 case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
483 index = IWL_CALIB_TX_IQ_PERD;
485 case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
486 index = IWL_CALIB_BASE_BAND;
489 IWL_ERR(priv, "Unknown calibration notification %d\n",
493 iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
496 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
497 struct iwl_rx_mem_buffer *rxb)
499 IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
500 queue_work(priv->workqueue, &priv->restart);
506 static int iwl5000_load_section(struct iwl_priv *priv,
507 struct fw_desc *image,
510 dma_addr_t phy_addr = image->p_addr;
511 u32 byte_cnt = image->len;
513 iwl_write_direct32(priv,
514 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
515 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
517 iwl_write_direct32(priv,
518 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
520 iwl_write_direct32(priv,
521 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
522 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
524 iwl_write_direct32(priv,
525 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
526 (iwl_get_dma_hi_addr(phy_addr)
527 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
529 iwl_write_direct32(priv,
530 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
531 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
532 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
533 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
535 iwl_write_direct32(priv,
536 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
537 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
538 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
539 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
544 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
545 struct fw_desc *inst_image,
546 struct fw_desc *data_image)
550 ret = iwl5000_load_section(priv, inst_image,
551 IWL50_RTC_INST_LOWER_BOUND);
555 IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
556 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
557 priv->ucode_write_complete, 5 * HZ);
558 if (ret == -ERESTARTSYS) {
559 IWL_ERR(priv, "Could not load the INST uCode section due "
564 IWL_ERR(priv, "Could not load the INST uCode section\n");
568 priv->ucode_write_complete = 0;
570 ret = iwl5000_load_section(
571 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
575 IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
577 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
578 priv->ucode_write_complete, 5 * HZ);
579 if (ret == -ERESTARTSYS) {
580 IWL_ERR(priv, "Could not load the INST uCode section due "
584 IWL_ERR(priv, "Could not load the DATA uCode section\n");
589 priv->ucode_write_complete = 0;
594 int iwl5000_load_ucode(struct iwl_priv *priv)
598 /* check whether init ucode should be loaded, or rather runtime ucode */
599 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
600 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
601 ret = iwl5000_load_given_ucode(priv,
602 &priv->ucode_init, &priv->ucode_init_data);
604 IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
605 priv->ucode_type = UCODE_INIT;
608 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
609 "Loading runtime ucode...\n");
610 ret = iwl5000_load_given_ucode(priv,
611 &priv->ucode_code, &priv->ucode_data);
613 IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
614 priv->ucode_type = UCODE_RT;
621 void iwl5000_init_alive_start(struct iwl_priv *priv)
625 /* Check alive response for "valid" sign from uCode */
626 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
627 /* We had an error bringing up the hardware, so take it
628 * all the way back down so we can try again */
629 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
633 /* initialize uCode was loaded... verify inst image.
634 * This is a paranoid check, because we would not have gotten the
635 * "initialize" alive if code weren't properly loaded. */
636 if (iwl_verify_ucode(priv)) {
637 /* Runtime instruction load was bad;
638 * take it all the way back down so we can try again */
639 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
643 iwl_clear_stations_table(priv);
644 ret = priv->cfg->ops->lib->alive_notify(priv);
647 "Could not complete ALIVE transition: %d\n", ret);
651 iwl5000_send_calib_cfg(priv);
655 /* real restart (first load init_ucode) */
656 queue_work(priv->workqueue, &priv->restart);
659 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
660 int txq_id, u32 index)
662 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
663 (index & 0xff) | (txq_id << 8));
664 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
667 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
668 struct iwl_tx_queue *txq,
669 int tx_fifo_id, int scd_retry)
671 int txq_id = txq->q.id;
672 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
674 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
675 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
676 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
677 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
678 IWL50_SCD_QUEUE_STTS_REG_MSK);
680 txq->sched_retry = scd_retry;
682 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
683 active ? "Activate" : "Deactivate",
684 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
687 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
689 struct iwl_wimax_coex_cmd coex_cmd;
691 memset(&coex_cmd, 0, sizeof(coex_cmd));
693 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
694 sizeof(coex_cmd), &coex_cmd);
697 int iwl5000_alive_notify(struct iwl_priv *priv)
704 spin_lock_irqsave(&priv->lock, flags);
706 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
707 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
708 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
710 iwl_write_targ_mem(priv, a, 0);
711 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
713 iwl_write_targ_mem(priv, a, 0);
714 for (; a < priv->scd_base_addr +
715 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
716 iwl_write_targ_mem(priv, a, 0);
718 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
719 priv->scd_bc_tbls.dma >> 10);
721 /* Enable DMA channel */
722 for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
723 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
724 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
725 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
727 /* Update FH chicken bits */
728 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
729 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
730 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
732 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
733 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
734 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
736 /* initiate the queues */
737 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
738 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
739 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
740 iwl_write_targ_mem(priv, priv->scd_base_addr +
741 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
742 iwl_write_targ_mem(priv, priv->scd_base_addr +
743 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
746 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
747 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
749 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
750 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
753 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
754 IWL_MASK(0, priv->hw_params.max_txq_num));
756 /* Activate all Tx DMA/FIFO channels */
757 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
759 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
761 /* map qos queues to fifos one-to-one */
762 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
763 int ac = iwl5000_default_queue_to_tx_fifo[i];
764 iwl_txq_ctx_activate(priv, i);
765 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
767 /* TODO - need to initialize those FIFOs inside the loop above,
768 * not only mark them as active */
769 iwl_txq_ctx_activate(priv, 4);
770 iwl_txq_ctx_activate(priv, 7);
771 iwl_txq_ctx_activate(priv, 8);
772 iwl_txq_ctx_activate(priv, 9);
774 spin_unlock_irqrestore(&priv->lock, flags);
777 iwl5000_send_wimax_coex(priv);
779 iwl5000_set_Xtal_calib(priv);
780 iwl_send_calib_results(priv);
785 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
787 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
788 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
790 "invalid queues_num, should be between %d and %d\n",
791 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
795 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
796 priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
797 priv->hw_params.scd_bc_tbls_size =
798 IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
799 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
800 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
801 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
803 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
804 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
806 priv->hw_params.max_bsm_size = 0;
807 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_2GHZ) |
808 BIT(IEEE80211_BAND_5GHZ);
809 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
811 priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
812 priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
813 priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
814 priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
816 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
817 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
819 /* Set initial sensitivity parameters */
820 /* Set initial calibration set */
821 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
822 case CSR_HW_REV_TYPE_5150:
823 priv->hw_params.sens = &iwl5150_sensitivity;
824 priv->hw_params.calib_init_cfg =
827 BIT(IWL_CALIB_TX_IQ) |
828 BIT(IWL_CALIB_BASE_BAND);
832 priv->hw_params.sens = &iwl5000_sensitivity;
833 priv->hw_params.calib_init_cfg =
834 BIT(IWL_CALIB_XTAL) |
836 BIT(IWL_CALIB_TX_IQ) |
837 BIT(IWL_CALIB_TX_IQ_PERD) |
838 BIT(IWL_CALIB_BASE_BAND);
846 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
848 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
849 struct iwl_tx_queue *txq,
852 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
853 int write_ptr = txq->q.write_ptr;
854 int txq_id = txq->q.id;
857 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
860 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
862 if (txq_id != IWL_CMD_QUEUE_NUM) {
863 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
864 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
866 switch (sec_ctl & TX_CMD_SEC_MSK) {
870 case TX_CMD_SEC_TKIP:
874 len += WEP_IV_LEN + WEP_ICV_LEN;
879 bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
881 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
883 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
885 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
888 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
889 struct iwl_tx_queue *txq)
891 struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
892 int txq_id = txq->q.id;
893 int read_ptr = txq->q.read_ptr;
897 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
899 if (txq_id != IWL_CMD_QUEUE_NUM)
900 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
902 bc_ent = cpu_to_le16(1 | (sta_id << 12));
903 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
905 if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
907 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
910 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
917 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
919 tbl_dw_addr = priv->scd_base_addr +
920 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
922 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
925 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
927 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
929 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
933 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
935 /* Simply stop the queue, but don't change any configuration;
936 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
938 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
939 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
940 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
943 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
944 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
949 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
950 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
952 "queue number out of range: %d, must be %d to %d\n",
953 txq_id, IWL50_FIRST_AMPDU_QUEUE,
954 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
958 ra_tid = BUILD_RAxTID(sta_id, tid);
960 /* Modify device's station table to Tx this TID */
961 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
963 spin_lock_irqsave(&priv->lock, flags);
965 /* Stop this Tx queue before configuring it */
966 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
968 /* Map receiver-address / traffic-ID to this queue */
969 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
971 /* Set this queue as a chain-building queue */
972 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
974 /* enable aggregations for the queue */
975 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
977 /* Place first TFD at index corresponding to start sequence number.
978 * Assumes that ssn_idx is valid (!= 0xFFF) */
979 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
980 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
981 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
983 /* Set up Tx window size and frame limit for this queue */
984 iwl_write_targ_mem(priv, priv->scd_base_addr +
985 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
988 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
989 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
991 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
992 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
994 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
996 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
997 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
999 spin_unlock_irqrestore(&priv->lock, flags);
1004 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1005 u16 ssn_idx, u8 tx_fifo)
1007 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1008 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1010 "queue number out of range: %d, must be %d to %d\n",
1011 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1012 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1016 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1018 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1020 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1021 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1022 /* supposes that ssn_idx is valid (!= 0xFFF) */
1023 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1025 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1026 iwl_txq_ctx_deactivate(priv, txq_id);
1027 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1032 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1034 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1035 struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
1036 memcpy(addsta, cmd, size);
1037 /* resrved in 5000 */
1038 addsta->rate_n_flags = cpu_to_le16(0);
1044 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1045 * must be called under priv->lock and mac access
1047 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1049 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1053 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1055 return le32_to_cpup((__le32 *)&tx_resp->status +
1056 tx_resp->frame_count) & MAX_SN;
1059 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1060 struct iwl_ht_agg *agg,
1061 struct iwl5000_tx_resp *tx_resp,
1062 int txq_id, u16 start_idx)
1065 struct agg_tx_status *frame_status = &tx_resp->status;
1066 struct ieee80211_tx_info *info = NULL;
1067 struct ieee80211_hdr *hdr = NULL;
1068 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1072 if (agg->wait_for_ba)
1073 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1075 agg->frame_count = tx_resp->frame_count;
1076 agg->start_idx = start_idx;
1077 agg->rate_n_flags = rate_n_flags;
1080 /* # frames attempted by Tx command */
1081 if (agg->frame_count == 1) {
1082 /* Only one frame was attempted; no block-ack will arrive */
1083 status = le16_to_cpu(frame_status[0].status);
1086 /* FIXME: code repetition */
1087 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1088 agg->frame_count, agg->start_idx, idx);
1090 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1091 info->status.rates[0].count = tx_resp->failure_frame + 1;
1092 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1093 info->flags |= iwl_is_tx_success(status) ?
1094 IEEE80211_TX_STAT_ACK : 0;
1095 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1097 /* FIXME: code repetition end */
1099 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1100 status & 0xff, tx_resp->failure_frame);
1101 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1103 agg->wait_for_ba = 0;
1105 /* Two or more frames were attempted; expect block-ack */
1107 int start = agg->start_idx;
1109 /* Construct bit-map of pending frames within Tx window */
1110 for (i = 0; i < agg->frame_count; i++) {
1112 status = le16_to_cpu(frame_status[i].status);
1113 seq = le16_to_cpu(frame_status[i].sequence);
1114 idx = SEQ_TO_INDEX(seq);
1115 txq_id = SEQ_TO_QUEUE(seq);
1117 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1118 AGG_TX_STATE_ABORT_MSK))
1121 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1122 agg->frame_count, txq_id, idx);
1124 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1127 "BUG_ON idx doesn't point to valid skb"
1128 " idx=%d, txq_id=%d\n", idx, txq_id);
1132 sc = le16_to_cpu(hdr->seq_ctrl);
1133 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1135 "BUG_ON idx doesn't match seq control"
1136 " idx=%d, seq_idx=%d, seq=%d\n",
1142 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1143 i, idx, SEQ_TO_SN(sc));
1147 sh = (start - idx) + 0xff;
1148 bitmap = bitmap << sh;
1151 } else if (sh < -64)
1152 sh = 0xff - (start - idx);
1156 bitmap = bitmap << sh;
1159 bitmap |= 1ULL << sh;
1160 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1161 start, (unsigned long long)bitmap);
1164 agg->bitmap = bitmap;
1165 agg->start_idx = start;
1166 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1167 agg->frame_count, agg->start_idx,
1168 (unsigned long long)agg->bitmap);
1171 agg->wait_for_ba = 1;
1176 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1177 struct iwl_rx_mem_buffer *rxb)
1179 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1180 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1181 int txq_id = SEQ_TO_QUEUE(sequence);
1182 int index = SEQ_TO_INDEX(sequence);
1183 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1184 struct ieee80211_tx_info *info;
1185 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1186 u32 status = le16_to_cpu(tx_resp->status.status);
1191 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1192 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1193 "is out of range [0-%d] %d %d\n", txq_id,
1194 index, txq->q.n_bd, txq->q.write_ptr,
1199 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1200 memset(&info->status, 0, sizeof(info->status));
1202 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1203 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1205 if (txq->sched_retry) {
1206 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1207 struct iwl_ht_agg *agg = NULL;
1209 agg = &priv->stations[sta_id].tid[tid].agg;
1211 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1213 /* check if BAR is needed */
1214 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1215 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1217 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1218 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1219 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1220 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1221 scd_ssn , index, txq_id, txq->swq_id);
1223 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1224 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1226 if (priv->mac80211_registered &&
1227 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1228 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1229 if (agg->state == IWL_AGG_OFF)
1230 iwl_wake_queue(priv, txq_id);
1232 iwl_wake_queue(priv, txq->swq_id);
1236 BUG_ON(txq_id != txq->swq_id);
1238 info->status.rates[0].count = tx_resp->failure_frame + 1;
1239 info->flags |= iwl_is_tx_success(status) ?
1240 IEEE80211_TX_STAT_ACK : 0;
1241 iwl_hwrate_to_tx_control(priv,
1242 le32_to_cpu(tx_resp->rate_n_flags),
1245 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1246 "0x%x retries %d\n",
1248 iwl_get_tx_fail_reason(status), status,
1249 le32_to_cpu(tx_resp->rate_n_flags),
1250 tx_resp->failure_frame);
1252 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1253 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1254 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1256 if (priv->mac80211_registered &&
1257 (iwl_queue_space(&txq->q) > txq->q.low_mark))
1258 iwl_wake_queue(priv, txq_id);
1261 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1262 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1264 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1265 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
1268 /* Currently 5000 is the superset of everything */
1269 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1274 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1276 /* in 5000 the tx power calibration is done in uCode */
1277 priv->disable_tx_power_cal = 1;
1280 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1282 /* init calibration handlers */
1283 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1284 iwl5000_rx_calib_result;
1285 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1286 iwl5000_rx_calib_complete;
1287 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1291 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1293 return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1294 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1297 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1300 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1301 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1302 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1304 if ((rxon1->flags == rxon2->flags) &&
1305 (rxon1->filter_flags == rxon2->filter_flags) &&
1306 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1307 (rxon1->ofdm_ht_single_stream_basic_rates ==
1308 rxon2->ofdm_ht_single_stream_basic_rates) &&
1309 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1310 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1311 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1312 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1313 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1314 (rxon1->rx_chain == rxon2->rx_chain) &&
1315 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1316 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1320 rxon_assoc.flags = priv->staging_rxon.flags;
1321 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1322 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1323 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1324 rxon_assoc.reserved1 = 0;
1325 rxon_assoc.reserved2 = 0;
1326 rxon_assoc.reserved3 = 0;
1327 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1328 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1329 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1330 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1331 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1332 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1333 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1334 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1336 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1337 sizeof(rxon_assoc), &rxon_assoc, NULL);
1343 int iwl5000_send_tx_power(struct iwl_priv *priv)
1345 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1348 /* half dBm need to multiply */
1349 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1350 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1351 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1353 if (IWL_UCODE_API(priv->ucode_ver) == 1)
1354 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1356 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1358 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1359 sizeof(tx_power_cmd), &tx_power_cmd,
1363 void iwl5000_temperature(struct iwl_priv *priv)
1365 /* store temperature from statistics (in Celsius) */
1366 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1367 iwl_tt_handler(priv);
1370 static void iwl5150_temperature(struct iwl_priv *priv)
1373 s32 offset = iwl_temp_calib_to_offset(priv);
1375 vt = le32_to_cpu(priv->statistics.general.temperature);
1376 vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1377 /* now vt hold the temperature in Kelvin */
1378 priv->temperature = KELVIN_TO_CELSIUS(vt);
1379 iwl_tt_handler(priv);
1382 /* Calc max signal level (dBm) among 3 possible receivers */
1383 int iwl5000_calc_rssi(struct iwl_priv *priv,
1384 struct iwl_rx_phy_res *rx_resp)
1386 /* data from PHY/DSP regarding signal strength, etc.,
1387 * contents are always there, not configurable by host
1389 struct iwl5000_non_cfg_phy *ncphy =
1390 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1391 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1394 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1395 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1397 /* Find max rssi among 3 possible receivers.
1398 * These values are measured by the digital signal processor (DSP).
1399 * They should stay fairly constant even as the signal strength varies,
1400 * if the radio's automatic gain control (AGC) is working right.
1401 * AGC value (see below) will provide the "interesting" info.
1403 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1404 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1405 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1406 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1407 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1409 max_rssi = max_t(u32, rssi_a, rssi_b);
1410 max_rssi = max_t(u32, max_rssi, rssi_c);
1412 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1413 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1415 /* dBm = max_rssi dB - agc dB - constant.
1416 * Higher AGC (higher radio gain) means lower signal. */
1417 return max_rssi - agc - IWL49_RSSI_OFFSET;
1420 static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1422 struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1423 .valid = cpu_to_le32(valid_tx_ant),
1426 if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1427 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1428 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1429 sizeof(struct iwl_tx_ant_config_cmd),
1432 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1438 #define IWL5000_UCODE_GET(item) \
1439 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1443 return le32_to_cpu(ucode->u.v1.item); \
1444 return le32_to_cpu(ucode->u.v2.item); \
1447 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1450 return UCODE_HEADER_SIZE(1);
1451 return UCODE_HEADER_SIZE(2);
1454 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1459 return le32_to_cpu(ucode->u.v2.build);
1462 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1466 return (u8 *) ucode->u.v1.data;
1467 return (u8 *) ucode->u.v2.data;
1470 IWL5000_UCODE_GET(inst_size);
1471 IWL5000_UCODE_GET(data_size);
1472 IWL5000_UCODE_GET(init_size);
1473 IWL5000_UCODE_GET(init_data_size);
1474 IWL5000_UCODE_GET(boot_size);
1476 struct iwl_hcmd_ops iwl5000_hcmd = {
1477 .rxon_assoc = iwl5000_send_rxon_assoc,
1478 .commit_rxon = iwl_commit_rxon,
1479 .set_rxon_chain = iwl_set_rxon_chain,
1480 .set_tx_ant = iwl5000_send_tx_ant_config,
1483 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1484 .get_hcmd_size = iwl5000_get_hcmd_size,
1485 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1486 .gain_computation = iwl5000_gain_computation,
1487 .chain_noise_reset = iwl5000_chain_noise_reset,
1488 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1489 .calc_rssi = iwl5000_calc_rssi,
1492 struct iwl_ucode_ops iwl5000_ucode = {
1493 .get_header_size = iwl5000_ucode_get_header_size,
1494 .get_build = iwl5000_ucode_get_build,
1495 .get_inst_size = iwl5000_ucode_get_inst_size,
1496 .get_data_size = iwl5000_ucode_get_data_size,
1497 .get_init_size = iwl5000_ucode_get_init_size,
1498 .get_init_data_size = iwl5000_ucode_get_init_data_size,
1499 .get_boot_size = iwl5000_ucode_get_boot_size,
1500 .get_data = iwl5000_ucode_get_data,
1503 struct iwl_lib_ops iwl5000_lib = {
1504 .set_hw_params = iwl5000_hw_set_hw_params,
1505 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1506 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1507 .txq_set_sched = iwl5000_txq_set_sched,
1508 .txq_agg_enable = iwl5000_txq_agg_enable,
1509 .txq_agg_disable = iwl5000_txq_agg_disable,
1510 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1511 .txq_free_tfd = iwl_hw_txq_free_tfd,
1512 .txq_init = iwl_hw_tx_queue_init,
1513 .rx_handler_setup = iwl5000_rx_handler_setup,
1514 .setup_deferred_work = iwl5000_setup_deferred_work,
1515 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1516 .dump_nic_event_log = iwl_dump_nic_event_log,
1517 .dump_nic_error_log = iwl_dump_nic_error_log,
1518 .load_ucode = iwl5000_load_ucode,
1519 .init_alive_start = iwl5000_init_alive_start,
1520 .alive_notify = iwl5000_alive_notify,
1521 .send_tx_power = iwl5000_send_tx_power,
1522 .update_chain_flags = iwl_update_chain_flags,
1524 .init = iwl5000_apm_init,
1525 .reset = iwl5000_apm_reset,
1526 .stop = iwl_apm_stop,
1527 .config = iwl5000_nic_config,
1528 .set_pwr_src = iwl_set_pwr_src,
1531 .regulatory_bands = {
1532 EEPROM_5000_REG_BAND_1_CHANNELS,
1533 EEPROM_5000_REG_BAND_2_CHANNELS,
1534 EEPROM_5000_REG_BAND_3_CHANNELS,
1535 EEPROM_5000_REG_BAND_4_CHANNELS,
1536 EEPROM_5000_REG_BAND_5_CHANNELS,
1537 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1538 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1540 .verify_signature = iwlcore_eeprom_verify_signature,
1541 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1542 .release_semaphore = iwlcore_eeprom_release_semaphore,
1543 .calib_version = iwl5000_eeprom_calib_version,
1544 .query_addr = iwl5000_eeprom_query_addr,
1546 .post_associate = iwl_post_associate,
1548 .config_ap = iwl_config_ap,
1550 .temperature = iwl5000_temperature,
1551 .set_ct_kill = iwl5000_set_ct_threshold,
1555 static struct iwl_lib_ops iwl5150_lib = {
1556 .set_hw_params = iwl5000_hw_set_hw_params,
1557 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1558 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1559 .txq_set_sched = iwl5000_txq_set_sched,
1560 .txq_agg_enable = iwl5000_txq_agg_enable,
1561 .txq_agg_disable = iwl5000_txq_agg_disable,
1562 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1563 .txq_free_tfd = iwl_hw_txq_free_tfd,
1564 .txq_init = iwl_hw_tx_queue_init,
1565 .rx_handler_setup = iwl5000_rx_handler_setup,
1566 .setup_deferred_work = iwl5000_setup_deferred_work,
1567 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1568 .dump_nic_event_log = iwl_dump_nic_event_log,
1569 .dump_nic_error_log = iwl_dump_nic_error_log,
1570 .load_ucode = iwl5000_load_ucode,
1571 .init_alive_start = iwl5000_init_alive_start,
1572 .alive_notify = iwl5000_alive_notify,
1573 .send_tx_power = iwl5000_send_tx_power,
1574 .update_chain_flags = iwl_update_chain_flags,
1576 .init = iwl5000_apm_init,
1577 .reset = iwl5000_apm_reset,
1578 .stop = iwl_apm_stop,
1579 .config = iwl5000_nic_config,
1580 .set_pwr_src = iwl_set_pwr_src,
1583 .regulatory_bands = {
1584 EEPROM_5000_REG_BAND_1_CHANNELS,
1585 EEPROM_5000_REG_BAND_2_CHANNELS,
1586 EEPROM_5000_REG_BAND_3_CHANNELS,
1587 EEPROM_5000_REG_BAND_4_CHANNELS,
1588 EEPROM_5000_REG_BAND_5_CHANNELS,
1589 EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1590 EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1592 .verify_signature = iwlcore_eeprom_verify_signature,
1593 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1594 .release_semaphore = iwlcore_eeprom_release_semaphore,
1595 .calib_version = iwl5000_eeprom_calib_version,
1596 .query_addr = iwl5000_eeprom_query_addr,
1598 .post_associate = iwl_post_associate,
1600 .config_ap = iwl_config_ap,
1602 .temperature = iwl5150_temperature,
1603 .set_ct_kill = iwl5150_set_ct_threshold,
1607 static struct iwl_ops iwl5000_ops = {
1608 .ucode = &iwl5000_ucode,
1609 .lib = &iwl5000_lib,
1610 .hcmd = &iwl5000_hcmd,
1611 .utils = &iwl5000_hcmd_utils,
1612 .led = &iwlagn_led_ops,
1615 static struct iwl_ops iwl5150_ops = {
1616 .ucode = &iwl5000_ucode,
1617 .lib = &iwl5150_lib,
1618 .hcmd = &iwl5000_hcmd,
1619 .utils = &iwl5000_hcmd_utils,
1620 .led = &iwlagn_led_ops,
1623 struct iwl_mod_params iwl50_mod_params = {
1624 .num_of_queues = IWL50_NUM_QUEUES,
1625 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1628 /* the rest are 0 by default */
1632 struct iwl_cfg iwl5300_agn_cfg = {
1634 .fw_name_pre = IWL5000_FW_PRE,
1635 .ucode_api_max = IWL5000_UCODE_API_MAX,
1636 .ucode_api_min = IWL5000_UCODE_API_MIN,
1637 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1638 .ops = &iwl5000_ops,
1639 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1640 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1641 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1642 .mod_params = &iwl50_mod_params,
1643 .valid_tx_ant = ANT_ABC,
1644 .valid_rx_ant = ANT_ABC,
1645 .need_pll_cfg = true,
1646 .ht_greenfield_support = true,
1647 .led_compensation = 51,
1648 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1651 struct iwl_cfg iwl5100_bg_cfg = {
1653 .fw_name_pre = IWL5000_FW_PRE,
1654 .ucode_api_max = IWL5000_UCODE_API_MAX,
1655 .ucode_api_min = IWL5000_UCODE_API_MIN,
1657 .ops = &iwl5000_ops,
1658 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1659 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1660 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1661 .mod_params = &iwl50_mod_params,
1662 .valid_tx_ant = ANT_B,
1663 .valid_rx_ant = ANT_AB,
1664 .need_pll_cfg = true,
1665 .ht_greenfield_support = true,
1666 .led_compensation = 51,
1667 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1670 struct iwl_cfg iwl5100_abg_cfg = {
1672 .fw_name_pre = IWL5000_FW_PRE,
1673 .ucode_api_max = IWL5000_UCODE_API_MAX,
1674 .ucode_api_min = IWL5000_UCODE_API_MIN,
1675 .sku = IWL_SKU_A|IWL_SKU_G,
1676 .ops = &iwl5000_ops,
1677 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1678 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1679 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1680 .mod_params = &iwl50_mod_params,
1681 .valid_tx_ant = ANT_B,
1682 .valid_rx_ant = ANT_AB,
1683 .need_pll_cfg = true,
1684 .ht_greenfield_support = true,
1685 .led_compensation = 51,
1686 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1689 struct iwl_cfg iwl5100_agn_cfg = {
1691 .fw_name_pre = IWL5000_FW_PRE,
1692 .ucode_api_max = IWL5000_UCODE_API_MAX,
1693 .ucode_api_min = IWL5000_UCODE_API_MIN,
1694 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1695 .ops = &iwl5000_ops,
1696 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1697 .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1698 .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1699 .mod_params = &iwl50_mod_params,
1700 .valid_tx_ant = ANT_B,
1701 .valid_rx_ant = ANT_AB,
1702 .need_pll_cfg = true,
1703 .ht_greenfield_support = true,
1704 .led_compensation = 51,
1705 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1708 struct iwl_cfg iwl5350_agn_cfg = {
1710 .fw_name_pre = IWL5000_FW_PRE,
1711 .ucode_api_max = IWL5000_UCODE_API_MAX,
1712 .ucode_api_min = IWL5000_UCODE_API_MIN,
1713 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1714 .ops = &iwl5000_ops,
1715 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1716 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1717 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1718 .mod_params = &iwl50_mod_params,
1719 .valid_tx_ant = ANT_ABC,
1720 .valid_rx_ant = ANT_ABC,
1721 .need_pll_cfg = true,
1722 .ht_greenfield_support = true,
1723 .led_compensation = 51,
1724 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1727 struct iwl_cfg iwl5150_agn_cfg = {
1729 .fw_name_pre = IWL5150_FW_PRE,
1730 .ucode_api_max = IWL5150_UCODE_API_MAX,
1731 .ucode_api_min = IWL5150_UCODE_API_MIN,
1732 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1733 .ops = &iwl5150_ops,
1734 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1735 .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1736 .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1737 .mod_params = &iwl50_mod_params,
1738 .valid_tx_ant = ANT_A,
1739 .valid_rx_ant = ANT_AB,
1740 .need_pll_cfg = true,
1741 .ht_greenfield_support = true,
1742 .led_compensation = 51,
1743 .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1746 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1747 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1749 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
1750 MODULE_PARM_DESC(swcrypto50,
1751 "using software crypto engine (default 0 [hardware])\n");
1752 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
1753 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1754 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
1755 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1756 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1758 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1759 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
1760 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");