drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/cpu.h>
  20 #include <linux/delay.h>
  21 #include <linux/errno.h>
  22 #include <linux/fs.h>
  23 #include <linux/genhd.h>
  24 #include <linux/hdreg.h>
  25 #include <linux/idr.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kdev_t.h>
  30 #include <linux/kernel.h>
  31 #include <linux/mm.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/mutex.h>
  35 #include <linux/pci.h>
  36 #include <linux/poison.h>
  37 #include <linux/ptrace.h>
  38 #include <linux/sched.h>
  39 #include <linux/slab.h>
  40 #include <linux/t10-pi.h>
  41 #include <linux/timer.h>
  42 #include <linux/types.h>
  43 #include <linux/io-64-nonatomic-lo-hi.h>
  44 #include <asm/unaligned.h>
  45
  46 #include "nvme.h"
  47
  48 #define NVME_Q_DEPTH            1024
  49 #define NVME_AQ_DEPTH           256
  50 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  51 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  52
  53 /*
  54  * We handle AEN commands ourselves and don't even let the
  55  * block layer know about them.
  56  */
  57 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AERS)
  58
  59 static int use_threaded_interrupts;
  60 module_param(use_threaded_interrupts, int, 0);
  61
  62 static bool use_cmb_sqes = true;
  63 module_param(use_cmb_sqes, bool, 0644);
  64 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  65
  66 static struct workqueue_struct *nvme_workq;
  67
  68 struct nvme_dev;
  69 struct nvme_queue;
  70
  71 static int nvme_reset(struct nvme_dev *dev);
  72 static void nvme_process_cq(struct nvme_queue *nvmeq);
  73 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  74
  75 /*
  76  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  77  */
  78 struct nvme_dev {
  79         struct nvme_queue **queues;
  80         struct blk_mq_tag_set tagset;
  81         struct blk_mq_tag_set admin_tagset;
  82         u32 __iomem *dbs;
  83         struct device *dev;
  84         struct dma_pool *prp_page_pool;
  85         struct dma_pool *prp_small_pool;
  86         unsigned queue_count;
  87         unsigned online_queues;
  88         unsigned max_qid;
  89         int q_depth;
  90         u32 db_stride;
  91         struct msix_entry *entry;
  92         void __iomem *bar;
  93         struct work_struct reset_work;
  94         struct work_struct remove_work;
  95         struct timer_list watchdog_timer;
  96         struct mutex shutdown_lock;
  97         bool subsystem;
  98         void __iomem *cmb;
  99         dma_addr_t cmb_dma_addr;
 100         u64 cmb_size;
 101         u32 cmbsz;
 102         struct nvme_ctrl ctrl;
 103         struct completion ioq_wait;
 104 };
 105
 106 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 107 {
 108         return container_of(ctrl, struct nvme_dev, ctrl);
 109 }
 110
 111 /*
 112  * An NVM Express queue.  Each device has at least two (one for admin
 113  * commands and one for I/O commands).
 114  */
 115 struct nvme_queue {
 116         struct device *q_dmadev;
 117         struct nvme_dev *dev;
 118         char irqname[24];       /* nvme4294967295-65535\0 */
 119         spinlock_t q_lock;
 120         struct nvme_command *sq_cmds;
 121         struct nvme_command __iomem *sq_cmds_io;
 122         volatile struct nvme_completion *cqes;
 123         struct blk_mq_tags **tags;
 124         dma_addr_t sq_dma_addr;
 125         dma_addr_t cq_dma_addr;
 126         u32 __iomem *q_db;
 127         u16 q_depth;
 128         s16 cq_vector;
 129         u16 sq_tail;
 130         u16 cq_head;
 131         u16 qid;
 132         u8 cq_phase;
 133         u8 cqe_seen;
 134 };
 135
 136 /*
 137  * The nvme_iod describes the data in an I/O, including the list of PRP
 138  * entries.  You can't see it in this data structure because C doesn't let
 139  * me express that.  Use nvme_init_iod to ensure there's enough space
 140  * allocated to store the PRP list.
 141  */
 142 struct nvme_iod {
 143         struct nvme_queue *nvmeq;
 144         int aborted;
 145         int npages;             /* In the PRP list. 0 means small pool in use */
 146         int nents;              /* Used in scatterlist */
 147         int length;             /* Of data, in bytes */
 148         dma_addr_t first_dma;
 149         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 150         struct scatterlist *sg;
 151         struct scatterlist inline_sg[0];
 152 };
 153
 154 /*
 155  * Check we didin't inadvertently grow the command struct
 156  */
 157 static inline void _nvme_check_size(void)
 158 {
 159         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 160         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 161         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 162         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 163         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 164         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 165         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 166         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 167         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 168         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 169         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 170         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 171 }
 172
 173 /*
 174  * Max size of iod being embedded in the request payload
 175  */
 176 #define NVME_INT_PAGES          2
 177 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 178
 179 /*
 180  * Will slightly overestimate the number of pages needed.  This is OK
 181  * as it only leads to a small amount of wasted memory for the lifetime of
 182  * the I/O.
 183  */
 184 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 185 {
 186         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 187                                       dev->ctrl.page_size);
 188         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 189 }
 190
 191 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 192                 unsigned int size, unsigned int nseg)
 193 {
 194         return sizeof(__le64 *) * nvme_npages(size, dev) +
 195                         sizeof(struct scatterlist) * nseg;
 196 }
 197
 198 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 199 {
 200         return sizeof(struct nvme_iod) +
 201                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 202 }
 203
 204 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 205                                 unsigned int hctx_idx)
 206 {
 207         struct nvme_dev *dev = data;
 208         struct nvme_queue *nvmeq = dev->queues[0];
 209
 210         WARN_ON(hctx_idx != 0);
 211         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 212         WARN_ON(nvmeq->tags);
 213
 214         hctx->driver_data = nvmeq;
 215         nvmeq->tags = &dev->admin_tagset.tags[0];
 216         return 0;
 217 }
 218
 219 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 220 {
 221         struct nvme_queue *nvmeq = hctx->driver_data;
 222
 223         nvmeq->tags = NULL;
 224 }
 225
 226 static int nvme_admin_init_request(void *data, struct request *req,
 227                                 unsigned int hctx_idx, unsigned int rq_idx,
 228                                 unsigned int numa_node)
 229 {
 230         struct nvme_dev *dev = data;
 231         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 232         struct nvme_queue *nvmeq = dev->queues[0];
 233
 234         BUG_ON(!nvmeq);
 235         iod->nvmeq = nvmeq;
 236         return 0;
 237 }
 238
 239 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 240                           unsigned int hctx_idx)
 241 {
 242         struct nvme_dev *dev = data;
 243         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 244
 245         if (!nvmeq->tags)
 246                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 247
 248         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 249         hctx->driver_data = nvmeq;
 250         return 0;
 251 }
 252
 253 static int nvme_init_request(void *data, struct request *req,
 254                                 unsigned int hctx_idx, unsigned int rq_idx,
 255                                 unsigned int numa_node)
 256 {
 257         struct nvme_dev *dev = data;
 258         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 259         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 260
 261         BUG_ON(!nvmeq);
 262         iod->nvmeq = nvmeq;
 263         return 0;
 264 }
 265
 266 /**
 267  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 268  * @nvmeq: The queue to use
 269  * @cmd: The command to send
 270  *
 271  * Safe to use from interrupt context
 272  */
 273 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 274                                                 struct nvme_command *cmd)
 275 {
 276         u16 tail = nvmeq->sq_tail;
 277
 278         if (nvmeq->sq_cmds_io)
 279                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 280         else
 281                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 282
 283         if (++tail == nvmeq->q_depth)
 284                 tail = 0;
 285         writel(tail, nvmeq->q_db);
 286         nvmeq->sq_tail = tail;
 287 }
 288
 289 static __le64 **iod_list(struct request *req)
 290 {
 291         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 292         return (__le64 **)(iod->sg + req->nr_phys_segments);
 293 }
 294
 295 static int nvme_init_iod(struct request *rq, unsigned size,
 296                 struct nvme_dev *dev)
 297 {
 298         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 299         int nseg = rq->nr_phys_segments;
 300
 301         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 302                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 303                 if (!iod->sg)
 304                         return BLK_MQ_RQ_QUEUE_BUSY;
 305         } else {
 306                 iod->sg = iod->inline_sg;
 307         }
 308
 309         iod->aborted = 0;
 310         iod->npages = -1;
 311         iod->nents = 0;
 312         iod->length = size;
 313
 314         if (!(rq->cmd_flags & REQ_DONTPREP)) {
 315                 rq->retries = 0;
 316                 rq->cmd_flags |= REQ_DONTPREP;
 317         }
 318         return 0;
 319 }
 320
 321 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 322 {
 323         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 324         const int last_prp = dev->ctrl.page_size / 8 - 1;
 325         int i;
 326         __le64 **list = iod_list(req);
 327         dma_addr_t prp_dma = iod->first_dma;
 328
 329         nvme_cleanup_cmd(req);
 330
 331         if (iod->npages == 0)
 332                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 333         for (i = 0; i < iod->npages; i++) {
 334                 __le64 *prp_list = list[i];
 335                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 336                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 337                 prp_dma = next_prp_dma;
 338         }
 339
 340         if (iod->sg != iod->inline_sg)
 341                 kfree(iod->sg);
 342 }
 343
 344 #ifdef CONFIG_BLK_DEV_INTEGRITY
 345 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 346 {
 347         if (be32_to_cpu(pi->ref_tag) == v)
 348                 pi->ref_tag = cpu_to_be32(p);
 349 }
 350
 351 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 352 {
 353         if (be32_to_cpu(pi->ref_tag) == p)
 354                 pi->ref_tag = cpu_to_be32(v);
 355 }
 356
 357 /**
 358  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 359  *
 360  * The virtual start sector is the one that was originally submitted by the
 361  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 362  * start sector may be different. Remap protection information to match the
 363  * physical LBA on writes, and back to the original seed on reads.
 364  *
 365  * Type 0 and 3 do not have a ref tag, so no remapping required.
 366  */
 367 static void nvme_dif_remap(struct request *req,
 368                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 369 {
 370         struct nvme_ns *ns = req->rq_disk->private_data;
 371         struct bio_integrity_payload *bip;
 372         struct t10_pi_tuple *pi;
 373         void *p, *pmap;
 374         u32 i, nlb, ts, phys, virt;
 375
 376         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 377                 return;
 378
 379         bip = bio_integrity(req->bio);
 380         if (!bip)
 381                 return;
 382
 383         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 384
 385         p = pmap;
 386         virt = bip_get_seed(bip);
 387         phys = nvme_block_nr(ns, blk_rq_pos(req));
 388         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 389         ts = ns->disk->queue->integrity.tuple_size;
 390
 391         for (i = 0; i < nlb; i++, virt++, phys++) {
 392                 pi = (struct t10_pi_tuple *)p;
 393                 dif_swap(phys, virt, pi);
 394                 p += ts;
 395         }
 396         kunmap_atomic(pmap);
 397 }
 398 #else /* CONFIG_BLK_DEV_INTEGRITY */
 399 static void nvme_dif_remap(struct request *req,
 400                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 401 {
 402 }
 403 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 404 {
 405 }
 406 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 407 {
 408 }
 409 #endif
 410
 411 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
 412                 int total_len)
 413 {
 414         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 415         struct dma_pool *pool;
 416         int length = total_len;
 417         struct scatterlist *sg = iod->sg;
 418         int dma_len = sg_dma_len(sg);
 419         u64 dma_addr = sg_dma_address(sg);
 420         u32 page_size = dev->ctrl.page_size;
 421         int offset = dma_addr & (page_size - 1);
 422         __le64 *prp_list;
 423         __le64 **list = iod_list(req);
 424         dma_addr_t prp_dma;
 425         int nprps, i;
 426
 427         length -= (page_size - offset);
 428         if (length <= 0)
 429                 return true;
 430
 431         dma_len -= (page_size - offset);
 432         if (dma_len) {
 433                 dma_addr += (page_size - offset);
 434         } else {
 435                 sg = sg_next(sg);
 436                 dma_addr = sg_dma_address(sg);
 437                 dma_len = sg_dma_len(sg);
 438         }
 439
 440         if (length <= page_size) {
 441                 iod->first_dma = dma_addr;
 442                 return true;
 443         }
 444
 445         nprps = DIV_ROUND_UP(length, page_size);
 446         if (nprps <= (256 / 8)) {
 447                 pool = dev->prp_small_pool;
 448                 iod->npages = 0;
 449         } else {
 450                 pool = dev->prp_page_pool;
 451                 iod->npages = 1;
 452         }
 453
 454         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 455         if (!prp_list) {
 456                 iod->first_dma = dma_addr;
 457                 iod->npages = -1;
 458                 return false;
 459         }
 460         list[0] = prp_list;
 461         iod->first_dma = prp_dma;
 462         i = 0;
 463         for (;;) {
 464                 if (i == page_size >> 3) {
 465                         __le64 *old_prp_list = prp_list;
 466                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 467                         if (!prp_list)
 468                                 return false;
 469                         list[iod->npages++] = prp_list;
 470                         prp_list[0] = old_prp_list[i - 1];
 471                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 472                         i = 1;
 473                 }
 474                 prp_list[i++] = cpu_to_le64(dma_addr);
 475                 dma_len -= page_size;
 476                 dma_addr += page_size;
 477                 length -= page_size;
 478                 if (length <= 0)
 479                         break;
 480                 if (dma_len > 0)
 481                         continue;
 482                 BUG_ON(dma_len < 0);
 483                 sg = sg_next(sg);
 484                 dma_addr = sg_dma_address(sg);
 485                 dma_len = sg_dma_len(sg);
 486         }
 487
 488         return true;
 489 }
 490
 491 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 492                 unsigned size, struct nvme_command *cmnd)
 493 {
 494         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 495         struct request_queue *q = req->q;
 496         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 497                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 498         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 499
 500         sg_init_table(iod->sg, req->nr_phys_segments);
 501         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 502         if (!iod->nents)
 503                 goto out;
 504
 505         ret = BLK_MQ_RQ_QUEUE_BUSY;
 506         if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir))
 507                 goto out;
 508
 509         if (!nvme_setup_prps(dev, req, size))
 510                 goto out_unmap;
 511
 512         ret = BLK_MQ_RQ_QUEUE_ERROR;
 513         if (blk_integrity_rq(req)) {
 514                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 515                         goto out_unmap;
 516
 517                 sg_init_table(&iod->meta_sg, 1);
 518                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 519                         goto out_unmap;
 520
 521                 if (rq_data_dir(req))
 522                         nvme_dif_remap(req, nvme_dif_prep);
 523
 524                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 525                         goto out_unmap;
 526         }
 527
 528         cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 529         cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
 530         if (blk_integrity_rq(req))
 531                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 532         return BLK_MQ_RQ_QUEUE_OK;
 533
 534 out_unmap:
 535         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 536 out:
 537         return ret;
 538 }
 539
 540 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 541 {
 542         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 543         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 544                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 545
 546         if (iod->nents) {
 547                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 548                 if (blk_integrity_rq(req)) {
 549                         if (!rq_data_dir(req))
 550                                 nvme_dif_remap(req, nvme_dif_complete);
 551                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 552                 }
 553         }
 554
 555         nvme_free_iod(dev, req);
 556 }
 557
 558 /*
 559  * NOTE: ns is NULL when called on the admin queue.
 560  */
 561 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 562                          const struct blk_mq_queue_data *bd)
 563 {
 564         struct nvme_ns *ns = hctx->queue->queuedata;
 565         struct nvme_queue *nvmeq = hctx->driver_data;
 566         struct nvme_dev *dev = nvmeq->dev;
 567         struct request *req = bd->rq;
 568         struct nvme_command cmnd;
 569         unsigned map_len;
 570         int ret = BLK_MQ_RQ_QUEUE_OK;
 571
 572         /*
 573          * If formated with metadata, require the block layer provide a buffer
 574          * unless this namespace is formated such that the metadata can be
 575          * stripped/generated by the controller with PRACT=1.
 576          */
 577         if (ns && ns->ms && !blk_integrity_rq(req)) {
 578                 if (!(ns->pi_type && ns->ms == 8) &&
 579                                         req->cmd_type != REQ_TYPE_DRV_PRIV) {
 580                         blk_mq_end_request(req, -EFAULT);
 581                         return BLK_MQ_RQ_QUEUE_OK;
 582                 }
 583         }
 584
 585         map_len = nvme_map_len(req);
 586         ret = nvme_init_iod(req, map_len, dev);
 587         if (ret)
 588                 return ret;
 589
 590         ret = nvme_setup_cmd(ns, req, &cmnd);
 591         if (ret)
 592                 goto out;
 593
 594         if (req->nr_phys_segments)
 595                 ret = nvme_map_data(dev, req, map_len, &cmnd);
 596
 597         if (ret)
 598                 goto out;
 599
 600         cmnd.common.command_id = req->tag;
 601         blk_mq_start_request(req);
 602
 603         spin_lock_irq(&nvmeq->q_lock);
 604         if (unlikely(nvmeq->cq_vector < 0)) {
 605                 if (ns && !test_bit(NVME_NS_DEAD, &ns->flags))
 606                         ret = BLK_MQ_RQ_QUEUE_BUSY;
 607                 else
 608                         ret = BLK_MQ_RQ_QUEUE_ERROR;
 609                 spin_unlock_irq(&nvmeq->q_lock);
 610                 goto out;
 611         }
 612         __nvme_submit_cmd(nvmeq, &cmnd);
 613         nvme_process_cq(nvmeq);
 614         spin_unlock_irq(&nvmeq->q_lock);
 615         return BLK_MQ_RQ_QUEUE_OK;
 616 out:
 617         nvme_free_iod(dev, req);
 618         return ret;
 619 }
 620
 621 static void nvme_complete_rq(struct request *req)
 622 {
 623         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 624         struct nvme_dev *dev = iod->nvmeq->dev;
 625         int error = 0;
 626
 627         nvme_unmap_data(dev, req);
 628
 629         if (unlikely(req->errors)) {
 630                 if (nvme_req_needs_retry(req, req->errors)) {
 631                         req->retries++;
 632                         nvme_requeue_req(req);
 633                         return;
 634                 }
 635
 636                 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
 637                         error = req->errors;
 638                 else
 639                         error = nvme_error_status(req->errors);
 640         }
 641
 642         if (unlikely(iod->aborted)) {
 643                 dev_warn(dev->ctrl.device,
 644                         "completing aborted command with status: %04x\n",
 645                         req->errors);
 646         }
 647
 648         blk_mq_end_request(req, error);
 649 }
 650
 651 /* We read the CQE phase first to check if the rest of the entry is valid */
 652 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 653                 u16 phase)
 654 {
 655         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 656 }
 657
 658 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 659 {
 660         u16 head, phase;
 661
 662         head = nvmeq->cq_head;
 663         phase = nvmeq->cq_phase;
 664
 665         while (nvme_cqe_valid(nvmeq, head, phase)) {
 666                 struct nvme_completion cqe = nvmeq->cqes[head];
 667                 struct request *req;
 668
 669                 if (++head == nvmeq->q_depth) {
 670                         head = 0;
 671                         phase = !phase;
 672                 }
 673
 674                 if (tag && *tag == cqe.command_id)
 675                         *tag = -1;
 676
 677                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 678                         dev_warn(nvmeq->dev->ctrl.device,
 679                                 "invalid id %d completed on queue %d\n",
 680                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 681                         continue;
 682                 }
 683
 684                 /*
 685                  * AEN requests are special as they don't time out and can
 686                  * survive any kind of queue freeze and often don't respond to
 687                  * aborts.  We don't even bother to allocate a struct request
 688                  * for them but rather special case them here.
 689                  */
 690                 if (unlikely(nvmeq->qid == 0 &&
 691                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 692                         nvme_complete_async_event(&nvmeq->dev->ctrl, &cqe);
 693                         continue;
 694                 }
 695
 696                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 697                 if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special)
 698                         memcpy(req->special, &cqe, sizeof(cqe));
 699                 blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
 700
 701         }
 702
 703         /* If the controller ignores the cq head doorbell and continuously
 704          * writes to the queue, it is theoretically possible to wrap around
 705          * the queue twice and mistakenly return IRQ_NONE.  Linux only
 706          * requires that 0.1% of your interrupts are handled, so this isn't
 707          * a big problem.
 708          */
 709         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 710                 return;
 711
 712         if (likely(nvmeq->cq_vector >= 0))
 713                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 714         nvmeq->cq_head = head;
 715         nvmeq->cq_phase = phase;
 716
 717         nvmeq->cqe_seen = 1;
 718 }
 719
 720 static void nvme_process_cq(struct nvme_queue *nvmeq)
 721 {
 722         __nvme_process_cq(nvmeq, NULL);
 723 }
 724
 725 static irqreturn_t nvme_irq(int irq, void *data)
 726 {
 727         irqreturn_t result;
 728         struct nvme_queue *nvmeq = data;
 729         spin_lock(&nvmeq->q_lock);
 730         nvme_process_cq(nvmeq);
 731         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 732         nvmeq->cqe_seen = 0;
 733         spin_unlock(&nvmeq->q_lock);
 734         return result;
 735 }
 736
 737 static irqreturn_t nvme_irq_check(int irq, void *data)
 738 {
 739         struct nvme_queue *nvmeq = data;
 740         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 741                 return IRQ_WAKE_THREAD;
 742         return IRQ_NONE;
 743 }
 744
 745 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 746 {
 747         struct nvme_queue *nvmeq = hctx->driver_data;
 748
 749         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 750                 spin_lock_irq(&nvmeq->q_lock);
 751                 __nvme_process_cq(nvmeq, &tag);
 752                 spin_unlock_irq(&nvmeq->q_lock);
 753
 754                 if (tag == -1)
 755                         return 1;
 756         }
 757
 758         return 0;
 759 }
 760
 761 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
 762 {
 763         struct nvme_dev *dev = to_nvme_dev(ctrl);
 764         struct nvme_queue *nvmeq = dev->queues[0];
 765         struct nvme_command c;
 766
 767         memset(&c, 0, sizeof(c));
 768         c.common.opcode = nvme_admin_async_event;
 769         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
 770
 771         spin_lock_irq(&nvmeq->q_lock);
 772         __nvme_submit_cmd(nvmeq, &c);
 773         spin_unlock_irq(&nvmeq->q_lock);
 774 }
 775
 776 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 777 {
 778         struct nvme_command c;
 779
 780         memset(&c, 0, sizeof(c));
 781         c.delete_queue.opcode = opcode;
 782         c.delete_queue.qid = cpu_to_le16(id);
 783
 784         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 785 }
 786
 787 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 788                                                 struct nvme_queue *nvmeq)
 789 {
 790         struct nvme_command c;
 791         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 792
 793         /*
 794          * Note: we (ab)use the fact the the prp fields survive if no data
 795          * is attached to the request.
 796          */
 797         memset(&c, 0, sizeof(c));
 798         c.create_cq.opcode = nvme_admin_create_cq;
 799         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 800         c.create_cq.cqid = cpu_to_le16(qid);
 801         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 802         c.create_cq.cq_flags = cpu_to_le16(flags);
 803         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 804
 805         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 806 }
 807
 808 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 809                                                 struct nvme_queue *nvmeq)
 810 {
 811         struct nvme_command c;
 812         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 813
 814         /*
 815          * Note: we (ab)use the fact the the prp fields survive if no data
 816          * is attached to the request.
 817          */
 818         memset(&c, 0, sizeof(c));
 819         c.create_sq.opcode = nvme_admin_create_sq;
 820         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 821         c.create_sq.sqid = cpu_to_le16(qid);
 822         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 823         c.create_sq.sq_flags = cpu_to_le16(flags);
 824         c.create_sq.cqid = cpu_to_le16(qid);
 825
 826         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 827 }
 828
 829 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 830 {
 831         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 832 }
 833
 834 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 835 {
 836         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 837 }
 838
 839 static void abort_endio(struct request *req, int error)
 840 {
 841         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 842         struct nvme_queue *nvmeq = iod->nvmeq;
 843         u16 status = req->errors;
 844
 845         dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
 846         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 847         blk_mq_free_request(req);
 848 }
 849
 850 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 851 {
 852         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 853         struct nvme_queue *nvmeq = iod->nvmeq;
 854         struct nvme_dev *dev = nvmeq->dev;
 855         struct request *abort_req;
 856         struct nvme_command cmd;
 857
 858         /*
 859          * Shutdown immediately if controller times out while starting. The
 860          * reset work will see the pci device disabled when it gets the forced
 861          * cancellation error. All outstanding requests are completed on
 862          * shutdown, so we return BLK_EH_HANDLED.
 863          */
 864         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
 865                 dev_warn(dev->ctrl.device,
 866                          "I/O %d QID %d timeout, disable controller\n",
 867                          req->tag, nvmeq->qid);
 868                 nvme_dev_disable(dev, false);
 869                 req->errors = NVME_SC_CANCELLED;
 870                 return BLK_EH_HANDLED;
 871         }
 872
 873         /*
 874          * Shutdown the controller immediately and schedule a reset if the
 875          * command was already aborted once before and still hasn't been
 876          * returned to the driver, or if this is the admin queue.
 877          */
 878         if (!nvmeq->qid || iod->aborted) {
 879                 dev_warn(dev->ctrl.device,
 880                          "I/O %d QID %d timeout, reset controller\n",
 881                          req->tag, nvmeq->qid);
 882                 nvme_dev_disable(dev, false);
 883                 queue_work(nvme_workq, &dev->reset_work);
 884
 885                 /*
 886                  * Mark the request as handled, since the inline shutdown
 887                  * forces all outstanding requests to complete.
 888                  */
 889                 req->errors = NVME_SC_CANCELLED;
 890                 return BLK_EH_HANDLED;
 891         }
 892
 893         iod->aborted = 1;
 894
 895         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 896                 atomic_inc(&dev->ctrl.abort_limit);
 897                 return BLK_EH_RESET_TIMER;
 898         }
 899
 900         memset(&cmd, 0, sizeof(cmd));
 901         cmd.abort.opcode = nvme_admin_abort_cmd;
 902         cmd.abort.cid = req->tag;
 903         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 904
 905         dev_warn(nvmeq->dev->ctrl.device,
 906                 "I/O %d QID %d timeout, aborting\n",
 907                  req->tag, nvmeq->qid);
 908
 909         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 910                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
 911         if (IS_ERR(abort_req)) {
 912                 atomic_inc(&dev->ctrl.abort_limit);
 913                 return BLK_EH_RESET_TIMER;
 914         }
 915
 916         abort_req->timeout = ADMIN_TIMEOUT;
 917         abort_req->end_io_data = NULL;
 918         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 919
 920         /*
 921          * The aborted req will be completed on receiving the abort req.
 922          * We enable the timer again. If hit twice, it'll cause a device reset,
 923          * as the device then is in a faulty state.
 924          */
 925         return BLK_EH_RESET_TIMER;
 926 }
 927
 928 static void nvme_free_queue(struct nvme_queue *nvmeq)
 929 {
 930         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 931                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 932         if (nvmeq->sq_cmds)
 933                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 934                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 935         kfree(nvmeq);
 936 }
 937
 938 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
 939 {
 940         int i;
 941
 942         for (i = dev->queue_count - 1; i >= lowest; i--) {
 943                 struct nvme_queue *nvmeq = dev->queues[i];
 944                 dev->queue_count--;
 945                 dev->queues[i] = NULL;
 946                 nvme_free_queue(nvmeq);
 947         }
 948 }
 949
 950 /**
 951  * nvme_suspend_queue - put queue into suspended state
 952  * @nvmeq - queue to suspend
 953  */
 954 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
 955 {
 956         int vector;
 957
 958         spin_lock_irq(&nvmeq->q_lock);
 959         if (nvmeq->cq_vector == -1) {
 960                 spin_unlock_irq(&nvmeq->q_lock);
 961                 return 1;
 962         }
 963         vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
 964         nvmeq->dev->online_queues--;
 965         nvmeq->cq_vector = -1;
 966         spin_unlock_irq(&nvmeq->q_lock);
 967
 968         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
 969                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
 970
 971         irq_set_affinity_hint(vector, NULL);
 972         free_irq(vector, nvmeq);
 973
 974         return 0;
 975 }
 976
 977 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
 978 {
 979         struct nvme_queue *nvmeq = dev->queues[0];
 980
 981         if (!nvmeq)
 982                 return;
 983         if (nvme_suspend_queue(nvmeq))
 984                 return;
 985
 986         if (shutdown)
 987                 nvme_shutdown_ctrl(&dev->ctrl);
 988         else
 989                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
 990                                                 dev->bar + NVME_REG_CAP));
 991
 992         spin_lock_irq(&nvmeq->q_lock);
 993         nvme_process_cq(nvmeq);
 994         spin_unlock_irq(&nvmeq->q_lock);
 995 }
 996
 997 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
 998                                 int entry_size)
 999 {
1000         int q_depth = dev->q_depth;
1001         unsigned q_size_aligned = roundup(q_depth * entry_size,
1002                                           dev->ctrl.page_size);
1003
1004         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1005                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1006                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1007                 q_depth = div_u64(mem_per_q, entry_size);
1008
1009                 /*
1010                  * Ensure the reduced q_depth is above some threshold where it
1011                  * would be better to map queues in system memory with the
1012                  * original depth
1013                  */
1014                 if (q_depth < 64)
1015                         return -ENOMEM;
1016         }
1017
1018         return q_depth;
1019 }
1020
1021 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1022                                 int qid, int depth)
1023 {
1024         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1025                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1026                                                       dev->ctrl.page_size);
1027                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1028                 nvmeq->sq_cmds_io = dev->cmb + offset;
1029         } else {
1030                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1031                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1032                 if (!nvmeq->sq_cmds)
1033                         return -ENOMEM;
1034         }
1035
1036         return 0;
1037 }
1038
1039 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1040                                                         int depth)
1041 {
1042         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1043         if (!nvmeq)
1044                 return NULL;
1045
1046         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1047                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1048         if (!nvmeq->cqes)
1049                 goto free_nvmeq;
1050
1051         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1052                 goto free_cqdma;
1053
1054         nvmeq->q_dmadev = dev->dev;
1055         nvmeq->dev = dev;
1056         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1057                         dev->ctrl.instance, qid);
1058         spin_lock_init(&nvmeq->q_lock);
1059         nvmeq->cq_head = 0;
1060         nvmeq->cq_phase = 1;
1061         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1062         nvmeq->q_depth = depth;
1063         nvmeq->qid = qid;
1064         nvmeq->cq_vector = -1;
1065         dev->queues[qid] = nvmeq;
1066         dev->queue_count++;
1067
1068         return nvmeq;
1069
1070  free_cqdma:
1071         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1072                                                         nvmeq->cq_dma_addr);
1073  free_nvmeq:
1074         kfree(nvmeq);
1075         return NULL;
1076 }
1077
1078 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1079                                                         const char *name)
1080 {
1081         if (use_threaded_interrupts)
1082                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1083                                         nvme_irq_check, nvme_irq, IRQF_SHARED,
1084                                         name, nvmeq);
1085         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1086                                 IRQF_SHARED, name, nvmeq);
1087 }
1088
1089 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1090 {
1091         struct nvme_dev *dev = nvmeq->dev;
1092
1093         spin_lock_irq(&nvmeq->q_lock);
1094         nvmeq->sq_tail = 0;
1095         nvmeq->cq_head = 0;
1096         nvmeq->cq_phase = 1;
1097         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1098         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1099         dev->online_queues++;
1100         spin_unlock_irq(&nvmeq->q_lock);
1101 }
1102
1103 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1104 {
1105         struct nvme_dev *dev = nvmeq->dev;
1106         int result;
1107
1108         nvmeq->cq_vector = qid - 1;
1109         result = adapter_alloc_cq(dev, qid, nvmeq);
1110         if (result < 0)
1111                 return result;
1112
1113         result = adapter_alloc_sq(dev, qid, nvmeq);
1114         if (result < 0)
1115                 goto release_cq;
1116
1117         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1118         if (result < 0)
1119                 goto release_sq;
1120
1121         nvme_init_queue(nvmeq, qid);
1122         return result;
1123
1124  release_sq:
1125         adapter_delete_sq(dev, qid);
1126  release_cq:
1127         adapter_delete_cq(dev, qid);
1128         return result;
1129 }
1130
1131 static struct blk_mq_ops nvme_mq_admin_ops = {
1132         .queue_rq       = nvme_queue_rq,
1133         .complete       = nvme_complete_rq,
1134         .map_queue      = blk_mq_map_queue,
1135         .init_hctx      = nvme_admin_init_hctx,
1136         .exit_hctx      = nvme_admin_exit_hctx,
1137         .init_request   = nvme_admin_init_request,
1138         .timeout        = nvme_timeout,
1139 };
1140
1141 static struct blk_mq_ops nvme_mq_ops = {
1142         .queue_rq       = nvme_queue_rq,
1143         .complete       = nvme_complete_rq,
1144         .map_queue      = blk_mq_map_queue,
1145         .init_hctx      = nvme_init_hctx,
1146         .init_request   = nvme_init_request,
1147         .timeout        = nvme_timeout,
1148         .poll           = nvme_poll,
1149 };
1150
1151 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1152 {
1153         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1154                 /*
1155                  * If the controller was reset during removal, it's possible
1156                  * user requests may be waiting on a stopped queue. Start the
1157                  * queue to flush these to completion.
1158                  */
1159                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1160                 blk_cleanup_queue(dev->ctrl.admin_q);
1161                 blk_mq_free_tag_set(&dev->admin_tagset);
1162         }
1163 }
1164
1165 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1166 {
1167         if (!dev->ctrl.admin_q) {
1168                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1169                 dev->admin_tagset.nr_hw_queues = 1;
1170
1171                 /*
1172                  * Subtract one to leave an empty queue entry for 'Full Queue'
1173                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1174                  */
1175                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1176                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1177                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1178                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1179                 dev->admin_tagset.driver_data = dev;
1180
1181                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1182                         return -ENOMEM;
1183
1184                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1185                 if (IS_ERR(dev->ctrl.admin_q)) {
1186                         blk_mq_free_tag_set(&dev->admin_tagset);
1187                         return -ENOMEM;
1188                 }
1189                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1190                         nvme_dev_remove_admin(dev);
1191                         dev->ctrl.admin_q = NULL;
1192                         return -ENODEV;
1193                 }
1194         } else
1195                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1196
1197         return 0;
1198 }
1199
1200 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1201 {
1202         int result;
1203         u32 aqa;
1204         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1205         struct nvme_queue *nvmeq;
1206
1207         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ?
1208                                                 NVME_CAP_NSSRC(cap) : 0;
1209
1210         if (dev->subsystem &&
1211             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1212                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1213
1214         result = nvme_disable_ctrl(&dev->ctrl, cap);
1215         if (result < 0)
1216                 return result;
1217
1218         nvmeq = dev->queues[0];
1219         if (!nvmeq) {
1220                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1221                 if (!nvmeq)
1222                         return -ENOMEM;
1223         }
1224
1225         aqa = nvmeq->q_depth - 1;
1226         aqa |= aqa << 16;
1227
1228         writel(aqa, dev->bar + NVME_REG_AQA);
1229         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1230         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1231
1232         result = nvme_enable_ctrl(&dev->ctrl, cap);
1233         if (result)
1234                 goto free_nvmeq;
1235
1236         nvmeq->cq_vector = 0;
1237         result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1238         if (result) {
1239                 nvmeq->cq_vector = -1;
1240                 goto free_nvmeq;
1241         }
1242
1243         return result;
1244
1245  free_nvmeq:
1246         nvme_free_queues(dev, 0);
1247         return result;
1248 }
1249
1250 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1251 {
1252
1253         /* If true, indicates loss of adapter communication, possibly by a
1254          * NVMe Subsystem reset.
1255          */
1256         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1257
1258         /* If there is a reset ongoing, we shouldn't reset again. */
1259         if (work_busy(&dev->reset_work))
1260                 return false;
1261
1262         /* We shouldn't reset unless the controller is on fatal error state
1263          * _or_ if we lost the communication with it.
1264          */
1265         if (!(csts & NVME_CSTS_CFS) && !nssro)
1266                 return false;
1267
1268         /* If PCI error recovery process is happening, we cannot reset or
1269          * the recovery mechanism will surely fail.
1270          */
1271         if (pci_channel_offline(to_pci_dev(dev->dev)))
1272                 return false;
1273
1274         return true;
1275 }
1276
1277 static void nvme_watchdog_timer(unsigned long data)
1278 {
1279         struct nvme_dev *dev = (struct nvme_dev *)data;
1280         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1281
1282         /* Skip controllers under certain specific conditions. */
1283         if (nvme_should_reset(dev, csts)) {
1284                 if (queue_work(nvme_workq, &dev->reset_work))
1285                         dev_warn(dev->dev,
1286                                 "Failed status: 0x%x, reset controller.\n",
1287                                 csts);
1288                 return;
1289         }
1290
1291         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1292 }
1293
1294 static int nvme_create_io_queues(struct nvme_dev *dev)
1295 {
1296         unsigned i, max;
1297         int ret = 0;
1298
1299         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1300                 if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1301                         ret = -ENOMEM;
1302                         break;
1303                 }
1304         }
1305
1306         max = min(dev->max_qid, dev->queue_count - 1);
1307         for (i = dev->online_queues; i <= max; i++) {
1308                 ret = nvme_create_queue(dev->queues[i], i);
1309                 if (ret) {
1310                         nvme_free_queues(dev, i);
1311                         break;
1312                 }
1313         }
1314
1315         /*
1316          * Ignore failing Create SQ/CQ commands, we can continue with less
1317          * than the desired aount of queues, and even a controller without
1318          * I/O queues an still be used to issue admin commands.  This might
1319          * be useful to upgrade a buggy firmware for example.
1320          */
1321         return ret >= 0 ? 0 : ret;
1322 }
1323
1324 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1325 {
1326         u64 szu, size, offset;
1327         u32 cmbloc;
1328         resource_size_t bar_size;
1329         struct pci_dev *pdev = to_pci_dev(dev->dev);
1330         void __iomem *cmb;
1331         dma_addr_t dma_addr;
1332
1333         if (!use_cmb_sqes)
1334                 return NULL;
1335
1336         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1337         if (!(NVME_CMB_SZ(dev->cmbsz)))
1338                 return NULL;
1339
1340         cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1341
1342         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1343         size = szu * NVME_CMB_SZ(dev->cmbsz);
1344         offset = szu * NVME_CMB_OFST(cmbloc);
1345         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
1346
1347         if (offset > bar_size)
1348                 return NULL;
1349
1350         /*
1351          * Controllers may support a CMB size larger than their BAR,
1352          * for example, due to being behind a bridge. Reduce the CMB to
1353          * the reported size of the BAR
1354          */
1355         if (size > bar_size - offset)
1356                 size = bar_size - offset;
1357
1358         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
1359         cmb = ioremap_wc(dma_addr, size);
1360         if (!cmb)
1361                 return NULL;
1362
1363         dev->cmb_dma_addr = dma_addr;
1364         dev->cmb_size = size;
1365         return cmb;
1366 }
1367
1368 static inline void nvme_release_cmb(struct nvme_dev *dev)
1369 {
1370         if (dev->cmb) {
1371                 iounmap(dev->cmb);
1372                 dev->cmb = NULL;
1373         }
1374 }
1375
1376 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1377 {
1378         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1379 }
1380
1381 static int nvme_setup_io_queues(struct nvme_dev *dev)
1382 {
1383         struct nvme_queue *adminq = dev->queues[0];
1384         struct pci_dev *pdev = to_pci_dev(dev->dev);
1385         int result, i, vecs, nr_io_queues, size;
1386
1387         nr_io_queues = num_online_cpus();
1388         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1389         if (result < 0)
1390                 return result;
1391
1392         if (nr_io_queues == 0)
1393                 return 0;
1394
1395         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1396                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1397                                 sizeof(struct nvme_command));
1398                 if (result > 0)
1399                         dev->q_depth = result;
1400                 else
1401                         nvme_release_cmb(dev);
1402         }
1403
1404         size = db_bar_size(dev, nr_io_queues);
1405         if (size > 8192) {
1406                 iounmap(dev->bar);
1407                 do {
1408                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1409                         if (dev->bar)
1410                                 break;
1411                         if (!--nr_io_queues)
1412                                 return -ENOMEM;
1413                         size = db_bar_size(dev, nr_io_queues);
1414                 } while (1);
1415                 dev->dbs = dev->bar + 4096;
1416                 adminq->q_db = dev->dbs;
1417         }
1418
1419         /* Deregister the admin queue's interrupt */
1420         free_irq(dev->entry[0].vector, adminq);
1421
1422         /*
1423          * If we enable msix early due to not intx, disable it again before
1424          * setting up the full range we need.
1425          */
1426         if (pdev->msi_enabled)
1427                 pci_disable_msi(pdev);
1428         else if (pdev->msix_enabled)
1429                 pci_disable_msix(pdev);
1430
1431         for (i = 0; i < nr_io_queues; i++)
1432                 dev->entry[i].entry = i;
1433         vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
1434         if (vecs < 0) {
1435                 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
1436                 if (vecs < 0) {
1437                         vecs = 1;
1438                 } else {
1439                         for (i = 0; i < vecs; i++)
1440                                 dev->entry[i].vector = i + pdev->irq;
1441                 }
1442         }
1443
1444         /*
1445          * Should investigate if there's a performance win from allocating
1446          * more queues than interrupt vectors; it might allow the submission
1447          * path to scale better, even if the receive path is limited by the
1448          * number of interrupts.
1449          */
1450         nr_io_queues = vecs;
1451         dev->max_qid = nr_io_queues;
1452
1453         result = queue_request_irq(dev, adminq, adminq->irqname);
1454         if (result) {
1455                 adminq->cq_vector = -1;
1456                 goto free_queues;
1457         }
1458         return nvme_create_io_queues(dev);
1459
1460  free_queues:
1461         nvme_free_queues(dev, 1);
1462         return result;
1463 }
1464
1465 static void nvme_pci_post_scan(struct nvme_ctrl *ctrl)
1466 {
1467         struct nvme_dev *dev = to_nvme_dev(ctrl);
1468         struct nvme_queue *nvmeq;
1469         int i;
1470
1471         for (i = 0; i < dev->online_queues; i++) {
1472                 nvmeq = dev->queues[i];
1473
1474                 if (!nvmeq->tags || !(*nvmeq->tags))
1475                         continue;
1476
1477                 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
1478                                         blk_mq_tags_cpumask(*nvmeq->tags));
1479         }
1480 }
1481
1482 static void nvme_del_queue_end(struct request *req, int error)
1483 {
1484         struct nvme_queue *nvmeq = req->end_io_data;
1485
1486         blk_mq_free_request(req);
1487         complete(&nvmeq->dev->ioq_wait);
1488 }
1489
1490 static void nvme_del_cq_end(struct request *req, int error)
1491 {
1492         struct nvme_queue *nvmeq = req->end_io_data;
1493
1494         if (!error) {
1495                 unsigned long flags;
1496
1497                 /*
1498                  * We might be called with the AQ q_lock held
1499                  * and the I/O queue q_lock should always
1500                  * nest inside the AQ one.
1501                  */
1502                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1503                                         SINGLE_DEPTH_NESTING);
1504                 nvme_process_cq(nvmeq);
1505                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1506         }
1507
1508         nvme_del_queue_end(req, error);
1509 }
1510
1511 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1512 {
1513         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1514         struct request *req;
1515         struct nvme_command cmd;
1516
1517         memset(&cmd, 0, sizeof(cmd));
1518         cmd.delete_queue.opcode = opcode;
1519         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1520
1521         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1522         if (IS_ERR(req))
1523                 return PTR_ERR(req);
1524
1525         req->timeout = ADMIN_TIMEOUT;
1526         req->end_io_data = nvmeq;
1527
1528         blk_execute_rq_nowait(q, NULL, req, false,
1529                         opcode == nvme_admin_delete_cq ?
1530                                 nvme_del_cq_end : nvme_del_queue_end);
1531         return 0;
1532 }
1533
1534 static void nvme_disable_io_queues(struct nvme_dev *dev)
1535 {
1536         int pass, queues = dev->online_queues - 1;
1537         unsigned long timeout;
1538         u8 opcode = nvme_admin_delete_sq;
1539
1540         for (pass = 0; pass < 2; pass++) {
1541                 int sent = 0, i = queues;
1542
1543                 reinit_completion(&dev->ioq_wait);
1544  retry:
1545                 timeout = ADMIN_TIMEOUT;
1546                 for (; i > 0; i--, sent++)
1547                         if (nvme_delete_queue(dev->queues[i], opcode))
1548                                 break;
1549
1550                 while (sent--) {
1551                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1552                         if (timeout == 0)
1553                                 return;
1554                         if (i)
1555                                 goto retry;
1556                 }
1557                 opcode = nvme_admin_delete_cq;
1558         }
1559 }
1560
1561 /*
1562  * Return: error value if an error occurred setting up the queues or calling
1563  * Identify Device.  0 if these succeeded, even if adding some of the
1564  * namespaces failed.  At the moment, these failures are silent.  TBD which
1565  * failures should be reported.
1566  */
1567 static int nvme_dev_add(struct nvme_dev *dev)
1568 {
1569         if (!dev->ctrl.tagset) {
1570                 dev->tagset.ops = &nvme_mq_ops;
1571                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1572                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1573                 dev->tagset.numa_node = dev_to_node(dev->dev);
1574                 dev->tagset.queue_depth =
1575                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1576                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1577                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1578                 dev->tagset.driver_data = dev;
1579
1580                 if (blk_mq_alloc_tag_set(&dev->tagset))
1581                         return 0;
1582                 dev->ctrl.tagset = &dev->tagset;
1583         } else {
1584                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1585
1586                 /* Free previously allocated queues that are no longer usable */
1587                 nvme_free_queues(dev, dev->online_queues);
1588         }
1589
1590         return 0;
1591 }
1592
1593 static int nvme_pci_enable(struct nvme_dev *dev)
1594 {
1595         u64 cap;
1596         int result = -ENOMEM;
1597         struct pci_dev *pdev = to_pci_dev(dev->dev);
1598
1599         if (pci_enable_device_mem(pdev))
1600                 return result;
1601
1602         pci_set_master(pdev);
1603
1604         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1605             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1606                 goto disable;
1607
1608         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1609                 result = -ENODEV;
1610                 goto disable;
1611         }
1612
1613         /*
1614          * Some devices and/or platforms don't advertise or work with INTx
1615          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1616          * adjust this later.
1617          */
1618         if (pci_enable_msix(pdev, dev->entry, 1)) {
1619                 pci_enable_msi(pdev);
1620                 dev->entry[0].vector = pdev->irq;
1621         }
1622
1623         if (!dev->entry[0].vector) {
1624                 result = -ENODEV;
1625                 goto disable;
1626         }
1627
1628         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1629
1630         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1631         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1632         dev->dbs = dev->bar + 4096;
1633
1634         /*
1635          * Temporary fix for the Apple controller found in the MacBook8,1 and
1636          * some MacBook7,1 to avoid controller resets and data loss.
1637          */
1638         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1639                 dev->q_depth = 2;
1640                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1641                         "queue depth=%u to work around controller resets\n",
1642                         dev->q_depth);
1643         }
1644
1645         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2))
1646                 dev->cmb = nvme_map_cmb(dev);
1647
1648         pci_enable_pcie_error_reporting(pdev);
1649         pci_save_state(pdev);
1650         return 0;
1651
1652  disable:
1653         pci_disable_device(pdev);
1654         return result;
1655 }
1656
1657 static void nvme_dev_unmap(struct nvme_dev *dev)
1658 {
1659         if (dev->bar)
1660                 iounmap(dev->bar);
1661         pci_release_mem_regions(to_pci_dev(dev->dev));
1662 }
1663
1664 static void nvme_pci_disable(struct nvme_dev *dev)
1665 {
1666         struct pci_dev *pdev = to_pci_dev(dev->dev);
1667
1668         if (pdev->msi_enabled)
1669                 pci_disable_msi(pdev);
1670         else if (pdev->msix_enabled)
1671                 pci_disable_msix(pdev);
1672
1673         if (pci_is_enabled(pdev)) {
1674                 pci_disable_pcie_error_reporting(pdev);
1675                 pci_disable_device(pdev);
1676         }
1677 }
1678
1679 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1680 {
1681         int i;
1682         u32 csts = -1;
1683
1684         del_timer_sync(&dev->watchdog_timer);
1685
1686         mutex_lock(&dev->shutdown_lock);
1687         if (pci_is_enabled(to_pci_dev(dev->dev))) {
1688                 nvme_stop_queues(&dev->ctrl);
1689                 csts = readl(dev->bar + NVME_REG_CSTS);
1690         }
1691
1692         for (i = dev->queue_count - 1; i > 0; i--)
1693                 nvme_suspend_queue(dev->queues[i]);
1694
1695         if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1696                 nvme_suspend_queue(dev->queues[0]);
1697         } else {
1698                 nvme_disable_io_queues(dev);
1699                 nvme_disable_admin_queue(dev, shutdown);
1700         }
1701         nvme_pci_disable(dev);
1702
1703         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
1704         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
1705         mutex_unlock(&dev->shutdown_lock);
1706 }
1707
1708 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1709 {
1710         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1711                                                 PAGE_SIZE, PAGE_SIZE, 0);
1712         if (!dev->prp_page_pool)
1713                 return -ENOMEM;
1714
1715         /* Optimisation for I/Os between 4k and 128k */
1716         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1717                                                 256, 256, 0);
1718         if (!dev->prp_small_pool) {
1719                 dma_pool_destroy(dev->prp_page_pool);
1720                 return -ENOMEM;
1721         }
1722         return 0;
1723 }
1724
1725 static void nvme_release_prp_pools(struct nvme_dev *dev)
1726 {
1727         dma_pool_destroy(dev->prp_page_pool);
1728         dma_pool_destroy(dev->prp_small_pool);
1729 }
1730
1731 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1732 {
1733         struct nvme_dev *dev = to_nvme_dev(ctrl);
1734
1735         put_device(dev->dev);
1736         if (dev->tagset.tags)
1737                 blk_mq_free_tag_set(&dev->tagset);
1738         if (dev->ctrl.admin_q)
1739                 blk_put_queue(dev->ctrl.admin_q);
1740         kfree(dev->queues);
1741         kfree(dev->entry);
1742         kfree(dev);
1743 }
1744
1745 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1746 {
1747         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1748
1749         kref_get(&dev->ctrl.kref);
1750         nvme_dev_disable(dev, false);
1751         if (!schedule_work(&dev->remove_work))
1752                 nvme_put_ctrl(&dev->ctrl);
1753 }
1754
1755 static void nvme_reset_work(struct work_struct *work)
1756 {
1757         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1758         int result = -ENODEV;
1759
1760         if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1761                 goto out;
1762
1763         /*
1764          * If we're called to reset a live controller first shut it down before
1765          * moving on.
1766          */
1767         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1768                 nvme_dev_disable(dev, false);
1769
1770         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1771                 goto out;
1772
1773         result = nvme_pci_enable(dev);
1774         if (result)
1775                 goto out;
1776
1777         result = nvme_configure_admin_queue(dev);
1778         if (result)
1779                 goto out;
1780
1781         nvme_init_queue(dev->queues[0], 0);
1782         result = nvme_alloc_admin_tags(dev);
1783         if (result)
1784                 goto out;
1785
1786         result = nvme_init_identify(&dev->ctrl);
1787         if (result)
1788                 goto out;
1789
1790         result = nvme_setup_io_queues(dev);
1791         if (result)
1792                 goto out;
1793
1794         /*
1795          * A controller that can not execute IO typically requires user
1796          * intervention to correct. For such degraded controllers, the driver
1797          * should not submit commands the user did not request, so skip
1798          * registering for asynchronous event notification on this condition.
1799          */
1800         if (dev->online_queues > 1)
1801                 nvme_queue_async_events(&dev->ctrl);
1802
1803         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1804
1805         /*
1806          * Keep the controller around but remove all namespaces if we don't have
1807          * any working I/O queue.
1808          */
1809         if (dev->online_queues < 2) {
1810                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1811                 nvme_kill_queues(&dev->ctrl);
1812                 nvme_remove_namespaces(&dev->ctrl);
1813         } else {
1814                 nvme_start_queues(&dev->ctrl);
1815                 nvme_dev_add(dev);
1816         }
1817
1818         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1819                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1820                 goto out;
1821         }
1822
1823         if (dev->online_queues > 1)
1824                 nvme_queue_scan(&dev->ctrl);
1825         return;
1826
1827  out:
1828         nvme_remove_dead_ctrl(dev, result);
1829 }
1830
1831 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1832 {
1833         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1834         struct pci_dev *pdev = to_pci_dev(dev->dev);
1835
1836         nvme_kill_queues(&dev->ctrl);
1837         if (pci_get_drvdata(pdev))
1838                 device_release_driver(&pdev->dev);
1839         nvme_put_ctrl(&dev->ctrl);
1840 }
1841
1842 static int nvme_reset(struct nvme_dev *dev)
1843 {
1844         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1845                 return -ENODEV;
1846
1847         if (!queue_work(nvme_workq, &dev->reset_work))
1848                 return -EBUSY;
1849
1850         flush_work(&dev->reset_work);
1851         return 0;
1852 }
1853
1854 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1855 {
1856         *val = readl(to_nvme_dev(ctrl)->bar + off);
1857         return 0;
1858 }
1859
1860 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1861 {
1862         writel(val, to_nvme_dev(ctrl)->bar + off);
1863         return 0;
1864 }
1865
1866 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1867 {
1868         *val = readq(to_nvme_dev(ctrl)->bar + off);
1869         return 0;
1870 }
1871
1872 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1873 {
1874         return nvme_reset(to_nvme_dev(ctrl));
1875 }
1876
1877 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1878         .name                   = "pcie",
1879         .module                 = THIS_MODULE,
1880         .reg_read32             = nvme_pci_reg_read32,
1881         .reg_write32            = nvme_pci_reg_write32,
1882         .reg_read64             = nvme_pci_reg_read64,
1883         .reset_ctrl             = nvme_pci_reset_ctrl,
1884         .free_ctrl              = nvme_pci_free_ctrl,
1885         .post_scan              = nvme_pci_post_scan,
1886         .submit_async_event     = nvme_pci_submit_async_event,
1887 };
1888
1889 static int nvme_dev_map(struct nvme_dev *dev)
1890 {
1891         struct pci_dev *pdev = to_pci_dev(dev->dev);
1892
1893         if (pci_request_mem_regions(pdev, "nvme"))
1894                 return -ENODEV;
1895
1896         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1897         if (!dev->bar)
1898                 goto release;
1899
1900        return 0;
1901   release:
1902        pci_release_mem_regions(pdev);
1903        return -ENODEV;
1904 }
1905
1906 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1907 {
1908         int node, result = -ENOMEM;
1909         struct nvme_dev *dev;
1910
1911         node = dev_to_node(&pdev->dev);
1912         if (node == NUMA_NO_NODE)
1913                 set_dev_node(&pdev->dev, first_memory_node);
1914
1915         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1916         if (!dev)
1917                 return -ENOMEM;
1918         dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
1919                                                         GFP_KERNEL, node);
1920         if (!dev->entry)
1921                 goto free;
1922         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1923                                                         GFP_KERNEL, node);
1924         if (!dev->queues)
1925                 goto free;
1926
1927         dev->dev = get_device(&pdev->dev);
1928         pci_set_drvdata(pdev, dev);
1929
1930         result = nvme_dev_map(dev);
1931         if (result)
1932                 goto free;
1933
1934         INIT_WORK(&dev->reset_work, nvme_reset_work);
1935         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1936         setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1937                 (unsigned long)dev);
1938         mutex_init(&dev->shutdown_lock);
1939         init_completion(&dev->ioq_wait);
1940
1941         result = nvme_setup_prp_pools(dev);
1942         if (result)
1943                 goto put_pci;
1944
1945         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
1946                         id->driver_data);
1947         if (result)
1948                 goto release_pools;
1949
1950         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
1951
1952         queue_work(nvme_workq, &dev->reset_work);
1953         return 0;
1954
1955  release_pools:
1956         nvme_release_prp_pools(dev);
1957  put_pci:
1958         put_device(dev->dev);
1959         nvme_dev_unmap(dev);
1960  free:
1961         kfree(dev->queues);
1962         kfree(dev->entry);
1963         kfree(dev);
1964         return result;
1965 }
1966
1967 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
1968 {
1969         struct nvme_dev *dev = pci_get_drvdata(pdev);
1970
1971         if (prepare)
1972                 nvme_dev_disable(dev, false);
1973         else
1974                 queue_work(nvme_workq, &dev->reset_work);
1975 }
1976
1977 static void nvme_shutdown(struct pci_dev *pdev)
1978 {
1979         struct nvme_dev *dev = pci_get_drvdata(pdev);
1980         nvme_dev_disable(dev, true);
1981 }
1982
1983 /*
1984  * The driver's remove may be called on a device in a partially initialized
1985  * state. This function must not have any dependencies on the device state in
1986  * order to proceed.
1987  */
1988 static void nvme_remove(struct pci_dev *pdev)
1989 {
1990         struct nvme_dev *dev = pci_get_drvdata(pdev);
1991
1992         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1993
1994         pci_set_drvdata(pdev, NULL);
1995
1996         if (!pci_device_is_present(pdev))
1997                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1998
1999         flush_work(&dev->reset_work);
2000         nvme_uninit_ctrl(&dev->ctrl);
2001         nvme_dev_disable(dev, true);
2002         nvme_dev_remove_admin(dev);
2003         nvme_free_queues(dev, 0);
2004         nvme_release_cmb(dev);
2005         nvme_release_prp_pools(dev);
2006         nvme_dev_unmap(dev);
2007         nvme_put_ctrl(&dev->ctrl);
2008 }
2009
2010 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2011 {
2012         int ret = 0;
2013
2014         if (numvfs == 0) {
2015                 if (pci_vfs_assigned(pdev)) {
2016                         dev_warn(&pdev->dev,
2017                                 "Cannot disable SR-IOV VFs while assigned\n");
2018                         return -EPERM;
2019                 }
2020                 pci_disable_sriov(pdev);
2021                 return 0;
2022         }
2023
2024         ret = pci_enable_sriov(pdev, numvfs);
2025         return ret ? ret : numvfs;
2026 }
2027
2028 #ifdef CONFIG_PM_SLEEP
2029 static int nvme_suspend(struct device *dev)
2030 {
2031         struct pci_dev *pdev = to_pci_dev(dev);
2032         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2033
2034         nvme_dev_disable(ndev, true);
2035         return 0;
2036 }
2037
2038 static int nvme_resume(struct device *dev)
2039 {
2040         struct pci_dev *pdev = to_pci_dev(dev);
2041         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2042
2043         queue_work(nvme_workq, &ndev->reset_work);
2044         return 0;
2045 }
2046 #endif
2047
2048 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2049
2050 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2051                                                 pci_channel_state_t state)
2052 {
2053         struct nvme_dev *dev = pci_get_drvdata(pdev);
2054
2055         /*
2056          * A frozen channel requires a reset. When detected, this method will
2057          * shutdown the controller to quiesce. The controller will be restarted
2058          * after the slot reset through driver's slot_reset callback.
2059          */
2060         switch (state) {
2061         case pci_channel_io_normal:
2062                 return PCI_ERS_RESULT_CAN_RECOVER;
2063         case pci_channel_io_frozen:
2064                 dev_warn(dev->ctrl.device,
2065                         "frozen state error detected, reset controller\n");
2066                 nvme_dev_disable(dev, false);
2067                 return PCI_ERS_RESULT_NEED_RESET;
2068         case pci_channel_io_perm_failure:
2069                 dev_warn(dev->ctrl.device,
2070                         "failure state error detected, request disconnect\n");
2071                 return PCI_ERS_RESULT_DISCONNECT;
2072         }
2073         return PCI_ERS_RESULT_NEED_RESET;
2074 }
2075
2076 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2077 {
2078         struct nvme_dev *dev = pci_get_drvdata(pdev);
2079
2080         dev_info(dev->ctrl.device, "restart after slot reset\n");
2081         pci_restore_state(pdev);
2082         queue_work(nvme_workq, &dev->reset_work);
2083         return PCI_ERS_RESULT_RECOVERED;
2084 }
2085
2086 static void nvme_error_resume(struct pci_dev *pdev)
2087 {
2088         pci_cleanup_aer_uncorrect_error_status(pdev);
2089 }
2090
2091 static const struct pci_error_handlers nvme_err_handler = {
2092         .error_detected = nvme_error_detected,
2093         .slot_reset     = nvme_slot_reset,
2094         .resume         = nvme_error_resume,
2095         .reset_notify   = nvme_reset_notify,
2096 };
2097
2098 /* Move to pci_ids.h later */
2099 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
2100
2101 static const struct pci_device_id nvme_id_table[] = {
2102         { PCI_VDEVICE(INTEL, 0x0953),
2103                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2104                                 NVME_QUIRK_DISCARD_ZEROES, },
2105         { PCI_VDEVICE(INTEL, 0x0a53),
2106                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2107                                 NVME_QUIRK_DISCARD_ZEROES, },
2108         { PCI_VDEVICE(INTEL, 0x0a54),
2109                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2110                                 NVME_QUIRK_DISCARD_ZEROES, },
2111         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2112                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2113         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2114                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2115         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2116         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2117         { 0, }
2118 };
2119 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2120
2121 static struct pci_driver nvme_driver = {
2122         .name           = "nvme",
2123         .id_table       = nvme_id_table,
2124         .probe          = nvme_probe,
2125         .remove         = nvme_remove,
2126         .shutdown       = nvme_shutdown,
2127         .driver         = {
2128                 .pm     = &nvme_dev_pm_ops,
2129         },
2130         .sriov_configure = nvme_pci_sriov_configure,
2131         .err_handler    = &nvme_err_handler,
2132 };
2133
2134 static int __init nvme_init(void)
2135 {
2136         int result;
2137
2138         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2139         if (!nvme_workq)
2140                 return -ENOMEM;
2141
2142         result = pci_register_driver(&nvme_driver);
2143         if (result)
2144                 destroy_workqueue(nvme_workq);
2145         return result;
2146 }
2147
2148 static void __exit nvme_exit(void)
2149 {
2150         pci_unregister_driver(&nvme_driver);
2151         destroy_workqueue(nvme_workq);
2152         _nvme_check_size();
2153 }
2154
2155 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2156 MODULE_LICENSE("GPL");
2157 MODULE_VERSION("1.0");
2158 module_init(nvme_init);
2159 module_exit(nvme_exit);