drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/blk-mq-pci.h>
  20 #include <linux/cpu.h>
  21 #include <linux/delay.h>
  22 #include <linux/errno.h>
  23 #include <linux/fs.h>
  24 #include <linux/genhd.h>
  25 #include <linux/hdreg.h>
  26 #include <linux/idr.h>
  27 #include <linux/init.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/io.h>
  30 #include <linux/kdev_t.h>
  31 #include <linux/kernel.h>
  32 #include <linux/mm.h>
  33 #include <linux/module.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/mutex.h>
  36 #include <linux/pci.h>
  37 #include <linux/poison.h>
  38 #include <linux/ptrace.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/t10-pi.h>
  42 #include <linux/timer.h>
  43 #include <linux/types.h>
  44 #include <linux/io-64-nonatomic-lo-hi.h>
  45 #include <asm/unaligned.h>
  46 #include <linux/sed-opal.h>
  47
  48 #include "nvme.h"
  49
  50 #define NVME_Q_DEPTH            1024
  51 #define NVME_AQ_DEPTH           256
  52 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  53 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  54
  55 /*
  56  * We handle AEN commands ourselves and don't even let the
  57  * block layer know about them.
  58  */
  59 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AERS)
  60
  61 static int use_threaded_interrupts;
  62 module_param(use_threaded_interrupts, int, 0);
  63
  64 static bool use_cmb_sqes = true;
  65 module_param(use_cmb_sqes, bool, 0644);
  66 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  67
  68 static struct workqueue_struct *nvme_workq;
  69
  70 struct nvme_dev;
  71 struct nvme_queue;
  72
  73 static int nvme_reset(struct nvme_dev *dev);
  74 static void nvme_process_cq(struct nvme_queue *nvmeq);
  75 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  76
  77 /*
  78  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  79  */
  80 struct nvme_dev {
  81         struct nvme_queue **queues;
  82         struct blk_mq_tag_set tagset;
  83         struct blk_mq_tag_set admin_tagset;
  84         u32 __iomem *dbs;
  85         struct device *dev;
  86         struct dma_pool *prp_page_pool;
  87         struct dma_pool *prp_small_pool;
  88         unsigned queue_count;
  89         unsigned online_queues;
  90         unsigned max_qid;
  91         int q_depth;
  92         u32 db_stride;
  93         void __iomem *bar;
  94         struct work_struct reset_work;
  95         struct work_struct remove_work;
  96         struct timer_list watchdog_timer;
  97         struct mutex shutdown_lock;
  98         bool subsystem;
  99         void __iomem *cmb;
 100         dma_addr_t cmb_dma_addr;
 101         u64 cmb_size;
 102         u32 cmbsz;
 103         u32 cmbloc;
 104         struct nvme_ctrl ctrl;
 105         struct completion ioq_wait;
 106 };
 107
 108 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 109 {
 110         return container_of(ctrl, struct nvme_dev, ctrl);
 111 }
 112
 113 /*
 114  * An NVM Express queue.  Each device has at least two (one for admin
 115  * commands and one for I/O commands).
 116  */
 117 struct nvme_queue {
 118         struct device *q_dmadev;
 119         struct nvme_dev *dev;
 120         char irqname[24];       /* nvme4294967295-65535\0 */
 121         spinlock_t q_lock;
 122         struct nvme_command *sq_cmds;
 123         struct nvme_command __iomem *sq_cmds_io;
 124         volatile struct nvme_completion *cqes;
 125         struct blk_mq_tags **tags;
 126         dma_addr_t sq_dma_addr;
 127         dma_addr_t cq_dma_addr;
 128         u32 __iomem *q_db;
 129         u16 q_depth;
 130         s16 cq_vector;
 131         u16 sq_tail;
 132         u16 cq_head;
 133         u16 qid;
 134         u8 cq_phase;
 135         u8 cqe_seen;
 136 };
 137
 138 /*
 139  * The nvme_iod describes the data in an I/O, including the list of PRP
 140  * entries.  You can't see it in this data structure because C doesn't let
 141  * me express that.  Use nvme_init_iod to ensure there's enough space
 142  * allocated to store the PRP list.
 143  */
 144 struct nvme_iod {
 145         struct nvme_request req;
 146         struct nvme_queue *nvmeq;
 147         int aborted;
 148         int npages;             /* In the PRP list. 0 means small pool in use */
 149         int nents;              /* Used in scatterlist */
 150         int length;             /* Of data, in bytes */
 151         dma_addr_t first_dma;
 152         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 153         struct scatterlist *sg;
 154         struct scatterlist inline_sg[0];
 155 };
 156
 157 /*
 158  * Check we didin't inadvertently grow the command struct
 159  */
 160 static inline void _nvme_check_size(void)
 161 {
 162         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 163         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 164         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 165         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 166         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 167         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 168         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 169         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 170         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
 171         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
 172         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 173         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 174 }
 175
 176 /*
 177  * Max size of iod being embedded in the request payload
 178  */
 179 #define NVME_INT_PAGES          2
 180 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 181
 182 /*
 183  * Will slightly overestimate the number of pages needed.  This is OK
 184  * as it only leads to a small amount of wasted memory for the lifetime of
 185  * the I/O.
 186  */
 187 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 188 {
 189         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 190                                       dev->ctrl.page_size);
 191         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 192 }
 193
 194 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 195                 unsigned int size, unsigned int nseg)
 196 {
 197         return sizeof(__le64 *) * nvme_npages(size, dev) +
 198                         sizeof(struct scatterlist) * nseg;
 199 }
 200
 201 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 202 {
 203         return sizeof(struct nvme_iod) +
 204                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 205 }
 206
 207 static int nvmeq_irq(struct nvme_queue *nvmeq)
 208 {
 209         return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector);
 210 }
 211
 212 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 213                                 unsigned int hctx_idx)
 214 {
 215         struct nvme_dev *dev = data;
 216         struct nvme_queue *nvmeq = dev->queues[0];
 217
 218         WARN_ON(hctx_idx != 0);
 219         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 220         WARN_ON(nvmeq->tags);
 221
 222         hctx->driver_data = nvmeq;
 223         nvmeq->tags = &dev->admin_tagset.tags[0];
 224         return 0;
 225 }
 226
 227 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 228 {
 229         struct nvme_queue *nvmeq = hctx->driver_data;
 230
 231         nvmeq->tags = NULL;
 232 }
 233
 234 static int nvme_admin_init_request(void *data, struct request *req,
 235                                 unsigned int hctx_idx, unsigned int rq_idx,
 236                                 unsigned int numa_node)
 237 {
 238         struct nvme_dev *dev = data;
 239         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 240         struct nvme_queue *nvmeq = dev->queues[0];
 241
 242         BUG_ON(!nvmeq);
 243         iod->nvmeq = nvmeq;
 244         return 0;
 245 }
 246
 247 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 248                           unsigned int hctx_idx)
 249 {
 250         struct nvme_dev *dev = data;
 251         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 252
 253         if (!nvmeq->tags)
 254                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 255
 256         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 257         hctx->driver_data = nvmeq;
 258         return 0;
 259 }
 260
 261 static int nvme_init_request(void *data, struct request *req,
 262                                 unsigned int hctx_idx, unsigned int rq_idx,
 263                                 unsigned int numa_node)
 264 {
 265         struct nvme_dev *dev = data;
 266         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 267         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 268
 269         BUG_ON(!nvmeq);
 270         iod->nvmeq = nvmeq;
 271         return 0;
 272 }
 273
 274 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 275 {
 276         struct nvme_dev *dev = set->driver_data;
 277
 278         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
 279 }
 280
 281 /**
 282  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 283  * @nvmeq: The queue to use
 284  * @cmd: The command to send
 285  *
 286  * Safe to use from interrupt context
 287  */
 288 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 289                                                 struct nvme_command *cmd)
 290 {
 291         u16 tail = nvmeq->sq_tail;
 292
 293         if (nvmeq->sq_cmds_io)
 294                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 295         else
 296                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 297
 298         if (++tail == nvmeq->q_depth)
 299                 tail = 0;
 300         writel(tail, nvmeq->q_db);
 301         nvmeq->sq_tail = tail;
 302 }
 303
 304 static __le64 **iod_list(struct request *req)
 305 {
 306         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 307         return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
 308 }
 309
 310 static int nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 311 {
 312         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 313         int nseg = blk_rq_nr_phys_segments(rq);
 314         unsigned int size = blk_rq_payload_bytes(rq);
 315
 316         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 317                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 318                 if (!iod->sg)
 319                         return BLK_MQ_RQ_QUEUE_BUSY;
 320         } else {
 321                 iod->sg = iod->inline_sg;
 322         }
 323
 324         iod->aborted = 0;
 325         iod->npages = -1;
 326         iod->nents = 0;
 327         iod->length = size;
 328
 329         if (!(rq->rq_flags & RQF_DONTPREP)) {
 330                 rq->retries = 0;
 331                 rq->rq_flags |= RQF_DONTPREP;
 332         }
 333         return BLK_MQ_RQ_QUEUE_OK;
 334 }
 335
 336 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 337 {
 338         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 339         const int last_prp = dev->ctrl.page_size / 8 - 1;
 340         int i;
 341         __le64 **list = iod_list(req);
 342         dma_addr_t prp_dma = iod->first_dma;
 343
 344         if (iod->npages == 0)
 345                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 346         for (i = 0; i < iod->npages; i++) {
 347                 __le64 *prp_list = list[i];
 348                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 349                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 350                 prp_dma = next_prp_dma;
 351         }
 352
 353         if (iod->sg != iod->inline_sg)
 354                 kfree(iod->sg);
 355 }
 356
 357 #ifdef CONFIG_BLK_DEV_INTEGRITY
 358 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 359 {
 360         if (be32_to_cpu(pi->ref_tag) == v)
 361                 pi->ref_tag = cpu_to_be32(p);
 362 }
 363
 364 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 365 {
 366         if (be32_to_cpu(pi->ref_tag) == p)
 367                 pi->ref_tag = cpu_to_be32(v);
 368 }
 369
 370 /**
 371  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 372  *
 373  * The virtual start sector is the one that was originally submitted by the
 374  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 375  * start sector may be different. Remap protection information to match the
 376  * physical LBA on writes, and back to the original seed on reads.
 377  *
 378  * Type 0 and 3 do not have a ref tag, so no remapping required.
 379  */
 380 static void nvme_dif_remap(struct request *req,
 381                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 382 {
 383         struct nvme_ns *ns = req->rq_disk->private_data;
 384         struct bio_integrity_payload *bip;
 385         struct t10_pi_tuple *pi;
 386         void *p, *pmap;
 387         u32 i, nlb, ts, phys, virt;
 388
 389         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 390                 return;
 391
 392         bip = bio_integrity(req->bio);
 393         if (!bip)
 394                 return;
 395
 396         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 397
 398         p = pmap;
 399         virt = bip_get_seed(bip);
 400         phys = nvme_block_nr(ns, blk_rq_pos(req));
 401         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 402         ts = ns->disk->queue->integrity.tuple_size;
 403
 404         for (i = 0; i < nlb; i++, virt++, phys++) {
 405                 pi = (struct t10_pi_tuple *)p;
 406                 dif_swap(phys, virt, pi);
 407                 p += ts;
 408         }
 409         kunmap_atomic(pmap);
 410 }
 411 #else /* CONFIG_BLK_DEV_INTEGRITY */
 412 static void nvme_dif_remap(struct request *req,
 413                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 414 {
 415 }
 416 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 417 {
 418 }
 419 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 420 {
 421 }
 422 #endif
 423
 424 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req)
 425 {
 426         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 427         struct dma_pool *pool;
 428         int length = blk_rq_payload_bytes(req);
 429         struct scatterlist *sg = iod->sg;
 430         int dma_len = sg_dma_len(sg);
 431         u64 dma_addr = sg_dma_address(sg);
 432         u32 page_size = dev->ctrl.page_size;
 433         int offset = dma_addr & (page_size - 1);
 434         __le64 *prp_list;
 435         __le64 **list = iod_list(req);
 436         dma_addr_t prp_dma;
 437         int nprps, i;
 438
 439         length -= (page_size - offset);
 440         if (length <= 0)
 441                 return true;
 442
 443         dma_len -= (page_size - offset);
 444         if (dma_len) {
 445                 dma_addr += (page_size - offset);
 446         } else {
 447                 sg = sg_next(sg);
 448                 dma_addr = sg_dma_address(sg);
 449                 dma_len = sg_dma_len(sg);
 450         }
 451
 452         if (length <= page_size) {
 453                 iod->first_dma = dma_addr;
 454                 return true;
 455         }
 456
 457         nprps = DIV_ROUND_UP(length, page_size);
 458         if (nprps <= (256 / 8)) {
 459                 pool = dev->prp_small_pool;
 460                 iod->npages = 0;
 461         } else {
 462                 pool = dev->prp_page_pool;
 463                 iod->npages = 1;
 464         }
 465
 466         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 467         if (!prp_list) {
 468                 iod->first_dma = dma_addr;
 469                 iod->npages = -1;
 470                 return false;
 471         }
 472         list[0] = prp_list;
 473         iod->first_dma = prp_dma;
 474         i = 0;
 475         for (;;) {
 476                 if (i == page_size >> 3) {
 477                         __le64 *old_prp_list = prp_list;
 478                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 479                         if (!prp_list)
 480                                 return false;
 481                         list[iod->npages++] = prp_list;
 482                         prp_list[0] = old_prp_list[i - 1];
 483                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 484                         i = 1;
 485                 }
 486                 prp_list[i++] = cpu_to_le64(dma_addr);
 487                 dma_len -= page_size;
 488                 dma_addr += page_size;
 489                 length -= page_size;
 490                 if (length <= 0)
 491                         break;
 492                 if (dma_len > 0)
 493                         continue;
 494                 BUG_ON(dma_len < 0);
 495                 sg = sg_next(sg);
 496                 dma_addr = sg_dma_address(sg);
 497                 dma_len = sg_dma_len(sg);
 498         }
 499
 500         return true;
 501 }
 502
 503 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
 504                 struct nvme_command *cmnd)
 505 {
 506         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 507         struct request_queue *q = req->q;
 508         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 509                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 510         int ret = BLK_MQ_RQ_QUEUE_ERROR;
 511
 512         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 513         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 514         if (!iod->nents)
 515                 goto out;
 516
 517         ret = BLK_MQ_RQ_QUEUE_BUSY;
 518         if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
 519                                 DMA_ATTR_NO_WARN))
 520                 goto out;
 521
 522         if (!nvme_setup_prps(dev, req))
 523                 goto out_unmap;
 524
 525         ret = BLK_MQ_RQ_QUEUE_ERROR;
 526         if (blk_integrity_rq(req)) {
 527                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 528                         goto out_unmap;
 529
 530                 sg_init_table(&iod->meta_sg, 1);
 531                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 532                         goto out_unmap;
 533
 534                 if (rq_data_dir(req))
 535                         nvme_dif_remap(req, nvme_dif_prep);
 536
 537                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 538                         goto out_unmap;
 539         }
 540
 541         cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 542         cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
 543         if (blk_integrity_rq(req))
 544                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 545         return BLK_MQ_RQ_QUEUE_OK;
 546
 547 out_unmap:
 548         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 549 out:
 550         return ret;
 551 }
 552
 553 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 554 {
 555         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 556         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 557                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 558
 559         if (iod->nents) {
 560                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 561                 if (blk_integrity_rq(req)) {
 562                         if (!rq_data_dir(req))
 563                                 nvme_dif_remap(req, nvme_dif_complete);
 564                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 565                 }
 566         }
 567
 568         nvme_cleanup_cmd(req);
 569         nvme_free_iod(dev, req);
 570 }
 571
 572 /*
 573  * NOTE: ns is NULL when called on the admin queue.
 574  */
 575 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 576                          const struct blk_mq_queue_data *bd)
 577 {
 578         struct nvme_ns *ns = hctx->queue->queuedata;
 579         struct nvme_queue *nvmeq = hctx->driver_data;
 580         struct nvme_dev *dev = nvmeq->dev;
 581         struct request *req = bd->rq;
 582         struct nvme_command cmnd;
 583         int ret = BLK_MQ_RQ_QUEUE_OK;
 584
 585         /*
 586          * If formated with metadata, require the block layer provide a buffer
 587          * unless this namespace is formated such that the metadata can be
 588          * stripped/generated by the controller with PRACT=1.
 589          */
 590         if (ns && ns->ms && !blk_integrity_rq(req)) {
 591                 if (!(ns->pi_type && ns->ms == 8) &&
 592                     !blk_rq_is_passthrough(req)) {
 593                         blk_mq_end_request(req, -EFAULT);
 594                         return BLK_MQ_RQ_QUEUE_OK;
 595                 }
 596         }
 597
 598         ret = nvme_setup_cmd(ns, req, &cmnd);
 599         if (ret != BLK_MQ_RQ_QUEUE_OK)
 600                 return ret;
 601
 602         ret = nvme_init_iod(req, dev);
 603         if (ret != BLK_MQ_RQ_QUEUE_OK)
 604                 goto out_free_cmd;
 605
 606         if (blk_rq_nr_phys_segments(req))
 607                 ret = nvme_map_data(dev, req, &cmnd);
 608
 609         if (ret != BLK_MQ_RQ_QUEUE_OK)
 610                 goto out_cleanup_iod;
 611
 612         blk_mq_start_request(req);
 613
 614         spin_lock_irq(&nvmeq->q_lock);
 615         if (unlikely(nvmeq->cq_vector < 0)) {
 616                 ret = BLK_MQ_RQ_QUEUE_ERROR;
 617                 spin_unlock_irq(&nvmeq->q_lock);
 618                 goto out_cleanup_iod;
 619         }
 620         __nvme_submit_cmd(nvmeq, &cmnd);
 621         nvme_process_cq(nvmeq);
 622         spin_unlock_irq(&nvmeq->q_lock);
 623         return BLK_MQ_RQ_QUEUE_OK;
 624 out_cleanup_iod:
 625         nvme_free_iod(dev, req);
 626 out_free_cmd:
 627         nvme_cleanup_cmd(req);
 628         return ret;
 629 }
 630
 631 static void nvme_complete_rq(struct request *req)
 632 {
 633         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 634         struct nvme_dev *dev = iod->nvmeq->dev;
 635         int error = 0;
 636
 637         nvme_unmap_data(dev, req);
 638
 639         if (unlikely(req->errors)) {
 640                 if (nvme_req_needs_retry(req, req->errors)) {
 641                         req->retries++;
 642                         nvme_requeue_req(req);
 643                         return;
 644                 }
 645
 646                 if (blk_rq_is_passthrough(req))
 647                         error = req->errors;
 648                 else
 649                         error = nvme_error_status(req->errors);
 650         }
 651
 652         if (unlikely(iod->aborted)) {
 653                 dev_warn(dev->ctrl.device,
 654                         "completing aborted command with status: %04x\n",
 655                         req->errors);
 656         }
 657
 658         blk_mq_end_request(req, error);
 659 }
 660
 661 /* We read the CQE phase first to check if the rest of the entry is valid */
 662 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 663                 u16 phase)
 664 {
 665         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 666 }
 667
 668 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
 669 {
 670         u16 head, phase;
 671
 672         head = nvmeq->cq_head;
 673         phase = nvmeq->cq_phase;
 674
 675         while (nvme_cqe_valid(nvmeq, head, phase)) {
 676                 struct nvme_completion cqe = nvmeq->cqes[head];
 677                 struct request *req;
 678
 679                 if (++head == nvmeq->q_depth) {
 680                         head = 0;
 681                         phase = !phase;
 682                 }
 683
 684                 if (tag && *tag == cqe.command_id)
 685                         *tag = -1;
 686
 687                 if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
 688                         dev_warn(nvmeq->dev->ctrl.device,
 689                                 "invalid id %d completed on queue %d\n",
 690                                 cqe.command_id, le16_to_cpu(cqe.sq_id));
 691                         continue;
 692                 }
 693
 694                 /*
 695                  * AEN requests are special as they don't time out and can
 696                  * survive any kind of queue freeze and often don't respond to
 697                  * aborts.  We don't even bother to allocate a struct request
 698                  * for them but rather special case them here.
 699                  */
 700                 if (unlikely(nvmeq->qid == 0 &&
 701                                 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 702                         nvme_complete_async_event(&nvmeq->dev->ctrl,
 703                                         cqe.status, &cqe.result);
 704                         continue;
 705                 }
 706
 707                 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
 708                 nvme_req(req)->result = cqe.result;
 709                 blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
 710         }
 711
 712         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
 713                 return;
 714
 715         if (likely(nvmeq->cq_vector >= 0))
 716                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 717         nvmeq->cq_head = head;
 718         nvmeq->cq_phase = phase;
 719
 720         nvmeq->cqe_seen = 1;
 721 }
 722
 723 static void nvme_process_cq(struct nvme_queue *nvmeq)
 724 {
 725         __nvme_process_cq(nvmeq, NULL);
 726 }
 727
 728 static irqreturn_t nvme_irq(int irq, void *data)
 729 {
 730         irqreturn_t result;
 731         struct nvme_queue *nvmeq = data;
 732         spin_lock(&nvmeq->q_lock);
 733         nvme_process_cq(nvmeq);
 734         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 735         nvmeq->cqe_seen = 0;
 736         spin_unlock(&nvmeq->q_lock);
 737         return result;
 738 }
 739
 740 static irqreturn_t nvme_irq_check(int irq, void *data)
 741 {
 742         struct nvme_queue *nvmeq = data;
 743         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 744                 return IRQ_WAKE_THREAD;
 745         return IRQ_NONE;
 746 }
 747
 748 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 749 {
 750         struct nvme_queue *nvmeq = hctx->driver_data;
 751
 752         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 753                 spin_lock_irq(&nvmeq->q_lock);
 754                 __nvme_process_cq(nvmeq, &tag);
 755                 spin_unlock_irq(&nvmeq->q_lock);
 756
 757                 if (tag == -1)
 758                         return 1;
 759         }
 760
 761         return 0;
 762 }
 763
 764 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
 765 {
 766         struct nvme_dev *dev = to_nvme_dev(ctrl);
 767         struct nvme_queue *nvmeq = dev->queues[0];
 768         struct nvme_command c;
 769
 770         memset(&c, 0, sizeof(c));
 771         c.common.opcode = nvme_admin_async_event;
 772         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
 773
 774         spin_lock_irq(&nvmeq->q_lock);
 775         __nvme_submit_cmd(nvmeq, &c);
 776         spin_unlock_irq(&nvmeq->q_lock);
 777 }
 778
 779 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 780 {
 781         struct nvme_command c;
 782
 783         memset(&c, 0, sizeof(c));
 784         c.delete_queue.opcode = opcode;
 785         c.delete_queue.qid = cpu_to_le16(id);
 786
 787         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 788 }
 789
 790 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 791                                                 struct nvme_queue *nvmeq)
 792 {
 793         struct nvme_command c;
 794         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 795
 796         /*
 797          * Note: we (ab)use the fact the the prp fields survive if no data
 798          * is attached to the request.
 799          */
 800         memset(&c, 0, sizeof(c));
 801         c.create_cq.opcode = nvme_admin_create_cq;
 802         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 803         c.create_cq.cqid = cpu_to_le16(qid);
 804         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 805         c.create_cq.cq_flags = cpu_to_le16(flags);
 806         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 807
 808         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 809 }
 810
 811 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 812                                                 struct nvme_queue *nvmeq)
 813 {
 814         struct nvme_command c;
 815         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
 816
 817         /*
 818          * Note: we (ab)use the fact the the prp fields survive if no data
 819          * is attached to the request.
 820          */
 821         memset(&c, 0, sizeof(c));
 822         c.create_sq.opcode = nvme_admin_create_sq;
 823         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 824         c.create_sq.sqid = cpu_to_le16(qid);
 825         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 826         c.create_sq.sq_flags = cpu_to_le16(flags);
 827         c.create_sq.cqid = cpu_to_le16(qid);
 828
 829         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 830 }
 831
 832 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 833 {
 834         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 835 }
 836
 837 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 838 {
 839         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 840 }
 841
 842 static void abort_endio(struct request *req, int error)
 843 {
 844         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 845         struct nvme_queue *nvmeq = iod->nvmeq;
 846         u16 status = req->errors;
 847
 848         dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
 849         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 850         blk_mq_free_request(req);
 851 }
 852
 853 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 854 {
 855         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 856         struct nvme_queue *nvmeq = iod->nvmeq;
 857         struct nvme_dev *dev = nvmeq->dev;
 858         struct request *abort_req;
 859         struct nvme_command cmd;
 860
 861         /*
 862          * Shutdown immediately if controller times out while starting. The
 863          * reset work will see the pci device disabled when it gets the forced
 864          * cancellation error. All outstanding requests are completed on
 865          * shutdown, so we return BLK_EH_HANDLED.
 866          */
 867         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
 868                 dev_warn(dev->ctrl.device,
 869                          "I/O %d QID %d timeout, disable controller\n",
 870                          req->tag, nvmeq->qid);
 871                 nvme_dev_disable(dev, false);
 872                 req->errors = NVME_SC_CANCELLED;
 873                 return BLK_EH_HANDLED;
 874         }
 875
 876         /*
 877          * Shutdown the controller immediately and schedule a reset if the
 878          * command was already aborted once before and still hasn't been
 879          * returned to the driver, or if this is the admin queue.
 880          */
 881         if (!nvmeq->qid || iod->aborted) {
 882                 dev_warn(dev->ctrl.device,
 883                          "I/O %d QID %d timeout, reset controller\n",
 884                          req->tag, nvmeq->qid);
 885                 nvme_dev_disable(dev, false);
 886                 nvme_reset(dev);
 887
 888                 /*
 889                  * Mark the request as handled, since the inline shutdown
 890                  * forces all outstanding requests to complete.
 891                  */
 892                 req->errors = NVME_SC_CANCELLED;
 893                 return BLK_EH_HANDLED;
 894         }
 895
 896         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
 897                 atomic_inc(&dev->ctrl.abort_limit);
 898                 return BLK_EH_RESET_TIMER;
 899         }
 900         iod->aborted = 1;
 901
 902         memset(&cmd, 0, sizeof(cmd));
 903         cmd.abort.opcode = nvme_admin_abort_cmd;
 904         cmd.abort.cid = req->tag;
 905         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
 906
 907         dev_warn(nvmeq->dev->ctrl.device,
 908                 "I/O %d QID %d timeout, aborting\n",
 909                  req->tag, nvmeq->qid);
 910
 911         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
 912                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
 913         if (IS_ERR(abort_req)) {
 914                 atomic_inc(&dev->ctrl.abort_limit);
 915                 return BLK_EH_RESET_TIMER;
 916         }
 917
 918         abort_req->timeout = ADMIN_TIMEOUT;
 919         abort_req->end_io_data = NULL;
 920         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
 921
 922         /*
 923          * The aborted req will be completed on receiving the abort req.
 924          * We enable the timer again. If hit twice, it'll cause a device reset,
 925          * as the device then is in a faulty state.
 926          */
 927         return BLK_EH_RESET_TIMER;
 928 }
 929
 930 static void nvme_free_queue(struct nvme_queue *nvmeq)
 931 {
 932         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
 933                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
 934         if (nvmeq->sq_cmds)
 935                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
 936                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
 937         kfree(nvmeq);
 938 }
 939
 940 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
 941 {
 942         int i;
 943
 944         for (i = dev->queue_count - 1; i >= lowest; i--) {
 945                 struct nvme_queue *nvmeq = dev->queues[i];
 946                 dev->queue_count--;
 947                 dev->queues[i] = NULL;
 948                 nvme_free_queue(nvmeq);
 949         }
 950 }
 951
 952 /**
 953  * nvme_suspend_queue - put queue into suspended state
 954  * @nvmeq - queue to suspend
 955  */
 956 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
 957 {
 958         int vector;
 959
 960         spin_lock_irq(&nvmeq->q_lock);
 961         if (nvmeq->cq_vector == -1) {
 962                 spin_unlock_irq(&nvmeq->q_lock);
 963                 return 1;
 964         }
 965         vector = nvmeq_irq(nvmeq);
 966         nvmeq->dev->online_queues--;
 967         nvmeq->cq_vector = -1;
 968         spin_unlock_irq(&nvmeq->q_lock);
 969
 970         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
 971                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
 972
 973         free_irq(vector, nvmeq);
 974
 975         return 0;
 976 }
 977
 978 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
 979 {
 980         struct nvme_queue *nvmeq = dev->queues[0];
 981
 982         if (!nvmeq)
 983                 return;
 984         if (nvme_suspend_queue(nvmeq))
 985                 return;
 986
 987         if (shutdown)
 988                 nvme_shutdown_ctrl(&dev->ctrl);
 989         else
 990                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
 991                                                 dev->bar + NVME_REG_CAP));
 992
 993         spin_lock_irq(&nvmeq->q_lock);
 994         nvme_process_cq(nvmeq);
 995         spin_unlock_irq(&nvmeq->q_lock);
 996 }
 997
 998 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
 999                                 int entry_size)
1000 {
1001         int q_depth = dev->q_depth;
1002         unsigned q_size_aligned = roundup(q_depth * entry_size,
1003                                           dev->ctrl.page_size);
1004
1005         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1006                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1007                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1008                 q_depth = div_u64(mem_per_q, entry_size);
1009
1010                 /*
1011                  * Ensure the reduced q_depth is above some threshold where it
1012                  * would be better to map queues in system memory with the
1013                  * original depth
1014                  */
1015                 if (q_depth < 64)
1016                         return -ENOMEM;
1017         }
1018
1019         return q_depth;
1020 }
1021
1022 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1023                                 int qid, int depth)
1024 {
1025         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1026                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1027                                                       dev->ctrl.page_size);
1028                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1029                 nvmeq->sq_cmds_io = dev->cmb + offset;
1030         } else {
1031                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1032                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1033                 if (!nvmeq->sq_cmds)
1034                         return -ENOMEM;
1035         }
1036
1037         return 0;
1038 }
1039
1040 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1041                                                         int depth, int node)
1042 {
1043         struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1044                                                         node);
1045         if (!nvmeq)
1046                 return NULL;
1047
1048         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1049                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1050         if (!nvmeq->cqes)
1051                 goto free_nvmeq;
1052
1053         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1054                 goto free_cqdma;
1055
1056         nvmeq->q_dmadev = dev->dev;
1057         nvmeq->dev = dev;
1058         snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1059                         dev->ctrl.instance, qid);
1060         spin_lock_init(&nvmeq->q_lock);
1061         nvmeq->cq_head = 0;
1062         nvmeq->cq_phase = 1;
1063         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1064         nvmeq->q_depth = depth;
1065         nvmeq->qid = qid;
1066         nvmeq->cq_vector = -1;
1067         dev->queues[qid] = nvmeq;
1068         dev->queue_count++;
1069
1070         return nvmeq;
1071
1072  free_cqdma:
1073         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1074                                                         nvmeq->cq_dma_addr);
1075  free_nvmeq:
1076         kfree(nvmeq);
1077         return NULL;
1078 }
1079
1080 static int queue_request_irq(struct nvme_queue *nvmeq)
1081 {
1082         if (use_threaded_interrupts)
1083                 return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check,
1084                                 nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq);
1085         else
1086                 return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED,
1087                                 nvmeq->irqname, nvmeq);
1088 }
1089
1090 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1091 {
1092         struct nvme_dev *dev = nvmeq->dev;
1093
1094         spin_lock_irq(&nvmeq->q_lock);
1095         nvmeq->sq_tail = 0;
1096         nvmeq->cq_head = 0;
1097         nvmeq->cq_phase = 1;
1098         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1099         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1100         dev->online_queues++;
1101         spin_unlock_irq(&nvmeq->q_lock);
1102 }
1103
1104 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1105 {
1106         struct nvme_dev *dev = nvmeq->dev;
1107         int result;
1108
1109         nvmeq->cq_vector = qid - 1;
1110         result = adapter_alloc_cq(dev, qid, nvmeq);
1111         if (result < 0)
1112                 return result;
1113
1114         result = adapter_alloc_sq(dev, qid, nvmeq);
1115         if (result < 0)
1116                 goto release_cq;
1117
1118         result = queue_request_irq(nvmeq);
1119         if (result < 0)
1120                 goto release_sq;
1121
1122         nvme_init_queue(nvmeq, qid);
1123         return result;
1124
1125  release_sq:
1126         adapter_delete_sq(dev, qid);
1127  release_cq:
1128         adapter_delete_cq(dev, qid);
1129         return result;
1130 }
1131
1132 static struct blk_mq_ops nvme_mq_admin_ops = {
1133         .queue_rq       = nvme_queue_rq,
1134         .complete       = nvme_complete_rq,
1135         .init_hctx      = nvme_admin_init_hctx,
1136         .exit_hctx      = nvme_admin_exit_hctx,
1137         .init_request   = nvme_admin_init_request,
1138         .timeout        = nvme_timeout,
1139 };
1140
1141 static struct blk_mq_ops nvme_mq_ops = {
1142         .queue_rq       = nvme_queue_rq,
1143         .complete       = nvme_complete_rq,
1144         .init_hctx      = nvme_init_hctx,
1145         .init_request   = nvme_init_request,
1146         .map_queues     = nvme_pci_map_queues,
1147         .timeout        = nvme_timeout,
1148         .poll           = nvme_poll,
1149 };
1150
1151 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1152 {
1153         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1154                 /*
1155                  * If the controller was reset during removal, it's possible
1156                  * user requests may be waiting on a stopped queue. Start the
1157                  * queue to flush these to completion.
1158                  */
1159                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1160                 blk_cleanup_queue(dev->ctrl.admin_q);
1161                 blk_mq_free_tag_set(&dev->admin_tagset);
1162         }
1163 }
1164
1165 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1166 {
1167         if (!dev->ctrl.admin_q) {
1168                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1169                 dev->admin_tagset.nr_hw_queues = 1;
1170
1171                 /*
1172                  * Subtract one to leave an empty queue entry for 'Full Queue'
1173                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1174                  */
1175                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1176                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1177                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1178                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1179                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1180                 dev->admin_tagset.driver_data = dev;
1181
1182                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1183                         return -ENOMEM;
1184
1185                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1186                 if (IS_ERR(dev->ctrl.admin_q)) {
1187                         blk_mq_free_tag_set(&dev->admin_tagset);
1188                         return -ENOMEM;
1189                 }
1190                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1191                         nvme_dev_remove_admin(dev);
1192                         dev->ctrl.admin_q = NULL;
1193                         return -ENODEV;
1194                 }
1195         } else
1196                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1197
1198         return 0;
1199 }
1200
1201 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1202 {
1203         int result;
1204         u32 aqa;
1205         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1206         struct nvme_queue *nvmeq;
1207
1208         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1209                                                 NVME_CAP_NSSRC(cap) : 0;
1210
1211         if (dev->subsystem &&
1212             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1213                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1214
1215         result = nvme_disable_ctrl(&dev->ctrl, cap);
1216         if (result < 0)
1217                 return result;
1218
1219         nvmeq = dev->queues[0];
1220         if (!nvmeq) {
1221                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1222                                         dev_to_node(dev->dev));
1223                 if (!nvmeq)
1224                         return -ENOMEM;
1225         }
1226
1227         aqa = nvmeq->q_depth - 1;
1228         aqa |= aqa << 16;
1229
1230         writel(aqa, dev->bar + NVME_REG_AQA);
1231         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1232         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1233
1234         result = nvme_enable_ctrl(&dev->ctrl, cap);
1235         if (result)
1236                 return result;
1237
1238         nvmeq->cq_vector = 0;
1239         result = queue_request_irq(nvmeq);
1240         if (result) {
1241                 nvmeq->cq_vector = -1;
1242                 return result;
1243         }
1244
1245         return result;
1246 }
1247
1248 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1249 {
1250
1251         /* If true, indicates loss of adapter communication, possibly by a
1252          * NVMe Subsystem reset.
1253          */
1254         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1255
1256         /* If there is a reset ongoing, we shouldn't reset again. */
1257         if (work_busy(&dev->reset_work))
1258                 return false;
1259
1260         /* We shouldn't reset unless the controller is on fatal error state
1261          * _or_ if we lost the communication with it.
1262          */
1263         if (!(csts & NVME_CSTS_CFS) && !nssro)
1264                 return false;
1265
1266         /* If PCI error recovery process is happening, we cannot reset or
1267          * the recovery mechanism will surely fail.
1268          */
1269         if (pci_channel_offline(to_pci_dev(dev->dev)))
1270                 return false;
1271
1272         return true;
1273 }
1274
1275 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1276 {
1277         /* Read a config register to help see what died. */
1278         u16 pci_status;
1279         int result;
1280
1281         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1282                                       &pci_status);
1283         if (result == PCIBIOS_SUCCESSFUL)
1284                 dev_warn(dev->dev,
1285                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1286                          csts, pci_status);
1287         else
1288                 dev_warn(dev->dev,
1289                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1290                          csts, result);
1291 }
1292
1293 static void nvme_watchdog_timer(unsigned long data)
1294 {
1295         struct nvme_dev *dev = (struct nvme_dev *)data;
1296         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1297
1298         /* Skip controllers under certain specific conditions. */
1299         if (nvme_should_reset(dev, csts)) {
1300                 if (!nvme_reset(dev))
1301                         nvme_warn_reset(dev, csts);
1302                 return;
1303         }
1304
1305         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1306 }
1307
1308 static int nvme_create_io_queues(struct nvme_dev *dev)
1309 {
1310         unsigned i, max;
1311         int ret = 0;
1312
1313         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1314                 /* vector == qid - 1, match nvme_create_queue */
1315                 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1316                      pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
1317                         ret = -ENOMEM;
1318                         break;
1319                 }
1320         }
1321
1322         max = min(dev->max_qid, dev->queue_count - 1);
1323         for (i = dev->online_queues; i <= max; i++) {
1324                 ret = nvme_create_queue(dev->queues[i], i);
1325                 if (ret)
1326                         break;
1327         }
1328
1329         /*
1330          * Ignore failing Create SQ/CQ commands, we can continue with less
1331          * than the desired aount of queues, and even a controller without
1332          * I/O queues an still be used to issue admin commands.  This might
1333          * be useful to upgrade a buggy firmware for example.
1334          */
1335         return ret >= 0 ? 0 : ret;
1336 }
1337
1338 static ssize_t nvme_cmb_show(struct device *dev,
1339                              struct device_attribute *attr,
1340                              char *buf)
1341 {
1342         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1343
1344         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1345                        ndev->cmbloc, ndev->cmbsz);
1346 }
1347 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1348
1349 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1350 {
1351         u64 szu, size, offset;
1352         resource_size_t bar_size;
1353         struct pci_dev *pdev = to_pci_dev(dev->dev);
1354         void __iomem *cmb;
1355         dma_addr_t dma_addr;
1356
1357         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1358         if (!(NVME_CMB_SZ(dev->cmbsz)))
1359                 return NULL;
1360         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1361
1362         if (!use_cmb_sqes)
1363                 return NULL;
1364
1365         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1366         size = szu * NVME_CMB_SZ(dev->cmbsz);
1367         offset = szu * NVME_CMB_OFST(dev->cmbloc);
1368         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1369
1370         if (offset > bar_size)
1371                 return NULL;
1372
1373         /*
1374          * Controllers may support a CMB size larger than their BAR,
1375          * for example, due to being behind a bridge. Reduce the CMB to
1376          * the reported size of the BAR
1377          */
1378         if (size > bar_size - offset)
1379                 size = bar_size - offset;
1380
1381         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1382         cmb = ioremap_wc(dma_addr, size);
1383         if (!cmb)
1384                 return NULL;
1385
1386         dev->cmb_dma_addr = dma_addr;
1387         dev->cmb_size = size;
1388         return cmb;
1389 }
1390
1391 static inline void nvme_release_cmb(struct nvme_dev *dev)
1392 {
1393         if (dev->cmb) {
1394                 iounmap(dev->cmb);
1395                 dev->cmb = NULL;
1396         }
1397 }
1398
1399 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1400 {
1401         return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1402 }
1403
1404 static int nvme_setup_io_queues(struct nvme_dev *dev)
1405 {
1406         struct nvme_queue *adminq = dev->queues[0];
1407         struct pci_dev *pdev = to_pci_dev(dev->dev);
1408         int result, nr_io_queues, size;
1409
1410         nr_io_queues = num_online_cpus();
1411         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1412         if (result < 0)
1413                 return result;
1414
1415         if (nr_io_queues == 0)
1416                 return 0;
1417
1418         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1419                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1420                                 sizeof(struct nvme_command));
1421                 if (result > 0)
1422                         dev->q_depth = result;
1423                 else
1424                         nvme_release_cmb(dev);
1425         }
1426
1427         size = db_bar_size(dev, nr_io_queues);
1428         if (size > 8192) {
1429                 iounmap(dev->bar);
1430                 do {
1431                         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1432                         if (dev->bar)
1433                                 break;
1434                         if (!--nr_io_queues)
1435                                 return -ENOMEM;
1436                         size = db_bar_size(dev, nr_io_queues);
1437                 } while (1);
1438                 dev->dbs = dev->bar + 4096;
1439                 adminq->q_db = dev->dbs;
1440         }
1441
1442         /* Deregister the admin queue's interrupt */
1443         free_irq(pci_irq_vector(pdev, 0), adminq);
1444
1445         /*
1446          * If we enable msix early due to not intx, disable it again before
1447          * setting up the full range we need.
1448          */
1449         pci_free_irq_vectors(pdev);
1450         nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1451                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1452         if (nr_io_queues <= 0)
1453                 return -EIO;
1454         dev->max_qid = nr_io_queues;
1455
1456         /*
1457          * Should investigate if there's a performance win from allocating
1458          * more queues than interrupt vectors; it might allow the submission
1459          * path to scale better, even if the receive path is limited by the
1460          * number of interrupts.
1461          */
1462
1463         result = queue_request_irq(adminq);
1464         if (result) {
1465                 adminq->cq_vector = -1;
1466                 return result;
1467         }
1468         return nvme_create_io_queues(dev);
1469 }
1470
1471 static void nvme_del_queue_end(struct request *req, int error)
1472 {
1473         struct nvme_queue *nvmeq = req->end_io_data;
1474
1475         blk_mq_free_request(req);
1476         complete(&nvmeq->dev->ioq_wait);
1477 }
1478
1479 static void nvme_del_cq_end(struct request *req, int error)
1480 {
1481         struct nvme_queue *nvmeq = req->end_io_data;
1482
1483         if (!error) {
1484                 unsigned long flags;
1485
1486                 /*
1487                  * We might be called with the AQ q_lock held
1488                  * and the I/O queue q_lock should always
1489                  * nest inside the AQ one.
1490                  */
1491                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1492                                         SINGLE_DEPTH_NESTING);
1493                 nvme_process_cq(nvmeq);
1494                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1495         }
1496
1497         nvme_del_queue_end(req, error);
1498 }
1499
1500 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1501 {
1502         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1503         struct request *req;
1504         struct nvme_command cmd;
1505
1506         memset(&cmd, 0, sizeof(cmd));
1507         cmd.delete_queue.opcode = opcode;
1508         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1509
1510         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1511         if (IS_ERR(req))
1512                 return PTR_ERR(req);
1513
1514         req->timeout = ADMIN_TIMEOUT;
1515         req->end_io_data = nvmeq;
1516
1517         blk_execute_rq_nowait(q, NULL, req, false,
1518                         opcode == nvme_admin_delete_cq ?
1519                                 nvme_del_cq_end : nvme_del_queue_end);
1520         return 0;
1521 }
1522
1523 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1524 {
1525         int pass;
1526         unsigned long timeout;
1527         u8 opcode = nvme_admin_delete_sq;
1528
1529         for (pass = 0; pass < 2; pass++) {
1530                 int sent = 0, i = queues;
1531
1532                 reinit_completion(&dev->ioq_wait);
1533  retry:
1534                 timeout = ADMIN_TIMEOUT;
1535                 for (; i > 0; i--, sent++)
1536                         if (nvme_delete_queue(dev->queues[i], opcode))
1537                                 break;
1538
1539                 while (sent--) {
1540                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1541                         if (timeout == 0)
1542                                 return;
1543                         if (i)
1544                                 goto retry;
1545                 }
1546                 opcode = nvme_admin_delete_cq;
1547         }
1548 }
1549
1550 /*
1551  * Return: error value if an error occurred setting up the queues or calling
1552  * Identify Device.  0 if these succeeded, even if adding some of the
1553  * namespaces failed.  At the moment, these failures are silent.  TBD which
1554  * failures should be reported.
1555  */
1556 static int nvme_dev_add(struct nvme_dev *dev)
1557 {
1558         if (!dev->ctrl.tagset) {
1559                 dev->tagset.ops = &nvme_mq_ops;
1560                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1561                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1562                 dev->tagset.numa_node = dev_to_node(dev->dev);
1563                 dev->tagset.queue_depth =
1564                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1565                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1566                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1567                 dev->tagset.driver_data = dev;
1568
1569                 if (blk_mq_alloc_tag_set(&dev->tagset))
1570                         return 0;
1571                 dev->ctrl.tagset = &dev->tagset;
1572         } else {
1573                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1574
1575                 /* Free previously allocated queues that are no longer usable */
1576                 nvme_free_queues(dev, dev->online_queues);
1577         }
1578
1579         return 0;
1580 }
1581
1582 static int nvme_pci_enable(struct nvme_dev *dev)
1583 {
1584         u64 cap;
1585         int result = -ENOMEM;
1586         struct pci_dev *pdev = to_pci_dev(dev->dev);
1587
1588         if (pci_enable_device_mem(pdev))
1589                 return result;
1590
1591         pci_set_master(pdev);
1592
1593         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1594             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1595                 goto disable;
1596
1597         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1598                 result = -ENODEV;
1599                 goto disable;
1600         }
1601
1602         /*
1603          * Some devices and/or platforms don't advertise or work with INTx
1604          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1605          * adjust this later.
1606          */
1607         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1608         if (result < 0)
1609                 return result;
1610
1611         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1612
1613         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1614         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1615         dev->dbs = dev->bar + 4096;
1616
1617         /*
1618          * Temporary fix for the Apple controller found in the MacBook8,1 and
1619          * some MacBook7,1 to avoid controller resets and data loss.
1620          */
1621         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1622                 dev->q_depth = 2;
1623                 dev_warn(dev->dev, "detected Apple NVMe controller, set "
1624                         "queue depth=%u to work around controller resets\n",
1625                         dev->q_depth);
1626         }
1627
1628         /*
1629          * CMBs can currently only exist on >=1.2 PCIe devices. We only
1630          * populate sysfs if a CMB is implemented. Note that we add the
1631          * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1632          * it on exit. Since nvme_dev_attrs_group has no name we can pass
1633          * NULL as final argument to sysfs_add_file_to_group.
1634          */
1635
1636         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1637                 dev->cmb = nvme_map_cmb(dev);
1638
1639                 if (dev->cmbsz) {
1640                         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1641                                                     &dev_attr_cmb.attr, NULL))
1642                                 dev_warn(dev->dev,
1643                                          "failed to add sysfs attribute for CMB\n");
1644                 }
1645         }
1646
1647         pci_enable_pcie_error_reporting(pdev);
1648         pci_save_state(pdev);
1649         return 0;
1650
1651  disable:
1652         pci_disable_device(pdev);
1653         return result;
1654 }
1655
1656 static void nvme_dev_unmap(struct nvme_dev *dev)
1657 {
1658         if (dev->bar)
1659                 iounmap(dev->bar);
1660         pci_release_mem_regions(to_pci_dev(dev->dev));
1661 }
1662
1663 static void nvme_pci_disable(struct nvme_dev *dev)
1664 {
1665         struct pci_dev *pdev = to_pci_dev(dev->dev);
1666
1667         pci_free_irq_vectors(pdev);
1668
1669         if (pci_is_enabled(pdev)) {
1670                 pci_disable_pcie_error_reporting(pdev);
1671                 pci_disable_device(pdev);
1672         }
1673 }
1674
1675 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1676 {
1677         int i, queues;
1678         bool dead = true;
1679         struct pci_dev *pdev = to_pci_dev(dev->dev);
1680
1681         del_timer_sync(&dev->watchdog_timer);
1682
1683         mutex_lock(&dev->shutdown_lock);
1684         if (pci_is_enabled(pdev)) {
1685                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1686
1687                 if (dev->ctrl.state == NVME_CTRL_LIVE)
1688                         nvme_start_freeze(&dev->ctrl);
1689                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
1690                         pdev->error_state  != pci_channel_io_normal);
1691         }
1692
1693         /*
1694          * Give the controller a chance to complete all entered requests if
1695          * doing a safe shutdown.
1696          */
1697         if (!dead && shutdown)
1698                 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
1699         nvme_stop_queues(&dev->ctrl);
1700
1701         queues = dev->online_queues - 1;
1702         for (i = dev->queue_count - 1; i > 0; i--)
1703                 nvme_suspend_queue(dev->queues[i]);
1704
1705         if (dead) {
1706                 /* A device might become IO incapable very soon during
1707                  * probe, before the admin queue is configured. Thus,
1708                  * queue_count can be 0 here.
1709                  */
1710                 if (dev->queue_count)
1711                         nvme_suspend_queue(dev->queues[0]);
1712         } else {
1713                 nvme_disable_io_queues(dev, queues);
1714                 nvme_disable_admin_queue(dev, shutdown);
1715         }
1716         nvme_pci_disable(dev);
1717
1718         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
1719         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
1720
1721         /*
1722          * The driver will not be starting up queues again if shutting down so
1723          * must flush all entered requests to their failed completion to avoid
1724          * deadlocking blk-mq hot-cpu notifier.
1725          */
1726         if (shutdown)
1727                 nvme_start_queues(&dev->ctrl);
1728         mutex_unlock(&dev->shutdown_lock);
1729 }
1730
1731 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1732 {
1733         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1734                                                 PAGE_SIZE, PAGE_SIZE, 0);
1735         if (!dev->prp_page_pool)
1736                 return -ENOMEM;
1737
1738         /* Optimisation for I/Os between 4k and 128k */
1739         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1740                                                 256, 256, 0);
1741         if (!dev->prp_small_pool) {
1742                 dma_pool_destroy(dev->prp_page_pool);
1743                 return -ENOMEM;
1744         }
1745         return 0;
1746 }
1747
1748 static void nvme_release_prp_pools(struct nvme_dev *dev)
1749 {
1750         dma_pool_destroy(dev->prp_page_pool);
1751         dma_pool_destroy(dev->prp_small_pool);
1752 }
1753
1754 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1755 {
1756         struct nvme_dev *dev = to_nvme_dev(ctrl);
1757
1758         put_device(dev->dev);
1759         if (dev->tagset.tags)
1760                 blk_mq_free_tag_set(&dev->tagset);
1761         if (dev->ctrl.admin_q)
1762                 blk_put_queue(dev->ctrl.admin_q);
1763         kfree(dev->queues);
1764         free_opal_dev(dev->ctrl.opal_dev);
1765         kfree(dev);
1766 }
1767
1768 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1769 {
1770         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1771
1772         kref_get(&dev->ctrl.kref);
1773         nvme_dev_disable(dev, false);
1774         if (!schedule_work(&dev->remove_work))
1775                 nvme_put_ctrl(&dev->ctrl);
1776 }
1777
1778 static void nvme_reset_work(struct work_struct *work)
1779 {
1780         struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1781         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
1782         int result = -ENODEV;
1783
1784         if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1785                 goto out;
1786
1787         /*
1788          * If we're called to reset a live controller first shut it down before
1789          * moving on.
1790          */
1791         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1792                 nvme_dev_disable(dev, false);
1793
1794         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1795                 goto out;
1796
1797         result = nvme_pci_enable(dev);
1798         if (result)
1799                 goto out;
1800
1801         result = nvme_configure_admin_queue(dev);
1802         if (result)
1803                 goto out;
1804
1805         nvme_init_queue(dev->queues[0], 0);
1806         result = nvme_alloc_admin_tags(dev);
1807         if (result)
1808                 goto out;
1809
1810         result = nvme_init_identify(&dev->ctrl);
1811         if (result)
1812                 goto out;
1813
1814         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
1815                 if (!dev->ctrl.opal_dev)
1816                         dev->ctrl.opal_dev =
1817                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
1818                 else if (was_suspend)
1819                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
1820         } else {
1821                 free_opal_dev(dev->ctrl.opal_dev);
1822                 dev->ctrl.opal_dev = NULL;
1823         }
1824
1825         result = nvme_setup_io_queues(dev);
1826         if (result)
1827                 goto out;
1828
1829         /*
1830          * A controller that can not execute IO typically requires user
1831          * intervention to correct. For such degraded controllers, the driver
1832          * should not submit commands the user did not request, so skip
1833          * registering for asynchronous event notification on this condition.
1834          */
1835         if (dev->online_queues > 1)
1836                 nvme_queue_async_events(&dev->ctrl);
1837
1838         mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1839
1840         /*
1841          * Keep the controller around but remove all namespaces if we don't have
1842          * any working I/O queue.
1843          */
1844         if (dev->online_queues < 2) {
1845                 dev_warn(dev->ctrl.device, "IO queues not created\n");
1846                 nvme_kill_queues(&dev->ctrl);
1847                 nvme_remove_namespaces(&dev->ctrl);
1848         } else {
1849                 nvme_start_queues(&dev->ctrl);
1850                 nvme_wait_freeze(&dev->ctrl);
1851                 nvme_dev_add(dev);
1852                 nvme_unfreeze(&dev->ctrl);
1853         }
1854
1855         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1856                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1857                 goto out;
1858         }
1859
1860         if (dev->online_queues > 1)
1861                 nvme_queue_scan(&dev->ctrl);
1862         return;
1863
1864  out:
1865         nvme_remove_dead_ctrl(dev, result);
1866 }
1867
1868 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1869 {
1870         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1871         struct pci_dev *pdev = to_pci_dev(dev->dev);
1872
1873         nvme_kill_queues(&dev->ctrl);
1874         if (pci_get_drvdata(pdev))
1875                 device_release_driver(&pdev->dev);
1876         nvme_put_ctrl(&dev->ctrl);
1877 }
1878
1879 static int nvme_reset(struct nvme_dev *dev)
1880 {
1881         if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1882                 return -ENODEV;
1883         if (work_busy(&dev->reset_work))
1884                 return -ENODEV;
1885         if (!queue_work(nvme_workq, &dev->reset_work))
1886                 return -EBUSY;
1887         return 0;
1888 }
1889
1890 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1891 {
1892         *val = readl(to_nvme_dev(ctrl)->bar + off);
1893         return 0;
1894 }
1895
1896 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1897 {
1898         writel(val, to_nvme_dev(ctrl)->bar + off);
1899         return 0;
1900 }
1901
1902 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1903 {
1904         *val = readq(to_nvme_dev(ctrl)->bar + off);
1905         return 0;
1906 }
1907
1908 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1909 {
1910         struct nvme_dev *dev = to_nvme_dev(ctrl);
1911         int ret = nvme_reset(dev);
1912
1913         if (!ret)
1914                 flush_work(&dev->reset_work);
1915         return ret;
1916 }
1917
1918 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1919         .name                   = "pcie",
1920         .module                 = THIS_MODULE,
1921         .reg_read32             = nvme_pci_reg_read32,
1922         .reg_write32            = nvme_pci_reg_write32,
1923         .reg_read64             = nvme_pci_reg_read64,
1924         .reset_ctrl             = nvme_pci_reset_ctrl,
1925         .free_ctrl              = nvme_pci_free_ctrl,
1926         .submit_async_event     = nvme_pci_submit_async_event,
1927 };
1928
1929 static int nvme_dev_map(struct nvme_dev *dev)
1930 {
1931         struct pci_dev *pdev = to_pci_dev(dev->dev);
1932
1933         if (pci_request_mem_regions(pdev, "nvme"))
1934                 return -ENODEV;
1935
1936         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1937         if (!dev->bar)
1938                 goto release;
1939
1940         return 0;
1941   release:
1942         pci_release_mem_regions(pdev);
1943         return -ENODEV;
1944 }
1945
1946 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1947 {
1948         int node, result = -ENOMEM;
1949         struct nvme_dev *dev;
1950
1951         node = dev_to_node(&pdev->dev);
1952         if (node == NUMA_NO_NODE)
1953                 set_dev_node(&pdev->dev, first_memory_node);
1954
1955         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1956         if (!dev)
1957                 return -ENOMEM;
1958         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1959                                                         GFP_KERNEL, node);
1960         if (!dev->queues)
1961                 goto free;
1962
1963         dev->dev = get_device(&pdev->dev);
1964         pci_set_drvdata(pdev, dev);
1965
1966         result = nvme_dev_map(dev);
1967         if (result)
1968                 goto free;
1969
1970         INIT_WORK(&dev->reset_work, nvme_reset_work);
1971         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1972         setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1973                 (unsigned long)dev);
1974         mutex_init(&dev->shutdown_lock);
1975         init_completion(&dev->ioq_wait);
1976
1977         result = nvme_setup_prp_pools(dev);
1978         if (result)
1979                 goto put_pci;
1980
1981         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
1982                         id->driver_data);
1983         if (result)
1984                 goto release_pools;
1985
1986         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
1987
1988         queue_work(nvme_workq, &dev->reset_work);
1989         return 0;
1990
1991  release_pools:
1992         nvme_release_prp_pools(dev);
1993  put_pci:
1994         put_device(dev->dev);
1995         nvme_dev_unmap(dev);
1996  free:
1997         kfree(dev->queues);
1998         kfree(dev);
1999         return result;
2000 }
2001
2002 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2003 {
2004         struct nvme_dev *dev = pci_get_drvdata(pdev);
2005
2006         if (prepare)
2007                 nvme_dev_disable(dev, false);
2008         else
2009                 nvme_reset(dev);
2010 }
2011
2012 static void nvme_shutdown(struct pci_dev *pdev)
2013 {
2014         struct nvme_dev *dev = pci_get_drvdata(pdev);
2015         nvme_dev_disable(dev, true);
2016 }
2017
2018 /*
2019  * The driver's remove may be called on a device in a partially initialized
2020  * state. This function must not have any dependencies on the device state in
2021  * order to proceed.
2022  */
2023 static void nvme_remove(struct pci_dev *pdev)
2024 {
2025         struct nvme_dev *dev = pci_get_drvdata(pdev);
2026
2027         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2028
2029         pci_set_drvdata(pdev, NULL);
2030
2031         if (!pci_device_is_present(pdev)) {
2032                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2033                 nvme_dev_disable(dev, false);
2034         }
2035
2036         flush_work(&dev->reset_work);
2037         nvme_uninit_ctrl(&dev->ctrl);
2038         nvme_dev_disable(dev, true);
2039         nvme_dev_remove_admin(dev);
2040         nvme_free_queues(dev, 0);
2041         nvme_release_cmb(dev);
2042         nvme_release_prp_pools(dev);
2043         nvme_dev_unmap(dev);
2044         nvme_put_ctrl(&dev->ctrl);
2045 }
2046
2047 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2048 {
2049         int ret = 0;
2050
2051         if (numvfs == 0) {
2052                 if (pci_vfs_assigned(pdev)) {
2053                         dev_warn(&pdev->dev,
2054                                 "Cannot disable SR-IOV VFs while assigned\n");
2055                         return -EPERM;
2056                 }
2057                 pci_disable_sriov(pdev);
2058                 return 0;
2059         }
2060
2061         ret = pci_enable_sriov(pdev, numvfs);
2062         return ret ? ret : numvfs;
2063 }
2064
2065 #ifdef CONFIG_PM_SLEEP
2066 static int nvme_suspend(struct device *dev)
2067 {
2068         struct pci_dev *pdev = to_pci_dev(dev);
2069         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2070
2071         nvme_dev_disable(ndev, true);
2072         return 0;
2073 }
2074
2075 static int nvme_resume(struct device *dev)
2076 {
2077         struct pci_dev *pdev = to_pci_dev(dev);
2078         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2079
2080         nvme_reset(ndev);
2081         return 0;
2082 }
2083 #endif
2084
2085 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2086
2087 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2088                                                 pci_channel_state_t state)
2089 {
2090         struct nvme_dev *dev = pci_get_drvdata(pdev);
2091
2092         /*
2093          * A frozen channel requires a reset. When detected, this method will
2094          * shutdown the controller to quiesce. The controller will be restarted
2095          * after the slot reset through driver's slot_reset callback.
2096          */
2097         switch (state) {
2098         case pci_channel_io_normal:
2099                 return PCI_ERS_RESULT_CAN_RECOVER;
2100         case pci_channel_io_frozen:
2101                 dev_warn(dev->ctrl.device,
2102                         "frozen state error detected, reset controller\n");
2103                 nvme_dev_disable(dev, false);
2104                 return PCI_ERS_RESULT_NEED_RESET;
2105         case pci_channel_io_perm_failure:
2106                 dev_warn(dev->ctrl.device,
2107                         "failure state error detected, request disconnect\n");
2108                 return PCI_ERS_RESULT_DISCONNECT;
2109         }
2110         return PCI_ERS_RESULT_NEED_RESET;
2111 }
2112
2113 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2114 {
2115         struct nvme_dev *dev = pci_get_drvdata(pdev);
2116
2117         dev_info(dev->ctrl.device, "restart after slot reset\n");
2118         pci_restore_state(pdev);
2119         nvme_reset(dev);
2120         return PCI_ERS_RESULT_RECOVERED;
2121 }
2122
2123 static void nvme_error_resume(struct pci_dev *pdev)
2124 {
2125         pci_cleanup_aer_uncorrect_error_status(pdev);
2126 }
2127
2128 static const struct pci_error_handlers nvme_err_handler = {
2129         .error_detected = nvme_error_detected,
2130         .slot_reset     = nvme_slot_reset,
2131         .resume         = nvme_error_resume,
2132         .reset_notify   = nvme_reset_notify,
2133 };
2134
2135 static const struct pci_device_id nvme_id_table[] = {
2136         { PCI_VDEVICE(INTEL, 0x0953),
2137                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2138                                 NVME_QUIRK_DISCARD_ZEROES, },
2139         { PCI_VDEVICE(INTEL, 0x0a53),
2140                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2141                                 NVME_QUIRK_DISCARD_ZEROES, },
2142         { PCI_VDEVICE(INTEL, 0x0a54),
2143                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2144                                 NVME_QUIRK_DISCARD_ZEROES, },
2145         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2146                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2147         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2148                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2149         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2150                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2151         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2152         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2153         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2154         { 0, }
2155 };
2156 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2157
2158 static struct pci_driver nvme_driver = {
2159         .name           = "nvme",
2160         .id_table       = nvme_id_table,
2161         .probe          = nvme_probe,
2162         .remove         = nvme_remove,
2163         .shutdown       = nvme_shutdown,
2164         .driver         = {
2165                 .pm     = &nvme_dev_pm_ops,
2166         },
2167         .sriov_configure = nvme_pci_sriov_configure,
2168         .err_handler    = &nvme_err_handler,
2169 };
2170
2171 static int __init nvme_init(void)
2172 {
2173         int result;
2174
2175         nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2176         if (!nvme_workq)
2177                 return -ENOMEM;
2178
2179         result = pci_register_driver(&nvme_driver);
2180         if (result)
2181                 destroy_workqueue(nvme_workq);
2182         return result;
2183 }
2184
2185 static void __exit nvme_exit(void)
2186 {
2187         pci_unregister_driver(&nvme_driver);
2188         destroy_workqueue(nvme_workq);
2189         _nvme_check_size();
2190 }
2191
2192 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2193 MODULE_LICENSE("GPL");
2194 MODULE_VERSION("1.0");
2195 module_init(nvme_init);
2196 module_exit(nvme_exit);