2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
16 #include <linux/of_pci.h>
17 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/string.h>
23 #include <linux/log2.h>
24 #include <linux/pci-aspm.h>
25 #include <linux/pm_wakeup.h>
26 #include <linux/interrupt.h>
27 #include <linux/device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/pci_hotplug.h>
30 #include <linux/vmalloc.h>
31 #include <asm/setup.h>
33 #include <linux/aer.h>
36 const char *pci_power_names[] = {
37 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
39 EXPORT_SYMBOL_GPL(pci_power_names);
41 int isa_dma_bridge_buggy;
42 EXPORT_SYMBOL(isa_dma_bridge_buggy);
45 EXPORT_SYMBOL(pci_pci_problems);
47 unsigned int pci_pm_d3_delay;
49 static void pci_pme_list_scan(struct work_struct *work);
51 static LIST_HEAD(pci_pme_list);
52 static DEFINE_MUTEX(pci_pme_list_mutex);
53 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
55 struct pci_pme_device {
56 struct list_head list;
60 #define PME_TIMEOUT 1000 /* How long between PME checks */
62 static void pci_dev_d3_sleep(struct pci_dev *dev)
64 unsigned int delay = dev->d3_delay;
66 if (delay < pci_pm_d3_delay)
67 delay = pci_pm_d3_delay;
72 #ifdef CONFIG_PCI_DOMAINS
73 int pci_domains_supported = 1;
76 #define DEFAULT_CARDBUS_IO_SIZE (256)
77 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
78 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
79 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
80 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
82 #define DEFAULT_HOTPLUG_IO_SIZE (256)
83 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
84 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
85 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
86 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
88 #define DEFAULT_HOTPLUG_BUS_SIZE 1
89 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
91 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
94 * The default CLS is used if arch didn't set CLS explicitly and not
95 * all pci devices agree on the same value. Arch can override either
96 * the dfl or actual value as it sees fit. Don't forget this is
97 * measured in 32-bit words, not bytes.
99 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
100 u8 pci_cache_line_size;
103 * If we set up a device for bus mastering, we need to check the latency
104 * timer as certain BIOSes forget to set it properly.
106 unsigned int pcibios_max_latency = 255;
108 /* If set, the PCIe ARI capability will not be used. */
109 static bool pcie_ari_disabled;
111 /* Disable bridge_d3 for all PCIe ports */
112 static bool pci_bridge_d3_disable;
113 /* Force bridge_d3 for all PCIe ports */
114 static bool pci_bridge_d3_force;
116 static int __init pcie_port_pm_setup(char *str)
118 if (!strcmp(str, "off"))
119 pci_bridge_d3_disable = true;
120 else if (!strcmp(str, "force"))
121 pci_bridge_d3_force = true;
124 __setup("pcie_port_pm=", pcie_port_pm_setup);
127 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
128 * @bus: pointer to PCI bus structure to search
130 * Given a PCI bus, returns the highest PCI bus number present in the set
131 * including the given PCI bus and its list of child PCI buses.
133 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
136 unsigned char max, n;
138 max = bus->busn_res.end;
139 list_for_each_entry(tmp, &bus->children, node) {
140 n = pci_bus_max_busnr(tmp);
146 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
148 #ifdef CONFIG_HAS_IOMEM
149 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
151 struct resource *res = &pdev->resource[bar];
154 * Make sure the BAR is actually a memory resource, not an IO resource
156 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
157 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
160 return ioremap_nocache(res->start, resource_size(res));
162 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
164 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
167 * Make sure the BAR is actually a memory resource, not an IO resource
169 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
173 return ioremap_wc(pci_resource_start(pdev, bar),
174 pci_resource_len(pdev, bar));
176 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
180 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
181 u8 pos, int cap, int *ttl)
186 pci_bus_read_config_byte(bus, devfn, pos, &pos);
192 pci_bus_read_config_word(bus, devfn, pos, &ent);
204 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
207 int ttl = PCI_FIND_CAP_TTL;
209 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
212 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
214 return __pci_find_next_cap(dev->bus, dev->devfn,
215 pos + PCI_CAP_LIST_NEXT, cap);
217 EXPORT_SYMBOL_GPL(pci_find_next_capability);
219 static int __pci_bus_find_cap_start(struct pci_bus *bus,
220 unsigned int devfn, u8 hdr_type)
224 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
225 if (!(status & PCI_STATUS_CAP_LIST))
229 case PCI_HEADER_TYPE_NORMAL:
230 case PCI_HEADER_TYPE_BRIDGE:
231 return PCI_CAPABILITY_LIST;
232 case PCI_HEADER_TYPE_CARDBUS:
233 return PCI_CB_CAPABILITY_LIST;
240 * pci_find_capability - query for devices' capabilities
241 * @dev: PCI device to query
242 * @cap: capability code
244 * Tell if a device supports a given PCI capability.
245 * Returns the address of the requested capability structure within the
246 * device's PCI configuration space or 0 in case the device does not
247 * support it. Possible values for @cap:
249 * %PCI_CAP_ID_PM Power Management
250 * %PCI_CAP_ID_AGP Accelerated Graphics Port
251 * %PCI_CAP_ID_VPD Vital Product Data
252 * %PCI_CAP_ID_SLOTID Slot Identification
253 * %PCI_CAP_ID_MSI Message Signalled Interrupts
254 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
255 * %PCI_CAP_ID_PCIX PCI-X
256 * %PCI_CAP_ID_EXP PCI Express
258 int pci_find_capability(struct pci_dev *dev, int cap)
262 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
264 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
268 EXPORT_SYMBOL(pci_find_capability);
271 * pci_bus_find_capability - query for devices' capabilities
272 * @bus: the PCI bus to query
273 * @devfn: PCI device to query
274 * @cap: capability code
276 * Like pci_find_capability() but works for pci devices that do not have a
277 * pci_dev structure set up yet.
279 * Returns the address of the requested capability structure within the
280 * device's PCI configuration space or 0 in case the device does not
283 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
288 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
290 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
292 pos = __pci_find_next_cap(bus, devfn, pos, cap);
296 EXPORT_SYMBOL(pci_bus_find_capability);
299 * pci_find_next_ext_capability - Find an extended capability
300 * @dev: PCI device to query
301 * @start: address at which to start looking (0 to start at beginning of list)
302 * @cap: capability code
304 * Returns the address of the next matching extended capability structure
305 * within the device's PCI configuration space or 0 if the device does
306 * not support it. Some capabilities can occur several times, e.g., the
307 * vendor-specific capability, and this provides a way to find them all.
309 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
313 int pos = PCI_CFG_SPACE_SIZE;
315 /* minimum 8 bytes per capability */
316 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
318 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
324 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
328 * If we have no capabilities, this is indicated by cap ID,
329 * cap version and next pointer all being 0.
335 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
338 pos = PCI_EXT_CAP_NEXT(header);
339 if (pos < PCI_CFG_SPACE_SIZE)
342 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
348 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
351 * pci_find_ext_capability - Find an extended capability
352 * @dev: PCI device to query
353 * @cap: capability code
355 * Returns the address of the requested extended capability structure
356 * within the device's PCI configuration space or 0 if the device does
357 * not support it. Possible values for @cap:
359 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
360 * %PCI_EXT_CAP_ID_VC Virtual Channel
361 * %PCI_EXT_CAP_ID_DSN Device Serial Number
362 * %PCI_EXT_CAP_ID_PWR Power Budgeting
364 int pci_find_ext_capability(struct pci_dev *dev, int cap)
366 return pci_find_next_ext_capability(dev, 0, cap);
368 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
370 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
372 int rc, ttl = PCI_FIND_CAP_TTL;
375 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
376 mask = HT_3BIT_CAP_MASK;
378 mask = HT_5BIT_CAP_MASK;
380 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
381 PCI_CAP_ID_HT, &ttl);
383 rc = pci_read_config_byte(dev, pos + 3, &cap);
384 if (rc != PCIBIOS_SUCCESSFUL)
387 if ((cap & mask) == ht_cap)
390 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
391 pos + PCI_CAP_LIST_NEXT,
392 PCI_CAP_ID_HT, &ttl);
398 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
399 * @dev: PCI device to query
400 * @pos: Position from which to continue searching
401 * @ht_cap: Hypertransport capability code
403 * To be used in conjunction with pci_find_ht_capability() to search for
404 * all capabilities matching @ht_cap. @pos should always be a value returned
405 * from pci_find_ht_capability().
407 * NB. To be 100% safe against broken PCI devices, the caller should take
408 * steps to avoid an infinite loop.
410 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
412 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
414 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
417 * pci_find_ht_capability - query a device's Hypertransport capabilities
418 * @dev: PCI device to query
419 * @ht_cap: Hypertransport capability code
421 * Tell if a device supports a given Hypertransport capability.
422 * Returns an address within the device's PCI configuration space
423 * or 0 in case the device does not support the request capability.
424 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
425 * which has a Hypertransport capability matching @ht_cap.
427 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
431 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
433 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
437 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
440 * pci_find_parent_resource - return resource region of parent bus of given region
441 * @dev: PCI device structure contains resources to be searched
442 * @res: child resource record for which parent is sought
444 * For given resource region of given device, return the resource
445 * region of parent bus the given region is contained in.
447 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
448 struct resource *res)
450 const struct pci_bus *bus = dev->bus;
454 pci_bus_for_each_resource(bus, r, i) {
457 if (res->start && resource_contains(r, res)) {
460 * If the window is prefetchable but the BAR is
461 * not, the allocator made a mistake.
463 if (r->flags & IORESOURCE_PREFETCH &&
464 !(res->flags & IORESOURCE_PREFETCH))
468 * If we're below a transparent bridge, there may
469 * be both a positively-decoded aperture and a
470 * subtractively-decoded region that contain the BAR.
471 * We want the positively-decoded one, so this depends
472 * on pci_bus_for_each_resource() giving us those
480 EXPORT_SYMBOL(pci_find_parent_resource);
483 * pci_find_resource - Return matching PCI device resource
484 * @dev: PCI device to query
485 * @res: Resource to look for
487 * Goes over standard PCI resources (BARs) and checks if the given resource
488 * is partially or fully contained in any of them. In that case the
489 * matching resource is returned, %NULL otherwise.
491 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
495 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
496 struct resource *r = &dev->resource[i];
498 if (r->start && resource_contains(r, res))
504 EXPORT_SYMBOL(pci_find_resource);
507 * pci_find_pcie_root_port - return PCIe Root Port
508 * @dev: PCI device to query
510 * Traverse up the parent chain and return the PCIe Root Port PCI Device
511 * for a given PCI Device.
513 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
515 struct pci_dev *bridge, *highest_pcie_bridge = NULL;
517 bridge = pci_upstream_bridge(dev);
518 while (bridge && pci_is_pcie(bridge)) {
519 highest_pcie_bridge = bridge;
520 bridge = pci_upstream_bridge(bridge);
523 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
526 return highest_pcie_bridge;
528 EXPORT_SYMBOL(pci_find_pcie_root_port);
531 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
532 * @dev: the PCI device to operate on
533 * @pos: config space offset of status word
534 * @mask: mask of bit(s) to care about in status word
536 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
538 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
542 /* Wait for Transaction Pending bit clean */
543 for (i = 0; i < 4; i++) {
546 msleep((1 << (i - 1)) * 100);
548 pci_read_config_word(dev, pos, &status);
549 if (!(status & mask))
557 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
558 * @dev: PCI device to have its BARs restored
560 * Restore the BAR values for a given device, so as to make it
561 * accessible by its driver.
563 static void pci_restore_bars(struct pci_dev *dev)
567 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
571 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
572 pci_update_resource(dev, i);
575 static const struct pci_platform_pm_ops *pci_platform_pm;
577 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
579 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
580 !ops->choose_state || !ops->sleep_wake || !ops->run_wake ||
583 pci_platform_pm = ops;
587 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
589 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
592 static inline int platform_pci_set_power_state(struct pci_dev *dev,
595 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
598 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
600 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
603 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
605 return pci_platform_pm ?
606 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
609 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
611 return pci_platform_pm ?
612 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
615 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
617 return pci_platform_pm ?
618 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
621 static inline bool platform_pci_need_resume(struct pci_dev *dev)
623 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
627 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
629 * @dev: PCI device to handle.
630 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
633 * -EINVAL if the requested state is invalid.
634 * -EIO if device does not support PCI PM or its PM capabilities register has a
635 * wrong version, or device doesn't support the requested state.
636 * 0 if device already is in the requested state.
637 * 0 if device's power state has been successfully changed.
639 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
642 bool need_restore = false;
644 /* Check if we're already there */
645 if (dev->current_state == state)
651 if (state < PCI_D0 || state > PCI_D3hot)
654 /* Validate current state:
655 * Can enter D0 from any state, but if we can only go deeper
656 * to sleep if we're already in a low power state
658 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
659 && dev->current_state > state) {
660 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
661 dev->current_state, state);
665 /* check if this device supports the desired state */
666 if ((state == PCI_D1 && !dev->d1_support)
667 || (state == PCI_D2 && !dev->d2_support))
670 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
672 /* If we're (effectively) in D3, force entire word to 0.
673 * This doesn't affect PME_Status, disables PME_En, and
674 * sets PowerState to 0.
676 switch (dev->current_state) {
680 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
685 case PCI_UNKNOWN: /* Boot-up */
686 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
687 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
689 /* Fall-through: force to D0 */
695 /* enter specified state */
696 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
698 /* Mandatory power management transition delays */
699 /* see PCI PM 1.1 5.6.1 table 18 */
700 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
701 pci_dev_d3_sleep(dev);
702 else if (state == PCI_D2 || dev->current_state == PCI_D2)
703 udelay(PCI_PM_D2_DELAY);
705 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
706 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
707 if (dev->current_state != state && printk_ratelimit())
708 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
712 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
713 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
714 * from D3hot to D0 _may_ perform an internal reset, thereby
715 * going to "D0 Uninitialized" rather than "D0 Initialized".
716 * For example, at least some versions of the 3c905B and the
717 * 3c556B exhibit this behaviour.
719 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
720 * devices in a D3hot state at boot. Consequently, we need to
721 * restore at least the BARs so that the device will be
722 * accessible to its driver.
725 pci_restore_bars(dev);
728 pcie_aspm_pm_state_change(dev->bus->self);
734 * pci_update_current_state - Read power state of given device and cache it
735 * @dev: PCI device to handle.
736 * @state: State to cache in case the device doesn't have the PM capability
738 * The power state is read from the PMCSR register, which however is
739 * inaccessible in D3cold. The platform firmware is therefore queried first
740 * to detect accessibility of the register. In case the platform firmware
741 * reports an incorrect state or the device isn't power manageable by the
742 * platform at all, we try to detect D3cold by testing accessibility of the
743 * vendor ID in config space.
745 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
747 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
748 !pci_device_is_present(dev)) {
749 dev->current_state = PCI_D3cold;
750 } else if (dev->pm_cap) {
753 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
754 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
756 dev->current_state = state;
761 * pci_power_up - Put the given device into D0 forcibly
762 * @dev: PCI device to power up
764 void pci_power_up(struct pci_dev *dev)
766 if (platform_pci_power_manageable(dev))
767 platform_pci_set_power_state(dev, PCI_D0);
769 pci_raw_set_power_state(dev, PCI_D0);
770 pci_update_current_state(dev, PCI_D0);
774 * pci_platform_power_transition - Use platform to change device power state
775 * @dev: PCI device to handle.
776 * @state: State to put the device into.
778 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
782 if (platform_pci_power_manageable(dev)) {
783 error = platform_pci_set_power_state(dev, state);
785 pci_update_current_state(dev, state);
789 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
790 dev->current_state = PCI_D0;
796 * pci_wakeup - Wake up a PCI device
797 * @pci_dev: Device to handle.
798 * @ign: ignored parameter
800 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
802 pci_wakeup_event(pci_dev);
803 pm_request_resume(&pci_dev->dev);
808 * pci_wakeup_bus - Walk given bus and wake up devices on it
809 * @bus: Top bus of the subtree to walk.
811 static void pci_wakeup_bus(struct pci_bus *bus)
814 pci_walk_bus(bus, pci_wakeup, NULL);
818 * __pci_start_power_transition - Start power transition of a PCI device
819 * @dev: PCI device to handle.
820 * @state: State to put the device into.
822 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
824 if (state == PCI_D0) {
825 pci_platform_power_transition(dev, PCI_D0);
827 * Mandatory power management transition delays, see
828 * PCI Express Base Specification Revision 2.0 Section
829 * 6.6.1: Conventional Reset. Do not delay for
830 * devices powered on/off by corresponding bridge,
831 * because have already delayed for the bridge.
833 if (dev->runtime_d3cold) {
834 msleep(dev->d3cold_delay);
836 * When powering on a bridge from D3cold, the
837 * whole hierarchy may be powered on into
838 * D0uninitialized state, resume them to give
839 * them a chance to suspend again
841 pci_wakeup_bus(dev->subordinate);
847 * __pci_dev_set_current_state - Set current state of a PCI device
848 * @dev: Device to handle
849 * @data: pointer to state to be set
851 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
853 pci_power_t state = *(pci_power_t *)data;
855 dev->current_state = state;
860 * __pci_bus_set_current_state - Walk given bus and set current state of devices
861 * @bus: Top bus of the subtree to walk.
862 * @state: state to be set
864 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
867 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
871 * __pci_complete_power_transition - Complete power transition of a PCI device
872 * @dev: PCI device to handle.
873 * @state: State to put the device into.
875 * This function should not be called directly by device drivers.
877 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
883 ret = pci_platform_power_transition(dev, state);
884 /* Power off the bridge may power off the whole hierarchy */
885 if (!ret && state == PCI_D3cold)
886 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
889 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
892 * pci_set_power_state - Set the power state of a PCI device
893 * @dev: PCI device to handle.
894 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
896 * Transition a device to a new power state, using the platform firmware and/or
897 * the device's PCI PM registers.
900 * -EINVAL if the requested state is invalid.
901 * -EIO if device does not support PCI PM or its PM capabilities register has a
902 * wrong version, or device doesn't support the requested state.
903 * 0 if device already is in the requested state.
904 * 0 if device's power state has been successfully changed.
906 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
910 /* bound the state we're entering */
911 if (state > PCI_D3cold)
913 else if (state < PCI_D0)
915 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
917 * If the device or the parent bridge do not support PCI PM,
918 * ignore the request if we're doing anything other than putting
919 * it into D0 (which would only happen on boot).
923 /* Check if we're already there */
924 if (dev->current_state == state)
927 __pci_start_power_transition(dev, state);
929 /* This device is quirked not to be put into D3, so
930 don't put it in D3 */
931 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
935 * To put device in D3cold, we put device into D3hot in native
936 * way, then put device into D3cold with platform ops
938 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
941 if (!__pci_complete_power_transition(dev, state))
946 EXPORT_SYMBOL(pci_set_power_state);
949 * pci_choose_state - Choose the power state of a PCI device
950 * @dev: PCI device to be suspended
951 * @state: target sleep state for the whole system. This is the value
952 * that is passed to suspend() function.
954 * Returns PCI power state suitable for given device and given system
958 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
965 ret = platform_pci_choose_state(dev);
966 if (ret != PCI_POWER_ERROR)
969 switch (state.event) {
972 case PM_EVENT_FREEZE:
973 case PM_EVENT_PRETHAW:
974 /* REVISIT both freeze and pre-thaw "should" use D0 */
975 case PM_EVENT_SUSPEND:
976 case PM_EVENT_HIBERNATE:
979 dev_info(&dev->dev, "unrecognized suspend event %d\n",
985 EXPORT_SYMBOL(pci_choose_state);
987 #define PCI_EXP_SAVE_REGS 7
989 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
990 u16 cap, bool extended)
992 struct pci_cap_saved_state *tmp;
994 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
995 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1001 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1003 return _pci_find_saved_cap(dev, cap, false);
1006 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1008 return _pci_find_saved_cap(dev, cap, true);
1011 static int pci_save_pcie_state(struct pci_dev *dev)
1014 struct pci_cap_saved_state *save_state;
1017 if (!pci_is_pcie(dev))
1020 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1022 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1026 cap = (u16 *)&save_state->cap.data[0];
1027 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1028 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1029 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1030 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1031 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1032 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1033 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1038 static void pci_restore_pcie_state(struct pci_dev *dev)
1041 struct pci_cap_saved_state *save_state;
1044 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1048 cap = (u16 *)&save_state->cap.data[0];
1049 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1050 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1051 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1052 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1053 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1054 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1055 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1059 static int pci_save_pcix_state(struct pci_dev *dev)
1062 struct pci_cap_saved_state *save_state;
1064 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1068 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1070 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
1074 pci_read_config_word(dev, pos + PCI_X_CMD,
1075 (u16 *)save_state->cap.data);
1080 static void pci_restore_pcix_state(struct pci_dev *dev)
1083 struct pci_cap_saved_state *save_state;
1086 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1087 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1088 if (!save_state || !pos)
1090 cap = (u16 *)&save_state->cap.data[0];
1092 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1097 * pci_save_state - save the PCI configuration space of a device before suspending
1098 * @dev: - PCI device that we're dealing with
1100 int pci_save_state(struct pci_dev *dev)
1103 /* XXX: 100% dword access ok here? */
1104 for (i = 0; i < 16; i++)
1105 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1106 dev->state_saved = true;
1108 i = pci_save_pcie_state(dev);
1112 i = pci_save_pcix_state(dev);
1116 return pci_save_vc_state(dev);
1118 EXPORT_SYMBOL(pci_save_state);
1120 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1121 u32 saved_val, int retry)
1125 pci_read_config_dword(pdev, offset, &val);
1126 if (val == saved_val)
1130 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1131 offset, val, saved_val);
1132 pci_write_config_dword(pdev, offset, saved_val);
1136 pci_read_config_dword(pdev, offset, &val);
1137 if (val == saved_val)
1144 static void pci_restore_config_space_range(struct pci_dev *pdev,
1145 int start, int end, int retry)
1149 for (index = end; index >= start; index--)
1150 pci_restore_config_dword(pdev, 4 * index,
1151 pdev->saved_config_space[index],
1155 static void pci_restore_config_space(struct pci_dev *pdev)
1157 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1158 pci_restore_config_space_range(pdev, 10, 15, 0);
1159 /* Restore BARs before the command register. */
1160 pci_restore_config_space_range(pdev, 4, 9, 10);
1161 pci_restore_config_space_range(pdev, 0, 3, 0);
1163 pci_restore_config_space_range(pdev, 0, 15, 0);
1168 * pci_restore_state - Restore the saved state of a PCI device
1169 * @dev: - PCI device that we're dealing with
1171 void pci_restore_state(struct pci_dev *dev)
1173 if (!dev->state_saved)
1176 /* PCI Express register must be restored first */
1177 pci_restore_pcie_state(dev);
1178 pci_restore_ats_state(dev);
1179 pci_restore_vc_state(dev);
1181 pci_cleanup_aer_error_status_regs(dev);
1183 pci_restore_config_space(dev);
1185 pci_restore_pcix_state(dev);
1186 pci_restore_msi_state(dev);
1188 /* Restore ACS and IOV configuration state */
1189 pci_enable_acs(dev);
1190 pci_restore_iov_state(dev);
1192 dev->state_saved = false;
1194 EXPORT_SYMBOL(pci_restore_state);
1196 struct pci_saved_state {
1197 u32 config_space[16];
1198 struct pci_cap_saved_data cap[0];
1202 * pci_store_saved_state - Allocate and return an opaque struct containing
1203 * the device saved state.
1204 * @dev: PCI device that we're dealing with
1206 * Return NULL if no state or error.
1208 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1210 struct pci_saved_state *state;
1211 struct pci_cap_saved_state *tmp;
1212 struct pci_cap_saved_data *cap;
1215 if (!dev->state_saved)
1218 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1220 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1221 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1223 state = kzalloc(size, GFP_KERNEL);
1227 memcpy(state->config_space, dev->saved_config_space,
1228 sizeof(state->config_space));
1231 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1232 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1233 memcpy(cap, &tmp->cap, len);
1234 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1236 /* Empty cap_save terminates list */
1240 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1243 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1244 * @dev: PCI device that we're dealing with
1245 * @state: Saved state returned from pci_store_saved_state()
1247 int pci_load_saved_state(struct pci_dev *dev,
1248 struct pci_saved_state *state)
1250 struct pci_cap_saved_data *cap;
1252 dev->state_saved = false;
1257 memcpy(dev->saved_config_space, state->config_space,
1258 sizeof(state->config_space));
1262 struct pci_cap_saved_state *tmp;
1264 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1265 if (!tmp || tmp->cap.size != cap->size)
1268 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1269 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1270 sizeof(struct pci_cap_saved_data) + cap->size);
1273 dev->state_saved = true;
1276 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1279 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1280 * and free the memory allocated for it.
1281 * @dev: PCI device that we're dealing with
1282 * @state: Pointer to saved state returned from pci_store_saved_state()
1284 int pci_load_and_free_saved_state(struct pci_dev *dev,
1285 struct pci_saved_state **state)
1287 int ret = pci_load_saved_state(dev, *state);
1292 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1294 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1296 return pci_enable_resources(dev, bars);
1299 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1302 struct pci_dev *bridge;
1306 err = pci_set_power_state(dev, PCI_D0);
1307 if (err < 0 && err != -EIO)
1310 bridge = pci_upstream_bridge(dev);
1312 pcie_aspm_powersave_config_link(bridge);
1314 err = pcibios_enable_device(dev, bars);
1317 pci_fixup_device(pci_fixup_enable, dev);
1319 if (dev->msi_enabled || dev->msix_enabled)
1322 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1324 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1325 if (cmd & PCI_COMMAND_INTX_DISABLE)
1326 pci_write_config_word(dev, PCI_COMMAND,
1327 cmd & ~PCI_COMMAND_INTX_DISABLE);
1334 * pci_reenable_device - Resume abandoned device
1335 * @dev: PCI device to be resumed
1337 * Note this function is a backend of pci_default_resume and is not supposed
1338 * to be called by normal code, write proper resume handler and use it instead.
1340 int pci_reenable_device(struct pci_dev *dev)
1342 if (pci_is_enabled(dev))
1343 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1346 EXPORT_SYMBOL(pci_reenable_device);
1348 static void pci_enable_bridge(struct pci_dev *dev)
1350 struct pci_dev *bridge;
1353 bridge = pci_upstream_bridge(dev);
1355 pci_enable_bridge(bridge);
1357 if (pci_is_enabled(dev)) {
1358 if (!dev->is_busmaster)
1359 pci_set_master(dev);
1363 retval = pci_enable_device(dev);
1365 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1367 pci_set_master(dev);
1370 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1372 struct pci_dev *bridge;
1377 * Power state could be unknown at this point, either due to a fresh
1378 * boot or a device removal call. So get the current power state
1379 * so that things like MSI message writing will behave as expected
1380 * (e.g. if the device really is in D0 at enable time).
1384 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1385 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1388 if (atomic_inc_return(&dev->enable_cnt) > 1)
1389 return 0; /* already enabled */
1391 bridge = pci_upstream_bridge(dev);
1393 pci_enable_bridge(bridge);
1395 /* only skip sriov related */
1396 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1397 if (dev->resource[i].flags & flags)
1399 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1400 if (dev->resource[i].flags & flags)
1403 err = do_pci_enable_device(dev, bars);
1405 atomic_dec(&dev->enable_cnt);
1410 * pci_enable_device_io - Initialize a device for use with IO space
1411 * @dev: PCI device to be initialized
1413 * Initialize device before it's used by a driver. Ask low-level code
1414 * to enable I/O resources. Wake up the device if it was suspended.
1415 * Beware, this function can fail.
1417 int pci_enable_device_io(struct pci_dev *dev)
1419 return pci_enable_device_flags(dev, IORESOURCE_IO);
1421 EXPORT_SYMBOL(pci_enable_device_io);
1424 * pci_enable_device_mem - Initialize a device for use with Memory space
1425 * @dev: PCI device to be initialized
1427 * Initialize device before it's used by a driver. Ask low-level code
1428 * to enable Memory resources. Wake up the device if it was suspended.
1429 * Beware, this function can fail.
1431 int pci_enable_device_mem(struct pci_dev *dev)
1433 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1435 EXPORT_SYMBOL(pci_enable_device_mem);
1438 * pci_enable_device - Initialize device before it's used by a driver.
1439 * @dev: PCI device to be initialized
1441 * Initialize device before it's used by a driver. Ask low-level code
1442 * to enable I/O and memory. Wake up the device if it was suspended.
1443 * Beware, this function can fail.
1445 * Note we don't actually enable the device many times if we call
1446 * this function repeatedly (we just increment the count).
1448 int pci_enable_device(struct pci_dev *dev)
1450 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1452 EXPORT_SYMBOL(pci_enable_device);
1455 * Managed PCI resources. This manages device on/off, intx/msi/msix
1456 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1457 * there's no need to track it separately. pci_devres is initialized
1458 * when a device is enabled using managed PCI device enable interface.
1461 unsigned int enabled:1;
1462 unsigned int pinned:1;
1463 unsigned int orig_intx:1;
1464 unsigned int restore_intx:1;
1468 static void pcim_release(struct device *gendev, void *res)
1470 struct pci_dev *dev = to_pci_dev(gendev);
1471 struct pci_devres *this = res;
1474 if (dev->msi_enabled)
1475 pci_disable_msi(dev);
1476 if (dev->msix_enabled)
1477 pci_disable_msix(dev);
1479 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1480 if (this->region_mask & (1 << i))
1481 pci_release_region(dev, i);
1483 if (this->restore_intx)
1484 pci_intx(dev, this->orig_intx);
1486 if (this->enabled && !this->pinned)
1487 pci_disable_device(dev);
1490 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
1492 struct pci_devres *dr, *new_dr;
1494 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1498 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1501 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1504 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
1506 if (pci_is_managed(pdev))
1507 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1512 * pcim_enable_device - Managed pci_enable_device()
1513 * @pdev: PCI device to be initialized
1515 * Managed pci_enable_device().
1517 int pcim_enable_device(struct pci_dev *pdev)
1519 struct pci_devres *dr;
1522 dr = get_pci_dr(pdev);
1528 rc = pci_enable_device(pdev);
1530 pdev->is_managed = 1;
1535 EXPORT_SYMBOL(pcim_enable_device);
1538 * pcim_pin_device - Pin managed PCI device
1539 * @pdev: PCI device to pin
1541 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1542 * driver detach. @pdev must have been enabled with
1543 * pcim_enable_device().
1545 void pcim_pin_device(struct pci_dev *pdev)
1547 struct pci_devres *dr;
1549 dr = find_pci_dr(pdev);
1550 WARN_ON(!dr || !dr->enabled);
1554 EXPORT_SYMBOL(pcim_pin_device);
1557 * pcibios_add_device - provide arch specific hooks when adding device dev
1558 * @dev: the PCI device being added
1560 * Permits the platform to provide architecture specific functionality when
1561 * devices are added. This is the default implementation. Architecture
1562 * implementations can override this.
1564 int __weak pcibios_add_device(struct pci_dev *dev)
1570 * pcibios_release_device - provide arch specific hooks when releasing device dev
1571 * @dev: the PCI device being released
1573 * Permits the platform to provide architecture specific functionality when
1574 * devices are released. This is the default implementation. Architecture
1575 * implementations can override this.
1577 void __weak pcibios_release_device(struct pci_dev *dev) {}
1580 * pcibios_disable_device - disable arch specific PCI resources for device dev
1581 * @dev: the PCI device to disable
1583 * Disables architecture specific PCI resources for the device. This
1584 * is the default implementation. Architecture implementations can
1587 void __weak pcibios_disable_device(struct pci_dev *dev) {}
1590 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1591 * @irq: ISA IRQ to penalize
1592 * @active: IRQ active or not
1594 * Permits the platform to provide architecture-specific functionality when
1595 * penalizing ISA IRQs. This is the default implementation. Architecture
1596 * implementations can override this.
1598 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1600 static void do_pci_disable_device(struct pci_dev *dev)
1604 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1605 if (pci_command & PCI_COMMAND_MASTER) {
1606 pci_command &= ~PCI_COMMAND_MASTER;
1607 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1610 pcibios_disable_device(dev);
1614 * pci_disable_enabled_device - Disable device without updating enable_cnt
1615 * @dev: PCI device to disable
1617 * NOTE: This function is a backend of PCI power management routines and is
1618 * not supposed to be called drivers.
1620 void pci_disable_enabled_device(struct pci_dev *dev)
1622 if (pci_is_enabled(dev))
1623 do_pci_disable_device(dev);
1627 * pci_disable_device - Disable PCI device after use
1628 * @dev: PCI device to be disabled
1630 * Signal to the system that the PCI device is not in use by the system
1631 * anymore. This only involves disabling PCI bus-mastering, if active.
1633 * Note we don't actually disable the device until all callers of
1634 * pci_enable_device() have called pci_disable_device().
1636 void pci_disable_device(struct pci_dev *dev)
1638 struct pci_devres *dr;
1640 dr = find_pci_dr(dev);
1644 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1645 "disabling already-disabled device");
1647 if (atomic_dec_return(&dev->enable_cnt) != 0)
1650 do_pci_disable_device(dev);
1652 dev->is_busmaster = 0;
1654 EXPORT_SYMBOL(pci_disable_device);
1657 * pcibios_set_pcie_reset_state - set reset state for device dev
1658 * @dev: the PCIe device reset
1659 * @state: Reset state to enter into
1662 * Sets the PCIe reset state for the device. This is the default
1663 * implementation. Architecture implementations can override this.
1665 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1666 enum pcie_reset_state state)
1672 * pci_set_pcie_reset_state - set reset state for device dev
1673 * @dev: the PCIe device reset
1674 * @state: Reset state to enter into
1677 * Sets the PCI reset state for the device.
1679 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1681 return pcibios_set_pcie_reset_state(dev, state);
1683 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1686 * pci_check_pme_status - Check if given device has generated PME.
1687 * @dev: Device to check.
1689 * Check the PME status of the device and if set, clear it and clear PME enable
1690 * (if set). Return 'true' if PME status and PME enable were both set or
1691 * 'false' otherwise.
1693 bool pci_check_pme_status(struct pci_dev *dev)
1702 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1703 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1704 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1707 /* Clear PME status. */
1708 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1709 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1710 /* Disable PME to avoid interrupt flood. */
1711 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1715 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1721 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1722 * @dev: Device to handle.
1723 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1725 * Check if @dev has generated PME and queue a resume request for it in that
1728 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1730 if (pme_poll_reset && dev->pme_poll)
1731 dev->pme_poll = false;
1733 if (pci_check_pme_status(dev)) {
1734 pci_wakeup_event(dev);
1735 pm_request_resume(&dev->dev);
1741 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1742 * @bus: Top bus of the subtree to walk.
1744 void pci_pme_wakeup_bus(struct pci_bus *bus)
1747 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1752 * pci_pme_capable - check the capability of PCI device to generate PME#
1753 * @dev: PCI device to handle.
1754 * @state: PCI state from which device will issue PME#.
1756 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1761 return !!(dev->pme_support & (1 << state));
1763 EXPORT_SYMBOL(pci_pme_capable);
1765 static void pci_pme_list_scan(struct work_struct *work)
1767 struct pci_pme_device *pme_dev, *n;
1769 mutex_lock(&pci_pme_list_mutex);
1770 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1771 if (pme_dev->dev->pme_poll) {
1772 struct pci_dev *bridge;
1774 bridge = pme_dev->dev->bus->self;
1776 * If bridge is in low power state, the
1777 * configuration space of subordinate devices
1778 * may be not accessible
1780 if (bridge && bridge->current_state != PCI_D0)
1782 pci_pme_wakeup(pme_dev->dev, NULL);
1784 list_del(&pme_dev->list);
1788 if (!list_empty(&pci_pme_list))
1789 schedule_delayed_work(&pci_pme_work,
1790 msecs_to_jiffies(PME_TIMEOUT));
1791 mutex_unlock(&pci_pme_list_mutex);
1794 static void __pci_pme_active(struct pci_dev *dev, bool enable)
1798 if (!dev->pme_support)
1801 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1802 /* Clear PME_Status by writing 1 to it and enable PME# */
1803 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1805 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1807 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1811 * pci_pme_active - enable or disable PCI device's PME# function
1812 * @dev: PCI device to handle.
1813 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1815 * The caller must verify that the device is capable of generating PME# before
1816 * calling this function with @enable equal to 'true'.
1818 void pci_pme_active(struct pci_dev *dev, bool enable)
1820 __pci_pme_active(dev, enable);
1823 * PCI (as opposed to PCIe) PME requires that the device have
1824 * its PME# line hooked up correctly. Not all hardware vendors
1825 * do this, so the PME never gets delivered and the device
1826 * remains asleep. The easiest way around this is to
1827 * periodically walk the list of suspended devices and check
1828 * whether any have their PME flag set. The assumption is that
1829 * we'll wake up often enough anyway that this won't be a huge
1830 * hit, and the power savings from the devices will still be a
1833 * Although PCIe uses in-band PME message instead of PME# line
1834 * to report PME, PME does not work for some PCIe devices in
1835 * reality. For example, there are devices that set their PME
1836 * status bits, but don't really bother to send a PME message;
1837 * there are PCI Express Root Ports that don't bother to
1838 * trigger interrupts when they receive PME messages from the
1839 * devices below. So PME poll is used for PCIe devices too.
1842 if (dev->pme_poll) {
1843 struct pci_pme_device *pme_dev;
1845 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1848 dev_warn(&dev->dev, "can't enable PME#\n");
1852 mutex_lock(&pci_pme_list_mutex);
1853 list_add(&pme_dev->list, &pci_pme_list);
1854 if (list_is_singular(&pci_pme_list))
1855 schedule_delayed_work(&pci_pme_work,
1856 msecs_to_jiffies(PME_TIMEOUT));
1857 mutex_unlock(&pci_pme_list_mutex);
1859 mutex_lock(&pci_pme_list_mutex);
1860 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1861 if (pme_dev->dev == dev) {
1862 list_del(&pme_dev->list);
1867 mutex_unlock(&pci_pme_list_mutex);
1871 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1873 EXPORT_SYMBOL(pci_pme_active);
1876 * __pci_enable_wake - enable PCI device as wakeup event source
1877 * @dev: PCI device affected
1878 * @state: PCI state from which device will issue wakeup events
1879 * @runtime: True if the events are to be generated at run time
1880 * @enable: True to enable event generation; false to disable
1882 * This enables the device as a wakeup event source, or disables it.
1883 * When such events involves platform-specific hooks, those hooks are
1884 * called automatically by this routine.
1886 * Devices with legacy power management (no standard PCI PM capabilities)
1887 * always require such platform hooks.
1890 * 0 is returned on success
1891 * -EINVAL is returned if device is not supposed to wake up the system
1892 * Error code depending on the platform is returned if both the platform and
1893 * the native mechanism fail to enable the generation of wake-up events
1895 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1896 bool runtime, bool enable)
1900 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1903 /* Don't do the same thing twice in a row for one device. */
1904 if (!!enable == !!dev->wakeup_prepared)
1908 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1909 * Anderson we should be doing PME# wake enable followed by ACPI wake
1910 * enable. To disable wake-up we call the platform first, for symmetry.
1916 if (pci_pme_capable(dev, state))
1917 pci_pme_active(dev, true);
1920 error = runtime ? platform_pci_run_wake(dev, true) :
1921 platform_pci_sleep_wake(dev, true);
1925 dev->wakeup_prepared = true;
1928 platform_pci_run_wake(dev, false);
1930 platform_pci_sleep_wake(dev, false);
1931 pci_pme_active(dev, false);
1932 dev->wakeup_prepared = false;
1937 EXPORT_SYMBOL(__pci_enable_wake);
1940 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1941 * @dev: PCI device to prepare
1942 * @enable: True to enable wake-up event generation; false to disable
1944 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1945 * and this function allows them to set that up cleanly - pci_enable_wake()
1946 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1947 * ordering constraints.
1949 * This function only returns error code if the device is not capable of
1950 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1951 * enable wake-up power for it.
1953 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1955 return pci_pme_capable(dev, PCI_D3cold) ?
1956 pci_enable_wake(dev, PCI_D3cold, enable) :
1957 pci_enable_wake(dev, PCI_D3hot, enable);
1959 EXPORT_SYMBOL(pci_wake_from_d3);
1962 * pci_target_state - find an appropriate low power state for a given PCI dev
1965 * Use underlying platform code to find a supported low power state for @dev.
1966 * If the platform can't manage @dev, return the deepest state from which it
1967 * can generate wake events, based on any available PME info.
1969 static pci_power_t pci_target_state(struct pci_dev *dev)
1971 pci_power_t target_state = PCI_D3hot;
1973 if (platform_pci_power_manageable(dev)) {
1975 * Call the platform to choose the target state of the device
1976 * and enable wake-up from this state if supported.
1978 pci_power_t state = platform_pci_choose_state(dev);
1981 case PCI_POWER_ERROR:
1986 if (pci_no_d1d2(dev))
1989 target_state = state;
1992 return target_state;
1996 target_state = PCI_D0;
1999 * If the device is in D3cold even though it's not power-manageable by
2000 * the platform, it may have been powered down by non-standard means.
2001 * Best to let it slumber.
2003 if (dev->current_state == PCI_D3cold)
2004 target_state = PCI_D3cold;
2006 if (device_may_wakeup(&dev->dev)) {
2008 * Find the deepest state from which the device can generate
2009 * wake-up events, make it the target state and enable device
2012 if (dev->pme_support) {
2014 && !(dev->pme_support & (1 << target_state)))
2019 return target_state;
2023 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2024 * @dev: Device to handle.
2026 * Choose the power state appropriate for the device depending on whether
2027 * it can wake up the system and/or is power manageable by the platform
2028 * (PCI_D3hot is the default) and put the device into that state.
2030 int pci_prepare_to_sleep(struct pci_dev *dev)
2032 pci_power_t target_state = pci_target_state(dev);
2035 if (target_state == PCI_POWER_ERROR)
2038 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
2040 error = pci_set_power_state(dev, target_state);
2043 pci_enable_wake(dev, target_state, false);
2047 EXPORT_SYMBOL(pci_prepare_to_sleep);
2050 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
2051 * @dev: Device to handle.
2053 * Disable device's system wake-up capability and put it into D0.
2055 int pci_back_from_sleep(struct pci_dev *dev)
2057 pci_enable_wake(dev, PCI_D0, false);
2058 return pci_set_power_state(dev, PCI_D0);
2060 EXPORT_SYMBOL(pci_back_from_sleep);
2063 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2064 * @dev: PCI device being suspended.
2066 * Prepare @dev to generate wake-up events at run time and put it into a low
2069 int pci_finish_runtime_suspend(struct pci_dev *dev)
2071 pci_power_t target_state = pci_target_state(dev);
2074 if (target_state == PCI_POWER_ERROR)
2077 dev->runtime_d3cold = target_state == PCI_D3cold;
2079 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
2081 error = pci_set_power_state(dev, target_state);
2084 __pci_enable_wake(dev, target_state, true, false);
2085 dev->runtime_d3cold = false;
2092 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2093 * @dev: Device to check.
2095 * Return true if the device itself is capable of generating wake-up events
2096 * (through the platform or using the native PCIe PME) or if the device supports
2097 * PME and one of its upstream bridges can generate wake-up events.
2099 bool pci_dev_run_wake(struct pci_dev *dev)
2101 struct pci_bus *bus = dev->bus;
2103 if (device_run_wake(&dev->dev))
2106 if (!dev->pme_support)
2109 /* PME-capable in principle, but not from the intended sleep state */
2110 if (!pci_pme_capable(dev, pci_target_state(dev)))
2113 while (bus->parent) {
2114 struct pci_dev *bridge = bus->self;
2116 if (device_run_wake(&bridge->dev))
2122 /* We have reached the root bus. */
2124 return device_run_wake(bus->bridge);
2128 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2131 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2132 * @pci_dev: Device to check.
2134 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2135 * reconfigured due to wakeup settings difference between system and runtime
2136 * suspend and the current power state of it is suitable for the upcoming
2137 * (system) transition.
2139 * If the device is not configured for system wakeup, disable PME for it before
2140 * returning 'true' to prevent it from waking up the system unnecessarily.
2142 bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2144 struct device *dev = &pci_dev->dev;
2146 if (!pm_runtime_suspended(dev)
2147 || pci_target_state(pci_dev) != pci_dev->current_state
2148 || platform_pci_need_resume(pci_dev))
2152 * At this point the device is good to go unless it's been configured
2153 * to generate PME at the runtime suspend time, but it is not supposed
2154 * to wake up the system. In that case, simply disable PME for it
2155 * (it will have to be re-enabled on exit from system resume).
2157 * If the device's power state is D3cold and the platform check above
2158 * hasn't triggered, the device's configuration is suitable and we don't
2159 * need to manipulate it at all.
2161 spin_lock_irq(&dev->power.lock);
2163 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2164 !device_may_wakeup(dev))
2165 __pci_pme_active(pci_dev, false);
2167 spin_unlock_irq(&dev->power.lock);
2172 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2173 * @pci_dev: Device to handle.
2175 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2176 * it might have been disabled during the prepare phase of system suspend if
2177 * the device was not configured for system wakeup.
2179 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2181 struct device *dev = &pci_dev->dev;
2183 if (!pci_dev_run_wake(pci_dev))
2186 spin_lock_irq(&dev->power.lock);
2188 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2189 __pci_pme_active(pci_dev, true);
2191 spin_unlock_irq(&dev->power.lock);
2194 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2196 struct device *dev = &pdev->dev;
2197 struct device *parent = dev->parent;
2200 pm_runtime_get_sync(parent);
2201 pm_runtime_get_noresume(dev);
2203 * pdev->current_state is set to PCI_D3cold during suspending,
2204 * so wait until suspending completes
2206 pm_runtime_barrier(dev);
2208 * Only need to resume devices in D3cold, because config
2209 * registers are still accessible for devices suspended but
2212 if (pdev->current_state == PCI_D3cold)
2213 pm_runtime_resume(dev);
2216 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2218 struct device *dev = &pdev->dev;
2219 struct device *parent = dev->parent;
2221 pm_runtime_put(dev);
2223 pm_runtime_put_sync(parent);
2227 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2228 * @bridge: Bridge to check
2230 * This function checks if it is possible to move the bridge to D3.
2231 * Currently we only allow D3 for recent enough PCIe ports.
2233 static bool pci_bridge_d3_possible(struct pci_dev *bridge)
2237 if (!pci_is_pcie(bridge))
2240 switch (pci_pcie_type(bridge)) {
2241 case PCI_EXP_TYPE_ROOT_PORT:
2242 case PCI_EXP_TYPE_UPSTREAM:
2243 case PCI_EXP_TYPE_DOWNSTREAM:
2244 if (pci_bridge_d3_disable)
2246 if (pci_bridge_d3_force)
2250 * It should be safe to put PCIe ports from 2015 or newer
2253 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
2263 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2265 bool *d3cold_ok = data;
2269 * The device needs to be allowed to go D3cold and if it is wake
2270 * capable to do so from D3cold.
2272 no_d3cold = dev->no_d3cold || !dev->d3cold_allowed ||
2273 (device_may_wakeup(&dev->dev) && !pci_pme_capable(dev, PCI_D3cold)) ||
2274 !pci_power_manageable(dev);
2276 *d3cold_ok = !no_d3cold;
2282 * pci_bridge_d3_update - Update bridge D3 capabilities
2283 * @dev: PCI device which is changed
2284 * @remove: Is the device being removed
2286 * Update upstream bridge PM capabilities accordingly depending on if the
2287 * device PM configuration was changed or the device is being removed. The
2288 * change is also propagated upstream.
2290 static void pci_bridge_d3_update(struct pci_dev *dev, bool remove)
2292 struct pci_dev *bridge;
2293 bool d3cold_ok = true;
2295 bridge = pci_upstream_bridge(dev);
2296 if (!bridge || !pci_bridge_d3_possible(bridge))
2299 pci_dev_get(bridge);
2301 * If the device is removed we do not care about its D3cold
2305 pci_dev_check_d3cold(dev, &d3cold_ok);
2309 * We need to go through all children to find out if all of
2310 * them can still go to D3cold.
2312 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2316 if (bridge->bridge_d3 != d3cold_ok) {
2317 bridge->bridge_d3 = d3cold_ok;
2318 /* Propagate change to upstream bridges */
2319 pci_bridge_d3_update(bridge, false);
2322 pci_dev_put(bridge);
2326 * pci_bridge_d3_device_changed - Update bridge D3 capabilities on change
2327 * @dev: PCI device that was changed
2329 * If a device is added or its PM configuration, such as is it allowed to
2330 * enter D3cold, is changed this function updates upstream bridge PM
2331 * capabilities accordingly.
2333 void pci_bridge_d3_device_changed(struct pci_dev *dev)
2335 pci_bridge_d3_update(dev, false);
2339 * pci_bridge_d3_device_removed - Update bridge D3 capabilities on remove
2340 * @dev: PCI device being removed
2342 * Function updates upstream bridge PM capabilities based on other devices
2343 * still left on the bus.
2345 void pci_bridge_d3_device_removed(struct pci_dev *dev)
2347 pci_bridge_d3_update(dev, true);
2351 * pci_d3cold_enable - Enable D3cold for device
2352 * @dev: PCI device to handle
2354 * This function can be used in drivers to enable D3cold from the device
2355 * they handle. It also updates upstream PCI bridge PM capabilities
2358 void pci_d3cold_enable(struct pci_dev *dev)
2360 if (dev->no_d3cold) {
2361 dev->no_d3cold = false;
2362 pci_bridge_d3_device_changed(dev);
2365 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2368 * pci_d3cold_disable - Disable D3cold for device
2369 * @dev: PCI device to handle
2371 * This function can be used in drivers to disable D3cold from the device
2372 * they handle. It also updates upstream PCI bridge PM capabilities
2375 void pci_d3cold_disable(struct pci_dev *dev)
2377 if (!dev->no_d3cold) {
2378 dev->no_d3cold = true;
2379 pci_bridge_d3_device_changed(dev);
2382 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2385 * pci_pm_init - Initialize PM functions of given PCI device
2386 * @dev: PCI device to handle.
2388 void pci_pm_init(struct pci_dev *dev)
2393 pm_runtime_forbid(&dev->dev);
2394 pm_runtime_set_active(&dev->dev);
2395 pm_runtime_enable(&dev->dev);
2396 device_enable_async_suspend(&dev->dev);
2397 dev->wakeup_prepared = false;
2400 dev->pme_support = 0;
2402 /* find PCI PM capability in list */
2403 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2406 /* Check device's ability to generate PME# */
2407 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2409 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2410 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2411 pmc & PCI_PM_CAP_VER_MASK);
2416 dev->d3_delay = PCI_PM_D3_WAIT;
2417 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2418 dev->bridge_d3 = pci_bridge_d3_possible(dev);
2419 dev->d3cold_allowed = true;
2421 dev->d1_support = false;
2422 dev->d2_support = false;
2423 if (!pci_no_d1d2(dev)) {
2424 if (pmc & PCI_PM_CAP_D1)
2425 dev->d1_support = true;
2426 if (pmc & PCI_PM_CAP_D2)
2427 dev->d2_support = true;
2429 if (dev->d1_support || dev->d2_support)
2430 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2431 dev->d1_support ? " D1" : "",
2432 dev->d2_support ? " D2" : "");
2435 pmc &= PCI_PM_CAP_PME_MASK;
2437 dev_printk(KERN_DEBUG, &dev->dev,
2438 "PME# supported from%s%s%s%s%s\n",
2439 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2440 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2441 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2442 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2443 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2444 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2445 dev->pme_poll = true;
2447 * Make device's PM flags reflect the wake-up capability, but
2448 * let the user space enable it to wake up the system as needed.
2450 device_set_wakeup_capable(&dev->dev, true);
2451 /* Disable the PME# generation functionality */
2452 pci_pme_active(dev, false);
2456 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2458 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
2462 case PCI_EA_P_VF_MEM:
2463 flags |= IORESOURCE_MEM;
2465 case PCI_EA_P_MEM_PREFETCH:
2466 case PCI_EA_P_VF_MEM_PREFETCH:
2467 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2470 flags |= IORESOURCE_IO;
2479 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2482 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2483 return &dev->resource[bei];
2484 #ifdef CONFIG_PCI_IOV
2485 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2486 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2487 return &dev->resource[PCI_IOV_RESOURCES +
2488 bei - PCI_EA_BEI_VF_BAR0];
2490 else if (bei == PCI_EA_BEI_ROM)
2491 return &dev->resource[PCI_ROM_RESOURCE];
2496 /* Read an Enhanced Allocation (EA) entry */
2497 static int pci_ea_read(struct pci_dev *dev, int offset)
2499 struct resource *res;
2500 int ent_size, ent_offset = offset;
2501 resource_size_t start, end;
2502 unsigned long flags;
2503 u32 dw0, bei, base, max_offset;
2505 bool support_64 = (sizeof(resource_size_t) >= 8);
2507 pci_read_config_dword(dev, ent_offset, &dw0);
2510 /* Entry size field indicates DWORDs after 1st */
2511 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2513 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2516 bei = (dw0 & PCI_EA_BEI) >> 4;
2517 prop = (dw0 & PCI_EA_PP) >> 8;
2520 * If the Property is in the reserved range, try the Secondary
2523 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
2524 prop = (dw0 & PCI_EA_SP) >> 16;
2525 if (prop > PCI_EA_P_BRIDGE_IO)
2528 res = pci_ea_get_resource(dev, bei, prop);
2530 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei);
2534 flags = pci_ea_flags(dev, prop);
2536 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop);
2541 pci_read_config_dword(dev, ent_offset, &base);
2542 start = (base & PCI_EA_FIELD_MASK);
2545 /* Read MaxOffset */
2546 pci_read_config_dword(dev, ent_offset, &max_offset);
2549 /* Read Base MSBs (if 64-bit entry) */
2550 if (base & PCI_EA_IS_64) {
2553 pci_read_config_dword(dev, ent_offset, &base_upper);
2556 flags |= IORESOURCE_MEM_64;
2558 /* entry starts above 32-bit boundary, can't use */
2559 if (!support_64 && base_upper)
2563 start |= ((u64)base_upper << 32);
2566 end = start + (max_offset | 0x03);
2568 /* Read MaxOffset MSBs (if 64-bit entry) */
2569 if (max_offset & PCI_EA_IS_64) {
2570 u32 max_offset_upper;
2572 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2575 flags |= IORESOURCE_MEM_64;
2577 /* entry too big, can't use */
2578 if (!support_64 && max_offset_upper)
2582 end += ((u64)max_offset_upper << 32);
2586 dev_err(&dev->dev, "EA Entry crosses address boundary\n");
2590 if (ent_size != ent_offset - offset) {
2592 "EA Entry Size (%d) does not match length read (%d)\n",
2593 ent_size, ent_offset - offset);
2597 res->name = pci_name(dev);
2602 if (bei <= PCI_EA_BEI_BAR5)
2603 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2605 else if (bei == PCI_EA_BEI_ROM)
2606 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2608 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2609 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2610 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2612 dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2616 return offset + ent_size;
2619 /* Enhanced Allocation Initialization */
2620 void pci_ea_init(struct pci_dev *dev)
2627 /* find PCI EA capability in list */
2628 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2632 /* determine the number of entries */
2633 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2635 num_ent &= PCI_EA_NUM_ENT_MASK;
2637 offset = ea + PCI_EA_FIRST_ENT;
2639 /* Skip DWORD 2 for type 1 functions */
2640 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2643 /* parse each EA entry */
2644 for (i = 0; i < num_ent; ++i)
2645 offset = pci_ea_read(dev, offset);
2648 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2649 struct pci_cap_saved_state *new_cap)
2651 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2655 * _pci_add_cap_save_buffer - allocate buffer for saving given
2656 * capability registers
2657 * @dev: the PCI device
2658 * @cap: the capability to allocate the buffer for
2659 * @extended: Standard or Extended capability ID
2660 * @size: requested size of the buffer
2662 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2663 bool extended, unsigned int size)
2666 struct pci_cap_saved_state *save_state;
2669 pos = pci_find_ext_capability(dev, cap);
2671 pos = pci_find_capability(dev, cap);
2676 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2680 save_state->cap.cap_nr = cap;
2681 save_state->cap.cap_extended = extended;
2682 save_state->cap.size = size;
2683 pci_add_saved_cap(dev, save_state);
2688 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2690 return _pci_add_cap_save_buffer(dev, cap, false, size);
2693 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2695 return _pci_add_cap_save_buffer(dev, cap, true, size);
2699 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2700 * @dev: the PCI device
2702 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2706 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2707 PCI_EXP_SAVE_REGS * sizeof(u16));
2710 "unable to preallocate PCI Express save buffer\n");
2712 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2715 "unable to preallocate PCI-X save buffer\n");
2717 pci_allocate_vc_save_buffers(dev);
2720 void pci_free_cap_save_buffers(struct pci_dev *dev)
2722 struct pci_cap_saved_state *tmp;
2723 struct hlist_node *n;
2725 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2730 * pci_configure_ari - enable or disable ARI forwarding
2731 * @dev: the PCI device
2733 * If @dev and its upstream bridge both support ARI, enable ARI in the
2734 * bridge. Otherwise, disable ARI in the bridge.
2736 void pci_configure_ari(struct pci_dev *dev)
2739 struct pci_dev *bridge;
2741 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2744 bridge = dev->bus->self;
2748 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2749 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2752 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2753 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2754 PCI_EXP_DEVCTL2_ARI);
2755 bridge->ari_enabled = 1;
2757 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2758 PCI_EXP_DEVCTL2_ARI);
2759 bridge->ari_enabled = 0;
2763 static int pci_acs_enable;
2766 * pci_request_acs - ask for ACS to be enabled if supported
2768 void pci_request_acs(void)
2774 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2775 * @dev: the PCI device
2777 static void pci_std_enable_acs(struct pci_dev *dev)
2783 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2787 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2788 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2790 /* Source Validation */
2791 ctrl |= (cap & PCI_ACS_SV);
2793 /* P2P Request Redirect */
2794 ctrl |= (cap & PCI_ACS_RR);
2796 /* P2P Completion Redirect */
2797 ctrl |= (cap & PCI_ACS_CR);
2799 /* Upstream Forwarding */
2800 ctrl |= (cap & PCI_ACS_UF);
2802 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2806 * pci_enable_acs - enable ACS if hardware support it
2807 * @dev: the PCI device
2809 void pci_enable_acs(struct pci_dev *dev)
2811 if (!pci_acs_enable)
2814 if (!pci_dev_specific_enable_acs(dev))
2817 pci_std_enable_acs(dev);
2820 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2825 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2830 * Except for egress control, capabilities are either required
2831 * or only required if controllable. Features missing from the
2832 * capability field can therefore be assumed as hard-wired enabled.
2834 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2835 acs_flags &= (cap | PCI_ACS_EC);
2837 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2838 return (ctrl & acs_flags) == acs_flags;
2842 * pci_acs_enabled - test ACS against required flags for a given device
2843 * @pdev: device to test
2844 * @acs_flags: required PCI ACS flags
2846 * Return true if the device supports the provided flags. Automatically
2847 * filters out flags that are not implemented on multifunction devices.
2849 * Note that this interface checks the effective ACS capabilities of the
2850 * device rather than the actual capabilities. For instance, most single
2851 * function endpoints are not required to support ACS because they have no
2852 * opportunity for peer-to-peer access. We therefore return 'true'
2853 * regardless of whether the device exposes an ACS capability. This makes
2854 * it much easier for callers of this function to ignore the actual type
2855 * or topology of the device when testing ACS support.
2857 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2861 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2866 * Conventional PCI and PCI-X devices never support ACS, either
2867 * effectively or actually. The shared bus topology implies that
2868 * any device on the bus can receive or snoop DMA.
2870 if (!pci_is_pcie(pdev))
2873 switch (pci_pcie_type(pdev)) {
2875 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2876 * but since their primary interface is PCI/X, we conservatively
2877 * handle them as we would a non-PCIe device.
2879 case PCI_EXP_TYPE_PCIE_BRIDGE:
2881 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2882 * applicable... must never implement an ACS Extended Capability...".
2883 * This seems arbitrary, but we take a conservative interpretation
2884 * of this statement.
2886 case PCI_EXP_TYPE_PCI_BRIDGE:
2887 case PCI_EXP_TYPE_RC_EC:
2890 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2891 * implement ACS in order to indicate their peer-to-peer capabilities,
2892 * regardless of whether they are single- or multi-function devices.
2894 case PCI_EXP_TYPE_DOWNSTREAM:
2895 case PCI_EXP_TYPE_ROOT_PORT:
2896 return pci_acs_flags_enabled(pdev, acs_flags);
2898 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2899 * implemented by the remaining PCIe types to indicate peer-to-peer
2900 * capabilities, but only when they are part of a multifunction
2901 * device. The footnote for section 6.12 indicates the specific
2902 * PCIe types included here.
2904 case PCI_EXP_TYPE_ENDPOINT:
2905 case PCI_EXP_TYPE_UPSTREAM:
2906 case PCI_EXP_TYPE_LEG_END:
2907 case PCI_EXP_TYPE_RC_END:
2908 if (!pdev->multifunction)
2911 return pci_acs_flags_enabled(pdev, acs_flags);
2915 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2916 * to single function devices with the exception of downstream ports.
2922 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2923 * @start: starting downstream device
2924 * @end: ending upstream device or NULL to search to the root bus
2925 * @acs_flags: required flags
2927 * Walk up a device tree from start to end testing PCI ACS support. If
2928 * any step along the way does not support the required flags, return false.
2930 bool pci_acs_path_enabled(struct pci_dev *start,
2931 struct pci_dev *end, u16 acs_flags)
2933 struct pci_dev *pdev, *parent = start;
2938 if (!pci_acs_enabled(pdev, acs_flags))
2941 if (pci_is_root_bus(pdev->bus))
2942 return (end == NULL);
2944 parent = pdev->bus->self;
2945 } while (pdev != end);
2951 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2952 * @dev: the PCI device
2953 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2955 * Perform INTx swizzling for a device behind one level of bridge. This is
2956 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2957 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2958 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2959 * the PCI Express Base Specification, Revision 2.1)
2961 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2965 if (pci_ari_enabled(dev->bus))
2968 slot = PCI_SLOT(dev->devfn);
2970 return (((pin - 1) + slot) % 4) + 1;
2973 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2981 while (!pci_is_root_bus(dev->bus)) {
2982 pin = pci_swizzle_interrupt_pin(dev, pin);
2983 dev = dev->bus->self;
2990 * pci_common_swizzle - swizzle INTx all the way to root bridge
2991 * @dev: the PCI device
2992 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2994 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2995 * bridges all the way up to a PCI root bus.
2997 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3001 while (!pci_is_root_bus(dev->bus)) {
3002 pin = pci_swizzle_interrupt_pin(dev, pin);
3003 dev = dev->bus->self;
3006 return PCI_SLOT(dev->devfn);
3008 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3011 * pci_release_region - Release a PCI bar
3012 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3013 * @bar: BAR to release
3015 * Releases the PCI I/O and memory resources previously reserved by a
3016 * successful call to pci_request_region. Call this function only
3017 * after all use of the PCI regions has ceased.
3019 void pci_release_region(struct pci_dev *pdev, int bar)
3021 struct pci_devres *dr;
3023 if (pci_resource_len(pdev, bar) == 0)
3025 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3026 release_region(pci_resource_start(pdev, bar),
3027 pci_resource_len(pdev, bar));
3028 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3029 release_mem_region(pci_resource_start(pdev, bar),
3030 pci_resource_len(pdev, bar));
3032 dr = find_pci_dr(pdev);
3034 dr->region_mask &= ~(1 << bar);
3036 EXPORT_SYMBOL(pci_release_region);
3039 * __pci_request_region - Reserved PCI I/O and memory resource
3040 * @pdev: PCI device whose resources are to be reserved
3041 * @bar: BAR to be reserved
3042 * @res_name: Name to be associated with resource.
3043 * @exclusive: whether the region access is exclusive or not
3045 * Mark the PCI region associated with PCI device @pdev BR @bar as
3046 * being reserved by owner @res_name. Do not access any
3047 * address inside the PCI regions unless this call returns
3050 * If @exclusive is set, then the region is marked so that userspace
3051 * is explicitly not allowed to map the resource via /dev/mem or
3052 * sysfs MMIO access.
3054 * Returns 0 on success, or %EBUSY on error. A warning
3055 * message is also printed on failure.
3057 static int __pci_request_region(struct pci_dev *pdev, int bar,
3058 const char *res_name, int exclusive)
3060 struct pci_devres *dr;
3062 if (pci_resource_len(pdev, bar) == 0)
3065 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3066 if (!request_region(pci_resource_start(pdev, bar),
3067 pci_resource_len(pdev, bar), res_name))
3069 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3070 if (!__request_mem_region(pci_resource_start(pdev, bar),
3071 pci_resource_len(pdev, bar), res_name,
3076 dr = find_pci_dr(pdev);
3078 dr->region_mask |= 1 << bar;
3083 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
3084 &pdev->resource[bar]);
3089 * pci_request_region - Reserve PCI I/O and memory resource
3090 * @pdev: PCI device whose resources are to be reserved
3091 * @bar: BAR to be reserved
3092 * @res_name: Name to be associated with resource
3094 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3095 * being reserved by owner @res_name. Do not access any
3096 * address inside the PCI regions unless this call returns
3099 * Returns 0 on success, or %EBUSY on error. A warning
3100 * message is also printed on failure.
3102 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3104 return __pci_request_region(pdev, bar, res_name, 0);
3106 EXPORT_SYMBOL(pci_request_region);
3109 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3110 * @pdev: PCI device whose resources are to be reserved
3111 * @bar: BAR to be reserved
3112 * @res_name: Name to be associated with resource.
3114 * Mark the PCI region associated with PCI device @pdev BR @bar as
3115 * being reserved by owner @res_name. Do not access any
3116 * address inside the PCI regions unless this call returns
3119 * Returns 0 on success, or %EBUSY on error. A warning
3120 * message is also printed on failure.
3122 * The key difference that _exclusive makes it that userspace is
3123 * explicitly not allowed to map the resource via /dev/mem or
3126 int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3127 const char *res_name)
3129 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3131 EXPORT_SYMBOL(pci_request_region_exclusive);
3134 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3135 * @pdev: PCI device whose resources were previously reserved
3136 * @bars: Bitmask of BARs to be released
3138 * Release selected PCI I/O and memory resources previously reserved.
3139 * Call this function only after all use of the PCI regions has ceased.
3141 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3145 for (i = 0; i < 6; i++)
3146 if (bars & (1 << i))
3147 pci_release_region(pdev, i);
3149 EXPORT_SYMBOL(pci_release_selected_regions);
3151 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3152 const char *res_name, int excl)
3156 for (i = 0; i < 6; i++)
3157 if (bars & (1 << i))
3158 if (__pci_request_region(pdev, i, res_name, excl))
3164 if (bars & (1 << i))
3165 pci_release_region(pdev, i);
3172 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3173 * @pdev: PCI device whose resources are to be reserved
3174 * @bars: Bitmask of BARs to be requested
3175 * @res_name: Name to be associated with resource
3177 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3178 const char *res_name)
3180 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3182 EXPORT_SYMBOL(pci_request_selected_regions);
3184 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3185 const char *res_name)
3187 return __pci_request_selected_regions(pdev, bars, res_name,
3188 IORESOURCE_EXCLUSIVE);
3190 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
3193 * pci_release_regions - Release reserved PCI I/O and memory resources
3194 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3196 * Releases all PCI I/O and memory resources previously reserved by a
3197 * successful call to pci_request_regions. Call this function only
3198 * after all use of the PCI regions has ceased.
3201 void pci_release_regions(struct pci_dev *pdev)
3203 pci_release_selected_regions(pdev, (1 << 6) - 1);
3205 EXPORT_SYMBOL(pci_release_regions);
3208 * pci_request_regions - Reserved PCI I/O and memory resources
3209 * @pdev: PCI device whose resources are to be reserved
3210 * @res_name: Name to be associated with resource.
3212 * Mark all PCI regions associated with PCI device @pdev as
3213 * being reserved by owner @res_name. Do not access any
3214 * address inside the PCI regions unless this call returns
3217 * Returns 0 on success, or %EBUSY on error. A warning
3218 * message is also printed on failure.
3220 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
3222 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
3224 EXPORT_SYMBOL(pci_request_regions);
3227 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3228 * @pdev: PCI device whose resources are to be reserved
3229 * @res_name: Name to be associated with resource.
3231 * Mark all PCI regions associated with PCI device @pdev as
3232 * being reserved by owner @res_name. Do not access any
3233 * address inside the PCI regions unless this call returns
3236 * pci_request_regions_exclusive() will mark the region so that
3237 * /dev/mem and the sysfs MMIO access will not be allowed.
3239 * Returns 0 on success, or %EBUSY on error. A warning
3240 * message is also printed on failure.
3242 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3244 return pci_request_selected_regions_exclusive(pdev,
3245 ((1 << 6) - 1), res_name);
3247 EXPORT_SYMBOL(pci_request_regions_exclusive);
3251 struct list_head list;
3253 resource_size_t size;
3256 static LIST_HEAD(io_range_list);
3257 static DEFINE_SPINLOCK(io_range_lock);
3261 * Record the PCI IO range (expressed as CPU physical address + size).
3262 * Return a negative value if an error has occured, zero otherwise
3264 int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
3269 struct io_range *range;
3270 resource_size_t allocated_size = 0;
3272 /* check if the range hasn't been previously recorded */
3273 spin_lock(&io_range_lock);
3274 list_for_each_entry(range, &io_range_list, list) {
3275 if (addr >= range->start && addr + size <= range->start + size) {
3276 /* range already registered, bail out */
3279 allocated_size += range->size;
3282 /* range not registed yet, check for available space */
3283 if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
3284 /* if it's too big check if 64K space can be reserved */
3285 if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
3291 pr_warn("Requested IO range too big, new size set to 64K\n");
3294 /* add the range to the list */
3295 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3301 range->start = addr;
3304 list_add_tail(&range->list, &io_range_list);
3307 spin_unlock(&io_range_lock);
3313 phys_addr_t pci_pio_to_address(unsigned long pio)
3315 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3318 struct io_range *range;
3319 resource_size_t allocated_size = 0;
3321 if (pio > IO_SPACE_LIMIT)
3324 spin_lock(&io_range_lock);
3325 list_for_each_entry(range, &io_range_list, list) {
3326 if (pio >= allocated_size && pio < allocated_size + range->size) {
3327 address = range->start + pio - allocated_size;
3330 allocated_size += range->size;
3332 spin_unlock(&io_range_lock);
3338 unsigned long __weak pci_address_to_pio(phys_addr_t address)
3341 struct io_range *res;
3342 resource_size_t offset = 0;
3343 unsigned long addr = -1;
3345 spin_lock(&io_range_lock);
3346 list_for_each_entry(res, &io_range_list, list) {
3347 if (address >= res->start && address < res->start + res->size) {
3348 addr = address - res->start + offset;
3351 offset += res->size;
3353 spin_unlock(&io_range_lock);
3357 if (address > IO_SPACE_LIMIT)
3358 return (unsigned long)-1;
3360 return (unsigned long) address;
3365 * pci_remap_iospace - Remap the memory mapped I/O space
3366 * @res: Resource describing the I/O space
3367 * @phys_addr: physical address of range to be mapped
3369 * Remap the memory mapped I/O space described by the @res
3370 * and the CPU physical address @phys_addr into virtual address space.
3371 * Only architectures that have memory mapped IO functions defined
3372 * (and the PCI_IOBASE value defined) should call this function.
3374 int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3376 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3377 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3379 if (!(res->flags & IORESOURCE_IO))
3382 if (res->end > IO_SPACE_LIMIT)
3385 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3386 pgprot_device(PAGE_KERNEL));
3388 /* this architecture does not have memory mapped I/O space,
3389 so this function should never be called */
3390 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3396 * pci_unmap_iospace - Unmap the memory mapped I/O space
3397 * @res: resource to be unmapped
3399 * Unmap the CPU virtual address @res from virtual address space.
3400 * Only architectures that have memory mapped IO functions defined
3401 * (and the PCI_IOBASE value defined) should call this function.
3403 void pci_unmap_iospace(struct resource *res)
3405 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3406 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3408 unmap_kernel_range(vaddr, resource_size(res));
3412 static void __pci_set_master(struct pci_dev *dev, bool enable)
3416 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3418 cmd = old_cmd | PCI_COMMAND_MASTER;
3420 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3421 if (cmd != old_cmd) {
3422 dev_dbg(&dev->dev, "%s bus mastering\n",
3423 enable ? "enabling" : "disabling");
3424 pci_write_config_word(dev, PCI_COMMAND, cmd);
3426 dev->is_busmaster = enable;
3430 * pcibios_setup - process "pci=" kernel boot arguments
3431 * @str: string used to pass in "pci=" kernel boot arguments
3433 * Process kernel boot arguments. This is the default implementation.
3434 * Architecture specific implementations can override this as necessary.
3436 char * __weak __init pcibios_setup(char *str)
3442 * pcibios_set_master - enable PCI bus-mastering for device dev
3443 * @dev: the PCI device to enable
3445 * Enables PCI bus-mastering for the device. This is the default
3446 * implementation. Architecture specific implementations can override
3447 * this if necessary.
3449 void __weak pcibios_set_master(struct pci_dev *dev)
3453 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3454 if (pci_is_pcie(dev))
3457 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3459 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3460 else if (lat > pcibios_max_latency)
3461 lat = pcibios_max_latency;
3465 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3469 * pci_set_master - enables bus-mastering for device dev
3470 * @dev: the PCI device to enable
3472 * Enables bus-mastering on the device and calls pcibios_set_master()
3473 * to do the needed arch specific settings.
3475 void pci_set_master(struct pci_dev *dev)
3477 __pci_set_master(dev, true);
3478 pcibios_set_master(dev);
3480 EXPORT_SYMBOL(pci_set_master);
3483 * pci_clear_master - disables bus-mastering for device dev
3484 * @dev: the PCI device to disable
3486 void pci_clear_master(struct pci_dev *dev)
3488 __pci_set_master(dev, false);
3490 EXPORT_SYMBOL(pci_clear_master);
3493 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3494 * @dev: the PCI device for which MWI is to be enabled
3496 * Helper function for pci_set_mwi.
3497 * Originally copied from drivers/net/acenic.c.
3498 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3500 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3502 int pci_set_cacheline_size(struct pci_dev *dev)
3506 if (!pci_cache_line_size)
3509 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3510 equal to or multiple of the right value. */
3511 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3512 if (cacheline_size >= pci_cache_line_size &&
3513 (cacheline_size % pci_cache_line_size) == 0)
3516 /* Write the correct value. */
3517 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3519 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3520 if (cacheline_size == pci_cache_line_size)
3523 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
3524 pci_cache_line_size << 2);
3528 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3531 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3532 * @dev: the PCI device for which MWI is enabled
3534 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3536 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3538 int pci_set_mwi(struct pci_dev *dev)
3540 #ifdef PCI_DISABLE_MWI
3546 rc = pci_set_cacheline_size(dev);
3550 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3551 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
3552 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
3553 cmd |= PCI_COMMAND_INVALIDATE;
3554 pci_write_config_word(dev, PCI_COMMAND, cmd);
3559 EXPORT_SYMBOL(pci_set_mwi);
3562 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3563 * @dev: the PCI device for which MWI is enabled
3565 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3566 * Callers are not required to check the return value.
3568 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3570 int pci_try_set_mwi(struct pci_dev *dev)
3572 #ifdef PCI_DISABLE_MWI
3575 return pci_set_mwi(dev);
3578 EXPORT_SYMBOL(pci_try_set_mwi);
3581 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3582 * @dev: the PCI device to disable
3584 * Disables PCI Memory-Write-Invalidate transaction on the device
3586 void pci_clear_mwi(struct pci_dev *dev)
3588 #ifndef PCI_DISABLE_MWI
3591 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3592 if (cmd & PCI_COMMAND_INVALIDATE) {
3593 cmd &= ~PCI_COMMAND_INVALIDATE;
3594 pci_write_config_word(dev, PCI_COMMAND, cmd);
3598 EXPORT_SYMBOL(pci_clear_mwi);
3601 * pci_intx - enables/disables PCI INTx for device dev
3602 * @pdev: the PCI device to operate on
3603 * @enable: boolean: whether to enable or disable PCI INTx
3605 * Enables/disables PCI INTx for device dev
3607 void pci_intx(struct pci_dev *pdev, int enable)
3609 u16 pci_command, new;
3611 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3614 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3616 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3618 if (new != pci_command) {
3619 struct pci_devres *dr;
3621 pci_write_config_word(pdev, PCI_COMMAND, new);
3623 dr = find_pci_dr(pdev);
3624 if (dr && !dr->restore_intx) {
3625 dr->restore_intx = 1;
3626 dr->orig_intx = !enable;
3630 EXPORT_SYMBOL_GPL(pci_intx);
3633 * pci_intx_mask_supported - probe for INTx masking support
3634 * @dev: the PCI device to operate on
3636 * Check if the device dev support INTx masking via the config space
3639 bool pci_intx_mask_supported(struct pci_dev *dev)
3641 bool mask_supported = false;
3644 if (dev->broken_intx_masking)
3647 pci_cfg_access_lock(dev);
3649 pci_read_config_word(dev, PCI_COMMAND, &orig);
3650 pci_write_config_word(dev, PCI_COMMAND,
3651 orig ^ PCI_COMMAND_INTX_DISABLE);
3652 pci_read_config_word(dev, PCI_COMMAND, &new);
3655 * There's no way to protect against hardware bugs or detect them
3656 * reliably, but as long as we know what the value should be, let's
3657 * go ahead and check it.
3659 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
3660 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3662 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3663 mask_supported = true;
3664 pci_write_config_word(dev, PCI_COMMAND, orig);
3667 pci_cfg_access_unlock(dev);
3668 return mask_supported;
3670 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3672 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3674 struct pci_bus *bus = dev->bus;
3675 bool mask_updated = true;
3676 u32 cmd_status_dword;
3677 u16 origcmd, newcmd;
3678 unsigned long flags;
3682 * We do a single dword read to retrieve both command and status.
3683 * Document assumptions that make this possible.
3685 BUILD_BUG_ON(PCI_COMMAND % 4);
3686 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3688 raw_spin_lock_irqsave(&pci_lock, flags);
3690 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3692 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3695 * Check interrupt status register to see whether our device
3696 * triggered the interrupt (when masking) or the next IRQ is
3697 * already pending (when unmasking).
3699 if (mask != irq_pending) {
3700 mask_updated = false;
3704 origcmd = cmd_status_dword;
3705 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3707 newcmd |= PCI_COMMAND_INTX_DISABLE;
3708 if (newcmd != origcmd)
3709 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3712 raw_spin_unlock_irqrestore(&pci_lock, flags);
3714 return mask_updated;
3718 * pci_check_and_mask_intx - mask INTx on pending interrupt
3719 * @dev: the PCI device to operate on
3721 * Check if the device dev has its INTx line asserted, mask it and
3722 * return true in that case. False is returned if not interrupt was
3725 bool pci_check_and_mask_intx(struct pci_dev *dev)
3727 return pci_check_and_set_intx_mask(dev, true);
3729 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3732 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3733 * @dev: the PCI device to operate on
3735 * Check if the device dev has its INTx line asserted, unmask it if not
3736 * and return true. False is returned and the mask remains active if
3737 * there was still an interrupt pending.
3739 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3741 return pci_check_and_set_intx_mask(dev, false);
3743 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3746 * pci_wait_for_pending_transaction - waits for pending transaction
3747 * @dev: the PCI device to operate on
3749 * Return 0 if transaction is pending 1 otherwise.
3751 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3753 if (!pci_is_pcie(dev))
3756 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3757 PCI_EXP_DEVSTA_TRPND);
3759 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3762 * We should only need to wait 100ms after FLR, but some devices take longer.
3763 * Wait for up to 1000ms for config space to return something other than -1.
3764 * Intel IGD requires this when an LCD panel is attached. We read the 2nd
3765 * dword because VFs don't implement the 1st dword.
3767 static void pci_flr_wait(struct pci_dev *dev)
3774 pci_read_config_dword(dev, PCI_COMMAND, &id);
3775 } while (i++ < 10 && id == ~0);
3778 dev_warn(&dev->dev, "Failed to return from FLR\n");
3780 dev_info(&dev->dev, "Required additional %dms to return from FLR\n",
3784 static int pcie_flr(struct pci_dev *dev, int probe)
3788 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3789 if (!(cap & PCI_EXP_DEVCAP_FLR))
3795 if (!pci_wait_for_pending_transaction(dev))
3796 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
3798 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3803 static int pci_af_flr(struct pci_dev *dev, int probe)
3808 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3812 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3813 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3820 * Wait for Transaction Pending bit to clear. A word-aligned test
3821 * is used, so we use the conrol offset rather than status and shift
3822 * the test bit to match.
3824 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
3825 PCI_AF_STATUS_TP << 8))
3826 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
3828 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3834 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3835 * @dev: Device to reset.
3836 * @probe: If set, only check if the device can be reset this way.
3838 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3839 * unset, it will be reinitialized internally when going from PCI_D3hot to
3840 * PCI_D0. If that's the case and the device is not in a low-power state
3841 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3843 * NOTE: This causes the caller to sleep for twice the device power transition
3844 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3845 * by default (i.e. unless the @dev's d3_delay field has a different value).
3846 * Moreover, only devices in D0 can be reset by this function.
3848 static int pci_pm_reset(struct pci_dev *dev, int probe)
3852 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
3855 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3856 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3862 if (dev->current_state != PCI_D0)
3865 csr &= ~PCI_PM_CTRL_STATE_MASK;
3867 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3868 pci_dev_d3_sleep(dev);
3870 csr &= ~PCI_PM_CTRL_STATE_MASK;
3872 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3873 pci_dev_d3_sleep(dev);
3878 void pci_reset_secondary_bus(struct pci_dev *dev)
3882 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3883 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3884 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3886 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3887 * this to 2ms to ensure that we meet the minimum requirement.
3891 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3892 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3895 * Trhfa for conventional PCI is 2^25 clock cycles.
3896 * Assuming a minimum 33MHz clock this results in a 1s
3897 * delay before we can consider subordinate devices to
3898 * be re-initialized. PCIe has some ways to shorten this,
3899 * but we don't make use of them yet.
3904 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3906 pci_reset_secondary_bus(dev);
3910 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3911 * @dev: Bridge device
3913 * Use the bridge control register to assert reset on the secondary bus.
3914 * Devices on the secondary bus are left in power-on state.
3916 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3918 pcibios_reset_secondary_bus(dev);
3920 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3922 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3924 struct pci_dev *pdev;
3926 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
3927 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3930 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3937 pci_reset_bridge_secondary_bus(dev->bus->self);
3942 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3946 if (!hotplug || !try_module_get(hotplug->ops->owner))
3949 if (hotplug->ops->reset_slot)
3950 rc = hotplug->ops->reset_slot(hotplug, probe);
3952 module_put(hotplug->ops->owner);
3957 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3959 struct pci_dev *pdev;
3961 if (dev->subordinate || !dev->slot ||
3962 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
3965 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3966 if (pdev != dev && pdev->slot == dev->slot)
3969 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3972 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3978 rc = pci_dev_specific_reset(dev, probe);
3982 rc = pcie_flr(dev, probe);
3986 rc = pci_af_flr(dev, probe);
3990 rc = pci_pm_reset(dev, probe);
3994 rc = pci_dev_reset_slot_function(dev, probe);
3998 rc = pci_parent_bus_reset(dev, probe);
4003 static void pci_dev_lock(struct pci_dev *dev)
4005 pci_cfg_access_lock(dev);
4006 /* block PM suspend, driver probe, etc. */
4007 device_lock(&dev->dev);
4010 /* Return 1 on successful lock, 0 on contention */
4011 static int pci_dev_trylock(struct pci_dev *dev)
4013 if (pci_cfg_access_trylock(dev)) {
4014 if (device_trylock(&dev->dev))
4016 pci_cfg_access_unlock(dev);
4022 static void pci_dev_unlock(struct pci_dev *dev)
4024 device_unlock(&dev->dev);
4025 pci_cfg_access_unlock(dev);
4029 * pci_reset_notify - notify device driver of reset
4030 * @dev: device to be notified of reset
4031 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
4034 * Must be called prior to device access being disabled and after device
4035 * access is restored.
4037 static void pci_reset_notify(struct pci_dev *dev, bool prepare)
4039 const struct pci_error_handlers *err_handler =
4040 dev->driver ? dev->driver->err_handler : NULL;
4041 if (err_handler && err_handler->reset_notify)
4042 err_handler->reset_notify(dev, prepare);
4045 static void pci_dev_save_and_disable(struct pci_dev *dev)
4047 pci_reset_notify(dev, true);
4050 * Wake-up device prior to save. PM registers default to D0 after
4051 * reset and a simple register restore doesn't reliably return
4052 * to a non-D0 state anyway.
4054 pci_set_power_state(dev, PCI_D0);
4056 pci_save_state(dev);
4058 * Disable the device by clearing the Command register, except for
4059 * INTx-disable which is set. This not only disables MMIO and I/O port
4060 * BARs, but also prevents the device from being Bus Master, preventing
4061 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4062 * compliant devices, INTx-disable prevents legacy interrupts.
4064 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4067 static void pci_dev_restore(struct pci_dev *dev)
4069 pci_restore_state(dev);
4070 pci_reset_notify(dev, false);
4073 static int pci_dev_reset(struct pci_dev *dev, int probe)
4080 rc = __pci_dev_reset(dev, probe);
4083 pci_dev_unlock(dev);
4089 * __pci_reset_function - reset a PCI device function
4090 * @dev: PCI device to reset
4092 * Some devices allow an individual function to be reset without affecting
4093 * other functions in the same device. The PCI device must be responsive
4094 * to PCI config space in order to use this function.
4096 * The device function is presumed to be unused when this function is called.
4097 * Resetting the device will make the contents of PCI configuration space
4098 * random, so any caller of this must be prepared to reinitialise the
4099 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4102 * Returns 0 if the device function was successfully reset or negative if the
4103 * device doesn't support resetting a single function.
4105 int __pci_reset_function(struct pci_dev *dev)
4107 return pci_dev_reset(dev, 0);
4109 EXPORT_SYMBOL_GPL(__pci_reset_function);
4112 * __pci_reset_function_locked - reset a PCI device function while holding
4113 * the @dev mutex lock.
4114 * @dev: PCI device to reset
4116 * Some devices allow an individual function to be reset without affecting
4117 * other functions in the same device. The PCI device must be responsive
4118 * to PCI config space in order to use this function.
4120 * The device function is presumed to be unused and the caller is holding
4121 * the device mutex lock when this function is called.
4122 * Resetting the device will make the contents of PCI configuration space
4123 * random, so any caller of this must be prepared to reinitialise the
4124 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4127 * Returns 0 if the device function was successfully reset or negative if the
4128 * device doesn't support resetting a single function.
4130 int __pci_reset_function_locked(struct pci_dev *dev)
4132 return __pci_dev_reset(dev, 0);
4134 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4137 * pci_probe_reset_function - check whether the device can be safely reset
4138 * @dev: PCI device to reset
4140 * Some devices allow an individual function to be reset without affecting
4141 * other functions in the same device. The PCI device must be responsive
4142 * to PCI config space in order to use this function.
4144 * Returns 0 if the device function can be reset or negative if the
4145 * device doesn't support resetting a single function.
4147 int pci_probe_reset_function(struct pci_dev *dev)
4149 return pci_dev_reset(dev, 1);
4153 * pci_reset_function - quiesce and reset a PCI device function
4154 * @dev: PCI device to reset
4156 * Some devices allow an individual function to be reset without affecting
4157 * other functions in the same device. The PCI device must be responsive
4158 * to PCI config space in order to use this function.
4160 * This function does not just reset the PCI portion of a device, but
4161 * clears all the state associated with the device. This function differs
4162 * from __pci_reset_function in that it saves and restores device state
4165 * Returns 0 if the device function was successfully reset or negative if the
4166 * device doesn't support resetting a single function.
4168 int pci_reset_function(struct pci_dev *dev)
4172 rc = pci_dev_reset(dev, 1);
4176 pci_dev_save_and_disable(dev);
4178 rc = pci_dev_reset(dev, 0);
4180 pci_dev_restore(dev);
4184 EXPORT_SYMBOL_GPL(pci_reset_function);
4187 * pci_try_reset_function - quiesce and reset a PCI device function
4188 * @dev: PCI device to reset
4190 * Same as above, except return -EAGAIN if unable to lock device.
4192 int pci_try_reset_function(struct pci_dev *dev)
4196 rc = pci_dev_reset(dev, 1);
4200 pci_dev_save_and_disable(dev);
4202 if (pci_dev_trylock(dev)) {
4203 rc = __pci_dev_reset(dev, 0);
4204 pci_dev_unlock(dev);
4208 pci_dev_restore(dev);
4212 EXPORT_SYMBOL_GPL(pci_try_reset_function);
4214 /* Do any devices on or below this bus prevent a bus reset? */
4215 static bool pci_bus_resetable(struct pci_bus *bus)
4217 struct pci_dev *dev;
4219 list_for_each_entry(dev, &bus->devices, bus_list) {
4220 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4221 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4228 /* Lock devices from the top of the tree down */
4229 static void pci_bus_lock(struct pci_bus *bus)
4231 struct pci_dev *dev;
4233 list_for_each_entry(dev, &bus->devices, bus_list) {
4235 if (dev->subordinate)
4236 pci_bus_lock(dev->subordinate);
4240 /* Unlock devices from the bottom of the tree up */
4241 static void pci_bus_unlock(struct pci_bus *bus)
4243 struct pci_dev *dev;
4245 list_for_each_entry(dev, &bus->devices, bus_list) {
4246 if (dev->subordinate)
4247 pci_bus_unlock(dev->subordinate);
4248 pci_dev_unlock(dev);
4252 /* Return 1 on successful lock, 0 on contention */
4253 static int pci_bus_trylock(struct pci_bus *bus)
4255 struct pci_dev *dev;
4257 list_for_each_entry(dev, &bus->devices, bus_list) {
4258 if (!pci_dev_trylock(dev))
4260 if (dev->subordinate) {
4261 if (!pci_bus_trylock(dev->subordinate)) {
4262 pci_dev_unlock(dev);
4270 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4271 if (dev->subordinate)
4272 pci_bus_unlock(dev->subordinate);
4273 pci_dev_unlock(dev);
4278 /* Do any devices on or below this slot prevent a bus reset? */
4279 static bool pci_slot_resetable(struct pci_slot *slot)
4281 struct pci_dev *dev;
4283 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4284 if (!dev->slot || dev->slot != slot)
4286 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4287 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4294 /* Lock devices from the top of the tree down */
4295 static void pci_slot_lock(struct pci_slot *slot)
4297 struct pci_dev *dev;
4299 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4300 if (!dev->slot || dev->slot != slot)
4303 if (dev->subordinate)
4304 pci_bus_lock(dev->subordinate);
4308 /* Unlock devices from the bottom of the tree up */
4309 static void pci_slot_unlock(struct pci_slot *slot)
4311 struct pci_dev *dev;
4313 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4314 if (!dev->slot || dev->slot != slot)
4316 if (dev->subordinate)
4317 pci_bus_unlock(dev->subordinate);
4318 pci_dev_unlock(dev);
4322 /* Return 1 on successful lock, 0 on contention */
4323 static int pci_slot_trylock(struct pci_slot *slot)
4325 struct pci_dev *dev;
4327 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4328 if (!dev->slot || dev->slot != slot)
4330 if (!pci_dev_trylock(dev))
4332 if (dev->subordinate) {
4333 if (!pci_bus_trylock(dev->subordinate)) {
4334 pci_dev_unlock(dev);
4342 list_for_each_entry_continue_reverse(dev,
4343 &slot->bus->devices, bus_list) {
4344 if (!dev->slot || dev->slot != slot)
4346 if (dev->subordinate)
4347 pci_bus_unlock(dev->subordinate);
4348 pci_dev_unlock(dev);
4353 /* Save and disable devices from the top of the tree down */
4354 static void pci_bus_save_and_disable(struct pci_bus *bus)
4356 struct pci_dev *dev;
4358 list_for_each_entry(dev, &bus->devices, bus_list) {
4359 pci_dev_save_and_disable(dev);
4360 if (dev->subordinate)
4361 pci_bus_save_and_disable(dev->subordinate);
4366 * Restore devices from top of the tree down - parent bridges need to be
4367 * restored before we can get to subordinate devices.
4369 static void pci_bus_restore(struct pci_bus *bus)
4371 struct pci_dev *dev;
4373 list_for_each_entry(dev, &bus->devices, bus_list) {
4374 pci_dev_restore(dev);
4375 if (dev->subordinate)
4376 pci_bus_restore(dev->subordinate);
4380 /* Save and disable devices from the top of the tree down */
4381 static void pci_slot_save_and_disable(struct pci_slot *slot)
4383 struct pci_dev *dev;
4385 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4386 if (!dev->slot || dev->slot != slot)
4388 pci_dev_save_and_disable(dev);
4389 if (dev->subordinate)
4390 pci_bus_save_and_disable(dev->subordinate);
4395 * Restore devices from top of the tree down - parent bridges need to be
4396 * restored before we can get to subordinate devices.
4398 static void pci_slot_restore(struct pci_slot *slot)
4400 struct pci_dev *dev;
4402 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4403 if (!dev->slot || dev->slot != slot)
4405 pci_dev_restore(dev);
4406 if (dev->subordinate)
4407 pci_bus_restore(dev->subordinate);
4411 static int pci_slot_reset(struct pci_slot *slot, int probe)
4415 if (!slot || !pci_slot_resetable(slot))
4419 pci_slot_lock(slot);
4423 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4426 pci_slot_unlock(slot);
4432 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4433 * @slot: PCI slot to probe
4435 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4437 int pci_probe_reset_slot(struct pci_slot *slot)
4439 return pci_slot_reset(slot, 1);
4441 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4444 * pci_reset_slot - reset a PCI slot
4445 * @slot: PCI slot to reset
4447 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4448 * independent of other slots. For instance, some slots may support slot power
4449 * control. In the case of a 1:1 bus to slot architecture, this function may
4450 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4451 * Generally a slot reset should be attempted before a bus reset. All of the
4452 * function of the slot and any subordinate buses behind the slot are reset
4453 * through this function. PCI config space of all devices in the slot and
4454 * behind the slot is saved before and restored after reset.
4456 * Return 0 on success, non-zero on error.
4458 int pci_reset_slot(struct pci_slot *slot)
4462 rc = pci_slot_reset(slot, 1);
4466 pci_slot_save_and_disable(slot);
4468 rc = pci_slot_reset(slot, 0);
4470 pci_slot_restore(slot);
4474 EXPORT_SYMBOL_GPL(pci_reset_slot);
4477 * pci_try_reset_slot - Try to reset a PCI slot
4478 * @slot: PCI slot to reset
4480 * Same as above except return -EAGAIN if the slot cannot be locked
4482 int pci_try_reset_slot(struct pci_slot *slot)
4486 rc = pci_slot_reset(slot, 1);
4490 pci_slot_save_and_disable(slot);
4492 if (pci_slot_trylock(slot)) {
4494 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4495 pci_slot_unlock(slot);
4499 pci_slot_restore(slot);
4503 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4505 static int pci_bus_reset(struct pci_bus *bus, int probe)
4507 if (!bus->self || !pci_bus_resetable(bus))
4517 pci_reset_bridge_secondary_bus(bus->self);
4519 pci_bus_unlock(bus);
4525 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4526 * @bus: PCI bus to probe
4528 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4530 int pci_probe_reset_bus(struct pci_bus *bus)
4532 return pci_bus_reset(bus, 1);
4534 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4537 * pci_reset_bus - reset a PCI bus
4538 * @bus: top level PCI bus to reset
4540 * Do a bus reset on the given bus and any subordinate buses, saving
4541 * and restoring state of all devices.
4543 * Return 0 on success, non-zero on error.
4545 int pci_reset_bus(struct pci_bus *bus)
4549 rc = pci_bus_reset(bus, 1);
4553 pci_bus_save_and_disable(bus);
4555 rc = pci_bus_reset(bus, 0);
4557 pci_bus_restore(bus);
4561 EXPORT_SYMBOL_GPL(pci_reset_bus);
4564 * pci_try_reset_bus - Try to reset a PCI bus
4565 * @bus: top level PCI bus to reset
4567 * Same as above except return -EAGAIN if the bus cannot be locked
4569 int pci_try_reset_bus(struct pci_bus *bus)
4573 rc = pci_bus_reset(bus, 1);
4577 pci_bus_save_and_disable(bus);
4579 if (pci_bus_trylock(bus)) {
4581 pci_reset_bridge_secondary_bus(bus->self);
4582 pci_bus_unlock(bus);
4586 pci_bus_restore(bus);
4590 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
4593 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4594 * @dev: PCI device to query
4596 * Returns mmrbc: maximum designed memory read count in bytes
4597 * or appropriate error value.
4599 int pcix_get_max_mmrbc(struct pci_dev *dev)
4604 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4608 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4611 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
4613 EXPORT_SYMBOL(pcix_get_max_mmrbc);
4616 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4617 * @dev: PCI device to query
4619 * Returns mmrbc: maximum memory read count in bytes
4620 * or appropriate error value.
4622 int pcix_get_mmrbc(struct pci_dev *dev)
4627 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4631 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4634 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
4636 EXPORT_SYMBOL(pcix_get_mmrbc);
4639 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4640 * @dev: PCI device to query
4641 * @mmrbc: maximum memory read count in bytes
4642 * valid values are 512, 1024, 2048, 4096
4644 * If possible sets maximum memory read byte count, some bridges have erratas
4645 * that prevent this.
4647 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4653 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
4656 v = ffs(mmrbc) - 10;
4658 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4662 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4665 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4668 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4671 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4673 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
4676 cmd &= ~PCI_X_CMD_MAX_READ;
4678 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4683 EXPORT_SYMBOL(pcix_set_mmrbc);
4686 * pcie_get_readrq - get PCI Express read request size
4687 * @dev: PCI device to query
4689 * Returns maximum memory read request in bytes
4690 * or appropriate error value.
4692 int pcie_get_readrq(struct pci_dev *dev)
4696 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4698 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4700 EXPORT_SYMBOL(pcie_get_readrq);
4703 * pcie_set_readrq - set PCI Express maximum memory read request
4704 * @dev: PCI device to query
4705 * @rq: maximum memory read count in bytes
4706 * valid values are 128, 256, 512, 1024, 2048, 4096
4708 * If possible sets maximum memory read request in bytes
4710 int pcie_set_readrq(struct pci_dev *dev, int rq)
4714 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4718 * If using the "performance" PCIe config, we clamp the
4719 * read rq size to the max packet size to prevent the
4720 * host bridge generating requests larger than we can
4723 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4724 int mps = pcie_get_mps(dev);
4730 v = (ffs(rq) - 8) << 12;
4732 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4733 PCI_EXP_DEVCTL_READRQ, v);
4735 EXPORT_SYMBOL(pcie_set_readrq);
4738 * pcie_get_mps - get PCI Express maximum payload size
4739 * @dev: PCI device to query
4741 * Returns maximum payload size in bytes
4743 int pcie_get_mps(struct pci_dev *dev)
4747 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4749 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4751 EXPORT_SYMBOL(pcie_get_mps);
4754 * pcie_set_mps - set PCI Express maximum payload size
4755 * @dev: PCI device to query
4756 * @mps: maximum payload size in bytes
4757 * valid values are 128, 256, 512, 1024, 2048, 4096
4759 * If possible sets maximum payload size
4761 int pcie_set_mps(struct pci_dev *dev, int mps)
4765 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4769 if (v > dev->pcie_mpss)
4773 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4774 PCI_EXP_DEVCTL_PAYLOAD, v);
4776 EXPORT_SYMBOL(pcie_set_mps);
4779 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4780 * @dev: PCI device to query
4781 * @speed: storage for minimum speed
4782 * @width: storage for minimum width
4784 * This function will walk up the PCI device chain and determine the minimum
4785 * link width and speed of the device.
4787 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4788 enum pcie_link_width *width)
4792 *speed = PCI_SPEED_UNKNOWN;
4793 *width = PCIE_LNK_WIDTH_UNKNOWN;
4797 enum pci_bus_speed next_speed;
4798 enum pcie_link_width next_width;
4800 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4804 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4805 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4806 PCI_EXP_LNKSTA_NLW_SHIFT;
4808 if (next_speed < *speed)
4809 *speed = next_speed;
4811 if (next_width < *width)
4812 *width = next_width;
4814 dev = dev->bus->self;
4819 EXPORT_SYMBOL(pcie_get_minimum_link);
4822 * pci_select_bars - Make BAR mask from the type of resource
4823 * @dev: the PCI device for which BAR mask is made
4824 * @flags: resource type mask to be selected
4826 * This helper routine makes bar mask from the type of resource.
4828 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4831 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4832 if (pci_resource_flags(dev, i) & flags)
4836 EXPORT_SYMBOL(pci_select_bars);
4839 * pci_resource_bar - get position of the BAR associated with a resource
4840 * @dev: the PCI device
4841 * @resno: the resource number
4842 * @type: the BAR type to be filled in
4844 * Returns BAR position in config space, or 0 if the BAR is invalid.
4846 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4850 if (resno < PCI_ROM_RESOURCE) {
4851 *type = pci_bar_unknown;
4852 return PCI_BASE_ADDRESS_0 + 4 * resno;
4853 } else if (resno == PCI_ROM_RESOURCE) {
4854 *type = pci_bar_mem32;
4855 return dev->rom_base_reg;
4856 } else if (resno < PCI_BRIDGE_RESOURCES) {
4857 /* device specific resource */
4858 *type = pci_bar_unknown;
4859 reg = pci_iov_resource_bar(dev, resno);
4864 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4868 /* Some architectures require additional programming to enable VGA */
4869 static arch_set_vga_state_t arch_set_vga_state;
4871 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4873 arch_set_vga_state = func; /* NULL disables */
4876 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4877 unsigned int command_bits, u32 flags)
4879 if (arch_set_vga_state)
4880 return arch_set_vga_state(dev, decode, command_bits,
4886 * pci_set_vga_state - set VGA decode state on device and parents if requested
4887 * @dev: the PCI device
4888 * @decode: true = enable decoding, false = disable decoding
4889 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4890 * @flags: traverse ancestors and change bridges
4891 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4893 int pci_set_vga_state(struct pci_dev *dev, bool decode,
4894 unsigned int command_bits, u32 flags)
4896 struct pci_bus *bus;
4897 struct pci_dev *bridge;
4901 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4903 /* ARCH specific VGA enables */
4904 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4908 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4909 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4911 cmd |= command_bits;
4913 cmd &= ~command_bits;
4914 pci_write_config_word(dev, PCI_COMMAND, cmd);
4917 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4924 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4927 cmd |= PCI_BRIDGE_CTL_VGA;
4929 cmd &= ~PCI_BRIDGE_CTL_VGA;
4930 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4939 * pci_add_dma_alias - Add a DMA devfn alias for a device
4940 * @dev: the PCI device for which alias is added
4941 * @devfn: alias slot and function
4943 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
4944 * It should be called early, preferably as PCI fixup header quirk.
4946 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
4948 if (!dev->dma_alias_mask)
4949 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
4950 sizeof(long), GFP_KERNEL);
4951 if (!dev->dma_alias_mask) {
4952 dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n");
4956 set_bit(devfn, dev->dma_alias_mask);
4957 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
4958 PCI_SLOT(devfn), PCI_FUNC(devfn));
4961 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
4963 return (dev1->dma_alias_mask &&
4964 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
4965 (dev2->dma_alias_mask &&
4966 test_bit(dev1->devfn, dev2->dma_alias_mask));
4969 bool pci_device_is_present(struct pci_dev *pdev)
4973 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4975 EXPORT_SYMBOL_GPL(pci_device_is_present);
4977 void pci_ignore_hotplug(struct pci_dev *dev)
4979 struct pci_dev *bridge = dev->bus->self;
4981 dev->ignore_hotplug = 1;
4982 /* Propagate the "ignore hotplug" setting to the parent bridge. */
4984 bridge->ignore_hotplug = 1;
4986 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
4988 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4989 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4990 static DEFINE_SPINLOCK(resource_alignment_lock);
4993 * pci_specified_resource_alignment - get resource alignment specified by user.
4994 * @dev: the PCI device to get
4996 * RETURNS: Resource alignment if it is specified.
4997 * Zero if it is not specified.
4999 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
5001 int seg, bus, slot, func, align_order, count;
5002 unsigned short vendor, device, subsystem_vendor, subsystem_device;
5003 resource_size_t align = 0;
5006 spin_lock(&resource_alignment_lock);
5007 p = resource_alignment_param;
5010 if (pci_has_flag(PCI_PROBE_ONLY)) {
5011 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
5017 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
5023 if (strncmp(p, "pci:", 4) == 0) {
5024 /* PCI vendor/device (subvendor/subdevice) ids are specified */
5026 if (sscanf(p, "%hx:%hx:%hx:%hx%n",
5027 &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) {
5028 if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) {
5029 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n",
5033 subsystem_vendor = subsystem_device = 0;
5036 if ((!vendor || (vendor == dev->vendor)) &&
5037 (!device || (device == dev->device)) &&
5038 (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) &&
5039 (!subsystem_device || (subsystem_device == dev->subsystem_device))) {
5040 if (align_order == -1)
5043 align = 1 << align_order;
5049 if (sscanf(p, "%x:%x:%x.%x%n",
5050 &seg, &bus, &slot, &func, &count) != 4) {
5052 if (sscanf(p, "%x:%x.%x%n",
5053 &bus, &slot, &func, &count) != 3) {
5054 /* Invalid format */
5055 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
5061 if (seg == pci_domain_nr(dev->bus) &&
5062 bus == dev->bus->number &&
5063 slot == PCI_SLOT(dev->devfn) &&
5064 func == PCI_FUNC(dev->devfn)) {
5065 if (align_order == -1)
5068 align = 1 << align_order;
5073 if (*p != ';' && *p != ',') {
5074 /* End of param or invalid format */
5080 spin_unlock(&resource_alignment_lock);
5085 * This function disables memory decoding and releases memory resources
5086 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5087 * It also rounds up size to specified alignment.
5088 * Later on, the kernel will assign page-aligned memory resource back
5091 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5095 resource_size_t align, size;
5099 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5100 * 3.4.1.11. Their resources are allocated from the space
5101 * described by the VF BARx register in the PF's SR-IOV capability.
5102 * We can't influence their alignment here.
5107 /* check if specified PCI is target device to reassign */
5108 align = pci_specified_resource_alignment(dev);
5112 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5113 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5115 "Can't reassign resources to host bridge.\n");
5120 "Disabling memory decoding and releasing memory resources.\n");
5121 pci_read_config_word(dev, PCI_COMMAND, &command);
5122 command &= ~PCI_COMMAND_MEMORY;
5123 pci_write_config_word(dev, PCI_COMMAND, command);
5125 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
5126 r = &dev->resource[i];
5127 if (!(r->flags & IORESOURCE_MEM))
5129 if (r->flags & IORESOURCE_PCI_FIXED) {
5130 dev_info(&dev->dev, "Ignoring requested alignment for BAR%d: %pR\n",
5135 size = resource_size(r);
5139 "Rounding up size of resource #%d to %#llx.\n",
5140 i, (unsigned long long)size);
5142 r->flags |= IORESOURCE_UNSET;
5146 /* Need to disable bridge's resource window,
5147 * to enable the kernel to reassign new resource
5150 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5151 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5152 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5153 r = &dev->resource[i];
5154 if (!(r->flags & IORESOURCE_MEM))
5156 r->flags |= IORESOURCE_UNSET;
5157 r->end = resource_size(r) - 1;
5160 pci_disable_bridge_window(dev);
5164 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
5166 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5167 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5168 spin_lock(&resource_alignment_lock);
5169 strncpy(resource_alignment_param, buf, count);
5170 resource_alignment_param[count] = '\0';
5171 spin_unlock(&resource_alignment_lock);
5175 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
5178 spin_lock(&resource_alignment_lock);
5179 count = snprintf(buf, size, "%s", resource_alignment_param);
5180 spin_unlock(&resource_alignment_lock);
5184 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5186 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5189 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5190 const char *buf, size_t count)
5192 return pci_set_resource_alignment_param(buf, count);
5195 static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
5196 pci_resource_alignment_store);
5198 static int __init pci_resource_alignment_sysfs_init(void)
5200 return bus_create_file(&pci_bus_type,
5201 &bus_attr_resource_alignment);
5203 late_initcall(pci_resource_alignment_sysfs_init);
5205 static void pci_no_domains(void)
5207 #ifdef CONFIG_PCI_DOMAINS
5208 pci_domains_supported = 0;
5212 #ifdef CONFIG_PCI_DOMAINS
5213 static atomic_t __domain_nr = ATOMIC_INIT(-1);
5215 int pci_get_new_domain_nr(void)
5217 return atomic_inc_return(&__domain_nr);
5220 #ifdef CONFIG_PCI_DOMAINS_GENERIC
5221 static int of_pci_bus_find_domain_nr(struct device *parent)
5223 static int use_dt_domains = -1;
5227 domain = of_get_pci_domain_nr(parent->of_node);
5229 * Check DT domain and use_dt_domains values.
5231 * If DT domain property is valid (domain >= 0) and
5232 * use_dt_domains != 0, the DT assignment is valid since this means
5233 * we have not previously allocated a domain number by using
5234 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5235 * 1, to indicate that we have just assigned a domain number from
5238 * If DT domain property value is not valid (ie domain < 0), and we
5239 * have not previously assigned a domain number from DT
5240 * (use_dt_domains != 1) we should assign a domain number by
5243 * pci_get_new_domain_nr()
5245 * API and update the use_dt_domains value to keep track of method we
5246 * are using to assign domain numbers (use_dt_domains = 0).
5248 * All other combinations imply we have a platform that is trying
5249 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5250 * which is a recipe for domain mishandling and it is prevented by
5251 * invalidating the domain value (domain = -1) and printing a
5252 * corresponding error.
5254 if (domain >= 0 && use_dt_domains) {
5256 } else if (domain < 0 && use_dt_domains != 1) {
5258 domain = pci_get_new_domain_nr();
5260 dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
5261 parent->of_node->full_name);
5268 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
5270 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
5271 acpi_pci_bus_find_domain_nr(bus);
5277 * pci_ext_cfg_avail - can we access extended PCI config space?
5279 * Returns 1 if we can access PCI extended config space (offsets
5280 * greater than 0xff). This is the default implementation. Architecture
5281 * implementations can override this.
5283 int __weak pci_ext_cfg_avail(void)
5288 void __weak pci_fixup_cardbus(struct pci_bus *bus)
5291 EXPORT_SYMBOL(pci_fixup_cardbus);
5293 static int __init pci_setup(char *str)
5296 char *k = strchr(str, ',');
5299 if (*str && (str = pcibios_setup(str)) && *str) {
5300 if (!strcmp(str, "nomsi")) {
5302 } else if (!strcmp(str, "noaer")) {
5304 } else if (!strncmp(str, "realloc=", 8)) {
5305 pci_realloc_get_opt(str + 8);
5306 } else if (!strncmp(str, "realloc", 7)) {
5307 pci_realloc_get_opt("on");
5308 } else if (!strcmp(str, "nodomains")) {
5310 } else if (!strncmp(str, "noari", 5)) {
5311 pcie_ari_disabled = true;
5312 } else if (!strncmp(str, "cbiosize=", 9)) {
5313 pci_cardbus_io_size = memparse(str + 9, &str);
5314 } else if (!strncmp(str, "cbmemsize=", 10)) {
5315 pci_cardbus_mem_size = memparse(str + 10, &str);
5316 } else if (!strncmp(str, "resource_alignment=", 19)) {
5317 pci_set_resource_alignment_param(str + 19,
5319 } else if (!strncmp(str, "ecrc=", 5)) {
5320 pcie_ecrc_get_policy(str + 5);
5321 } else if (!strncmp(str, "hpiosize=", 9)) {
5322 pci_hotplug_io_size = memparse(str + 9, &str);
5323 } else if (!strncmp(str, "hpmemsize=", 10)) {
5324 pci_hotplug_mem_size = memparse(str + 10, &str);
5325 } else if (!strncmp(str, "hpbussize=", 10)) {
5326 pci_hotplug_bus_size =
5327 simple_strtoul(str + 10, &str, 0);
5328 if (pci_hotplug_bus_size > 0xff)
5329 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
5330 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5331 pcie_bus_config = PCIE_BUS_TUNE_OFF;
5332 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5333 pcie_bus_config = PCIE_BUS_SAFE;
5334 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5335 pcie_bus_config = PCIE_BUS_PERFORMANCE;
5336 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5337 pcie_bus_config = PCIE_BUS_PEER2PEER;
5338 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5339 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
5341 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5349 early_param("pci", pci_setup);