2 * Marvell 37xx SoC pinctrl driver
4 * Copyright (C) 2017 Marvell
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
13 #include <linux/gpio/driver.h>
14 #include <linux/mfd/syscon.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/of_irq.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
27 #include "../pinctrl-utils.h"
30 #define INPUT_VAL 0x10
31 #define OUTPUT_VAL 0x18
32 #define OUTPUT_CTL 0x20
33 #define SELECTION 0x30
37 #define IRQ_STATUS 0x10
41 #define GPIO_PER_REG 32
44 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
45 * The pins of a pinmux groups are composed of one or two groups of contiguous
47 * @name: Name of the pin group, used to lookup the group.
48 * @start_pins: Index of the first pin of the main range of pins belonging to
50 * @npins: Number of pins included in the first range
51 * @reg_mask: Bit mask matching the group in the selection register
52 * @extra_pins: Index of the first pin of the optional second range of pins
53 * belonging to the group
54 * @npins: Number of pins included in the second optional range
55 * @funcs: A list of pinmux functions that can be selected for this group.
56 * @pins: List of the pins included in the group
58 struct armada_37xx_pin_group {
60 unsigned int start_pin;
64 unsigned int extra_pin;
65 unsigned int extra_npins;
66 const char *funcs[NB_FUNCS];
70 struct armada_37xx_pin_data {
73 struct armada_37xx_pin_group *groups;
77 struct armada_37xx_pmx_func {
83 struct armada_37xx_pinctrl {
84 struct regmap *regmap;
86 const struct armada_37xx_pin_data *data;
88 struct gpio_chip gpio_chip;
89 struct irq_chip irq_chip;
91 struct pinctrl_desc pctl;
92 struct pinctrl_dev *pctl_dev;
93 struct armada_37xx_pin_group *groups;
95 struct armada_37xx_pmx_func *funcs;
99 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
102 .start_pin = _start, \
106 .funcs = {_func1, _func2} \
109 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
112 .start_pin = _start, \
116 .funcs = {_func1, "gpio"} \
119 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
122 .start_pin = _start, \
125 .val = {_val1, _val2}, \
126 .funcs = {_func1, "gpio"} \
129 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
133 .start_pin = _start, \
137 .extra_pin = _start2, \
138 .extra_npins = _nr2, \
139 .funcs = {_f1, _f2} \
142 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
143 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
144 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
145 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
146 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
147 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
148 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
149 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
150 PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"),
151 PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"),
152 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
153 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
154 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
155 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
156 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
157 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
158 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
159 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
160 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
161 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
162 18, 2, "gpio", "uart"),
163 PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"),
164 PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"),
165 PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"),
166 PIN_GRP_GPIO("led3_od", 14, 1, BIT(23), "led"),
170 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
171 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
172 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
173 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
174 PIN_GRP_EXTRA("rgmii", 6, 12, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"),
175 PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
176 PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
177 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
178 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
179 PIN_GRP("mii_col", 23, 1, BIT(8), "mii", "mii_err"),
182 const struct armada_37xx_pin_data armada_37xx_pin_nb = {
185 .groups = armada_37xx_nb_groups,
186 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
189 const struct armada_37xx_pin_data armada_37xx_pin_sb = {
192 .groups = armada_37xx_sb_groups,
193 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
196 static inline void armada_37xx_update_reg(unsigned int *reg,
199 /* We never have more than 2 registers */
200 if (offset >= GPIO_PER_REG) {
201 offset -= GPIO_PER_REG;
206 static int armada_37xx_get_func_reg(struct armada_37xx_pin_group *grp,
211 for (f = 0; f < NB_FUNCS; f++)
212 if (!strcmp(grp->funcs[f], func))
218 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
219 struct armada_37xx_pinctrl *info, int pin, int *grp)
221 while (*grp < info->ngroups) {
222 struct armada_37xx_pin_group *group = &info->groups[*grp];
226 for (j = 0; j < (group->npins + group->extra_npins); j++)
227 if (group->pins[j] == pin)
233 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
234 unsigned int selector, unsigned long *config)
239 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
240 unsigned int selector, unsigned long *configs,
241 unsigned int num_configs)
246 static struct pinconf_ops armada_37xx_pinconf_ops = {
248 .pin_config_group_get = armada_37xx_pin_config_group_get,
249 .pin_config_group_set = armada_37xx_pin_config_group_set,
252 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
254 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
256 return info->ngroups;
259 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
262 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
264 return info->groups[group].name;
267 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
268 unsigned int selector,
269 const unsigned int **pins,
272 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
274 if (selector >= info->ngroups)
277 *pins = info->groups[selector].pins;
278 *npins = info->groups[selector].npins +
279 info->groups[selector].extra_npins;
284 static const struct pinctrl_ops armada_37xx_pctrl_ops = {
285 .get_groups_count = armada_37xx_get_groups_count,
286 .get_group_name = armada_37xx_get_group_name,
287 .get_group_pins = armada_37xx_get_group_pins,
288 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
289 .dt_free_map = pinctrl_utils_free_map,
293 * Pinmux_ops handling
296 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
298 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
303 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
304 unsigned int selector)
306 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
308 return info->funcs[selector].name;
311 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
312 unsigned int selector,
313 const char * const **groups,
314 unsigned int * const num_groups)
316 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
318 *groups = info->funcs[selector].groups;
319 *num_groups = info->funcs[selector].ngroups;
324 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
326 struct armada_37xx_pin_group *grp)
328 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
329 unsigned int reg = SELECTION;
330 unsigned int mask = grp->reg_mask;
333 dev_dbg(info->dev, "enable function %s group %s\n",
336 func = armada_37xx_get_func_reg(grp, name);
341 val = grp->val[func];
343 regmap_update_bits(info->regmap, reg, mask, val);
348 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
349 unsigned int selector,
353 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
354 struct armada_37xx_pin_group *grp = &info->groups[group];
355 const char *name = info->funcs[selector].name;
357 return armada_37xx_pmx_set_by_name(pctldev, name, grp);
360 static inline void armada_37xx_irq_update_reg(unsigned int *reg,
363 int offset = irqd_to_hwirq(d);
365 armada_37xx_update_reg(reg, offset);
368 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
371 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
372 unsigned int reg = OUTPUT_EN;
375 armada_37xx_update_reg(®, offset);
378 return regmap_update_bits(info->regmap, reg, mask, 0);
381 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
384 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
385 unsigned int reg = OUTPUT_EN;
386 unsigned int val, mask;
388 armada_37xx_update_reg(®, offset);
390 regmap_read(info->regmap, reg, &val);
392 return !(val & mask);
395 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
396 unsigned int offset, int value)
398 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
399 unsigned int reg = OUTPUT_EN;
402 armada_37xx_update_reg(®, offset);
405 return regmap_update_bits(info->regmap, reg, mask, mask);
408 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
410 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
411 unsigned int reg = INPUT_VAL;
412 unsigned int val, mask;
414 armada_37xx_update_reg(®, offset);
417 regmap_read(info->regmap, reg, &val);
419 return (val & mask) != 0;
422 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
425 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
426 unsigned int reg = OUTPUT_VAL;
427 unsigned int mask, val;
429 armada_37xx_update_reg(®, offset);
431 val = value ? mask : 0;
433 regmap_update_bits(info->regmap, reg, mask, val);
436 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
437 struct pinctrl_gpio_range *range,
438 unsigned int offset, bool input)
440 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
441 struct gpio_chip *chip = range->gc;
443 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
444 offset, range->name, offset, input ? "input" : "output");
447 armada_37xx_gpio_direction_input(chip, offset);
449 armada_37xx_gpio_direction_output(chip, offset, 0);
454 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
455 struct pinctrl_gpio_range *range,
458 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
459 struct armada_37xx_pin_group *group;
462 dev_dbg(info->dev, "requesting gpio %d\n", offset);
464 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
465 armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
470 static const struct pinmux_ops armada_37xx_pmx_ops = {
471 .get_functions_count = armada_37xx_pmx_get_funcs_count,
472 .get_function_name = armada_37xx_pmx_get_func_name,
473 .get_function_groups = armada_37xx_pmx_get_groups,
474 .set_mux = armada_37xx_pmx_set,
475 .gpio_request_enable = armada_37xx_gpio_request_enable,
476 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
479 static const struct gpio_chip armada_37xx_gpiolib_chip = {
480 .request = gpiochip_generic_request,
481 .free = gpiochip_generic_free,
482 .set = armada_37xx_gpio_set,
483 .get = armada_37xx_gpio_get,
484 .get_direction = armada_37xx_gpio_get_direction,
485 .direction_input = armada_37xx_gpio_direction_input,
486 .direction_output = armada_37xx_gpio_direction_output,
487 .owner = THIS_MODULE,
490 static void armada_37xx_irq_ack(struct irq_data *d)
492 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
493 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
494 u32 reg = IRQ_STATUS;
497 armada_37xx_irq_update_reg(®, d);
498 spin_lock_irqsave(&info->irq_lock, flags);
499 writel(d->mask, info->base + reg);
500 spin_unlock_irqrestore(&info->irq_lock, flags);
503 static void armada_37xx_irq_mask(struct irq_data *d)
505 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
506 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
507 u32 val, reg = IRQ_EN;
510 armada_37xx_irq_update_reg(®, d);
511 spin_lock_irqsave(&info->irq_lock, flags);
512 val = readl(info->base + reg);
513 writel(val & ~d->mask, info->base + reg);
514 spin_unlock_irqrestore(&info->irq_lock, flags);
517 static void armada_37xx_irq_unmask(struct irq_data *d)
519 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
520 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
521 u32 val, reg = IRQ_EN;
524 armada_37xx_irq_update_reg(®, d);
525 spin_lock_irqsave(&info->irq_lock, flags);
526 val = readl(info->base + reg);
527 writel(val | d->mask, info->base + reg);
528 spin_unlock_irqrestore(&info->irq_lock, flags);
531 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
533 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
534 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
535 u32 val, reg = IRQ_WKUP;
538 armada_37xx_irq_update_reg(®, d);
539 spin_lock_irqsave(&info->irq_lock, flags);
540 val = readl(info->base + reg);
545 writel(val, info->base + reg);
546 spin_unlock_irqrestore(&info->irq_lock, flags);
551 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
553 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
554 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
555 u32 val, reg = IRQ_POL;
558 spin_lock_irqsave(&info->irq_lock, flags);
559 armada_37xx_irq_update_reg(®, d);
560 val = readl(info->base + reg);
562 case IRQ_TYPE_EDGE_RISING:
565 case IRQ_TYPE_EDGE_FALLING:
569 spin_unlock_irqrestore(&info->irq_lock, flags);
572 writel(val, info->base + reg);
573 spin_unlock_irqrestore(&info->irq_lock, flags);
579 static void armada_37xx_irq_handler(struct irq_desc *desc)
581 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
582 struct irq_chip *chip = irq_desc_get_chip(desc);
583 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
584 struct irq_domain *d = gc->irqdomain;
587 chained_irq_enter(chip, desc);
588 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
592 spin_lock_irqsave(&info->irq_lock, flags);
593 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
594 /* Manage only the interrupt that was enabled */
595 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
596 spin_unlock_irqrestore(&info->irq_lock, flags);
598 u32 hwirq = ffs(status) - 1;
599 u32 virq = irq_find_mapping(d, hwirq +
602 generic_handle_irq(virq);
604 /* Update status in case a new IRQ appears */
605 spin_lock_irqsave(&info->irq_lock, flags);
606 status = readl_relaxed(info->base +
608 /* Manage only the interrupt that was enabled */
609 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
610 spin_unlock_irqrestore(&info->irq_lock, flags);
613 chained_irq_exit(chip, desc);
616 static int armada_37xx_irqchip_register(struct platform_device *pdev,
617 struct armada_37xx_pinctrl *info)
619 struct device_node *np = info->dev->of_node;
620 int nrirqs = info->data->nr_pins;
621 struct gpio_chip *gc = &info->gpio_chip;
622 struct irq_chip *irqchip = &info->irq_chip;
624 int ret = -ENODEV, i, nr_irq_parent;
626 /* Check if we have at least one gpio-controller child node */
627 for_each_child_of_node(info->dev->of_node, np) {
628 if (of_property_read_bool(np, "gpio-controller")) {
636 nr_irq_parent = of_irq_count(np);
637 spin_lock_init(&info->irq_lock);
639 if (!nr_irq_parent) {
640 dev_err(&pdev->dev, "Invalid or no IRQ\n");
644 if (of_address_to_resource(info->dev->of_node, 1, &res)) {
645 dev_err(info->dev, "cannot find IO resource\n");
649 info->base = devm_ioremap_resource(info->dev, &res);
650 if (IS_ERR(info->base))
651 return PTR_ERR(info->base);
653 irqchip->irq_ack = armada_37xx_irq_ack;
654 irqchip->irq_mask = armada_37xx_irq_mask;
655 irqchip->irq_unmask = armada_37xx_irq_unmask;
656 irqchip->irq_set_wake = armada_37xx_irq_set_wake;
657 irqchip->irq_set_type = armada_37xx_irq_set_type;
658 irqchip->name = info->data->name;
660 ret = gpiochip_irqchip_add(gc, irqchip, 0,
661 handle_edge_irq, IRQ_TYPE_NONE);
663 dev_info(&pdev->dev, "could not add irqchip\n");
668 * Many interrupts are connected to the parent interrupt
669 * controller. But we do not take advantage of this and use
670 * the chained irq with all of them.
672 for (i = 0; i < nrirqs; i++) {
673 struct irq_data *d = irq_get_irq_data(gc->irq_base + i);
676 * The mask field is a "precomputed bitmask for
677 * accessing the chip registers" which was introduced
678 * for the generic irqchip framework. As we don't use
679 * this framework, we can reuse this field for our own
682 d->mask = BIT(i % GPIO_PER_REG);
685 for (i = 0; i < nr_irq_parent; i++) {
686 int irq = irq_of_parse_and_map(np, i);
691 gpiochip_set_chained_irqchip(gc, irqchip, irq,
692 armada_37xx_irq_handler);
698 static int armada_37xx_gpiochip_register(struct platform_device *pdev,
699 struct armada_37xx_pinctrl *info)
701 struct device_node *np;
702 struct gpio_chip *gc;
705 for_each_child_of_node(info->dev->of_node, np) {
706 if (of_find_property(np, "gpio-controller", NULL)) {
714 info->gpio_chip = armada_37xx_gpiolib_chip;
716 gc = &info->gpio_chip;
717 gc->ngpio = info->data->nr_pins;
718 gc->parent = &pdev->dev;
721 gc->label = info->data->name;
723 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
726 ret = armada_37xx_irqchip_register(pdev, info);
734 * armada_37xx_add_function() - Add a new function to the list
735 * @funcs: array of function to add the new one
736 * @funcsize: size of the remaining space for the function
737 * @name: name of the function to add
739 * If it is a new function then create it by adding its name else
740 * increment the number of group associated to this function.
742 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
743 int *funcsize, const char *name)
750 while (funcs->ngroups) {
751 /* function already there */
752 if (strcmp(funcs->name, name) == 0) {
761 /* append new unique function */
770 * armada_37xx_fill_group() - complete the group array
771 * @info: info driver instance
773 * Based on the data available from the armada_37xx_pin_group array
774 * completes the last member of the struct for each function: the list
775 * of the groups associated to this function.
778 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
780 int n, num = 0, funcsize = info->data->nr_pins;
782 for (n = 0; n < info->ngroups; n++) {
783 struct armada_37xx_pin_group *grp = &info->groups[n];
786 grp->pins = devm_kzalloc(info->dev,
787 (grp->npins + grp->extra_npins) *
788 sizeof(*grp->pins), GFP_KERNEL);
792 for (i = 0; i < grp->npins; i++)
793 grp->pins[i] = grp->start_pin + i;
795 for (j = 0; j < grp->extra_npins; j++)
796 grp->pins[i+j] = grp->extra_pin + j;
798 for (f = 0; f < NB_FUNCS; f++) {
800 /* check for unique functions and count groups */
801 ret = armada_37xx_add_function(info->funcs, &funcsize,
803 if (ret == -EOVERFLOW)
805 "More functions than pins(%d)\n",
806 info->data->nr_pins);
819 * armada_37xx_fill_funcs() - complete the funcs array
820 * @info: info driver instance
822 * Based on the data available from the armada_37xx_pin_group array
823 * completes the last two member of the struct for each group:
824 * - the list of the pins included in the group
825 * - the list of pinmux functions that can be selected for this group
828 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
830 struct armada_37xx_pmx_func *funcs = info->funcs;
833 for (n = 0; n < info->nfuncs; n++) {
834 const char *name = funcs[n].name;
838 funcs[n].groups = devm_kzalloc(info->dev, funcs[n].ngroups *
839 sizeof(*(funcs[n].groups)),
841 if (!funcs[n].groups)
844 groups = funcs[n].groups;
846 for (g = 0; g < info->ngroups; g++) {
847 struct armada_37xx_pin_group *gp = &info->groups[g];
850 for (f = 0; f < NB_FUNCS; f++) {
851 if (strcmp(gp->funcs[f], name) == 0) {
861 static int armada_37xx_pinctrl_register(struct platform_device *pdev,
862 struct armada_37xx_pinctrl *info)
864 const struct armada_37xx_pin_data *pin_data = info->data;
865 struct pinctrl_desc *ctrldesc = &info->pctl;
866 struct pinctrl_pin_desc *pindesc, *pdesc;
869 info->groups = pin_data->groups;
870 info->ngroups = pin_data->ngroups;
872 ctrldesc->name = "armada_37xx-pinctrl";
873 ctrldesc->owner = THIS_MODULE;
874 ctrldesc->pctlops = &armada_37xx_pctrl_ops;
875 ctrldesc->pmxops = &armada_37xx_pmx_ops;
876 ctrldesc->confops = &armada_37xx_pinconf_ops;
878 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
879 pin_data->nr_pins, GFP_KERNEL);
883 ctrldesc->pins = pindesc;
884 ctrldesc->npins = pin_data->nr_pins;
887 for (pin = 0; pin < pin_data->nr_pins; pin++) {
889 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
890 pin_data->name, pin);
895 * we allocate functions for number of pins and hope there are
896 * fewer unique functions than pins available
898 info->funcs = devm_kzalloc(&pdev->dev, pin_data->nr_pins *
899 sizeof(struct armada_37xx_pmx_func), GFP_KERNEL);
904 ret = armada_37xx_fill_group(info);
908 ret = armada_37xx_fill_func(info);
912 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
913 if (IS_ERR(info->pctl_dev)) {
914 dev_err(&pdev->dev, "could not register pinctrl driver\n");
915 return PTR_ERR(info->pctl_dev);
921 static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
923 .compatible = "marvell,armada3710-sb-pinctrl",
924 .data = (void *)&armada_37xx_pin_sb,
927 .compatible = "marvell,armada3710-nb-pinctrl",
928 .data = (void *)&armada_37xx_pin_nb,
933 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
935 struct armada_37xx_pinctrl *info;
936 struct device *dev = &pdev->dev;
937 struct device_node *np = dev->of_node;
938 struct regmap *regmap;
941 info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
948 regmap = syscon_node_to_regmap(np);
949 if (IS_ERR(regmap)) {
950 dev_err(&pdev->dev, "cannot get regmap\n");
951 return PTR_ERR(regmap);
953 info->regmap = regmap;
955 info->data = of_device_get_match_data(dev);
957 ret = armada_37xx_pinctrl_register(pdev, info);
961 ret = armada_37xx_gpiochip_register(pdev, info);
965 platform_set_drvdata(pdev, info);
970 static struct platform_driver armada_37xx_pinctrl_driver = {
972 .name = "armada-37xx-pinctrl",
973 .of_match_table = armada_37xx_pinctrl_of_match,
977 builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
978 armada_37xx_pinctrl_probe);