drivers/pinctrl/pinctrl-single.c

   1 /*
   2  * Generic device tree based pinctrl driver for one register per pin
   3  * type pinmux controllers
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/list.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <linux/irqchip/chained_irq.h>
  21
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30
  31 #include <linux/platform_data/pinctrl-single.h>
  32
  33 #include "core.h"
  34 #include "pinconf.h"
  35
  36 #define DRIVER_NAME                     "pinctrl-single"
  37 #define PCS_MUX_PINS_NAME               "pinctrl-single,pins"
  38 #define PCS_MUX_BITS_NAME               "pinctrl-single,bits"
  39 #define PCS_REG_NAME_LEN                ((sizeof(unsigned long) * 2) + 3)
  40 #define PCS_OFF_DISABLED                ~0U
  41
  42 /**
  43  * struct pcs_pingroup - pingroups for a function
  44  * @np:         pingroup device node pointer
  45  * @name:       pingroup name
  46  * @gpins:      array of the pins in the group
  47  * @ngpins:     number of pins in the group
  48  * @node:       list node
  49  */
  50 struct pcs_pingroup {
  51         struct device_node *np;
  52         const char *name;
  53         int *gpins;
  54         int ngpins;
  55         struct list_head node;
  56 };
  57
  58 /**
  59  * struct pcs_func_vals - mux function register offset and value pair
  60  * @reg:        register virtual address
  61  * @val:        register value
  62  */
  63 struct pcs_func_vals {
  64         void __iomem *reg;
  65         unsigned val;
  66         unsigned mask;
  67 };
  68
  69 /**
  70  * struct pcs_conf_vals - pinconf parameter, pinconf register offset
  71  * and value, enable, disable, mask
  72  * @param:      config parameter
  73  * @val:        user input bits in the pinconf register
  74  * @enable:     enable bits in the pinconf register
  75  * @disable:    disable bits in the pinconf register
  76  * @mask:       mask bits in the register value
  77  */
  78 struct pcs_conf_vals {
  79         enum pin_config_param param;
  80         unsigned val;
  81         unsigned enable;
  82         unsigned disable;
  83         unsigned mask;
  84 };
  85
  86 /**
  87  * struct pcs_conf_type - pinconf property name, pinconf param pair
  88  * @name:       property name in DTS file
  89  * @param:      config parameter
  90  */
  91 struct pcs_conf_type {
  92         const char *name;
  93         enum pin_config_param param;
  94 };
  95
  96 /**
  97  * struct pcs_function - pinctrl function
  98  * @name:       pinctrl function name
  99  * @vals:       register and vals array
 100  * @nvals:      number of entries in vals array
 101  * @pgnames:    array of pingroup names the function uses
 102  * @npgnames:   number of pingroup names the function uses
 103  * @node:       list node
 104  */
 105 struct pcs_function {
 106         const char *name;
 107         struct pcs_func_vals *vals;
 108         unsigned nvals;
 109         const char **pgnames;
 110         int npgnames;
 111         struct pcs_conf_vals *conf;
 112         int nconfs;
 113         struct list_head node;
 114 };
 115
 116 /**
 117  * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
 118  * @offset:     offset base of pins
 119  * @npins:      number pins with the same mux value of gpio function
 120  * @gpiofunc:   mux value of gpio function
 121  * @node:       list node
 122  */
 123 struct pcs_gpiofunc_range {
 124         unsigned offset;
 125         unsigned npins;
 126         unsigned gpiofunc;
 127         struct list_head node;
 128 };
 129
 130 /**
 131  * struct pcs_data - wrapper for data needed by pinctrl framework
 132  * @pa:         pindesc array
 133  * @cur:        index to current element
 134  *
 135  * REVISIT: We should be able to drop this eventually by adding
 136  * support for registering pins individually in the pinctrl
 137  * framework for those drivers that don't need a static array.
 138  */
 139 struct pcs_data {
 140         struct pinctrl_pin_desc *pa;
 141         int cur;
 142 };
 143
 144 /**
 145  * struct pcs_name - register name for a pin
 146  * @name:       name of the pinctrl register
 147  *
 148  * REVISIT: We may want to make names optional in the pinctrl
 149  * framework as some drivers may not care about pin names to
 150  * avoid kernel bloat. The pin names can be deciphered by user
 151  * space tools using debugfs based on the register address and
 152  * SoC packaging information.
 153  */
 154 struct pcs_name {
 155         char name[PCS_REG_NAME_LEN];
 156 };
 157
 158 /**
 159  * struct pcs_soc_data - SoC specific settings
 160  * @flags:      initial SoC specific PCS_FEAT_xxx values
 161  * @irq:        optional interrupt for the controller
 162  * @irq_enable_mask:    optional SoC specific interrupt enable mask
 163  * @irq_status_mask:    optional SoC specific interrupt status mask
 164  * @rearm:      optional SoC specific wake-up rearm function
 165  */
 166 struct pcs_soc_data {
 167         unsigned flags;
 168         int irq;
 169         unsigned irq_enable_mask;
 170         unsigned irq_status_mask;
 171         void (*rearm)(void);
 172 };
 173
 174 /**
 175  * struct pcs_device - pinctrl device instance
 176  * @res:        resources
 177  * @base:       virtual address of the controller
 178  * @size:       size of the ioremapped area
 179  * @dev:        device entry
 180  * @pctl:       pin controller device
 181  * @flags:      mask of PCS_FEAT_xxx values
 182  * @lock:       spinlock for register access
 183  * @mutex:      mutex protecting the lists
 184  * @width:      bits per mux register
 185  * @fmask:      function register mask
 186  * @fshift:     function register shift
 187  * @foff:       value to turn mux off
 188  * @fmax:       max number of functions in fmask
 189  * @bits_per_pin:number of bits per pin
 190  * @names:      array of register names for pins
 191  * @pins:       physical pins on the SoC
 192  * @pgtree:     pingroup index radix tree
 193  * @ftree:      function index radix tree
 194  * @pingroups:  list of pingroups
 195  * @functions:  list of functions
 196  * @gpiofuncs:  list of gpio functions
 197  * @irqs:       list of interrupt registers
 198  * @chip:       chip container for this instance
 199  * @domain:     IRQ domain for this instance
 200  * @ngroups:    number of pingroups
 201  * @nfuncs:     number of functions
 202  * @desc:       pin controller descriptor
 203  * @read:       register read function to use
 204  * @write:      register write function to use
 205  */
 206 struct pcs_device {
 207         struct resource *res;
 208         void __iomem *base;
 209         unsigned size;
 210         struct device *dev;
 211         struct pinctrl_dev *pctl;
 212         unsigned flags;
 213 #define PCS_QUIRK_SHARED_IRQ    (1 << 2)
 214 #define PCS_FEAT_IRQ            (1 << 1)
 215 #define PCS_FEAT_PINCONF        (1 << 0)
 216         struct pcs_soc_data socdata;
 217         raw_spinlock_t lock;
 218         struct mutex mutex;
 219         unsigned width;
 220         unsigned fmask;
 221         unsigned fshift;
 222         unsigned foff;
 223         unsigned fmax;
 224         bool bits_per_mux;
 225         unsigned bits_per_pin;
 226         struct pcs_name *names;
 227         struct pcs_data pins;
 228         struct radix_tree_root pgtree;
 229         struct radix_tree_root ftree;
 230         struct list_head pingroups;
 231         struct list_head functions;
 232         struct list_head gpiofuncs;
 233         struct list_head irqs;
 234         struct irq_chip chip;
 235         struct irq_domain *domain;
 236         unsigned ngroups;
 237         unsigned nfuncs;
 238         struct pinctrl_desc desc;
 239         unsigned (*read)(void __iomem *reg);
 240         void (*write)(unsigned val, void __iomem *reg);
 241 };
 242
 243 #define PCS_QUIRK_HAS_SHARED_IRQ        (pcs->flags & PCS_QUIRK_SHARED_IRQ)
 244 #define PCS_HAS_IRQ             (pcs->flags & PCS_FEAT_IRQ)
 245 #define PCS_HAS_PINCONF         (pcs->flags & PCS_FEAT_PINCONF)
 246
 247 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 248                            unsigned long *config);
 249 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 250                            unsigned long *configs, unsigned num_configs);
 251
 252 static enum pin_config_param pcs_bias[] = {
 253         PIN_CONFIG_BIAS_PULL_DOWN,
 254         PIN_CONFIG_BIAS_PULL_UP,
 255 };
 256
 257 /*
 258  * This lock class tells lockdep that irqchip core that this single
 259  * pinctrl can be in a different category than its parents, so it won't
 260  * report false recursion.
 261  */
 262 static struct lock_class_key pcs_lock_class;
 263
 264 /*
 265  * REVISIT: Reads and writes could eventually use regmap or something
 266  * generic. But at least on omaps, some mux registers are performance
 267  * critical as they may need to be remuxed every time before and after
 268  * idle. Adding tests for register access width for every read and
 269  * write like regmap is doing is not desired, and caching the registers
 270  * does not help in this case.
 271  */
 272
 273 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
 274 {
 275         return readb(reg);
 276 }
 277
 278 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
 279 {
 280         return readw(reg);
 281 }
 282
 283 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
 284 {
 285         return readl(reg);
 286 }
 287
 288 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
 289 {
 290         writeb(val, reg);
 291 }
 292
 293 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
 294 {
 295         writew(val, reg);
 296 }
 297
 298 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
 299 {
 300         writel(val, reg);
 301 }
 302
 303 static int pcs_get_groups_count(struct pinctrl_dev *pctldev)
 304 {
 305         struct pcs_device *pcs;
 306
 307         pcs = pinctrl_dev_get_drvdata(pctldev);
 308
 309         return pcs->ngroups;
 310 }
 311
 312 static const char *pcs_get_group_name(struct pinctrl_dev *pctldev,
 313                                         unsigned gselector)
 314 {
 315         struct pcs_device *pcs;
 316         struct pcs_pingroup *group;
 317
 318         pcs = pinctrl_dev_get_drvdata(pctldev);
 319         group = radix_tree_lookup(&pcs->pgtree, gselector);
 320         if (!group) {
 321                 dev_err(pcs->dev, "%s could not find pingroup%i\n",
 322                         __func__, gselector);
 323                 return NULL;
 324         }
 325
 326         return group->name;
 327 }
 328
 329 static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
 330                                         unsigned gselector,
 331                                         const unsigned **pins,
 332                                         unsigned *npins)
 333 {
 334         struct pcs_device *pcs;
 335         struct pcs_pingroup *group;
 336
 337         pcs = pinctrl_dev_get_drvdata(pctldev);
 338         group = radix_tree_lookup(&pcs->pgtree, gselector);
 339         if (!group) {
 340                 dev_err(pcs->dev, "%s could not find pingroup%i\n",
 341                         __func__, gselector);
 342                 return -EINVAL;
 343         }
 344
 345         *pins = group->gpins;
 346         *npins = group->ngpins;
 347
 348         return 0;
 349 }
 350
 351 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
 352                                         struct seq_file *s,
 353                                         unsigned pin)
 354 {
 355         struct pcs_device *pcs;
 356         unsigned val, mux_bytes;
 357
 358         pcs = pinctrl_dev_get_drvdata(pctldev);
 359
 360         mux_bytes = pcs->width / BITS_PER_BYTE;
 361         val = pcs->read(pcs->base + pin * mux_bytes);
 362
 363         seq_printf(s, "%08x %s " , val, DRIVER_NAME);
 364 }
 365
 366 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
 367                                 struct pinctrl_map *map, unsigned num_maps)
 368 {
 369         struct pcs_device *pcs;
 370
 371         pcs = pinctrl_dev_get_drvdata(pctldev);
 372         devm_kfree(pcs->dev, map);
 373 }
 374
 375 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 376                                 struct device_node *np_config,
 377                                 struct pinctrl_map **map, unsigned *num_maps);
 378
 379 static const struct pinctrl_ops pcs_pinctrl_ops = {
 380         .get_groups_count = pcs_get_groups_count,
 381         .get_group_name = pcs_get_group_name,
 382         .get_group_pins = pcs_get_group_pins,
 383         .pin_dbg_show = pcs_pin_dbg_show,
 384         .dt_node_to_map = pcs_dt_node_to_map,
 385         .dt_free_map = pcs_dt_free_map,
 386 };
 387
 388 static int pcs_get_functions_count(struct pinctrl_dev *pctldev)
 389 {
 390         struct pcs_device *pcs;
 391
 392         pcs = pinctrl_dev_get_drvdata(pctldev);
 393
 394         return pcs->nfuncs;
 395 }
 396
 397 static const char *pcs_get_function_name(struct pinctrl_dev *pctldev,
 398                                                 unsigned fselector)
 399 {
 400         struct pcs_device *pcs;
 401         struct pcs_function *func;
 402
 403         pcs = pinctrl_dev_get_drvdata(pctldev);
 404         func = radix_tree_lookup(&pcs->ftree, fselector);
 405         if (!func) {
 406                 dev_err(pcs->dev, "%s could not find function%i\n",
 407                         __func__, fselector);
 408                 return NULL;
 409         }
 410
 411         return func->name;
 412 }
 413
 414 static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
 415                                         unsigned fselector,
 416                                         const char * const **groups,
 417                                         unsigned * const ngroups)
 418 {
 419         struct pcs_device *pcs;
 420         struct pcs_function *func;
 421
 422         pcs = pinctrl_dev_get_drvdata(pctldev);
 423         func = radix_tree_lookup(&pcs->ftree, fselector);
 424         if (!func) {
 425                 dev_err(pcs->dev, "%s could not find function%i\n",
 426                         __func__, fselector);
 427                 return -EINVAL;
 428         }
 429         *groups = func->pgnames;
 430         *ngroups = func->npgnames;
 431
 432         return 0;
 433 }
 434
 435 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
 436                             struct pcs_function **func)
 437 {
 438         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 439         struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
 440         const struct pinctrl_setting_mux *setting;
 441         unsigned fselector;
 442
 443         /* If pin is not described in DTS & enabled, mux_setting is NULL. */
 444         setting = pdesc->mux_setting;
 445         if (!setting)
 446                 return -ENOTSUPP;
 447         fselector = setting->func;
 448         *func = radix_tree_lookup(&pcs->ftree, fselector);
 449         if (!(*func)) {
 450                 dev_err(pcs->dev, "%s could not find function%i\n",
 451                         __func__, fselector);
 452                 return -ENOTSUPP;
 453         }
 454         return 0;
 455 }
 456
 457 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
 458         unsigned group)
 459 {
 460         struct pcs_device *pcs;
 461         struct pcs_function *func;
 462         int i;
 463
 464         pcs = pinctrl_dev_get_drvdata(pctldev);
 465         /* If function mask is null, needn't enable it. */
 466         if (!pcs->fmask)
 467                 return 0;
 468         func = radix_tree_lookup(&pcs->ftree, fselector);
 469         if (!func)
 470                 return -EINVAL;
 471
 472         dev_dbg(pcs->dev, "enabling %s function%i\n",
 473                 func->name, fselector);
 474
 475         for (i = 0; i < func->nvals; i++) {
 476                 struct pcs_func_vals *vals;
 477                 unsigned long flags;
 478                 unsigned val, mask;
 479
 480                 vals = &func->vals[i];
 481                 raw_spin_lock_irqsave(&pcs->lock, flags);
 482                 val = pcs->read(vals->reg);
 483
 484                 if (pcs->bits_per_mux)
 485                         mask = vals->mask;
 486                 else
 487                         mask = pcs->fmask;
 488
 489                 val &= ~mask;
 490                 val |= (vals->val & mask);
 491                 pcs->write(val, vals->reg);
 492                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
 493         }
 494
 495         return 0;
 496 }
 497
 498 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
 499                             struct pinctrl_gpio_range *range, unsigned pin)
 500 {
 501         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 502         struct pcs_gpiofunc_range *frange = NULL;
 503         struct list_head *pos, *tmp;
 504         int mux_bytes = 0;
 505         unsigned data;
 506
 507         /* If function mask is null, return directly. */
 508         if (!pcs->fmask)
 509                 return -ENOTSUPP;
 510
 511         list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
 512                 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
 513                 if (pin >= frange->offset + frange->npins
 514                         || pin < frange->offset)
 515                         continue;
 516                 mux_bytes = pcs->width / BITS_PER_BYTE;
 517                 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
 518                 data |= frange->gpiofunc;
 519                 pcs->write(data, pcs->base + pin * mux_bytes);
 520                 break;
 521         }
 522         return 0;
 523 }
 524
 525 static const struct pinmux_ops pcs_pinmux_ops = {
 526         .get_functions_count = pcs_get_functions_count,
 527         .get_function_name = pcs_get_function_name,
 528         .get_function_groups = pcs_get_function_groups,
 529         .set_mux = pcs_set_mux,
 530         .gpio_request_enable = pcs_request_gpio,
 531 };
 532
 533 /* Clear BIAS value */
 534 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
 535 {
 536         unsigned long config;
 537         int i;
 538         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 539                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 540                 pcs_pinconf_set(pctldev, pin, &config, 1);
 541         }
 542 }
 543
 544 /*
 545  * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
 546  * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
 547  */
 548 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
 549 {
 550         unsigned long config;
 551         int i;
 552
 553         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 554                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 555                 if (!pcs_pinconf_get(pctldev, pin, &config))
 556                         goto out;
 557         }
 558         return true;
 559 out:
 560         return false;
 561 }
 562
 563 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
 564                                 unsigned pin, unsigned long *config)
 565 {
 566         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 567         struct pcs_function *func;
 568         enum pin_config_param param;
 569         unsigned offset = 0, data = 0, i, j, ret;
 570
 571         ret = pcs_get_function(pctldev, pin, &func);
 572         if (ret)
 573                 return ret;
 574
 575         for (i = 0; i < func->nconfs; i++) {
 576                 param = pinconf_to_config_param(*config);
 577                 if (param == PIN_CONFIG_BIAS_DISABLE) {
 578                         if (pcs_pinconf_bias_disable(pctldev, pin)) {
 579                                 *config = 0;
 580                                 return 0;
 581                         } else {
 582                                 return -ENOTSUPP;
 583                         }
 584                 } else if (param != func->conf[i].param) {
 585                         continue;
 586                 }
 587
 588                 offset = pin * (pcs->width / BITS_PER_BYTE);
 589                 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
 590                 switch (func->conf[i].param) {
 591                 /* 4 parameters */
 592                 case PIN_CONFIG_BIAS_PULL_DOWN:
 593                 case PIN_CONFIG_BIAS_PULL_UP:
 594                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 595                         if ((data != func->conf[i].enable) ||
 596                             (data == func->conf[i].disable))
 597                                 return -ENOTSUPP;
 598                         *config = 0;
 599                         break;
 600                 /* 2 parameters */
 601                 case PIN_CONFIG_INPUT_SCHMITT:
 602                         for (j = 0; j < func->nconfs; j++) {
 603                                 switch (func->conf[j].param) {
 604                                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 605                                         if (data != func->conf[j].enable)
 606                                                 return -ENOTSUPP;
 607                                         break;
 608                                 default:
 609                                         break;
 610                                 }
 611                         }
 612                         *config = data;
 613                         break;
 614                 case PIN_CONFIG_DRIVE_STRENGTH:
 615                 case PIN_CONFIG_SLEW_RATE:
 616                 case PIN_CONFIG_LOW_POWER_MODE:
 617                 default:
 618                         *config = data;
 619                         break;
 620                 }
 621                 return 0;
 622         }
 623         return -ENOTSUPP;
 624 }
 625
 626 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
 627                                 unsigned pin, unsigned long *configs,
 628                                 unsigned num_configs)
 629 {
 630         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 631         struct pcs_function *func;
 632         unsigned offset = 0, shift = 0, i, data, ret;
 633         u16 arg;
 634         int j;
 635
 636         ret = pcs_get_function(pctldev, pin, &func);
 637         if (ret)
 638                 return ret;
 639
 640         for (j = 0; j < num_configs; j++) {
 641                 for (i = 0; i < func->nconfs; i++) {
 642                         if (pinconf_to_config_param(configs[j])
 643                                 != func->conf[i].param)
 644                                 continue;
 645
 646                         offset = pin * (pcs->width / BITS_PER_BYTE);
 647                         data = pcs->read(pcs->base + offset);
 648                         arg = pinconf_to_config_argument(configs[j]);
 649                         switch (func->conf[i].param) {
 650                         /* 2 parameters */
 651                         case PIN_CONFIG_INPUT_SCHMITT:
 652                         case PIN_CONFIG_DRIVE_STRENGTH:
 653                         case PIN_CONFIG_SLEW_RATE:
 654                         case PIN_CONFIG_LOW_POWER_MODE:
 655                                 shift = ffs(func->conf[i].mask) - 1;
 656                                 data &= ~func->conf[i].mask;
 657                                 data |= (arg << shift) & func->conf[i].mask;
 658                                 break;
 659                         /* 4 parameters */
 660                         case PIN_CONFIG_BIAS_DISABLE:
 661                                 pcs_pinconf_clear_bias(pctldev, pin);
 662                                 break;
 663                         case PIN_CONFIG_BIAS_PULL_DOWN:
 664                         case PIN_CONFIG_BIAS_PULL_UP:
 665                                 if (arg)
 666                                         pcs_pinconf_clear_bias(pctldev, pin);
 667                                 /* fall through */
 668                         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 669                                 data &= ~func->conf[i].mask;
 670                                 if (arg)
 671                                         data |= func->conf[i].enable;
 672                                 else
 673                                         data |= func->conf[i].disable;
 674                                 break;
 675                         default:
 676                                 return -ENOTSUPP;
 677                         }
 678                         pcs->write(data, pcs->base + offset);
 679
 680                         break;
 681                 }
 682                 if (i >= func->nconfs)
 683                         return -ENOTSUPP;
 684         } /* for each config */
 685
 686         return 0;
 687 }
 688
 689 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
 690                                 unsigned group, unsigned long *config)
 691 {
 692         const unsigned *pins;
 693         unsigned npins, old = 0;
 694         int i, ret;
 695
 696         ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
 697         if (ret)
 698                 return ret;
 699         for (i = 0; i < npins; i++) {
 700                 if (pcs_pinconf_get(pctldev, pins[i], config))
 701                         return -ENOTSUPP;
 702                 /* configs do not match between two pins */
 703                 if (i && (old != *config))
 704                         return -ENOTSUPP;
 705                 old = *config;
 706         }
 707         return 0;
 708 }
 709
 710 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
 711                                 unsigned group, unsigned long *configs,
 712                                 unsigned num_configs)
 713 {
 714         const unsigned *pins;
 715         unsigned npins;
 716         int i, ret;
 717
 718         ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
 719         if (ret)
 720                 return ret;
 721         for (i = 0; i < npins; i++) {
 722                 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
 723                         return -ENOTSUPP;
 724         }
 725         return 0;
 726 }
 727
 728 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 729                                 struct seq_file *s, unsigned pin)
 730 {
 731 }
 732
 733 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 734                                 struct seq_file *s, unsigned selector)
 735 {
 736 }
 737
 738 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 739                                         struct seq_file *s,
 740                                         unsigned long config)
 741 {
 742         pinconf_generic_dump_config(pctldev, s, config);
 743 }
 744
 745 static const struct pinconf_ops pcs_pinconf_ops = {
 746         .pin_config_get = pcs_pinconf_get,
 747         .pin_config_set = pcs_pinconf_set,
 748         .pin_config_group_get = pcs_pinconf_group_get,
 749         .pin_config_group_set = pcs_pinconf_group_set,
 750         .pin_config_dbg_show = pcs_pinconf_dbg_show,
 751         .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
 752         .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
 753         .is_generic = true,
 754 };
 755
 756 /**
 757  * pcs_add_pin() - add a pin to the static per controller pin array
 758  * @pcs: pcs driver instance
 759  * @offset: register offset from base
 760  */
 761 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
 762                 unsigned pin_pos)
 763 {
 764         struct pcs_soc_data *pcs_soc = &pcs->socdata;
 765         struct pinctrl_pin_desc *pin;
 766         struct pcs_name *pn;
 767         int i;
 768
 769         i = pcs->pins.cur;
 770         if (i >= pcs->desc.npins) {
 771                 dev_err(pcs->dev, "too many pins, max %i\n",
 772                         pcs->desc.npins);
 773                 return -ENOMEM;
 774         }
 775
 776         if (pcs_soc->irq_enable_mask) {
 777                 unsigned val;
 778
 779                 val = pcs->read(pcs->base + offset);
 780                 if (val & pcs_soc->irq_enable_mask) {
 781                         dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
 782                                 (unsigned long)pcs->res->start + offset, val);
 783                         val &= ~pcs_soc->irq_enable_mask;
 784                         pcs->write(val, pcs->base + offset);
 785                 }
 786         }
 787
 788         pin = &pcs->pins.pa[i];
 789         pn = &pcs->names[i];
 790         sprintf(pn->name, "%lx.%u",
 791                 (unsigned long)pcs->res->start + offset, pin_pos);
 792         pin->name = pn->name;
 793         pin->number = i;
 794         pcs->pins.cur++;
 795
 796         return i;
 797 }
 798
 799 /**
 800  * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
 801  * @pcs: pcs driver instance
 802  *
 803  * In case of errors, resources are freed in pcs_free_resources.
 804  *
 805  * If your hardware needs holes in the address space, then just set
 806  * up multiple driver instances.
 807  */
 808 static int pcs_allocate_pin_table(struct pcs_device *pcs)
 809 {
 810         int mux_bytes, nr_pins, i;
 811         int num_pins_in_register = 0;
 812
 813         mux_bytes = pcs->width / BITS_PER_BYTE;
 814
 815         if (pcs->bits_per_mux) {
 816                 pcs->bits_per_pin = fls(pcs->fmask);
 817                 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
 818                 num_pins_in_register = pcs->width / pcs->bits_per_pin;
 819         } else {
 820                 nr_pins = pcs->size / mux_bytes;
 821         }
 822
 823         dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
 824         pcs->pins.pa = devm_kzalloc(pcs->dev,
 825                                 sizeof(*pcs->pins.pa) * nr_pins,
 826                                 GFP_KERNEL);
 827         if (!pcs->pins.pa)
 828                 return -ENOMEM;
 829
 830         pcs->names = devm_kzalloc(pcs->dev,
 831                                 sizeof(struct pcs_name) * nr_pins,
 832                                 GFP_KERNEL);
 833         if (!pcs->names)
 834                 return -ENOMEM;
 835
 836         pcs->desc.pins = pcs->pins.pa;
 837         pcs->desc.npins = nr_pins;
 838
 839         for (i = 0; i < pcs->desc.npins; i++) {
 840                 unsigned offset;
 841                 int res;
 842                 int byte_num;
 843                 int pin_pos = 0;
 844
 845                 if (pcs->bits_per_mux) {
 846                         byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
 847                         offset = (byte_num / mux_bytes) * mux_bytes;
 848                         pin_pos = i % num_pins_in_register;
 849                 } else {
 850                         offset = i * mux_bytes;
 851                 }
 852                 res = pcs_add_pin(pcs, offset, pin_pos);
 853                 if (res < 0) {
 854                         dev_err(pcs->dev, "error adding pins: %i\n", res);
 855                         return res;
 856                 }
 857         }
 858
 859         return 0;
 860 }
 861
 862 /**
 863  * pcs_add_function() - adds a new function to the function list
 864  * @pcs: pcs driver instance
 865  * @np: device node of the mux entry
 866  * @name: name of the function
 867  * @vals: array of mux register value pairs used by the function
 868  * @nvals: number of mux register value pairs
 869  * @pgnames: array of pingroup names for the function
 870  * @npgnames: number of pingroup names
 871  */
 872 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
 873                                         struct device_node *np,
 874                                         const char *name,
 875                                         struct pcs_func_vals *vals,
 876                                         unsigned nvals,
 877                                         const char **pgnames,
 878                                         unsigned npgnames)
 879 {
 880         struct pcs_function *function;
 881
 882         function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
 883         if (!function)
 884                 return NULL;
 885
 886         function->name = name;
 887         function->vals = vals;
 888         function->nvals = nvals;
 889         function->pgnames = pgnames;
 890         function->npgnames = npgnames;
 891
 892         mutex_lock(&pcs->mutex);
 893         list_add_tail(&function->node, &pcs->functions);
 894         radix_tree_insert(&pcs->ftree, pcs->nfuncs, function);
 895         pcs->nfuncs++;
 896         mutex_unlock(&pcs->mutex);
 897
 898         return function;
 899 }
 900
 901 static void pcs_remove_function(struct pcs_device *pcs,
 902                                 struct pcs_function *function)
 903 {
 904         int i;
 905
 906         mutex_lock(&pcs->mutex);
 907         for (i = 0; i < pcs->nfuncs; i++) {
 908                 struct pcs_function *found;
 909
 910                 found = radix_tree_lookup(&pcs->ftree, i);
 911                 if (found == function)
 912                         radix_tree_delete(&pcs->ftree, i);
 913         }
 914         list_del(&function->node);
 915         mutex_unlock(&pcs->mutex);
 916 }
 917
 918 /**
 919  * pcs_add_pingroup() - add a pingroup to the pingroup list
 920  * @pcs: pcs driver instance
 921  * @np: device node of the mux entry
 922  * @name: name of the pingroup
 923  * @gpins: array of the pins that belong to the group
 924  * @ngpins: number of pins in the group
 925  */
 926 static int pcs_add_pingroup(struct pcs_device *pcs,
 927                                         struct device_node *np,
 928                                         const char *name,
 929                                         int *gpins,
 930                                         int ngpins)
 931 {
 932         struct pcs_pingroup *pingroup;
 933
 934         pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL);
 935         if (!pingroup)
 936                 return -ENOMEM;
 937
 938         pingroup->name = name;
 939         pingroup->np = np;
 940         pingroup->gpins = gpins;
 941         pingroup->ngpins = ngpins;
 942
 943         mutex_lock(&pcs->mutex);
 944         list_add_tail(&pingroup->node, &pcs->pingroups);
 945         radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup);
 946         pcs->ngroups++;
 947         mutex_unlock(&pcs->mutex);
 948
 949         return 0;
 950 }
 951
 952 /**
 953  * pcs_get_pin_by_offset() - get a pin index based on the register offset
 954  * @pcs: pcs driver instance
 955  * @offset: register offset from the base
 956  *
 957  * Note that this is OK as long as the pins are in a static array.
 958  */
 959 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
 960 {
 961         unsigned index;
 962
 963         if (offset >= pcs->size) {
 964                 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
 965                         offset, pcs->size);
 966                 return -EINVAL;
 967         }
 968
 969         if (pcs->bits_per_mux)
 970                 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
 971         else
 972                 index = offset / (pcs->width / BITS_PER_BYTE);
 973
 974         return index;
 975 }
 976
 977 /*
 978  * check whether data matches enable bits or disable bits
 979  * Return value: 1 for matching enable bits, 0 for matching disable bits,
 980  *               and negative value for matching failure.
 981  */
 982 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
 983 {
 984         int ret = -EINVAL;
 985
 986         if (data == enable)
 987                 ret = 1;
 988         else if (data == disable)
 989                 ret = 0;
 990         return ret;
 991 }
 992
 993 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
 994                        unsigned value, unsigned enable, unsigned disable,
 995                        unsigned mask)
 996 {
 997         (*conf)->param = param;
 998         (*conf)->val = value;
 999         (*conf)->enable = enable;
1000         (*conf)->disable = disable;
1001         (*conf)->mask = mask;
1002         (*conf)++;
1003 }
1004
1005 static void add_setting(unsigned long **setting, enum pin_config_param param,
1006                         unsigned arg)
1007 {
1008         **setting = pinconf_to_config_packed(param, arg);
1009         (*setting)++;
1010 }
1011
1012 /* add pinconf setting with 2 parameters */
1013 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
1014                           const char *name, enum pin_config_param param,
1015                           struct pcs_conf_vals **conf, unsigned long **settings)
1016 {
1017         unsigned value[2], shift;
1018         int ret;
1019
1020         ret = of_property_read_u32_array(np, name, value, 2);
1021         if (ret)
1022                 return;
1023         /* set value & mask */
1024         value[0] &= value[1];
1025         shift = ffs(value[1]) - 1;
1026         /* skip enable & disable */
1027         add_config(conf, param, value[0], 0, 0, value[1]);
1028         add_setting(settings, param, value[0] >> shift);
1029 }
1030
1031 /* add pinconf setting with 4 parameters */
1032 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
1033                           const char *name, enum pin_config_param param,
1034                           struct pcs_conf_vals **conf, unsigned long **settings)
1035 {
1036         unsigned value[4];
1037         int ret;
1038
1039         /* value to set, enable, disable, mask */
1040         ret = of_property_read_u32_array(np, name, value, 4);
1041         if (ret)
1042                 return;
1043         if (!value[3]) {
1044                 dev_err(pcs->dev, "mask field of the property can't be 0\n");
1045                 return;
1046         }
1047         value[0] &= value[3];
1048         value[1] &= value[3];
1049         value[2] &= value[3];
1050         ret = pcs_config_match(value[0], value[1], value[2]);
1051         if (ret < 0)
1052                 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
1053         add_config(conf, param, value[0], value[1], value[2], value[3]);
1054         add_setting(settings, param, ret);
1055 }
1056
1057 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
1058                              struct pcs_function *func,
1059                              struct pinctrl_map **map)
1060
1061 {
1062         struct pinctrl_map *m = *map;
1063         int i = 0, nconfs = 0;
1064         unsigned long *settings = NULL, *s = NULL;
1065         struct pcs_conf_vals *conf = NULL;
1066         struct pcs_conf_type prop2[] = {
1067                 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
1068                 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
1069                 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
1070                 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
1071         };
1072         struct pcs_conf_type prop4[] = {
1073                 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
1074                 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
1075                 { "pinctrl-single,input-schmitt-enable",
1076                         PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
1077         };
1078
1079         /* If pinconf isn't supported, don't parse properties in below. */
1080         if (!PCS_HAS_PINCONF)
1081                 return 0;
1082
1083         /* cacluate how much properties are supported in current node */
1084         for (i = 0; i < ARRAY_SIZE(prop2); i++) {
1085                 if (of_find_property(np, prop2[i].name, NULL))
1086                         nconfs++;
1087         }
1088         for (i = 0; i < ARRAY_SIZE(prop4); i++) {
1089                 if (of_find_property(np, prop4[i].name, NULL))
1090                         nconfs++;
1091         }
1092         if (!nconfs)
1093                 return 0;
1094
1095         func->conf = devm_kzalloc(pcs->dev,
1096                                   sizeof(struct pcs_conf_vals) * nconfs,
1097                                   GFP_KERNEL);
1098         if (!func->conf)
1099                 return -ENOMEM;
1100         func->nconfs = nconfs;
1101         conf = &(func->conf[0]);
1102         m++;
1103         settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
1104                                 GFP_KERNEL);
1105         if (!settings)
1106                 return -ENOMEM;
1107         s = &settings[0];
1108
1109         for (i = 0; i < ARRAY_SIZE(prop2); i++)
1110                 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
1111                               &conf, &s);
1112         for (i = 0; i < ARRAY_SIZE(prop4); i++)
1113                 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
1114                               &conf, &s);
1115         m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
1116         m->data.configs.group_or_pin = np->name;
1117         m->data.configs.configs = settings;
1118         m->data.configs.num_configs = nconfs;
1119         return 0;
1120 }
1121
1122 static void pcs_free_pingroups(struct pcs_device *pcs);
1123
1124 /**
1125  * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
1126  * @pcs: pinctrl driver instance
1127  * @np: device node of the mux entry
1128  * @map: map entry
1129  * @num_maps: number of map
1130  * @pgnames: pingroup names
1131  *
1132  * Note that this binding currently supports only sets of one register + value.
1133  *
1134  * Also note that this driver tries to avoid understanding pin and function
1135  * names because of the extra bloat they would cause especially in the case of
1136  * a large number of pins. This driver just sets what is specified for the board
1137  * in the .dts file. Further user space debugging tools can be developed to
1138  * decipher the pin and function names using debugfs.
1139  *
1140  * If you are concerned about the boot time, set up the static pins in
1141  * the bootloader, and only set up selected pins as device tree entries.
1142  */
1143 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1144                                                 struct device_node *np,
1145                                                 struct pinctrl_map **map,
1146                                                 unsigned *num_maps,
1147                                                 const char **pgnames)
1148 {
1149         struct pcs_func_vals *vals;
1150         const __be32 *mux;
1151         int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1152         struct pcs_function *function;
1153
1154         mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
1155         if ((!mux) || (size < sizeof(*mux) * 2)) {
1156                 dev_err(pcs->dev, "bad data for mux %s\n",
1157                         np->name);
1158                 return -EINVAL;
1159         }
1160
1161         size /= sizeof(*mux);   /* Number of elements in array */
1162         rows = size / 2;
1163
1164         vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
1165         if (!vals)
1166                 return -ENOMEM;
1167
1168         pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
1169         if (!pins)
1170                 goto free_vals;
1171
1172         while (index < size) {
1173                 unsigned offset, val;
1174                 int pin;
1175
1176                 offset = be32_to_cpup(mux + index++);
1177                 val = be32_to_cpup(mux + index++);
1178                 vals[found].reg = pcs->base + offset;
1179                 vals[found].val = val;
1180
1181                 pin = pcs_get_pin_by_offset(pcs, offset);
1182                 if (pin < 0) {
1183                         dev_err(pcs->dev,
1184                                 "could not add functions for %s %ux\n",
1185                                 np->name, offset);
1186                         break;
1187                 }
1188                 pins[found++] = pin;
1189         }
1190
1191         pgnames[0] = np->name;
1192         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1193         if (!function)
1194                 goto free_pins;
1195
1196         res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1197         if (res < 0)
1198                 goto free_function;
1199
1200         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1201         (*map)->data.mux.group = np->name;
1202         (*map)->data.mux.function = np->name;
1203
1204         if (PCS_HAS_PINCONF) {
1205                 res = pcs_parse_pinconf(pcs, np, function, map);
1206                 if (res)
1207                         goto free_pingroups;
1208                 *num_maps = 2;
1209         } else {
1210                 *num_maps = 1;
1211         }
1212         return 0;
1213
1214 free_pingroups:
1215         pcs_free_pingroups(pcs);
1216         *num_maps = 1;
1217 free_function:
1218         pcs_remove_function(pcs, function);
1219
1220 free_pins:
1221         devm_kfree(pcs->dev, pins);
1222
1223 free_vals:
1224         devm_kfree(pcs->dev, vals);
1225
1226         return res;
1227 }
1228
1229 #define PARAMS_FOR_BITS_PER_MUX 3
1230
1231 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1232                                                 struct device_node *np,
1233                                                 struct pinctrl_map **map,
1234                                                 unsigned *num_maps,
1235                                                 const char **pgnames)
1236 {
1237         struct pcs_func_vals *vals;
1238         const __be32 *mux;
1239         int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1240         int npins_in_row;
1241         struct pcs_function *function;
1242
1243         mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
1244
1245         if (!mux) {
1246                 dev_err(pcs->dev, "no valid property for %s\n", np->name);
1247                 return -EINVAL;
1248         }
1249
1250         if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) {
1251                 dev_err(pcs->dev, "bad data for %s\n", np->name);
1252                 return -EINVAL;
1253         }
1254
1255         /* Number of elements in array */
1256         size /= sizeof(*mux);
1257
1258         rows = size / PARAMS_FOR_BITS_PER_MUX;
1259         npins_in_row = pcs->width / pcs->bits_per_pin;
1260
1261         vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1262                         GFP_KERNEL);
1263         if (!vals)
1264                 return -ENOMEM;
1265
1266         pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1267                         GFP_KERNEL);
1268         if (!pins)
1269                 goto free_vals;
1270
1271         while (index < size) {
1272                 unsigned offset, val;
1273                 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1274                 unsigned pin_num_from_lsb;
1275                 int pin;
1276
1277                 offset = be32_to_cpup(mux + index++);
1278                 val = be32_to_cpup(mux + index++);
1279                 mask = be32_to_cpup(mux + index++);
1280
1281                 /* Parse pins in each row from LSB */
1282                 while (mask) {
1283                         bit_pos = __ffs(mask);
1284                         pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1285                         mask_pos = ((pcs->fmask) << bit_pos);
1286                         val_pos = val & mask_pos;
1287                         submask = mask & mask_pos;
1288
1289                         if ((mask & mask_pos) == 0) {
1290                                 dev_err(pcs->dev,
1291                                         "Invalid mask for %s at 0x%x\n",
1292                                         np->name, offset);
1293                                 break;
1294                         }
1295
1296                         mask &= ~mask_pos;
1297
1298                         if (submask != mask_pos) {
1299                                 dev_warn(pcs->dev,
1300                                                 "Invalid submask 0x%x for %s at 0x%x\n",
1301                                                 submask, np->name, offset);
1302                                 continue;
1303                         }
1304
1305                         vals[found].mask = submask;
1306                         vals[found].reg = pcs->base + offset;
1307                         vals[found].val = val_pos;
1308
1309                         pin = pcs_get_pin_by_offset(pcs, offset);
1310                         if (pin < 0) {
1311                                 dev_err(pcs->dev,
1312                                         "could not add functions for %s %ux\n",
1313                                         np->name, offset);
1314                                 break;
1315                         }
1316                         pins[found++] = pin + pin_num_from_lsb;
1317                 }
1318         }
1319
1320         pgnames[0] = np->name;
1321         function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1322         if (!function)
1323                 goto free_pins;
1324
1325         res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1326         if (res < 0)
1327                 goto free_function;
1328
1329         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1330         (*map)->data.mux.group = np->name;
1331         (*map)->data.mux.function = np->name;
1332
1333         if (PCS_HAS_PINCONF) {
1334                 dev_err(pcs->dev, "pinconf not supported\n");
1335                 goto free_pingroups;
1336         }
1337
1338         *num_maps = 1;
1339         return 0;
1340
1341 free_pingroups:
1342         pcs_free_pingroups(pcs);
1343         *num_maps = 1;
1344 free_function:
1345         pcs_remove_function(pcs, function);
1346
1347 free_pins:
1348         devm_kfree(pcs->dev, pins);
1349
1350 free_vals:
1351         devm_kfree(pcs->dev, vals);
1352
1353         return res;
1354 }
1355 /**
1356  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1357  * @pctldev: pinctrl instance
1358  * @np_config: device tree pinmux entry
1359  * @map: array of map entries
1360  * @num_maps: number of maps
1361  */
1362 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1363                                 struct device_node *np_config,
1364                                 struct pinctrl_map **map, unsigned *num_maps)
1365 {
1366         struct pcs_device *pcs;
1367         const char **pgnames;
1368         int ret;
1369
1370         pcs = pinctrl_dev_get_drvdata(pctldev);
1371
1372         /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1373         *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1374         if (!*map)
1375                 return -ENOMEM;
1376
1377         *num_maps = 0;
1378
1379         pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1380         if (!pgnames) {
1381                 ret = -ENOMEM;
1382                 goto free_map;
1383         }
1384
1385         if (pcs->bits_per_mux) {
1386                 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1387                                 num_maps, pgnames);
1388                 if (ret < 0) {
1389                         dev_err(pcs->dev, "no pins entries for %s\n",
1390                                 np_config->name);
1391                         goto free_pgnames;
1392                 }
1393         } else {
1394                 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1395                                 num_maps, pgnames);
1396                 if (ret < 0) {
1397                         dev_err(pcs->dev, "no pins entries for %s\n",
1398                                 np_config->name);
1399                         goto free_pgnames;
1400                 }
1401         }
1402
1403         return 0;
1404
1405 free_pgnames:
1406         devm_kfree(pcs->dev, pgnames);
1407 free_map:
1408         devm_kfree(pcs->dev, *map);
1409
1410         return ret;
1411 }
1412
1413 /**
1414  * pcs_free_funcs() - free memory used by functions
1415  * @pcs: pcs driver instance
1416  */
1417 static void pcs_free_funcs(struct pcs_device *pcs)
1418 {
1419         struct list_head *pos, *tmp;
1420         int i;
1421
1422         mutex_lock(&pcs->mutex);
1423         for (i = 0; i < pcs->nfuncs; i++) {
1424                 struct pcs_function *func;
1425
1426                 func = radix_tree_lookup(&pcs->ftree, i);
1427                 if (!func)
1428                         continue;
1429                 radix_tree_delete(&pcs->ftree, i);
1430         }
1431         list_for_each_safe(pos, tmp, &pcs->functions) {
1432                 struct pcs_function *function;
1433
1434                 function = list_entry(pos, struct pcs_function, node);
1435                 list_del(&function->node);
1436         }
1437         mutex_unlock(&pcs->mutex);
1438 }
1439
1440 /**
1441  * pcs_free_pingroups() - free memory used by pingroups
1442  * @pcs: pcs driver instance
1443  */
1444 static void pcs_free_pingroups(struct pcs_device *pcs)
1445 {
1446         struct list_head *pos, *tmp;
1447         int i;
1448
1449         mutex_lock(&pcs->mutex);
1450         for (i = 0; i < pcs->ngroups; i++) {
1451                 struct pcs_pingroup *pingroup;
1452
1453                 pingroup = radix_tree_lookup(&pcs->pgtree, i);
1454                 if (!pingroup)
1455                         continue;
1456                 radix_tree_delete(&pcs->pgtree, i);
1457         }
1458         list_for_each_safe(pos, tmp, &pcs->pingroups) {
1459                 struct pcs_pingroup *pingroup;
1460
1461                 pingroup = list_entry(pos, struct pcs_pingroup, node);
1462                 list_del(&pingroup->node);
1463         }
1464         mutex_unlock(&pcs->mutex);
1465 }
1466
1467 /**
1468  * pcs_irq_free() - free interrupt
1469  * @pcs: pcs driver instance
1470  */
1471 static void pcs_irq_free(struct pcs_device *pcs)
1472 {
1473         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1474
1475         if (pcs_soc->irq < 0)
1476                 return;
1477
1478         if (pcs->domain)
1479                 irq_domain_remove(pcs->domain);
1480
1481         if (PCS_QUIRK_HAS_SHARED_IRQ)
1482                 free_irq(pcs_soc->irq, pcs_soc);
1483         else
1484                 irq_set_chained_handler(pcs_soc->irq, NULL);
1485 }
1486
1487 /**
1488  * pcs_free_resources() - free memory used by this driver
1489  * @pcs: pcs driver instance
1490  */
1491 static void pcs_free_resources(struct pcs_device *pcs)
1492 {
1493         pcs_irq_free(pcs);
1494         pinctrl_unregister(pcs->pctl);
1495         pcs_free_funcs(pcs);
1496         pcs_free_pingroups(pcs);
1497 }
1498
1499 #define PCS_GET_PROP_U32(name, reg, err)                                \
1500         do {                                                            \
1501                 ret = of_property_read_u32(np, name, reg);              \
1502                 if (ret) {                                              \
1503                         dev_err(pcs->dev, err);                         \
1504                         return ret;                                     \
1505                 }                                                       \
1506         } while (0);
1507
1508 static const struct of_device_id pcs_of_match[];
1509
1510 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1511 {
1512         const char *propname = "pinctrl-single,gpio-range";
1513         const char *cellname = "#pinctrl-single,gpio-range-cells";
1514         struct of_phandle_args gpiospec;
1515         struct pcs_gpiofunc_range *range;
1516         int ret, i;
1517
1518         for (i = 0; ; i++) {
1519                 ret = of_parse_phandle_with_args(node, propname, cellname,
1520                                                  i, &gpiospec);
1521                 /* Do not treat it as error. Only treat it as end condition. */
1522                 if (ret) {
1523                         ret = 0;
1524                         break;
1525                 }
1526                 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1527                 if (!range) {
1528                         ret = -ENOMEM;
1529                         break;
1530                 }
1531                 range->offset = gpiospec.args[0];
1532                 range->npins = gpiospec.args[1];
1533                 range->gpiofunc = gpiospec.args[2];
1534                 mutex_lock(&pcs->mutex);
1535                 list_add_tail(&range->node, &pcs->gpiofuncs);
1536                 mutex_unlock(&pcs->mutex);
1537         }
1538         return ret;
1539 }
1540 /**
1541  * @reg:        virtual address of interrupt register
1542  * @hwirq:      hardware irq number
1543  * @irq:        virtual irq number
1544  * @node:       list node
1545  */
1546 struct pcs_interrupt {
1547         void __iomem *reg;
1548         irq_hw_number_t hwirq;
1549         unsigned int irq;
1550         struct list_head node;
1551 };
1552
1553 /**
1554  * pcs_irq_set() - enables or disables an interrupt
1555  *
1556  * Note that this currently assumes one interrupt per pinctrl
1557  * register that is typically used for wake-up events.
1558  */
1559 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1560                                int irq, const bool enable)
1561 {
1562         struct pcs_device *pcs;
1563         struct list_head *pos;
1564         unsigned mask;
1565
1566         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1567         list_for_each(pos, &pcs->irqs) {
1568                 struct pcs_interrupt *pcswi;
1569                 unsigned soc_mask;
1570
1571                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1572                 if (irq != pcswi->irq)
1573                         continue;
1574
1575                 soc_mask = pcs_soc->irq_enable_mask;
1576                 raw_spin_lock(&pcs->lock);
1577                 mask = pcs->read(pcswi->reg);
1578                 if (enable)
1579                         mask |= soc_mask;
1580                 else
1581                         mask &= ~soc_mask;
1582                 pcs->write(mask, pcswi->reg);
1583
1584                 /* flush posted write */
1585                 mask = pcs->read(pcswi->reg);
1586                 raw_spin_unlock(&pcs->lock);
1587         }
1588
1589         if (pcs_soc->rearm)
1590                 pcs_soc->rearm();
1591 }
1592
1593 /**
1594  * pcs_irq_mask() - mask pinctrl interrupt
1595  * @d: interrupt data
1596  */
1597 static void pcs_irq_mask(struct irq_data *d)
1598 {
1599         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1600
1601         pcs_irq_set(pcs_soc, d->irq, false);
1602 }
1603
1604 /**
1605  * pcs_irq_unmask() - unmask pinctrl interrupt
1606  * @d: interrupt data
1607  */
1608 static void pcs_irq_unmask(struct irq_data *d)
1609 {
1610         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1611
1612         pcs_irq_set(pcs_soc, d->irq, true);
1613 }
1614
1615 /**
1616  * pcs_irq_set_wake() - toggle the suspend and resume wake up
1617  * @d: interrupt data
1618  * @state: wake-up state
1619  *
1620  * Note that this should be called only for suspend and resume.
1621  * For runtime PM, the wake-up events should be enabled by default.
1622  */
1623 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1624 {
1625         if (state)
1626                 pcs_irq_unmask(d);
1627         else
1628                 pcs_irq_mask(d);
1629
1630         return 0;
1631 }
1632
1633 /**
1634  * pcs_irq_handle() - common interrupt handler
1635  * @pcs_irq: interrupt data
1636  *
1637  * Note that this currently assumes we have one interrupt bit per
1638  * mux register. This interrupt is typically used for wake-up events.
1639  * For more complex interrupts different handlers can be specified.
1640  */
1641 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1642 {
1643         struct pcs_device *pcs;
1644         struct list_head *pos;
1645         int count = 0;
1646
1647         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1648         list_for_each(pos, &pcs->irqs) {
1649                 struct pcs_interrupt *pcswi;
1650                 unsigned mask;
1651
1652                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1653                 raw_spin_lock(&pcs->lock);
1654                 mask = pcs->read(pcswi->reg);
1655                 raw_spin_unlock(&pcs->lock);
1656                 if (mask & pcs_soc->irq_status_mask) {
1657                         generic_handle_irq(irq_find_mapping(pcs->domain,
1658                                                             pcswi->hwirq));
1659                         count++;
1660                 }
1661         }
1662
1663         return count;
1664 }
1665
1666 /**
1667  * pcs_irq_handler() - handler for the shared interrupt case
1668  * @irq: interrupt
1669  * @d: data
1670  *
1671  * Use this for cases where multiple instances of
1672  * pinctrl-single share a single interrupt like on omaps.
1673  */
1674 static irqreturn_t pcs_irq_handler(int irq, void *d)
1675 {
1676         struct pcs_soc_data *pcs_soc = d;
1677
1678         return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1679 }
1680
1681 /**
1682  * pcs_irq_handle() - handler for the dedicated chained interrupt case
1683  * @irq: interrupt
1684  * @desc: interrupt descriptor
1685  *
1686  * Use this if you have a separate interrupt for each
1687  * pinctrl-single instance.
1688  */
1689 static void pcs_irq_chain_handler(struct irq_desc *desc)
1690 {
1691         struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1692         struct irq_chip *chip;
1693
1694         chip = irq_desc_get_chip(desc);
1695         chained_irq_enter(chip, desc);
1696         pcs_irq_handle(pcs_soc);
1697         /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1698         chained_irq_exit(chip, desc);
1699
1700         return;
1701 }
1702
1703 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1704                              irq_hw_number_t hwirq)
1705 {
1706         struct pcs_soc_data *pcs_soc = d->host_data;
1707         struct pcs_device *pcs;
1708         struct pcs_interrupt *pcswi;
1709
1710         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1711         pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1712         if (!pcswi)
1713                 return -ENOMEM;
1714
1715         pcswi->reg = pcs->base + hwirq;
1716         pcswi->hwirq = hwirq;
1717         pcswi->irq = irq;
1718
1719         mutex_lock(&pcs->mutex);
1720         list_add_tail(&pcswi->node, &pcs->irqs);
1721         mutex_unlock(&pcs->mutex);
1722
1723         irq_set_chip_data(irq, pcs_soc);
1724         irq_set_chip_and_handler(irq, &pcs->chip,
1725                                  handle_level_irq);
1726         irq_set_lockdep_class(irq, &pcs_lock_class);
1727         irq_set_noprobe(irq);
1728
1729         return 0;
1730 }
1731
1732 static const struct irq_domain_ops pcs_irqdomain_ops = {
1733         .map = pcs_irqdomain_map,
1734         .xlate = irq_domain_xlate_onecell,
1735 };
1736
1737 /**
1738  * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1739  * @pcs: pcs driver instance
1740  * @np: device node pointer
1741  */
1742 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1743                                         struct device_node *np)
1744 {
1745         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1746         const char *name = "pinctrl";
1747         int num_irqs;
1748
1749         if (!pcs_soc->irq_enable_mask ||
1750             !pcs_soc->irq_status_mask) {
1751                 pcs_soc->irq = -1;
1752                 return -EINVAL;
1753         }
1754
1755         INIT_LIST_HEAD(&pcs->irqs);
1756         pcs->chip.name = name;
1757         pcs->chip.irq_ack = pcs_irq_mask;
1758         pcs->chip.irq_mask = pcs_irq_mask;
1759         pcs->chip.irq_unmask = pcs_irq_unmask;
1760         pcs->chip.irq_set_wake = pcs_irq_set_wake;
1761
1762         if (PCS_QUIRK_HAS_SHARED_IRQ) {
1763                 int res;
1764
1765                 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1766                                   IRQF_SHARED | IRQF_NO_SUSPEND |
1767                                   IRQF_NO_THREAD,
1768                                   name, pcs_soc);
1769                 if (res) {
1770                         pcs_soc->irq = -1;
1771                         return res;
1772                 }
1773         } else {
1774                 irq_set_chained_handler_and_data(pcs_soc->irq,
1775                                                  pcs_irq_chain_handler,
1776                                                  pcs_soc);
1777         }
1778
1779         /*
1780          * We can use the register offset as the hardirq
1781          * number as irq_domain_add_simple maps them lazily.
1782          * This way we can easily support more than one
1783          * interrupt per function if needed.
1784          */
1785         num_irqs = pcs->size;
1786
1787         pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1788                                             &pcs_irqdomain_ops,
1789                                             pcs_soc);
1790         if (!pcs->domain) {
1791                 irq_set_chained_handler(pcs_soc->irq, NULL);
1792                 return -EINVAL;
1793         }
1794
1795         return 0;
1796 }
1797
1798 #ifdef CONFIG_PM
1799 static int pinctrl_single_suspend(struct platform_device *pdev,
1800                                         pm_message_t state)
1801 {
1802         struct pcs_device *pcs;
1803
1804         pcs = platform_get_drvdata(pdev);
1805         if (!pcs)
1806                 return -EINVAL;
1807
1808         return pinctrl_force_sleep(pcs->pctl);
1809 }
1810
1811 static int pinctrl_single_resume(struct platform_device *pdev)
1812 {
1813         struct pcs_device *pcs;
1814
1815         pcs = platform_get_drvdata(pdev);
1816         if (!pcs)
1817                 return -EINVAL;
1818
1819         return pinctrl_force_default(pcs->pctl);
1820 }
1821 #endif
1822
1823 static int pcs_probe(struct platform_device *pdev)
1824 {
1825         struct device_node *np = pdev->dev.of_node;
1826         const struct of_device_id *match;
1827         struct pcs_pdata *pdata;
1828         struct resource *res;
1829         struct pcs_device *pcs;
1830         const struct pcs_soc_data *soc;
1831         int ret;
1832
1833         match = of_match_device(pcs_of_match, &pdev->dev);
1834         if (!match)
1835                 return -EINVAL;
1836
1837         pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1838         if (!pcs) {
1839                 dev_err(&pdev->dev, "could not allocate\n");
1840                 return -ENOMEM;
1841         }
1842         pcs->dev = &pdev->dev;
1843         raw_spin_lock_init(&pcs->lock);
1844         mutex_init(&pcs->mutex);
1845         INIT_LIST_HEAD(&pcs->pingroups);
1846         INIT_LIST_HEAD(&pcs->functions);
1847         INIT_LIST_HEAD(&pcs->gpiofuncs);
1848         soc = match->data;
1849         pcs->flags = soc->flags;
1850         memcpy(&pcs->socdata, soc, sizeof(*soc));
1851
1852         PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
1853                          "register width not specified\n");
1854
1855         ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1856                                    &pcs->fmask);
1857         if (!ret) {
1858                 pcs->fshift = __ffs(pcs->fmask);
1859                 pcs->fmax = pcs->fmask >> pcs->fshift;
1860         } else {
1861                 /* If mask property doesn't exist, function mux is invalid. */
1862                 pcs->fmask = 0;
1863                 pcs->fshift = 0;
1864                 pcs->fmax = 0;
1865         }
1866
1867         ret = of_property_read_u32(np, "pinctrl-single,function-off",
1868                                         &pcs->foff);
1869         if (ret)
1870                 pcs->foff = PCS_OFF_DISABLED;
1871
1872         pcs->bits_per_mux = of_property_read_bool(np,
1873                                                   "pinctrl-single,bit-per-mux");
1874
1875         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1876         if (!res) {
1877                 dev_err(pcs->dev, "could not get resource\n");
1878                 return -ENODEV;
1879         }
1880
1881         pcs->res = devm_request_mem_region(pcs->dev, res->start,
1882                         resource_size(res), DRIVER_NAME);
1883         if (!pcs->res) {
1884                 dev_err(pcs->dev, "could not get mem_region\n");
1885                 return -EBUSY;
1886         }
1887
1888         pcs->size = resource_size(pcs->res);
1889         pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1890         if (!pcs->base) {
1891                 dev_err(pcs->dev, "could not ioremap\n");
1892                 return -ENODEV;
1893         }
1894
1895         INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL);
1896         INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL);
1897         platform_set_drvdata(pdev, pcs);
1898
1899         switch (pcs->width) {
1900         case 8:
1901                 pcs->read = pcs_readb;
1902                 pcs->write = pcs_writeb;
1903                 break;
1904         case 16:
1905                 pcs->read = pcs_readw;
1906                 pcs->write = pcs_writew;
1907                 break;
1908         case 32:
1909                 pcs->read = pcs_readl;
1910                 pcs->write = pcs_writel;
1911                 break;
1912         default:
1913                 break;
1914         }
1915
1916         pcs->desc.name = DRIVER_NAME;
1917         pcs->desc.pctlops = &pcs_pinctrl_ops;
1918         pcs->desc.pmxops = &pcs_pinmux_ops;
1919         if (PCS_HAS_PINCONF)
1920                 pcs->desc.confops = &pcs_pinconf_ops;
1921         pcs->desc.owner = THIS_MODULE;
1922
1923         ret = pcs_allocate_pin_table(pcs);
1924         if (ret < 0)
1925                 goto free;
1926
1927         pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs);
1928         if (IS_ERR(pcs->pctl)) {
1929                 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1930                 ret = PTR_ERR(pcs->pctl);
1931                 goto free;
1932         }
1933
1934         ret = pcs_add_gpio_func(np, pcs);
1935         if (ret < 0)
1936                 goto free;
1937
1938         pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1939         if (pcs->socdata.irq)
1940                 pcs->flags |= PCS_FEAT_IRQ;
1941
1942         /* We still need auxdata for some omaps for PRM interrupts */
1943         pdata = dev_get_platdata(&pdev->dev);
1944         if (pdata) {
1945                 if (pdata->rearm)
1946                         pcs->socdata.rearm = pdata->rearm;
1947                 if (pdata->irq) {
1948                         pcs->socdata.irq = pdata->irq;
1949                         pcs->flags |= PCS_FEAT_IRQ;
1950                 }
1951         }
1952
1953         if (PCS_HAS_IRQ) {
1954                 ret = pcs_irq_init_chained_handler(pcs, np);
1955                 if (ret < 0)
1956                         dev_warn(pcs->dev, "initialized with no interrupts\n");
1957         }
1958
1959         dev_info(pcs->dev, "%i pins at pa %p size %u\n",
1960                  pcs->desc.npins, pcs->base, pcs->size);
1961
1962         return 0;
1963
1964 free:
1965         pcs_free_resources(pcs);
1966
1967         return ret;
1968 }
1969
1970 static int pcs_remove(struct platform_device *pdev)
1971 {
1972         struct pcs_device *pcs = platform_get_drvdata(pdev);
1973
1974         if (!pcs)
1975                 return 0;
1976
1977         pcs_free_resources(pcs);
1978
1979         return 0;
1980 }
1981
1982 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1983         .flags = PCS_QUIRK_SHARED_IRQ,
1984         .irq_enable_mask = (1 << 14),   /* OMAP_WAKEUP_EN */
1985         .irq_status_mask = (1 << 15),   /* OMAP_WAKEUP_EVENT */
1986 };
1987
1988 static const struct pcs_soc_data pinctrl_single_dra7 = {
1989         .irq_enable_mask = (1 << 24),   /* WAKEUPENABLE */
1990         .irq_status_mask = (1 << 25),   /* WAKEUPEVENT */
1991 };
1992
1993 static const struct pcs_soc_data pinctrl_single_am437x = {
1994         .flags = PCS_QUIRK_SHARED_IRQ,
1995         .irq_enable_mask = (1 << 29),   /* OMAP_WAKEUP_EN */
1996         .irq_status_mask = (1 << 30),   /* OMAP_WAKEUP_EVENT */
1997 };
1998
1999 static const struct pcs_soc_data pinctrl_single = {
2000 };
2001
2002 static const struct pcs_soc_data pinconf_single = {
2003         .flags = PCS_FEAT_PINCONF,
2004 };
2005
2006 static const struct of_device_id pcs_of_match[] = {
2007         { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
2008         { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
2009         { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
2010         { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
2011         { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
2012         { .compatible = "pinctrl-single", .data = &pinctrl_single },
2013         { .compatible = "pinconf-single", .data = &pinconf_single },
2014         { },
2015 };
2016 MODULE_DEVICE_TABLE(of, pcs_of_match);
2017
2018 static struct platform_driver pcs_driver = {
2019         .probe          = pcs_probe,
2020         .remove         = pcs_remove,
2021         .driver = {
2022                 .name           = DRIVER_NAME,
2023                 .of_match_table = pcs_of_match,
2024         },
2025 #ifdef CONFIG_PM
2026         .suspend = pinctrl_single_suspend,
2027         .resume = pinctrl_single_resume,
2028 #endif
2029 };
2030
2031 module_platform_driver(pcs_driver);
2032
2033 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
2034 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
2035 MODULE_LICENSE("GPL v2");