2 * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
3 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
7 * Driver for Semtech SX150X I2C GPIO Expanders
9 * Author: Gregory Bean <gbean@codeaurora.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 and
13 * only version 2 as published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include <linux/regmap.h>
22 #include <linux/i2c.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/mutex.h>
27 #include <linux/slab.h>
29 #include <linux/of_device.h>
30 #include <linux/gpio/driver.h>
31 #include <linux/pinctrl/pinconf.h>
32 #include <linux/pinctrl/pinctrl.h>
33 #include <linux/pinctrl/pinmux.h>
34 #include <linux/pinctrl/pinconf-generic.h>
38 #include "pinctrl-utils.h"
40 /* The chip models of sx150x */
47 SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0,
48 SX150X_MAX_REGISTER = 0xad,
49 SX150X_IRQ_TYPE_EDGE_RISING = 0x1,
50 SX150X_IRQ_TYPE_EDGE_FALLING = 0x2,
51 SX150X_789_RESET_KEY1 = 0x12,
52 SX150X_789_RESET_KEY2 = 0x34,
55 struct sx150x_123_pri {
65 struct sx150x_456_pri {
75 struct sx150x_789_pri {
84 struct sx150x_device_data {
95 struct sx150x_123_pri x123;
96 struct sx150x_456_pri x456;
97 struct sx150x_789_pri x789;
99 const struct pinctrl_pin_desc *pins;
103 struct sx150x_pinctrl {
105 struct i2c_client *client;
106 struct pinctrl_dev *pctldev;
107 struct pinctrl_desc pinctrl_desc;
108 struct gpio_chip gpio;
109 struct irq_chip irq_chip;
110 struct regmap *regmap;
116 const struct sx150x_device_data *data;
119 static const struct pinctrl_pin_desc sx150x_8_pins[] = {
120 PINCTRL_PIN(0, "gpio0"),
121 PINCTRL_PIN(1, "gpio1"),
122 PINCTRL_PIN(2, "gpio2"),
123 PINCTRL_PIN(3, "gpio3"),
124 PINCTRL_PIN(4, "gpio4"),
125 PINCTRL_PIN(5, "gpio5"),
126 PINCTRL_PIN(6, "gpio6"),
127 PINCTRL_PIN(7, "gpio7"),
128 PINCTRL_PIN(8, "oscio"),
131 static const struct pinctrl_pin_desc sx150x_16_pins[] = {
132 PINCTRL_PIN(0, "gpio0"),
133 PINCTRL_PIN(1, "gpio1"),
134 PINCTRL_PIN(2, "gpio2"),
135 PINCTRL_PIN(3, "gpio3"),
136 PINCTRL_PIN(4, "gpio4"),
137 PINCTRL_PIN(5, "gpio5"),
138 PINCTRL_PIN(6, "gpio6"),
139 PINCTRL_PIN(7, "gpio7"),
140 PINCTRL_PIN(8, "gpio8"),
141 PINCTRL_PIN(9, "gpio9"),
142 PINCTRL_PIN(10, "gpio10"),
143 PINCTRL_PIN(11, "gpio11"),
144 PINCTRL_PIN(12, "gpio12"),
145 PINCTRL_PIN(13, "gpio13"),
146 PINCTRL_PIN(14, "gpio14"),
147 PINCTRL_PIN(15, "gpio15"),
148 PINCTRL_PIN(16, "oscio"),
151 static const struct sx150x_device_data sx1508q_device_data = {
157 .reg_irq_mask = 0x09,
162 .reg_polarity = 0x06,
168 .pins = sx150x_8_pins,
169 .npins = ARRAY_SIZE(sx150x_8_pins),
172 static const struct sx150x_device_data sx1509q_device_data = {
178 .reg_irq_mask = 0x12,
183 .reg_polarity = 0x0c,
189 .pins = sx150x_16_pins,
190 .npins = ARRAY_SIZE(sx150x_16_pins),
193 static const struct sx150x_device_data sx1506q_device_data = {
199 .reg_irq_mask = 0x08,
203 .reg_pld_mode = 0x20,
204 .reg_pld_table0 = 0x22,
205 .reg_pld_table1 = 0x24,
206 .reg_pld_table2 = 0x26,
207 .reg_pld_table3 = 0x28,
208 .reg_pld_table4 = 0x2a,
212 .pins = sx150x_16_pins,
213 .npins = 16, /* oscio not available */
216 static const struct sx150x_device_data sx1502q_device_data = {
222 .reg_irq_mask = 0x05,
226 .reg_pld_mode = 0x10,
227 .reg_pld_table0 = 0x11,
228 .reg_pld_table1 = 0x12,
229 .reg_pld_table2 = 0x13,
230 .reg_pld_table3 = 0x14,
231 .reg_pld_table4 = 0x15,
235 .pins = sx150x_8_pins,
236 .npins = 8, /* oscio not available */
239 static const struct sx150x_device_data sx1503q_device_data = {
245 .reg_irq_mask = 0x08,
249 .reg_pld_mode = 0x20,
250 .reg_pld_table0 = 0x22,
251 .reg_pld_table1 = 0x24,
252 .reg_pld_table2 = 0x26,
253 .reg_pld_table3 = 0x28,
254 .reg_pld_table4 = 0x2a,
258 .pins = sx150x_16_pins,
259 .npins = 16, /* oscio not available */
262 static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
267 static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
273 static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
275 const unsigned int **pins,
276 unsigned int *num_pins)
281 static const struct pinctrl_ops sx150x_pinctrl_ops = {
282 .get_groups_count = sx150x_pinctrl_get_groups_count,
283 .get_group_name = sx150x_pinctrl_get_group_name,
284 .get_group_pins = sx150x_pinctrl_get_group_pins,
286 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
287 .dt_free_map = pinctrl_utils_free_map,
291 static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin)
293 if (pin >= pctl->data->npins)
296 /* OSCIO pin is only present in 789 devices */
297 if (pctl->data->model != SX150X_789)
300 return !strcmp(pctl->data->pins[pin].name, "oscio");
303 static int sx150x_gpio_get_direction(struct gpio_chip *chip,
306 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
310 if (sx150x_pin_is_oscio(pctl, offset))
313 ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
317 return !!(value & BIT(offset));
320 static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
322 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
326 if (sx150x_pin_is_oscio(pctl, offset))
329 ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
333 return !!(value & BIT(offset));
336 static int sx150x_gpio_set_single_ended(struct gpio_chip *chip,
338 enum single_ended_mode mode)
340 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
344 case LINE_MODE_PUSH_PULL:
345 if (pctl->data->model != SX150X_789 ||
346 sx150x_pin_is_oscio(pctl, offset))
349 ret = regmap_write_bits(pctl->regmap,
350 pctl->data->pri.x789.reg_drain,
354 case LINE_MODE_OPEN_DRAIN:
355 if (pctl->data->model != SX150X_789 ||
356 sx150x_pin_is_oscio(pctl, offset))
359 ret = regmap_write_bits(pctl->regmap,
360 pctl->data->pri.x789.reg_drain,
361 BIT(offset), BIT(offset));
371 static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset,
374 return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
375 BIT(offset), value ? BIT(offset) : 0);
378 static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl,
381 return regmap_write(pctl->regmap,
382 pctl->data->pri.x789.reg_clock,
383 (value ? 0x1f : 0x10));
386 static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
389 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
391 if (sx150x_pin_is_oscio(pctl, offset))
392 sx150x_gpio_oscio_set(pctl, value);
394 __sx150x_gpio_set(pctl, offset, value);
398 static int sx150x_gpio_direction_input(struct gpio_chip *chip,
401 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
403 if (sx150x_pin_is_oscio(pctl, offset))
406 return regmap_write_bits(pctl->regmap,
408 BIT(offset), BIT(offset));
411 static int sx150x_gpio_direction_output(struct gpio_chip *chip,
412 unsigned int offset, int value)
414 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
417 if (sx150x_pin_is_oscio(pctl, offset))
418 return sx150x_gpio_oscio_set(pctl, value);
420 ret = __sx150x_gpio_set(pctl, offset, value);
424 return regmap_write_bits(pctl->regmap,
429 static void sx150x_irq_mask(struct irq_data *d)
431 struct sx150x_pinctrl *pctl =
432 gpiochip_get_data(irq_data_get_irq_chip_data(d));
433 unsigned int n = d->hwirq;
435 pctl->irq.masked |= BIT(n);
438 static void sx150x_irq_unmask(struct irq_data *d)
440 struct sx150x_pinctrl *pctl =
441 gpiochip_get_data(irq_data_get_irq_chip_data(d));
442 unsigned int n = d->hwirq;
444 pctl->irq.masked &= ~BIT(n);
447 static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl,
448 unsigned int line, unsigned int sense)
451 * Every interrupt line is represented by two bits shifted
452 * proportionally to the line number
454 const unsigned int n = line * 2;
455 const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING |
456 SX150X_IRQ_TYPE_EDGE_FALLING) << n);
458 pctl->irq.sense &= mask;
459 pctl->irq.sense |= sense << n;
462 static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
464 struct sx150x_pinctrl *pctl =
465 gpiochip_get_data(irq_data_get_irq_chip_data(d));
466 unsigned int n, val = 0;
468 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
473 if (flow_type & IRQ_TYPE_EDGE_RISING)
474 val |= SX150X_IRQ_TYPE_EDGE_RISING;
475 if (flow_type & IRQ_TYPE_EDGE_FALLING)
476 val |= SX150X_IRQ_TYPE_EDGE_FALLING;
478 sx150x_irq_set_sense(pctl, n, val);
482 static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
484 struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id;
485 unsigned long n, status;
489 err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
493 err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
498 for_each_set_bit(n, &status, pctl->data->ngpios)
499 handle_nested_irq(irq_find_mapping(pctl->gpio.irqdomain, n));
504 static void sx150x_irq_bus_lock(struct irq_data *d)
506 struct sx150x_pinctrl *pctl =
507 gpiochip_get_data(irq_data_get_irq_chip_data(d));
509 mutex_lock(&pctl->lock);
512 static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
514 struct sx150x_pinctrl *pctl =
515 gpiochip_get_data(irq_data_get_irq_chip_data(d));
517 regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
518 regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
519 mutex_unlock(&pctl->lock);
522 static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
523 unsigned long *config)
525 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
526 unsigned int param = pinconf_to_config_param(*config);
531 if (sx150x_pin_is_oscio(pctl, pin)) {
533 case PIN_CONFIG_DRIVE_PUSH_PULL:
534 case PIN_CONFIG_OUTPUT:
535 ret = regmap_read(pctl->regmap,
536 pctl->data->pri.x789.reg_clock,
541 if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
542 arg = (data & 0x1f) ? 1 : 0;
544 if ((data & 0x1f) == 0x1f)
546 else if ((data & 0x1f) == 0x10)
561 case PIN_CONFIG_BIAS_PULL_DOWN:
562 ret = regmap_read(pctl->regmap,
563 pctl->data->reg_pulldn,
576 case PIN_CONFIG_BIAS_PULL_UP:
577 ret = regmap_read(pctl->regmap,
578 pctl->data->reg_pullup,
591 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
592 if (pctl->data->model != SX150X_789)
595 ret = regmap_read(pctl->regmap,
596 pctl->data->pri.x789.reg_drain,
609 case PIN_CONFIG_DRIVE_PUSH_PULL:
610 if (pctl->data->model != SX150X_789)
613 ret = regmap_read(pctl->regmap,
614 pctl->data->pri.x789.reg_drain,
628 case PIN_CONFIG_OUTPUT:
629 ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
636 ret = sx150x_gpio_get(&pctl->gpio, pin);
648 *config = pinconf_to_config_packed(param, arg);
653 static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
654 unsigned long *configs, unsigned int num_configs)
656 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
657 enum pin_config_param param;
662 for (i = 0; i < num_configs; i++) {
663 param = pinconf_to_config_param(configs[i]);
664 arg = pinconf_to_config_argument(configs[i]);
666 if (sx150x_pin_is_oscio(pctl, pin)) {
667 if (param == PIN_CONFIG_OUTPUT) {
668 ret = sx150x_gpio_direction_output(&pctl->gpio,
679 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
680 case PIN_CONFIG_BIAS_DISABLE:
681 ret = regmap_write_bits(pctl->regmap,
682 pctl->data->reg_pulldn,
687 ret = regmap_write_bits(pctl->regmap,
688 pctl->data->reg_pullup,
695 case PIN_CONFIG_BIAS_PULL_UP:
696 ret = regmap_write_bits(pctl->regmap,
697 pctl->data->reg_pullup,
704 case PIN_CONFIG_BIAS_PULL_DOWN:
705 ret = regmap_write_bits(pctl->regmap,
706 pctl->data->reg_pulldn,
713 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
714 ret = sx150x_gpio_set_single_ended(&pctl->gpio,
715 pin, LINE_MODE_OPEN_DRAIN);
721 case PIN_CONFIG_DRIVE_PUSH_PULL:
722 ret = sx150x_gpio_set_single_ended(&pctl->gpio,
723 pin, LINE_MODE_PUSH_PULL);
729 case PIN_CONFIG_OUTPUT:
730 ret = sx150x_gpio_direction_output(&pctl->gpio,
740 } /* for each config */
745 static const struct pinconf_ops sx150x_pinconf_ops = {
746 .pin_config_get = sx150x_pinconf_get,
747 .pin_config_set = sx150x_pinconf_set,
751 static const struct i2c_device_id sx150x_id[] = {
752 {"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
753 {"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
754 {"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
755 {"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
756 {"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
760 static const struct of_device_id sx150x_of_match[] = {
761 { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
762 { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
763 { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
764 { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
765 { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
769 static int sx150x_reset(struct sx150x_pinctrl *pctl)
773 err = i2c_smbus_write_byte_data(pctl->client,
774 pctl->data->pri.x789.reg_reset,
775 SX150X_789_RESET_KEY1);
779 err = i2c_smbus_write_byte_data(pctl->client,
780 pctl->data->pri.x789.reg_reset,
781 SX150X_789_RESET_KEY2);
785 static int sx150x_init_misc(struct sx150x_pinctrl *pctl)
789 switch (pctl->data->model) {
791 reg = pctl->data->pri.x789.reg_misc;
792 value = SX150X_789_REG_MISC_AUTOCLEAR_OFF;
795 reg = pctl->data->pri.x456.reg_advance;
799 * Only SX1506 has RegAdvanced, SX1504/5 are expected
800 * to initialize this offset to zero
806 reg = pctl->data->pri.x123.reg_advance;
810 WARN(1, "Unknown chip model %d\n", pctl->data->model);
814 return regmap_write(pctl->regmap, reg, value);
817 static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
820 [SX150X_789] = pctl->data->pri.x789.reg_polarity,
821 [SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
822 [SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
826 if (pctl->data->model == SX150X_789 &&
827 of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) {
828 err = sx150x_reset(pctl);
833 err = sx150x_init_misc(pctl);
837 /* Set all pins to work in normal mode */
838 return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
841 static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl,
844 const struct sx150x_device_data *data = pctl->data;
846 if (reg == data->reg_sense) {
848 * RegSense packs two bits of configuration per GPIO,
849 * so we'd need to read twice as many bits as there
850 * are GPIO in our chip
852 return 2 * data->ngpios;
853 } else if ((data->model == SX150X_789 &&
854 (reg == data->pri.x789.reg_misc ||
855 reg == data->pri.x789.reg_clock ||
856 reg == data->pri.x789.reg_reset))
858 (data->model == SX150X_123 &&
859 reg == data->pri.x123.reg_advance)
861 (data->model == SX150X_456 &&
862 reg == data->pri.x456.reg_advance)) {
869 static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
870 unsigned int reg, unsigned int val)
873 const struct sx150x_device_data *data = pctl->data;
876 * Whereas SX1509 presents RegSense in a simple layout as such:
877 * reg [ f f e e d d c c ]
878 * reg + 1 [ b b a a 9 9 8 8 ]
879 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
880 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
882 * SX1503 and SX1506 deviate from that data layout, instead storing
883 * their contents as follows:
885 * reg [ f f e e d d c c ]
886 * reg + 1 [ 7 7 6 6 5 5 4 4 ]
887 * reg + 2 [ b b a a 9 9 8 8 ]
888 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
890 * so, taking that into account, we swap two
891 * inner bytes of a 4-byte result
894 if (reg == data->reg_sense &&
895 data->ngpios == 16 &&
896 (data->model == SX150X_123 ||
897 data->model == SX150X_456)) {
898 a = val & 0x00ff0000;
899 b = val & 0x0000ff00;
910 * In order to mask the differences between 16 and 8 bit expander
911 * devices we set up a sligthly ficticious regmap that pretends to be
912 * a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh
913 * pair/quartet) registers and transparently reconstructs those
914 * registers via multiple I2C/SMBus reads
916 * This way the rest of the driver code, interfacing with the chip via
917 * regmap API, can work assuming that each GPIO pin is represented by
918 * a group of bits at an offset proportional to GPIO number within a
921 static int sx150x_regmap_reg_read(void *context, unsigned int reg,
922 unsigned int *result)
925 struct sx150x_pinctrl *pctl = context;
926 struct i2c_client *i2c = pctl->client;
927 const int width = sx150x_regmap_reg_width(pctl, reg);
928 unsigned int idx, val;
931 * There are four potential cases covered by this function:
933 * 1) 8-pin chip, single configuration bit register
935 * This is trivial the code below just needs to read:
936 * reg [ 7 6 5 4 3 2 1 0 ]
938 * 2) 8-pin chip, double configuration bit register (RegSense)
940 * The read will be done as follows:
941 * reg [ 7 7 6 6 5 5 4 4 ]
942 * reg + 1 [ 3 3 2 2 1 1 0 0 ]
944 * 3) 16-pin chip, single configuration bit register
946 * The read will be done as follows:
947 * reg [ f e d c b a 9 8 ]
948 * reg + 1 [ 7 6 5 4 3 2 1 0 ]
950 * 4) 16-pin chip, double configuration bit register (RegSense)
952 * The read will be done as follows:
953 * reg [ f f e e d d c c ]
954 * reg + 1 [ b b a a 9 9 8 8 ]
955 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
956 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
959 for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
962 ret = i2c_smbus_read_byte_data(i2c, idx);
969 *result = sx150x_maybe_swizzle(pctl, reg, val);
974 static int sx150x_regmap_reg_write(void *context, unsigned int reg,
978 struct sx150x_pinctrl *pctl = context;
979 struct i2c_client *i2c = pctl->client;
980 const int width = sx150x_regmap_reg_width(pctl, reg);
982 val = sx150x_maybe_swizzle(pctl, reg, val);
986 const u8 byte = (val >> n) & 0xff;
988 ret = i2c_smbus_write_byte_data(i2c, reg, byte);
999 static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
1001 struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev));
1003 return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
1006 const struct regmap_config sx150x_regmap_config = {
1010 .cache_type = REGCACHE_RBTREE,
1012 .reg_read = sx150x_regmap_reg_read,
1013 .reg_write = sx150x_regmap_reg_write,
1015 .max_register = SX150X_MAX_REGISTER,
1016 .volatile_reg = sx150x_reg_volatile,
1019 static int sx150x_probe(struct i2c_client *client,
1020 const struct i2c_device_id *id)
1022 static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
1023 I2C_FUNC_SMBUS_WRITE_WORD_DATA;
1024 struct device *dev = &client->dev;
1025 struct sx150x_pinctrl *pctl;
1028 if (!i2c_check_functionality(client->adapter, i2c_funcs))
1031 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1035 i2c_set_clientdata(client, pctl);
1038 pctl->client = client;
1041 pctl->data = of_device_get_match_data(dev);
1043 pctl->data = (struct sx150x_device_data *)id->driver_data;
1048 pctl->regmap = devm_regmap_init(dev, NULL, pctl,
1049 &sx150x_regmap_config);
1050 if (IS_ERR(pctl->regmap)) {
1051 ret = PTR_ERR(pctl->regmap);
1052 dev_err(dev, "Failed to allocate register map: %d\n",
1057 mutex_init(&pctl->lock);
1059 ret = sx150x_init_hw(pctl);
1063 /* Register GPIO controller */
1064 pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
1065 pctl->gpio.base = -1;
1066 pctl->gpio.ngpio = pctl->data->npins;
1067 pctl->gpio.get_direction = sx150x_gpio_get_direction;
1068 pctl->gpio.direction_input = sx150x_gpio_direction_input;
1069 pctl->gpio.direction_output = sx150x_gpio_direction_output;
1070 pctl->gpio.get = sx150x_gpio_get;
1071 pctl->gpio.set = sx150x_gpio_set;
1072 pctl->gpio.set_single_ended = sx150x_gpio_set_single_ended;
1073 pctl->gpio.parent = dev;
1074 #ifdef CONFIG_OF_GPIO
1075 pctl->gpio.of_node = dev->of_node;
1077 pctl->gpio.can_sleep = true;
1079 ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
1083 /* Add Interrupt support if an irq is specified */
1084 if (client->irq > 0) {
1085 pctl->irq_chip.name = devm_kstrdup(dev, client->name,
1087 pctl->irq_chip.irq_mask = sx150x_irq_mask;
1088 pctl->irq_chip.irq_unmask = sx150x_irq_unmask;
1089 pctl->irq_chip.irq_set_type = sx150x_irq_set_type;
1090 pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
1091 pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
1093 pctl->irq.masked = ~0;
1094 pctl->irq.sense = 0;
1097 * Because sx150x_irq_threaded_fn invokes all of the
1098 * nested interrrupt handlers via handle_nested_irq,
1099 * any "handler" passed to gpiochip_irqchip_add()
1100 * below is going to be ignored, so the choice of the
1101 * function does not matter that much.
1103 * We set it to handle_bad_irq to avoid confusion,
1104 * plus it will be instantly noticeable if it is ever
1105 * called (should not happen)
1107 ret = gpiochip_irqchip_add(&pctl->gpio,
1109 handle_bad_irq, IRQ_TYPE_NONE);
1111 dev_err(dev, "could not connect irqchip to gpiochip\n");
1115 ret = devm_request_threaded_irq(dev, client->irq, NULL,
1116 sx150x_irq_thread_fn,
1117 IRQF_ONESHOT | IRQF_SHARED |
1118 IRQF_TRIGGER_FALLING,
1119 pctl->irq_chip.name, pctl);
1125 pctl->pinctrl_desc.name = "sx150x-pinctrl";
1126 pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
1127 pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
1128 pctl->pinctrl_desc.pins = pctl->data->pins;
1129 pctl->pinctrl_desc.npins = pctl->data->npins;
1130 pctl->pinctrl_desc.owner = THIS_MODULE;
1132 pctl->pctldev = pinctrl_register(&pctl->pinctrl_desc, dev, pctl);
1133 if (IS_ERR(pctl->pctldev)) {
1134 dev_err(dev, "Failed to register pinctrl device\n");
1135 return PTR_ERR(pctl->pctldev);
1141 static struct i2c_driver sx150x_driver = {
1143 .name = "sx150x-pinctrl",
1144 .of_match_table = of_match_ptr(sx150x_of_match),
1146 .probe = sx150x_probe,
1147 .id_table = sx150x_id,
1150 static int __init sx150x_init(void)
1152 return i2c_add_driver(&sx150x_driver);
1154 subsys_initcall(sx150x_init);