2 * Qualcomm Peripheral Image Loader
4 * Copyright (C) 2016 Linaro Ltd.
5 * Copyright (C) 2014 Sony Mobile Communications AB
6 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/module.h>
26 #include <linux/of_address.h>
27 #include <linux/platform_device.h>
28 #include <linux/regmap.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/remoteproc.h>
31 #include <linux/reset.h>
32 #include <linux/soc/qcom/smem.h>
33 #include <linux/soc/qcom/smem_state.h>
35 #include "remoteproc_internal.h"
36 #include "qcom_mdt_loader.h"
38 #include <linux/qcom_scm.h>
40 #define MBA_FIRMWARE_NAME "mba.b00"
41 #define MPSS_FIRMWARE_NAME "modem.mdt"
43 #define MPSS_CRASH_REASON_SMEM 421
45 /* RMB Status Register Values */
46 #define RMB_PBL_SUCCESS 0x1
48 #define RMB_MBA_XPU_UNLOCKED 0x1
49 #define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2
50 #define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3
51 #define RMB_MBA_AUTH_COMPLETE 0x4
53 /* PBL/MBA interface registers */
54 #define RMB_MBA_IMAGE_REG 0x00
55 #define RMB_PBL_STATUS_REG 0x04
56 #define RMB_MBA_COMMAND_REG 0x08
57 #define RMB_MBA_STATUS_REG 0x0C
58 #define RMB_PMI_META_DATA_REG 0x10
59 #define RMB_PMI_CODE_START_REG 0x14
60 #define RMB_PMI_CODE_LENGTH_REG 0x18
62 #define RMB_CMD_META_DATA_READY 0x1
63 #define RMB_CMD_LOAD_READY 0x2
65 /* QDSP6SS Register Offsets */
66 #define QDSP6SS_RESET_REG 0x014
67 #define QDSP6SS_GFMUX_CTL_REG 0x020
68 #define QDSP6SS_PWR_CTL_REG 0x030
70 /* AXI Halt Register Offsets */
71 #define AXI_HALTREQ_REG 0x0
72 #define AXI_HALTACK_REG 0x4
73 #define AXI_IDLE_REG 0x8
75 #define HALT_ACK_TIMEOUT_MS 100
78 #define Q6SS_STOP_CORE BIT(0)
79 #define Q6SS_CORE_ARES BIT(1)
80 #define Q6SS_BUS_ARES_ENABLE BIT(2)
82 /* QDSP6SS_GFMUX_CTL */
83 #define Q6SS_CLK_ENABLE BIT(1)
86 #define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0)
87 #define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1)
88 #define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2)
89 #define Q6SS_L2TAG_SLP_NRET_N BIT(16)
90 #define Q6SS_ETB_SLP_NRET_N BIT(17)
91 #define Q6SS_L2DATA_STBY_N BIT(18)
92 #define Q6SS_SLP_RET_N BIT(19)
93 #define Q6SS_CLAMP_IO BIT(20)
94 #define QDSS_BHS_ON BIT(21)
95 #define QDSS_LDO_BYP BIT(22)
101 void __iomem *reg_base;
102 void __iomem *rmb_base;
104 struct regmap *halt_map;
109 struct reset_control *mss_restart;
111 struct qcom_smem_state *state;
114 struct regulator_bulk_data supply[4];
120 struct completion start_done;
121 struct completion stop_done;
124 phys_addr_t mba_phys;
128 phys_addr_t mpss_phys;
129 phys_addr_t mpss_reloc;
141 static int q6v5_regulator_init(struct q6v5 *qproc)
145 qproc->supply[Q6V5_SUPPLY_CX].supply = "cx";
146 qproc->supply[Q6V5_SUPPLY_MX].supply = "mx";
147 qproc->supply[Q6V5_SUPPLY_MSS].supply = "mss";
148 qproc->supply[Q6V5_SUPPLY_PLL].supply = "pll";
150 ret = devm_regulator_bulk_get(qproc->dev,
151 ARRAY_SIZE(qproc->supply), qproc->supply);
153 dev_err(qproc->dev, "failed to get supplies\n");
157 regulator_set_load(qproc->supply[Q6V5_SUPPLY_CX].consumer, 100000);
158 regulator_set_load(qproc->supply[Q6V5_SUPPLY_MSS].consumer, 100000);
159 regulator_set_load(qproc->supply[Q6V5_SUPPLY_PLL].consumer, 10000);
164 static int q6v5_regulator_enable(struct q6v5 *qproc)
168 /* TODO: Q6V5_SUPPLY_CX is supposed to be set to super-turbo here */
169 ret = regulator_set_voltage(qproc->supply[Q6V5_SUPPLY_MX].consumer,
174 regulator_set_voltage(qproc->supply[Q6V5_SUPPLY_MSS].consumer,
177 return regulator_bulk_enable(ARRAY_SIZE(qproc->supply), qproc->supply);
180 static void q6v5_regulator_disable(struct q6v5 *qproc)
182 regulator_bulk_disable(ARRAY_SIZE(qproc->supply), qproc->supply);
183 regulator_set_voltage(qproc->supply[Q6V5_SUPPLY_CX].consumer, 0, INT_MAX);
184 regulator_set_voltage(qproc->supply[Q6V5_SUPPLY_MX].consumer, 0, INT_MAX);
185 regulator_set_voltage(qproc->supply[Q6V5_SUPPLY_MSS].consumer, 0, 1150000);
188 static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
190 struct q6v5 *qproc = rproc->priv;
192 memcpy(qproc->mba_region, fw->data, fw->size);
197 static const struct rproc_fw_ops q6v5_fw_ops = {
198 .find_rsc_table = qcom_mdt_find_rsc_table,
202 static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
204 unsigned long timeout;
207 timeout = jiffies + msecs_to_jiffies(ms);
209 val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
213 if (time_after(jiffies, timeout))
222 static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
225 unsigned long timeout;
228 timeout = jiffies + msecs_to_jiffies(ms);
230 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
236 else if (status && val == status)
239 if (time_after(jiffies, timeout))
248 static void q6v5proc_reset(struct q6v5 *qproc)
252 /* Assert resets, stop core */
253 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
254 val |= (Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE);
255 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
257 /* Enable power block headswitch, and wait for it to stabilize */
258 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
259 val |= QDSS_BHS_ON | QDSS_LDO_BYP;
260 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
265 * Turn on memories. L2 banks should be done individually
266 * to minimize inrush current.
268 val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
269 val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
270 Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
271 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
272 val |= Q6SS_L2DATA_SLP_NRET_N_2;
273 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
274 val |= Q6SS_L2DATA_SLP_NRET_N_1;
275 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
276 val |= Q6SS_L2DATA_SLP_NRET_N_0;
277 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
279 /* Remove IO clamp */
280 val &= ~Q6SS_CLAMP_IO;
281 writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
283 /* Bring core out of reset */
284 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
285 val &= ~Q6SS_CORE_ARES;
286 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
288 /* Turn on core clock */
289 val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
290 val |= Q6SS_CLK_ENABLE;
291 writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
293 /* Start core execution */
294 val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
295 val &= ~Q6SS_STOP_CORE;
296 writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
299 static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
300 struct regmap *halt_map,
303 unsigned long timeout;
307 /* Check if we're already idle */
308 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
312 /* Assert halt request */
313 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
316 timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
318 ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
319 if (ret || val || time_after(jiffies, timeout))
325 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
327 dev_err(qproc->dev, "port failed halt\n");
329 /* Clear halt request (port will remain halted until reset) */
330 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
333 static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
335 DEFINE_DMA_ATTRS(attrs);
340 dma_set_attr(DMA_ATTR_FORCE_CONTIGUOUS, &attrs);
341 ptr = dma_alloc_attrs(qproc->dev, fw->size, &phys, GFP_KERNEL, &attrs);
343 dev_err(qproc->dev, "failed to allocate mdt buffer\n");
347 memcpy(ptr, fw->data, fw->size);
349 writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
350 writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
352 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
353 if (ret == -ETIMEDOUT)
354 dev_err(qproc->dev, "MBA header authentication timed out\n");
356 dev_err(qproc->dev, "MBA returned error %d for MDT header\n", ret);
358 dma_free_attrs(qproc->dev, fw->size, ptr, phys, &attrs);
360 return ret < 0 ? ret : 0;
363 static int q6v5_mpss_validate(struct q6v5 *qproc, const struct firmware *fw)
365 const struct elf32_phdr *phdrs;
366 const struct elf32_phdr *phdr;
367 struct elf32_hdr *ehdr;
368 phys_addr_t boot_addr;
376 ret = qcom_mdt_parse(fw, &fw_addr, NULL, &relocate);
378 dev_err(qproc->dev, "failed to parse mdt header\n");
383 boot_addr = qproc->mpss_phys;
387 ehdr = (struct elf32_hdr *)fw->data;
388 phdrs = (struct elf32_phdr *)(ehdr + 1);
389 for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
392 if (phdr->p_type != PT_LOAD)
395 if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
401 size = readl(qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
403 writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
404 writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
407 size += phdr->p_memsz;
408 writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
411 val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
412 return val < 0 ? val : 0;
415 static int q6v5_mpss_load(struct q6v5 *qproc)
417 const struct firmware *fw;
422 ret = request_firmware(&fw, MPSS_FIRMWARE_NAME, qproc->dev);
424 dev_err(qproc->dev, "unable to load " MPSS_FIRMWARE_NAME "\n");
428 ret = qcom_mdt_parse(fw, &fw_addr, NULL, &relocate);
430 dev_err(qproc->dev, "failed to parse mdt header\n");
431 goto release_firmware;
435 qproc->mpss_reloc = fw_addr;
437 /* Initialize the RMB validator */
438 writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
440 ret = q6v5_mpss_init_image(qproc, fw);
442 goto release_firmware;
444 ret = qcom_mdt_load(qproc->rproc, fw, MPSS_FIRMWARE_NAME);
446 goto release_firmware;
448 ret = q6v5_mpss_validate(qproc, fw);
450 goto release_firmware;
452 ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
453 if (ret == -ETIMEDOUT)
454 dev_err(qproc->dev, "MBA authentication timed out\n");
456 dev_err(qproc->dev, "MBA returned error %d\n", ret);
459 release_firmware(fw);
461 return ret < 0 ? ret : 0;
464 static int q6v5_start(struct rproc *rproc)
466 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
469 ret = q6v5_regulator_enable(qproc);
471 dev_err(qproc->dev, "failed to enable supplies\n");
475 ret = reset_control_deassert(qproc->mss_restart);
477 dev_err(qproc->dev, "failed to deassert mss restart\n");
481 ret = clk_prepare_enable(qproc->ahb_clk);
485 ret = clk_prepare_enable(qproc->axi_clk);
487 goto disable_ahb_clk;
489 ret = clk_prepare_enable(qproc->rom_clk);
491 goto disable_axi_clk;
493 writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
495 q6v5proc_reset(qproc);
497 ret = q6v5_rmb_pbl_wait(qproc, 1000);
498 if (ret == -ETIMEDOUT) {
499 dev_err(qproc->dev, "PBL boot timed out\n");
501 } else if (ret != RMB_PBL_SUCCESS) {
502 dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
507 ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
508 if (ret == -ETIMEDOUT) {
509 dev_err(qproc->dev, "MBA boot timed out\n");
511 } else if (ret != RMB_MBA_XPU_UNLOCKED && ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
512 dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
517 dev_info(qproc->dev, "MBA booted, loading mpss\n");
519 ret = q6v5_mpss_load(qproc);
523 ret = wait_for_completion_timeout(&qproc->start_done,
524 msecs_to_jiffies(5000));
526 dev_err(qproc->dev, "start timed out\n");
531 qproc->running = true;
533 /* All done, release the handover resources */
538 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
539 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
540 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
542 clk_disable_unprepare(qproc->axi_clk);
544 clk_disable_unprepare(qproc->ahb_clk);
546 reset_control_assert(qproc->mss_restart);
548 q6v5_regulator_disable(qproc);
553 static int q6v5_stop(struct rproc *rproc)
555 struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
558 qproc->running = false;
560 qcom_smem_state_update_bits(qproc->state,
561 BIT(qproc->stop_bit), BIT(qproc->stop_bit));
563 ret = wait_for_completion_timeout(&qproc->stop_done,
564 msecs_to_jiffies(5000));
566 dev_err(qproc->dev, "timed out on wait\n");
568 qcom_smem_state_update_bits(qproc->state, BIT(qproc->stop_bit), 0);
570 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
571 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
572 q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
574 reset_control_assert(qproc->mss_restart);
575 clk_disable_unprepare(qproc->axi_clk);
576 clk_disable_unprepare(qproc->ahb_clk);
577 q6v5_regulator_disable(qproc);
582 static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
584 struct q6v5 *qproc = rproc->priv;
587 offset = da - qproc->mpss_reloc;
588 if (offset < 0 || offset + len > qproc->mpss_size)
591 return qproc->mpss_region + offset;
594 static const struct rproc_ops q6v5_ops = {
597 .da_to_va = q6v5_da_to_va,
600 static irqreturn_t q6v5_wdog_interrupt(int irq, void *dev)
602 struct q6v5 *qproc = dev;
606 /* Sometimes the stop triggers a watchdog rather than a stop-ack */
607 if (!qproc->running) {
608 complete(&qproc->stop_done);
612 msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len);
613 if (!IS_ERR(msg) && len > 0 && msg[0])
614 dev_err(qproc->dev, "watchdog received: %s\n", msg);
616 dev_err(qproc->dev, "watchdog without message\n");
618 rproc_report_crash(qproc->rproc, RPROC_WATCHDOG);
626 static irqreturn_t q6v5_fatal_interrupt(int irq, void *dev)
628 struct q6v5 *qproc = dev;
632 msg = qcom_smem_get(QCOM_SMEM_HOST_ANY, MPSS_CRASH_REASON_SMEM, &len);
633 if (!IS_ERR(msg) && len > 0 && msg[0])
634 dev_err(qproc->dev, "fatal error received: %s\n", msg);
636 dev_err(qproc->dev, "fatal error without message\n");
638 rproc_report_crash(qproc->rproc, RPROC_FATAL_ERROR);
646 static irqreturn_t q6v5_handover_interrupt(int irq, void *dev)
648 struct q6v5 *qproc = dev;
650 complete(&qproc->start_done);
654 static irqreturn_t q6v5_stop_ack_interrupt(int irq, void *dev)
656 struct q6v5 *qproc = dev;
658 complete(&qproc->stop_done);
662 static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
664 struct device_node *halt_np;
665 struct resource *res;
668 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
669 qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
670 if (IS_ERR(qproc->reg_base)) {
671 dev_err(qproc->dev, "failed to get qdsp6_base\n");
672 return PTR_ERR(qproc->reg_base);
675 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
676 qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
677 if (IS_ERR(qproc->rmb_base)) {
678 dev_err(qproc->dev, "failed to get rmb_base\n");
679 return PTR_ERR(qproc->rmb_base);
682 halt_np = of_parse_phandle(pdev->dev.of_node, "qcom,halt-regs", 0);
684 dev_err(&pdev->dev, "no qcom,halt-regs node\n");
688 qproc->halt_map = syscon_node_to_regmap(halt_np);
689 if (IS_ERR(qproc->halt_map))
690 return PTR_ERR(qproc->halt_map);
692 ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs",
695 dev_err(&pdev->dev, "no q6 halt offset\n");
699 ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs",
700 2, &qproc->halt_modem);
702 dev_err(&pdev->dev, "no modem halt offset\n");
706 ret = of_property_read_u32_index(pdev->dev.of_node, "qcom,halt-regs",
709 dev_err(&pdev->dev, "no nc halt offset\n");
716 static int q6v5_init_clocks(struct q6v5 *qproc)
718 qproc->ahb_clk = devm_clk_get(qproc->dev, "iface");
719 if (IS_ERR(qproc->ahb_clk)) {
720 dev_err(qproc->dev, "failed to get iface clock\n");
721 return PTR_ERR(qproc->ahb_clk);
724 qproc->axi_clk = devm_clk_get(qproc->dev, "bus");
725 if (IS_ERR(qproc->axi_clk)) {
726 dev_err(qproc->dev, "failed to get bus clock\n");
727 return PTR_ERR(qproc->axi_clk);
730 qproc->rom_clk = devm_clk_get(qproc->dev, "mem");
731 if (IS_ERR(qproc->rom_clk)) {
732 dev_err(qproc->dev, "failed to get mem clock\n");
733 return PTR_ERR(qproc->rom_clk);
739 static int q6v5_init_reset(struct q6v5 *qproc)
741 qproc->mss_restart = devm_reset_control_get(qproc->dev, NULL);
742 if (IS_ERR(qproc->mss_restart)) {
743 dev_err(qproc->dev, "failed to acquire mss restart\n");
744 return PTR_ERR(qproc->mss_restart);
750 static int q6v5_request_irq(struct q6v5 *qproc,
751 struct platform_device *pdev,
753 irq_handler_t thread_fn)
757 ret = platform_get_irq_byname(pdev, name);
759 dev_err(&pdev->dev, "no %s IRQ defined\n", name);
763 ret = devm_request_threaded_irq(&pdev->dev, ret,
765 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
768 dev_err(&pdev->dev, "request %s IRQ failed\n", name);
772 static int q6v5_alloc_memory_region(struct q6v5 *qproc)
774 struct device_node *child;
775 struct device_node *node;
779 child = of_get_child_by_name(qproc->dev->of_node, "mba");
780 node = of_parse_phandle(child, "memory-region", 0);
781 ret = of_address_to_resource(node, 0, &r);
783 dev_err(qproc->dev, "unable to resolve mba region\n");
787 qproc->mba_phys = r.start;
788 qproc->mba_size = resource_size(&r);
789 qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
790 if (!qproc->mba_region) {
791 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
792 &r.start, qproc->mba_size);
796 child = of_get_child_by_name(qproc->dev->of_node, "mpss");
797 node = of_parse_phandle(child, "memory-region", 0);
798 ret = of_address_to_resource(node, 0, &r);
800 dev_err(qproc->dev, "unable to resolve mpss region\n");
804 qproc->mpss_phys = qproc->mpss_reloc = r.start;
805 qproc->mpss_size = resource_size(&r);
806 qproc->mpss_region = devm_ioremap_wc(qproc->dev, qproc->mpss_phys, qproc->mpss_size);
807 if (!qproc->mpss_region) {
808 dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
809 &r.start, qproc->mpss_size);
816 static int q6v5_probe(struct platform_device *pdev)
822 rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
823 MBA_FIRMWARE_NAME, sizeof(*qproc));
825 dev_err(&pdev->dev, "failed to allocate rproc\n");
829 rproc->fw_ops = &q6v5_fw_ops;
831 qproc = (struct q6v5 *)rproc->priv;
832 qproc->dev = &pdev->dev;
833 qproc->rproc = rproc;
834 platform_set_drvdata(pdev, qproc);
836 init_completion(&qproc->start_done);
837 init_completion(&qproc->stop_done);
839 ret = q6v5_init_mem(qproc, pdev);
843 ret = q6v5_alloc_memory_region(qproc);
847 ret = q6v5_init_clocks(qproc);
851 ret = q6v5_regulator_init(qproc);
855 ret = q6v5_init_reset(qproc);
859 ret = q6v5_request_irq(qproc, pdev, "wdog", q6v5_wdog_interrupt);
863 ret = q6v5_request_irq(qproc, pdev, "fatal", q6v5_fatal_interrupt);
867 ret = q6v5_request_irq(qproc, pdev, "handover", q6v5_handover_interrupt);
871 ret = q6v5_request_irq(qproc, pdev, "stop-ack", q6v5_stop_ack_interrupt);
875 qproc->state = qcom_smem_state_get(&pdev->dev, "stop", &qproc->stop_bit);
876 if (IS_ERR(qproc->state))
879 ret = rproc_add(rproc);
891 static int q6v5_remove(struct platform_device *pdev)
893 struct q6v5 *qproc = platform_get_drvdata(pdev);
895 rproc_del(qproc->rproc);
896 rproc_put(qproc->rproc);
901 static const struct of_device_id q6v5_of_match[] = {
902 { .compatible = "qcom,q6v5-pil", },
906 static struct platform_driver q6v5_driver = {
908 .remove = q6v5_remove,
910 .name = "qcom-q6v5-pil",
911 .of_match_table = q6v5_of_match,
915 module_platform_driver(q6v5_driver);